From 985cf3fb6bb496ea20dd2141d1c3e3eeb6afa0dc Mon Sep 17 00:00:00 2001 From: wifi-ci-agent Date: Mon, 21 Oct 2024 17:10:46 +0000 Subject: [PATCH] WiSeConnect 3 SDK release: v3.3.4 --- .../si91x/mcu/drivers/cmsis_driver/CAN.c | 982 ++++ .../si91x/mcu/drivers/cmsis_driver/CAN.h | 136 + .../CMSIS/Driver/Include/Driver_CAN.h | 232 + .../CMSIS/Driver/Include/Driver_ETH.h | 85 + .../CMSIS/Driver/Include/Driver_ETH_MAC.h | 301 ++ .../CMSIS/Driver/Include/Driver_ETH_PHY.h | 133 + .../CMSIS/Driver/Include/Driver_MCI.h | 350 ++ .../CMSIS/Driver/Include/Driver_NAND.h | 403 ++ .../CMSIS/Driver/Include/Driver_USB.h | 95 + .../CMSIS/Driver/Include/Driver_USBD.h | 263 + .../CMSIS/Driver/Include/Driver_USBH.h | 406 ++ .../Driver/component/cmsis_can_driver.slcc | 16 + .../Driver/component/cmsis_eth_driver.slcc | 16 + .../component/cmsis_eth_mac_driver.slcc | 16 + .../component/cmsis_eth_phy_driver.slcc | 16 + .../Driver/component/cmsis_mci_driver.slcc | 16 + .../Driver/component/cmsis_nand_driver.slcc | 16 + .../Driver/component/cmsis_usb_driver.slcc | 16 + .../Driver/component/cmsis_usbd_driver.slcc | 16 + .../Driver/component/cmsis_usbh_driver.slcc | 16 + .../si91x/mcu/drivers/cmsis_driver/EMAC.c | 1069 +++++ .../si91x/mcu/drivers/cmsis_driver/EMAC.h | 445 ++ .../si91x/mcu/drivers/cmsis_driver/MCI.c | 1118 +++++ .../si91x/mcu/drivers/cmsis_driver/MCI.h | 195 + .../mcu/drivers/cmsis_driver/PHY_LAN8742A.c | 292 ++ .../mcu/drivers/cmsis_driver/PHY_LAN8742A.h | 91 + .../si91x/mcu/drivers/cmsis_driver/USB.c | 80 + .../si91x/mcu/drivers/cmsis_driver/USB.h | 210 + .../si91x/mcu/drivers/cmsis_driver/USBD.c | 886 ++++ .../si91x/mcu/drivers/cmsis_driver/USBH.c | 244 + .../cmsis_driver/component/cmsis_can.slcc | 18 + .../cmsis_driver/component/cmsis_emac.slcc | 18 + .../cmsis_driver/component/cmsis_mci.slcc | 18 + .../cmsis_driver/component/cmsis_phy_lan.slcc | 18 + .../cmsis_driver/component/cmsis_usb.slcc | 18 + .../cmsis_driver/component/cmsis_usbd.slcc | 14 + .../cmsis_driver/component/cmsis_usbh.slcc | 14 + .../component/rsilib_cci.slcc | 18 + .../component/rsilib_fim.slcc | 18 + .../component/rsilib_ir.slcc | 18 + .../component/rsilib_sdioh.slcc | 18 + .../component/rsilib_sdmem.slcc | 18 + .../component/rsilib_smih.slcc | 18 + .../component/rsilib_vad.slcc | 18 + .../component/rsilib_wurx.slcc | 18 + .../drivers/peripheral_drivers/inc/rsi_cci.h | 104 + .../drivers/peripheral_drivers/inc/rsi_fim.h | 725 +++ .../drivers/peripheral_drivers/inc/rsi_ir.h | 227 + .../peripheral_drivers/inc/rsi_sdioh.h | 205 + .../peripheral_drivers/inc/rsi_sdmem.h | 219 + .../drivers/peripheral_drivers/inc/rsi_smih.h | 486 ++ .../drivers/peripheral_drivers/inc/rsi_vad.h | 164 + .../drivers/peripheral_drivers/inc/rsi_wurx.h | 143 + .../drivers/peripheral_drivers/src/rsi_cci.c | 174 + .../drivers/peripheral_drivers/src/rsi_fim.c | 4223 +++++++++++++++++ .../drivers/peripheral_drivers/src/rsi_ir.c | 59 + .../peripheral_drivers/src/rsi_sdioh.c | 798 ++++ .../peripheral_drivers/src/rsi_sdmem.c | 1242 +++++ .../drivers/peripheral_drivers/src/rsi_smih.c | 1184 +++++ .../drivers/peripheral_drivers/src/rsi_vad.c | 516 ++ .../drivers/peripheral_drivers/src/rsi_wurx.c | 716 +++ demos/brd2605a/out_of_box_demo.rps | Bin 107220 -> 107220 bytes demos/brd2605a/siwx917_dev_kit.rps | Bin 120244 -> 120244 bytes demos/brd4338a/cli_demo_soc.rps | Bin 132844 -> 132844 bytes demos/brd4338a/out_of_box_demo.rps | Bin 108188 -> 108188 bytes demos/brd4342a/out_of_box_demo.rps | Bin 108380 -> 108380 bytes demos/brd4343a/out_of_box_demo.rps | Bin 108108 -> 108108 bytes docs/release-notes/index_ncp.md | 458 +- docs/release-notes/index_soc.md | 650 +++ .../aws_device_shadow_ncp.slcp | 2 +- .../aws_device_shadow_psram.slcp | 2 +- .../aws_device_shadow_soc.slcp | 2 +- .../aws_device_shadow_uart_ncp.slcp | 2 +- examples/featured/ble_per/ble_per_ncp.slcp | 2 +- examples/featured/ble_per/ble_per_psram.slcp | 2 +- examples/featured/ble_per/ble_per_soc.slcp | 2 +- .../featured/ble_per/ble_per_uart_ncp.slcp | 2 +- .../firmware_update_fg25_ncp.slcp | 2 +- .../firmware_update/firmware_update_ncp.slcp | 2 +- .../firmware_update_psram.slcp | 2 +- .../firmware_update/firmware_update_soc.slcp | 2 +- .../firmware_update_uart_ncp.slcp | 2 +- .../power_save_deep_sleep_ncp.slcp | 2 +- .../power_save_deep_sleep_soc.slcp | 2 +- .../power_save_deep_sleep_uart_ncp.slcp | 2 +- .../powersave_standby_associated_ncp.slcp | 2 +- .../powersave_standby_associated_psram.slcp | 2 +- .../powersave_standby_associated_soc.slcp | 2 +- ...powersave_standby_associated_uart_ncp.slcp | 2 +- ...ave_standby_associated_tcp_client_ncp.slcp | 2 +- ...e_standby_associated_tcp_client_psram.slcp | 2 +- ...ave_standby_associated_tcp_client_soc.slcp | 2 +- ...tandby_associated_tcp_client_uart_ncp.slcp | 2 +- .../twt_tcp_client/twt_tcp_client_ncp.slcp | 2 +- .../twt_tcp_client/twt_tcp_client_soc.slcp | 2 +- .../wlan_throughput/wlan_throughput_ncp.slcp | 2 +- .../wlan_throughput_psram.slcp | 2 +- .../wlan_throughput/wlan_throughput_soc.slcp | 2 +- .../wlan_throughput_uart_ncp.slcp | 2 +- .../sl_si91x_msg_queue.slcp | 2 +- .../sl_si91x_mutex/sl_si91x_mutex.slcp | 2 +- .../crypto/si91x_psa_aes/si91x_psa_aes.slcp | 2 +- .../si91x_psa_asymmetric_key_storage.slcp | 2 +- .../crypto/si91x_psa_ccm/si91x_psa_ccm.slcp | 2 +- .../si91x_psa_chachapoly.slcp | 2 +- .../crypto/si91x_psa_cmac/si91x_psa_cmac.slcp | 2 +- .../crypto/si91x_psa_ecdh/si91x_psa_ecdh.slcp | 2 +- .../si91x_psa_ecdsa/si91x_psa_ecdsa.slcp | 2 +- .../crypto/si91x_psa_gcm/si91x_psa_gcm.slcp | 2 +- .../crypto/si91x_psa_hmac/si91x_psa_hmac.slcp | 2 +- .../si91x_psa_multithread.slcp | 2 +- .../crypto/si91x_psa_sha/si91x_psa_sha.slcp | 2 +- .../si91x_psa_symmetric_key_storage.slcp | 2 +- .../crypto/test/aead/si91x_test_aead.slcp | 2 +- .../crypto/test/cipher/si91x_test_cipher.slcp | 2 +- .../crypto/test/hash/si91x_test_hash.slcp | 2 +- .../crypto/test/mac/si91x_test_mac.slcp | 2 +- .../hello_world/si91x_hello_world.slcp | 2 +- .../memlcd_baremetal/memlcd_baremetal.slcp | 2 +- .../peripheral/psram_blinky/psram_blinky.slcp | 2 +- .../psram_driver_example.slcp | 2 +- .../sl_si91x_adc_fifo_mode.slcp | 2 +- .../sl_si91x_adc_static_mode.slcp | 2 +- .../sl_si91x_analog_comparator.slcp | 2 +- .../sl_si91x_bjt_temperature_sensor.slcp | 2 +- .../sl_si91x_blinky/sl_si91x_blinky.slcp | 2 +- .../sl_si91x_button_baremetal.slcp | 2 +- .../sl_si91x_calendar/sl_si91x_calendar.slcp | 2 +- .../sl_si91x_combo_app.slcp | 2 +- .../sl_si91x_config_timer.slcp | 2 +- .../peripheral/sl_si91x_crc/sl_si91x_crc.slcp | 2 +- .../peripheral/sl_si91x_dac/sl_si91x_dac.slcp | 2 +- .../peripheral/sl_si91x_dma/sl_si91x_dma.slcp | 2 +- .../sl_si91x_efuse/sl_si91x_efuse.slcp | 2 +- .../sl_si91x_gpio/sl_si91x_gpio.slcp | 2 +- .../sl_si91x_gpio_detailed_example.slcp | 2 +- .../sl_si91x_gpio_example.slcp | 2 +- .../sl_si91x_gpio_group_example.slcp | 2 +- .../sl_si91x_gpio_ulp_example.slcp | 2 +- .../sl_si91x_gpio_uulp_example.slcp | 2 +- .../sl_si91x_gspi/sl_si91x_gspi.slcp | 2 +- .../sl_si91x_i2c_driver_follower.slcp | 2 +- .../sl_si91x_i2c_driver_leader.slcp | 2 +- .../sl_si91x_i2s_loopback.slcp | 2 +- .../sl_si91x_i2s_primary.slcp | 2 +- .../sl_si91x_i2s_secondary.slcp | 2 +- .../sl_si91x_icm40627/sl_si91x_icm40627.slcp | 2 +- .../sl_si91x_joystick/sl_si91x_joystick.slcp | 2 +- .../peripheral/sl_si91x_pwm/sl_si91x_pwm.slcp | 2 +- .../sl_si91x_rgb_led/sl_si91x_rgb_led.slcp | 2 +- .../sl_si91x_sdio_secondary.slcp | 2 +- .../sl_si91x_si70xx/sl_si91x_si70xx.slcp | 2 +- .../sl_si91x_ssi_master.slcp | 2 +- .../sl_si91x_ssi_slave.slcp | 2 +- .../sl_si91x_sysrtc/sl_si91x_sysrtc.slcp | 2 +- .../sl_si91x_uart/sl_si91x_uart.slcp | 2 +- .../sl_si91x_ulp_adc/sl_si91x_ulp_adc.slcp | 2 +- .../sl_si91x_ulp_calendar.slcp | 2 +- .../sl_si91x_ulp_dac/sl_si91x_ulp_dac.slcp | 2 +- .../sl_si91x_ulp_dma/sl_si91x_ulp_dma.slcp | 2 +- .../sl_si91x_ulp_gpio/sl_si91x_ulp_gpio.slcp | 2 +- .../sl_si91x_ulp_i2c_driver_leader.slcp | 2 +- .../sl_si91x_ulp_i2s/sl_si91x_ulp_i2s.slcp | 2 +- .../sl_si91x_ulp_ssi_master.slcp | 2 +- .../sl_si91x_ulp_timer.slcp | 2 +- .../sl_si91x_ulp_uart/sl_si91x_ulp_uart.slcp | 2 +- .../sl_si91x_usart_async.slcp | 2 +- .../sl_si91x_usart_sync_master.slcp | 2 +- .../sl_si91x_usart_sync_slave.slcp | 2 +- .../sl_si91x_veml6035/sl_si91x_veml6035.slcp | 2 +- .../sl_si91x_watchdog_timer.slcp | 2 +- .../iostream_usart_baremetal.slcp | 2 +- .../sl_si91x_file_system.slcp | 2 +- .../sl_si91x_nvm3_common_flash.slcp | 2 +- .../sl_si91x_nvm3_dual_flash.slcp | 2 +- .../sl_si91x_power_manager_m4_wireless.slcp | 2 +- .../sl_si91x_power_manager_tickless_idle.slcp | 2 +- .../sl_si91x_sensorhub.slcp | 2 +- .../sl_si91x_sleeptimer.slcp | 2 +- .../siwx917_dev_kit/siwx917_dev_kit.slcp | 2 +- .../ble_accept_list/ble_accept_list_ncp.slcp | 2 +- .../ble_accept_list_psram.slcp | 2 +- .../ble_accept_list/ble_accept_list_soc.slcp | 2 +- .../ble_ae_central/ble_ae_central_ncp.slcp | 2 +- .../ble_ae_central/ble_ae_central_psram.slcp | 2 +- .../ble_ae_central/ble_ae_central_soc.slcp | 2 +- .../ble_ae_central_uart_ncp.slcp | 2 +- .../ble_ae_peripheral_ncp.slcp | 2 +- .../ble_ae_peripheral_psram.slcp | 2 +- .../ble_ae_peripheral_soc.slcp | 2 +- .../ble_ae_peripheral_uart_ncp.slcp | 2 +- .../ble/ble_central/ble_central_ncp.slcp | 2 +- .../ble/ble_central/ble_central_psram.slcp | 2 +- .../ble/ble_central/ble_central_soc.slcp | 2 +- .../ble_datalength/ble_datalength_ncp.slcp | 2 +- .../ble_datalength/ble_datalength_psram.slcp | 2 +- .../ble_datalength/ble_datalength_soc.slcp | 2 +- .../ble_heart_rate_profile_ncp.slcp | 2 +- .../ble_heart_rate_profile_psram.slcp | 2 +- .../ble_heart_rate_profile_soc.slcp | 2 +- .../ble_hid_on_gatt/ble_hid_on_gatt_ncp.slcp | 2 +- .../ble_hid_on_gatt_psram.slcp | 2 +- .../ble_hid_on_gatt/ble_hid_on_gatt_soc.slcp | 2 +- .../ble/ble_ibeacon/ble_ibeacon_ncp.slcp | 2 +- .../ble/ble_ibeacon/ble_ibeacon_psram.slcp | 2 +- .../ble/ble_ibeacon/ble_ibeacon_soc.slcp | 2 +- .../ble_longrange_2mbps_ncp.slcp | 2 +- .../ble_longrange_2mbps_psram.slcp | 2 +- .../ble_longrange_2mbps_soc.slcp | 2 +- .../ble_multiconnection_gatt_test_ncp.slcp | 2 +- .../ble_multiconnection_gatt_test_psram.slcp | 2 +- .../ble_multiconnection_gatt_test_soc.slcp | 2 +- .../ble_power_save/ble_power_save_ncp.slcp | 2 +- .../ble_power_save/ble_power_save_psram.slcp | 2 +- .../ble_power_save/ble_power_save_soc.slcp | 2 +- .../ble_power_save_uart_ncp.slcp | 2 +- .../ble/ble_privacy/ble_privacy_ncp.slcp | 2 +- .../ble/ble_privacy/ble_privacy_psram.slcp | 2 +- .../ble/ble_privacy/ble_privacy_soc.slcp | 2 +- .../ble_secureconnection_ncp.slcp | 2 +- .../ble_secureconnection_psram.slcp | 2 +- .../ble_secureconnection_soc.slcp | 2 +- .../ble/ble_testmodes/ble_testmodes_ncp.slcp | 2 +- .../ble_testmodes/ble_testmodes_psram.slcp | 2 +- .../ble/ble_testmodes/ble_testmodes_soc.slcp | 2 +- .../ble_throughput_app_ncp.slcp | 2 +- .../ble_throughput_app_psram.slcp | 2 +- .../ble_throughput_app_soc.slcp | 2 +- .../ble_throughput_app_uart_ncp.slcp | 2 +- .../ble_unified_ae_coex_app_ncp.slcp | 2 +- .../ble_unified_ae_coex_app_psram.slcp | 2 +- .../ble_unified_ae_coex_app_soc.slcp | 2 +- .../ble_update_gain_table_ncp.slcp | 2 +- .../ble_update_gain_table_psram.slcp | 2 +- .../ble_update_gain_table_soc.slcp | 2 +- .../ble/bt_stack_bypass/bt_stack_bypass.slcp | 2 +- .../gatt_long_read/gatt_long_read_ncp.slcp | 2 +- .../gatt_long_read/gatt_long_read_psram.slcp | 2 +- .../gatt_long_read/gatt_long_read_soc.slcp | 2 +- examples/snippets/cli_demo/cli_demo_ncp.slcp | 2 +- examples/snippets/cli_demo/cli_demo_soc.slcp | 2 +- .../snippets/cli_demo/cli_demo_uart_ncp.slcp | 2 +- examples/snippets/crypto/aes/aes.slcp | 2 +- .../crypto/attestation/attestation.slcp | 2 +- examples/snippets/crypto/ecdh/ecdh.slcp | 2 +- examples/snippets/crypto/ecdsa/ecdsa.slcp | 2 +- .../snippets/crypto/gcm_cmac/gcm_cmac.slcp | 2 +- examples/snippets/crypto/hmac/hmac.slcp | 2 +- examples/snippets/crypto/sha/sha.slcp | 2 +- .../flash_read_write/flash_read_write.slcp | 2 +- .../sl_si91x_empty_c_ncp.slcp | 2 +- .../sl_si91x_empty_c_soc.slcp | 2 +- .../sl_si91x_empty_cpp_ncp.slcp | 2 +- .../sl_si91x_empty_cpp_soc.slcp | 2 +- .../wlan/access_point/access_point_ncp.slcp | 2 +- .../wlan/access_point/access_point_soc.slcp | 2 +- .../access_point/access_point_uart_ncp.slcp | 2 +- .../wlan/ap_throughput/ap_throughput_ncp.slcp | 2 +- .../wlan/ap_throughput/ap_throughput_soc.slcp | 2 +- .../calibration_app/calibration_app_ncp.slcp | 2 +- .../calibration_app/calibration_app_soc.slcp | 2 +- .../calibration_app_uart_ncp.slcp | 2 +- .../cloud_apps/aws/mqtt/aws_mqtt_ncp.slcp | 2 +- .../cloud_apps/aws/mqtt/aws_mqtt_soc.slcp | 2 +- .../wlan/cloud_apps/azure/azure_iot_ncp.slcp | 2 +- .../wlan/cloud_apps/azure/azure_iot_soc.slcp | 2 +- ...rmware_update_from_host_uart_fg25_ncp.slcp | 2 +- .../concurrent_http_server_ncp.slcp | 2 +- .../concurrent_http_server_soc.slcp | 2 +- ...ent_http_server_provisioning_fg25_ncp.slcp | 2 +- ...ncurrent_http_server_provisioning_ncp.slcp | 2 +- ...ncurrent_http_server_provisioning_soc.slcp | 2 +- .../concurrent_mode_fg25_ncp.slcp | 2 +- .../concurrent_mode/concurrent_mode_ncp.slcp | 2 +- .../concurrent_mode/concurrent_mode_soc.slcp | 2 +- .../concurrent_mode_uart_ncp.slcp | 2 +- .../concurrent_mode_dual_ip_fg25_ncp.slcp | 2 +- .../concurrent_mode_dual_ip_ncp.slcp | 2 +- .../concurrent_mode_dual_ip_soc.slcp | 2 +- .../wlan/data_transfer/data_transfer_ncp.slcp | 2 +- .../wlan/data_transfer/data_transfer_soc.slcp | 2 +- .../embedded_mqtt_client_ncp.slcp | 2 +- .../embedded_mqtt_client_soc.slcp | 2 +- .../embedded_mqtt_client_twt_ncp.slcp | 2 +- .../embedded_mqtt_client_twt_soc.slcp | 2 +- .../embedded_mqtt_client_twt_uart_ncp.slcp | 2 +- .../enterprise_client_ncp.slcp | 2 +- .../enterprise_client_soc.slcp | 2 +- .../firmware_flashing_ncp.slcp | 2 +- .../firmware_flashing_soc.slcp | 2 +- .../wlan/http_client/http_client_ncp.slcp | 2 +- .../wlan/http_client/http_client_soc.slcp | 2 +- .../wlan/http_otaf/http_otaf_ncp.slcp | 2 +- .../wlan/http_otaf/http_otaf_soc.slcp | 2 +- .../wlan/http_otaf/http_otaf_uart_ncp.slcp | 2 +- .../wlan/http_otaf_twt/http_otaf_twt_ncp.slcp | 2 +- .../wlan/http_otaf_twt/http_otaf_twt_soc.slcp | 2 +- .../wlan/http_server/http_server_soc.slcp | 2 +- .../lwip_tcp_client/lwip_tcp_client_ncp.slcp | 2 +- .../lwip_tcp_client/lwip_tcp_client_soc.slcp | 2 +- .../lwip_tcp_client_uart_ncp.slcp | 2 +- .../m4_firmware_update.slcp | 2 +- .../multithreading_application_ncp.slcp | 2 +- .../multithreading_application_soc.slcp | 2 +- .../wlan/select_app/select_app_ncp.slcp | 2 +- .../wlan/select_app/select_app_soc.slcp | 2 +- .../wlan/sntp_client/sntp_client_ncp.slcp | 2 +- .../wlan/sntp_client/sntp_client_soc.slcp | 2 +- .../sntp_client/sntp_client_uart_ncp.slcp | 2 +- .../wlan/station_ping/station_ping_ncp.slcp | 2 +- .../wlan/station_ping/station_ping_soc.slcp | 2 +- .../station_ping/station_ping_uart_ncp.slcp | 2 +- .../wlan/station_ping_v6/station_ping_v6.slcp | 2 +- .../tcp_tx_on_periodic_wakeup_ncp.slcp | 2 +- .../tcp_tx_on_periodic_wakeup_soc.slcp | 2 +- .../three_ssl_client_sockets_ncp.slcp | 2 +- .../three_ssl_client_sockets_soc.slcp | 2 +- .../wlan/tls_client/tls_client_ncp.slcp | 2 +- .../wlan/tls_client/tls_client_soc.slcp | 2 +- .../twt_use_case_remote_app_ncp.slcp | 2 +- .../twt_use_case_remote_app_soc.slcp | 2 +- .../user_gain_table/user_gain_table_ncp.slcp | 2 +- .../user_gain_table/user_gain_table_soc.slcp | 2 +- .../user_gain_table_uart_ncp.slcp | 2 +- .../wifi6_twt_use_case_demo_ncp.slcp | 2 +- .../wifi6_twt_use_case_demo_soc.slcp | 2 +- .../wifi6_twt_use_case_demo_uart_ncp.slcp | 2 +- .../wlan/wlan_rf_test/wlan_rf_test_ncp.slcp | 2 +- .../wlan/wlan_rf_test/wlan_rf_test_soc.slcp | 2 +- .../wlan_rf_test/wlan_rf_test_uart_ncp.slcp | 2 +- .../wlan_throughput_v6_ncp.slcp | 2 +- .../wlan_throughput_v6_soc.slcp | 2 +- .../out_of_box_demo/out_of_box_demo.slcp | 2 +- .../wifi_https_ble_dual_role_ncp.slcp | 2 +- .../wifi_https_ble_dual_role_soc.slcp | 2 +- .../wifi_station_ble_provisioning_ncp.slcp | 2 +- .../wifi_station_ble_provisioning_soc.slcp | 2 +- ...wifi_station_ble_provisioning_aws_ncp.slcp | 2 +- ...wifi_station_ble_provisioning_aws_soc.slcp | 2 +- ...station_ble_provisioning_aws_uart_ncp.slcp | 2 +- .../wifi_station_ble_throughput_app_ncp.slcp | 2 +- .../wifi_station_ble_throughput_app_soc.slcp | 2 +- .../wifi_throughput_ble_dual_role_ncp.slcp | 2 +- .../wifi_throughput_ble_dual_role_soc.slcp | 2 +- wiseconnect3.slce | 4 +- wiseconnect3.slsdk | 4 +- wiseconnect3_demos.xml | 24 +- wiseconnect3_docs.xml | 18 +- 348 files changed, 21014 insertions(+), 301 deletions(-) create mode 100644 components/device/silabs/si91x/mcu/drivers/cmsis_driver/CAN.c create mode 100644 components/device/silabs/si91x/mcu/drivers/cmsis_driver/CAN.h create mode 100644 components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_CAN.h create mode 100644 components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_ETH.h create mode 100644 components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_ETH_MAC.h create mode 100644 components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_ETH_PHY.h create mode 100644 components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_MCI.h create mode 100644 components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_NAND.h create mode 100644 components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_USB.h create mode 100644 components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_USBD.h create mode 100644 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components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_smih.c create mode 100644 components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_vad.c create mode 100644 components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_wurx.c diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CAN.c b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CAN.c new file mode 100644 index 000000000..679a2a27d --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CAN.c @@ -0,0 +1,982 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * $Date: 02. March 2016 + * $Revision: V1.1 + * + * Driver: Driver_CAN1 + * Configured: via RTE_Device.h configuration file + * Project: CAN Driver for Silicon Labs MCU + * -------------------------------------------------------------------------- + * Use the following configuration settings in the middleware component + * to connect to this driver. + * + * Configuration Setting Value CAN Interface + * --------------------- ----- ------------- + * Connect to hardware via Driver_CAN# = 1 use CAN1 + * -------------------------------------------------------------------------- + * Defines used for driver configuration (at compile time): + * + * CAN_CLOCK_TOLERANCE: defines maximum allowed clock tolerance in 1/1024 steps + * - default value: 15 (approx. 1.5 %) + * CAN0_OBJ_NUM: number of message objects used by CAN0 controller + * this value can be reduced to save some RAM space + * - default value: 2 (also this is maximum value) + * CAN1_OBJ_NUM: number of message objects used by CAN1 controller + * this value can be reduced to save some RAM space + * - default value: 2 (also this is maximum value) + * -------------------------------------------------------------------------- */ + +/* History: + * Version 1.0 + * Initial release + */ +#include "rsi_ccp_user_config.h" +#if defined(CHIP_9118) +#include "CAN.h" +#if RTE_CAN1 +// Externally overridable configuration definitions + +// Maximum allowed clock tolerance in 1/1024 steps +#ifndef CAN_CLOCK_TOLERANCE +#define CAN_CLOCK_TOLERANCE (15U) ///< 15/1024 approx. 1.5 % +#endif + +// Maximum number of Message Objects used for CAN1 controller +#ifndef CAN1_OBJ_NUM +#define CAN1_OBJ_NUM (2U) ///< Number of CAN objects +#endif +#if (CAN1_OBJ_NUM > 2U) +#error Too many Message Objects defined for CAN1, maximum number of Message Objects is 32 !!! +#endif + +#define CAN_IRQ_NUM (CAN1_IRQn) ///< CAN IRQ number + +// CAN Driver ****************************************************************** + +#define ARM_CAN_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,1) ///< CAN driver version + +// Driver Version +static const ARM_DRIVER_VERSION can_driver_version = { ARM_CAN_API_VERSION, ARM_CAN_DRV_VERSION }; + +// Driver Capabilities +static const ARM_CAN_CAPABILITIES can_driver_capabilities = { + CAN1_OBJ_NUM, ///< Number of CAN Objects available + 1U, // Supports reentrant calls to ARM_CAN_MessageSend, ARM_CAN_MessageRead, ARM_CAN_ObjectConfigure and abort message sending used by ARM_CAN_Control. + 0U, // Does not support CAN with Flexible Data-rate mode (CAN_FD) + 0U, // Does not support restricted operation mode + 1U, // Supports bus monitoring mode + 0U, // Supports internal loopback mode + 0U, // Supports external loopback mode +}; + +// Object Capabilities +static const ARM_CAN_OBJ_CAPABILITIES can_object_capabilities_rx = { + 0U, // Object does not support transmission + 1U, // Object supports reception + 0U, // Object does not support RTR reception and automatic Data transmission + 0U, // Object does not support RTR transmission and automatic Data reception + 0U, // Object allows assignment of multiple filters to it + 1U, // Object supports exact identifier filtering + 1U, // Object supports range identifier filtering + 1U, // Object does not support mask identifier filtering + 5U // Object can buffer 5 messages +}; +static const ARM_CAN_OBJ_CAPABILITIES can_object_capabilities_tx = { + 1U, // Object supports transmission + 0U, // Object does not support reception + 0U, // Object does not support RTR reception and automatic Data transmission + 0U, // Object does not support RTR transmission and automatic Data reception + 0U, // Object does not allow assignment of multiple filters to it + 0U, // Object does not support exact identifier filtering + 0U, // Object does not support range identifier filtering + 0U, // Object does not support mask identifier filtering + 1U // Object can buffer 1 message +}; + +// Local variables and structures +static uint8_t can_driver_powered = 0U; +static uint8_t can_driver_initialized = 0U; +static ARM_CAN_SignalUnitEvent_t CAN_SignalUnitEvent = NULL; +static ARM_CAN_SignalObjectEvent_t CAN_SignalObjectEvent = NULL; +static uint8_t can_obj_cfg_msk = 0U; +static uint8_t can_last_error_code = 0U; +/* CAN PIN configuration structure*/ +static const CAN_PIN can_pins[] = { + { RTE_CAN1_TX_PORT , RTE_CAN1_TX_PIN , RTE_CAN1_TX_MODE , RTE_CAN1_TX_PAD_SEL }, + { RTE_CAN1_RX_PORT , RTE_CAN1_RX_PIN , RTE_CAN1_RX_MODE , RTE_CAN1_TX_PAD_SEL }, +}; + + +// Helper Functions + +/** + @fn void CAN_SetHwModeConfig(CAN_HW_MODE_CONFIG mode) + @brief Configures the CAN hardware mode + @param[in] mode CAN operational mode + - \ref CAN_HW_RESET_MODE_CONFIG : CAN configure in reset mode + - \ref CAN_HW_NORMAL_MODE_CONFIG : CAN configure in normal mode + - \ref CAN_HW_LISTEN_ONLY_MODE_CONFIG : CAN configure in listen only mode + - \ref CAN_HW_DUAL_FILTER_MODE_CONFIG : CAN configure in dual filter mode + - \ref CAN_HW_SINGLE_FILTER_MODE_CONFIG : CAN configure in single filter mode + - \ref CAN_HW_ACCEPTANCE_SINGLE_FILTER_MODE_CONFIG_ENABLE : CAN enable configuration in hardware acceptance for single filter mode + - \ref CAN_HW_ACCEPTANCE_DUAL_FILTER_MODE_CONFIG_ENABLE : CAN enable configuration in hardware acceptance for dual filter mode + @return none +*/ +static void CAN_SetHwModeConfig(CAN_HW_MODE_CONFIG mode) +{ + switch(mode){ + case CAN_HW_RESET_MODE_CONFIG: // Keep DCAN in RESET mode + CAN1->CAN_MR = 0x04; + break ; + case CAN_HW_NORMAL_MODE_CONFIG: // Keep DCAN in RESET mode + CAN1->CAN_MR = 0x04; + CAN1->CAN_MR = 0x00; + break ; + case CAN_HW_LISTEN_ONLY_MODE_CONFIG: // Keep CAN in soft RESET operating mode to get the write access to AFM bit + CAN1->CAN_MR = 0x04; + CAN1->CAN_MR = 0x02; // Set standard single filter mode + break ; + case CAN_HW_DUAL_FILTER_MODE_CONFIG: // Dual filter mode configuration set + CAN1->CAN_MR = 0x04; + break ; + case CAN_HW_SINGLE_FILTER_MODE_CONFIG: //Single filter mode configuration set + CAN1->CAN_MR = 0x04; // Set CAN in RESET mode + CAN1->CAN_MR = 0x05; // Set standard single filter mode + break ; + case CAN_HW_ACCEPTANCE_SINGLE_FILTER_MODE_CONFIG_ENABLE: // Enable single filter mode configuration for filters + CAN1->CAN_MR = 0x01; + break; + case CAN_HW_ACCEPTANCE_DUAL_FILTER_MODE_CONFIG_ENABLE: // Enable dual filter mode configuration for filters + CAN1->CAN_MR = 0x00; + break; + default : + break ; + } +} + +/** + @fn int32_t CAN_AddHwFilter (CAN_FILTER_TYPE filter_type, uint32_t id, uint32_t mask) { + @brief Add filter for message reception. + @param[in] filter_type Operation on filter + - \ref CAN_FILTER_TYPE_EXACT_ID : add exact id filter + - \ref CAN_FILTER_TYPE_MASKABLE_ID : add maskable id filter + @param[in] id ID or start of ID range (depending on filter type) + @param[in] mask Mask or end of ID range (depending on filter type) + @return execution status +*/ +static int32_t CAN_AddHwFilter (CAN_FILTER_TYPE filter_type, uint32_t id, uint32_t mask) { + if ((id & ARM_CAN_ID_IDE_Msk) == 0U) { // Standard Identifier (11 bit) + switch (filter_type) { + case CAN_FILTER_TYPE_EXACT_ID: + CAN_SetHwModeConfig(CAN_HW_SINGLE_FILTER_MODE_CONFIG); //Keep CAN in filter configuration mode + CAN1->CAN_ACR = 0x00; //Reset defaults + CAN1->CAN_AMR = 0x00; + CAN1->CAN_ACR_b.ACR0 = (( id >> 3) & 0xFF); + CAN1->CAN_ACR_b.ACR1 = ((((id >> 0) & 0x07) << 5) | BIT(4)); + CAN1->CAN_ACR_b.ACR2 = 0x00; + CAN1->CAN_ACR_b.ACR3 = 0x00; + CAN1->CAN_AMR_b.AMR0 = 0x00; + CAN1->CAN_AMR_b.AMR1 = BIT(4); // Mark RTR bit as don't care + CAN1->CAN_AMR_b.AMR2 = 0xFF; + CAN1->CAN_AMR_b.AMR3 = 0xFF; + // Enable hardware filter scheme + CAN_SetHwModeConfig(CAN_HW_ACCEPTANCE_SINGLE_FILTER_MODE_CONFIG_ENABLE); + break; + + case CAN_FILTER_TYPE_MASKABLE_ID: // Add code to setup peripheral to receive messages with specified maskable ID + CAN_SetHwModeConfig(CAN_HW_SINGLE_FILTER_MODE_CONFIG); //Keep CAN in filter configuration mode + CAN1->CAN_ACR = 0x00; //Reset defaults + CAN1->CAN_AMR = 0x00; + CAN1->CAN_ACR_b.ACR0 = (( id >> 3) & 0xFF); + CAN1->CAN_ACR_b.ACR1 = ((((id >> 0) & 0x07) << 5) | BIT(4)); + CAN1->CAN_ACR_b.ACR2 = 0x00; + CAN1->CAN_ACR_b.ACR3 = 0x00; + CAN1->CAN_AMR_b.AMR0 = (( mask >> 3) & 0xFF); //Configure the mask bits + CAN1->CAN_AMR_b.AMR1 = ((((mask >> 0) & 0x07) << 5) | BIT(4)); + CAN1->CAN_AMR_b.AMR2 = 0xFF; + CAN1->CAN_AMR_b.AMR3 = 0xFF; + CAN_SetHwModeConfig(CAN_HW_ACCEPTANCE_SINGLE_FILTER_MODE_CONFIG_ENABLE); // Enable hardware filter scheme + break; + default: + // Handle unknown operation code + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + }else{ // Extended Identifier (29 bit) + switch (filter_type) { + case CAN_FILTER_TYPE_EXACT_ID: + // Add code to setup peripheral to receive messages with specified exact ID + CAN_SetHwModeConfig(CAN_HW_SINGLE_FILTER_MODE_CONFIG); + //Reset defaults + CAN1->CAN_ACR = 0x00; + CAN1->CAN_AMR = 0x00; + CAN1->CAN_ACR_b.ACR0 = (( id >> 21 ) & 0xFF); + CAN1->CAN_ACR_b.ACR1 = (( id >> 13 ) & 0xFF); + CAN1->CAN_ACR_b.ACR2 = (( id >> 5 ) & 0xFF); + CAN1->CAN_ACR_b.ACR3 = (((id >> 0 ) & 0xFF) << 3) ; + CAN1->CAN_ACR_b.ACR3 |= BIT(2); + CAN1->CAN_AMR_b.AMR3 = BIT(2); + /*Apply filter logic here */ + CAN_SetHwModeConfig(CAN_HW_ACCEPTANCE_SINGLE_FILTER_MODE_CONFIG_ENABLE); + break; + + case CAN_FILTER_TYPE_MASKABLE_ID: + // Add code to setup peripheral to receive messages with specified maskable ID + CAN_SetHwModeConfig(CAN_HW_SINGLE_FILTER_MODE_CONFIG); + //Reset defaults + CAN1->CAN_ACR = 0x00; + CAN1->CAN_AMR = 0x00; + CAN1->CAN_ACR_b.ACR0 = (( id >> 21 ) & 0xFF); + CAN1->CAN_ACR_b.ACR1 = (( id >> 13 ) & 0xFF); + CAN1->CAN_ACR_b.ACR2 = (( id >> 5 ) & 0xFF); + CAN1->CAN_ACR_b.ACR3 = (((id >> 0 ) & 0xFF) << 3) ; + CAN1->CAN_ACR_b.ACR3 |= BIT(2); + //Configure the mask bits + CAN1->CAN_AMR_b.AMR0 = (( mask >> 21 ) & 0xFF); + CAN1->CAN_AMR_b.AMR1 = (( mask >> 13 ) & 0xFF); + CAN1->CAN_AMR_b.AMR2 = (( mask >> 5 ) & 0xFF); + CAN1->CAN_AMR_b.AMR3 = ((( mask >> 0 ) & 0xFF) << 3) ; + CAN1->CAN_AMR_b.AMR3 |= BIT(2); + + /*Apply filter logic here */ + CAN_SetHwModeConfig(CAN_HW_ACCEPTANCE_SINGLE_FILTER_MODE_CONFIG_ENABLE); + break; + default: + // Handle unknown operation code + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + } + return ARM_DRIVER_OK; +} + +/** + @fn int32_t CAN_RemoveFilter (CAN_FILTER_TYPE filter_type, uint32_t id, uint32_t mask) { + @brief Add filter for message reception. + @param[in] filter_type Operation on filter + - \ref CAN_FILTER_TYPE_EXACT_ID : remove exact id filter + - \ref CAN_FILTER_TYPE_MASKABLE_ID : remove maskable id filter + @param[in] id ID or start of ID range (depending on filter type) + @param[in] mask Mask or end of ID range (depending on filter type) + @return execution status +*/ +static int32_t CAN_RemoveFilter (CAN_FILTER_TYPE filter_type, uint32_t id, uint32_t mask) { + switch (filter_type) { + case CAN_FILTER_TYPE_EXACT_ID: + case CAN_FILTER_TYPE_MASKABLE_ID: + //Keep CAN in filter configuration mode + CAN_SetHwModeConfig(CAN_HW_SINGLE_FILTER_MODE_CONFIG); + CAN1->CAN_ACR = 0xFFFFFFFF; + CAN1->CAN_AMR = 0xFFFFFFFF; + // Enable hardware filter scheme + CAN_SetHwModeConfig(CAN_HW_ACCEPTANCE_SINGLE_FILTER_MODE_CONFIG_ENABLE); + break; + default: + // Handle unknown operation code + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + return ARM_DRIVER_OK; +} + + +// CAN Driver Functions + +/** + @fn ARM_DRIVER_VERSION CAN_GetVersion (void) + @brief Get driver version. + @return \ref ARM_DRIVER_VERSION +*/ +static ARM_DRIVER_VERSION CAN_GetVersion (void) { + // Return driver version + return can_driver_version; +} + +/** + @fn ARM_CAN_CAPABILITIES CAN_GetCapabilities (void) + @brief Get driver capabilities. + @return \ref ARM_CAN_CAPABILITIES +*/ +static ARM_CAN_CAPABILITIES CAN_GetCapabilities (void) { + // Return driver capabilities + return can_driver_capabilities; +} + +/** + @fn int32_t CAN_Initialize (ARM_CAN_SignalUnitEvent_t cb_unit_event, + ARM_CAN_SignalObjectEvent_t cb_object_event) + @brief Initialize CAN interface and register signal (callback) functions. + @param[in] cb_unit_event Pointer to \ref ARM_CAN_SignalUnitEvent_t callback function + @param[in] cb_object_event Pointer to \ref ARM_CAN_SignalObjectEvent_t callback function + @return execution status +*/ +static int32_t CAN_Initialize (ARM_CAN_SignalUnitEvent_t cb_unit_event, + ARM_CAN_SignalObjectEvent_t cb_object_event) { + + const CAN_PIN *io; + + if(MCU_RET->CHIP_CONFIG_MCU_READ_b.DISABLE_CAN_INTERFACE == 1U){ + return ARM_DRIVER_ERROR_UNSUPPORTED; // If CAN peripheral is not supported by this chip + } + + if (can_driver_initialized != 0U) { return ARM_DRIVER_OK; } + + for (io = can_pins; io != &can_pins[sizeof(can_pins)/sizeof(CAN_PIN)]; io++) { + if(io->pin > 63){ + RSI_EGPIO_SetPinMux(EGPIO1 ,io->port , (io->pin - 64) , 6); + RSI_EGPIO_UlpPadReceiverEnable((io->pin) - 64); + }else{ + RSI_EGPIO_PadReceiverEnable(io->pin); + } + RSI_EGPIO_SetPinMux(EGPIO,io->port,io->pin , io->mode); + RSI_EGPIO_PadSelectionEnable(io->pad_sel); + } + + CAN_SignalUnitEvent = cb_unit_event; + CAN_SignalObjectEvent = cb_object_event; + + can_driver_initialized = 1U; + + return ARM_DRIVER_OK; +} + +/** + @fn int32_t CAN_Uninitialize (void) + @brief De-initialize CAN interface. + @return execution status +*/ +static int32_t CAN_Uninitialize (void) { + const CAN_PIN *io; + + for (io = can_pins; io != &can_pins[sizeof(can_pins)/sizeof(CAN_PIN)]; io++) { + RSI_EGPIO_SetPinMux(EGPIO,io->port,io->pin , EGPIO_PIN_MUX_MODE0); + RSI_EGPIO_PadReceiverEnable(io->pin); + if(io->pin < 63){ + RSI_EGPIO_PadSelectionEnable(io->pad_sel); + } + else{ + RSI_EGPIO_SetPinMux(EGPIO1,(io->port),(io->pin - 64U),6U); + } + } + can_driver_initialized = 0U; + return ARM_DRIVER_OK; +} + +/** + @fn int32_t CAN_PowerControl (ARM_POWER_STATE state) + @brief Control CAN interface power. + @param[in] state Power state + - \ref ARM_POWER_OFF : power off : no operation possible + - \ref ARM_POWER_LOW : low power mode: retain state, detect and signal wake-up events + - \ref ARM_POWER_FULL : power on : full operation at maximum performance + @return execution status +*/ +static int32_t CAN_PowerControl (ARM_POWER_STATE state) { + switch (state) { + case ARM_POWER_OFF: + can_driver_powered = 0U; + NVIC_DisableIRQ (CAN_IRQ_NUM); // Disable CAN NVIC + CAN1->CAN_IMR = 0U; // Disable all CAN controller interrupts + // Clear bit rate + CAN1->CAN_BTIM0_b.BRP = 0U; + CAN1->CAN_BTIM0_b.SJW = 0U; + CAN1->CAN_BTIM1_b.TSEG1 = 0U; + CAN1->CAN_BTIM1_b.TSEG2 = 0U; + CAN1->CAN_MR = 4U; // Keep CAN in reset mode + case ARM_POWER_FULL: + if (can_driver_initialized == 0U) { return ARM_DRIVER_ERROR; } + if (can_driver_powered != 0U) { return ARM_DRIVER_OK; } + M4CLK->CLK_ENABLE_SET_REG3 = M4_SOC_CLK_FOR_OTHER_ENABLE; // Enable common clock for peripheral on which CAN is also workin + M4CLK->CLK_ENABLE_SET_REG2 = CAN1_CLK_ENABLE ; // Enable CAN clock + CAN1->CAN_IMR = CAN_IMR_DOIM | // Enable interrupts + CAN_IMR_BEIM | + CAN_IMR_TIM | + CAN_IMR_RIM | + CAN_IMR_EPIM | + CAN_IMR_EWIM | + CAN_IMR_ALIM ; + can_driver_powered = 1U; + NVIC_ClearPendingIRQ (CAN_IRQ_NUM); + NVIC_EnableIRQ (CAN_IRQ_NUM); + break; + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; // Other states are not supported + } + return ARM_DRIVER_OK; +} + +/** + @fn uint32_t CAN_GetClock (void) + @brief Retrieve CAN base clock frequency. + @return base clock frequency +*/ +uint32_t CAN_GetClock (void) { + uint32_t can_div_factor = 0; + if ((M4CLK->CLK_ENABLE_SET_REG3 & M4_SOC_CLK_FOR_OTHER_ENABLE) == 0U) { // If clock to peripheral is not enabled + return 0U; + } + can_div_factor = M4CLK->CLK_CONFIG_REG3_b.CAN1_CLK_DIV_FAC; // Get CAN division factor value + if(can_div_factor == 0){ // If divider is 0 , divider is bypassed + return SystemCoreClock; + }else{ + return (SystemCoreClock /(2*can_div_factor)); + } +} + +/** + @fn CAN_SetBitrate (ARM_CAN_BITRATE_SELECT select, uint32_t bitrate, uint32_t bit_segments) + @brief Set bitrate for CAN interface. + @param[in] select Bitrate selection + - \ref ARM_CAN_BITRATE_NOMINAL : nominal (flexible data-rate arbitration) bitrate + - \ref ARM_CAN_BITRATE_FD_DATA : flexible data-rate data bitrate + @param[in] bitrate Bitrate + @param[in] bit_segments Bit segments settings + @return execution status +*/ +static int32_t CAN_SetBitrate (ARM_CAN_BITRATE_SELECT select, uint32_t bitrate, uint32_t bit_segments) { + float sjw, prop_seg, phase_seg1, phase_seg2, pclk, brp, tq_num ; + + if (select != ARM_CAN_BITRATE_NOMINAL) { return ARM_CAN_INVALID_BITRATE_SELECT; } + if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; } + + prop_seg = (bit_segments & ARM_CAN_BIT_PROP_SEG_Msk ) >> ARM_CAN_BIT_PROP_SEG_Pos; + phase_seg1 = (bit_segments & ARM_CAN_BIT_PHASE_SEG1_Msk) >> ARM_CAN_BIT_PHASE_SEG1_Pos; + phase_seg2 = (bit_segments & ARM_CAN_BIT_PHASE_SEG2_Msk) >> ARM_CAN_BIT_PHASE_SEG2_Pos; + sjw = (bit_segments & ARM_CAN_BIT_SJW_Msk ) >> ARM_CAN_BIT_SJW_Pos; + + if (((prop_seg + phase_seg1) < 1U) || ((prop_seg + phase_seg1) > 16U)) { return ARM_CAN_INVALID_BIT_PROP_SEG; } + if (( phase_seg2 < 1U) || ( phase_seg2 > 8U)) { return ARM_CAN_INVALID_BIT_PHASE_SEG2; } + if (( sjw < 1U) || ( sjw > 4U)) { return ARM_CAN_INVALID_BIT_SJW; } + + tq_num = 1U + prop_seg + phase_seg1 + phase_seg2; + pclk = CAN_GetClock(); + + if (pclk == 0U) { return ARM_DRIVER_ERROR; } + + brp = (int)((float)(1.0f/bitrate)/(float)(2.0f*(1/pclk)*tq_num)); + + if(brp > 64U) { return ARM_CAN_INVALID_BITRATE; } + + CAN_SetHwModeConfig(CAN_HW_RESET_MODE_CONFIG); // Keep CAN in reset mode + + CAN1->CAN_BTIM0_b.BRP = (brp - 1); + CAN1->CAN_BTIM0_b.SJW = (sjw - 1); + CAN1->CAN_BTIM1_b.TSEG1 = ((prop_seg + phase_seg1)- 1); + CAN1->CAN_BTIM1_b.TSEG2 = (phase_seg2 - 1); + CAN_SetHwModeConfig(CAN_HW_NORMAL_MODE_CONFIG); // Keep CAN in reset mode + + return ARM_DRIVER_OK; +} + +/** + @fn int32_t CAN_SetMode (ARM_CAN_MODE mode) + @brief Set operating mode for CAN interface. + @param[in] mode Operating mode + - \ref ARM_CAN_MODE_INITIALIZATION : initialization mode + - \ref ARM_CAN_MODE_NORMAL : normal operation mode + - \ref ARM_CAN_MODE_RESTRICTED : restricted operation mode + - \ref ARM_CAN_MODE_MONITOR : bus monitoring mode + - \ref ARM_CAN_MODE_LOOPBACK_INTERNAL : loopback internal mode + - \ref ARM_CAN_MODE_LOOPBACK_EXTERNAL : loopback external mode + @return execution status +*/ +static int32_t CAN_SetMode (ARM_CAN_MODE mode) { + + if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; } + + switch (mode) { + case ARM_CAN_MODE_INITIALIZATION: + CAN_RemoveFilter(CAN_FILTER_TYPE_EXACT_ID , 0 ,0); // Remove filters + break; + case ARM_CAN_MODE_NORMAL: + CAN_SetHwModeConfig(CAN_HW_NORMAL_MODE_CONFIG); // Configure CAN in normal mode + break; + case ARM_CAN_MODE_MONITOR: + CAN_SetHwModeConfig(CAN_HW_LISTEN_ONLY_MODE_CONFIG); // Configure the CAN in listen only mode + break; + case ARM_CAN_MODE_LOOPBACK_INTERNAL: // Not supported + case ARM_CAN_MODE_RESTRICTED: // Not supported + case ARM_CAN_MODE_LOOPBACK_EXTERNAL: // Not supported + default: + // Handle unknown mode code + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + return ARM_DRIVER_OK; +} + +/** + @fn ARM_CAN_OBJ_CAPABILITIES CAN_ObjectGetCapabilities (uint32_t obj_idx) + @brief Retrieve capabilities of an object. + @param[in] obj_idx Object index + @return \ref ARM_CAN_OBJ_CAPABILITIES +*/ +ARM_CAN_OBJ_CAPABILITIES CAN_ObjectGetCapabilities (uint32_t obj_idx) { + ARM_CAN_OBJ_CAPABILITIES obj_cap_null; + + if (obj_idx > 1U){ + memset (&obj_cap_null, 0U, sizeof(ARM_CAN_OBJ_CAPABILITIES)); + return obj_cap_null; + } + if (obj_idx == 0U) { + return can_object_capabilities_rx; + }else { + return can_object_capabilities_tx; + } +} + +/** + @fn CAN_ObjectSetFilter (uint32_t obj_idx, ARM_CAN_FILTER_OPERATION operation, uint32_t id, uint32_t arg) + @brief Add or remove filter for message reception. + @param[in] obj_idx Object index of object that filter should be or is assigned to + @param[in] operation Operation on filter + - \ref ARM_CAN_FILTER_ID_EXACT_ADD : add exact id filter + - \ref ARM_CAN_FILTER_ID_EXACT_REMOVE : remove exact id filter + - \ref ARM_CAN_FILTER_ID_RANGE_ADD : add range id filter + - \ref ARM_CAN_FILTER_ID_RANGE_REMOVE : remove range id filter + - \ref ARM_CAN_FILTER_ID_MASKABLE_ADD : add maskable id filter + - \ref ARM_CAN_FILTER_ID_MASKABLE_REMOVE : remove maskable id filter + @param[in] id ID or start of ID range (depending on filter type) + @param[in] arg Mask or end of ID range (depending on filter type) + @return execution status +*/ +static int32_t CAN_ObjectSetFilter (uint32_t obj_idx, ARM_CAN_FILTER_OPERATION operation, uint32_t id, uint32_t arg) { + int32_t status; + + if (obj_idx != 0U) { return ARM_DRIVER_ERROR_PARAMETER; } + if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; } + + switch (operation) { + case ARM_CAN_FILTER_ID_EXACT_ADD: + status = CAN_AddHwFilter (CAN_FILTER_TYPE_EXACT_ID, id, 0U); + break; + case ARM_CAN_FILTER_ID_MASKABLE_ADD: + status = CAN_AddHwFilter (CAN_FILTER_TYPE_MASKABLE_ID, id, arg); + break; + case ARM_CAN_FILTER_ID_EXACT_REMOVE: + status = CAN_RemoveFilter (CAN_FILTER_TYPE_EXACT_ID, id, 0U); + break; + case ARM_CAN_FILTER_ID_MASKABLE_REMOVE: + status = CAN_RemoveFilter (CAN_FILTER_TYPE_MASKABLE_ID, id, 0); + break; + case ARM_CAN_FILTER_ID_RANGE_ADD: // Not supported + case ARM_CAN_FILTER_ID_RANGE_REMOVE: // Not supported + default: + status = ARM_DRIVER_ERROR_UNSUPPORTED; + break; + } + + return status; +} + +/** + @fn int32_t CAN_ObjectConfigure (uint32_t obj_idx, ARM_CAN_OBJ_CONFIG obj_cfg) + @brief Configure object. + @param[in] obj_idx Object index + @param[in] obj_cfg Object configuration state + - \ref ARM_CAN_OBJ_INACTIVE : deactivate object + - \ref ARM_CAN_OBJ_RX : configure object for reception + - \ref ARM_CAN_OBJ_TX : configure object for transmission + - \ref ARM_CAN_OBJ_RX_RTR_TX_DATA : configure object that on RTR reception automatically transmits Data Frame + - \ref ARM_CAN_OBJ_TX_RTR_RX_DATA : configure object that transmits RTR and automatically receives Data Frame + @return execution status +*/ +static int32_t CAN_ObjectConfigure (uint32_t obj_idx, ARM_CAN_OBJ_CONFIG obj_cfg) { + + if (obj_idx > 1U) { return ARM_DRIVER_ERROR_PARAMETER; } + if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; } + + switch (obj_cfg) { + case ARM_CAN_OBJ_INACTIVE: + can_obj_cfg_msk &= ~(1U << obj_idx); + break; + case ARM_CAN_OBJ_RX_RTR_TX_DATA: + case ARM_CAN_OBJ_TX_RTR_RX_DATA: + can_obj_cfg_msk &= ~(1U << obj_idx); + return ARM_DRIVER_ERROR_UNSUPPORTED; + case ARM_CAN_OBJ_TX: + if (obj_idx != 1U) { return ARM_DRIVER_ERROR_PARAMETER; } + can_obj_cfg_msk = 2U; + break; + case ARM_CAN_OBJ_RX: + if (obj_idx != 0U) { return ARM_DRIVER_ERROR_PARAMETER; } + can_obj_cfg_msk = 1U; + break; + default: + return ARM_DRIVER_ERROR; + } + + return ARM_DRIVER_OK; +} + +/** + @fn int32_t CAN_MessageSend (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, const uint8_t *data, uint8_t size) + @brief Send message on CAN bus. + @param[in] obj_idx Object index + @param[in] msg_info Pointer to CAN message information + @param[in] data Pointer to data buffer + @param[in] size Number of data bytes to send + @return value >= 0 number of data bytes accepted to send + @return value < 0 execution status +*/ +static int32_t CAN_MessageSend (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, const uint8_t *data, uint8_t size) { + uint32_t tx_buf_reg1 = 0U; + uint32_t tx_buf_reg2 = 0U; + uint32_t tx_buf_reg3 = 0U; + + if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; } + if (obj_idx != 1U) { return ARM_DRIVER_ERROR_PARAMETER; } + + if(CAN1->CAN_SR_b.TBS !=1U){ // Check for the previous transmission status + return ARM_DRIVER_ERROR_BUSY; + } + if (((msg_info->id) & ARM_CAN_ID_IDE_Msk) == 0U) { // Standard Identifier (11 bit) + tx_buf_reg1 = (msg_info->dlc); + tx_buf_reg1 |= ((msg_info->id >> 3) & 0xFF) << 8U ; + tx_buf_reg1 |= ((msg_info->id >> 0) & 0x07) << 21U; + if(msg_info->rtr == 0U){ // If data frame + tx_buf_reg1 |= (data[0] << 24); + CAN1->CAN_TXBUF = tx_buf_reg1; + tx_buf_reg1 = 0U; + switch(size){ + case 8: + tx_buf_reg2 |= (data[7] << 16U); + case 7: + tx_buf_reg2 |= (data[6] << 8U ); + case 6: + tx_buf_reg2 |= (data[5] << 0U ); + case 5: + tx_buf_reg1 |= (data[4] << 24U); + case 4: + tx_buf_reg1 |= (data[3] << 16U); + case 3: + tx_buf_reg1 |= (data[2] << 8U ); + case 2: + tx_buf_reg1 |= (data[1] << 0U ); + CAN1->CAN_TXBUF = tx_buf_reg1; + CAN1->CAN_TXBUF = tx_buf_reg2; + break; + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + }else{ // Remote frame + size = 0U; + tx_buf_reg1 |= BIT(6); + CAN1->CAN_TXBUF = tx_buf_reg1; + } + }else{ // Extended Identifier (11 bit) + tx_buf_reg1 = BIT(7); + tx_buf_reg1 |= (((msg_info->id >> 21) & 0xFF ) << 8 ); + tx_buf_reg1 |= (((msg_info->id >> 13) & 0xFF ) << 16); + tx_buf_reg1 |= (((msg_info->id >> 5) & 0xFF ) << 24); + if(msg_info->rtr == 0U){ // If Data frame + tx_buf_reg1 |= msg_info->dlc; + CAN1->CAN_TXBUF = tx_buf_reg1; // Update the hardware; + tx_buf_reg1 = 0; + tx_buf_reg1 = ((msg_info->id << 3) & 0xFF); + switch(size){ + case 8: + tx_buf_reg3 |= (data[7] << 0U ); + case 7: + tx_buf_reg2 |= (data[6] << 24U); + case 6: + tx_buf_reg2 |= (data[5] << 16U); + case 5: + tx_buf_reg2 |= (data[4] << 8U ); + case 4: + tx_buf_reg2 |= (data[3] << 0U ); + case 3: + tx_buf_reg1 |= (data[2] << 24U); + case 2: + tx_buf_reg1 |= (data[1] << 16U); + case 1: + tx_buf_reg1 |= (data[0] << 8U ); + CAN1->CAN_TXBUF = tx_buf_reg1; // Update the hardware; + CAN1->CAN_TXBUF = tx_buf_reg2; // Update the hardware; + CAN1->CAN_TXBUF = tx_buf_reg3; // Update the hardware; + break; + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + }else{ // If remote frame + size = 0U; + tx_buf_reg1 |= BIT(6); + CAN1->CAN_TXBUF = tx_buf_reg1; // Update the hardware; + tx_buf_reg1 = 0; + tx_buf_reg1 = ((msg_info->id << 3) & 0xFF); + CAN1->CAN_TXBUF = tx_buf_reg1; // Update the hardware; + } + } + + CAN1->CAN_CMR_b.TR = 1U; // Trigger transfer + + return ((int32_t)size); +} + +/** + @fn int32_t CAN_MessageRead (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, uint8_t *data, uint8_t size) { + @brief Read message received on CAN bus. + @param[in] obj_idx Object index + @param[out] msg_info Pointer to read CAN message information + @param[out] data Pointer to data buffer for read data + @param[in] size Maximum number of data bytes to read + @return value >= 0 number of data bytes read + @return value < 0 execution status +*/ +static int32_t CAN_MessageRead (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, uint8_t *data, uint8_t size) { + uint32_t rx_buf_reg0=0; + uint32_t rx_buf_reg1=0; + uint32_t rx_buf_reg2=0; + uint32_t rx_buf_reg3=0; + + if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; } + if (obj_idx != 0U) { return ARM_DRIVER_ERROR_PARAMETER; } + + rx_buf_reg0 = CAN1->CAN_RXBUF; //Read FIFO + + if(rx_buf_reg0 & (1 << 6)){ + msg_info->rtr = 1U; + }else{ + msg_info->rtr = 0U; + } + msg_info->dlc= (rx_buf_reg0 & 0x0F); + if(rx_buf_reg0 & (1 << 7)){ // If extended ID is received + rx_buf_reg1 = CAN1->CAN_RXBUF; //Read FIFO + rx_buf_reg2 = CAN1->CAN_RXBUF; //Read FIFO + rx_buf_reg3 = CAN1->CAN_RXBUF; //Read FIFO + msg_info->id = (((rx_buf_reg0 >> 8 ) & 0xFF) << 21U); + msg_info->id |= (((rx_buf_reg0 >> 16) & 0xFF) << 13U); + msg_info->id |= (((rx_buf_reg0 >> 24) & 0xFF) << 5U); + msg_info->id |= (((rx_buf_reg1 >> 3 ) & 0x1F) << 0); + if(msg_info->rtr == 0U){ // Data frame is received + switch(size){ + case 8: + data[7] = ((rx_buf_reg3 >> 0) & 0xFF); + case 7: + data[6] = ((rx_buf_reg2 >> 24) & 0xFF); + case 6: + data[5] = ((rx_buf_reg2 >> 16) & 0xFF); + case 5: + data[4] = ((rx_buf_reg2 >> 8 ) & 0xFF); + case 4: + data[3] = ((rx_buf_reg2 >> 0 ) & 0xFF); + case 3: + data[2] = ((rx_buf_reg1 >> 24) & 0xFF); + case 2: + data[1] = ((rx_buf_reg1 >> 16) & 0xFF); + case 1: + data[0] = ((rx_buf_reg1 >> 8 ) & 0xFF); + break ; + case 0: + break; + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + }else{ // If remote frame is received + // Nothing + size=0U; + } + }else{ // If standard ID is received + rx_buf_reg1 = CAN1->CAN_RXBUF; //Read FIFO + rx_buf_reg2 = CAN1->CAN_RXBUF; //Read FIFO + msg_info->id = ((rx_buf_reg0 & 0xFF00) >> 8 ); + msg_info->id = (msg_info->id << 3 ); + msg_info->id |= ((rx_buf_reg0 & 0xE00000) >> 21); + if(msg_info->rtr == 0U){ // If data frame received + switch(size){ + case 8: + data[7] = ((rx_buf_reg2 >> 16) & 0xFF); + case 7: + data[6] = ((rx_buf_reg2 >> 8 ) & 0xFF); + case 6: + data[5] = ((rx_buf_reg2 >> 0 ) & 0xFF); + case 5: + data[4] = ((rx_buf_reg1 >> 24) & 0xFF); + case 4: + data[3] = ((rx_buf_reg1 >> 16) & 0xFF); + case 3: + data[2] = ((rx_buf_reg1 >> 8 ) & 0xFF); + case 2: + data[1] = ((rx_buf_reg1 >> 0 ) & 0xFF); + case 1: + data[0] = ((rx_buf_reg0 >> 24) & 0xFF); + break ; + case 0: + break; + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + }else{ + // If remote frame is received + // Nothing + size = 0U; + } + } + return ((int32_t)size); +} + +/** + @fn int32_t CAN_Control (uint32_t control, uint32_t arg) + @brief Control CAN interface. + @param[in] control Operation + - \ref ARM_CAN_SET_FD_MODE : set FD operation mode + - \ref ARM_CAN_ABORT_MESSAGE_SEND : abort sending of CAN message + - \ref ARM_CAN_CONTROL_RETRANSMISSION : enable/disable automatic retransmission + - \ref ARM_CAN_SET_TRANSCEIVER_DELAY : set transceiver delay + @param[in] arg Argument of operation + @return execution status +*/ +static int32_t CAN_Control (uint32_t control, uint32_t arg) { + + if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; } + + switch (control & ARM_CAN_CONTROL_Msk) { + case ARM_CAN_ABORT_MESSAGE_SEND: + if (arg == 1U) { + CAN1->CAN_CMR = CAN_CMR_AT; + } + break; + case ARM_CAN_CONTROL_RETRANSMISSION: + if(arg == 1U){ + CAN1->CAN_CMR = CAN_CMR_TR; + }else{ + CAN1->CAN_CMR = (CAN_CMR_AT | CAN_CMR_TR); + } + break; + case ARM_CAN_SET_FD_MODE: + case ARM_CAN_SET_TRANSCEIVER_DELAY: + default: + // Handle unknown control code + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + return ARM_DRIVER_OK; +} + +/** + @fn ARM_CAN_STATUS CAN_GetStatus (void) + @brief Get CAN status. + @return CAN status \ref ARM_CAN_STATUS +*/ +static ARM_CAN_STATUS CAN_GetStatus (void) { + ARM_CAN_STATUS status; + + memset(&status, 0U, sizeof(ARM_CAN_STATUS)); + + if (can_driver_powered == 0U) { + return status; + } + + status.last_error_code = can_last_error_code; + status.tx_error_count = CAN1->CAN_TXERR; // Update TX error count + status.rx_error_count = CAN1->CAN_RXERR; // Update RX error count + + if ((((CAN1->CAN_TXERR) > 127U) || ((CAN1->CAN_RXERR) > 127U))) { // If Error Passive Interrupt is active + status.unit_state = ARM_CAN_UNIT_STATE_PASSIVE; + } else { + status.unit_state = ARM_CAN_UNIT_STATE_ACTIVE; + } + return status; +} + + +/** + @fn void IRQ066_Handler (void) + @brief CAN1 Interrupt Routine (IRQ). +*/ +void IRQ066_Handler(void){ + uint8_t isr , sr; + + if (can_driver_powered != 0U) { + isr = CAN1->CAN_ISR_IACK; // Read interrupt status register + sr = CAN1->CAN_SR; + if(isr & CAN_ISR_DO){ // Data Over run interrupt is active + CAN_SignalObjectEvent(0U, ARM_CAN_EVENT_RECEIVE_OVERRUN); + CAN1->CAN_ISR_IACK = CAN_ISR_DO; + } + if(isr & CAN_ISR_BEI){ // Bus error interrupt is active + + if(CAN1->CAN_ECC_b.BER){ + can_last_error_code = ARM_CAN_LEC_BIT_ERROR; + } + if (CAN1->CAN_ECC_b.STFER) { + can_last_error_code = ARM_CAN_LEC_STUFF_ERROR; + } + if (CAN1->CAN_ECC_b.CRCER) { + can_last_error_code = ARM_CAN_LEC_CRC_ERROR; + } + if (CAN1->CAN_ECC_b.FRMER) { + can_last_error_code = ARM_CAN_LEC_FORM_ERROR; + } + if (CAN1->CAN_ECC_b.ACKER) { + can_last_error_code = ARM_CAN_LEC_ACK_ERROR; + } + CAN1->CAN_ISR_IACK = CAN_ISR_BEI; + } + if(isr & CAN_ISR_TI){ // Transmit interrupt interrupt is active + CAN_SignalObjectEvent(1U, ARM_CAN_EVENT_SEND_COMPLETE); + CAN1->CAN_ISR_IACK = CAN_ISR_TI; + } + if(isr & CAN_ISR_RI){ // Receive interrupt is triggered + + while(CAN1->CAN_RMC) // Note keep reading messages until FIFO empty + { + CAN_SignalObjectEvent(0U, ARM_CAN_EVENT_RECEIVE); + CAN1->CAN_ISR_IACK = CAN_ISR_RI; //Clear the RX Data over run interrupt + } + } + if(isr & CAN_ISR_EPI){ // Error passive interrupt is active + if ((((CAN1->CAN_TXERR) > 127U) || ((CAN1->CAN_RXERR) > 127U))) { // If Error Passive Interrupt is active + CAN_SignalUnitEvent(ARM_CAN_EVENT_UNIT_PASSIVE); + } else { + CAN_SignalUnitEvent(ARM_CAN_EVENT_UNIT_ACTIVE); + } + CAN1->CAN_ISR_IACK = CAN_ISR_EPI; + } + if(isr & CAN_ISR_EWI){ // Error warning interrupt + if(sr & CAN_SR_ES){ + CAN_SignalUnitEvent(ARM_CAN_EVENT_UNIT_WARNING); + } + CAN1->CAN_ISR_IACK = CAN_ISR_EWI; + } + if(isr & CAN_ISR_ALI){ // Arbitration lost interrupt + //FIXME: Handle this here //Added by me this handle + CAN_SignalUnitEvent(ARM_CAN_ARBITRATION_LOST); + CAN1->CAN_ISR_IACK = CAN_ISR_ALI; + } + } +} + +// CAN driver functions structure +ARM_DRIVER_CAN Driver_CAN1 = { + CAN_GetVersion, + CAN_GetCapabilities, + CAN_Initialize, + CAN_Uninitialize, + CAN_PowerControl, + CAN_GetClock, + CAN_SetBitrate, + CAN_SetMode, + CAN_ObjectGetCapabilities, + CAN_ObjectSetFilter, + CAN_ObjectConfigure, + CAN_MessageSend, + CAN_MessageRead, + CAN_Control, + CAN_GetStatus +}; + +#endif //RTE_CAN1 +#endif diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CAN.h b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CAN.h new file mode 100644 index 000000000..21369311c --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CAN.h @@ -0,0 +1,136 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2015 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * + * $Date: 9. September 2015 + * $Revision: V1.00 + * + * Project: CAN (Controller Area Network) Driver definitions + * -------------------------------------------------------------------------- */ + +/* History: + * Version 1.0 + * - Initial CMSIS Driver API V4.5.0 release + * + */ + + + +/** @defgroup CAN CAN Peripheral + * @{ + * +*/ + +#ifndef __CAN_H +#define __CAN_H + +#include "Driver_CAN.h" + +#include "RTE_Device.h" + + +#define ARM_CAN_ARBITRATION_LOST (5U) ///< Unit entered arbitration lost error FIXME: added by me + + +/** @defgroup CANIMRREG Can interrupt mask register bit fields + * @{ + */ +/****** CAN Interrupt mask bits *****/ +#define CAN_IMR_DOIM (1UL << 0) ///< mask for DOI interrupt +#define CAN_IMR_BEIM (1UL << 1) ///< mask for BEI interrupt +#define CAN_IMR_TIM (1UL << 2) ///< mask for TI interrupt +#define CAN_IMR_RIM (1UL << 3) ///< mask for RI interrupt +#define CAN_IMR_EPIM (1UL << 4) ///< mask for EPI interrupt +#define CAN_IMR_EWIM (1UL << 5) ///< mask for EWI interrupt +#define CAN_IMR_ALIM (1UL << 6) ///< mask for ALI interrupt +/* + * @} end of CAN_IMR_REG + * */ + +/** @defgroup CAN_ISR_REG: Can interrupt Status register bit fields + * \addtogroup CAN_ISR_REG + * @{ + */ +/****** CAN Interrupt status bits *****/ +#define CAN_ISR_DO (1UL << 0) ///< DOI interrupt +#define CAN_ISR_BEI (1UL << 1) ///< BEI interrupt +#define CAN_ISR_TI (1UL << 2) ///< TI interrupt +#define CAN_ISR_RI (1UL << 3) ///< RI interrupt +#define CAN_ISR_EPI (1UL << 4) ///< EPI interrupt +#define CAN_ISR_EWI (1UL << 5) ///< EWI interrupt +#define CAN_ISR_ALI (1UL << 6) ///< ALI interrupt +/* + * @} end of CAN_ISR_REG + * */ + +/** @defgroup CAN_SR_REG: Can Status register bit fields + * \addtogroup CAN_SR_REG + * @{ + */ +/****** CAN Interrupt status bits *****/ +#define CAN_SR_BS (1UL << 0) ///< Bus off Status +#define CAN_SR_ES (1UL << 1) ///< Error Status +#define CAN_SR_TS (1UL << 2) ///< Transmit Status +#define CAN_SR_RS (1UL << 3) ///< Receive Status +#define CAN_SR_TBS (1UL << 5) ///< Transmit Buffer Status +#define CAN_SR_DSO (1UL << 6) ///< Data Overrun Status +#define CAN_SR_RBS (1UL << 7) ///< Receive Buffer Status +/* + * @} end of CAN_SR_REG + * */ + +/** @defgroup CAN_MR_REG: Can mode register bit fields + * \addtogroup CAN_MR_REG + * @{ + */ +/****** CAN mode control bits *****/ +#define CAN_CMR_AT (1UL << 1) ///< Transmit Request +#define CAN_CMR_TR (1UL << 2) ///< Abort Transmission +/* + * @} end of CAN_MR_REG + * */ + +/****** CAN mode configuration codes *****/ +typedef enum { + CAN_HW_RESET_MODE_CONFIG, ///< CAN configure in reset mode + CAN_HW_NORMAL_MODE_CONFIG, ///< CAN configure in normal mode + CAN_HW_LISTEN_ONLY_MODE_CONFIG, ///< CAN configure in listen only mode + CAN_HW_DUAL_FILTER_MODE_CONFIG, ///< CAN configure in dual filter mode + CAN_HW_SINGLE_FILTER_MODE_CONFIG, ///< CAN configure in single filter mode + CAN_HW_ACCEPTANCE_SINGLE_FILTER_MODE_CONFIG_ENABLE,///< CAN enable configuration in hardware acceptance for single filter mode + CAN_HW_ACCEPTANCE_DUAL_FILTER_MODE_CONFIG_ENABLE, ///< CAN enable configuration in hardware acceptance for dual filter mode +}CAN_HW_MODE_CONFIG; + +/****** CAN filter type configuration codes *****/ +typedef enum { + CAN_FILTER_TYPE_EXACT_ID = 0U, ///< Add exact id filter + CAN_FILTER_TYPE_MASKABLE_ID = 1U ///< Add maskable id filter +} CAN_FILTER_TYPE; + +/** +\brief CAN Device Driver pin configurations +*/ +typedef struct { + uint8_t port; ///< CAN GPIO port + uint8_t pin; ///< CAN GPIO pin + uint8_t mode; ///< CAN GPIO mode + uint8_t pad_sel; ///< CAN GPIO pad selection +}CAN_PIN; + +#endif /* __CAN_H */ diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_CAN.h b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_CAN.h new file mode 100644 index 000000000..60a8094e5 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_CAN.h @@ -0,0 +1,232 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2015 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * + * $Date: 9. September 2015 + * $Revision: V1.00 + * + * Project: CAN (Controller Area Network) Driver definitions + * -------------------------------------------------------------------------- */ + +/* History: + * Version 1.00 + * Initial release + */ + +#ifndef __DRIVER_CAN_H +#define __DRIVER_CAN_H + +#include "Driver_Common.h" + +#define ARM_CAN_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0)/* API version */ + + +/****** CAN Bitrate selection codes *****/ +typedef enum _ARM_CAN_BITRATE_SELECT { + ARM_CAN_BITRATE_NOMINAL, ///< Select nominal (flexible data-rate arbitration) bitrate + ARM_CAN_BITRATE_FD_DATA ///< Select flexible data-rate data bitrate +} ARM_CAN_BITRATE_SELECT; + +/****** CAN Bit Propagation Segment codes (PROP_SEG) *****/ +#define ARM_CAN_BIT_PROP_SEG_Pos 0UL ///< bits 7..0 +#define ARM_CAN_BIT_PROP_SEG_Msk (0xFFUL << ARM_CAN_BIT_PROP_SEG_Pos) +#define ARM_CAN_BIT_PROP_SEG(x) (((x) << ARM_CAN_BIT_PROP_SEG_Pos) & ARM_CAN_BIT_PROP_SEG_Msk) + +/****** CAN Bit Phase Buffer Segment 1 (PHASE_SEG1) codes *****/ +#define ARM_CAN_BIT_PHASE_SEG1_Pos 8UL ///< bits 15..8 +#define ARM_CAN_BIT_PHASE_SEG1_Msk (0xFFUL << ARM_CAN_BIT_PHASE_SEG1_Pos) +#define ARM_CAN_BIT_PHASE_SEG1(x) (((x) << ARM_CAN_BIT_PHASE_SEG1_Pos) & ARM_CAN_BIT_PHASE_SEG1_Msk) + +/****** CAN Bit Phase Buffer Segment 2 (PHASE_SEG2) codes *****/ +#define ARM_CAN_BIT_PHASE_SEG2_Pos 16UL ///< bits 23..16 +#define ARM_CAN_BIT_PHASE_SEG2_Msk (0xFFUL << ARM_CAN_BIT_PHASE_SEG2_Pos) +#define ARM_CAN_BIT_PHASE_SEG2(x) (((x) << ARM_CAN_BIT_PHASE_SEG2_Pos) & ARM_CAN_BIT_PHASE_SEG2_Msk) + +/****** CAN Bit (Re)Synchronization Jump Width Segment (SJW) *****/ +#define ARM_CAN_BIT_SJW_Pos 24UL ///< bits 28..24 +#define ARM_CAN_BIT_SJW_Msk (0x1FUL << ARM_CAN_BIT_SJW_Pos) +#define ARM_CAN_BIT_SJW(x) (((x) << ARM_CAN_BIT_SJW_Pos) & ARM_CAN_BIT_SJW_Msk) + +/****** CAN Mode codes *****/ +typedef enum _ARM_CAN_MODE { + ARM_CAN_MODE_INITIALIZATION, ///< Initialization mode + ARM_CAN_MODE_NORMAL, ///< Normal operation mode + ARM_CAN_MODE_RESTRICTED, ///< Restricted operation mode + ARM_CAN_MODE_MONITOR, ///< Bus monitoring mode + ARM_CAN_MODE_LOOPBACK_INTERNAL, ///< Loopback internal mode + ARM_CAN_MODE_LOOPBACK_EXTERNAL ///< Loopback external mode +} ARM_CAN_MODE; + +/****** CAN Filter Operation codes *****/ +typedef enum _ARM_CAN_FILTER_OPERATION { + ARM_CAN_FILTER_ID_EXACT_ADD, ///< Add exact id filter + ARM_CAN_FILTER_ID_EXACT_REMOVE, ///< Remove exact id filter + ARM_CAN_FILTER_ID_RANGE_ADD, ///< Add range id filter + ARM_CAN_FILTER_ID_RANGE_REMOVE, ///< Remove range id filter + ARM_CAN_FILTER_ID_MASKABLE_ADD, ///< Add maskable id filter + ARM_CAN_FILTER_ID_MASKABLE_REMOVE ///< Remove maskable id filter +} ARM_CAN_FILTER_OPERATION; + +/****** CAN Object Configuration codes *****/ +typedef enum _ARM_CAN_OBJ_CONFIG { + ARM_CAN_OBJ_INACTIVE, ///< CAN object inactive + ARM_CAN_OBJ_TX, ///< CAN transmit object + ARM_CAN_OBJ_RX, ///< CAN receive object + ARM_CAN_OBJ_RX_RTR_TX_DATA, ///< CAN object that on RTR reception automatically transmits Data Frame + ARM_CAN_OBJ_TX_RTR_RX_DATA ///< CAN object that transmits RTR and automatically receives Data Frame +} ARM_CAN_OBJ_CONFIG; + +/** +\brief CAN Object Capabilities +*/ +typedef struct _ARM_CAN_OBJ_CAPABILITIES { + uint32_t tx : 1; ///< Object supports transmission + uint32_t rx : 1; ///< Object supports reception + uint32_t rx_rtr_tx_data : 1; ///< Object supports RTR reception and automatic Data Frame transmission + uint32_t tx_rtr_rx_data : 1; ///< Object supports RTR transmission and automatic Data Frame reception + uint32_t multiple_filters : 1; ///< Object allows assignment of multiple filters to it + uint32_t exact_filtering : 1; ///< Object supports exact identifier filtering + uint32_t range_filtering : 1; ///< Object supports range identifier filtering + uint32_t mask_filtering : 1; ///< Object supports mask identifier filtering + uint32_t message_depth : 8; ///< Number of messages buffers (FIFO) for that object +} ARM_CAN_OBJ_CAPABILITIES; + +/****** CAN Control Function Operation codes *****/ +#define ARM_CAN_CONTROL_Pos 0UL +#define ARM_CAN_CONTROL_Msk (0xFFUL << ARM_CAN_CONTROL_Pos) +#define ARM_CAN_SET_FD_MODE (1UL << ARM_CAN_CONTROL_Pos) ///< Set FD operation mode; arg: 0 = disable, 1 = enable +#define ARM_CAN_ABORT_MESSAGE_SEND (2UL << ARM_CAN_CONTROL_Pos) ///< Abort sending of CAN message; arg = object +#define ARM_CAN_CONTROL_RETRANSMISSION (3UL << ARM_CAN_CONTROL_Pos) ///< Enable/disable automatic retransmission; arg: 0 = disable, 1 = enable (default state) +#define ARM_CAN_SET_TRANSCEIVER_DELAY (4UL << ARM_CAN_CONTROL_Pos) ///< Set transceiver delay; arg = delay in time quanta + +/****** CAN ID Frame Format codes *****/ +#define ARM_CAN_ID_IDE_Pos 31UL +#define ARM_CAN_ID_IDE_Msk (1UL << ARM_CAN_ID_IDE_Pos) + +/****** CAN Identifier encoding *****/ +#define ARM_CAN_STANDARD_ID(id) (id & 0x000007FFUL) ///< CAN identifier in standard format (11-bits) +#define ARM_CAN_EXTENDED_ID(id) ((id & 0x1FFFFFFFUL) | ARM_CAN_ID_IDE_Msk)///< CAN identifier in extended format (29-bits) + +/** +\brief CAN Message Information +*/ +typedef struct _ARM_CAN_MSG_INFO { + uint32_t id; ///< CAN identifier with frame format specifier (bit 31) + uint32_t rtr : 1; ///< Remote transmission request frame + uint32_t edl : 1; ///< Flexible data-rate format extended data length + uint32_t brs : 1; ///< Flexible data-rate format with bitrate switch + uint32_t esi : 1; ///< Flexible data-rate format error state indicator + uint32_t dlc : 4; ///< Data length code +} ARM_CAN_MSG_INFO; + +/****** CAN specific error code *****/ +#define ARM_CAN_INVALID_BITRATE_SELECT (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Bitrate selection not supported +#define ARM_CAN_INVALID_BITRATE (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Requested bitrate not supported +#define ARM_CAN_INVALID_BIT_PROP_SEG (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Propagation segment value not supported +#define ARM_CAN_INVALID_BIT_PHASE_SEG1 (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Phase segment 1 value not supported +#define ARM_CAN_INVALID_BIT_PHASE_SEG2 (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Phase segment 2 value not supported +#define ARM_CAN_INVALID_BIT_SJW (ARM_DRIVER_ERROR_SPECIFIC - 6) ///< SJW value not supported +#define ARM_CAN_NO_MESSAGE_AVAILABLE (ARM_DRIVER_ERROR_SPECIFIC - 7) ///< Message is not available + +/****** CAN Status codes *****/ +#define ARM_CAN_UNIT_STATE_INACTIVE (0U) ///< Unit state: Not active on bus (initialize or error bus off) +#define ARM_CAN_UNIT_STATE_ACTIVE (1U) ///< Unit state: Active on bus (can generate active error frame) +#define ARM_CAN_UNIT_STATE_PASSIVE (2U) ///< Unit state: Error passive (can not generate active error frame) +#define ARM_CAN_LEC_NO_ERROR (0U) ///< Last error code: No error +#define ARM_CAN_LEC_BIT_ERROR (1U) ///< Last error code: Bit error +#define ARM_CAN_LEC_STUFF_ERROR (2U) ///< Last error code: Bit stuffing error +#define ARM_CAN_LEC_CRC_ERROR (3U) ///< Last error code: CRC error +#define ARM_CAN_LEC_FORM_ERROR (4U) ///< Last error code: Illegal fixed-form bit +#define ARM_CAN_LEC_ACK_ERROR (5U) ///< Last error code: Acknowledgement error + +/** +\brief CAN Status +*/ +typedef struct _ARM_CAN_STATUS { + uint32_t unit_state : 4; ///< Unit bus state + uint32_t last_error_code : 4; ///< Last error code + uint32_t tx_error_count : 8; ///< Transmitter error count + uint32_t rx_error_count : 8; ///< Receiver error count +} ARM_CAN_STATUS; + + +/****** CAN Unit Event *****/ +#define ARM_CAN_EVENT_UNIT_ACTIVE (1U) ///< Unit entered Error Active state +#define ARM_CAN_EVENT_UNIT_WARNING (2U) ///< Unit entered Error Warning state (one or both error counters >= 96) +#define ARM_CAN_EVENT_UNIT_PASSIVE (3U) ///< Unit entered Error Passive state +#define ARM_CAN_EVENT_UNIT_BUS_OFF (4U) ///< Unit entered bus off state + +/****** CAN Send/Receive Event *****/ +#define ARM_CAN_EVENT_SEND_COMPLETE (1UL << 0) ///< Send complete +#define ARM_CAN_EVENT_RECEIVE (1UL << 1) ///< Message received +#define ARM_CAN_EVENT_RECEIVE_OVERRUN (1UL << 2) ///< Received message overrun + +typedef void (*ARM_CAN_SignalUnitEvent_t) (uint32_t event); ///< Pointer to \ref ARM_CAN_SignalUnitEvent : Signal CAN Unit Event. +typedef void (*ARM_CAN_SignalObjectEvent_t) (uint32_t obj_idx, uint32_t event); ///< Pointer to \ref ARM_CAN_SignalObjectEvent : Signal CAN Object Event. + +/** +\brief CAN Device Driver Capabilities. +*/ +typedef struct _ARM_CAN_CAPABILITIES { + uint32_t num_objects : 8; ///< Number of \ref can_objects available + uint32_t reentrant_operation : 1; ///< Support for reentrant calls to \ref ARM_CAN_MessageSend, \ref ARM_CAN_MessageRead, \ref ARM_CAN_ObjectConfigure and abort message sending used by \ref ARM_CAN_Control + uint32_t fd_mode : 1; ///< Support for CAN with flexible data-rate mode (CAN_FD) (set by \ref ARM_CAN_Control) + uint32_t restricted_mode : 1; ///< Support for restricted operation mode (set by \ref ARM_CAN_SetMode) + uint32_t monitor_mode : 1; ///< Support for bus monitoring mode (set by \ref ARM_CAN_SetMode) + uint32_t internal_loopback : 1; ///< Support for internal loopback mode (set by \ref ARM_CAN_SetMode) + uint32_t external_loopback : 1; ///< Support for external loopback mode (set by \ref ARM_CAN_SetMode) +} ARM_CAN_CAPABILITIES; + + +/** +\brief Access structure of the CAN Driver. +*/ +typedef struct _ARM_DRIVER_CAN { + ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_CAN_GetVersion : Get driver version. + ARM_CAN_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_CAN_GetCapabilities : Get driver capabilities. + int32_t (*Initialize) (ARM_CAN_SignalUnitEvent_t cb_unit_event, + ARM_CAN_SignalObjectEvent_t cb_object_event); ///< Pointer to \ref ARM_CAN_Initialize : Initialize CAN interface. + int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_CAN_Uninitialize : De-initialize CAN interface. + int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_CAN_PowerControl : Control CAN interface power. + uint32_t (*GetClock) (void); ///< Pointer to \ref ARM_CAN_GetClock : Retrieve CAN base clock frequency. + int32_t (*SetBitrate) (ARM_CAN_BITRATE_SELECT select, + uint32_t bitrate, + uint32_t bit_segments); ///< Pointer to \ref ARM_CAN_SetBitrate : Set bitrate for CAN interface. + int32_t (*SetMode) (ARM_CAN_MODE mode); ///< Pointer to \ref ARM_CAN_SetMode : Set operating mode for CAN interface. + ARM_CAN_OBJ_CAPABILITIES (*ObjectGetCapabilities) (uint32_t obj_idx); ///< Pointer to \ref ARM_CAN_ObjectGetCapabilities : Retrieve capabilities of an object. + int32_t (*ObjectSetFilter) (uint32_t obj_idx, + ARM_CAN_FILTER_OPERATION operation, + uint32_t id, + uint32_t arg); ///< Pointer to \ref ARM_CAN_ObjectSetFilter : Add or remove filter for message reception. + int32_t (*ObjectConfigure) (uint32_t obj_idx, + ARM_CAN_OBJ_CONFIG obj_cfg); ///< Pointer to \ref ARM_CAN_ObjectConfigure : Configure object. + int32_t (*MessageSend) (uint32_t obj_idx, + ARM_CAN_MSG_INFO *msg_info, + const uint8_t *data, + uint8_t size); ///< Pointer to \ref ARM_CAN_MessageSend : Send message on CAN bus. + int32_t (*MessageRead) (uint32_t obj_idx, + ARM_CAN_MSG_INFO *msg_info, + uint8_t *data, + uint8_t size); ///< Pointer to \ref ARM_CAN_MessageRead : Read message received on CAN bus. + int32_t (*Control) (uint32_t control, + uint32_t arg); ///< Pointer to \ref ARM_CAN_Control : Control CAN interface. + ARM_CAN_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_CAN_GetStatus : Get CAN status. +} const ARM_DRIVER_CAN; + +#endif /* __DRIVER_CAN_H */ diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_ETH.h b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_ETH.h new file mode 100644 index 000000000..29b9e06e7 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_ETH.h @@ -0,0 +1,85 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2014 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * + * $Date: 7. Mar 2014 + * $Revision: V2.00 + * + * Project: Ethernet PHY and MAC Driver common definitions + * -------------------------------------------------------------------------- */ + +/* History: + * Version 2.00 + * Removed ARM_ETH_STATUS enumerator + * Removed ARM_ETH_MODE enumerator + * Version 1.10 + * Namespace prefix ARM_ added + * Version 1.00 + * Initial release + */ + +#ifndef __DRIVER_ETH_H +#define __DRIVER_ETH_H + +#include "Driver_Common.h" + +/** +\brief Ethernet Media Interface type +*/ +#define ARM_ETH_INTERFACE_MII 0 ///< Media Independent Interface (MII) +#define ARM_ETH_INTERFACE_RMII 1 ///< Reduced Media Independent Interface (RMII) +#define ARM_ETH_INTERFACE_SMII 2 ///< Serial Media Independent Interface (SMII) + +/** +\brief Ethernet link speed +*/ +#define ARM_ETH_SPEED_10M 0 ///< 10 Mbps link speed +#define ARM_ETH_SPEED_100M 1 ///< 100 Mbps link speed +#define ARM_ETH_SPEED_1G 2 ///< 1 Gpbs link speed + +/** +\brief Ethernet duplex mode +*/ +#define ARM_ETH_DUPLEX_HALF 0 ///< Half duplex link +#define ARM_ETH_DUPLEX_FULL 1 ///< Full duplex link + +/** +\brief Ethernet link state +*/ +typedef enum _ARM_ETH_LINK_STATE { + ARM_ETH_LINK_DOWN, ///< Link is down + ARM_ETH_LINK_UP ///< Link is up +} ARM_ETH_LINK_STATE; + +/** +\brief Ethernet link information +*/ +typedef struct _ARM_ETH_LINK_INFO { + uint32_t speed : 2; ///< Link speed: 0= 10 MBit, 1= 100 MBit, 2= 1 GBit + uint32_t duplex : 1; ///< Duplex mode: 0= Half, 1= Full +} ARM_ETH_LINK_INFO; + +/** +\brief Ethernet MAC Address +*/ +typedef struct _ARM_ETH_MAC_ADDR { + uint8_t b[6]; ///< MAC Address (6 bytes), MSB first +} ARM_ETH_MAC_ADDR; + +#endif /* __DRIVER_ETH_H */ diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_ETH_MAC.h b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_ETH_MAC.h new file mode 100644 index 000000000..775fab5d9 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_ETH_MAC.h @@ -0,0 +1,301 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2014 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * + * $Date: 30. May 2014 + * $Revision: V2.01 + * + * Project: Ethernet MAC (Media Access Control) Driver definitions + * -------------------------------------------------------------------------- */ + +/* History: + * Version 2.01 + * Added ARM_ETH_MAC_SLEEP Control + * Version 2.00 + * Changed MAC Address handling: + * moved from ARM_ETH_MAC_Initialize + * to new functions ARM_ETH_MAC_GetMacAddress and ARM_ETH_MAC_SetMacAddress + * Replaced ARM_ETH_MAC_SetMulticastAddr function with ARM_ETH_MAC_SetAddressFilter + * Extended ARM_ETH_MAC_SendFrame function with flags + * Added ARM_ETH_MAC_Control function: + * more control options (Broadcast, Multicast, Checksum offload, VLAN, ...) + * replaces ARM_ETH_MAC_SetMode + * replaces ARM_ETH_MAC_EnableTx, ARM_ETH_MAC_EnableRx + * Added optional event on transmitted frame + * Added support for PTP (Precision Time Protocol) through new functions: + * ARM_ETH_MAC_ControlTimer + * ARM_ETH_MAC_GetRxFrameTime + * ARM_ETH_MAC_GetTxFrameTime + * Changed prefix ARM_DRV -> ARM_DRIVER + * Changed return values of some functions to int32_t + * Version 1.10 + * Name space prefix ARM_ added + * Version 1.01 + * Renamed capabilities items for checksum offload + * Version 1.00 + * Initial release + */ + +#ifndef __DRIVER_ETH_MAC_H +#define __DRIVER_ETH_MAC_H + +#include "Driver_ETH.h" + +#define ARM_ETH_MAC_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,01) /* API version */ + + +#define _ARM_Driver_ETH_MAC_(n) Driver_ETH_MAC##n +#define ARM_Driver_ETH_MAC_(n) _ARM_Driver_ETH_MAC_(n) + + +/****** Ethernet MAC Control Codes *****/ + +#define ARM_ETH_MAC_CONFIGURE (0x01) ///< Configure MAC; arg = configuration +#define ARM_ETH_MAC_CONTROL_TX (0x02) ///< Transmitter; arg: 0=disabled (default), 1=enabled +#define ARM_ETH_MAC_CONTROL_RX (0x03) ///< Receiver; arg: 0=disabled (default), 1=enabled +#define ARM_ETH_MAC_FLUSH (0x04) ///< Flush buffer; arg = ARM_ETH_MAC_FLUSH_... +#define ARM_ETH_MAC_SLEEP (0x05) ///< Sleep mode; arg: 1=enter and wait for Magic packet, 0=exit +#define ARM_ETH_MAC_VLAN_FILTER (0x06) ///< VLAN Filter for received frames; arg15..0: VLAN Tag; arg16: optional ARM_ETH_MAC_VLAN_FILTER_ID_ONLY; 0=disabled (default) + +/*----- Ethernet MAC Configuration -----*/ +#define ARM_ETH_MAC_SPEED_Pos 0 +#define ARM_ETH_MAC_SPEED_Msk (3UL << ARM_ETH_MAC_SPEED_Pos) +#define ARM_ETH_MAC_SPEED_10M (ARM_ETH_SPEED_10M << ARM_ETH_MAC_SPEED_Pos) ///< 10 Mbps link speed +#define ARM_ETH_MAC_SPEED_100M (ARM_ETH_SPEED_100M << ARM_ETH_MAC_SPEED_Pos) ///< 100 Mbps link speed +#define ARM_ETH_MAC_SPEED_1G (ARM_ETH_SPEED_1G << ARM_ETH_MAC_SPEED_Pos) ///< 1 Gpbs link speed +#define ARM_ETH_MAC_DUPLEX_Pos 2 +#define ARM_ETH_MAC_DUPLEX_Msk (1UL << ARM_ETH_MAC_DUPLEX_Pos) +#define ARM_ETH_MAC_DUPLEX_HALF (ARM_ETH_DUPLEX_HALF << ARM_ETH_MAC_DUPLEX_Pos) ///< Half duplex link +#define ARM_ETH_MAC_DUPLEX_FULL (ARM_ETH_DUPLEX_FULL << ARM_ETH_MAC_DUPLEX_Pos) ///< Full duplex link +#define ARM_ETH_MAC_LOOPBACK (1UL << 4) ///< Loop-back test mode +#define ARM_ETH_MAC_CHECKSUM_OFFLOAD_RX (1UL << 5) ///< Receiver Checksum offload +#define ARM_ETH_MAC_CHECKSUM_OFFLOAD_TX (1UL << 6) ///< Transmitter Checksum offload +#define ARM_ETH_MAC_ADDRESS_BROADCAST (1UL << 7) ///< Accept frames with Broadcast address +#define ARM_ETH_MAC_ADDRESS_MULTICAST (1UL << 8) ///< Accept frames with any Multicast address +#define ARM_ETH_MAC_ADDRESS_ALL (1UL << 9) ///< Accept frames with any address (Promiscuous Mode) + +/*----- Ethernet MAC Flush Flags -----*/ +#define ARM_ETH_MAC_FLUSH_RX (1UL << 0) ///< Flush Receive buffer +#define ARM_ETH_MAC_FLUSH_TX (1UL << 1) ///< Flush Transmit buffer + +/*----- Ethernet MAC VLAN Filter Flag -----*/ +#define ARM_ETH_MAC_VLAN_FILTER_ID_ONLY (1UL << 16) ///< Compare only the VLAN Identifier (12-bit) + + +/****** Ethernet MAC Frame Transmit Flags *****/ +#define ARM_ETH_MAC_TX_FRAME_FRAGMENT (1UL << 0) ///< Indicate frame fragment +#define ARM_ETH_MAC_TX_FRAME_EVENT (1UL << 1) ///< Generate event when frame is transmitted +#define ARM_ETH_MAC_TX_FRAME_TIMESTAMP (1UL << 2) ///< Capture frame time stamp + + +/****** Ethernet MAC Timer Control Codes *****/ +#define ARM_ETH_MAC_TIMER_GET_TIME (0x01) ///< Get current time +#define ARM_ETH_MAC_TIMER_SET_TIME (0x02) ///< Set new time +#define ARM_ETH_MAC_TIMER_INC_TIME (0x03) ///< Increment current time +#define ARM_ETH_MAC_TIMER_DEC_TIME (0x04) ///< Decrement current time +#define ARM_ETH_MAC_TIMER_SET_ALARM (0x05) ///< Set alarm time +#define ARM_ETH_MAC_TIMER_ADJUST_CLOCK (0x06) ///< Adjust clock frequency; time->ns: correction factor * 2^31 + + +/** +\brief Ethernet MAC Time +*/ +typedef struct _ARM_ETH_MAC_TIME { + uint32_t ns; ///< Nano seconds + uint32_t sec; ///< Seconds +} ARM_ETH_MAC_TIME; + + +/****** Ethernet MAC Event *****/ +#define ARM_ETH_MAC_EVENT_RX_FRAME (1UL << 0) ///< Frame Received +#define ARM_ETH_MAC_EVENT_TX_FRAME (1UL << 1) ///< Frame Transmitted +#define ARM_ETH_MAC_EVENT_WAKEUP (1UL << 2) ///< Wake-up (on Magic Packet) +#define ARM_ETH_MAC_EVENT_TIMER_ALARM (1UL << 3) ///< Timer Alarm + + +// Function documentation +/** + \fn ARM_DRIVER_VERSION ARM_ETH_MAC_GetVersion (void) + \brief Get driver version. + \return \ref ARM_DRIVER_VERSION +*/ +/** + \fn ARM_ETH_MAC_CAPABILITIES ARM_ETH_MAC_GetCapabilities (void) + \brief Get driver capabilities. + \return \ref ARM_ETH_MAC_CAPABILITIES +*/ +/** + \fn int32_t ARM_ETH_MAC_Initialize (ARM_ETH_MAC_SignalEvent_t cb_event) + \brief Initialize Ethernet MAC Device. + \param[in] cb_event Pointer to \ref ARM_ETH_MAC_SignalEvent + \return \ref execution_status +*/ +/** + \fn int32_t ARM_ETH_MAC_Uninitialize (void) + \brief De-initialize Ethernet MAC Device. + \return \ref execution_status +*/ +/** + \fn int32_t ARM_ETH_MAC_PowerControl (ARM_POWER_STATE state) + \brief Control Ethernet MAC Device Power. + \param[in] state Power state + \return \ref execution_status +*/ +/** + \fn int32_t ARM_ETH_MAC_GetMacAddress (ARM_ETH_MAC_ADDR *ptr_addr) + \brief Get Ethernet MAC Address. + \param[in] ptr_addr Pointer to address + \return \ref execution_status +*/ +/** + \fn int32_t ARM_ETH_MAC_SetMacAddress (const ARM_ETH_MAC_ADDR *ptr_addr) + \brief Set Ethernet MAC Address. + \param[in] ptr_addr Pointer to address + \return \ref execution_status +*/ +/** + \fn int32_t ARM_ETH_MAC_SetAddressFilter (const ARM_ETH_MAC_ADDR *ptr_addr, + uint32_t num_addr) + \brief Configure Address Filter. + \param[in] ptr_addr Pointer to addresses + \param[in] num_addr Number of addresses to configure + \return \ref execution_status +*/ +/** + \fn int32_t ARM_ETH_MAC_SendFrame (const uint8_t *frame, uint32_t len, uint32_t flags) + \brief Send Ethernet frame. + \param[in] frame Pointer to frame buffer with data to send + \param[in] len Frame buffer length in bytes + \param[in] flags Frame transmit flags (see ARM_ETH_MAC_TX_FRAME_...) + \return \ref execution_status +*/ +/** + \fn int32_t ARM_ETH_MAC_ReadFrame (uint8_t *frame, uint32_t len) + \brief Read data of received Ethernet frame. + \param[in] frame Pointer to frame buffer for data to read into + \param[in] len Frame buffer length in bytes + \return number of data bytes read or execution status + - value >= 0: number of data bytes read + - value < 0: error occurred, value is execution status as defined with \ref execution_status +*/ +/** + \fn uint32_t ARM_ETH_MAC_GetRxFrameSize (void) + \brief Get size of received Ethernet frame. + \return number of bytes in received frame +*/ +/** + \fn int32_t ARM_ETH_MAC_GetRxFrameTime (ARM_ETH_MAC_TIME *time) + \brief Get time of received Ethernet frame. + \param[in] time Pointer to time structure for data to read into + \return \ref execution_status +*/ +/** + \fn int32_t ARM_ETH_MAC_GetTxFrameTime (ARM_ETH_MAC_TIME *time) + \brief Get time of transmitted Ethernet frame. + \param[in] time Pointer to time structure for data to read into + \return \ref execution_status +*/ +/** + \fn int32_t ARM_ETH_MAC_Control (uint32_t control, uint32_t arg) + \brief Control Ethernet Interface. + \param[in] control Operation + \param[in] arg Argument of operation (optional) + \return \ref execution_status +*/ +/** + \fn int32_t ARM_ETH_MAC_ControlTimer (uint32_t control, ARM_ETH_MAC_TIME *time) + \brief Control Precision Timer. + \param[in] control Operation + \param[in] time Pointer to time structure + \return \ref execution_status +*/ +/** + \fn int32_t ARM_ETH_MAC_PHY_Read (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data) + \brief Read Ethernet PHY Register through Management Interface. + \param[in] phy_addr 5-bit device address + \param[in] reg_addr 5-bit register address + \param[out] data Pointer where the result is written to + \return \ref execution_status +*/ +/** + \fn int32_t ARM_ETH_MAC_PHY_Write (uint8_t phy_addr, uint8_t reg_addr, uint16_t data) + \brief Write Ethernet PHY Register through Management Interface. + \param[in] phy_addr 5-bit device address + \param[in] reg_addr 5-bit register address + \param[in] data 16-bit data to write + \return \ref execution_status +*/ + +/** + \fn void ARM_ETH_MAC_SignalEvent (uint32_t event) + \brief Callback function that signals a Ethernet Event. + \param[in] event event notification mask + \return none +*/ + +typedef void (*ARM_ETH_MAC_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_ETH_MAC_SignalEvent : Signal Ethernet Event. + + +/** +\brief Ethernet MAC Capabilities +*/ +typedef struct _ARM_ETH_MAC_CAPABILITIES { + uint32_t checksum_offload_rx_ip4 : 1; ///< 1 = IPv4 header checksum verified on receive + uint32_t checksum_offload_rx_ip6 : 1; ///< 1 = IPv6 checksum verification supported on receive + uint32_t checksum_offload_rx_udp : 1; ///< 1 = UDP payload checksum verified on receive + uint32_t checksum_offload_rx_tcp : 1; ///< 1 = TCP payload checksum verified on receive + uint32_t checksum_offload_rx_icmp : 1; ///< 1 = ICMP payload checksum verified on receive + uint32_t checksum_offload_tx_ip4 : 1; ///< 1 = IPv4 header checksum generated on transmit + uint32_t checksum_offload_tx_ip6 : 1; ///< 1 = IPv6 checksum generation supported on transmit + uint32_t checksum_offload_tx_udp : 1; ///< 1 = UDP payload checksum generated on transmit + uint32_t checksum_offload_tx_tcp : 1; ///< 1 = TCP payload checksum generated on transmit + uint32_t checksum_offload_tx_icmp : 1; ///< 1 = ICMP payload checksum generated on transmit + uint32_t media_interface : 2; ///< Ethernet Media Interface type + uint32_t mac_address : 1; ///< 1 = driver provides initial valid MAC address + uint32_t event_rx_frame : 1; ///< 1 = callback event \ref ARM_ETH_MAC_EVENT_RX_FRAME generated + uint32_t event_tx_frame : 1; ///< 1 = callback event \ref ARM_ETH_MAC_EVENT_TX_FRAME generated + uint32_t event_wakeup : 1; ///< 1 = wakeup event \ref ARM_ETH_MAC_EVENT_WAKEUP generated + uint32_t precision_timer : 1; ///< 1 = Precision Timer supported +} ARM_ETH_MAC_CAPABILITIES; + + +/** +\brief Access structure of the Ethernet MAC Driver +*/ +typedef struct _ARM_DRIVER_ETH_MAC { + ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_ETH_MAC_GetVersion : Get driver version. + ARM_ETH_MAC_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_ETH_MAC_GetCapabilities : Get driver capabilities. + int32_t (*Initialize) (ARM_ETH_MAC_SignalEvent_t cb_event); ///< Pointer to \ref ARM_ETH_MAC_Initialize : Initialize Ethernet MAC Device. + int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_ETH_MAC_Uninitialize : De-initialize Ethernet MAC Device. + int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_ETH_MAC_PowerControl : Control Ethernet MAC Device Power. + int32_t (*GetMacAddress) ( ARM_ETH_MAC_ADDR *ptr_addr); ///< Pointer to \ref ARM_ETH_MAC_GetMacAddress : Get Ethernet MAC Address. + int32_t (*SetMacAddress) (const ARM_ETH_MAC_ADDR *ptr_addr); ///< Pointer to \ref ARM_ETH_MAC_SetMacAddress : Set Ethernet MAC Address. + int32_t (*SetAddressFilter)(const ARM_ETH_MAC_ADDR *ptr_addr, uint32_t num_addr); ///< Pointer to \ref ARM_ETH_MAC_SetAddressFilter : Configure Address Filter. + int32_t (*SendFrame) (const uint8_t *frame, uint32_t len, uint32_t flags); ///< Pointer to \ref ARM_ETH_MAC_SendFrame : Send Ethernet frame. + int32_t (*ReadFrame) ( uint8_t *frame, uint32_t len); ///< Pointer to \ref ARM_ETH_MAC_ReadFrame : Read data of received Ethernet frame. + uint32_t (*GetRxFrameSize) (void); ///< Pointer to \ref ARM_ETH_MAC_GetRxFrameSize : Get size of received Ethernet frame. + int32_t (*GetRxFrameTime) (ARM_ETH_MAC_TIME *time); ///< Pointer to \ref ARM_ETH_MAC_GetRxFrameTime : Get time of received Ethernet frame. + int32_t (*GetTxFrameTime) (ARM_ETH_MAC_TIME *time); ///< Pointer to \ref ARM_ETH_MAC_GetTxFrameTime : Get time of transmitted Ethernet frame. + int32_t (*ControlTimer) (uint32_t control, ARM_ETH_MAC_TIME *time); ///< Pointer to \ref ARM_ETH_MAC_ControlTimer : Control Precision Timer. + int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_ETH_MAC_Control : Control Ethernet Interface. + int32_t (*PHY_Read) (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data); ///< Pointer to \ref ARM_ETH_MAC_PHY_Read : Read Ethernet PHY Register through Management Interface. + int32_t (*PHY_Write) (uint8_t phy_addr, uint8_t reg_addr, uint16_t data); ///< Pointer to \ref ARM_ETH_MAC_PHY_Write : Write Ethernet PHY Register through Management Interface. +} const ARM_DRIVER_ETH_MAC; + +#endif /* __DRIVER_ETH_MAC_H */ diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_ETH_PHY.h b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_ETH_PHY.h new file mode 100644 index 000000000..d647a5d7e --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_ETH_PHY.h @@ -0,0 +1,133 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2014 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * + * $Date: 7. Mar 2014 + * $Revision: V2.00 + * + * Project: Ethernet PHY (Physical Transceiver) Driver definitions + * -------------------------------------------------------------------------- */ + +/* History: + * Version 2.00 + * changed parameter "mode" in function ARM_ETH_PHY_SetMode + * Changed prefix ARM_DRV -> ARM_DRIVER + * Changed return values of some functions to int32_t + * Version 1.10 + * Namespace prefix ARM_ added + * Version 1.00 + * Initial release + */ + +#ifndef __DRIVER_ETH_PHY_H +#define __DRIVER_ETH_PHY_H + +#include "Driver_ETH.h" + +#define ARM_ETH_PHY_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,00) /* API version */ + + +#define _ARM_Driver_ETH_PHY_(n) Driver_ETH_PHY##n +#define ARM_Driver_ETH_PHY_(n) _ARM_Driver_ETH_PHY_(n) + + +/****** Ethernet PHY Mode *****/ +#define ARM_ETH_PHY_SPEED_Pos 0 +#define ARM_ETH_PHY_SPEED_Msk (3UL << ARM_ETH_PHY_SPEED_Pos) +#define ARM_ETH_PHY_SPEED_10M (ARM_ETH_SPEED_10M << ARM_ETH_PHY_SPEED_Pos) ///< 10 Mbps link speed +#define ARM_ETH_PHY_SPEED_100M (ARM_ETH_SPEED_100M << ARM_ETH_PHY_SPEED_Pos) ///< 100 Mbps link speed +#define ARM_ETH_PHY_SPEED_1G (ARM_ETH_SPEED_1G << ARM_ETH_PHY_SPEED_Pos) ///< 1 Gpbs link speed +#define ARM_ETH_PHY_DUPLEX_Pos 2 +#define ARM_ETH_PHY_DUPLEX_Msk (1UL << ARM_ETH_PHY_DUPLEX_Pos) +#define ARM_ETH_PHY_DUPLEX_HALF (ARM_ETH_DUPLEX_HALF << ARM_ETH_PHY_DUPLEX_Pos) ///< Half duplex link +#define ARM_ETH_PHY_DUPLEX_FULL (ARM_ETH_DUPLEX_FULL << ARM_ETH_PHY_DUPLEX_Pos) ///< Full duplex link +#define ARM_ETH_PHY_AUTO_NEGOTIATE (1UL << 3) ///< Auto Negotiation mode +#define ARM_ETH_PHY_LOOPBACK (1UL << 4) ///< Loop-back test mode +#define ARM_ETH_PHY_ISOLATE (1UL << 5) ///< Isolate PHY from MII/RMII interface + + +// Function documentation +/** + \fn ARM_DRIVER_VERSION ARM_ETH_PHY_GetVersion (void) + \brief Get driver version. + \return \ref ARM_DRIVER_VERSION +*/ +/** + \fn int32_t ARM_ETH_PHY_Initialize (ARM_ETH_PHY_Read_t fn_read, + ARM_ETH_PHY_Write_t fn_write) + \brief Initialize Ethernet PHY Device. + \param[in] fn_read Pointer to \ref ARM_ETH_MAC_PHY_Read + \param[in] fn_write Pointer to \ref ARM_ETH_MAC_PHY_Write + \return \ref execution_status +*/ +/** + \fn int32_t ARM_ETH_PHY_Uninitialize (void) + \brief De-initialize Ethernet PHY Device. + \return \ref execution_status +*/ +/** + \fn int32_t ARM_ETH_PHY_PowerControl (ARM_POWER_STATE state) + \brief Control Ethernet PHY Device Power. + \param[in] state Power state + \return \ref execution_status +*/ +/** + \fn int32_t ARM_ETH_PHY_SetInterface (uint32_t interface) + \brief Set Ethernet Media Interface. + \param[in] interface Media Interface type + \return \ref execution_status +*/ +/** + \fn int32_t ARM_ETH_PHY_SetMode (uint32_t mode) + \brief Set Ethernet PHY Device Operation mode. + \param[in] mode Operation Mode + \return \ref execution_status +*/ +/** + \fn ARM_ETH_LINK_STATE ARM_ETH_PHY_GetLinkState (void) + \brief Get Ethernet PHY Device Link state. + \return current link status \ref ARM_ETH_LINK_STATE +*/ +/** + \fn ARM_ETH_LINK_INFO ARM_ETH_PHY_GetLinkInfo (void) + \brief Get Ethernet PHY Device Link information. + \return current link parameters \ref ARM_ETH_LINK_INFO +*/ + + +typedef int32_t (*ARM_ETH_PHY_Read_t) (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data); ///< Pointer to \ref ARM_ETH_MAC_PHY_Read : Read Ethernet PHY Register. +typedef int32_t (*ARM_ETH_PHY_Write_t) (uint8_t phy_addr, uint8_t reg_addr, uint16_t data); ///< Pointer to \ref ARM_ETH_MAC_PHY_Write : Write Ethernet PHY Register. + + +/** +\brief Access structure of the Ethernet PHY Driver +*/ +typedef struct _ARM_DRIVER_ETH_PHY { + ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_ETH_PHY_GetVersion : Get driver version. + int32_t (*Initialize) (ARM_ETH_PHY_Read_t fn_read, + ARM_ETH_PHY_Write_t fn_write); ///< Pointer to \ref ARM_ETH_PHY_Initialize : Initialize PHY Device. + int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_ETH_PHY_Uninitialize : De-initialize PHY Device. + int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_ETH_PHY_PowerControl : Control PHY Device Power. + int32_t (*SetInterface) (uint32_t interface); ///< Pointer to \ref ARM_ETH_PHY_SetInterface : Set Ethernet Media Interface. + int32_t (*SetMode) (uint32_t mode); ///< Pointer to \ref ARM_ETH_PHY_SetMode : Set Ethernet PHY Device Operation mode. + ARM_ETH_LINK_STATE (*GetLinkState) (void); ///< Pointer to \ref ARM_ETH_PHY_GetLinkState : Get Ethernet PHY Device Link state. + ARM_ETH_LINK_INFO (*GetLinkInfo) (void); ///< Pointer to \ref ARM_ETH_PHY_GetLinkInfo : Get Ethernet PHY Device Link information. +} const ARM_DRIVER_ETH_PHY; + +#endif /* __DRIVER_ETH_PHY_H */ diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_MCI.h b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_MCI.h new file mode 100644 index 000000000..9565af669 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_MCI.h @@ -0,0 +1,350 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2014 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * + * $Date: 16. May 2014 + * $Revision: V2.02 + * + * Project: MCI (Memory Card Interface) Driver definitions + * -------------------------------------------------------------------------- */ + +/* History: + * Version 2.02 + * Added timeout and error flags to ARM_MCI_STATUS + * Added support for controlling optional RST_n pin (eMMC) + * Removed explicit Clock Control (ARM_MCI_CONTROL_CLOCK) + * Removed event ARM_MCI_EVENT_BOOT_ACK_TIMEOUT + * Version 2.01 + * Decoupled SPI mode from MCI driver + * Replaced function ARM_MCI_CardSwitchRead with ARM_MCI_ReadCD and ARM_MCI_ReadWP + * Version 2.00 + * Added support for: + * SD UHS-I (Ultra High Speed) + * SD I/O Interrupt + * Read Wait (SD I/O) + * Suspend/Resume (SD I/O) + * MMC Interrupt + * MMC Boot + * Stream Data transfer (MMC) + * VCCQ Power Supply Control (eMMC) + * Command Completion Signal (CCS) for CE-ATA + * Added ARM_MCI_Control function + * Added ARM_MCI_GetStatus function + * Removed ARM_MCI_BusMode, ARM_MCI_BusDataWidth, ARM_MCI_BusSingaling functions + * (replaced by ARM_MCI_Control) + * Changed ARM_MCI_CardPower function (voltage parameter) + * Changed ARM_MCI_SendCommnad function (flags parameter) + * Changed ARM_MCI_SetupTransfer function (mode parameter) + * Removed ARM_MCI_ReadTransfer and ARM_MCI_WriteTransfer functions + * Changed prefix ARM_DRV -> ARM_DRIVER + * Changed return values of some functions to int32_t + * Version 1.10 + * Namespace prefix ARM_ added + * Version 1.00 + * Initial release + */ + +#ifndef __DRIVER_MCI_H +#define __DRIVER_MCI_H + +#include "Driver_Common.h" + +#define ARM_MCI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,02) /* API version */ + + +/****** MCI Send Command Flags *****/ +#define ARM_MCI_RESPONSE_Pos 0 +#define ARM_MCI_RESPONSE_Msk (3UL << ARM_MCI_RESPONSE_Pos) +#define ARM_MCI_RESPONSE_NONE (0UL << ARM_MCI_RESPONSE_Pos) ///< No response expected (default) +#define ARM_MCI_RESPONSE_SHORT (1UL << ARM_MCI_RESPONSE_Pos) ///< Short response (48-bit) +#define ARM_MCI_RESPONSE_SHORT_BUSY (2UL << ARM_MCI_RESPONSE_Pos) ///< Short response with busy signal (48-bit) +#define ARM_MCI_RESPONSE_LONG (3UL << ARM_MCI_RESPONSE_Pos) ///< Long response (136-bit) + +#define ARM_MCI_RESPONSE_INDEX (1UL << 2) ///< Check command index in response +#define ARM_MCI_RESPONSE_CRC (1UL << 3) ///< Check CRC in response + +#define ARM_MCI_WAIT_BUSY (1UL << 4) ///< Wait until busy before sending the command + +#define ARM_MCI_TRANSFER_DATA (1UL << 5) ///< Activate Data transfer + +#define ARM_MCI_CARD_INITIALIZE (1UL << 6) ///< Execute Memory Card initialization sequence + +#define ARM_MCI_INTERRUPT_COMMAND (1UL << 7) ///< Send Interrupt command (CMD40 - MMC only) +#define ARM_MCI_INTERRUPT_RESPONSE (1UL << 8) ///< Send Interrupt response (CMD40 - MMC only) + +#define ARM_MCI_BOOT_OPERATION (1UL << 9) ///< Execute Boot operation (MMC only) +#define ARM_MCI_BOOT_ALTERNATIVE (1UL << 10) ///< Execute Alternative Boot operation (MMC only) +#define ARM_MCI_BOOT_ACK (1UL << 11) ///< Expect Boot Acknowledge (MMC only) + +#define ARM_MCI_CCSD (1UL << 12) ///< Send Command Completion Signal Disable (CCSD) for CE-ATA device +#define ARM_MCI_CCS (1UL << 13) ///< Expect Command Completion Signal (CCS) for CE-ATA device + + +/****** MCI Setup Transfer Mode *****/ +#define ARM_MCI_TRANSFER_READ (0UL << 0) ///< Data Read Transfer (from MCI) +#define ARM_MCI_TRANSFER_WRITE (1UL << 0) ///< Data Write Transfer (to MCI) +#define ARM_MCI_TRANSFER_BLOCK (0UL << 1) ///< Block Data transfer (default) +#define ARM_MCI_TRANSFER_STREAM (1UL << 1) ///< Stream Data transfer (MMC only) + + +/****** MCI Control Codes *****/ +#define ARM_MCI_BUS_SPEED (0x01) ///< Set Bus Speed; arg = requested speed in bits/s; returns configured speed in bits/s +#define ARM_MCI_BUS_SPEED_MODE (0x02) ///< Set Bus Speed Mode as specified with arg +#define ARM_MCI_BUS_CMD_MODE (0x03) ///< Set CMD Line Mode as specified with arg +#define ARM_MCI_BUS_DATA_WIDTH (0x04) ///< Set Bus Data Width as specified with arg +#define ARM_MCI_DRIVER_STRENGTH (0x05) ///< Set SD UHS-I Driver Strength as specified with arg +#define ARM_MCI_CONTROL_RESET (0x06) ///< Control optional RST_n Pin (eMMC); arg: 0=inactive, 1=active +#define ARM_MCI_CONTROL_CLOCK_IDLE (0x07) ///< Control Clock generation on CLK Pin when idle; arg: 0=disabled, 1=enabled +#define ARM_MCI_UHS_TUNING_OPERATION (0x08) ///< Sampling clock Tuning operation (SD UHS-I); arg: 0=reset, 1=execute +#define ARM_MCI_UHS_TUNING_RESULT (0x09) ///< Sampling clock Tuning result (SD UHS-I); returns: 0=done, 1=in progress, -1=error +#define ARM_MCI_DATA_TIMEOUT (0x0A) ///< Set Data timeout; arg = timeout in bus cycles +#define ARM_MCI_CSS_TIMEOUT (0x0B) ///< Set Command Completion Signal (CCS) timeout; arg = timeout in bus cycles +#define ARM_MCI_MONITOR_SDIO_INTERRUPT (0x0C) ///< Monitor SD I/O interrupt: arg: 0=disabled, 1=enabled +#define ARM_MCI_CONTROL_READ_WAIT (0x0D) ///< Control Read/Wait for SD I/O; arg: 0=disabled, 1=enabled +#define ARM_MCI_SUSPEND_TRANSFER (0x0E) ///< Suspend Data transfer (SD I/O); returns number of remaining bytes to transfer +#define ARM_MCI_RESUME_TRANSFER (0x0F) ///< Resume Data transfer (SD I/O) + +/*----- MCI Bus Speed Mode -----*/ +#define ARM_MCI_BUS_DEFAULT_SPEED (0x00) ///< SD/MMC: Default Speed mode up to 25/26MHz +#define ARM_MCI_BUS_HIGH_SPEED (0x01) ///< SD/MMC: High Speed mode up to 50/52MHz +#define ARM_MCI_BUS_UHS_SDR12 (0x02) ///< SD: SDR12 (Single Data Rate) up to 25MHz, 12.5MB/s: UHS-I (Ultra High Speed) 1.8V signaling +#define ARM_MCI_BUS_UHS_SDR25 (0x03) ///< SD: SDR25 (Single Data Rate) up to 50MHz, 25 MB/s: UHS-I (Ultra High Speed) 1.8V signaling +#define ARM_MCI_BUS_UHS_SDR50 (0x04) ///< SD: SDR50 (Single Data Rate) up to 100MHz, 50 MB/s: UHS-I (Ultra High Speed) 1.8V signaling +#define ARM_MCI_BUS_UHS_SDR104 (0x05) ///< SD: SDR104 (Single Data Rate) up to 208MHz, 104 MB/s: UHS-I (Ultra High Speed) 1.8V signaling +#define ARM_MCI_BUS_UHS_DDR50 (0x06) ///< SD: DDR50 (Dual Data Rate) up to 50MHz, 50 MB/s: UHS-I (Ultra High Speed) 1.8V signaling + +/*----- MCI CMD Line Mode -----*/ +#define ARM_MCI_BUS_CMD_PUSH_PULL (0x00) ///< Push-Pull CMD line (default) +#define ARM_MCI_BUS_CMD_OPEN_DRAIN (0x01) ///< Open Drain CMD line (MMC only) + +/*----- MCI Bus Data Width -----*/ +#define ARM_MCI_BUS_DATA_WIDTH_1 (0x00) ///< Bus data width: 1 bit (default) +#define ARM_MCI_BUS_DATA_WIDTH_4 (0x01) ///< Bus data width: 4 bits +#define ARM_MCI_BUS_DATA_WIDTH_8 (0x02) ///< Bus data width: 8 bits +#define ARM_MCI_BUS_DATA_WIDTH_4_DDR (0x03) ///< Bus data width: 4 bits, DDR (Dual Data Rate) - MMC only +#define ARM_MCI_BUS_DATA_WIDTH_8_DDR (0x04) ///< Bus data width: 8 bits, DDR (Dual Data Rate) - MMC only + +/*----- MCI Driver Strength -----*/ +#define ARM_MCI_DRIVER_TYPE_A (0x01) ///< SD UHS-I Driver Type A +#define ARM_MCI_DRIVER_TYPE_B (0x00) ///< SD UHS-I Driver Type B (default) +#define ARM_MCI_DRIVER_TYPE_C (0x02) ///< SD UHS-I Driver Type C +#define ARM_MCI_DRIVER_TYPE_D (0x03) ///< SD UHS-I Driver Type D + + +/****** MCI Card Power *****/ +#define ARM_MCI_POWER_VDD_Pos 0 +#define ARM_MCI_POWER_VDD_Msk (0x0FUL << ARM_MCI_POWER_VDD_Pos) +#define ARM_MCI_POWER_VDD_OFF (0x01UL << ARM_MCI_POWER_VDD_Pos) ///< VDD (VCC) turned off +#define ARM_MCI_POWER_VDD_3V3 (0x02UL << ARM_MCI_POWER_VDD_Pos) ///< VDD (VCC) = 3.3V +#define ARM_MCI_POWER_VDD_1V8 (0x03UL << ARM_MCI_POWER_VDD_Pos) ///< VDD (VCC) = 1.8V +#define ARM_MCI_POWER_VCCQ_Pos 4 +#define ARM_MCI_POWER_VCCQ_Msk (0x0FUL << ARM_MCI_POWER_VCCQ_Pos) +#define ARM_MCI_POWER_VCCQ_OFF (0x01UL << ARM_MCI_POWER_VCCQ_Pos) ///< eMMC VCCQ turned off +#define ARM_MCI_POWER_VCCQ_3V3 (0x02UL << ARM_MCI_POWER_VCCQ_Pos) ///< eMMC VCCQ = 3.3V +#define ARM_MCI_POWER_VCCQ_1V8 (0x03UL << ARM_MCI_POWER_VCCQ_Pos) ///< eMMC VCCQ = 1.8V +#define ARM_MCI_POWER_VCCQ_1V2 (0x04UL << ARM_MCI_POWER_VCCQ_Pos) ///< eMMC VCCQ = 1.2V + + +/** +\brief MCI Status +*/ +typedef struct _ARM_MCI_STATUS { + uint32_t command_active : 1; ///< Command active flag + uint32_t command_timeout : 1; ///< Command timeout flag (cleared on start of next command) + uint32_t command_error : 1; ///< Command error flag (cleared on start of next command) + uint32_t transfer_active : 1; ///< Transfer active flag + uint32_t transfer_timeout : 1; ///< Transfer timeout flag (cleared on start of next command) + uint32_t transfer_error : 1; ///< Transfer error flag (cleared on start of next command) + uint32_t sdio_interrupt : 1; ///< SD I/O Interrupt flag (cleared on start of monitoring) + uint32_t ccs : 1; ///< CCS flag (cleared on start of next command) +} ARM_MCI_STATUS; + + +/****** MCI Card Event *****/ +#define ARM_MCI_EVENT_CARD_INSERTED (1UL << 0) ///< Memory Card inserted +#define ARM_MCI_EVENT_CARD_REMOVED (1UL << 1) ///< Memory Card removed +#define ARM_MCI_EVENT_COMMAND_COMPLETE (1UL << 2) ///< Command completed +#define ARM_MCI_EVENT_COMMAND_TIMEOUT (1UL << 3) ///< Command timeout +#define ARM_MCI_EVENT_COMMAND_ERROR (1UL << 4) ///< Command response error (CRC error or invalid response) +#define ARM_MCI_EVENT_TRANSFER_COMPLETE (1UL << 5) ///< Data transfer completed +#define ARM_MCI_EVENT_TRANSFER_TIMEOUT (1UL << 6) ///< Data transfer timeout +#define ARM_MCI_EVENT_TRANSFER_ERROR (1UL << 7) ///< Data transfer CRC failed +#define ARM_MCI_EVENT_SDIO_INTERRUPT (1UL << 8) ///< SD I/O Interrupt +#define ARM_MCI_EVENT_CCS (1UL << 9) ///< Command Completion Signal (CCS) +#define ARM_MCI_EVENT_CCS_TIMEOUT (1UL << 10) ///< Command Completion Signal (CCS) Timeout + + +// Function documentation +/** + \fn ARM_DRIVER_VERSION ARM_MCI_GetVersion (void) + \brief Get driver version. + \return \ref ARM_DRIVER_VERSION +*/ +/** + \fn ARM_MCI_CAPABILITIES ARM_MCI_GetCapabilities (void) + \brief Get driver capabilities. + \return \ref ARM_MCI_CAPABILITIES +*/ +/** + \fn int32_t ARM_MCI_Initialize (ARM_MCI_SignalEvent_t cb_event) + \brief Initialize the Memory Card Interface + \param[in] cb_event Pointer to \ref ARM_MCI_SignalEvent + \return \ref execution_status +*/ +/** + \fn int32_t ARM_MCI_Uninitialize (void) + \brief De-initialize Memory Card Interface. + \return \ref execution_status +*/ +/** + \fn int32_t ARM_MCI_PowerControl (ARM_POWER_STATE state) + \brief Control Memory Card Interface Power. + \param[in] state Power state \ref ARM_POWER_STATE + \return \ref execution_status +*/ +/** + \fn int32_t ARM_MCI_CardPower (uint32_t voltage) + \brief Set Memory Card Power supply voltage. + \param[in] voltage Memory Card Power supply voltage + \return \ref execution_status +*/ +/** + \fn int32_t ARM_MCI_ReadCD (void) + \brief Read Card Detect (CD) state. + \return 1:card detected, 0:card not detected, or error +*/ +/** + \fn int32_t ARM_MCI_ReadWP (void) + \brief Read Write Protect (WP) state. + \return 1:write protected, 0:not write protected, or error +*/ +/** + \fn int32_t ARM_MCI_SendCommand (uint32_t cmd, + uint32_t arg, + uint32_t flags, + uint32_t *response) + \brief Send Command to card and get the response. + \param[in] cmd Memory Card command + \param[in] arg Command argument + \param[in] flags Command flags + \param[out] response Pointer to buffer for response + \return \ref execution_status +*/ +/** + \fn int32_t ARM_MCI_SetupTransfer (uint8_t *data, + uint32_t block_count, + uint32_t block_size, + uint32_t mode) + \brief Setup read or write transfer operation. + \param[in,out] data Pointer to data block(s) to be written or read + \param[in] block_count Number of blocks + \param[in] block_size Size of a block in bytes + \param[in] mode Transfer mode + \return \ref execution_status +*/ +/** + \fn int32_t ARM_MCI_AbortTransfer (void) + \brief Abort current read/write data transfer. + \return \ref execution_status +*/ +/** + \fn int32_t ARM_MCI_Control (uint32_t control, uint32_t arg) + \brief Control MCI Interface. + \param[in] control Operation + \param[in] arg Argument of operation (optional) + \return \ref execution_status +*/ +/** + \fn ARM_MCI_STATUS ARM_MCI_GetStatus (void) + \brief Get MCI status. + \return MCI status \ref ARM_MCI_STATUS +*/ + +/** + \fn void ARM_MCI_SignalEvent (uint32_t event) + \brief Callback function that signals a MCI Card Event. + \param[in] event \ref mci_event_gr + \return none +*/ + +typedef void (*ARM_MCI_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_MCI_SignalEvent : Signal MCI Card Event. + + +/** +\brief MCI Driver Capabilities. +*/ +typedef struct _ARM_MCI_CAPABILITIES { + uint32_t cd_state : 1; ///< Card Detect State available + uint32_t cd_event : 1; ///< Signal Card Detect change event + uint32_t wp_state : 1; ///< Write Protect State available + uint32_t vdd : 1; ///< Supports VDD Card Power Supply Control + uint32_t vdd_1v8 : 1; ///< Supports 1.8 VDD Card Power Supply + uint32_t vccq : 1; ///< Supports VCCQ Card Power Supply Control (eMMC) + uint32_t vccq_1v8 : 1; ///< Supports 1.8 VCCQ Card Power Supply (eMMC) + uint32_t vccq_1v2 : 1; ///< Supports 1.2 VCCQ Card Power Supply (eMMC) + uint32_t data_width_4 : 1; ///< Supports 4-bit data + uint32_t data_width_8 : 1; ///< Supports 8-bit data + uint32_t data_width_4_ddr : 1; ///< Supports 4-bit data, DDR (Dual Data Rate) - MMC only + uint32_t data_width_8_ddr : 1; ///< Supports 8-bit data, DDR (Dual Data Rate) - MMC only + uint32_t high_speed : 1; ///< Supports SD/MMC High Speed Mode + uint32_t uhs_signaling : 1; ///< Supports SD UHS-I (Ultra High Speed) 1.8V signaling + uint32_t uhs_tuning : 1; ///< Supports SD UHS-I tuning + uint32_t uhs_sdr50 : 1; ///< Supports SD UHS-I SDR50 (Single Data Rate) up to 50MB/s + uint32_t uhs_sdr104 : 1; ///< Supports SD UHS-I SDR104 (Single Data Rate) up to 104MB/s + uint32_t uhs_ddr50 : 1; ///< Supports SD UHS-I DDR50 (Dual Data Rate) up to 50MB/s + uint32_t uhs_driver_type_a : 1; ///< Supports SD UHS-I Driver Type A + uint32_t uhs_driver_type_c : 1; ///< Supports SD UHS-I Driver Type C + uint32_t uhs_driver_type_d : 1; ///< Supports SD UHS-I Driver Type D + uint32_t sdio_interrupt : 1; ///< Supports SD I/O Interrupt + uint32_t read_wait : 1; ///< Supports Read Wait (SD I/O) + uint32_t suspend_resume : 1; ///< Supports Suspend/Resume (SD I/O) + uint32_t mmc_interrupt : 1; ///< Supports MMC Interrupt + uint32_t mmc_boot : 1; ///< Supports MMC Boot + uint32_t rst_n : 1; ///< Supports RST_n Pin Control (eMMC) + uint32_t ccs : 1; ///< Supports Command Completion Signal (CCS) for CE-ATA + uint32_t ccs_timeout : 1; ///< Supports Command Completion Signal (CCS) timeout for CE-ATA +} ARM_MCI_CAPABILITIES; + + +/** +\brief Access structure of the MCI Driver. +*/ +typedef struct _ARM_DRIVER_MCI { + ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_MCI_GetVersion : Get driver version. + ARM_MCI_CAPABILITIES (*GetCapabilities)(void); ///< Pointer to \ref ARM_MCI_GetCapabilities : Get driver capabilities. + int32_t (*Initialize) (ARM_MCI_SignalEvent_t cb_event); ///< Pointer to \ref ARM_MCI_Initialize : Initialize MCI Interface. + int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_MCI_Uninitialize : De-initialize MCI Interface. + int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_MCI_PowerControl : Control MCI Interface Power. + int32_t (*CardPower) (uint32_t voltage); ///< Pointer to \ref ARM_MCI_CardPower : Set card power supply voltage. + int32_t (*ReadCD) (void); ///< Pointer to \ref ARM_MCI_ReadCD : Read Card Detect (CD) state. + int32_t (*ReadWP) (void); ///< Pointer to \ref ARM_MCI_ReadWP : Read Write Protect (WP) state. + int32_t (*SendCommand) (uint32_t cmd, + uint32_t arg, + uint32_t flags, + uint32_t *response); ///< Pointer to \ref ARM_MCI_SendCommand : Send Command to card and get the response. + int32_t (*SetupTransfer) (uint8_t *data, + uint32_t block_count, + uint32_t block_size, + uint32_t mode); ///< Pointer to \ref ARM_MCI_SetupTransfer : Setup data transfer operation. + int32_t (*AbortTransfer) (void); ///< Pointer to \ref ARM_MCI_AbortTransfer : Abort current data transfer. + int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_MCI_Control : Control MCI Interface. + ARM_MCI_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_MCI_GetStatus : Get MCI status. +} const ARM_DRIVER_MCI; + +#endif /* __DRIVER_MCI_H */ diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_NAND.h b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_NAND.h new file mode 100644 index 000000000..fb41cc9f7 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_NAND.h @@ -0,0 +1,403 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2014 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * + * $Date: 30. May 2014 + * $Revision: V2.01 + * + * Project: NAND Flash Driver definitions + * -------------------------------------------------------------------------- */ + +/* History: + * Version 2.01 + * Updated ARM_NAND_ECC_INFO structure and ARM_NAND_ECC_xxx definitions + * Version 2.00 + * New simplified driver: + * complexity moved to upper layer (command agnostic) + * Added support for: + * NV-DDR & NV-DDR2 Interface (ONFI specification) + * VCC, VCCQ and VPP Power Supply Control + * WP (Write Protect) Control + * Version 1.11 + * Changed prefix ARM_DRV -> ARM_DRIVER + * Version 1.10 + * Namespace prefix ARM_ added + * Version 1.00 + * Initial release + */ + +#ifndef __DRIVER_NAND_H +#define __DRIVER_NAND_H + +#include "Driver_Common.h" + +#define ARM_NAND_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,01) /* API version */ + + +/****** NAND Device Power *****/ +#define ARM_NAND_POWER_VCC_Pos 0 +#define ARM_NAND_POWER_VCC_Msk (0x07UL << ARM_NAND_POWER_VCC_Pos) +#define ARM_NAND_POWER_VCC_OFF (0x01UL << ARM_NAND_POWER_VCC_Pos) ///< VCC Power off +#define ARM_NAND_POWER_VCC_3V3 (0x02UL << ARM_NAND_POWER_VCC_Pos) ///< VCC = 3.3V +#define ARM_NAND_POWER_VCC_1V8 (0x03UL << ARM_NAND_POWER_VCC_Pos) ///< VCC = 1.8V +#define ARM_NAND_POWER_VCCQ_Pos 3 +#define ARM_NAND_POWER_VCCQ_Msk (0x07UL << ARM_NAND_POWER_VCCQ_Pos) +#define ARM_NAND_POWER_VCCQ_OFF (0x01UL << ARM_NAND_POWER_VCCQ_Pos) ///< VCCQ I/O Power off +#define ARM_NAND_POWER_VCCQ_3V3 (0x02UL << ARM_NAND_POWER_VCCQ_Pos) ///< VCCQ = 3.3V +#define ARM_NAND_POWER_VCCQ_1V8 (0x03UL << ARM_NAND_POWER_VCCQ_Pos) ///< VCCQ = 1.8V +#define ARM_NAND_POWER_VPP_OFF (1UL << 6) ///< VPP off +#define ARM_NAND_POWER_VPP_ON (1Ul << 7) ///< VPP on + + +/****** NAND Control Codes *****/ +#define ARM_NAND_BUS_MODE (0x01) ///< Set Bus Mode as specified with arg +#define ARM_NAND_BUS_DATA_WIDTH (0x02) ///< Set Bus Data Width as specified with arg +#define ARM_NAND_DRIVER_STRENGTH (0x03) ///< Set Driver Strength as specified with arg +#define ARM_NAND_DEVICE_READY_EVENT (0x04) ///< Generate \ref ARM_NAND_EVENT_DEVICE_READY; arg: 0=disabled (default), 1=enabled +#define ARM_NAND_DRIVER_READY_EVENT (0x05) ///< Generate \ref ARM_NAND_EVENT_DRIVER_READY; arg: 0=disabled (default), 1=enabled + +/*----- NAND Bus Mode (ONFI - Open NAND Flash Interface) -----*/ +#define ARM_NAND_BUS_INTERFACE_Pos 4 +#define ARM_NAND_BUS_INTERFACE_Msk (0x03UL << ARM_NAND_BUS_INTERFACE_Pos) +#define ARM_NAND_BUS_SDR (0x00UL << ARM_NAND_BUS_INTERFACE_Pos) ///< Data Interface: SDR (Single Data Rate) - Traditional interface (default) +#define ARM_NAND_BUS_DDR (0x01UL << ARM_NAND_BUS_INTERFACE_Pos) ///< Data Interface: NV-DDR (Double Data Rate) +#define ARM_NAND_BUS_DDR2 (0x02UL << ARM_NAND_BUS_INTERFACE_Pos) ///< Data Interface: NV-DDR2 (Double Data Rate) +#define ARM_NAND_BUS_TIMING_MODE_Pos 0 +#define ARM_NAND_BUS_TIMING_MODE_Msk (0x0FUL << ARM_NAND_BUS_TIMING_MODE_Pos) +#define ARM_NAND_BUS_TIMING_MODE_0 (0x00UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 0 (default) +#define ARM_NAND_BUS_TIMING_MODE_1 (0x01UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 1 +#define ARM_NAND_BUS_TIMING_MODE_2 (0x02UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 2 +#define ARM_NAND_BUS_TIMING_MODE_3 (0x03UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 3 +#define ARM_NAND_BUS_TIMING_MODE_4 (0x04UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 4 (SDR EDO capable) +#define ARM_NAND_BUS_TIMING_MODE_5 (0x05UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 5 (SDR EDO capable) +#define ARM_NAND_BUS_TIMING_MODE_6 (0x06UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 6 (NV-DDR2 only) +#define ARM_NAND_BUS_TIMING_MODE_7 (0x07UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 7 (NV-DDR2 only) +#define ARM_NAND_BUS_DDR2_DO_WCYC_Pos 8 +#define ARM_NAND_BUS_DDR2_DO_WCYC_Msk (0x0FUL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) +#define ARM_NAND_BUS_DDR2_DO_WCYC_0 (0x00UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 0 (default) +#define ARM_NAND_BUS_DDR2_DO_WCYC_1 (0x01UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 1 +#define ARM_NAND_BUS_DDR2_DO_WCYC_2 (0x02UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 2 +#define ARM_NAND_BUS_DDR2_DO_WCYC_4 (0x03UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 4 +#define ARM_NAND_BUS_DDR2_DI_WCYC_Pos 12 +#define ARM_NAND_BUS_DDR2_DI_WCYC_Msk (0x0FUL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) +#define ARM_NAND_BUS_DDR2_DI_WCYC_0 (0x00UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 0 (default) +#define ARM_NAND_BUS_DDR2_DI_WCYC_1 (0x01UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 1 +#define ARM_NAND_BUS_DDR2_DI_WCYC_2 (0x02UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 2 +#define ARM_NAND_BUS_DDR2_DI_WCYC_4 (0x03UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 4 +#define ARM_NAND_BUS_DDR2_VEN (1UL << 16) ///< DDR2 Enable external VREFQ as reference +#define ARM_NAND_BUS_DDR2_CMPD (1UL << 17) ///< DDR2 Enable complementary DQS (DQS_c) signal +#define ARM_NAND_BUS_DDR2_CMPR (1UL << 18) ///< DDR2 Enable complementary RE_n (RE_c) signal + +/*----- NAND Data Bus Width -----*/ +#define ARM_NAND_BUS_DATA_WIDTH_8 (0x00) ///< Bus Data Width: 8 bit (default) +#define ARM_NAND_BUS_DATA_WIDTH_16 (0x01) ///< Bus Data Width: 16 bit + +/*----- NAND Driver Strength (ONFI - Open NAND Flash Interface) -----*/ +#define ARM_NAND_DRIVER_STRENGTH_18 (0x00) ///< Driver Strength 2.0x = 18 Ohms +#define ARM_NAND_DRIVER_STRENGTH_25 (0x01) ///< Driver Strength 1.4x = 25 Ohms +#define ARM_NAND_DRIVER_STRENGTH_35 (0x02) ///< Driver Strength 1.0x = 35 Ohms (default) +#define ARM_NAND_DRIVER_STRENGTH_50 (0x03) ///< Driver Strength 0.7x = 50 Ohms + + +/****** NAND ECC for Read/Write Data Mode and Sequence Execution Code *****/ +#define ARM_NAND_ECC_INDEX_Pos 0 +#define ARM_NAND_ECC_INDEX_Msk (0xFFUL << ARM_NAND_ECC_INDEX_Pos) +#define ARM_NAND_ECC(n) ((n) & ARM_NAND_ECC_INDEX_Msk) ///< Select ECC +#define ARM_NAND_ECC0 (1UL << 8) ///< Use ECC0 of selected ECC +#define ARM_NAND_ECC1 (1UL << 9) ///< Use ECC1 of selected ECC + +/****** NAND Flag for Read/Write Data Mode and Sequence Execution Code *****/ +#define ARM_NAND_DRIVER_DONE_EVENT (1UL << 16) ///< Generate \ref ARM_NAND_EVENT_DRIVER_DONE + +/****** NAND Sequence Execution Code *****/ +#define ARM_NAND_CODE_SEND_CMD1 (1UL << 17) ///< Send Command 1 +#define ARM_NAND_CODE_SEND_ADDR_COL1 (1UL << 18) ///< Send Column Address 1 +#define ARM_NAND_CODE_SEND_ADDR_COL2 (1UL << 19) ///< Send Column Address 2 +#define ARM_NAND_CODE_SEND_ADDR_ROW1 (1UL << 20) ///< Send Row Address 1 +#define ARM_NAND_CODE_SEND_ADDR_ROW2 (1UL << 21) ///< Send Row Address 2 +#define ARM_NAND_CODE_SEND_ADDR_ROW3 (1UL << 22) ///< Send Row Address 3 +#define ARM_NAND_CODE_INC_ADDR_ROW (1UL << 23) ///< Auto-increment Row Address +#define ARM_NAND_CODE_WRITE_DATA (1UL << 24) ///< Write Data +#define ARM_NAND_CODE_SEND_CMD2 (1UL << 25) ///< Send Command 2 +#define ARM_NAND_CODE_WAIT_BUSY (1UL << 26) ///< Wait while R/Bn busy +#define ARM_NAND_CODE_READ_DATA (1UL << 27) ///< Read Data +#define ARM_NAND_CODE_SEND_CMD3 (1UL << 28) ///< Send Command 3 +#define ARM_NAND_CODE_READ_STATUS (1UL << 29) ///< Read Status byte and check FAIL bit (bit 0) + +/*----- NAND Sequence Execution Code: Command -----*/ +#define ARM_NAND_CODE_CMD1_Pos 0 +#define ARM_NAND_CODE_CMD1_Msk (0xFFUL << ARM_NAND_CODE_CMD1_Pos) +#define ARM_NAND_CODE_CMD2_Pos 8 +#define ARM_NAND_CODE_CMD2_Msk (0xFFUL << ARM_NAND_CODE_CMD2_Pos) +#define ARM_NAND_CODE_CMD3_Pos 16 +#define ARM_NAND_CODE_CMD3_Msk (0xFFUL << ARM_NAND_CODE_CMD3_Pos) + +/*----- NAND Sequence Execution Code: Column Address -----*/ +#define ARM_NAND_CODE_ADDR_COL1_Pos 0 +#define ARM_NAND_CODE_ADDR_COL1_Msk (0xFFUL << ARM_NAND_CODE_ADDR_COL1_Pos) +#define ARM_NAND_CODE_ADDR_COL2_Pos 8 +#define ARM_NAND_CODE_ADDR_COL2_Msk (0xFFUL << ARM_NAND_CODE_ADDR_COL2_Pos) + +/*----- NAND Sequence Execution Code: Row Address -----*/ +#define ARM_NAND_CODE_ADDR_ROW1_Pos 0 +#define ARM_NAND_CODE_ADDR_ROW1_Msk (0xFFUL << ARM_NAND_CODE_ADDR_ROW1_Pos) +#define ARM_NAND_CODE_ADDR_ROW2_Pos 8 +#define ARM_NAND_CODE_ADDR_ROW2_Msk (0xFFUL << ARM_NAND_CODE_ADDR_ROW2_Pos) +#define ARM_NAND_CODE_ADDR_ROW3_Pos 16 +#define ARM_NAND_CODE_ADDR_ROW3_Msk (0xFFUL << ARM_NAND_CODE_ADDR_ROW3_Pos) + + +/****** NAND specific error codes *****/ +#define ARM_NAND_ERROR_ECC (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< ECC generation/correction failed + + +/** +\brief NAND ECC (Error Correction Code) Information +*/ +typedef struct _ARM_NAND_ECC_INFO { + uint32_t type : 2; ///< Type: 1=ECC0 over Data, 2=ECC0 over Data+Spare, 3=ECC0 over Data and ECC1 over Spare + uint32_t page_layout : 1; ///< Page layout: 0=|Data0|Spare0|...|DataN-1|SpareN-1|, 1=|Data0|...|DataN-1|Spare0|...|SpareN-1| + uint32_t page_count : 3; ///< Number of virtual pages: N = 2 ^ page_count + uint32_t page_size : 4; ///< Virtual Page size (Data+Spare): 0=512+16, 1=1k+32, 2=2k+64, 3=4k+128, 4=8k+256, 8=512+28, 9=1k+56, 10=2k+112, 11=4k+224, 12=8k+448 + uint32_t reserved : 14; ///< Reserved (must be zero) + uint32_t correctable_bits : 8; ///< Number of correctable bits (based on 512 byte codeword size) + uint16_t codeword_size [2]; ///< Number of bytes over which ECC is calculated + uint16_t ecc_size [2]; ///< ECC size in bytes (rounded up) + uint16_t ecc_offset [2]; ///< ECC offset in bytes (where ECC starts in Spare area) +} ARM_NAND_ECC_INFO; + + +/** +\brief NAND Status +*/ +typedef struct _ARM_NAND_STATUS { + uint32_t busy : 1; ///< Driver busy flag + uint32_t ecc_error : 1; ///< ECC error detected (cleared on next Read/WriteData or ExecuteSequence) +} ARM_NAND_STATUS; + + +/****** NAND Event *****/ +#define ARM_NAND_EVENT_DEVICE_READY (1UL << 0) ///< Device Ready: R/Bn rising edge +#define ARM_NAND_EVENT_DRIVER_READY (1UL << 1) ///< Driver Ready +#define ARM_NAND_EVENT_DRIVER_DONE (1UL << 2) ///< Driver operation done +#define ARM_NAND_EVENT_ECC_ERROR (1UL << 3) ///< ECC could not correct data + + +// Function documentation +/** + \fn ARM_DRIVER_VERSION ARM_NAND_GetVersion (void) + \brief Get driver version. + \return \ref ARM_DRIVER_VERSION +*/ +/** + \fn ARM_NAND_CAPABILITIES ARM_NAND_GetCapabilities (void) + \brief Get driver capabilities. + \return \ref ARM_NAND_CAPABILITIES +*/ +/** + \fn int32_t ARM_NAND_Initialize (ARM_NAND_SignalEvent_t cb_event) + \brief Initialize the NAND Interface. + \param[in] cb_event Pointer to \ref ARM_NAND_SignalEvent + \return \ref execution_status +*/ +/** + \fn int32_t ARM_NAND_Uninitialize (void) + \brief De-initialize the NAND Interface. + \return \ref execution_status +*/ +/** + \fn int32_t ARM_NAND_PowerControl (ARM_POWER_STATE state) + \brief Control the NAND interface power. + \param[in] state Power state + \return \ref execution_status +*/ +/** + \fn int32_t ARM_NAND_DevicePower (uint32_t voltage) + \brief Set device power supply voltage. + \param[in] voltage NAND Device supply voltage + \return \ref execution_status +*/ +/** + \fn int32_t ARM_NAND_WriteProtect (uint32_t dev_num, bool enable) + \brief Control WPn (Write Protect). + \param[in] dev_num Device number + \param[in] enable + - \b false Write Protect off + - \b true Write Protect on + \return \ref execution_status +*/ +/** + \fn int32_t ARM_NAND_ChipEnable (uint32_t dev_num, bool enable) + \brief Control CEn (Chip Enable). + \param[in] dev_num Device number + \param[in] enable + - \b false Chip Enable off + - \b true Chip Enable on + \return \ref execution_status +*/ +/** + \fn int32_t ARM_NAND_GetDeviceBusy (uint32_t dev_num) + \brief Get Device Busy pin state. + \param[in] dev_num Device number + \return 1=busy, 0=not busy, or error +*/ +/** + \fn int32_t ARM_NAND_SendCommand (uint32_t dev_num, uint8_t cmd) + \brief Send command to NAND device. + \param[in] dev_num Device number + \param[in] cmd Command + \return \ref execution_status +*/ +/** + \fn int32_t ARM_NAND_SendAddress (uint32_t dev_num, uint8_t addr) + \brief Send address to NAND device. + \param[in] dev_num Device number + \param[in] addr Address + \return \ref execution_status +*/ +/** + \fn int32_t ARM_NAND_ReadData (uint32_t dev_num, void *data, uint32_t cnt, uint32_t mode) + \brief Read data from NAND device. + \param[in] dev_num Device number + \param[out] data Pointer to buffer for data to read from NAND device + \param[in] cnt Number of data items to read + \param[in] mode Operation mode + \return number of data items read or \ref execution_status +*/ +/** + \fn int32_t ARM_NAND_WriteData (uint32_t dev_num, const void *data, uint32_t cnt, uint32_t mode) + \brief Write data to NAND device. + \param[in] dev_num Device number + \param[out] data Pointer to buffer with data to write to NAND device + \param[in] cnt Number of data items to write + \param[in] mode Operation mode + \return number of data items written or \ref execution_status +*/ +/** + \fn int32_t ARM_NAND_ExecuteSequence (uint32_t dev_num, uint32_t code, uint32_t cmd, + uint32_t addr_col, uint32_t addr_row, + void *data, uint32_t data_cnt, + uint8_t *status, uint32_t *count) + \brief Execute sequence of operations. + \param[in] dev_num Device number + \param[in] code Sequence code + \param[in] cmd Command(s) + \param[in] addr_col Column address + \param[in] addr_row Row address + \param[in,out] data Pointer to data to be written or read + \param[in] data_cnt Number of data items in one iteration + \param[out] status Pointer to status read + \param[in,out] count Number of iterations + \return \ref execution_status +*/ +/** + \fn int32_t ARM_NAND_AbortSequence (uint32_t dev_num) + \brief Abort sequence execution. + \param[in] dev_num Device number + \return \ref execution_status +*/ +/** + \fn int32_t ARM_NAND_Control (uint32_t dev_num, uint32_t control, uint32_t arg) + \brief Control NAND Interface. + \param[in] dev_num Device number + \param[in] control Operation + \param[in] arg Argument of operation + \return \ref execution_status +*/ +/** + \fn ARM_NAND_STATUS ARM_NAND_GetStatus (uint32_t dev_num) + \brief Get NAND status. + \param[in] dev_num Device number + \return NAND status \ref ARM_NAND_STATUS +*/ +/** + \fn int32_t ARM_NAND_InquireECC (int32_t index, ARM_NAND_ECC_INFO *info) + \brief Inquire about available ECC. + \param[in] index Device number + \param[out] info Pointer to ECC information \ref ARM_NAND_ECC_INFO retrieved + \return \ref execution_status +*/ + +/** + \fn void ARM_NAND_SignalEvent (uint32_t dev_num, uint32_t event) + \brief Signal NAND event. + \param[in] dev_num Device number + \param[in] event Event notification mask + \return none +*/ + +typedef void (*ARM_NAND_SignalEvent_t) (uint32_t dev_num, uint32_t event); ///< Pointer to \ref ARM_NAND_SignalEvent : Signal NAND Event. + + +/** +\brief NAND Driver Capabilities. +*/ +typedef struct _ARM_NAND_CAPABILITIES { + uint32_t event_device_ready : 1; ///< Signal Device Ready event (R/Bn rising edge) + uint32_t reentrant_operation : 1; ///< Supports re-entrant operation (SendCommand/Address, Read/WriteData) + uint32_t sequence_operation : 1; ///< Supports Sequence operation (ExecuteSequence, AbortSequence) + uint32_t vcc : 1; ///< Supports VCC Power Supply Control + uint32_t vcc_1v8 : 1; ///< Supports 1.8 VCC Power Supply + uint32_t vccq : 1; ///< Supports VCCQ I/O Power Supply Control + uint32_t vccq_1v8 : 1; ///< Supports 1.8 VCCQ I/O Power Supply + uint32_t vpp : 1; ///< Supports VPP High Voltage Power Supply Control + uint32_t wp : 1; ///< Supports WPn (Write Protect) Control + uint32_t ce_lines : 4; ///< Number of CEn (Chip Enable) lines: ce_lines + 1 + uint32_t ce_manual : 1; ///< Supports manual CEn (Chip Enable) Control + uint32_t rb_monitor : 1; ///< Supports R/Bn (Ready/Busy) Monitoring + uint32_t data_width_16 : 1; ///< Supports 16-bit data + uint32_t ddr : 1; ///< Supports NV-DDR Data Interface (ONFI) + uint32_t ddr2 : 1; ///< Supports NV-DDR2 Data Interface (ONFI) + uint32_t sdr_timing_mode : 3; ///< Fastest (highest) SDR Timing Mode supported (ONFI) + uint32_t ddr_timing_mode : 3; ///< Fastest (highest) NV_DDR Timing Mode supported (ONFI) + uint32_t ddr2_timing_mode : 3; ///< Fastest (highest) NV_DDR2 Timing Mode supported (ONFI) + uint32_t driver_strength_18 : 1; ///< Supports Driver Strength 2.0x = 18 Ohms + uint32_t driver_strength_25 : 1; ///< Supports Driver Strength 1.4x = 25 Ohms + uint32_t driver_strength_50 : 1; ///< Supports Driver Strength 0.7x = 50 Ohms +} ARM_NAND_CAPABILITIES; + + +/** +\brief Access structure of the NAND Driver. +*/ +typedef struct _ARM_DRIVER_NAND { + ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_NAND_GetVersion : Get driver version. + ARM_NAND_CAPABILITIES (*GetCapabilities)(void); ///< Pointer to \ref ARM_NAND_GetCapabilities : Get driver capabilities. + int32_t (*Initialize) (ARM_NAND_SignalEvent_t cb_event); ///< Pointer to \ref ARM_NAND_Initialize : Initialize NAND Interface. + int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_NAND_Uninitialize : De-initialize NAND Interface. + int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_NAND_PowerControl : Control NAND Interface Power. + int32_t (*DevicePower) (uint32_t voltage); ///< Pointer to \ref ARM_NAND_DevicePower : Set device power supply voltage. + int32_t (*WriteProtect) (uint32_t dev_num, bool enable); ///< Pointer to \ref ARM_NAND_WriteProtect : Control WPn (Write Protect). + int32_t (*ChipEnable) (uint32_t dev_num, bool enable); ///< Pointer to \ref ARM_NAND_ChipEnable : Control CEn (Chip Enable). + int32_t (*GetDeviceBusy) (uint32_t dev_num); ///< Pointer to \ref ARM_NAND_GetDeviceBusy : Get Device Busy pin state. + int32_t (*SendCommand) (uint32_t dev_num, uint8_t cmd); ///< Pointer to \ref ARM_NAND_SendCommand : Send command to NAND device. + int32_t (*SendAddress) (uint32_t dev_num, uint8_t addr); ///< Pointer to \ref ARM_NAND_SendAddress : Send address to NAND device. + int32_t (*ReadData) (uint32_t dev_num, void *data, uint32_t cnt, uint32_t mode); ///< Pointer to \ref ARM_NAND_ReadData : Read data from NAND device. + int32_t (*WriteData) (uint32_t dev_num, const void *data, uint32_t cnt, uint32_t mode); ///< Pointer to \ref ARM_NAND_WriteData : Write data to NAND device. + int32_t (*ExecuteSequence)(uint32_t dev_num, uint32_t code, uint32_t cmd, + uint32_t addr_col, uint32_t addr_row, + void *data, uint32_t data_cnt, + uint8_t *status, uint32_t *count); ///< Pointer to \ref ARM_NAND_ExecuteSequence : Execute sequence of operations. + int32_t (*AbortSequence) (uint32_t dev_num); ///< Pointer to \ref ARM_NAND_AbortSequence : Abort sequence execution. + int32_t (*Control) (uint32_t dev_num, uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_NAND_Control : Control NAND Interface. + ARM_NAND_STATUS (*GetStatus) (uint32_t dev_num); ///< Pointer to \ref ARM_NAND_GetStatus : Get NAND status. + int32_t (*InquireECC) ( int32_t index, ARM_NAND_ECC_INFO *info); ///< Pointer to \ref ARM_NAND_InquireECC : Inquire about available ECC. +} const ARM_DRIVER_NAND; + +#endif /* __DRIVER_NAND_H */ diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_USB.h b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_USB.h new file mode 100644 index 000000000..7f51a2ad2 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_USB.h @@ -0,0 +1,95 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2014 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * + * $Date: 20. May 2014 + * $Revision: V2.00 + * + * Project: USB Driver common definitions + * -------------------------------------------------------------------------- */ + +/* History: + * Version 2.00 + * Version 1.10 + * Namespace prefix ARM_ added + * Version 1.01 + * Added PID Types + * Version 1.00 + * Initial release + */ + +#ifndef __DRIVER_USB_H +#define __DRIVER_USB_H + +#include "Driver_Common.h" + +/* USB Role */ +#define ARM_USB_ROLE_NONE 0 +#define ARM_USB_ROLE_HOST 1 +#define ARM_USB_ROLE_DEVICE 2 + +/* USB Pins */ +#define ARM_USB_PIN_DP (1 << 0) ///< USB D+ pin +#define ARM_USB_PIN_DM (1 << 1) ///< USB D- pin +#define ARM_USB_PIN_VBUS (1 << 2) ///< USB VBUS pin +#define ARM_USB_PIN_OC (1 << 3) ///< USB OverCurrent pin +#define ARM_USB_PIN_ID (1 << 4) ///< USB ID pin + +/* USB Speed */ +#define ARM_USB_SPEED_LOW 0 ///< Low-speed USB +#define ARM_USB_SPEED_FULL 1 ///< Full-speed USB +#define ARM_USB_SPEED_HIGH 2 ///< High-speed USB + +/* USB PID Types */ +#define ARM_USB_PID_OUT 1 +#define ARM_USB_PID_IN 9 +#define ARM_USB_PID_SOF 5 +#define ARM_USB_PID_SETUP 13 +#define ARM_USB_PID_DATA0 3 +#define ARM_USB_PID_DATA1 11 +#define ARM_USB_PID_DATA2 7 +#define ARM_USB_PID_MDATA 15 +#define ARM_USB_PID_ACK 2 +#define ARM_USB_PID_NAK 10 +#define ARM_USB_PID_STALL 14 +#define ARM_USB_PID_NYET 6 +#define ARM_USB_PID_PRE 12 +#define ARM_USB_PID_ERR 12 +#define ARM_USB_PID_SPLIT 8 +#define ARM_USB_PID_PING 4 +#define ARM_USB_PID_RESERVED 0 + +/* USB Endpoint Address (bEndpointAddress) */ +#define ARM_USB_ENDPOINT_NUMBER_MASK 0x0F +#define ARM_USB_ENDPOINT_DIRECTION_MASK 0x80 + +/* USB Endpoint Type */ +#define ARM_USB_ENDPOINT_CONTROL 0 ///< Control Endpoint +#define ARM_USB_ENDPOINT_ISOCHRONOUS 1 ///< Isochronous Endpoint +#define ARM_USB_ENDPOINT_BULK 2 ///< Bulk Endpoint +#define ARM_USB_ENDPOINT_INTERRUPT 3 ///< Interrupt Endpoint + +/* USB Endpoint Maximum Packet Size (wMaxPacketSize) */ +#define ARM_USB_ENDPOINT_MAX_PACKET_SIZE_MASK 0x07FF +#define ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_MASK 0x1800 +#define ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_1 0x0000 +#define ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_2 0x0800 +#define ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_3 0x1000 + +#endif /* __DRIVER_USB_H */ diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_USBD.h b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_USBD.h new file mode 100644 index 000000000..c470bb57b --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_USBD.h @@ -0,0 +1,263 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2014 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * + * $Date: 3. Jun 2014 + * $Revision: V2.01 + * + * Project: USB Device Driver definitions + * -------------------------------------------------------------------------- */ + +/* History: + * Version 2.01 + * Added ARM_USBD_ReadSetupPacket function + * Version 2.00 + * Removed ARM_USBD_DeviceConfigure function + * Removed ARM_USBD_SET_ADDRESS_STAGE parameter from ARM_USBD_DeviceSetAddress function + * Removed ARM_USBD_EndpointReadStart function + * Replaced ARM_USBD_EndpointRead and ARM_USBD_EndpointWrite functions with ARM_USBD_EndpointTransfer + * Added ARM_USBD_EndpointTransferGetResult function + * Renamed ARM_USBD_EndpointAbort function to ARM_USBD_EndpointTransferAbort + * Changed prefix ARM_DRV -> ARM_DRIVER + * Changed return values of some functions to int32_t + * Version 1.10 + * Namespace prefix ARM_ added + * Version 1.00 + * Initial release + */ + +#ifndef __DRIVER_USBD_H +#define __DRIVER_USBD_H + +#include "Driver_USB.h" + +#define ARM_USBD_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,01) /* API version */ + + +/** +\brief USB Device State +*/ +typedef struct _ARM_USBD_STATE { + uint32_t vbus : 1; ///< USB Device VBUS flag + uint32_t speed : 2; ///< USB Device speed setting (ARM_USB_SPEED_xxx) + uint32_t active : 1; ///< USB Device active flag +} ARM_USBD_STATE; + + +/****** USB Device Event *****/ +#define ARM_USBD_EVENT_VBUS_ON (1UL << 0) ///< USB Device VBUS On +#define ARM_USBD_EVENT_VBUS_OFF (1UL << 1) ///< USB Device VBUS Off +#define ARM_USBD_EVENT_RESET (1UL << 2) ///< USB Reset occurred +#define ARM_USBD_EVENT_HIGH_SPEED (1UL << 3) ///< USB switch to High Speed occurred +#define ARM_USBD_EVENT_SUSPEND (1UL << 4) ///< USB Suspend occurred +#define ARM_USBD_EVENT_RESUME (1UL << 5) ///< USB Resume occurred + +/****** USB Endpoint Event *****/ +#define ARM_USBD_EVENT_SETUP (1UL << 0) ///< SETUP Packet +#define ARM_USBD_EVENT_OUT (1UL << 1) ///< OUT Packet(s) +#define ARM_USBD_EVENT_IN (1UL << 2) ///< IN Packet(s) + + +#ifndef __DOXYGEN_MW__ // exclude from middleware documentation + +// Function documentation +/** + \fn ARM_DRIVER_VERSION ARM_USBD_GetVersion (void) + \brief Get driver version. + \return \ref ARM_DRIVER_VERSION +*/ +/** + \fn ARM_USBD_CAPABILITIES ARM_USBD_GetCapabilities (void) + \brief Get driver capabilities. + \return \ref ARM_USBD_CAPABILITIES +*/ +/** + \fn int32_t ARM_USBD_Initialize (ARM_USBD_SignalDeviceEvent_t cb_device_event, + ARM_USBD_SignalEndpointEvent_t cb_endpoint_event) + \brief Initialize USB Device Interface. + \param[in] cb_device_event Pointer to \ref ARM_USBD_SignalDeviceEvent + \param[in] cb_endpoint_event Pointer to \ref ARM_USBD_SignalEndpointEvent + \return \ref execution_status +*/ +/** + \fn int32_t ARM_USBD_Uninitialize (void) + \brief De-initialize USB Device Interface. + \return \ref execution_status +*/ +/** + \fn int32_t ARM_USBD_PowerControl (ARM_POWER_STATE state) + \brief Control USB Device Interface Power. + \param[in] state Power state + \return \ref execution_status +*/ +/** + \fn int32_t ARM_USBD_DeviceConnect (void) + \brief Connect USB Device. + \return \ref execution_status +*/ +/** + \fn int32_t ARM_USBD_DeviceDisconnect (void) + \brief Disconnect USB Device. + \return \ref execution_status +*/ +/** + \fn ARM_USBD_STATE ARM_USBD_DeviceGetState (void) + \brief Get current USB Device State. + \return Device State \ref ARM_USBD_STATE +*/ +/** + \fn int32_t ARM_USBD_DeviceRemoteWakeup (void) + \brief Trigger USB Remote Wakeup. + \return \ref execution_status +*/ +/** + \fn int32_t ARM_USBD_DeviceSetAddress (uint8_t dev_addr) + \brief Set USB Device Address. + \param[in] dev_addr Device Address + \return \ref execution_status +*/ +/** + \fn int32_t ARM_USBD_ReadSetupPacket (uint8_t *setup) + \brief Read setup packet received over Control Endpoint. + \param[out] setup Pointer to buffer for setup packet + \return \ref execution_status +*/ +/** + \fn int32_t ARM_USBD_EndpointConfigure (uint8_t ep_addr, + uint8_t ep_type, + uint16_t ep_max_packet_size) + \brief Configure USB Endpoint. + \param[in] ep_addr Endpoint Address + - ep_addr.0..3: Address + - ep_addr.7: Direction + \param[in] ep_type Endpoint Type (ARM_USB_ENDPOINT_xxx) + \param[in] ep_max_packet_size Endpoint Maximum Packet Size + \return \ref execution_status +*/ +/** + \fn int32_t ARM_USBD_EndpointUnconfigure (uint8_t ep_addr) + \brief Unconfigure USB Endpoint. + \param[in] ep_addr Endpoint Address + - ep_addr.0..3: Address + - ep_addr.7: Direction + \return \ref execution_status +*/ +/** + \fn int32_t ARM_USBD_EndpointStall (uint8_t ep_addr, bool stall) + \brief Set/Clear Stall for USB Endpoint. + \param[in] ep_addr Endpoint Address + - ep_addr.0..3: Address + - ep_addr.7: Direction + \param[in] stall Operation + - \b false Clear + - \b true Set + \return \ref execution_status +*/ +/** + \fn int32_t ARM_USBD_EndpointTransfer (uint8_t ep_addr, uint8_t *data, uint32_t num) + \brief Read data from or Write data to USB Endpoint. + \param[in] ep_addr Endpoint Address + - ep_addr.0..3: Address + - ep_addr.7: Direction + \param[out] data Pointer to buffer for data to read or with data to write + \param[in] num Number of data bytes to transfer + \return \ref execution_status +*/ +/** + \fn uint32_t ARM_USBD_EndpointTransferGetResult (uint8_t ep_addr) + \brief Get result of USB Endpoint transfer. + \param[in] ep_addr Endpoint Address + - ep_addr.0..3: Address + - ep_addr.7: Direction + \return number of successfully transferred data bytes +*/ +/** + \fn int32_t ARM_USBD_EndpointTransferAbort (uint8_t ep_addr) + \brief Abort current USB Endpoint transfer. + \param[in] ep_addr Endpoint Address + - ep_addr.0..3: Address + - ep_addr.7: Direction + \return \ref execution_status +*/ +/** + \fn uint16_t ARM_USBD_GetFrameNumber (void) + \brief Get current USB Frame Number. + \return Frame Number +*/ + +/** + \fn void ARM_USBD_SignalDeviceEvent (uint32_t event) + \brief Signal USB Device Event. + \param[in] event \ref USBD_dev_events + \return none +*/ +/** + \fn void ARM_USBD_SignalEndpointEvent (uint8_t ep_addr, uint32_t event) + \brief Signal USB Endpoint Event. + \param[in] ep_addr Endpoint Address + - ep_addr.0..3: Address + - ep_addr.7: Direction + \param[in] event \ref USBD_ep_events + \return none +*/ + +typedef void (*ARM_USBD_SignalDeviceEvent_t) (uint32_t event); ///< Pointer to \ref ARM_USBD_SignalDeviceEvent : Signal USB Device Event. +typedef void (*ARM_USBD_SignalEndpointEvent_t) (uint8_t ep_addr, uint32_t event); ///< Pointer to \ref ARM_USBD_SignalEndpointEvent : Signal USB Endpoint Event. + + +/** +\brief USB Device Driver Capabilities. +*/ +typedef struct _ARM_USBD_CAPABILITIES { + uint32_t vbus_detection : 1; ///< VBUS detection + uint32_t event_vbus_on : 1; ///< Signal VBUS On event + uint32_t event_vbus_off : 1; ///< Signal VBUS Off event +} ARM_USBD_CAPABILITIES; + + +/** +\brief Access structure of the USB Device Driver. +*/ +typedef struct _ARM_DRIVER_USBD { + ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_USBD_GetVersion : Get driver version. + ARM_USBD_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_USBD_GetCapabilities : Get driver capabilities. + int32_t (*Initialize) (ARM_USBD_SignalDeviceEvent_t cb_device_event, + ARM_USBD_SignalEndpointEvent_t cb_endpoint_event); ///< Pointer to \ref ARM_USBD_Initialize : Initialize USB Device Interface. + int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_USBD_Uninitialize : De-initialize USB Device Interface. + int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_USBD_PowerControl : Control USB Device Interface Power. + int32_t (*DeviceConnect) (void); ///< Pointer to \ref ARM_USBD_DeviceConnect : Connect USB Device. + int32_t (*DeviceDisconnect) (void); ///< Pointer to \ref ARM_USBD_DeviceDisconnect : Disconnect USB Device. + ARM_USBD_STATE (*DeviceGetState) (void); ///< Pointer to \ref ARM_USBD_DeviceGetState : Get current USB Device State. + int32_t (*DeviceRemoteWakeup) (void); ///< Pointer to \ref ARM_USBD_DeviceRemoteWakeup : Trigger USB Remote Wakeup. + int32_t (*DeviceSetAddress) (uint8_t dev_addr); ///< Pointer to \ref ARM_USBD_DeviceSetAddress : Set USB Device Address. + int32_t (*ReadSetupPacket) (uint8_t *setup); ///< Pointer to \ref ARM_USBD_ReadSetupPacket : Read setup packet received over Control Endpoint. + int32_t (*EndpointConfigure) (uint8_t ep_addr, + uint8_t ep_type, + uint16_t ep_max_packet_size); ///< Pointer to \ref ARM_USBD_EndpointConfigure : Configure USB Endpoint. + int32_t (*EndpointUnconfigure) (uint8_t ep_addr); ///< Pointer to \ref ARM_USBD_EndpointUnconfigure : Unconfigure USB Endpoint. + int32_t (*EndpointStall) (uint8_t ep_addr, bool stall); ///< Pointer to \ref ARM_USBD_EndpointStall : Set/Clear Stall for USB Endpoint. + int32_t (*EndpointTransfer) (uint8_t ep_addr, uint8_t *data, uint32_t num); ///< Pointer to \ref ARM_USBD_EndpointTransfer : Read data from or Write data to USB Endpoint. + uint32_t (*EndpointTransferGetResult) (uint8_t ep_addr); ///< Pointer to \ref ARM_USBD_EndpointTransferGetResult : Get result of USB Endpoint transfer. + int32_t (*EndpointTransferAbort) (uint8_t ep_addr); ///< Pointer to \ref ARM_USBD_EndpointTransferAbort : Abort current USB Endpoint transfer. + uint16_t (*GetFrameNumber) (void); ///< Pointer to \ref ARM_USBD_GetFrameNumber : Get current USB Frame Number. +} const ARM_DRIVER_USBD; + +#endif /* __DOXYGEN_MW__ */ + +#endif /* __DRIVER_USBD_H */ diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_USBH.h b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_USBH.h new file mode 100644 index 000000000..4e02d8c54 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_USBH.h @@ -0,0 +1,406 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2014 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * + * $Date: 3. September 2014 + * $Revision: V2.01 + * + * Project: USB Host Driver definitions + * -------------------------------------------------------------------------- */ + +/* History: + * Version 2.01 + * Renamed structure ARM_USBH_EP_HANDLE to ARM_USBH_PIPE_HANDLE + * Renamed functions ARM_USBH_Endpoint... to ARM_USBH_Pipe... + * Renamed function ARM_USBH_SignalEndpointEvent to ARM_USBH_SignalPipeEvent + * Version 2.00 + * Replaced function ARM_USBH_PortPowerOnOff with ARM_USBH_PortVbusOnOff + * Changed function ARM_USBH_EndpointCreate parameters + * Replaced function ARM_USBH_EndpointConfigure with ARM_USBH_EndpointModify + * Replaced function ARM_USBH_EndpointClearHalt with ARM_USBH_EndpointReset + * Replaced function ARM_USBH_URB_Submit with ARM_USBH_EndpointTransfer + * Replaced function ARM_USBH_URB_Abort with ARM_USBH_EndpointTransferAbort + * Added function ARM_USBH_EndpointTransferGetResult + * Added function ARM_USBH_GetFrameNumber + * Changed prefix ARM_DRV -> ARM_DRIVER + * Version 1.20 + * Added API for OHCI/EHCI Host Controller Interface (HCI) + * Version 1.10 + * Namespace prefix ARM_ added + * Version 1.00 + * Initial release + */ + +#ifndef __DRIVER_USBH_H +#define __DRIVER_USBH_H + +#include "Driver_USB.h" + +#define ARM_USBH_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,01) /* API version */ + + +/** +\brief USB Host Port State +*/ +typedef struct _ARM_USBH_PORT_STATE { + uint32_t connected : 1; ///< USB Host Port connected flag + uint32_t overcurrent : 1; ///< USB Host Port overcurrent flag + uint32_t speed : 2; ///< USB Host Port speed setting (ARM_USB_SPEED_xxx) +} ARM_USBH_PORT_STATE; + +/** +\brief USB Host Pipe Handle +*/ +typedef uint32_t ARM_USBH_PIPE_HANDLE; +#define ARM_USBH_EP_HANDLE ARM_USBH_PIPE_HANDLE /* Legacy name */ + + +/****** USB Host Packet Information *****/ +#define ARM_USBH_PACKET_TOKEN_Pos 0 +#define ARM_USBH_PACKET_TOKEN_Msk (0x0FUL << ARM_USBH_PACKET_TOKEN_Pos) +#define ARM_USBH_PACKET_SETUP (0x01UL << ARM_USBH_PACKET_TOKEN_Pos) ///< SETUP Packet +#define ARM_USBH_PACKET_OUT (0x02UL << ARM_USBH_PACKET_TOKEN_Pos) ///< OUT Packet +#define ARM_USBH_PACKET_IN (0x03UL << ARM_USBH_PACKET_TOKEN_Pos) ///< IN Packet +#define ARM_USBH_PACKET_PING (0x04UL << ARM_USBH_PACKET_TOKEN_Pos) ///< PING Packet + +#define ARM_USBH_PACKET_DATA_Pos 4 +#define ARM_USBH_PACKET_DATA_Msk (0x0FUL << ARM_USBH_PACKET_DATA_Pos) +#define ARM_USBH_PACKET_DATA0 (0x01UL << ARM_USBH_PACKET_DATA_Pos) ///< DATA0 PID +#define ARM_USBH_PACKET_DATA1 (0x02UL << ARM_USBH_PACKET_DATA_Pos) ///< DATA1 PID + +#define ARM_USBH_PACKET_SPLIT_Pos 8 +#define ARM_USBH_PACKET_SPLIT_Msk (0x0FUL << ARM_USBH_PACKET_SPLIT_Pos) +#define ARM_USBH_PACKET_SSPLIT (0x08UL << ARM_USBH_PACKET_SPLIT_Pos) ///< SSPLIT Packet +#define ARM_USBH_PACKET_SSPLIT_S (0x09UL << ARM_USBH_PACKET_SPLIT_Pos) ///< SSPLIT Packet: Data Start +#define ARM_USBH_PACKET_SSPLIT_E (0x0AUL << ARM_USBH_PACKET_SPLIT_Pos) ///< SSPLIT Packet: Data End +#define ARM_USBH_PACKET_SSPLIT_S_E (0x0BUL << ARM_USBH_PACKET_SPLIT_Pos) ///< SSPLIT Packet: Data All +#define ARM_USBH_PACKET_CSPLIT (0x0CUL << ARM_USBH_PACKET_SPLIT_Pos) ///< CSPLIT Packet + +#define ARM_USBH_PACKET_PRE (1UL << 12) ///< PRE Token + + +/****** USB Host Port Event *****/ +#define ARM_USBH_EVENT_CONNECT (1UL << 0) ///< USB Device Connected to Port +#define ARM_USBH_EVENT_DISCONNECT (1UL << 1) ///< USB Device Disconnected from Port +#define ARM_USBH_EVENT_OVERCURRENT (1UL << 2) ///< USB Device caused Overcurrent +#define ARM_USBH_EVENT_RESET (1UL << 3) ///< USB Reset completed +#define ARM_USBH_EVENT_SUSPEND (1UL << 4) ///< USB Suspend occurred +#define ARM_USBH_EVENT_RESUME (1UL << 5) ///< USB Resume occurred +#define ARM_USBH_EVENT_REMOTE_WAKEUP (1UL << 6) ///< USB Device activated Remote Wakeup + +/****** USB Host Pipe Event *****/ +#define ARM_USBH_EVENT_TRANSFER_COMPLETE (1UL << 0) ///< Transfer completed +#define ARM_USBH_EVENT_HANDSHAKE_NAK (1UL << 1) ///< NAK Handshake received +#define ARM_USBH_EVENT_HANDSHAKE_NYET (1UL << 2) ///< NYET Handshake received +#define ARM_USBH_EVENT_HANDSHAKE_MDATA (1UL << 3) ///< MDATA Handshake received +#define ARM_USBH_EVENT_HANDSHAKE_STALL (1UL << 4) ///< STALL Handshake received +#define ARM_USBH_EVENT_HANDSHAKE_ERR (1UL << 5) ///< ERR Handshake received +#define ARM_USBH_EVENT_BUS_ERROR (1UL << 6) ///< Bus Error detected + + +#ifndef __DOXYGEN_MW__ // exclude from middleware documentation + +// Function documentation +/** + \fn ARM_DRIVER_VERSION ARM_USBH_GetVersion (void) + \brief Get driver version. + \return \ref ARM_DRIVER_VERSION +*/ +/** + \fn ARM_USBH_CAPABILITIES ARM_USBH_GetCapabilities (void) + \brief Get driver capabilities. + \return \ref ARM_USBH_CAPABILITIES +*/ +/** + \fn int32_t ARM_USBH_Initialize (ARM_USBH_SignalPortEvent_t cb_port_event, + ARM_USBH_SignalPipeEvent_t cb_pipe_event) + \brief Initialize USB Host Interface. + \param[in] cb_port_event Pointer to \ref ARM_USBH_SignalPortEvent + \param[in] cb_pipe_event Pointer to \ref ARM_USBH_SignalPipeEvent + \return \ref execution_status +*/ +/** + \fn int32_t ARM_USBH_Uninitialize (void) + \brief De-initialize USB Host Interface. + \return \ref execution_status +*/ +/** + \fn int32_t ARM_USBH_PowerControl (ARM_POWER_STATE state) + \brief Control USB Host Interface Power. + \param[in] state Power state + \return \ref execution_status +*/ +/** + \fn int32_t ARM_USBH_PortVbusOnOff (uint8_t port, bool vbus) + \brief Root HUB Port VBUS on/off. + \param[in] port Root HUB Port Number + \param[in] vbus + - \b false VBUS off + - \b true VBUS on + \return \ref execution_status +*/ +/** + \fn int32_t ARM_USBH_PortReset (uint8_t port) + \brief Do Root HUB Port Reset. + \param[in] port Root HUB Port Number + \return \ref execution_status +*/ +/** + \fn int32_t ARM_USBH_PortSuspend (uint8_t port) + \brief Suspend Root HUB Port (stop generating SOFs). + \param[in] port Root HUB Port Number + \return \ref execution_status +*/ +/** + \fn int32_t ARM_USBH_PortResume (uint8_t port) + \brief Resume Root HUB Port (start generating SOFs). + \param[in] port Root HUB Port Number + \return \ref execution_status +*/ +/** + \fn ARM_USBH_PORT_STATE ARM_USBH_PortGetState (uint8_t port) + \brief Get current Root HUB Port State. + \param[in] port Root HUB Port Number + \return Port State \ref ARM_USBH_PORT_STATE +*/ +/** + \fn ARM_USBH_PIPE_HANDLE ARM_USBH_PipeCreate (uint8_t dev_addr, + uint8_t dev_speed, + uint8_t hub_addr, + uint8_t hub_port, + uint8_t ep_addr, + uint8_t ep_type, + uint16_t ep_max_packet_size, + uint8_t ep_interval) + \brief Create Pipe in System. + \param[in] dev_addr Device Address + \param[in] dev_speed Device Speed + \param[in] hub_addr Hub Address + \param[in] hub_port Hub Port + \param[in] ep_addr Endpoint Address + - ep_addr.0..3: Address + - ep_addr.7: Direction + \param[in] ep_type Endpoint Type (ARM_USB_ENDPOINT_xxx) + \param[in] ep_max_packet_size Endpoint Maximum Packet Size + \param[in] ep_interval Endpoint Polling Interval + \return Pipe Handle \ref ARM_USBH_PIPE_HANDLE +*/ +/** + \fn int32_t ARM_USBH_PipeModify (ARM_USBH_PIPE_HANDLE pipe_hndl, + uint8_t dev_addr, + uint8_t dev_speed, + uint8_t hub_addr, + uint8_t hub_port, + uint16_t ep_max_packet_size) + \brief Modify Pipe in System. + \param[in] pipe_hndl Pipe Handle + \param[in] dev_addr Device Address + \param[in] dev_speed Device Speed + \param[in] hub_addr Hub Address + \param[in] hub_port Hub Port + \param[in] ep_max_packet_size Endpoint Maximum Packet Size + \return \ref execution_status +*/ +/** + \fn int32_t ARM_USBH_PipeDelete (ARM_USBH_PIPE_HANDLE pipe_hndl) + \brief Delete Pipe from System. + \param[in] pipe_hndl Pipe Handle + \return \ref execution_status +*/ +/** + \fn int32_t ARM_USBH_PipeReset (ARM_USBH_PIPE_HANDLE pipe_hndl) + \brief Reset Pipe. + \param[in] pipe_hndl Pipe Handle + \return \ref execution_status +*/ +/** + \fn int32_t ARM_USBH_PipeTransfer (ARM_USBH_PIPE_HANDLE pipe_hndl, + uint32_t packet, + uint8_t *data, + uint32_t num) + \brief Transfer packets through USB Pipe. + \param[in] pipe_hndl Pipe Handle + \param[in] packet Packet information + \param[in] data Pointer to buffer with data to send or for data to receive + \param[in] num Number of data bytes to transfer + \return \ref execution_status +*/ +/** + \fn uint32_t ARM_USBH_PipeTransferGetResult (ARM_USBH_PIPE_HANDLE pipe_hndl) + \brief Get result of USB Pipe transfer. + \param[in] pipe_hndl Pipe Handle + \return number of successfully transferred data bytes +*/ +/** + \fn int32_t ARM_USBH_PipeTransferAbort (ARM_USBH_PIPE_HANDLE pipe_hndl) + \brief Abort current USB Pipe transfer. + \param[in] pipe_hndl Pipe Handle + \return \ref execution_status +*/ +/** + \fn uint16_t ARM_USBH_GetFrameNumber (void) + \brief Get current USB Frame Number. + \return Frame Number +*/ + +/** + \fn void ARM_USBH_SignalPortEvent (uint8_t port, uint32_t event) + \brief Signal Root HUB Port Event. + \param[in] port Root HUB Port Number + \param[in] event \ref USBH_port_events + \return none +*/ +/** + \fn void ARM_USBH_SignalPipeEvent (ARM_USBH_PIPE_HANDLE pipe_hndl, uint32_t event) + \brief Signal Pipe Event. + \param[in] pipe_hndl Pipe Handle + \param[in] event \ref USBH_pipe_events + \return none +*/ + +typedef void (*ARM_USBH_SignalPortEvent_t) (uint8_t port, uint32_t event); ///< Pointer to \ref ARM_USBH_SignalPortEvent : Signal Root HUB Port Event. +typedef void (*ARM_USBH_SignalPipeEvent_t) (ARM_USBH_PIPE_HANDLE pipe_hndl, uint32_t event); ///< Pointer to \ref ARM_USBH_SignalPipeEvent : Signal Pipe Event. +#define ARM_USBH_SignalEndpointEvent_t ARM_USBH_SignalPipeEvent_t /* Legacy name */ + + +/** +\brief USB Host Driver Capabilities. +*/ +typedef struct _ARM_USBH_CAPABILITIES { + uint32_t port_mask : 15; ///< Root HUB available Ports Mask + uint32_t auto_split : 1; ///< Automatic SPLIT packet handling + uint32_t event_connect : 1; ///< Signal Connect event + uint32_t event_disconnect : 1; ///< Signal Disconnect event + uint32_t event_overcurrent : 1; ///< Signal Overcurrent event +} ARM_USBH_CAPABILITIES; + + +/** +\brief Access structure of USB Host Driver. +*/ +typedef struct _ARM_DRIVER_USBH { + ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_USBH_GetVersion : Get driver version. + ARM_USBH_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_USBH_GetCapabilities : Get driver capabilities. + int32_t (*Initialize) (ARM_USBH_SignalPortEvent_t cb_port_event, + ARM_USBH_SignalPipeEvent_t cb_pipe_event); ///< Pointer to \ref ARM_USBH_Initialize : Initialize USB Host Interface. + int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_USBH_Uninitialize : De-initialize USB Host Interface. + int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_USBH_PowerControl : Control USB Host Interface Power. + int32_t (*PortVbusOnOff) (uint8_t port, bool vbus); ///< Pointer to \ref ARM_USBH_PortVbusOnOff : Root HUB Port VBUS on/off. + int32_t (*PortReset) (uint8_t port); ///< Pointer to \ref ARM_USBH_PortReset : Do Root HUB Port Reset. + int32_t (*PortSuspend) (uint8_t port); ///< Pointer to \ref ARM_USBH_PortSuspend : Suspend Root HUB Port (stop generating SOFs). + int32_t (*PortResume) (uint8_t port); ///< Pointer to \ref ARM_USBH_PortResume : Resume Root HUB Port (start generating SOFs). + ARM_USBH_PORT_STATE (*PortGetState) (uint8_t port); ///< Pointer to \ref ARM_USBH_PortGetState : Get current Root HUB Port State. + ARM_USBH_PIPE_HANDLE (*PipeCreate) (uint8_t dev_addr, + uint8_t dev_speed, + uint8_t hub_addr, + uint8_t hub_port, + uint8_t ep_addr, + uint8_t ep_type, + uint16_t ep_max_packet_size, + uint8_t ep_interval); ///< Pointer to \ref ARM_USBH_PipeCreate : Create Pipe in System. + int32_t (*PipeModify) (ARM_USBH_PIPE_HANDLE pipe_hndl, + uint8_t dev_addr, + uint8_t dev_speed, + uint8_t hub_addr, + uint8_t hub_port, + uint16_t ep_max_packet_size); ///< Pointer to \ref ARM_USBH_PipeModify : Modify Pipe in System. + int32_t (*PipeDelete) (ARM_USBH_PIPE_HANDLE pipe_hndl); ///< Pointer to \ref ARM_USBH_PipeDelete : Delete Pipe from System. + int32_t (*PipeReset) (ARM_USBH_PIPE_HANDLE pipe_hndl); ///< Pointer to \ref ARM_USBH_PipeReset : Reset Pipe. + int32_t (*PipeTransfer) (ARM_USBH_PIPE_HANDLE pipe_hndl, + uint32_t packet, + uint8_t *data, + uint32_t num); ///< Pointer to \ref ARM_USBH_PipeTransfer : Transfer packets through USB Pipe. + uint32_t (*PipeTransferGetResult) (ARM_USBH_PIPE_HANDLE pipe_hndl); ///< Pointer to \ref ARM_USBH_PipeTransferGetResult : Get result of USB Pipe transfer. + int32_t (*PipeTransferAbort) (ARM_USBH_PIPE_HANDLE pipe_hndl); ///< Pointer to \ref ARM_USBH_PipeTransferAbort : Abort current USB Pipe transfer. + uint16_t (*GetFrameNumber) (void); ///< Pointer to \ref ARM_USBH_GetFrameNumber : Get current USB Frame Number. +} const ARM_DRIVER_USBH; + + +// HCI (OHCI/EHCI) + +// Function documentation +/** + \fn ARM_DRIVER_VERSION ARM_USBH_HCI_GetVersion (void) + \brief Get USB Host HCI (OHCI/EHCI) driver version. + \return \ref ARM_DRIVER_VERSION +*/ +/** + \fn ARM_USBH_HCI_CAPABILITIES ARM_USBH_HCI_GetCapabilities (void) + \brief Get driver capabilities. + \return \ref ARM_USBH_HCI_CAPABILITIES +*/ +/** + \fn int32_t ARM_USBH_HCI_Initialize (ARM_USBH_HCI_Interrupt_t *cb_interrupt) + \brief Initialize USB Host HCI (OHCI/EHCI) Interface. + \param[in] cb_interrupt Pointer to Interrupt Handler Routine + \return \ref execution_status +*/ +/** + \fn int32_t ARM_USBH_HCI_Uninitialize (void) + \brief De-initialize USB Host HCI (OHCI/EHCI) Interface. + \return \ref execution_status +*/ +/** + \fn int32_t ARM_USBH_HCI_PowerControl (ARM_POWER_STATE state) + \brief Control USB Host HCI (OHCI/EHCI) Interface Power. + \param[in] state Power state + \return \ref execution_status +*/ +/** + \fn int32_t ARM_USBH_HCI_PortVbusOnOff (uint8_t port, bool vbus) + \brief USB Host HCI (OHCI/EHCI) Root HUB Port VBUS on/off. + \param[in] port Root HUB Port Number + \param[in] vbus + - \b false VBUS off + - \b true VBUS on + \return \ref execution_status +*/ + +/** + \fn void ARM_USBH_HCI_Interrupt (void) + \brief USB Host HCI Interrupt Handler. + \return none +*/ + +typedef void (*ARM_USBH_HCI_Interrupt_t) (void); ///< Pointer to Interrupt Handler Routine. + + +/** +\brief USB Host HCI (OHCI/EHCI) Driver Capabilities. +*/ +typedef struct _ARM_USBH_HCI_CAPABILITIES { + uint32_t port_mask : 15; ///< Root HUB available Ports Mask +} ARM_USBH_HCI_CAPABILITIES; + + +/** + \brief Access structure of USB Host HCI (OHCI/EHCI) Driver. +*/ +typedef struct _ARM_DRIVER_USBH_HCI { + ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_USBH_HCI_GetVersion : Get USB Host HCI (OHCI/EHCI) driver version. + ARM_USBH_HCI_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_USBH_HCI_GetCapabilities : Get driver capabilities. + int32_t (*Initialize) (ARM_USBH_HCI_Interrupt_t cb_interrupt); ///< Pointer to \ref ARM_USBH_HCI_Initialize : Initialize USB Host HCI (OHCI/EHCI) Interface. + int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_USBH_HCI_Uninitialize : De-initialize USB Host HCI (OHCI/EHCI) Interface. + int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_USBH_HCI_PowerControl : Control USB Host HCI (OHCI/EHCI) Interface Power. + int32_t (*PortVbusOnOff) (uint8_t port, bool vbus); ///< Pointer to \ref ARM_USBH_HCI_PortVbusOnOff : USB Host HCI (OHCI/EHCI) Root HUB Port VBUS on/off. +} const ARM_DRIVER_USBH_HCI; + +#endif /* __DOXYGEN_MW__ */ + +#endif /* __DRIVER_USBH_H */ diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/component/cmsis_can_driver.slcc b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/component/cmsis_can_driver.slcc new file mode 100644 index 000000000..d84d60526 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/component/cmsis_can_driver.slcc @@ -0,0 +1,16 @@ +id: cmsis_can_driver +label: CMSIS CAN DRIVER +package: platform +description: > + CMSIS CAN Driver include path +category: Device|Si91x|MCU|Internal|CMSIS Drivers +quality: production +ui_hints: + visibility: never +component_root_path: "components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver" +include: + - path: "Include" + file_list: + - path: "Driver_CAN.h" +provides: + - name: cmsis_can_driver \ No newline at end of file diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/component/cmsis_eth_driver.slcc b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/component/cmsis_eth_driver.slcc new file mode 100644 index 000000000..0c4fc0a12 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/component/cmsis_eth_driver.slcc @@ -0,0 +1,16 @@ +id: cmsis_eth_driver +label: CMSIS ETH DRIVER +package: platform +description: > + CMSIS ETH Driver include path +category: Device|Si91x|MCU|Internal|CMSIS Drivers +quality: production +ui_hints: + visibility: never +component_root_path: "components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver" +include: + - path: "Include" + file_list: + - path: "Driver_ETH.h" +provides: + - name: cmsis_eth_driver \ No newline at end of file diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/component/cmsis_eth_mac_driver.slcc b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/component/cmsis_eth_mac_driver.slcc new file mode 100644 index 000000000..de5ce6a44 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/component/cmsis_eth_mac_driver.slcc @@ -0,0 +1,16 @@ +id: cmsis_eth_mac_driver +label: CMSIS ETH MAC DRIVER +package: platform +description: > + CMSIS ETH MAC Driver include path +category: Device|Si91x|MCU|Internal|CMSIS Drivers +quality: production +ui_hints: + visibility: never +component_root_path: "components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver" +include: + - path: "Include" + file_list: + - path: "Driver_ETH_MAC.h" +provides: + - name: cmsis_eth_mac_driver \ No newline at end of file diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/component/cmsis_eth_phy_driver.slcc b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/component/cmsis_eth_phy_driver.slcc new file mode 100644 index 000000000..7465db3bc --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/component/cmsis_eth_phy_driver.slcc @@ -0,0 +1,16 @@ +id: cmsis_eth_phy_driver +label: CMSIS ETH PHY DRIVER +package: platform +description: > + CMSIS ETH PHY Driver include path +category: Device|Si91x|MCU|Internal|CMSIS Drivers +quality: production +ui_hints: + visibility: never +component_root_path: "components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver" +include: + - path: "Include" + file_list: + - path: "Driver_ETH_PHY.h" +provides: + - name: cmsis_eth_phy_driver \ No newline at end of file diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/component/cmsis_mci_driver.slcc b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/component/cmsis_mci_driver.slcc new file mode 100644 index 000000000..d39861fd6 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/component/cmsis_mci_driver.slcc @@ -0,0 +1,16 @@ +id: cmsis_mci_driver +label: CMSIS MCI DRIVER +package: platform +description: > + CMSIS MCI Driver include path +category: Device|Si91x|MCU|Internal|CMSIS Drivers +quality: production +ui_hints: + visibility: never +component_root_path: "components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver" +include: + - path: "Include" + file_list: + - path: "Driver_MCI.h" +provides: + - name: cmsis_mci_driver \ No newline at end of file diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/component/cmsis_nand_driver.slcc b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/component/cmsis_nand_driver.slcc new file mode 100644 index 000000000..ba5df4110 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/component/cmsis_nand_driver.slcc @@ -0,0 +1,16 @@ +id: cmsis_nand_driver +label: CMSIS NAND DRIVER +package: platform +description: > + CMSIS NAND Driver include path +category: Device|Si91x|MCU|Internal|CMSIS Drivers +quality: production +ui_hints: + visibility: never +component_root_path: "components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver" +include: + - path: "Include" + file_list: + - path: "Driver_NAND.h" +provides: + - name: cmsis_nand_driver \ No newline at end of file diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/component/cmsis_usb_driver.slcc b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/component/cmsis_usb_driver.slcc new file mode 100644 index 000000000..bcad1b8f0 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/component/cmsis_usb_driver.slcc @@ -0,0 +1,16 @@ +id: cmsis_usb_driver +label: CMSIS USB DRIVER +package: platform +description: > + CMSIS USB Driver include path +category: Device|Si91x|MCU|Internal|CMSIS Drivers +quality: production +ui_hints: + visibility: never +component_root_path: "components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver" +include: + - path: "Include" + file_list: + - path: "Driver_USB.h" +provides: + - name: cmsis_usb_driver \ No newline at end of file diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/component/cmsis_usbd_driver.slcc b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/component/cmsis_usbd_driver.slcc new file mode 100644 index 000000000..13ddfda69 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/component/cmsis_usbd_driver.slcc @@ -0,0 +1,16 @@ +id: cmsis_usbd_driver +label: CMSIS USBD DRIVER +package: platform +description: > + CMSIS USBD Driver include path +category: Device|Si91x|MCU|Internal|CMSIS Drivers +quality: production +ui_hints: + visibility: never +component_root_path: "components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver" +include: + - path: "Include" + file_list: + - path: "Driver_USBD.h" +provides: + - name: cmsis_usbd_driver \ No newline at end of file diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/component/cmsis_usbh_driver.slcc b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/component/cmsis_usbh_driver.slcc new file mode 100644 index 000000000..92756ade4 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/component/cmsis_usbh_driver.slcc @@ -0,0 +1,16 @@ +id: cmsis_usbh_driver +label: CMSIS USBH DRIVER +package: platform +description: > + CMSIS USBH Driver include path +category: Device|Si91x|MCU|Internal|CMSIS Drivers +quality: production +ui_hints: + visibility: never +component_root_path: "components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver" +include: + - path: "Include" + file_list: + - path: "Driver_USBH.h" +provides: + - name: cmsis_usbh_driver \ No newline at end of file diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/EMAC.c b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/EMAC.c new file mode 100644 index 000000000..93f0691b0 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/EMAC.c @@ -0,0 +1,1069 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * $Date: 25. Dec 2018 + * $Revision: V1.0 + * + * Driver: Driver_ETH_MAC0 + * Configured: via RTE_Device.h configuration file + * Project: Ethernet Media Access (MAC) Driver for Silicon Labs MCU + * -------------------------------------------------------------------------- + * Use the following configuration settings in the middleware component + * to connect to this driver. + * + * Configuration Setting Value + * --------------------- ----- + * Connect to hardware via Driver_ETH_MAC# = 0 + * -------------------------------------------------------------------------- */ + +/* History: + * Version 1.0 + * Initial release + */ +#include "rsi_ccp_user_config.h" +#if defined(CHIP_9118) +/* Receive/transmit Checksum offload enable */ +#ifndef EMAC_CHECKSUM_OFFLOAD +#define EMAC_CHECKSUM_OFFLOAD 1 +#endif + +/* IEEE 1588 time stamping enable (PTP) */ +#ifndef EMAC_TIME_STAMP +#define EMAC_TIME_STAMP 0 +#endif + +#include "EMAC.h" + +#include "clock_update.h" +#include "RTE_Device.h" +#include "PHY_LAN8742A.h" +#define ARM_ETH_MAC_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0) /* driver version */ + +/* Timeouts */ +#define PHY_TIMEOUT 2U /* PHY Register access timeout in ms */ + +/* ETH Memory Buffer configuration */ +#define NUM_RX_BUF 4U /* 0x1800 for Rx (4*1536=6K) */ +#define NUM_TX_BUF 2U /* 0x0C00 for Tx (2*1536=3K) */ +#define ETH_BUF_SIZE 1536U /* ETH Receive/Transmit buffer size */ +#define CLK_BIT (*(volatile uint32_t *)0x46000000) /* ETH clock enable register*/ +#define ETH_SPEED (*(volatile uint32_t *)0x46008040) /* ETH SPEED SELECTION*/ + +/* Interrupt Handler Prototype */ +void ETH_IRQHandler (void); + + +/* DMA RX Descriptor */ +typedef struct rx_desc { + uint32_t volatile Stat; + uint32_t Ctrl; + uint8_t const *Addr; + struct rx_desc *Next; +#if ((EMAC_CHECKSUM_OFFLOAD != 0) || (EMAC_TIME_STAMP != 0)) + uint32_t ExtStat; + uint32_t Reserved[1]; + uint32_t TimeLo; + uint32_t TimeHi; +#endif +} RX_Desc; + +/* DMA TX Descriptor */ +typedef struct tx_desc { + uint32_t volatile CtrlStat; + uint32_t Size; + uint8_t const *Addr; + struct tx_desc *Next; +#if ((EMAC_CHECKSUM_OFFLOAD != 0) || (EMAC_TIME_STAMP != 0)) + uint32_t Reserved[2]; + uint32_t TimeLo; + uint32_t TimeHi; +#endif +} TX_Desc; + +/*Ethernet pin definations for RMII interface*/ +static const ETH_PIN_Config eth_pins[] = { + { RTE_ETH_RMII_TXD0_PORT , RTE_ETH_RMII_TXD0_PIN , RTE_ETH_RMII_TXD0_MODE , RTE_ETH_RMII_TXD0_PAD_SEL }, + { RTE_ETH_RMII_TXD1_PORT , RTE_ETH_RMII_TXD1_PIN , RTE_ETH_RMII_TXD1_MODE , RTE_ETH_RMII_TXD1_PAD_SEL }, + { RTE_ETH_RMII_TX_EN_PORT , RTE_ETH_RMII_TX_EN_PIN , RTE_ETH_RMII_TX_EN_MODE , RTE_ETH_RMII_TX_EN_PAD_SEL }, + { RTE_ETH_RMII_RXD0_PORT , RTE_ETH_RMII_RXD0_PIN , RTE_ETH_RMII_RXD0_MODE , RTE_ETH_RMII_RXD0_PAD_SEL }, + { RTE_ETH_RMII_RXD1_PORT , RTE_ETH_RMII_RXD1_PIN , RTE_ETH_RMII_RXD1_MODE , RTE_ETH_RMII_RXD1_PAD_SEL }, + { RTE_ETH_RMII_REF_CLK_PORT , RTE_ETH_RMII_REF_CLK_PIN , RTE_ETH_RMII_REF_CLK_MODE , RTE_ETH_RMII_REF_CLK_PAD_SEL}, + { RTE_ETH_RMII_CRS_DV_PORT , RTE_ETH_RMII_CRS_DV_PIN , RTE_ETH_RMII_CRS_DV_MODE , RTE_ETH_RMII_CRS_DV_PAD_SEL }, + { RTE_ETH_MDI_MDC_PORT , RTE_ETH_MDI_MDC_PIN , RTE_ETH_MDI_MDC_MODE , RTE_ETH_MDI_MDC_PAD_SEL }, + { RTE_ETH_MDI_MDIO_PORT , RTE_ETH_MDI_MDIO_PIN , RTE_ETH_MDI_MDIO_MODE , RTE_ETH_MDI_MDIO_PAD_SEL }, +}; + +/* Driver Version */ +static const ARM_DRIVER_VERSION DriverVersion = { + ARM_ETH_MAC_API_VERSION, + ARM_ETH_MAC_DRV_VERSION +}; + +/* Driver Capabilities */ +static const ARM_ETH_MAC_CAPABILITIES DriverCapabilities = { + (EMAC_CHECKSUM_OFFLOAD != 0) ? 1U : 0U, /* checksum_offload_rx_ip4 */ + (EMAC_CHECKSUM_OFFLOAD != 0) ? 1U : 0U, /* checksum_offload_rx_ip6 */ + (EMAC_CHECKSUM_OFFLOAD != 0) ? 1U : 0U, /* checksum_offload_rx_udp */ + (EMAC_CHECKSUM_OFFLOAD != 0) ? 1U : 0U, /* checksum_offload_rx_tcp */ + (EMAC_CHECKSUM_OFFLOAD != 0) ? 1U : 0U, /* checksum_offload_rx_icmp */ + (EMAC_CHECKSUM_OFFLOAD != 0) ? 1U : 0U, /* checksum_offload_tx_ip4 */ + (EMAC_CHECKSUM_OFFLOAD != 0) ? 1U : 0U, /* checksum_offload_tx_ip6 */ + (EMAC_CHECKSUM_OFFLOAD != 0) ? 1U : 0U, /* checksum_offload_tx_udp */ + (EMAC_CHECKSUM_OFFLOAD != 0) ? 1U : 0U, /* checksum_offload_tx_tcp */ + (EMAC_CHECKSUM_OFFLOAD != 0) ? 1U : 0U, /* checksum_offload_tx_icmp */ + (ETH_MII != 0) ? + ARM_ETH_INTERFACE_MII : + ARM_ETH_INTERFACE_RMII, /* media_interface */ + 0U, /* mac_address */ + 1U, /* event_rx_frame */ + 1U, /* event_tx_frame */ + 1U, /* event_wakeup */ + (EMAC_TIME_STAMP != 0) ? 1U : 0U /* precision_timer */ +}; + +/* Local variables */ +static EMAC_CTRL Emac; + +static RX_Desc rx_desc[NUM_RX_BUF]; +static TX_Desc tx_desc[NUM_TX_BUF]; +static uint32_t rx_buf [NUM_RX_BUF][ETH_BUF_SIZE>>2]; +static uint32_t tx_buf [NUM_TX_BUF][ETH_BUF_SIZE>>2]; + + +/** + * @fn void init_rx_desc (void) + * @brief Initialize Rx DMA descriptors. + * @return none + */ +static void init_rx_desc (void) { + uint32_t i=0,next; + + for (i = 0U; i < NUM_RX_BUF; i++) { + rx_desc[i].Stat = DMA_RX_OWN; + rx_desc[i].Ctrl = DMA_RX_RCH | ETH_BUF_SIZE ; + rx_desc[i].Addr = (uint8_t *)&rx_buf[i]; + next = i + 1U; + if (next == NUM_RX_BUF) { next = 0U; } + rx_desc[i].Next = &rx_desc[next]; + } + ETH->DMA_RX_DESC_LIST_ADDR_REG = (uint32_t)&rx_desc[0]; + Emac.rx_index = 0U; +} + +/** + * @fn void init_tx_desc (void) + * @brief Initialize Tx DMA descriptors. + * @return none + */ +static void init_tx_desc (void) { + uint32_t i,next; + + for(i=0;i < NUM_TX_BUF;i++){ + tx_desc[i].Size= DMA_TX_TCH | DMA_TX_LS | DMA_TX_FS; + tx_desc[i].Addr=(uint8_t *)&tx_buf[i]; + next = i + 1U; + if(next == NUM_TX_BUF) { next = 0U; } + tx_desc[i].Next=&tx_desc[next]; + } + ETH->DMA_TX_DESC_LIST_ADDR_REG = (uint32_t)&tx_desc[0]; + Emac.tx_index = 0U; +} + +/** + * @fn void Init(void) + * @brief MDIO iniitialization. + * @param[in] dir : 1=input,0=output. + * @return None + */ +void MDIO_Init(void) +{ + /*Enable the clock*/ + RSI_CLK_PeripheralClkEnable(M4CLK,EGPIO_CLK,ENABLE_STATIC_CLK); + /*MDC*/ + RSI_EGPIO_PadSelectionEnable(RTE_ETH_MDI_MDC_PAD_SEL); + RSI_EGPIO_PadReceiverEnable(RTE_ETH_MDI_MDC_PIN); + RSI_EGPIO_SetPinMux(EGPIO,RTE_ETH_MDI_MDC_PORT,RTE_ETH_MDI_MDC_PIN,EGPIO_PIN_MUX_MODE0); + RSI_EGPIO_SetDir(EGPIO,RTE_ETH_MDI_MDC_PORT,RTE_ETH_MDI_MDC_PIN,EGPIO_PIN_MUX_MODE0); + + /*MDIO*/ + RSI_EGPIO_PadSelectionEnable(RTE_ETH_MDI_MDIO_PAD_SEL); + RSI_EGPIO_PadReceiverEnable(RTE_ETH_MDI_MDIO_PIN); + RSI_EGPIO_SetPinMux(EGPIO,RTE_ETH_MDI_MDC_PORT,RTE_ETH_MDI_MDIO_PIN,EGPIO_PIN_MUX_MODE0); +} + +/** + * @fn void MDIO_Dir(uint8_t dir) + * @brief Set MDIO dir. + * @param[in] dir : 1=input,0=output. + * @return None + */ +void MDIO_Dir(uint8_t dir) +{ + if(dir) + { + RSI_EGPIO_SetDir(EGPIO,RTE_ETH_MDI_MDC_PORT,RTE_ETH_MDI_MDIO_PIN,EGPIO_CONFIG_DIR_INPUT); + } + else + { + RSI_EGPIO_SetDir(EGPIO,RTE_ETH_MDI_MDC_PORT,RTE_ETH_MDI_MDIO_PIN,EGPIO_CONFIG_DIR_OUTPUT); + } +} + +/** + * @fn void MDIO_Write(uint32_t data,uint32_t length) + * @brief Write's the data to phy register. + * @param[in] data : Data to be written. + * @param[in] length : Length of the data. + * @return Returns data + */ +void MDIO_Write(uint32_t data,uint32_t length) +{ + volatile int x=0; + uint32_t i; + + data = data << (32-length); + for(i=0;iport,i->pin , i->mode); + RSI_EGPIO_PadReceiverEnable(i->pin); + RSI_EGPIO_PadSelectionEnable(i->pad_sel); + } + memset (&Emac, 0, sizeof (EMAC_CTRL)); + + Emac.cb_event = cb_event; + Emac.flags = EMAC_FLAG_INIT; + return ARM_DRIVER_OK; +} + +/** + * @fn int32_t Uninitialize (void) + * @brief De-initialize Ethernet MAC Device. + * @return \ref execution_status +*/ +static int32_t Uninitialize (void) { + const ETH_PIN_Config *i; + /* Ethernet ping Unconfigure */ + for (i = eth_pins; i != ð_pins[sizeof(eth_pins)/sizeof(ETH_PIN_Config)]; i++) { + RSI_EGPIO_SetPinMux(EGPIO,i->port,i->pin , EGPIO_PIN_MUX_MODE0); + RSI_EGPIO_PadReceiverDisable(i->pin); + RSI_EGPIO_PadSelectionDisable(i->pad_sel); + } + + Emac.flags &= ~EMAC_FLAG_INIT; + + return ARM_DRIVER_OK; +} + +/** + * @fn int32_t PowerControl (ARM_POWER_STATE state) + * @brief Control Ethernet MAC Device Power. + * @param[in] state : Power state + * @return \ref execution_status +*/ +static int32_t PowerControl (ARM_POWER_STATE state) { + volatile uint32_t systemclk, clkdiv; + + switch (state) { + case ARM_POWER_OFF: + + /* Disable ethernet interrupts */ + NVIC_DisableIRQ(ETHERNET_IRQn); + ETH->DMA_INTR_EN_REG = 0U; + + Emac.flags &= ~EMAC_FLAG_POWER; + break; + + case ARM_POWER_LOW: + return ARM_DRIVER_ERROR_UNSUPPORTED; + + case ARM_POWER_FULL: + /* Clock to Ethernet peripheral */ + RSI_CLK_PeripheralClkEnable1(M4CLK , ETH_HCLK_ENABLE); + + if ((Emac.flags & EMAC_FLAG_INIT) == 0U) { + /* Driver not initialized */ + return ARM_DRIVER_ERROR; + } + if ((Emac.flags & EMAC_FLAG_POWER) != 0U) { + /* Driver already powered */ + break; + } + + /* set Software reset */ + ETH->DMA_BUS_MODE_REG |= ETH_DMABMR_SR; + while (ETH->DMA_BUS_MODE_REG & ETH_DMABMR_SR) { + ; /* Wait until software reset completed */ + } + + /* MDC clock range selection */ + + systemclk=RSI_CLK_GetBaseClock(M4_ETHERNET); + + if (systemclk >= 150000000U) { + clkdiv = ETH_MACMIIAR_CR_Div102; + } else if (systemclk >= 100000000U) { + clkdiv = ETH_MACMIIAR_CR_Div62; + } else if (systemclk >= 60000000U) { + clkdiv = ETH_MACMIIAR_CR_Div42; + } else if (systemclk >= 35000000U) { + clkdiv = ETH_MACMIIAR_CR_Div26; + } else if (systemclk >= 25000000U) { + clkdiv = ETH_MACMIIAR_CR_Div16; + } else { + /* systemclock is too slow for Ethernet */ + return (ARM_DRIVER_ERROR); + } + ETH->MAC_GMII_ADDR_REG = clkdiv; + + /* Initialize MAC configuration */ + ETH->MAC_CONFIG_REG = ETH_MACCR_DO | ETH_MACCR_PS; + + /* Initialize Filter registers */ + ETH->MAC_FRAME_FILTER_REG = ETH_MACFFR_DBF; + ETH->MAC_FLOW_CTRL_REG = ETH_MACFCR_DZPQ; + + /* Initialize Address registers */ + ETH->MAC_ADDR0_HIGH_REG = 0U; ETH->MAC_ADDR0_LOW_REG = 0U; + ETH->MAC_ADDR1_HIGH_REG = 0U; ETH->MAC_ADDR1_LOW_REG = 0U; + ETH->MAC_ADDR2_HIGH_REG = 0U; ETH->MAC_ADDR2_LOW_REG = 0U; + ETH->MAC_ADDR3_HIGH_REG = 0U; ETH->MAC_ADDR3_LOW_REG = 0U; + + /* Mask pmt interrupt */ + ETH->MAC_INTR_MASK_REG |= ETH_MACIMR_PMTIM; + + /* Initialize DMA Descriptors */ + init_rx_desc (); + init_tx_desc (); + + /* Enable Rx interrupts */ + ETH->DMA_STATUS_REG = 0xFFFFFFFFU; + ETH->DMA_INTR_EN_REG = ETH_DMAIER_NIE | ETH_DMAIER_RIE | ETH_DMAIER_TIE; + + + /* Disable MMC interrupts */ + ETH->MMC_INTR_MASK_TX_REG = ETH_MMCTIMR_TGFM | ETH_MMCTIMR_TGFSCM; + ETH->MMC_INTR_MASK_RX_REG = ETH_MMCRIMR_RFCEM; + + /*Enable ETHERNET interrupt */ + NVIC_ClearPendingIRQ (ETHERNET_IRQn); + NVIC_EnableIRQ (ETHERNET_IRQn); + + Emac.frame_end = NULL; + Emac.flags |= EMAC_FLAG_POWER; + break; + + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + return ARM_DRIVER_OK; +} + +/** + * @fn int32_t GetMacAddress (ARM_ETH_MAC_ADDR *ptr_addr) + * @brief Get Ethernet MAC Address. + * @param[in] ptr_addr : Pointer to address + * @return \ref execution_status +*/ +static int32_t GetMacAddress (ARM_ETH_MAC_ADDR *ptr_addr) { + uint32_t val; + + if (ptr_addr == NULL) { + return ARM_DRIVER_ERROR_PARAMETER; + } + + if ((Emac.flags & EMAC_FLAG_POWER) == 0U) { + return ARM_DRIVER_ERROR; + } + + val = ETH->MAC_ADDR0_HIGH_REG; + ptr_addr->b[5] = (uint8_t)(val >> 8); + ptr_addr->b[4] = (uint8_t)(val); + val = ETH->MAC_ADDR0_LOW_REG; + ptr_addr->b[3] = (uint8_t)(val >> 24); + ptr_addr->b[2] = (uint8_t)(val >> 16); + ptr_addr->b[1] = (uint8_t)(val >> 8); + ptr_addr->b[0] = (uint8_t)(val); + + return ARM_DRIVER_OK; +} + +/** + * @fn int32_t SetMacAddress (const ARM_ETH_MAC_ADDR *ptr_addr) + * @brief Set Ethernet MAC Address. + * @param[in] ptr_addr : Pointer to address + * @return \ref execution_status +*/ +static int32_t SetMacAddress (const ARM_ETH_MAC_ADDR *ptr_addr) { + + if (ptr_addr == NULL) { + return ARM_DRIVER_ERROR_PARAMETER; + } + + if ((Emac.flags & EMAC_FLAG_POWER) == 0U) { + return ARM_DRIVER_ERROR; + } + + /* Set Ethernet MAC Address registers */ + ETH->MAC_ADDR0_HIGH_REG = ((uint32_t)ptr_addr->b[5] << 8) | (uint32_t)ptr_addr->b[4]; + ETH->MAC_ADDR0_LOW_REG = ((uint32_t)ptr_addr->b[3] << 24) | ((uint32_t)ptr_addr->b[2] << 16) | + ((uint32_t)ptr_addr->b[1] << 8) | (uint32_t)ptr_addr->b[0]; + + return ARM_DRIVER_OK; +} + +/** + * @fn int32_t SetAddressFilter (const ARM_ETH_MAC_ADDR *ptr_addr, + uint32_t num_addr) + * @brief Configure Address Filter. + * @param[in] ptr_addr : Pointer to addresses + * @param[in] num_addr : Number of addresses to configure + * @return \ref execution_status +*/ +static int32_t SetAddressFilter (const ARM_ETH_MAC_ADDR *ptr_addr, uint32_t num_addr) { + uint32_t crc; + + if ((ptr_addr == NULL) && (num_addr != 0)) { + return ARM_DRIVER_ERROR_PARAMETER; + } + + if ((Emac.flags & EMAC_FLAG_POWER) == 0U) { + return ARM_DRIVER_ERROR; + } + + /* Use unicast address filtering for first 3 MAC addresses */ + ETH->MAC_FRAME_FILTER_REG &= ~(ETH_MACFFR_HPF | ETH_MACFFR_HMC); + ETH->MAC_HASH_TABLE_HIGH_REG = 0U; ETH->MAC_HASH_TABLE_LOW_REG = 0U; + + if (num_addr == 0U) { + ETH->MAC_ADDR1_HIGH_REG = 0U; ETH->MAC_ADDR1_LOW_REG = 0U; + ETH->MAC_ADDR2_HIGH_REG = 0U; ETH->MAC_ADDR2_LOW_REG = 0U; + ETH->MAC_ADDR3_HIGH_REG = 0U; ETH->MAC_ADDR3_LOW_REG = 0U; + return ARM_DRIVER_OK; + } + + ETH->MAC_ADDR1_HIGH_REG = ((uint32_t)ptr_addr->b[5] << 8) | (uint32_t)ptr_addr->b[4] | ETH_MACA1HR_AE; + ETH->MAC_ADDR1_LOW_REG = ((uint32_t)ptr_addr->b[3] << 24) | ((uint32_t)ptr_addr->b[2] << 16) | + ((uint32_t)ptr_addr->b[1] << 8) | (uint32_t)ptr_addr->b[0]; + num_addr--; + if (num_addr == 0U) { + ETH->MAC_ADDR2_HIGH_REG = 0U; ETH->MAC_ADDR2_LOW_REG = 0U; + ETH->MAC_ADDR3_HIGH_REG = 0U; ETH->MAC_ADDR3_LOW_REG = 0U; + return ARM_DRIVER_OK; + } + ptr_addr++; + + ETH->MAC_ADDR2_HIGH_REG = ((uint32_t)ptr_addr->b[5] << 8) | (uint32_t)ptr_addr->b[4] | ETH_MACA2HR_AE; + ETH->MAC_ADDR2_LOW_REG = ((uint32_t)ptr_addr->b[3] << 24) | ((uint32_t)ptr_addr->b[2] << 16) | + ((uint32_t)ptr_addr->b[1] << 8) | (uint32_t)ptr_addr->b[0]; + num_addr--; + if (num_addr == 0U) { + ETH->MAC_ADDR3_HIGH_REG = 0U; ETH->MAC_ADDR3_LOW_REG = 0U; + return ARM_DRIVER_OK; + } + ptr_addr++; + + ETH->MAC_ADDR3_HIGH_REG = ((uint32_t)ptr_addr->b[5] << 8) | (uint32_t)ptr_addr->b[4] | ETH_MACA3HR_AE; + ETH->MAC_ADDR3_LOW_REG = ((uint32_t)ptr_addr->b[3] << 24) | ((uint32_t)ptr_addr->b[2] << 16) | + ((uint32_t)ptr_addr->b[1] << 8) | (uint32_t)ptr_addr->b[0]; + num_addr--; + if (num_addr == 0U) { + return ARM_DRIVER_OK; + } + ptr_addr++; + + /* Calculate 64-bit Hash table for remaining MAC addresses */ + for ( ; num_addr; ptr_addr++, num_addr--) { + crc = crc32_data (&ptr_addr->b[0], 6U) >> 26; + if (crc & 0x20U) { + ETH->MAC_HASH_TABLE_HIGH_REG |= (1U << (crc & 0x1FU)); + } + else { + ETH->MAC_HASH_TABLE_LOW_REG |= (1U << crc); + } + } + /* Enable both, unicast and hash address filtering */ + ETH->MAC_FRAME_FILTER_REG |= ETH_MACFFR_HPF | ETH_MACFFR_HMC; + + return ARM_DRIVER_OK; +} + +/** + * @fn int32_t SendFrame (const uint8_t *frame, uint32_t len, uint32_t flags) + * @brief Send Ethernet frame. + * @param[in] frame : Pointer to frame buffer with data to send + * @param[in] len : Frame buffer length in bytes + * @param[in] flags : Frame transmit flags (see ARM_ETH_MAC_TX_FRAME_...) + * @return \ref execution_status +*/ +static int32_t SendFrame (const uint8_t *frame, uint32_t len, uint32_t flags) { + uint8_t *dst = Emac.frame_end; + uint32_t ctrl; + uint32_t dummy =0; + + if ((frame == NULL) || (len == 0U)) { + return ARM_DRIVER_ERROR_PARAMETER; + } + + if ((Emac.flags & EMAC_FLAG_POWER) == 0U) { + return ARM_DRIVER_ERROR; + } + + if (dst == NULL) { + /* New TX frame start */ + if (tx_desc[Emac.tx_index].CtrlStat & DMA_TX_OWN) { + /* wait upto transmitter is busy */ + return ARM_DRIVER_ERROR_BUSY; + } + dst = (uint8_t *)tx_desc[Emac.tx_index].Addr; + dummy = tx_desc[Emac.tx_index].Size; + dummy = (dummy & 0xFF800000); + tx_desc[Emac.tx_index].Size = (len | dummy); + } + else { + /* Sending data fragments in progress */ + tx_desc[Emac.tx_index].Size += len; + } + /* Fast-copy data fragments to ETH-DMA buffer */ + for ( ; len > 7U; dst += 8, frame += 8, len -= 8U) { + ((__packed uint32_t *)dst)[0] = ((__packed uint32_t *)frame)[0]; + ((__packed uint32_t *)dst)[1] = ((__packed uint32_t *)frame)[1]; + } + /* Copy remaining 7 bytes */ + for ( ; len > 1U; dst += 2, frame += 2, len -= 2U) { + ((__packed uint16_t *)dst)[0] = ((__packed uint16_t *)frame)[0]; + } + if (len > 0U) { dst++[0] = frame++[0]; } + + if (flags & ARM_ETH_MAC_TX_FRAME_FRAGMENT) { + /* If more data is there copy current write position */ + Emac.frame_end = dst; + return ARM_DRIVER_OK; + } + + /* Send the frame to DMA */ + ctrl = tx_desc[Emac.tx_index].Size & ~DMA_TX_CIC; +#if (EMAC_CHECKSUM_OFFLOAD != 0) + if (Emac.tx_cks_offload) { + + uint16_t prot = (*((const __packed uint16_t *)(&tx_desc[Emac.tx_index].Addr[12]))); + uint16_t frag = (*((const __packed uint16_t *)(&tx_desc[Emac.tx_index].Addr[20])));; + if ((prot == 0x0008) && (frag & 0xFF3F)) { + /* Insert only IP header checksum in fragmented frame */ + ctrl |= DMA_TX_CIC_IP; + } + else { + /* Insert IP header and payload checksums (TCP,UDP,ICMP) */ + ctrl |= DMA_TX_CIC; + } + } +#endif + ctrl &= ~(DMA_TX_IC); + if (flags & ARM_ETH_MAC_TX_FRAME_EVENT) { ctrl |= DMA_TX_IC; } + + tx_desc[Emac.tx_index].Size = ctrl; + tx_desc[Emac.tx_index].CtrlStat = DMA_TX_OWN; + + Emac.tx_index++; + if (Emac.tx_index == NUM_TX_BUF) { Emac.tx_index = 0U; } + Emac.frame_end = NULL; + + /* Start frame transmission */ + ETH->DMA_STATUS_REG = ETH_DMASR_TPSS; + + ETH->DMA_TX_POLL_DEMAND_REG = 0U; + + return ARM_DRIVER_OK; +} + +/** + * @fn int32_t ReadFrame (uint8_t *frame, uint32_t len) + * @brief Read data of received Ethernet frame. + * @param[in] frame : Pointer to frame buffer for data to read into + * @param[in] len : Frame buffer length in bytes + * @return number of data bytes read or execution status + - value >= 0: number of data bytes read + - value < 0: error occurred, value is execution status as defined with \ref execution_status +*/ +static int32_t ReadFrame (uint8_t *frame, uint32_t len) { + uint8_t const *src = rx_desc[Emac.rx_index].Addr; + int32_t cnt = (int32_t)len; + + if ((frame == NULL) && (len != 0U)) { + return ARM_DRIVER_ERROR_PARAMETER; + } + + if ((Emac.flags & EMAC_FLAG_POWER) == 0U) { + return ARM_DRIVER_ERROR; + } + + /* Fast-copy data to frame buffer */ + for ( ; len > 7U; frame += 8, src += 8, len -= 8U) { + ((__packed uint32_t *)frame)[0] = ((uint32_t *)src)[0]; + ((__packed uint32_t *)frame)[1] = ((uint32_t *)src)[1]; + } + /* Copy remaining 7 bytes */ + for ( ; len > 1U; frame += 2, src += 2, len -= 2U) { + ((__packed uint16_t *)frame)[0] = ((uint16_t *)src)[0]; + } + if (len > 0U) { frame[0] = src[0]; } + + /* Return this block back to ETH-DMA */ + rx_desc[Emac.rx_index].Stat = DMA_RX_OWN; + + Emac.rx_index++; + if (Emac.rx_index == NUM_RX_BUF) { Emac.rx_index = 0; } + + if (ETH->DMA_STATUS_REG & ETH_DMASR_RBU) { + /* Receive buffer unavailable, resume DMA */ + ETH->DMA_STATUS_REG = ETH_DMASR_RBU; + ETH->DMA_RX_POLL_DEMAND_REG = 0; + } + + return (cnt); +} + +/** + * @fn uint32_t GetRxFrameSize (void) + * @brief Get size of received Ethernet frame. + * @return number of bytes in received frame +*/ +static uint32_t GetRxFrameSize (void) { + + uint32_t stat = rx_desc[Emac.rx_index].Stat; + + if ((Emac.flags & EMAC_FLAG_POWER) == 0U) { + return (0U); + } + + if (stat & DMA_RX_OWN) { + /* Owned by DMA */ + return (0U); + } + if (((stat & DMA_RX_ES) != 0) || + ((stat & DMA_RX_FS) == 0) || + ((stat & DMA_RX_LS) == 0)) { + /* Error, this block is invalid */ + return (0xFFFFFFFFU); + } + + return (((stat & DMA_RX_FL) >> 16) - 4U); +} + +/** + * @fn int32_t GetRxFrameTime (ARM_ETH_MAC_TIME *time) + * @brief Get time of received Ethernet frame. + * @param[in] time : Pointer to time structure for data to read into + * @return \ref execution_status +*/ +static int32_t GetRxFrameTime (ARM_ETH_MAC_TIME *time) { + return ARM_DRIVER_ERROR_UNSUPPORTED; +} + +/** + * @fn int32_t GetTxFrameTime (ARM_ETH_MAC_TIME *time) + * @brief Get time of transmitted Ethernet frame. + * @param[in] time : Pointer to time structure for data to read into + * @return \ref execution_status +*/ +static int32_t GetTxFrameTime (ARM_ETH_MAC_TIME *time) { + return ARM_DRIVER_ERROR_UNSUPPORTED; +} + +/** + * @fn int32_t ControlTimer (uint32_t control, ARM_ETH_MAC_TIME *time) + * @brief Control Precision Timer. + * @param[in] control : operation + * @param[in] time : Pointer to time structure + * @return \ref execution_status +*/ +static int32_t ControlTimer (uint32_t control, ARM_ETH_MAC_TIME *time) { + return ARM_DRIVER_ERROR_UNSUPPORTED; +} + +/** + * @fn int32_t Control (uint32_t control, uint32_t arg) + * @brief Control Ethernet Interface. + * @param[in] control : operation + * @param[in] arg : argument of operation (optional) + * @return \ref execution_status +*/ +static int32_t Control (uint32_t control, uint32_t arg) { + uint32_t maccr; + uint32_t dmaomr; + uint32_t macffr; + + if ((Emac.flags & EMAC_FLAG_POWER) == 0U) { + return ARM_DRIVER_ERROR; + } + + switch (control) { + case ARM_ETH_MAC_CONFIGURE: + maccr = ETH->MAC_CONFIG_REG & ~( ETH_MACCR_DM | + ETH_MACCR_LM | ETH_MACCR_IPC); + + + /* Configure the speed of operation(10/100 mbps) */ + switch (arg & ARM_ETH_MAC_SPEED_Msk) { + case ARM_ETH_MAC_SPEED_10M: + ETH_SPEED &= ~ETH_MACCR_FES; + break; + case ARM_ETH_SPEED_100M: + ETH_SPEED |= ETH_MACCR_FES; + break; + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + /* Confige the mode (Half/Full duplex) */ + switch (arg & ARM_ETH_MAC_DUPLEX_Msk) { + case ARM_ETH_MAC_DUPLEX_FULL: + maccr |= ETH_MACCR_DM; + break; + case ARM_ETH_MAC_DUPLEX_HALF: + maccr &= ~ETH_MACCR_DM; + break; + default: + return ARM_DRIVER_ERROR; + } + + /* Configurration of mac level loopback opearation */ + if (arg & ARM_ETH_MAC_LOOPBACK) { + maccr |= ETH_MACCR_LM; + } + + dmaomr = ETH->DMA_OPER_MODE_REG & ~(ETH_DMAOMR_RSF| ETH_DMAOMR_TSF); +#if (EMAC_CHECKSUM_OFFLOAD != 0) + /* Enable rx checksum verification */ + if (arg & ARM_ETH_MAC_CHECKSUM_OFFLOAD_RX) { + maccr |= ETH_MACCR_IPC; + } + + /* Enable tx checksum generation */ + if (arg & ARM_ETH_MAC_CHECKSUM_OFFLOAD_TX) { + dmaomr |= ETH_DMAOMR_TSF; + Emac.tx_cks_offload = true; + } + else { + Emac.tx_cks_offload = false; + } +#else + if ((arg & ARM_ETH_MAC_CHECKSUM_OFFLOAD_RX) || + (arg & ARM_ETH_MAC_CHECKSUM_OFFLOAD_TX)) { + /* Checksum offload is disabled in the driver */ + return ARM_DRIVER_ERROR; + } +#endif + ETH->DMA_OPER_MODE_REG = dmaomr; + ETH->MAC_CONFIG_REG = maccr; + + macffr = ETH->MAC_FRAME_FILTER_REG & ~(ETH_MACFFR_PR | ETH_MACFFR_PM | ETH_MACFFR_DBF); + /* Enable broadcast frame receive */ + if ((arg & ARM_ETH_MAC_ADDRESS_BROADCAST) == 0) { + macffr |= ETH_MACFFR_DBF; + } + + /* Enable all multicast frame receive */ + if (arg & ARM_ETH_MAC_ADDRESS_MULTICAST) { + macffr |= ETH_MACFFR_PM; + } + + /* Enable promiscuous mode (no filtering) */ + if (arg & ARM_ETH_MAC_ADDRESS_ALL) { + macffr |= ETH_MACFFR_PR; + } + ETH->MAC_FRAME_FILTER_REG = macffr; + break; + + case ARM_ETH_MAC_CONTROL_TX: + /* Enable/disable MAC transmitter */ + maccr = ETH->MAC_CONFIG_REG & ~ETH_MACCR_TE; + dmaomr = ETH->DMA_OPER_MODE_REG & ~ETH_DMAOMR_ST; + if (arg != 0) { + maccr |= ETH_MACCR_TE; + dmaomr |= ETH_DMAOMR_ST; + } + ETH->MAC_CONFIG_REG = maccr; + ETH->DMA_OPER_MODE_REG = dmaomr; + break; + + case ARM_ETH_MAC_CONTROL_RX: + /* Enable/disable MAC receiver */ + maccr = ETH->MAC_CONFIG_REG & ~ETH_MACCR_RE; + dmaomr = ETH->DMA_OPER_MODE_REG & ~ETH_DMAOMR_SR; + if (arg != 0) { + maccr |= ETH_MACCR_RE; + dmaomr |= ETH_DMAOMR_SR; + } + ETH->MAC_CONFIG_REG = maccr; + ETH->DMA_OPER_MODE_REG = dmaomr; + break; + + case ARM_ETH_MAC_FLUSH: + /* Flush tx and rx buffers */ + if (arg & ARM_ETH_MAC_FLUSH_RX) { + } + if (arg & ARM_ETH_MAC_FLUSH_TX) { + ETH->DMA_OPER_MODE_REG |= ETH_DMAOMR_FTF; + } + break; + + case ARM_ETH_MAC_VLAN_FILTER: + /* Configure VLAN filter */ + ETH->MAC_VLAN_TAG_REG = arg; + break; + + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + return ARM_DRIVER_OK; +} + + +/** + * @fn int32_t PHY_Read (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data) + * @brief Read Ethernet PHY Register through Management Interface. + * @param[in] phy_addr : 5-bit device address + * @param[in] reg_addr : 5-bit register address + * @param[out] data : Pointer where the result is written to + * @return \ref execution_status +*/ +static int32_t PHY_Read (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data) { + + /*Initialize the mdio*/ + MDIO_Init(); + /*Set the MDIO Direction*/ + MDIO_Dir(EGPIO_CONFIG_DIR_OUTPUT); + /*32 continuous 1's*/ + MDIO_Write(0xFFFFFFFF,32); + /*Start of frame(01) and read command(10) */ + MDIO_Write(0x6,4); + /*PHY address*/ + MDIO_Write(phy_addr,5); + /*reg address*/ + MDIO_Write(reg_addr,5); + + MDIO_Dir(EGPIO_CONFIG_DIR_INPUT); + /*Turn around time*/ + MDIO_Write(0x0,2); + + *data=MDIO_Read(); + + MDIO_Dir(EGPIO_CONFIG_DIR_OUTPUT); + + return ARM_DRIVER_OK; +} + +/** + * @fn int32_t PHY_Write (uint8_t phy_addr, uint8_t reg_addr, uint16_t data) + * @brief Write Ethernet PHY Register through Management Interface. + * @param[in] phy_addr : 5-bit device address + * @param[in] reg_addr : 5-bit register address + * @param[in] data : 16-bit data to write + * @return \ref execution_status +*/ +static int32_t PHY_Write (uint8_t phy_addr, uint8_t reg_addr, uint16_t data) { + + /*Initialize the mdio*/ + MDIO_Init(); + /*Set the MDIO Direction*/ + MDIO_Dir(EGPIO_CONFIG_DIR_OUTPUT); + /*32 continuous 1's*/ + MDIO_Write(0xFFFFFFFF,32); + /*start of frame(01) and write command(01) */ + MDIO_Write(0x5,4); + /*phy address*/ + MDIO_Write(phy_addr,5); + /*reg address*/ + MDIO_Write(reg_addr,5); + /*Turn around time*/ + MDIO_Write(0x2,2); + /*write the data*/ + MDIO_Write(data,16); + + return ARM_DRIVER_OK; +} + + +/* Ethernet IRQ Handler */ +void IRQ062_Handler (void) { + uint32_t dmasr, macsr, event = 0; + + dmasr = ETH->DMA_STATUS_REG; + ETH->DMA_STATUS_REG = dmasr & (ETH_DMASR_NIS | ETH_DMASR_RI | ETH_DMASR_TI); + + if (dmasr & ETH_DMASR_TI) { + /* Frame sent */ + event |= ARM_ETH_MAC_EVENT_TX_FRAME; + } + if (dmasr & ETH_DMASR_RI) { + /* Frame received */ + event |= ARM_ETH_MAC_EVENT_RX_FRAME; + } + macsr = ETH->MAC_STATUS_REG; + + + if (macsr & ETH_MACSR_PMTS) { + ETH->MAC_PMT_CTRL_STATUS_REG; + event |= ARM_ETH_MAC_EVENT_WAKEUP; + } + + /* Callback event notification */ + if (event && Emac.cb_event) { + Emac.cb_event (event); + } +} + + +/* MAC Driver Control Block */ +ARM_DRIVER_ETH_MAC Driver_ETH_MAC0 = { + GetVersion, + GetCapabilities, + Initialize, + Uninitialize, + PowerControl, + GetMacAddress, + SetMacAddress, + SetAddressFilter, + SendFrame, + ReadFrame, + GetRxFrameSize, + GetRxFrameTime, + GetTxFrameTime, + ControlTimer, + Control, + PHY_Read, + PHY_Write +}; +#endif + + diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/EMAC.h b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/EMAC.h new file mode 100644 index 000000000..1d4aa6c23 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/EMAC.h @@ -0,0 +1,445 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2018 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * $Date: 25. Dec 2018 + * $Revision: V2.8 + * + * Project: Ethernet Media Access (MAC) Definitions + * -------------------------------------------------------------------------- */ + + +#include + +#include "Driver_ETH_MAC.h" + +#define ETH_MII 0 +/* EMAC Driver state flags */ +#define EMAC_FLAG_INIT (1 << 0) // Driver initialized +#define EMAC_FLAG_POWER (1 << 1) // Driver power on + +/* TDES0 - DMA Descriptor TX Packet Control/Status */ +#define DMA_TX_OWN 0x80000000U // Own bit 1=DMA,0=CPU + +/* TDES1 - DMA Descriptor TX Packet Control/Status */ +#define DMA_TX_IC 0x80000000U // Interrupt on completition +#define DMA_TX_LS 0x40000000U // Last segment +#define DMA_TX_FS 0x20000000U // First segment +#define DMA_TX_DC 0x04000000U // Disable CRC +#define DMA_TX_DP 0x00800000U // Disable pad +#define DMA_TX_CIC 0x18000000U // Checksum insertion control +#define DMA_TX_CIC_IP 0x08000000U //Checksum insertion control for IP header only +#define DMA_TX_CIC_BYPASS 0x00000000U +#define DMA_TX_TER 0x02000000U // Transmit end of ring +#define DMA_TX_TCH 0x01000000U // Second address chained +#define DMA_TX_TTSS 0x00020000U // Transmit time stamp status +#define DMA_TX_IHE 0x00010000U // IP header error status +#define DMA_TX_ES 0x00008000U // Error summary +#define DMA_TX_JT 0x00004000U // Jabber timeout +#define DMA_TX_FF 0x00002000U // Frame flushed +#define DMA_TX_IPE 0x00001000U // IP payload error +#define DMA_TX_LC 0x00000800U // Loss of carrier +#define DMA_TX_NC 0x00000400U // No carrier +#define DMA_TX_LCOL 0x00000200U // Late collision +#define DMA_TX_EC 0x00000100U // Excessive collision +#define DMA_TX_VF 0x00000080U // VLAN frame +#define DMA_TX_CC 0x00000078U // Collision count +#define DMA_TX_ED 0x00000004U // Excessive deferral +#define DMA_TX_UF 0x00000002U // Underflow error +#define DMA_TX_DB 0x00000001U // Deferred bit + +/* TDES1 - DMA Descriptor TX Packet Control */ +#define DMA_TX_TBS2 0x1FFF0000U // Transmit buffer 2 size +#define DMA_TX_TBS1 0x00001FFFU // Transmit buffer 1 size + +/* RDES0 - DMA Descriptor RX Packet Status */ +#define DMA_RX_OWN 0x80000000U // Own bit 1=DMA,0=CPU +#define DMA_RX_AFM 0x40000000U // Destination address filter fail +#define DMA_RX_FL 0x3FFF0000U // Frame length mask +#define DMA_RX_ES 0x00008000U // Error summary +#define DMA_RX_DE 0x00004000U // Descriptor error +#define DMA_RX_SAF 0x00002000U // Source address filter fail +#define DMA_RX_LE 0x00001000U // Length error +#define DMA_RX_OE 0x00000800U // Overflow error +#define DMA_RX_VLAN 0x00000400U // VLAN tag +#define DMA_RX_FS 0x00000200U // First descriptor +#define DMA_RX_LS 0x00000100U // Last descriptor +#define DMA_RX_IPHCE 0x00000080U // IPv4 header checksum error +#define DMA_RX_LC 0x00000040U // late collision +#define DMA_RX_FT 0x00000020U // Frame type +#define DMA_RX_RWT 0x00000010U // Receive watchdog timeout +#define DMA_RX_RE 0x00000008U // Receive error +#define DMA_RX_DRE 0x00000004U // Dribble bit error +#define DMA_RX_CE 0x00000002U // CRC error +#define DMA_RX_RMAM 0x00000001U // Rx MAC adr.match/payload cks.error + +/* RDES1 - DMA Descriptor RX Packet Control */ +#define DMA_RX_DIC 0x80000000U // Disable interrupt on completion +#define DMA_RX_RBS2 0x1FFF0000U // Receive buffer 2 size +#define DMA_RX_RER 0x02000000U // Receive end of ring +#define DMA_RX_RCH 0x01000000U // Second address chained +#define DMA_RX_RBS1 0x00001FFFU // Receive buffer 1 size + +/* Ethernet MAC configuration register */ +#define ETH_MACCR_WD 0x00800000U /* Watchdog disable */ +#define ETH_MACCR_JD 0x00400000U /* Jabber disable */ +#define ETH_MACCR_IFG 0x000E0000U /* Inter-frame gap mask*/ +#define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */ +#define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */ +#define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */ +#define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */ +#define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */ +#define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */ +#define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */ +#define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */ +#define ETH_MACCR_DCRS 0x00010000U /* Disable Carrier sense during transmission */ +#define ETH_MACCR_PS 0x00008000U /* PORT Select */ +#define ETH_MACCR_FES 0x00000010U /* Fast ethernet speed */ +#define ETH_MACCR_DO 0x00002000U /* Disable Receive own */ +#define ETH_MACCR_LM 0x00001000U /* loopback mode */ +#define ETH_MACCR_DM 0x00000800U /* Duplex mode */ +#define ETH_MACCR_IPC 0x00000400U /* IP Checksum offload */ +#define ETH_MACCR_DR 0x00000200U /* Disable Retry */ +#define ETH_MACCR_APCS 0x00000080U /* Automatic Pad/CRC stripping */ +#define ETH_MACCR_BL 0x00000060U /* Back-off limit mask The random integer (r) of slot time delays where r takes the value in the range 0 = r < 2k*/ + +#define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */ +#define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */ +#define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */ +#define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */ +#define ETH_MACCR_DC 0x00000010U /* Defferal check */ +#define ETH_MACCR_TE 0x00000008U /* Transmitter enable */ +#define ETH_MACCR_RE 0x00000004U /* Receiver enable */ + + +/* Ethernet MAC Frame Filter Register */ +#define ETH_MACFFR_RA 0x80000000U /* Receive all */ +#define ETH_MACFFR_HPF 0x00000400U /* Hash or perfect filter */ +#define ETH_MACFFR_SAF 0x00000200U /* Source address filter enable */ +#define ETH_MACFFR_SAIF 0x00000100U /* SA inverse filtering */ +#define ETH_MACFFR_PCF 0x000000C0U /* Pass control frames: 3 cases */ +#define ETH_MACFFR_PCF_BlockAll 0x00000040U /* MAC filters all control frames from reaching the application */ +#define ETH_MACFFR_PCF_ForwardAll 0x00000080U /* MAC forwards all control frames to application even if they fail the Address Filter */ +#define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U /* MAC forwards control frames that pass the Address Filter. */ +#define ETH_MACFFR_DBF 0x00000020U /* Disable Broadcast Frames */ +#define ETH_MACFFR_PM 0x00000010U /* Pass all mutlicast */ +#define ETH_MACFFR_DAIF 0x00000008U /* DA Inverse filtering */ +#define ETH_MACFFR_HMC 0x00000004U /* Hash multicast */ +#define ETH_MACFFR_HUC 0x00000002U /* Hash unicast */ +#define ETH_MACFFR_PR 0x00000001U /* Promiscuous mode */ + +/*Ethernet MAC Hash Table High Register */ +#define ETH_MACHTHR_HTH 0xFFFFFFFFU /* Hash table high */ + + +/*Ethernet MAC Hash Table Low Register */ +#define ETH_MACHTLR_HTL 0xFFFFFFFFU /* Hash table low */ + +/*Ethernet MAC MII Address Register */ +#define ETH_MACMIIAR_PA 0x0000F800U /* Physical layer address */ +#define ETH_MACMIIAR_MR 0x000007C0U /* MII register in the selected PHY */ +#define ETH_MACMIIAR_CR 0x0000001CU /* CR clock range: 6 cases */ +#define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */ +#define ETH_MACMIIAR_CR_Div62 0x00000004U /* HCLK:100-150 MHz; MDC clock= HCLK/62 */ +#define ETH_MACMIIAR_CR_Div16 0x00000008U /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ +#define ETH_MACMIIAR_CR_Div26 0x0000000CU /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ +#define ETH_MACMIIAR_CR_Div102 0x00000010U /* HCLK:150-180 MHz; MDC clock= HCLK/102 */ +#define ETH_MACMIIAR_MW 0x00000002U /* MII write */ +#define ETH_MACMIIAR_MB 0x00000002U /* MII busy */ + +/*Ethernet MAC MII Data Register */ +#define ETH_MACMIIDR_GD 0x0000FFFFU /* MII data: read/write data from/to PHY */ + +/*Ethernet MAC Flow Control Register */ +#define ETH_MACFCR_PT 0xFFFF0000U /* Pause time */ +#define ETH_MACFCR_DZPQ 0x00000080U /* Disable Zero-Quanta Pause */ +#define ETH_MACFCR_PLT 0x00000030U /* Pause low threshold */ +#define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */ +#define ETH_MACFCR_PLT_Minus28 0x00000010U /* Pause time minus 28 slot times */ +#define ETH_MACFCR_PLT_Minus144 0x00000020U /* Pause time minus 144 slot times */ +#define ETH_MACFCR_PLT_Minus256 0x00000030U /* Pause time minus 256 slot times */ +#define ETH_MACFCR_UP 0x00000008U /* Unicast pause frame detect */ +#define ETH_MACFCR_RFE 0x00000004U /* Receive flow control enable */ +#define ETH_MACFCR_TFE 0x00000002U /* Transmit flow control enable */ +#define ETH_MACFCR_FCBBPA 0x00000001U /* Flow control busy/backpressure activate */ + +/*Ethernet MAC VLAN Tag Register */ +#define ETH_MACVLANTR_VLANTI 0x0000FFFFU /* VLAN tag identifier (for receive frames) */ + +/*Ethernet MAC Remote Wake-UpFrame Filter Register */ +#define ETH_MACRWUFFR_D 0xFFFFFFFF /* Wake-up frame filter register data */ + +/*Ethernet MAC PMT Control and Status Register */ +#define ETH_MACPMTCSR_WFFRPR 0x80000000 /* Wake-Up Frame Filter Register Pointer Reset */ +#define ETH_MACPMTCSR_GU 0x00000200 /* Global Unicast */ +#define ETH_MACPMTCSR_WFR 0x00000040 /* Wake-Up Frame Received */ +#define ETH_MACPMTCSR_MPR 0x00000020 /* Magic Packet Received */ +#define ETH_MACPMTCSR_WFE 0x00000004 /* Wake-Up Frame Enable */ +#define ETH_MACPMTCSR_MPE 0x00000002 /* Magic Packet Enable */ +#define ETH_MACPMTCSR_PD 0x00000001 /* Power Down */ + +/*Ethernet MAC Status Register */ +#define ETH_MACSR_MMCTS 0x00000040U /* MMC transmit status */ +#define ETH_MACSR_MMCRS 0x00000020U /* MMC receive status */ +#define ETH_MACSR_MMCS 0x00000010U /* MMC status */ +#define ETH_MACSR_PMTS 0x00000008U /* PMT status */ + +/* Ethernet MAC Interrupt Mask Register */ +#define ETH_MACIMR_PMTIM 0x00000008U /* PMT interrupt mask */ + +/* Ethernet MAC Address0 High Register */ +#define ETH_MACA0HR_MACA0H 0x0000FFFFU /* MAC address0 high */ + +/* Ethernet MAC Address0 Low Register */ +#define ETH_MACA0LR_MACA0L 0xFFFFFFFFU /* MAC address0 low */ + +/* Ethernet MAC Address1 High Register */ +#define ETH_MACA1HR_AE 0x80000000U /* Address enable */ +#define ETH_MACA1HR_SA 0x40000000U /* Source address */ +#define ETH_MACA1HR_MBC 0x3F000000U /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ +#define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */ +#define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */ +#define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */ +#define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */ +#define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */ +#define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */ +#define ETH_MACA1HR_MACA1H 0x0000FFFFU /* MAC address1 high */ + +/* Ethernet MAC Address1 Low Register */ +#define ETH_MACA1LR_MACA1L 0xFFFFFFFFU /* MAC address1 low */ + +/* Ethernet MAC Address2 High Register */ +#define ETH_MACA2HR_AE 0x80000000U /* Address enable */ +#define ETH_MACA2HR_SA 0x40000000U /* Source address */ +#define ETH_MACA2HR_MBC 0x3F000000U /* Mask byte control */ +#define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */ +#define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */ +#define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */ +#define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */ +#define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */ +#define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */ +#define ETH_MACA2HR_MACA2H 0x0000FFFFU /* MAC address1 high */ + +/*Ethernet MAC Address2 Low Register */ +#define ETH_MACA2LR_MACA2L 0xFFFFFFFFU /* MAC address2 low */ + +/* Ethernet MAC Address3 High Register */ +#define ETH_MACA3HR_AE 0x80000000U /* Address enable */ +#define ETH_MACA3HR_SA 0x40000000U /* Source address */ +#define ETH_MACA3HR_MBC 0x3F000000U /* Mask byte control */ +#define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */ +#define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */ +#define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */ +#define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */ +#define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */ +#define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */ +#define ETH_MACA3HR_MACA3H 0x0000FFFFU /* MAC address3 high */ + +/* Ethernet MAC Address3 Low Register */ +#define ETH_MACA3LR_MACA3L 0xFFFFFFFFU /* MAC address3 low */ + +/* Ethernet MMC Contol Register */ +#define ETH_MMCCR_MCF 0x00000008U /* MMC Counter Freeze */ +#define ETH_MMCCR_ROR 0x00000004U /* Reset on Read */ +#define ETH_MMCCR_CSR 0x00000002U /* Counter Stop Rollover */ +#define ETH_MMCCR_CR 0x00000001U /* Counters Reset */ + +/* Ethernet MMC Receive Interrupt Register */ +#define ETH_MMCRIR_RFCES 0x00000020U /* Set when Rx crc error counter reaches half the maximum value */ + +/* MMC Transmit Interrupt Register */ +#define ETH_MMCTIR_TGFS 0x00200000U /* Set when Tx good frame count counter reaches half the maximum value */ +#define ETH_MMCTIR_TGFSCS 0x00004000U /* Set when Tx good single col counter reaches half the maximum value */ + +/*Ethernet MMC Receive Interrupt Mask Register */ +#define ETH_MMCRIMR_RFCEM 0x00000020U /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ + +/*Ethernet MMC Transmit Interrupt Mask Register */ +#define ETH_MMCTIMR_TGFM 0x00200000U /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ +#define ETH_MMCTIMR_TGFSCM 0x00004000U /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ + +/* DMA Bus Mode Register */ +#define ETH_DMABMR_AAB 0x02000000U /* Address-Aligned beats */ +#define ETH_DMABMR_FPM 0x01000000U /* 4xPBL mode */ +#define ETH_DMABMR_USP 0x00800000U /* Use separate PBL */ +#define ETH_DMABMR_RDP 0x007E0000U /* RxDMA PBL */ +#define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ +#define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ +#define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ +#define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ +#define ETH_DMABMR_FB 0x00010000U /* Fixed Burst */ +#define ETH_DMABMR_RTPR 0x0000C000U /* Rx Tx priority ratio */ +#define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */ +#define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */ +#define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */ +#define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */ +#define ETH_DMABMR_PBL 0x00003F00U /* Programmable burst length */ +#define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ +#define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ +#define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ +#define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ +#define ETH_DMABMR_DSL 0x0000007CU /* Descriptor Skip Length */ +#define ETH_DMABMR_DA 0x00000002U /* DMA arbitration scheme */ +#define ETH_DMABMR_SR 0x00000001U /* Software reset */ + +/* DMA Transmit Poll Demand Register */ +#define ETH_DMATPDR_TPD 0xFFFFFFFFU /* Transmit poll demand */ + +/* DMA Receive Poll Demand Register */ +#define ETH_DMARPDR_RPD 0xFFFFFFFFU + +/* DMA Receive Descriptor List Address Register */ +#define ETH_DMARDLAR_SRL 0xFFFFFFFFU /* Start of receive list */ + +/* DMA Transmit Descriptor List Address Register */ +#define ETH_DMATDLAR_STL 0xFFFFFFFFU /* Start of transmit list */ + +/* DMA Status Register */ +#define ETH_DMASR_PMTS 0x10000000U /* PMT status */ +#define ETH_DMASR_MMCS 0x08000000U /* MMC status */ +#define ETH_DMASR_EBS 0x03800000U /* Error bits status */ +#define ETH_DMASR_EBS_DescAccess 0x02000000U /* Error bits 0-data buffer, 1-desc. access */ +#define ETH_DMASR_EBS_ReadTransf 0x01000000U /* Error bits 0-write trnsfer, 1-read transfer */ +#define ETH_DMASR_EBS_DataTransfTx 0x00800000U /* Error bits 0-Data transfer by Rx DMA, 1-Tx DMA */ +#define ETH_DMASR_TPS 0x00700000U /* Transmit process state */ +#define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */ +#define ETH_DMASR_TPS_Fetching 0x00100000U /* Running - fetching the Tx descriptor */ +#define ETH_DMASR_TPS_Waiting 0x00200000U /* Running - waiting for status */ +#define ETH_DMASR_TPS_Reading 0x00300000U /* Running - reading the data from host memory */ +#define ETH_DMASR_TPS_Suspended 0x00600000U /* Suspended - Tx Descriptor unavailabe */ +#define ETH_DMASR_TPS_Closing 0x00700000U /* Running - closing Rx descriptor */ +#define ETH_DMASR_RPS 0x000E0000U /* Receive process state */ +#define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */ +#define ETH_DMASR_RPS_Fetching 0x00020000U /* Running - fetching the Rx descriptor */ +#define ETH_DMASR_RPS_Waiting 0x00060000U /* Running - waiting for packet */ +#define ETH_DMASR_RPS_Suspended 0x00080000U /* Suspended - Rx Descriptor unavailable */ +#define ETH_DMASR_RPS_Closing 0x000A0000U /* Running - closing descriptor */ +#define ETH_DMASR_RPS_Queuing 0x000E0000U /* Running - queuing the recieve frame into host memory */ +#define ETH_DMASR_NIS 0x00010000U /* Normal interrupt summary */ +#define ETH_DMASR_AIS 0x00008000U /* Abnormal interrupt summary */ +#define ETH_DMASR_ERI 0x00004000U /* Early receive interrupt */ +#define ETH_DMASR_FBEI 0x00002000U /* Fatal bus error Interrupt */ +#define ETH_DMASR_ETI 0x00000400U /* Early transmit Interrupt */ +#define ETH_DMASR_RWT 0x00000200U /* Receive watchdog timeout status */ +#define ETH_DMASR_RPSS 0x00000100U /* Receive process stopped status */ +#define ETH_DMASR_RBU 0x00000080U /* Receive buffer unavailable status */ +#define ETH_DMASR_RI 0x00000040U /* Receive interrupt status */ +#define ETH_DMASR_TUNF 0x00000020U /* Transmit underflow status */ +#define ETH_DMASR_ROVF 0x00000010U /* Receive overflow status */ +#define ETH_DMASR_TJT 0x00000008U /* Transmit jabber timeout status */ +#define ETH_DMASR_TBU 0x00000004U /* Transmit buffer unavailable status */ +#define ETH_DMASR_TPSS 0x00000002U /* Transmit process stopped status */ +#define ETH_DMASR_TI 0x00000001U /* Transmit interrupt status */ + +/* DMA Operation Mode Register */ +#define ETH_DMAOMR_DT 0x04000000U /* Disable Dropping of TCP/IP checksum error frames */ +#define ETH_DMAOMR_RSF 0x02000000U /* Receive store and forward */ +#define ETH_DMAOMR_DFF 0x01000000U /* Disable flushing of received frames */ +#define ETH_DMAOMR_TSF 0x00200000U /* Transmit store and forward */ +#define ETH_DMAOMR_FTF 0x00100000U /* Flush transmit FIFO */ +#define ETH_DMAOMR_TTC 0x0001C000U /* Transmit threshold control */ +#define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */ +#define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */ +#define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */ +#define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */ +#define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */ +#define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */ +#define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */ +#define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */ +#define ETH_DMAOMR_ST 0x00002000U /* Start/stop transmission command */ +#define ETH_DMAOMR_FEF 0x00000080U /* Forward error frames */ +#define ETH_DMAOMR_FUF 0x00000040U /* Forward undersized good frames */ +#define ETH_DMAOMR_RTC 0x00000018U /* receive threshold control */ +#define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */ +#define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */ +#define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */ +#define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */ +#define ETH_DMAOMR_OSF 0x00000004U /* operate on second frame */ +#define ETH_DMAOMR_SR 0x00000002U /* Start/stop receive */ + +/* DMA Interrupt Enable Register */ +#define ETH_DMAIER_NIE 0x00010000U /* Normal interrupt summary enable */ +#define ETH_DMAIER_AIE 0x00008000U /* Abnormal interrupt summary enable */ +#define ETH_DMAIER_ERIE 0x00004000U /* Early receive interrupt enable */ +#define ETH_DMAIER_FBIE 0x00002000U /* Fatal bus error interrupt enable */ +#define ETH_DMAIER_ETIE 0x00000400U /* Early transmit interrupt enable */ +#define ETH_DMAIER_RWIE 0x00000200U /* Receive watchdog timeout interrupt enable */ +#define ETH_DMAIER_RSIE 0x00000100U /* Receive process stopped interrupt enable */ +#define ETH_DMAIER_RUIE 0x00000080U /* Receive buffer unavailable interrupt enable */ +#define ETH_DMAIER_RIE 0x00000040U /* Receive interrupt enable */ +#define ETH_DMAIER_TUIE 0x00000020U /* Transmit Underflow interrupt enable */ +#define ETH_DMAIER_ROIE 0x00000010U /* Receive Overflow interrupt enable */ +#define ETH_DMAIER_TJIE 0x00000008U /* Transmit jabber timeout interrupt enable */ +#define ETH_DMAIER_TBUIE 0x00000004U /* Transmit buffer unavailable interrupt enable */ +#define ETH_DMAIER_TSIE 0x00000002U /* Transmit process stopped interrupt enable */ +#define ETH_DMAIER_TIE 0x00000001U /* Transmit interrupt enable */ + +/* DMA Missed Frame and Buffer Overflow Counter Register */ +#define ETH_DMAMFBOCR_OFOC 0x10000000U /* Overflow bit for FIFO overflow counter */ +#define ETH_DMAMFBOCR_MFA 0x0FFE0000U /* Number of frames missed by the application */ +#define ETH_DMAMFBOCR_OMFC 0x00010000U /* Overflow bit for missed frame counter */ +#define ETH_DMAMFBOCR_MFC 0x0000FFFFU /* Number of frames missed by the controller */ + +/* DMA Current Host Transmit Descriptor Register */ +#define ETH_DMACHTDR_HTDAP 0xFFFFFFFFU /* Host transmit descriptor address pointer */ + +/* DMA Current Host Receive Descriptor Register */ +#define ETH_DMACHRDR_HRDAP 0xFFFFFFFFU /* Host receive descriptor address pointer */ + +/* DMA Current Host Transmit Buffer Address Register */ +#define ETH_DMACHTBAR_HTBAP 0xFFFFFFFFU /* Host transmit buffer address pointer */ + +/* DMA Current Host Receive Buffer Address Register */ +#define ETH_DMACHRBAR_HRBAP 0xFFFFFFFFU /* Host receive buffer address pointer */ + +typedef struct _ETH_PIN_config { + uint8_t port; + uint8_t pin; + uint8_t mode; + uint8_t pad_sel; +} ETH_PIN_Config; + +/* EMAC Driver Control Information */ +typedef struct { + ARM_ETH_MAC_SignalEvent_t cb_event; // Event callback + uint8_t flags; // Control and state flags + uint8_t tx_index; // Transmit descriptor index + uint8_t rx_index; // Receive descriptor index +#if (EMAC_CHECKSUM_OFFLOAD) + bool tx_cks_offload; // Checksum offload enabled/disabled +#endif +#if (EMAC_TIME_STAMP) + uint8_t tx_ts_index; // Transmit Timestamp descriptor index +#endif + uint8_t *frame_end; // End of assembled frame fragments +} EMAC_CTRL; + diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/MCI.c b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/MCI.c new file mode 100644 index 000000000..a5069308d --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/MCI.c @@ -0,0 +1,1118 @@ + /* -------------------------------------------------------------------------- + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * $Date: 02. March 2016 + * $Revision: V1.1 + * + * Driver: Driver_MCI0 + * Configured: via RTE_Device.h configuration file + * Project: MCI Driver for RS1xxxx + */ + +/* History: + * Version 1.0 + * Initial release + */ +#include "rsi_ccp_user_config.h" +#if defined(CHIP_9118) +#include "MCI.h" + + + +#define SDHC_IRQHandler IRQ068_Handler +#define ARM_MCI_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,2) /* driver version */ +static MCI_CTRL MCI; + +/* Driver Version */ +static const ARM_DRIVER_VERSION DriverVersion = { + ARM_MCI_API_VERSION, + ARM_MCI_DRV_VERSION +}; + +/* Driver Capabilities */ +static const ARM_MCI_CAPABILITIES DriverCapabilities = { + RTE_MCI_CD_PIN, /* cd_state */ + 0, /* cd_event */ + RTE_MCI_WP_PIN, /* wp_state */ + 0, /* vdd */ + 0, /* vdd_1v8 */ + 0, /* vccq */ + 0, /* vccq_1v8 */ + 0, /* vccq_1v2 */ + RTE_MCI_BUS_WIDTH_4, /* data_width_4 */ + RTE_MCI_BUS_WIDTH_8, /* data_width_8 */ + 0, /* data_width_4_ddr */ + 0, /* data_width_8_ddr */ + 1, /* high_speed */ + 0, /* uhs_signaling */ + 0, /* uhs_tuning */ + 0, /* uhs_sdr50 */ + 0, /* uhs_sdr104 */ + 0, /* uhs_ddr50 */ + 0, /* uhs_driver_type_a */ + 0, /* uhs_driver_type_c */ + 0, /* uhs_driver_type_d */ + 0, /* sdio_interrupt */ + 0, /* read_wait */ + 0, /* suspend_resume */ + 0, /* mmc_interrupt */ + 0, /* mmc_boot */ + 0, /* rst_n */ + 0, /* ccs */ + 0 /* ccs_timeout */ +}; + +/*********functions************/ +static MCI_ADMA_DESC_TABLE_T Adma2DescriptorTable[2] = { 0 }; + +/** + * @fn ARM_DRIVER_VERSION MCI_GetVersion(void) + * @brief Get Driver Version. + * @param[in] none + * @return ARM DRIVER VERSION + */ +static ARM_DRIVER_VERSION MCI_GetVersion(void) +{ + return DriverVersion; +} + +/** + * @fn ARM_MCI_CAPABILITIES MCI_GetCapabilities(void) + * @brief Get Driver capabilities. + * @param[in] none + * @return ARM_MCI_CAPABILITIES + */ +static ARM_MCI_CAPABILITIES MCI_GetCapabilities(void) +{ + return DriverCapabilities; +} + +/** + * @fn int32_t MCI_Initialize(ARM_MCI_SignalEvent_t cb_event) + * @brief Initialize the Memory Card Interface. + * @param[in] cb_event Pointer to the ARM_MCI_SignalEvent + * @return excecution status + */ +static int32_t MCI_Initialize(ARM_MCI_SignalEvent_t cb_event) +{ + if (MCI.flags & MCI_INIT) + { + return ARM_DRIVER_OK; + } + + MCI.cb_event = cb_event; + + /* Clear status */ + MCI.status.command_active = 0U; + MCI.status.command_timeout = 0U; + MCI.status.command_error = 0U; + MCI.status.transfer_active = 0U; + MCI.status.transfer_timeout = 0U; + MCI.status.transfer_error = 0U; + MCI.status.sdio_interrupt = 0U; + MCI.status.ccs = 0U; + + /*Configure clock gpio pin*/ + if(RTE_MCI_CLK_PIN == 25) + { + RSI_EGPIO_HostPadsGpioModeEnable(25); + } + RSI_EGPIO_PadSelectionEnable(RTE_MCI_CLOCK_PAD); + RSI_EGPIO_PadReceiverEnable(RTE_MCI_CLK_PIN); + RSI_EGPIO_SetPinMux(EGPIO,RTE_MCI_CLOCK_PORT,RTE_MCI_CLK_PIN,EGPIO_PIN_MUX_MODE8); + + if(RTE_MCI_CD_PIN) + { + /*Configure cd gpio pin*/ + RSI_EGPIO_PadSelectionEnable(RTE_MCI_CDD_PAD); + RSI_EGPIO_PadReceiverEnable(RTE_MCI_CDD_PIN); + RSI_EGPIO_PadDriverDisableState(RTE_MCI_CDD_PIN,Pulldown); + RSI_EGPIO_SetPinMux(EGPIO,RTE_MCI_CD_PORT,RTE_MCI_CDD_PIN,EGPIO_PIN_MUX_MODE8); + } + if(RTE_MCI_WP_PIN) + { + /*Configure write protect gpio pin*/ + RSI_EGPIO_PadSelectionEnable(RTE_MCI_WPP_PAD); + RSI_EGPIO_PadReceiverEnable(RTE_MCI_WPP_PIN); + RSI_EGPIO_PadDriverDisableState(RTE_MCI_WPP_PIN,Pulldown); + RSI_EGPIO_SetPinMux(EGPIO,RTE_MCI_WP_PORT,RTE_MCI_WPP_PIN,EGPIO_PIN_MUX_MODE8); + } + + /*Configure command gpio pin*/ + if(RTE_MCI_CMD_PIN == 26) + { + RSI_EGPIO_HostPadsGpioModeEnable(26); + } + RSI_EGPIO_PadSelectionEnable(RTE_MCI_CMD_PAD); + RSI_EGPIO_PadReceiverEnable(RTE_MCI_CMD_PIN); + RSI_EGPIO_PadDriverDisableState(RTE_MCI_CMD_PIN,Pullup); + RSI_EGPIO_SetPinMux(EGPIO,RTE_MCI_CMD_PORT,RTE_MCI_CMD_PIN,EGPIO_PIN_MUX_MODE8); + + /*Configure data0 gpio pin*/ + if(RTE_MCI_DATA0_PIN == 27) + { + RSI_EGPIO_HostPadsGpioModeEnable(27); + } + RSI_EGPIO_PadSelectionEnable(RTE_MCI_DATA0_PAD); + RSI_EGPIO_PadReceiverEnable(RTE_MCI_DATA0_PIN); + RSI_EGPIO_PadDriverDisableState(RTE_MCI_DATA0_PIN,Pullup); + RSI_EGPIO_SetPinMux(EGPIO,RTE_MCI_DATA0_PORT,RTE_MCI_DATA0_PIN,EGPIO_PIN_MUX_MODE8); + +#if(RTE_SDMMC_BUS_WIDTH_4) /* SD_DAT[3..1] */ + /*Configure data1 gpio pin*/ + if(RTE_MCI_DATA1_PIN == 28) + { + RSI_EGPIO_HostPadsGpioModeEnable(28); + } + RSI_EGPIO_PadSelectionEnable(RTE_MCI_DATA1_PAD); + RSI_EGPIO_PadReceiverEnable(RTE_MCI_DATA1_PIN); + RSI_EGPIO_PadDriverDisableState(RTE_MCI_DATA1_PIN,Pullup); + RSI_EGPIO_SetPinMux(EGPIO,RTE_MCI_DATA1_PORT,RTE_MCI_DATA1_PIN,EGPIO_PIN_MUX_MODE8); + + /*Configure data2 gpio pin*/ + if(RTE_MCI_DATA2_PIN == 29) + { + RSI_EGPIO_HostPadsGpioModeEnable(29); + } + RSI_EGPIO_PadSelectionEnable(RTE_MCI_DATA2_PAD); + RSI_EGPIO_PadReceiverEnable(RTE_MCI_DATA2_PIN); + RSI_EGPIO_PadDriverDisableState(RTE_MCI_DATA2_PIN,Pullup); + RSI_EGPIO_SetPinMux(EGPIO,RTE_MCI_DATA2_PORT,RTE_MCI_DATA2_PIN,EGPIO_PIN_MUX_MODE8); + + /*Configure data3 gpio pin*/ + if(RTE_MCI_DATA3_PIN == 30) + { + RSI_EGPIO_HostPadsGpioModeEnable(30); + } + RSI_EGPIO_PadSelectionEnable(RTE_MCI_DATA3_PAD); + RSI_EGPIO_PadReceiverEnable(RTE_MCI_DATA3_PIN); + RSI_EGPIO_PadDriverDisableState(RTE_MCI_DATA3_PIN,Pullup); + RSI_EGPIO_SetPinMux(EGPIO,RTE_MCI_DATA3_PORT,RTE_MCI_DATA3_PIN,EGPIO_PIN_MUX_MODE8); + +#if(RTE_SDMMC_BUS_WIDTH_8) /* RTE_SDMMC_BUS_WIDTH_8 */ + + /*Configure data4 gpio pin*/ + RSI_EGPIO_PadSelectionEnable(RTE_MCI_DATA4_PAD); + RSI_EGPIO_PadReceiverEnable(RTE_MCI_DATA4_PIN); + RSI_EGPIO_PadDriverDisableState(RTE_MCI_DATA4_PIN,Pullup); + RSI_EGPIO_SetPinMux(EGPIO,RTE_MCI_DATA4_PORT,RTE_MCI_DATA4_PIN,RTE_MCI_DATA6_MODE); + + /*Configure data5 gpio pin*/ + RSI_EGPIO_PadSelectionEnable(RTE_MCI_DATA5_PAD); + RSI_EGPIO_PadReceiverEnable(RTE_MCI_DATA5_PIN); + RSI_EGPIO_PadDriverDisableState(RTE_MCI_DATA5_PIN,Pullup); + RSI_EGPIO_SetPinMux(EGPIO,RTE_MCI_DATA5_PORT,RTE_MCI_DATA5_PIN,RTE_MCI_DATA5_MODE); + + /*Configure data6 gpio pin*/ + RSI_EGPIO_PadSelectionEnable(RTE_MCI_DATA6_PAD); + RSI_EGPIO_PadReceiverEnable(RTE_MCI_DATA6_PIN); + RSI_EGPIO_PadDriverDisableState(RTE_MCI_DATA6_PIN,Pullup); + RSI_EGPIO_SetPinMux(EGPIO,RTE_MCI_DATA6_PORT,RTE_MCI_DATA6_PIN,RTE_MCI_DATA6_MODE); + +#endif /* RTE_SDMMC_BUS_WIDTH_8 */ +#endif /* RTE_SDMMC_BUS_WIDTH_4 */ + + MCI.flags = MCI_INIT; + + return ARM_DRIVER_OK; +} + +/** + * @fn int32_t MCI_UnInitialize(ARM_MCI_SignalEvent_t cb_event) + * @brief DeInitialize the Memory Card Interface. + * @param[in] none + * @return excecution status + */ +int32_t MCI_Uninitialize(void) +{ + MCI.flags = 0; + + /*Disable sdmem clock */ + SMIH->SMIH_CLOCK_CONTROL_REGISTER_b.SD_CLOCK_ENABLE = 0u; + + return ARM_DRIVER_OK; +} +boolean_t sdioh_wait_for_card_insert( ) +{ + /* Wait until card is stable */ + while(SMIH->SMIH_PRESENT_STATE_REGISTER_b.CARD_STATE_STABLE != 0x1); + return (boolean_t)SMIH->SMIH_PRESENT_STATE_REGISTER_b.CARD_INSERTED; +} + +/** + * @fn int32_t MCI_PowerControl(ARM_POWER_STATE state) + * @brief Control Memory Card Interface Power. + * @param[in] state Power state + * @return excecution status + */ +int32_t MCI_PowerControl(ARM_POWER_STATE state) +{ + switch (state) + { + case ARM_POWER_OFF: + /* Disable SDHC interrupt in NVIC */ + NVIC_DisableIRQ(SDMEM_IRQn); + + /* Clear flags */ + MCI.flags = MCI_POWER; + + /* Clear status */ + MCI.status.command_active = 0U; + MCI.status.command_timeout = 0U; + MCI.status.command_error = 0U; + MCI.status.transfer_active = 0U; + MCI.status.transfer_timeout = 0U; + MCI.status.transfer_error = 0U; + MCI.status.sdio_interrupt = 0U; + MCI.status.ccs = 0U; + break; + + case ARM_POWER_FULL: + if ((MCI.flags & MCI_POWER) == 0) + { + /* Clear response variable */ + MCI.response = NULL; + + /* sleepclock prog */ + *(volatile uint32_t *) (0x46000024) = (0x0<<21); + + /* wait for clock switch */ + while((M4CLK->PLL_STAT_REG_b.SLEEP_CLK_SWITCHED) != 1); + + /* Wait for card insert */ + while (sdioh_wait_for_card_insert()==0); + + /* enable adma*/ + SMIH->SMIH_HOST_CONTROL_1_REGISTER_b.DMA_SELECT = 0x2; + + /* Enable normal interrupts*/ + SMIH->SMIH_NORMAL_INTERRUPT_STATUS_ENABLE_REGISTER = ( + COMMAND_COMPLETE_STATUS_ENABLE | + TRANSFER_COMPLETE_STATUS_ENABLE | + BLOCK_GAP_EVENT_STATUS_ENABLE | + DMA_INTERRUPT_STATUS_ENABLE | + BUFFER_WRITE_READY_STATUS_ENABLE| + BUFFER_READ_READY_STATUS_ENABLE | + CARD_INSERTION_STATUS_ENABLE | + CARD_REMOVAL_STATUS_ENABLE | + CARD_INTERRUPT_STATUS_ENABLE | + INT_A_STATUS_ENABLE | + INT_B_STATUS_ENABLE | + INT_C_STATUS_ENABLE | + RE_TUNING_EVENT_STATUS_ENABLE ); + + /* Enable error interrupts*/ + SMIH->SMIH_ERROR_INTERRUPT_STATUS_ENABLE_REGISTER = ( + COMMAND_TIMEOUT_ERROR_STATUS_ENABLE | + COMMAND_CRC_ERROR_STATUS_ENABLE | + COMMAND_END_BIT_ERROR_STATUS_ENABLE | + COMMAND_INDEX_ERROR_STATUS_ENABLE | + DATA_TIMEOUT_ERROR_STATUS_ENABLE | + DATA_CRC_ERROR_STATUS_ENABLE | + DATA_END_BIT_ERROR_STATUS_ENABLE | + CURRENT_LIMIT_ERROR_STATUS_ENABLE | + AUTO_CMD_ERROR_STATUS_ENABLE | + ADMA_ERROR_STATUS_ENABLE | + TUNING_ERROR_STATUS_ENABLE ); + + /* Enable normal interrupts signals*/ + SMIH->SMIH_NORMAL_INTERRUPT_SIGNAL_ENABLE_REGISTER = (COMMAND_COMPLETE_SIGNAL_ENABLE | + TRANSFER_COMPLETE_SIGNAL_ENABLE | + BUFFER_WRITE_READY_SIGNAL_ENABLE | + BUFFER_READ_READY_SIGNAL_ENABLE | + CARD_REMOVAL_SIGNAL_ENABLE ); + + SMIH->SMIH_ERROR_INTERRUPT_SIGNAL_ENABLE_REGISTER = 0x1; + + /* select voltage to 3.3v*/ + SMIH->SMIH_POWER_CONTROL_REGISTER_b.SD_BUS_VOLTAGE_SELECT = 7U; + + /*power on bus*/ + SMIH->SMIH_POWER_CONTROL_REGISTER_b.SD_BUS_POWER = 0x1; + + /*configure data timeout counter value*/ + SMIH->SMIH_TIMEOUT_CONTROL_REGISTER_b.DATA_TIMEOUT_COUNTER_VALUE = 0xE; + + /* NVIC Enable*/ + NVIC_ClearPendingIRQ (SDMEM_IRQn); + NVIC_EnableIRQ (SDMEM_IRQn); + + MCI.flags |= MCI_POWER; + } + break; + case ARM_POWER_LOW: + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + return ARM_DRIVER_OK; +} + +/** + * @fn int32_t MCI_CardPower(uint32_t voltage) + * @brief Set Memory Card Power supply voltage. + * @param[in] voltage : Memory Card Power supply voltage + * @return excecution status + */ +int32_t MCI_CardPower(uint32_t voltage) +{ + if ((MCI.flags & MCI_POWER) == 0U) + { + return ARM_DRIVER_ERROR; + } + return ARM_DRIVER_ERROR_UNSUPPORTED; +} + +/** + * @fn int32_t MCI_ReadCD(void) + * @brief Read Card Detect (CD) state. + * @param[in] none + * @return excecution status + */ +int32_t MCI_ReadCD(void) +{ + if(RTE_MCI_CD_PIN != 0) + { + if (MCI.flags & MCI_POWER) { + if((RSI_EGPIO_GetPin(EGPIO,RTE_MCI_CD_PORT,RTE_MCI_CDD_PIN) == 0)) + { + return (1); + } + } + } + return (0); +} + +/** + * @fn int32_t MCI_ReadWP(void) + * @brief Read Write Protect (WP) state. + * @param[in] none + * @return excecution status + */ +int32_t MCI_ReadWP(void) +{ + if(RTE_MCI_WP_PIN != 0) + { + if (MCI.flags & MCI_POWER) { + if((RSI_EGPIO_GetPin(EGPIO,RTE_MCI_WP_PORT,RTE_MCI_WPP_PIN) == 0)) + { + return (1); + } + } + } + return (0); +} + +/** + * @fn int32_t MCI_SendCommand(uint32_t cmd, uint32_t arg, uint32_t flags, uint32_t *response) + * @brief Send Command to card and get the response. + * @param[in] cmd : Memory Card command + * @param[in] arg : Command argument + * @param[in] flags : Command flags + * @param[in] response : Pointer to buffer for response + * @return excecution status + */ +int32_t MCI_SendCommand(uint32_t cmd, uint32_t arg, uint32_t flags, uint32_t *response) +{ + MCI_COMMAND_FRAME_CONFIG_T CommandCfg = { 0 }; + MCI_DATA_CONFIG_T DataCfg = { 0 }; + uint32_t i=0; + if (((flags & MCI_RESPONSE_EXPECTED) != 0U) && (response == NULL)) + { + return ARM_DRIVER_ERROR_PARAMETER; + } + if ((MCI.flags & MCI_SETUP) == 0U) + { + return ARM_DRIVER_ERROR; + } + if (MCI.status.command_active) + { + return ARM_DRIVER_ERROR_BUSY; + } + /* wait for data line free */ + if (flags & ARM_MCI_TRANSFER_DATA) { + + while( SMIH->SMIH_PRESENT_STATE_REGISTER_b.COMMAND_INHIBIT_DAT == 1); + } + while(SMIH->SMIH_PRESENT_STATE_REGISTER_b.COMMAND_INHIBIT_CMD == 1); + + MCI.status.command_active = 1U; + MCI.status.command_timeout = 0U; + MCI.status.command_error = 0U; + MCI.status.transfer_timeout = 0U; + MCI.status.transfer_error = 0U; + MCI.status.ccs = 0U; + + if (flags & ARM_MCI_CARD_INITIALIZE) + { + /* Configure sdmem internal clock */ + RSI_MCI_ClockCnfig(400000); + + /*wait for some time*/ + for(i=0;i<20000;i++); + } + CommandCfg.argument =arg; + CommandCfg.cmdIndex = cmd & 0xFF; + DataCfg.blockSize = MCI.bl_sz; + DataCfg.blockCount = MCI.bl_cnt; + + if (CommandCfg.cmdIndex == 0x0C) + { + //abort command + CommandCfg.cmdType = 3; + } + MCI.response = response; + MCI.flags &= ~MCI_RESP_LONG; + + switch (flags & ARM_MCI_RESPONSE_Msk) + { + case ARM_MCI_RESPONSE_NONE: + /* No response expected */ + break; + case ARM_MCI_RESPONSE_SHORT: + /* Short response expected */ + CommandCfg.responseType = MCI_RESPONSE_48BIT; + break; + case ARM_MCI_RESPONSE_SHORT_BUSY: + /* Short response with busy expected */ + CommandCfg.responseType = MCI_RESPONSE_48BIT_BUSY_CHECK; + break; + case ARM_MCI_RESPONSE_LONG: + MCI.flags |= MCI_RESP_LONG; + /* Long response expected */ + CommandCfg.responseType = MCI_RESPONSE_136BIT; + break; + default: + return ARM_DRIVER_ERROR; + } + if (flags & ARM_MCI_RESPONSE_INDEX) + { + /* Check for command index error */ + CommandCfg.checkCmdIndex = 1; + } + if (flags & ARM_MCI_RESPONSE_CRC) + { + /* Check for CRC error */ + CommandCfg.checkCmdCrc = 1; + } + + DataCfg.admaDespTableAddress = (uint32_t)&Adma2DescriptorTable[0]; + if (flags & ARM_MCI_TRANSFER_DATA) + { + /* Enable data transfer */ + CommandCfg.dataPresent = 1; + if (MCI.flags & MCI_DATA_READ) + { + /* Read transfer */ + DataCfg.dataTransferDirection = MCI_READ_DIRECTION; + } + if(MCI.flags & MCI_DATA_MULB) + { + /* Multiple block transfer */ + DataCfg.blockCountEnable = 1; + DataCfg.multiBlock = 1; + } + MCI.status.transfer_active = 1U; + } + /* initialize data transfer */ + RSI_MCI_DataTransferInitialization(&DataCfg); + + /* send command */ + RSI_MCI_SendCommand(&CommandCfg); + + return ARM_DRIVER_OK; +} + +/** + * @fn int32_t MCI_SetupTransfer(uint8_t *data, uint32_t block_count, uint32_t block_size, uint32_t mode) + * @brief Setup read or write transfer operation. + * @param[in] data : Pointer to data block(s) to be written or read + * @param[in] block_count : Number of blocks + * @param[in] block_size : Size of a block in bytes + * @param[in] mode : Transfer mode + * @return excecution status + */ +int32_t MCI_SetupTransfer(uint8_t *data, uint32_t block_count, uint32_t block_size, uint32_t mode) +{ + if ((data == NULL) || (block_count == 0U) || (block_size == 0U)) + { + return ARM_DRIVER_ERROR_PARAMETER; + } + if ((MCI.flags & MCI_SETUP) == 0U) + { + return ARM_DRIVER_ERROR; + } + if (MCI.status.transfer_active) + { + return ARM_DRIVER_ERROR_BUSY; + } + if (mode & ARM_MCI_TRANSFER_STREAM) + { + /* Stream or SDIO multibyte data transfer not supported by peripheral */ + return ARM_DRIVER_ERROR; + } + + SMIH->TRANSFER_MODE_REGISTER_b.DMA_ENABLE=0x1; + + memset(Adma2DescriptorTable, 0x0, sizeof(Adma2DescriptorTable)); + + /*Fill adma descriptor table*/ + Adma2DescriptorTable[0].attributeValid = 1; + Adma2DescriptorTable[0].attributeEnd = 1; + Adma2DescriptorTable[0].attributeInt = 0; + Adma2DescriptorTable[0].attributeAct = 2; + Adma2DescriptorTable[0].length = (block_size * block_count); + Adma2DescriptorTable[0]._32BIT_Adress = (uint32_t)data; + + /* Set transfer block count and size */ + MCI.bl_cnt = block_count; + MCI.bl_sz = block_size; + + if (block_count == 1) + { + /* Single block transfer */ + MCI.flags &= ~MCI_DATA_MULB; + } + else + { + /* Multiple block transfer */ + MCI.flags |= MCI_DATA_MULB; + } + + if (mode & ARM_MCI_TRANSFER_WRITE) + { + /* Direction: From controller to card */ + MCI.flags &= ~MCI_DATA_READ; + } + else + { + /* Direction: From card to controller */ + MCI.flags |= MCI_DATA_READ; + } + while( SMIH->SMIH_PRESENT_STATE_REGISTER_b.COMMAND_INHIBIT_DAT == 0x1); + return (ARM_DRIVER_OK); +} + +/** + * @fn int32_t MCI_AbortTransfer(void) + * @brief Abort current read/write data transfer. + * @param[in] none + * @return excecution status + */ +int32_t MCI_AbortTransfer(void) +{ + int32_t status; + if ((MCI.flags & MCI_SETUP) == 0U) + { + return ARM_DRIVER_ERROR; + } + status = ARM_DRIVER_OK; + + /* Disable normal interrupts*/ + SMIH->SMIH_NORMAL_INTERRUPT_STATUS_ENABLE_REGISTER &= ~( + COMMAND_COMPLETE_STATUS_ENABLE | + TRANSFER_COMPLETE_STATUS_ENABLE | + BLOCK_GAP_EVENT_STATUS_ENABLE | + DMA_INTERRUPT_STATUS_ENABLE | + BUFFER_WRITE_READY_STATUS_ENABLE| + BUFFER_READ_READY_STATUS_ENABLE | + CARD_INSERTION_STATUS_ENABLE | + CARD_REMOVAL_STATUS_ENABLE | + CARD_INTERRUPT_STATUS_ENABLE | + INT_A_STATUS_ENABLE | + INT_B_STATUS_ENABLE | + INT_C_STATUS_ENABLE | + RE_TUNING_EVENT_STATUS_ENABLE ); + + /* Disable error interrupts*/ + SMIH->SMIH_ERROR_INTERRUPT_STATUS_ENABLE_REGISTER &= ~ ( + COMMAND_TIMEOUT_ERROR_STATUS_ENABLE | + COMMAND_CRC_ERROR_STATUS_ENABLE | + COMMAND_END_BIT_ERROR_STATUS_ENABLE | + COMMAND_INDEX_ERROR_STATUS_ENABLE | + DATA_TIMEOUT_ERROR_STATUS_ENABLE | + DATA_CRC_ERROR_STATUS_ENABLE | + DATA_END_BIT_ERROR_STATUS_ENABLE | + CURRENT_LIMIT_ERROR_STATUS_ENABLE | + AUTO_CMD_ERROR_STATUS_ENABLE | + ADMA_ERROR_STATUS_ENABLE | + TUNING_ERROR_STATUS_ENABLE ); + + /* Disable normal interrupts signals*/ + SMIH->SMIH_NORMAL_INTERRUPT_SIGNAL_ENABLE_REGISTER &= ~ (COMMAND_COMPLETE_SIGNAL_ENABLE | + TRANSFER_COMPLETE_SIGNAL_ENABLE | + BUFFER_WRITE_READY_SIGNAL_ENABLE | + BUFFER_READ_READY_SIGNAL_ENABLE | + CARD_REMOVAL_SIGNAL_ENABLE ); + SMIH->SMIH_ERROR_INTERRUPT_SIGNAL_ENABLE_REGISTER = 0x0; + + MCI.status.command_active = 0U; + MCI.status.transfer_active = 0U; + MCI.status.sdio_interrupt = 0U; + MCI.status.ccs = 0U; + + return status; +} + +/** + * @fn int32_t MCI_Control(uint32_t control, uint32_t arg) + * @brief Control MCI Interface. + * @param[in] control : Operation + * @param[in] arg : Argument of operation (optional) + * @return excecution status + */ +int32_t MCI_Control(uint32_t control, uint32_t arg) +{ + if ((MCI.flags & MCI_POWER) == 0U) + { + return ARM_DRIVER_ERROR; + } + switch (control) + { + case ARM_MCI_BUS_SPEED: + /* Bus speed configured */ + MCI.flags |= MCI_SETUP; + break; + case ARM_MCI_BUS_SPEED_MODE: + switch (arg) + { + case ARM_MCI_BUS_DEFAULT_SPEED: + /* Speed mode up to 25MHz */ + RSI_MCI_ClockCnfig(25000000); + break; + case ARM_MCI_BUS_HIGH_SPEED: + /* Speed mode up to 50MHz */ + break; + default: return ARM_DRIVER_ERROR_UNSUPPORTED; + } + break; + + case ARM_MCI_BUS_CMD_MODE: + switch (arg) + { + + case ARM_MCI_BUS_CMD_OPEN_DRAIN: + /* Configure command line in open-drain mode */ + break; + + case ARM_MCI_BUS_CMD_PUSH_PULL: + /* Configure command line in push-pull mode */ + break; + + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + break; + + case ARM_MCI_BUS_DATA_WIDTH: + switch (arg) + { + case ARM_MCI_BUS_DATA_WIDTH_1: + SMIH->SMIH_HOST_CONTROL_1_REGISTER_b.DATA_TRANSFER_WIDTH =0x0; + break; + case ARM_MCI_BUS_DATA_WIDTH_4: + SMIH->SMIH_HOST_CONTROL_1_REGISTER_b.DATA_TRANSFER_WIDTH =0x1; + break; + case ARM_MCI_BUS_DATA_WIDTH_8: + break; + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + break; + case ARM_MCI_CONTROL_CLOCK_IDLE: + if (arg) + { + + } + else + { + + } + break; + + case ARM_MCI_DATA_TIMEOUT: + SMIH->SMIH_TIMEOUT_CONTROL_REGISTER_b.DATA_TIMEOUT_COUNTER_VALUE=0xE; + break; + + case ARM_MCI_MONITOR_SDIO_INTERRUPT: + MCI.status.sdio_interrupt = 0U; + + /* Enable card interrupt*/ + SMIH->SMIH_NORMAL_INTERRUPT_STATUS_ENABLE_REGISTER |= CARD_INTERRUPT_STATUS_ENABLE; + + break; + + default: return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + return ARM_DRIVER_OK; +} + +/** + * @fn ARM_MCI_STATUS MCI_GetStatus(void) + * @brief Get MCI status. + * @param[in] none + * @return ARM_MCI_STATUS + */ +ARM_MCI_STATUS MCI_GetStatus(void) +{ + return MCI.status; +} + +/*SDHC IRQ Handler*/ +void SDHC_IRQHandler (void) +{ + uint32_t msk, event; + uint16_t normal_intr_status; + uint16_t error_intr_status; + uint32_t int_status; + + event = 0U; + /*read normal interrupt status reg*/ + normal_intr_status = SMIH->SMIH_NORMAL_INTERRUPT_STATUS_REGISTER; + + /*read error interrupt status reg*/ + error_intr_status = SMIH->SMIH_ERROR_INTERRUPT_STATUS_REGISTER; + + int_status = error_intr_status << 16; + int_status |= normal_intr_status; + + if (int_status & COMMANDS_INTERRUPTS) + { + int_status &= COMMANDS_INTERRUPTS; + + /* Command interrupts status */ + MCI.status.command_active = 0U; + + if ((int_status & ((COMMAND_TIMEOUT_ERROR_STATUS_ENABLE |COMMAND_CRC_ERROR_STATUS_ENABLE)<<16)) == (COMMAND_TIMEOUT_ERROR_STATUS_ENABLE <<16)) + { + /* command timeout error */ + MCI.status.command_timeout = 1U; + event = ARM_MCI_EVENT_COMMAND_TIMEOUT; + } + else if ((int_status & ((COMMAND_TIMEOUT_ERROR_STATUS_ENABLE | COMMAND_CRC_ERROR_STATUS_ENABLE) <<16)) == (COMMAND_CRC_ERROR_STATUS_ENABLE << 16)) + { + /* cmd crc error */ + MCI.status.command_error = 1U; + event = ARM_MCI_EVENT_COMMAND_ERROR; + } + else if (int_status & (COMMAND_INDEX_ERROR_STATUS_ENABLE << 16)) + { + /* Command index error */ + MCI.status.command_error = 1U; + event = ARM_MCI_EVENT_COMMAND_ERROR; + } + else if (int_status & (COMMAND_END_BIT_ERROR_STATUS_ENABLE << 16)) + { + /* Command end bit error */ + event = ARM_MCI_EVENT_COMMAND_ERROR; + } + else + { + msk = COMMAND_COMPLETE_STATUS_ENABLE | (( COMMAND_TIMEOUT_ERROR_STATUS_ENABLE | COMMAND_CRC_ERROR_STATUS_ENABLE ) << 16); + if ((int_status & msk) == COMMAND_COMPLETE_STATUS_ENABLE) + { + /* Command complete */ + if (MCI.response) + { + if (MCI.flags & MCI_RESP_LONG) + { + /* read response registers */ + MCI.response[3] = ((SMIH->SMIH_RESPONSE_REGISTER7 | SMIH->SMIH_RESPONSE_REGISTER6) << 8) | ((SMIH->SMIH_RESPONSE_REGISTER5 | SMIH->SMIH_RESPONSE_REGISTER4) >> 24); + MCI.response[2] = ((SMIH->SMIH_RESPONSE_REGISTER5 | SMIH->SMIH_RESPONSE_REGISTER4) << 8) | ((SMIH->SMIH_RESPONSE_REGISTER3 | SMIH->SMIH_RESPONSE_REGISTER2) >> 24); + MCI.response[1] = ((SMIH->SMIH_RESPONSE_REGISTER3 | SMIH->SMIH_RESPONSE_REGISTER2) << 8) | ((SMIH->SMIH_RESPONSE_REGISTER1 | SMIH->SMIH_RESPONSE_REGISTER0) >> 24); + MCI.response[0] = ((SMIH->SMIH_RESPONSE_REGISTER1 |SMIH->SMIH_RESPONSE_REGISTER0) << 8); + } + else + { + MCI.response[0] = SDMEM_RESPONSE_REG; + } + } + event = ARM_MCI_EVENT_COMMAND_COMPLETE; + } + } + } + if (int_status & DATA_INTERRUPTS) + { + int_status &= DATA_INTERRUPTS; + /* Data interrupts status */ + MCI.status.transfer_active = 0U; + + msk = ((DATA_CRC_ERROR_STATUS_ENABLE | DATA_END_BIT_ERROR_STATUS_ENABLE | ADMA_ERROR_STATUS_ENABLE) << 16); + if (int_status & msk) { + /* data crc or data end bit or DMA errors */ + MCI.status.transfer_error = 1U; + event = ARM_MCI_EVENT_TRANSFER_ERROR; + } + else if (int_status & (DATA_TIMEOUT_ERROR_STATUS_ENABLE << 16)) { + /* Data transfer timeout error */ + MCI.status.transfer_timeout = 1U; + event = ARM_MCI_EVENT_TRANSFER_TIMEOUT; + } + else { + if (int_status & TRANSFER_COMPLETE_STATUS_ENABLE) { + /* transfer complete interrupt */ + event = ARM_MCI_EVENT_TRANSFER_COMPLETE; + } + } + } + else { + if (int_status & CARD_INTERRUPT_STATUS_ENABLE) { + /* SDIO interrupt */ + MCI.status.sdio_interrupt = 1U; + event = ARM_MCI_EVENT_SDIO_INTERRUPT; + + /* Disable SDIO Interrupt */ + SMIH->SMIH_NORMAL_INTERRUPT_STATUS_ENABLE_REGISTER = CARD_INTERRUPT_STATUS_ENABLE; + } + } + /*clear interrupts*/ + SDMEM_INTR_STATUS_REG = int_status; + + /*send events*/ + if (event && (MCI.cb_event != NULL)) { + MCI.cb_event (event); + } +} + +/** + * @fn void RSI_MCI_ClockCnfig(uint32_t freq) + * @brief This API is used to configure the MCI clock + */ +void RSI_MCI_ClockCnfig(uint32_t freq) +{ + uint16_t u16Div = 0; + + uint32_t u32ClockInput = RTE_INPUT_CLOCK; + + u16Div = u32ClockInput /2/ (freq); + + /*Disable sdmem clock */ + SMIH->SMIH_CLOCK_CONTROL_REGISTER_b.SD_CLOCK_ENABLE = 0u; + + /*set division value to the card*/ + SMIH->SMIH_CLOCK_CONTROL_REGISTER_b.SDCLK_FREQUENCY_SELECT = (u16Div & 0xFFu); + SMIH->SMIH_CLOCK_CONTROL_REGISTER_b.UPPER_BITS_OF_SDCLK_FREQUENCY_SELECT = ((u16Div >> 8u) & 0x03u); + + /*Enable Smih internal clock*/ + SMIH->SMIH_CLOCK_CONTROL_REGISTER_b.INTERNAL_CLOCK_ENABLE = 0x1; + while(0x1 != SMIH->SMIH_CLOCK_CONTROL_REGISTER_b.INTERNAL_CLOCK_STABLE); + + /*enables SDMEM clock*/ + SMIH->SMIH_CLOCK_CONTROL_REGISTER_b.SD_CLOCK_ENABLE = 0x1; +} + +/** + * @fn rsi_error_t RSI_MCI_SendCommand( MCI_COMMAND_FRAME_CONFIG_T* pConfig ) + * @brief This API is used to send the command. + * @param[in] pConfig pointer to the command structure + * @return RSI_OK If command sent properly. + * INVALID_PARAMETERS If pConfig==NULL + */ +rsi_error_t RSI_MCI_SendCommand(MCI_COMMAND_FRAME_CONFIG_T* pConfig ) +{ + MCI_COMMAND_REG_T CmdData; + + memset(&CmdData, 0, sizeof(CmdData)); + + if (pConfig == NULL) + { + return INVALID_PARAMETERS ; + } + /* Set command CRC check */ + if(pConfig->checkCmdCrc) + { + CmdData.cmdCrcCheckEnable = 0x1; + } + else + { + CmdData.cmdCrcCheckEnable = 0x0; + } + /* Set command index check */ + if(pConfig->checkCmdIndex) + { + CmdData.cmdIndexCheckEnable = 0x1; + } + else + { + CmdData.cmdIndexCheckEnable = 0x0; + } + + /* Set data present or not when sending the command */ + if(pConfig->dataPresent) + { + CmdData.dataPresentSelect = 0x1; + } + else + { + CmdData.dataPresentSelect = 0x0; + } + /* Configure command type */ + switch (pConfig->cmdType) + { + case MCI_NORMAL_CMD: + CmdData.cmdType = 0u; + break; + case MCI_SUSPEND_CMD: + CmdData.cmdType = 1u; + break; + case MCI_RESUME_CMD: + CmdData.cmdType = 2u; + break; + case MCI_ABORT_CMD: + CmdData.cmdType = 3u; + break; + default: + return INVALID_PARAMETERS ; + } + /* Set command response type */ + switch (pConfig->responseType) + { + case MCI_RESPONSE_NONE: + CmdData.respType = 0u; + break; + case MCI_RESPONSE_136BIT: + CmdData.respType = 1u; + break; + case MCI_RESPONSE_48BIT: + CmdData.respType = 2u; + break; + case MCI_RESPONSE_48BIT_BUSY_CHECK: + CmdData.respType = 3u; + break; + default: + return INVALID_PARAMETERS ; + } + + /* Set command index */ + CmdData.cmdIndex = pConfig->cmdIndex; + + /* Auto command setting */ + switch (pConfig->autoCmdType) + { + case MCI_DISABLE_AUTO_CMD : + SMIH->TRANSFER_MODE_REGISTER_b.AUTO_CMD_ENABLE = 0u; + break; + case MCI_ENABLE_AUTO_CMD12 : + SMIH->TRANSFER_MODE_REGISTER_b.AUTO_CMD_ENABLE = 1u; + break; + case MCI_ENABLE_AUTO_CMD23 : + SMIH->TRANSFER_MODE_REGISTER_b.AUTO_CMD_ENABLE = 2u; + break; + default: + return INVALID_PARAMETERS ; + } + /* Configure argument register */ + SMIH->SMIH_ARGUMENT1_REGISTER = pConfig->argument; + + if(pConfig->cmdIndex == 5) + { + if((pConfig->argument & (1 << 24))) + { + SMIH->SMIH_HOST_CONTROL_2_REGISTER = (1 << 3); + } + } + /* assign fiiled data to the command register */ + SMIH->SMIH_COMMAND_REGISTER = *((uint16_t *)&CmdData); + return RSI_OK; +} +/** + * @fn rsi_error_t RSI_MCI_DataTransferInitialization(MCI_DATA_CONFIG_T* pDataConfig) + * @brief This API is used to initialize the data transfer(this must be called before data transfer). + * @param[in] pDataConfig pointer to the data transfer configuration + * @return RSI_OK data initialized properly. + * INVALID_PARAMETERS If pDataConfig==NULL + */ +rsi_error_t RSI_MCI_DataTransferInitialization(MCI_DATA_CONFIG_T* pDataConfig) +{ + if (pDataConfig == 0) + { + return INVALID_PARAMETERS ; + } + /* Configure multiple block or single block transfer */ + if(pDataConfig->multiBlock) + { + SMIH->TRANSFER_MODE_REGISTER_b.MULTI_OR_SINGLE_BLOCK_SELECT = 0x1; + } + else + { + SMIH->TRANSFER_MODE_REGISTER_b.MULTI_OR_SINGLE_BLOCK_SELECT = 0x0; + } + /* Confgure data transfer direction */ + if(pDataConfig->dataTransferDirection) + { + SMIH->TRANSFER_MODE_REGISTER_b.DATA_TRANSFER_DIRECTION_SELECT = 0x1; + } + else + { + SMIH->TRANSFER_MODE_REGISTER_b.DATA_TRANSFER_DIRECTION_SELECT = 0x0; + } + /* Configure block size */ + SMIH->SMIH_BLOCK_SIZE_REGISTER_b.TRANSFER_BLOCK_SIZE = pDataConfig->blockSize; + + /* Configure block count */ + if(pDataConfig->blockCount == 0) + { + SMIH->SMIH_BLOCK_COUNT_REGISTER = 1; + } + else + { + SMIH->SMIH_BLOCK_COUNT_REGISTER = pDataConfig->blockCount; + } + /*enable block count*/ + if(pDataConfig->blockCountEnable) + { + SMIH->TRANSFER_MODE_REGISTER_b.BLOCK_COUNT_ENABLE = 0x1; + } + else + { + SMIH->TRANSFER_MODE_REGISTER_b.BLOCK_COUNT_ENABLE = 0x0; + } + /* Enable DMA mode */ + if(pDataConfig->dmaEnable) + { + SMIH->TRANSFER_MODE_REGISTER_b.DMA_ENABLE = 0x1; + } + else + { + SMIH->TRANSFER_MODE_REGISTER_b.DMA_ENABLE = 0x1; + } + + /* Configure descriptor table for ADMA */ + SMIH->SMIH_ADMA_SYSTEM_ADDRESS0_REGISTER = (uint16_t) pDataConfig->admaDespTableAddress; + SMIH->SMIH_ADMA_SYSTEM_ADDRESS1_REGISTER = (uint16_t)(pDataConfig->admaDespTableAddress >> 16u); + + return RSI_OK; +} +// End MCI Interface +ARM_DRIVER_MCI Driver_MCI0 = +{ + MCI_GetVersion, + MCI_GetCapabilities, + MCI_Initialize, + MCI_Uninitialize, + MCI_PowerControl, + MCI_CardPower, + MCI_ReadCD, + MCI_ReadWP, + MCI_SendCommand, + MCI_SetupTransfer, + MCI_AbortTransfer, + MCI_Control, + MCI_GetStatus +}; +#endif diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/MCI.h b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/MCI.h new file mode 100644 index 000000000..bf841d135 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/MCI.h @@ -0,0 +1,195 @@ + /* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2014 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * + * $Date: 24. Nov 2014 + * $Revision: V2.02 + * + * Project: MCI (Memory Card Interface) + * Driver definitions + * -------------------------------------------------------------------------- */ +/* + * Version 1.00 + * Initial release + */ + + +#include "Driver_MCI.h" + +#include "RTE_Device.h" + + +typedef void (*ARM_MCI_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_MCI_SignalEvent : Signal MCI Event. + + + +/* MCI Driver State Definition */ +typedef struct MCI_Ctrl { + ARM_MCI_SignalEvent_t cb_event; /* Driver event callback function */ + ARM_MCI_STATUS status; /* Driver status */ + uint32_t *response; /* Pointer to response buffer */ + uint32_t bl_sz; + uint32_t bl_cnt; + uint8_t volatile flags; /* Driver state flags */ +} MCI_CTRL; + +/* Driver flag definitions */ +#define MCI_INIT ((uint8_t)0x01 ) /* MCI initialized */ +#define MCI_POWER ((uint8_t)0x02 ) /* MCI powered on */ +#define MCI_SETUP ((uint8_t)0x04 ) /* MCI configured */ +#define MCI_RESP_LONG ((uint8_t)0x08 ) /* Long response expected */ + + + +#define MCI_DATA_READ ((uint8_t)0x10) /* Read transfer */ +#define MCI_DATA_MULB ((uint8_t)0x20) /* Multiple block transfer */ + +/* Normal interrupt status enable reg */ +#define COMMAND_COMPLETE_STATUS_ENABLE BIT(0) +#define TRANSFER_COMPLETE_STATUS_ENABLE BIT(1) +#define BLOCK_GAP_EVENT_STATUS_ENABLE BIT(2) +#define DMA_INTERRUPT_STATUS_ENABLE BIT(3) +#define BUFFER_WRITE_READY_STATUS_ENABLE BIT(4) +#define BUFFER_READ_READY_STATUS_ENABLE BIT(5) +#define CARD_INSERTION_STATUS_ENABLE BIT(6) +#define CARD_REMOVAL_STATUS_ENABLE BIT(7) +#define CARD_INTERRUPT_STATUS_ENABLE BIT(8) +#define INT_A_STATUS_ENABLE BIT(9) +#define INT_B_STATUS_ENABLE BIT(10) +#define INT_C_STATUS_ENABLE BIT(11) +#define RE_TUNING_EVENT_STATUS_ENABLE BIT(12) + +/* Error interrupt status enables */ +#define COMMAND_TIMEOUT_ERROR_STATUS_ENABLE BIT(0) +#define COMMAND_CRC_ERROR_STATUS_ENABLE BIT(1) +#define COMMAND_END_BIT_ERROR_STATUS_ENABLE BIT(2) +#define COMMAND_INDEX_ERROR_STATUS_ENABLE BIT(3) +#define DATA_TIMEOUT_ERROR_STATUS_ENABLE BIT(4) +#define DATA_CRC_ERROR_STATUS_ENABLE BIT(5) +#define DATA_END_BIT_ERROR_STATUS_ENABLE BIT(6) +#define CURRENT_LIMIT_ERROR_STATUS_ENABLE BIT(7) +#define AUTO_CMD_ERROR_STATUS_ENABLE BIT(8) +#define ADMA_ERROR_STATUS_ENABLE BIT(9) +#define TUNING_ERROR_STATUS_ENABLE BIT(10) + +/* Normal interrupt status enable reg */ +#define COMMAND_COMPLETE_SIGNAL_ENABLE BIT(0) +#define TRANSFER_COMPLETE_SIGNAL_ENABLE BIT(1) +#define BLOCK_GAP_EVENT_SIGNAL_ENABLE BIT(2) +#define DMA_INTERRUPT_SIGNAL_ENABLE BIT(3) +#define BUFFER_WRITE_READY_SIGNAL_ENABLE BIT(4) +#define BUFFER_READ_READY_SIGNAL_ENABLE BIT(5) +#define CARD_INSERTION_SIGNAL_ENABLE BIT(6) +#define CARD_REMOVAL_SIGNAL_ENABLE BIT(7) +#define CARD_INTERRUPT_SIGNAL_ENABLE BIT(8) +#define INT_A_SIGNAL_ENABLE BIT(9) +#define INT_B_SIGNAL_ENABLE BIT(10) +#define INT_C_SIGNALS_ENABLE BIT(11) +#define RE_TUNING_EVENT_SIGNAL_ENABLE BIT(12) + +typedef struct MCI_COMMAND_FRAME_CONFIG +{ + uint8_t cmdIndex; + uint32_t argument; + uint8_t cmdType; + boolean_t dataPresent; + boolean_t checkCmdIndex; + boolean_t checkCmdCrc; + uint8_t responseType; + uint8_t autoCmdType; +}MCI_COMMAND_FRAME_CONFIG_T; +typedef struct MCI_ADMA_DESC_TABLE +{ + uint16_t attributeValid :1; + uint16_t attributeEnd :1; + uint16_t attributeInt :1; + uint16_t reserved1 :1; + uint16_t attributeAct :2; + uint16_t reserved2 :10; + uint16_t length; + uint32_t _32BIT_Adress; +} MCI_ADMA_DESC_TABLE_T; + +/*Command type defines */ +#define MCI_ABORT_CMD 3 +#define MCI_RESUME_CMD 2 +#define MCI_SUSPEND_CMD 1 +#define MCI_NORMAL_CMD 0 + +#define MCI_DISABLE_AUTO_CMD 0 +#define MCI_ENABLE_AUTO_CMD12 1 +#define MCI_ENABLE_AUTO_CMD23 2 + +/*response type defines*/ +#define MCI_RESPONSE_NONE 0 +#define MCI_RESPONSE_136BIT 1 +#define MCI_RESPONSE_48BIT 2 +#define MCI_RESPONSE_48BIT_BUSY_CHECK 3 + +/*data direction defines*/ +#define MCI_WRITE_DIRECTION 0x0 +#define MCI_READ_DIRECTION 0x1 + +#define MCI_RESPONSE_EXPECTED (ARM_MCI_RESPONSE_SHORT | \ + ARM_MCI_RESPONSE_SHORT_BUSY | \ + ARM_MCI_RESPONSE_LONG) + + +/* MCI data configuration structure*/ +typedef struct MCI_DATA_CONFIG +{ + boolean_t multiBlock; + boolean_t dataTransferDirection; + uint16_t blockSize; + uint16_t blockCount; + boolean_t blockCountEnable; + boolean_t dmaEnable; + uint32_t admaDespTableAddress; + uint8_t dataTimeout; +}MCI_DATA_CONFIG_T; + +/* MCI command reg structure*/ +typedef struct MCI_COMMAND_REG +{ + uint16_t respType : 2; + uint16_t resrvd : 1; + uint16_t cmdCrcCheckEnable : 1; + uint16_t cmdIndexCheckEnable : 1; + uint16_t dataPresentSelect : 1; + uint16_t cmdType : 2; + uint16_t cmdIndex : 6; +} MCI_COMMAND_REG_T; + + +#define COMMANDS_INTERRUPTS (((COMMAND_TIMEOUT_ERROR_STATUS_ENABLE | COMMAND_CRC_ERROR_STATUS_ENABLE | COMMAND_END_BIT_ERROR_STATUS_ENABLE |COMMAND_INDEX_ERROR_STATUS_ENABLE | AUTO_CMD_ERROR_STATUS_ENABLE) << 16) | \ + COMMAND_COMPLETE_STATUS_ENABLE ) + +#define DATA_INTERRUPTS (((DATA_TIMEOUT_ERROR_STATUS_ENABLE |DATA_CRC_ERROR_STATUS_ENABLE |DATA_END_BIT_ERROR_STATUS_ENABLE ) << 16) | TRANSFER_COMPLETE_STATUS_ENABLE | \ + BUFFER_READ_READY_STATUS_ENABLE | \ + BUFFER_WRITE_READY_STATUS_ENABLE | \ + DMA_INTERRUPT_STATUS_ENABLE) + +#define SDMEM_INTR_STATUS_REG (*(uint32_t *)(0x20220000 + 0x30)) +#define SDMEM_RESPONSE_REG ((*(uint32_t *)(0x20220000 + 0x10)) ) + +/* Function Prototypes */ +void RSI_MCI_ClockCnfig(uint32_t freq); +rsi_error_t RSI_MCI_SendCommand(MCI_COMMAND_FRAME_CONFIG_T* pConfig ); +rsi_error_t RSI_MCI_DataTransferInitialization(MCI_DATA_CONFIG_T* pDataConfig); + diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/PHY_LAN8742A.c b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/PHY_LAN8742A.c new file mode 100644 index 000000000..c3ce23dff --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/PHY_LAN8742A.c @@ -0,0 +1,292 @@ + +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2016 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * + * $Date: 1 AUG 2017 + * $Revision: V1.0 + * + * Driver: Driver_ETH_PHYn (default: Driver_ETH_PHY0) + * Project: Ethernet Physical Layer Transceiver (PHY) + * Driver for LAN8742A + * ---------------------------------------------------------------------- + * Use the following configuration settings in the middleware component + * to connect to this driver. + * + * Configuration Setting Value + * --------------------- ----- + * Connect to hardware via Driver_ETH_PHY# = n (default: 0) + * -------------------------------------------------------------------- + * + */ + +#include "rsi_ccp_user_config.h" +#if defined(CHIP_9118) +#include "PHY_LAN8742A.h" +/* driver version */ + + +#define ARM_ETH_PHY_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,1) +#ifndef ETH_PHY_NUM +#define ETH_PHY_NUM 0 /* Default driver number */ +#endif + +#ifndef ETH_PHY_ADDR +#define ETH_PHY_ADDR 0x00 /* Default device address */ +#endif + + +/* Driver Version */ +static const ARM_DRIVER_VERSION DriverVersion = { + ARM_ETH_PHY_API_VERSION, + ARM_ETH_PHY_DRV_VERSION +}; + +/* Ethernet PHY control structure */ +static PHY_CTRL PHY = { NULL, NULL, 0, 0 }; + + +/** + \fn ARM_DRIVER_VERSION GetVersion (void) + \brief Get driver version. + \return \ref ARM_DRIVER_VERSION + */ +static ARM_DRIVER_VERSION GetVersion (void) { + return DriverVersion; +} + + +/** + \fn int32_t Initialize (ARM_ETH_PHY_Read_t fn_read, + ARM_ETH_PHY_Write_t fn_write) + \brief Initialize Ethernet PHY Device. + \param[in] fn_read : Pointer to \ref ARM_ETH_MAC_PHY_Read + \param[in] fn_write : Pointer to \ref ARM_ETH_MAC_PHY_Write + \return \ref execution_status + */ +static int32_t Initialize (ARM_ETH_PHY_Read_t fn_read, ARM_ETH_PHY_Write_t fn_write) { + + if ((fn_read == NULL) || (fn_write == NULL)) { return ARM_DRIVER_ERROR_PARAMETER; } + + if ((PHY.flags & PHY_INIT) == 0U) { + /* Register PHY read/write functions. */ + PHY.reg_rd = fn_read; + PHY.reg_wr = fn_write; + + PHY.bcr = 0U; + PHY.flags = PHY_INIT; + } + + return ARM_DRIVER_OK; +} + +/** + \fn int32_t Uninitialize (void) + \brief De-initialize Ethernet PHY Device. + \return \ref execution_status + */ +static int32_t Uninitialize (void) { + + PHY.reg_rd = NULL; + PHY.reg_wr = NULL; + PHY.bcr = 0U; + PHY.flags = 0U; + + return ARM_DRIVER_OK; +} + +/** + \fn int32_t PowerControl (ARM_POWER_STATE state) + \brief Control Ethernet PHY Device Power. + \param[in] state : Power state + \return \ref execution_status + */ +static int32_t PowerControl (ARM_POWER_STATE state) { + uint16_t val; + + switch (state) { + case ARM_POWER_OFF: + if ((PHY.flags & PHY_INIT) == 0U) { + /* Initialize must provide register access function pointers */ + return ARM_DRIVER_ERROR; + } + + PHY.flags &= ~PHY_POWER; + PHY.bcr = BCR_POWER_DOWN; + + return (PHY.reg_wr(ETH_PHY_ADDR, REG_BCR, PHY.bcr)); + + case ARM_POWER_FULL: + if ((PHY.flags & PHY_INIT) == 0U) { + return ARM_DRIVER_ERROR; + } + if (PHY.flags & PHY_POWER) { + return ARM_DRIVER_OK; + } + + /* Check Device Identification. */ + PHY.reg_rd(ETH_PHY_ADDR, REG_PHYIDR1, &val); + + if (val != PHY_ID1) { + /* Invalid PHY ID */ + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + PHY.reg_rd(ETH_PHY_ADDR, REG_PHYIDR2, &val); + + if ((val & 0xFFF0) != PHY_ID2) { + /* Invalid PHY ID */ + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + PHY.bcr = 0U; + + if (PHY.reg_wr(ETH_PHY_ADDR, REG_BCR, PHY.bcr) != ARM_DRIVER_OK) { + return ARM_DRIVER_ERROR; + } + + PHY.flags |= PHY_POWER; + + return ARM_DRIVER_OK; + + case ARM_POWER_LOW: + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } +} + +/** + \fn int32_t SetInterface (uint32_t interface) + \brief Set Ethernet Media Interface. + \param[in] interface : Media Interface type + \return \ref execution_status + */ +static int32_t SetInterface (uint32_t interface) { + + if ((PHY.flags & PHY_POWER) == 0U) { return ARM_DRIVER_ERROR; } + + switch (interface) { + case ARM_ETH_INTERFACE_RMII: + break; + case ARM_ETH_INTERFACE_MII: + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + return(0); +} + +/** + \fn int32_t SetMode (uint32_t mode) + \brief Set Ethernet PHY Device Operation mode. + \param[in] mode : Operation Mode + \return \ref execution_status + */ +static int32_t SetMode (uint32_t mode) { + uint16_t val; + + if ((PHY.flags & PHY_POWER) == 0U) { return ARM_DRIVER_ERROR; } + + val = PHY.bcr & BCR_POWER_DOWN; + + switch (mode & ARM_ETH_PHY_SPEED_Msk) { + case ARM_ETH_PHY_SPEED_10M: + break; + case ARM_ETH_PHY_SPEED_100M: + val |= BCR_SPEED_SEL; + break; + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + switch (mode & ARM_ETH_PHY_DUPLEX_Msk) { + case ARM_ETH_PHY_DUPLEX_HALF: + break; + case ARM_ETH_PHY_DUPLEX_FULL: + val |= BCR_DUPLEX; + break; + } + + if (mode & ARM_ETH_PHY_AUTO_NEGOTIATE) { + val |= BCR_ANEG_EN; + } + + if (mode & ARM_ETH_PHY_LOOPBACK) { + val |= BCR_LOOPBACK; + } + + if (mode & ARM_ETH_PHY_ISOLATE) { + val |= BCR_ISOLATE; + } + + PHY.bcr = val; + + return (PHY.reg_wr(ETH_PHY_ADDR, REG_BCR, PHY.bcr)); +} + +/** + \fn ARM_ETH_LINK_STATE GetLinkState (void) + \brief Get Ethernet PHY Device Link state. + \return current link status \ref ARM_ETH_LINK_STATE + */ +static ARM_ETH_LINK_STATE GetLinkState (void) { + ARM_ETH_LINK_STATE state; + uint16_t val = 0U; + + if (PHY.flags & PHY_POWER) { + PHY.reg_rd(ETH_PHY_ADDR, REG_BSR, &val); + } + state = (val & BSR_LINK_STAT) ? ARM_ETH_LINK_UP : ARM_ETH_LINK_DOWN; + + return (state); +} + +/** + \fn ARM_ETH_LINK_INFO GetLinkInfo (void) + \brief Get Ethernet PHY Device Link information. + \return current link parameters \ref ARM_ETH_LINK_INFO + */ +static ARM_ETH_LINK_INFO GetLinkInfo (void) { + ARM_ETH_LINK_INFO info; + uint16_t val = 0U; + + if (PHY.flags & PHY_POWER) { + PHY.reg_rd(ETH_PHY_ADDR, REG_PSCS, &val); + } + + info.speed = (val & PSCS_SPEED) ? ARM_ETH_SPEED_10M : ARM_ETH_SPEED_100M; + info.duplex = (val & PSCS_DUPLEX) ? ARM_ETH_DUPLEX_FULL : ARM_ETH_DUPLEX_HALF; + + return (info); +} + + +/* PHY Driver Control Block */ +extern +ARM_DRIVER_ETH_PHY ARM_Driver_ETH_PHY0; +ARM_DRIVER_ETH_PHY ARM_Driver_ETH_PHY0= { + GetVersion, + Initialize, + Uninitialize, + PowerControl, + SetInterface, + SetMode, + GetLinkState, + GetLinkInfo +}; +#endif diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/PHY_LAN8742A.h b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/PHY_LAN8742A.h new file mode 100644 index 000000000..ca9f44204 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/PHY_LAN8742A.h @@ -0,0 +1,91 @@ +/* --------------------------------------------------------------------------- + * Copyright (C) 2013-2016 ARM Limited. All rights reserved. + * + * $Date: 28. June 2016 + * $Revision: V1.2 + * + * Project: Ethernet Physical Layer Transceiver (PHY) + * Definitions for LAN8742A + * --------------------------------------------------------------------------*/ + +#ifndef __PHY_LAN8742A_H +#define __PHY_LAN8742A_H + +#include "Driver_ETH_PHY.h" + +/* Basic Registers */ +#define REG_BCR 0 /* Basic Control Register */ +#define REG_BSR 1 /* Basic Status Register */ + +/* Extended Registers */ +#define REG_PHYIDR1 2 /* PHY Identifier 1 */ +#define REG_PHYIDR2 3 /* PHY Identifier 2 */ +#define REG_ANAR 4 /* Auto-Negotiation Advertisement */ +#define REG_ANLPAR 5 /* Auto-Neg. Link Partner Ability */ +#define REG_ANER 6 /* Auto-Neg. Expansion Register */ +#define REG_ANEG_NP_TX 7 /* Auto-Neg. Next Page Tx */ +#define REG_ANEG_NP_RX 8 /* Auto-Neg. Next Page Rx */ +#define REG_MMD_ACCES_CTRL 13 /* MMD Access Control */ +#define REG_MMD_ACCES_AD 14 /* MMD Access Address/Data */ + +/* Vendor-specific Registers */ +#define REG_MCSR 17 /* Mode Control/Status Register */ +#define REG_SPEC_MODE 18 /* Special Modes Register */ +#define REG_TDR_PAT_DEL 24 /* TDR Patterns/Delay Control Reg. */ +#define REG_TDR_CTRL_STAT 25 /* TDR Control/Status Register */ +#define REG_SEC 26 /* System Error Counter Register */ +#define REG_SC_SI 27 /* Specifal Control/Status Indication*/ +#define REG_CABLE_LEN 28 /* Cable Length Register */ +#define REG_ISF 29 /* Interrupt Source Flag Register */ +#define REG_IM 30 /* Interrupt Mask Register */ +#define REG_PSCS 31 /* PHY Special Ctrl/Status Register */ + +/* Basic Control Register */ +#define BCR_RESET 0x8000 /* Software Reset */ +#define BCR_LOOPBACK 0x4000 /* Loopback mode */ +#define BCR_SPEED_SEL 0x2000 /* Speed Select (1=100Mb/s) */ +#define BCR_ANEG_EN 0x1000 /* Auto Negotiation Enable */ +#define BCR_POWER_DOWN 0x8000 /* Power Down (1=power down mode) */ +#define BCR_ISOLATE 0x0400 /* Isolate Media interface */ +#define BCR_REST_ANEG 0x0200 /* Restart Auto Negotiation */ +#define BCR_DUPLEX 0x0100 /* Duplex Mode (1=Full duplex) */ +#define BCR_COL_TEST 0x0080 /* Enable Collision Test */ + +/* Basic Status Register */ +#define BSR_100B_T4 0x8000 /* 100BASE-T4 Capable */ +#define BSR_100B_TX_FD 0x4000 /* 100BASE-TX Full Duplex Capable */ +#define BSR_100B_TX_HD 0x2000 /* 100BASE-TX Half Duplex Capable */ +#define BSR_10B_T_FD 0x1000 /* 10BASE-T Full Duplex Capable */ +#define BSR_10B_T_HD 0x0800 /* 10BASE-T Half Duplex Capable */ +#define BSR_100B_T2_FD 0x0400 /* 1000BASE-T2 Full Duplex Capable */ +#define BSR_100B_T2_HD 0x0200 /* 1000BASE-T2 Half Duplex Capable */ +#define BSR_EXTENDED_STAT 0x0100 /* Extended Status in register 15 */ +#define BSR_ANEG_COMPL 0x0020 /* Auto Negotiation Complete */ +#define BSR_REM_FAULT 0x0010 /* Remote Fault */ +#define BSR_ANEG_ABIL 0x0008 /* Auto Negotiation Ability */ +#define BSR_LINK_STAT 0x0004 /* Link Status (1=link us up) */ +#define BSR_JABBER_DET 0x0002 /* Jabber Detect */ +#define BSR_EXT_CAPAB 0x0001 /* Extended Capabilities */ + +/* PHY Identifier Registers */ +#define PHY_ID1 0x0007 /* LAN8742A Device Identifier MSB */ +#define PHY_ID2 0xC130 /* LAN8742A Device Identifier LSB */ + +/* PHY Special Control/Status Register */ +#define PSCS_AUTODONE 0x1000 /* Auto-negotiation is done */ +#define PSCS_DUPLEX 0x0010 /* Duplex Status (1=Full duplex) */ +#define PSCS_SPEED 0x0004 /* Speed10 Status (1=10MBit/s) */ + +/* PHY Driver State Flags */ +#define PHY_INIT 0x01U /* Driver initialized */ +#define PHY_POWER 0x02U /* Driver power is on */ + +/* PHY Driver Control Structure */ +typedef struct phy_ctrl { + ARM_ETH_PHY_Read_t reg_rd; /* PHY register read function */ + ARM_ETH_PHY_Write_t reg_wr; /* PHY register write function */ + uint16_t bcr; /* BCR register value */ + uint8_t flags; /* Control flags */ +} PHY_CTRL; + +#endif /* __PHY_LAN8742A_H */ diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/USB.c b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/USB.c new file mode 100644 index 000000000..c29fb928e --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/USB.c @@ -0,0 +1,80 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2018 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * $Date: 01. Oct 2018 + * $Revision: V1.0 + * + * Project: Common file for both USB(Device and Host) + * -------------------------------------------------------------------------- */ + +/* History: + * Version 1.0 + * Initial release + */ + +#include "rsi_ccp_user_config.h" +#if defined(CHIP_9118) + + + +#include "Driver_USB.h" +#include "USB.h" +#include "RTE_Device.h" + + +volatile uint8_t USB_role = ARM_USB_ROLE_NONE; +volatile uint8_t USB_state = 0U; + +#ifdef RTE_Drivers_USBH +extern void USBH0_IRQ (void); +#endif +#ifdef RTE_Drivers_USBD +extern void USBD0_IRQ (void); +#endif + + +// Common IRQ Routine ********************************************************** + +/** + \fn void IRQ073_Handler (void) + \brief USB Interrupt Routine (IRQ). +*/ +void IRQ073_Handler (void) { +#if(defined(RTE_Drivers_USBH) && defined(RTE_Drivers_USBD)) + switch (USB_role) { +#ifdef RTE_Drivers_USBH + case ARM_USB_ROLE_HOST: + USBH_IRQ (); + break; +#endif +#ifdef RTE_Drivers_USBD + case ARM_USB_ROLE_DEVICE: + USBD_IRQ (); + break; +#endif + default: + break; + } +#else +#ifdef RTE_Drivers_USBH + USBH_IRQ (); +#else + USBD_IRQ (); +#endif +#endif +} +#endif diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/USB.h b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/USB.h new file mode 100644 index 000000000..96a6f4a40 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/USB.h @@ -0,0 +1,210 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2018 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * $Date: 12. Dec 2018 + * $Revision: V1.0 + * + * Project: USB Driver Definitions for Silicon Labs MCU + * -------------------------------------------------------------------------- */ + +/* History: + * Version 1.0 + * - Initial release + */ + +#ifndef __USB_H +#define __USB_H + +#include + +#ifndef USB_ENDPT_MSK +#define USB_ENDPT_MSK (0x3FU) +#endif + +// USB Device Command Register +#define USB_USBCMD_D_RS (1U ) +#define USB_USBCMD_D_RST (1U << 1U) +#define USB_USBCMD_D_SUTW (1U << 13U) +#define USB_USBCMD_D_ATDTW (1U << 14U) +#define USB_USBCMD_D_ITC_POS ( 16U) +#define USB_USBCMD_D_ITC_MSK (0xFFU << USB_USBCMD_D_ITC_POS) +#define USB_USBCMD_D_ITC(n) (((n) << USB_USBCMD_D_ITC_POS) & USB_USBCMD_D_ITC_MSK) + +// USB Device Status Register +#define USB_USBSTS_D_UI (1U ) +#define USB_USBSTS_D_UEI (1U << 1U) +#define USB_USBSTS_D_PCI (1U << 2U) +#define USB_USBSTS_D_URI (1U << 6U) +#define USB_USBSTS_D_SRI (1U << 7U) +#define USB_USBSTS_D_SLI (1U << 8U) +#define USB_USBSTS_D_NAKI (1U << 16U) + +// USB Device Interrupt Register +#define USB_USBINTR_D_UE (1U ) +#define USB_USBINTR_D_UEE (1U << 1U) +#define USB_USBINTR_D_PCE (1U << 2U) +#define USB_USBINTR_D_URE (1U << 6U) +#define USB_USBINTR_D_SRE (1U << 7U) +#define USB_USBINTR_D_SLE (1U << 8U) +#define USB_USBINTR_D_NAKE (1U << 16U) + +// USB Device Frame Index Register +#define USB_FRINDEX_D_FRINDEX2_0_POS ( 0U) +#define USB_FRINDEX_D_FRINDEX2_0_MSK (7U ) +#define USB_FRINDEX_D_FRINDEX13_3_POS ( 3U) +#define USB_FRINDEX_D_FRINDEX13_3_MSK (0x7FFU << USB_FRINDEX_D_FRINDEX13_3_POS) + +// USB Device Address Register +#define USB_DEVICEADDR_USBADRA (1U << 24U) +#define USB_DEVICEADDR_USBADR_POS ( 25U) +#define USB_DEVICEADDR_USBADR_MSK (0x7FUL << USB_DEVICEADDR_USBADR_POS) + +// USB Endpoint List Address Register +#define USB_ENDPOINTLISTADDR_EPBASE31_11_POS ( 11U) +#define USB_ENDPOINTLISTADDR_EPBASE_MSK (0x1FFFFFUL << USB_ENDPOINTLISTADDR_EPBASE31_11_POS) + +// USB Burst Size Register +#define USB_BURSTSIZE_RXPBURST_POS ( 0U) +#define USB_BURSTSIZE_RXPBURST_MSK (0xFFU ) +#define USB_BURSTSIZE_TXPBURST_POS ( 8U) +#define USB_BURSTSIZE_TXPBURST_MSK (0xFFU << USB_BURSTSIZE_TXPBURST_POS) + +// USB BInterval Register +#define USB_BINTERVAL_BINT_POS ( 0U) +#define USB_BINTERVAL_BINT_MSK (0x0FU << USB_BINTERVAL_BINT_POS) + +// USB Endpoint NAK Register +#define USB_ENDPTNAK_EPRN_POS ( 0U) +#define USB_ENDPTNAK_EPRN_MSK (USB_ENDPT_MSK) +#define USB_ENDPTNAK_EPTN_POS ( 16U) +#define USB_ENDPTNAK_EPTN_MSK (USB_ENDPT_MSK << USB_ENDPTNAK_EPTN_POS) + +// USB Endpoint NAK Enable Register +#define USB_ENDPTNAKEN_EPRNE_POS ( 0U) +#define USB_ENDPTNAKEN_EPRNE_MSK (USB_ENDPT_MSK) +#define USB_ENDPTNAKEN_EPTNE_POS ( 16U) +#define USB_ENDPTNAKEN_EPTNE_MSK (USB_ENDPT_MSK << USB_ENDPTNAKEN_EPTNE_POS) + +// USB Device Port Status and Control Register +#define USB_PORTSC1_D_CCS (1U ) +#define USB_PORTSC1_D_PE (1U << 2U) +#define USB_PORTSC1_D_PEC (1U << 3U) +#define USB_PORTSC1_D_FPR (1U << 6U) +#define USB_PORTSC1_D_SUSP (1U << 7U) +#define USB_PORTSC1_D_PR (1U << 8U) +#define USB_PORTSC1_D_HSP (1U << 9U) +#define USB_PORTSC1_D_PIC15_14_POS ( 14U) +#define USB_PORTSC1_D_PIC15_14_MSK (3U << USB_PORTSC1_D_PIC15_14_POS) +#define USB_PORTSC1_D_PIC15_14(n) (((n) << USB_PORTSC1_D_PIC15_14_POS) & USB_PORTSC1_D_PIC15_14_MSK) +#define USB_PORTSC1_D_PTC19_16_POS ( 16U) +#define USB_PORTSC1_D_PTC19_16_MSK (0x0FU << USB_PORTSC1_D_PTC19_16_POS) +#define USB_PORTSC1_D_PHCD (1U << 23U) +#define USB_PORTSC1_D_PFSC (1U << 24U) +#define USB_PORTSC1_D_PSPD_POS ( 26U) +#define USB_PORTSC1_D_PSPD_MSK (3U << USB_PORTSC1_D_PSPD_POS) +#define USB_PORTSC1_D_PTS_POS ( 30U) +#define USB_PORTSC1_D_PTS_MSK (3UL << USB_PORTSC1_D_PTS_POS) +#define USB_PORTSC1_D_PTS(n) (((n) << USB_PORTSC1_D_PTS_POS) & USB_PORTSC1_D_PTS_MSK) + +// USB Device Mode Register +#define USB_USBMODE_D_CM1_0_POS ( 0U) +#define USB_USBMODE_D_CM1_0_MSK (3U ) +#define USB_USBMODE_D_CM1_0(n) ((n) & USB_USBMODE_D_CM1_0_MSK) +#define USB_USBMODE_D_ES (1U << 2U) +#define USB_USBMODE_D_SLOM (1U << 3U) +#define USB_USBMODE_D_SDIS (1U << 4U) + +// USB Endpoint Setup Status Register +#define USB_ENDPTSETUPSTAT_POS ( 0U) +#define USB_ENDPTSETUPSTAT_MSK (USB_ENDPT_MSK << USB_ENDPTSETUPSTAT_POS) + +// USB Endpoint Prime Register +#define USB_ENDPTRPRIME_PERB_POS ( 0U) +#define USB_ENDPTRPRIME_PERB_MSK (USB_ENDPT_MSK) +#define USB_ENDPTRPRIME_PETB_POS ( 16U) +#define USB_ENDPTRPRIME_PETB_MSK (USB_ENDPT_MSK << USB_ENDPTRPRIME_PETB_POS) + +// USB Endpoint Flush Register +#define USB_ENDPTFLUSH_FERB_POS ( 0U) +#define USB_ENDPTFLUSH_FERB_MSK (USB_ENDPT_MSK) +#define USB_ENDPTFLUSH_FETB_POS ( 16U) +#define USB_ENDPTFLUSH_FETB_MSK (USB_ENDPT_MSK << USB_ENDPTFLUSH_FETB_POS) + +// USB Endpoint Status Register +#define USB_ENDPTSTAT_ERBR_POS ( 0U) +#define USB_ENDPTSTAT_ERBR_MSK (USB_ENDPT_MSK) +#define USB_ENDPTSTAT_ETBR_POS ( 16U) +#define USB_ENDPTSTAT_ETBR_MSK (USB_ENDPT_MSK << USB_ENDPTSTAT_ETBR_POS) + +// USB Endpoint Complete Register +#define USB_ENDPTCOMPLETE_ERCE_POS ( 0U) +#define USB_ENDPTCOMPLETE_ERCE_MSK (USB_ENDPT_MSK) +#define USB_ENDPTCOMPLETE_ETCE_POS ( 16U) +#define USB_ENDPTCOMPLETE_ETCE_MSK (USB_ENDPT_MSK << USB_ENDPTCOMPLETE_ETCE_POS) + +// USB Endpoint Control Register +#define USB_ENDPTCTRL_RXS (1U ) +#define USB_ENDPTCTRL_RXT_POS ( 2U) +#define USB_ENDPTCTRL_RXT_MSK (3U << USB_ENDPTCTRL_RXT_POS) +#define USB_ENDPTCTRL_RXT(n) (((n) << USB_ENDPTCTRL_RXT_POS) & USB_ENDPTCTRL_RXT_MSK) +#define USB_ENDPTCTRL_RXI (1U << 5U) +#define USB_ENDPTCTRL_RXR (1U << 6U) +#define USB_ENDPTCTRL_RXE (1U << 7U) +#define USB_ENDPTCTRL_TXS (1U << 16U) +#define USB_ENDPTCTRL_TXT_POS ( 18U) +#define USB_ENDPTCTRL_TXT_MSK (3U << USB_ENDPTCTRL_TXT_POS) +#define USB_ENDPTCTRL_TXT(n) (((n) << USB_ENDPTCTRL_TXT_POS) & USB_ENDPTCTRL_TXT_MSK) +#define USB_ENDPTCTRL_TXI (1U << 21U) +#define USB_ENDPTCTRL_TXR (1U << 22U) +#define USB_ENDPTCTRL_TXE (1U << 23U) + +// Endpoint Queue Head Capabilities and Characteristics +#define USB_EPQH_CAP_IOS (1U << 15U) +#define USB_EPQH_CAP_MAX_PACKET_LEN_POS ( 16U) +#define USB_EPQH_CAP_MAX_PACKET_LEN_MSK (0x7FFU << USB_EPQH_CAP_MAX_PACKET_LEN_POS) +#define USB_EPQH_CAP_MAX_PACKET_LEN(n) (((n) << USB_EPQH_CAP_MAX_PACKET_LEN_POS) & USB_EPQH_CAP_MAX_PACKET_LEN_MSK) +#define USB_EPQH_CAP_ZLT (1U << 29U) +#define USB_EPQH_CAP_MULT_POS ( 30U) +#define USB_EPQH_CAP_MULT_MSK (3UL << USB_EPQH_CAP_MULT_POS) + +// Transfer Descriptor Token +#define USB_dTD_TOKEN_STATUS_POS ( 0U) +#define USB_dTD_TOKEN_STATUS_MSK (0xFFU ) +#define USB_dTD_TOKEN_STATUS(n) (n & USB_dTD_TOKEN_STATUS_MSK) +#define USB_dTD_TOKEN_STATUS_TRAN_ERROR (0x08U & USB_dTD_TOKEN_STATUS_MSK) +#define USB_dTD_TOKEN_STATUS_BUFFER_ERROR (0x20U & USB_dTD_TOKEN_STATUS_MSK) +#define USB_dTD_TOKEN_STATUS_HALTED (0x40U & USB_dTD_TOKEN_STATUS_MSK) +#define USB_dTD_TOKEN_STATUS_ACTIVE (0x80U & USB_dTD_TOKEN_STATUS_MSK) +#define USB_dTD_TOKEN_MULTO_POS ( 10U) +#define USB_dTD_TOKEN_MULTO_MSK (3U << USB_dTD_TOKEN_MULTO_POS) +#define USB_dTD_TOKEN_MULTO(n) (((n) << USB_dTD_TOKEN_MULTO_POS) & USB_dTD_TOKEN_MULTO_MSK) +#define USB_dTD_TOKEN_IOC (1U << 15U) +#define USB_dTD_TOKEN_TOTAL_BYTES_POS ( 16U) +#define USB_dTD_TOKEN_TOTAL_BYTES_MSK (0x7FFFU<< USB_dTD_TOKEN_TOTAL_BYTES_POS) +#define USB_dTD_TOKEN_TOTAL_BYTES(n) (((n) << USB_dTD_TOKEN_TOTAL_BYTES_POS) & USB_dTD_TOKEN_TOTAL_BYTES_MSK) + +// USB Host and Device Driver status flags +#define USBD_DRIVER_INITIALIZED (1U ) +#define USBD_DRIVER_POWERED (1U << 1U) + +#define USBH_DRIVER_INITIALIZED (1U << 4U) +#define USBH_DRIVER_POWERED (1U << 5U) + +//USB Host and Device function declaration +void USBH_IRQ (void); +void USBD_IRQ (void); +#endif /* __USB_H */ diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/USBD.c b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/USBD.c new file mode 100644 index 000000000..a7d7574fd --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/USBD.c @@ -0,0 +1,886 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * + * $Date: 12. Dec 2018 + * $Revision: V1.0 + * + * Driver: Driver_USBD0 + * Configured: via RTE_Device.h configuration file + * Project: USB High-Speed Device Driver for Silicon Labs RS1xxxx + * -------------------------------------------------------------------------- + * Use the following configuration settings in the middleware component + * to connect to this driver. + * + * Configuration Setting Value + * --------------------- ----- + * Connect to hardware via Driver_USBD# = 0 + * -------------------------------------------------------------------------- + * Defines used for driver configuration (at compile time): + * + * USBD_MAX_ENDPOINT_NUM: defines maximum number of IN/OUT Endpoint pairs + * that driver will support with Control Endpoint 0 + * not included, this value impacts driver memory + * requirements + * - default value: 5 + * - maximum value: 5 + * -------------------------------------------------------------------------- */ + +/* History: + * Version 1.0 + * Initial release + */ + +#include "rsi_ccp_user_config.h" +#if defined(CHIP_9118) + +#include +#include + +#include "Driver_USBD.h" + + +#include "USB.h" +#include "RTE_Device.h" + + +#ifndef USBD_MAX_ENDPOINT_NUM +#define USBD_MAX_ENDPOINT_NUM 5U +#endif +#if (USBD_MAX_ENDPOINT_NUM > 6) +#error Too many Endpoints, maximum IN/OUT Endpoint pairs that this driver supports is 5 !!! +#endif + + +extern uint8_t USB_role; +extern uint8_t USB_state; + + +// USBD Driver ***************************************************************** + +#define ARM_USBD_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR (1,0) + +// Driver Version +static const ARM_DRIVER_VERSION usbd_driver_version = { ARM_USBD_API_VERSION, ARM_USBD_DRV_VERSION }; + +// Driver Capabilities +static const ARM_USBD_CAPABILITIES usbd_driver_capabilities = { + 1U, // VBUS Detection + 1U, // Event VBUS On + 1U // Event VBUS Off +}; + +#define ENDPTCTRL(ep_num) (*(volatile uint32_t *)((uint32_t)(&USB->USB_ENDPTCTRL0) + 4U * ep_num)) + +#define EP_NUM(ep_addr) (ep_addr & ARM_USB_ENDPOINT_NUMBER_MASK) +#define EP_DIR(ep_addr) ((ep_addr >> 7) & 1U) +#define EP_SLL(ep_addr) (EP_DIR(ep_addr) * 16U) +#define EP_QHNUM(ep_addr) ((EP_NUM(ep_addr) * 2U) + EP_DIR(ep_addr)) +#define EP_MSK(ep_addr) (1UL << (EP_NUM(ep_addr) + EP_SLL(ep_addr))) + +/*USB Device endpoint Queue Head*/ +typedef struct { + uint32_t cap; + uint32_t curr_dTD; + uint32_t next_dTD; + uint32_t dTD_token; + uint32_t buf[5]; + uint32_t reserved; + uint32_t setup[2]; + uint8_t *data; + uint32_t num; + uint32_t num_transferred_total; + uint16_t num_transferring; + uint8_t ep_type; + uint8_t ep_active; +} dQH_t; + +/*USB Device Endpoint transfer descriptor*/ +typedef struct { + uint32_t next_dTD; + uint32_t dTD_token; + uint32_t buf[5]; + uint32_t reserved; +} dTD_t; + +static dQH_t __align(2048) dQH[(USBD_MAX_ENDPOINT_NUM + 1U) * 2U]; /* Queue Heads aligned to 2k boundary */ +static dTD_t __align( 32) dTD[(USBD_MAX_ENDPOINT_NUM + 1U) * 2U]; /* Transfer Descriptors */ + +static ARM_USBD_SignalDeviceEvent_t SignalDeviceEvent; +static ARM_USBD_SignalEndpointEvent_t SignalEndpointEvent; + +static ARM_USBD_STATE usbd_state; +/* Setup packet data buffer */ +static uint32_t setup_packet[2]; +/* Setup packet received */ +static volatile uint8_t setup_packet_recv; + +// Function prototypes +static int32_t USBD_EndpointConfigure (uint8_t ep_addr, uint8_t ep_type, uint16_t ep_max_packet_size); + +#define M4SS_CLK_PWR_CTRL_BASE_ADDR 0x46000000 +#define USB_SYSCLK_CLKCLNR_ON (1 << 23) +#define M4SS_CLOCK_CONFIG_REG4 *(volatile uint32_t *)(M4SS_CLK_PWR_CTRL_BASE_ADDR + 0x24) +#define M4SS_CLOCK_CONFIG_REG5 *(volatile uint32_t *)(M4SS_CLK_PWR_CTRL_BASE_ADDR + 0x28) + +#define M4SS_MISC_REG_BASE 0x46008000 + +#define MISC_USB_CONFIG_REG *((volatile uint32_t *)(M4SS_MISC_REG_BASE + 0x1C)) +#define NWPAON_ACCESS_CTRL_CLEAR *((volatile uint32_t *)(NWPAON_MEM_HOST_ACCESS_CTRL_CLEAR)) +#define MISC_CFG_RST_LATCH_STATUS *((volatile uint32_t *)(M4SS_MISC_REG_BASE + 0x10)) +#define MISC_CFG_HOST_CTRL *((volatile uint32_t *)(M4SS_MISC_REG_BASE + 0x0C)) + +#define MISC_USB_SET_REG1 *((volatile uint32_t *)(M4SS_MISC_REG_BASE + 0xF0)) +#define MISC_USB_CLEAR_REG1 *((volatile uint32_t *)(M4SS_MISC_REG_BASE + 0xF4)) + +// Auxiliary functions + +/** + * @fn void USBD_HW_EndpointFlush (uint8_t ep_addr) + * @brief Flush Endpoint. + * @param[in] ep_addr : Endpoint Address + * - ep_addr.0..3: Address + * - ep_addr.7: Direction + * +*/ +static void USBD_HW_EndpointFlush (uint8_t ep_addr) { + uint32_t ep_msk=0; + + ep_msk = EP_MSK(ep_addr); + /*USB endpoint flush*/ + USB->USB_ENDPTFLUSH = ep_msk; + while (USB->USB_ENDPTFLUSH & ep_msk); +} + +/** + * @fn void USBD_Reset (void) + * @brief Reset USB Endpoint settings and variables. +*/ +static void USBD_Reset (void) { + uint8_t i; + + setup_packet[0] = 0U; + setup_packet[1] = 0U; + setup_packet_recv = 0U; + memset((void *)dQH, 0, sizeof(dQH)); + memset((void *)dTD, 0, sizeof(dTD)); + + /*Disable all the supported endpoint for tx and rx*/ + for (i = 1U; i <= USBD_MAX_ENDPOINT_NUM; i++) { + ENDPTCTRL(i) &= ~(USB_ENDPTCTRL_RXE | USB_ENDPTCTRL_TXE); + } + + /* Clear interrupts*/ + USB->USB_ENDPTNAK = 0xFFFFFFFFUL; + USB->USB_ENDPTNAKEN = 0U; + USB->USBSTS_D = 0xFFFFFFFFUL; + /*Clearing all setup tokens*/ + USB->USB_ENDPTSETUPSTAT = USB->USB_ENDPTSETUPSTAT; + /*Clearing all endpoint complete status bits*/ + USB->USB_ENDPTCOMPLETE = USB->USB_ENDPTCOMPLETE; + + /*Clear all prime status*/ + while (USB->USB_ENDPTPRIME); + /*Clear all primed buffers*/ + USB->USB_ENDPTFLUSH = 0xFFFFFFFFUL; + while (USB->USB_ENDPTFLUSH); + + /*Interupt threshold control to isusue an interrupt*/ + USB->USBCMD_D &= ~(USB_USBCMD_D_ITC(0xFFUL)); + + /* Initialization of an control Endpoint0*/ + if (usbd_state.speed == ARM_USB_SPEED_HIGH) { + USBD_EndpointConfigure (0x00U, ARM_USB_ENDPOINT_CONTROL, 64U); + USBD_EndpointConfigure (0x80U, ARM_USB_ENDPOINT_CONTROL, 64U); + } else { + /*for full/low speed*/ + USBD_EndpointConfigure (0x00U, ARM_USB_ENDPOINT_CONTROL, 8U); + USBD_EndpointConfigure (0x80U, ARM_USB_ENDPOINT_CONTROL, 8U); + } + + /*Assign the start of endpoint list address register*/ + USB->USB_ENDPOINTLISTADDR = (uint32_t)dQH; + + /*setup lockout mode off*/ + USB->USBMODE_D |= USB_USBMODE_D_SLOM; +} + +/** + * @fn void USBD_HW_ReadSetupPacket (void) + * @brief Read Setup Packet to buffer. +*/ +static void USBD_HW_ReadSetupPacket (void) { + + do { + /*Setup tripwire*/ + USB->USBCMD_D |= USB_USBCMD_D_SUTW; + /*Copy the setup packet data received to buffer */ + setup_packet[0] = dQH[0].setup[0]; + setup_packet[1] = dQH[0].setup[1]; + } while (!(USB->USBCMD_D & USB->USBCMD_D)); + /*Clear the setup tripwire*/ + USB->USBCMD_D &= ~USB_USBCMD_D_SUTW; + /*clear the setup endpoint status bit*/ + USB->USB_ENDPTSETUPSTAT = 1U; + +} + +/** + * @fn void USBD_HW_EndpointTransfer (uint8_t ep_addr) + * @brief Start transfer on Endpoint. + * @param[in] ep_addr : Endpoint Address + * - ep_addr.0..3: Address + * - ep_addr.7: Direction +*/ +static void USBD_HW_EndpointTransfer (uint8_t ep_addr) { + dQH_t *ptr_dqh; + dTD_t *ptr_dtd; + uint8_t *data; + uint32_t ep_msk=0, num=0; + uint8_t ep_qhnum=0; + + ep_qhnum = EP_QHNUM(ep_addr); + ep_msk = EP_MSK(ep_addr); + ptr_dqh = &dQH[ep_qhnum]; + ptr_dtd = &dTD[ep_qhnum]; + + data = ptr_dqh->data + ptr_dqh->num_transferred_total; + num = ptr_dqh->num - ptr_dqh->num_transferred_total; + /* max transfer length is 16k*/ + if (num > 0x4000U) { num = 0x4000U; } + + while (USB->USB_ENDPTSTAT & ep_msk); + + memset (ptr_dtd, 0, sizeof(dTD_t)); + + /* Driver does not support linked endpoint descriptors next address is invalid*/ + ptr_dtd->next_dTD = 1U; + + /* Configure Transfer Descriptor */ + ptr_dtd->dTD_token |= USB_dTD_TOKEN_TOTAL_BYTES(num) | + USB_dTD_TOKEN_IOC | + USB_dTD_TOKEN_STATUS_ACTIVE ; + + /* Set Buffer Addresses */ + ptr_dtd->buf[0] = (uint32_t)(data ); + ptr_dtd->buf[1] = (uint32_t)(data + 0x1000U); + ptr_dtd->buf[2] = (uint32_t)(data + 0x2000U); + ptr_dtd->buf[3] = (uint32_t)(data + 0x3000U); + ptr_dtd->buf[4] = (uint32_t)(data + 0x4000U); + /*clear status*/ + ptr_dqh->dTD_token &= ~USB_dTD_TOKEN_STATUS_MSK; + /* Save Transfer Descriptor address to overlay area of queue heads*/ + ptr_dqh->next_dTD = (uint32_t)(ptr_dtd); + + ptr_dqh->num_transferring = num; + /*start the endpoint transfer*/ + USB->USB_ENDPTPRIME |= ep_msk; +} + + +// USBD Driver functions + +/** + * @fn ARM_DRIVER_VERSION USBD_GetVersion (void) + * @brief Get driver version. + * @return \ref ARM_DRIVER_VERSION +*/ +static ARM_DRIVER_VERSION USBD_GetVersion (void) { return usbd_driver_version; } + +/** + * @fn ARM_USBD_CAPABILITIES USBD_GetCapabilities (void) + * @brief Get driver capabilities. + * @return \ref ARM_USBD_CAPABILITIES +*/ +static ARM_USBD_CAPABILITIES USBD_GetCapabilities (void) { return usbd_driver_capabilities; } + +/** + * @fn int32_t USBD_Initialize (ARM_USBD_SignalDeviceEvent_t cb_device_event, + ARM_USBD_SignalEndpointEvent_t cb_endpoint_event) + * @brief Initialize USB Device Interface. + * @param[in] cb_device_event : Pointer to \ref ARM_USBD_SignalDeviceEvent + * @param[in] cb_endpoint_event : Pointer to \ref ARM_USBD_SignalEndpointEvent + * @return \ref execution_status +*/ +static int32_t USBD_Initialize (ARM_USBD_SignalDeviceEvent_t cb_device_event, + ARM_USBD_SignalEndpointEvent_t cb_endpoint_event) { + + if(MCU_RET->CHIP_CONFIG_MCU_READ_b.DISABLE_USB == 1U){ + /* If USB peripheral is not supported by this chip*/ + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + if ((USB_state & USBD_DRIVER_INITIALIZED) != 0U) { return ARM_DRIVER_OK; } + + SignalDeviceEvent = cb_device_event; + SignalEndpointEvent = cb_endpoint_event; + + USB_role = ARM_USB_ROLE_DEVICE; + + USB_state = USBD_DRIVER_INITIALIZED; + + return ARM_DRIVER_OK; +} + +/** + * @fn int32_t USBD_Uninitialize (void) + * @brief De-initialize USB Device Interface. + * @return \ref execution_status +*/ +static int32_t USBD_Uninitialize (void) { + + USB_role = ARM_USB_ROLE_NONE; + USB_state &= ~USBD_DRIVER_INITIALIZED; + + return ARM_DRIVER_OK; +} + +/** + * @fn int32_t USBD_PowerControl (ARM_POWER_STATE state) + * @brief Control USB Device Interface Power. + * @param[in] state : Power state + * @return \ref execution_status +*/ +static int32_t USBD_PowerControl (ARM_POWER_STATE state) { + + switch (state) { + case ARM_POWER_OFF: + /*Disable interrupt*/ + NVIC_DisableIRQ (USB_IRQn); + NVIC_ClearPendingIRQ (USB_IRQn); + USB_state &= ~USBD_DRIVER_POWERED; + + setup_packet_recv = 0U; + memset((void *)&usbd_state, 0, sizeof(usbd_state)); + memset((void *)dQH, 0, sizeof(dQH)); + memset((void *)dTD, 0, sizeof(dTD)); + break; + + case ARM_POWER_FULL: + if ((USB_state & USBD_DRIVER_INITIALIZED) == 0U) { return ARM_DRIVER_ERROR; } + if ((USB_state & USBD_DRIVER_POWERED) != 0U) { return ARM_DRIVER_OK; } + + /*USB Config*/ + MISC_USB_CONFIG_REG =0x11; + /*Enable M4 USB*/ + NWPAON_ACCESS_CTRL_CLEAR = BIT(4); + + // Reset USB Controller + USB->USBCMD_D = USB_USBCMD_D_RST; + + while ((USB->USBCMD_D & (USB_USBCMD_D_RS | USB_USBCMD_D_RST)) != 0U); + + /*Set the usb in device mode and setup lockout mode*/ + USB->USBMODE_D = USB_USBMODE_D_CM1_0(2U) | USB_USBMODE_D_SLOM; + /* USB device reset*/ + USBD_Reset (); + +#if (RTE_USB_USB0_HS_EN) + USB->USB_PORTSC1_D &= ~USB_PORTSC1_D_PFSC; +#else + USB->USB_PORTSC1_D |= USB_PORTSC1_D_PFSC; +#endif + + /* Set all the usb interrupts*/ + USB->USBINTR_D = (USB_USBINTR_D_UE | + USB_USBINTR_D_PCE | + USB_USBINTR_D_SLE | + USB_USBINTR_D_URE); + + /*Set power flag*/ + USB_state |= USBD_DRIVER_POWERED; + /*Enable the usb interrupt */ + NVIC_EnableIRQ (USB_IRQn); + break; + + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + return ARM_DRIVER_OK; +} + +/** + * @fn int32_t USBD_DeviceConnect (void) + * @brief Connect USB Device. + * @return \ref execution_status +*/ +static int32_t USBD_DeviceConnect (void) { + + if ((USB_state & USBD_DRIVER_POWERED) == 0U) { return ARM_DRIVER_ERROR; } + + USB->USBCMD_D |= USB_USBCMD_D_RS; + + return ARM_DRIVER_OK; +} + +/** + * @fn int32_t USBD_DeviceDisconnect (void) + * @brief Disconnect USB Device. + * @return \ref execution_status +*/ +static int32_t USBD_DeviceDisconnect (void) { + + if ((USB_state & USBD_DRIVER_POWERED) == 0U) { return ARM_DRIVER_ERROR; } + + USB->USBCMD_D &= ~USB_USBCMD_D_RS; + +#if (RTE_USB0_IND0_PIN_EN) + USB->PORTSC1_D &= ~USB_PORTSC1_D_PIC1_0(1); // Clear indicator LED0 :FIXME :led indication dedicated pin not there +#endif + + return ARM_DRIVER_OK; +} + +/** + * @fn ARM_USBD_STATE USBD_DeviceGetState (void) + * @brief Get current USB Device State. + * @return Device State \ref ARM_USBD_STATE +*/ +static ARM_USBD_STATE USBD_DeviceGetState (void) { + ARM_USBD_STATE dev_state = { 0U, 0U, 0U }; + uint32_t portsc1_d=0; + + if ((USB_state & USBD_DRIVER_POWERED) == 0U) { return dev_state; } + + portsc1_d = USB->USB_PORTSC1_D; + dev_state = usbd_state; + /*Current status of usb device connection and usb device bus status*/ + dev_state.active = ((portsc1_d & USB_PORTSC1_D_CCS) != 0U) && + ((portsc1_d & USB_USBSTS_D_SLI) == 0U) ; + + return dev_state; +} + +/** + * @fn int32_t USBD_DeviceRemoteWakeup (void) + * @brief Trigger USB Remote Wakeup. + * @return \ref execution_status +*/ +static int32_t USBD_DeviceRemoteWakeup (void) { + + if ((USB_state & USBD_DRIVER_POWERED) == 0U) { return ARM_DRIVER_ERROR; } + /*Enable the phy clock*/ + USB->USB_PORTSC1_D &= ~USB_PORTSC1_D_PHCD; + /* Force Port Resume*/ + USB->USB_PORTSC1_D |= USB_PORTSC1_D_FPR; + + return ARM_DRIVER_OK; +} + +/** + * @fn int32_t USBD_DeviceSetAddress (uint8_t dev_addr) + * @brief Set USB Device Address. + * @param[in] dev_addr : Device Address + * @return \ref execution_status +*/ +static int32_t USBD_DeviceSetAddress (uint8_t dev_addr) { + + if ((USB_state & USBD_DRIVER_POWERED) == 0U) { return ARM_DRIVER_ERROR; } + + USB->USB_DEVICEADDR = (dev_addr << USB_DEVICEADDR_USBADR_POS) & USB_DEVICEADDR_USBADR_MSK; + USB->USB_DEVICEADDR |= USB_DEVICEADDR_USBADRA; + + return ARM_DRIVER_OK; +} + +/** + * @fn int32_t USBD_ReadSetupPacket (uint8_t *setup) + * @brief Read setup packet received over Control Endpoint. + * @param[out] setup : Pointer to buffer for setup packet + * @return \ref execution_status +*/ +static int32_t USBD_ReadSetupPacket (uint8_t *setup) { + + if ((USB_state & USBD_DRIVER_POWERED) == 0U) { return ARM_DRIVER_ERROR; } + if (setup_packet_recv == 0U) { return ARM_DRIVER_ERROR; } + + setup_packet_recv = 0U; + memcpy(setup, setup_packet, 8); + /* If new setup packet was received while this was being read*/ + if (setup_packet_recv != 0U) { + return ARM_DRIVER_ERROR; + } + + return ARM_DRIVER_OK; +} + +/** + * @fn int32_t USBD_EndpointConfigure (uint8_t ep_addr, + uint8_t ep_type, + uint16_t ep_max_packet_size) + * @brief Configure USB Endpoint. + * @param[in] ep_addr : Endpoint Address + - ep_addr.0..3: Address + - ep_addr.7: Direction + * @param[in] ep_type : Endpoint Type (ARM_USB_ENDPOINT_xxx) + * @param[in] ep_max_packet_size : Endpoint Maximum Packet Size + * @return \ref execution_status +*/ +static int32_t USBD_EndpointConfigure (uint8_t ep_addr, + uint8_t ep_type, + uint16_t ep_max_packet_size) { + dQH_t *ptr_dqh; + uint32_t ep_mult=0; + uint32_t ep_packet_size=0; + uint8_t ep_num=0,ep_sll=0; + + ep_num = EP_NUM(ep_addr); + if (ep_num > USBD_MAX_ENDPOINT_NUM) { return ARM_DRIVER_ERROR; } + if ((USB_state & USBD_DRIVER_POWERED) == 0U) { return ARM_DRIVER_ERROR; } + + ptr_dqh = &dQH[EP_QHNUM(ep_addr)]; + if (ptr_dqh->ep_active != 0U) { return ARM_DRIVER_ERROR_BUSY; } + + ep_num = EP_NUM(ep_addr); + ep_sll = EP_SLL(ep_addr); + ep_mult = (ep_max_packet_size & ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_MASK) >> 11; + ep_packet_size = ep_max_packet_size & ARM_USB_ENDPOINT_MAX_PACKET_SIZE_MASK; + + memset((void *)ptr_dqh, 0, sizeof(dQH_t)); + + ptr_dqh->ep_type = ep_type; + if (ep_type == ARM_USB_ENDPOINT_ISOCHRONOUS) { + /* For isochronous endpoints number of transactions per microframe in high-speed (or frame in full-speed)*/ + /* has to be 1 more than additional transactions per microframe for high-speed (or 1 for full-speed)*/ + ep_mult++; + } + + if ((ep_mult > 1U) && (usbd_state.speed == ARM_USB_SPEED_FULL)) { ep_mult = 1U; } + + ptr_dqh->cap = ((ep_mult << USB_EPQH_CAP_MULT_POS) & USB_EPQH_CAP_MULT_MSK) | + (USB_EPQH_CAP_MAX_PACKET_LEN(ep_packet_size)) | + (USB_EPQH_CAP_ZLT) | + ((ep_addr == 0U) * USB_EPQH_CAP_IOS); + ptr_dqh->next_dTD = 1U; + ptr_dqh->dTD_token = 0U; + + USBD_HW_EndpointFlush(ep_addr); + + /*clear all the enpoint settings*/ + ENDPTCTRL(ep_num) &= ~((USB_ENDPTCTRL_RXS | + USB_ENDPTCTRL_RXT_MSK | + USB_ENDPTCTRL_RXI | + USB_ENDPTCTRL_RXR | + USB_ENDPTCTRL_RXE ) + << ep_sll); + + /*set the enpoint setting*/ + ENDPTCTRL(ep_num) |= (USB_ENDPTCTRL_RXT(ep_type) | + USB_ENDPTCTRL_RXR | + USB_ENDPTCTRL_RXE ) + << ep_sll; + + return ARM_DRIVER_OK; +} + +/** + * @fn int32_t USBD_EndpointUnconfigure (uint8_t ep_addr) + * @brief Unconfigure USB Endpoint. + * @param[in] ep_addr : Endpoint Address + * - ep_addr.0..3: Address + * - ep_addr.7: Direction + * @return \ref execution_status +*/ +static int32_t USBD_EndpointUnconfigure (uint8_t ep_addr) { + dQH_t *ptr_dqh; + dTD_t *ptr_dtd; + uint8_t ep_qhnum=0, ep_num=0, ep_sll=0; + + ep_num = EP_NUM(ep_addr); + if (ep_num > USBD_MAX_ENDPOINT_NUM) { return ARM_DRIVER_ERROR; } + if ((USB_state & USBD_DRIVER_POWERED) == 0U) { return ARM_DRIVER_ERROR; } + + ep_qhnum = EP_QHNUM(ep_addr); + ptr_dqh = &dQH[ep_qhnum]; + if (ptr_dqh->ep_active != 0U) { return ARM_DRIVER_ERROR_BUSY; } + + ptr_dtd = &dTD[ep_qhnum]; + ep_sll = EP_SLL(ep_addr); + + /*clear all the enpoint settings*/ + ENDPTCTRL(ep_num) &= ~((USB_ENDPTCTRL_RXS | + USB_ENDPTCTRL_RXT_MSK | + USB_ENDPTCTRL_RXI | + USB_ENDPTCTRL_RXR | + USB_ENDPTCTRL_RXE ) + << ep_sll); + + ENDPTCTRL(ep_num) |= (USB_ENDPTCTRL_RXR << ep_sll); + + memset((void *)ptr_dqh, 0, sizeof(dQH_t)); + memset((void *)ptr_dtd, 0, sizeof(dTD_t)); + + return ARM_DRIVER_OK; +} + +/** + * @fn int32_t USBD_EndpointStall (uint8_t ep_addr, bool stall) + * @brief Set/Clear Stall for USB Endpoint. + * @param[in] ep_addr : Endpoint Address + * - ep_addr.0..3: Address + * - ep_addr.7: Direction + * @param[in] stall : Operation + * - \b false Clear + * - \b true Set + * @return \ref execution_status +*/ +static int32_t USBD_EndpointStall (uint8_t ep_addr, bool stall) { + dQH_t *ptr_dqh; + uint8_t ep_num=0, ep_sll=0; + + ep_num = EP_NUM(ep_addr); + if (ep_num > USBD_MAX_ENDPOINT_NUM) { return ARM_DRIVER_ERROR; } + if ((USB_state & USBD_DRIVER_POWERED) == 0U) { return ARM_DRIVER_ERROR; } + + ptr_dqh = &dQH[EP_QHNUM(ep_addr)]; + if (ptr_dqh->ep_active != 0U) { return ARM_DRIVER_ERROR_BUSY; } + /*check the endppoint is IN packet or OUT packet*/ + ep_sll = EP_SLL(ep_addr); + + if (stall != 0U) { + /*Set endpoint stall for IN or OUT packet*/ + ENDPTCTRL(ep_num) |= (USB_ENDPTCTRL_RXS << ep_sll); + } else { + /*Clear the endpoint stalling*/ + ENDPTCTRL(ep_num) &= ~(USB_ENDPTCTRL_RXS << ep_sll); + + ptr_dqh->dTD_token = 0U; + + USBD_HW_EndpointFlush(ep_addr); + /*Set data toggle reset */ + ENDPTCTRL(ep_num) |= (USB_ENDPTCTRL_RXR << ep_sll); + } + + return ARM_DRIVER_OK; +} + +/** + * @fn int32_t USBD_EndpointTransfer (uint8_t ep_addr, uint8_t *data, uint32_t num) + * @brief Read data from or Write data to USB Endpoint. + * @param[in] ep_addr : Endpoint Address + * - ep_addr.0..3: Address + * - ep_addr.7: Direction + * @param[out] data : Pointer to buffer for data to read or with data to write + * @param[in] num : Number of data bytes to transfer + * @return \ref execution_status +*/ +static int32_t USBD_EndpointTransfer (uint8_t ep_addr, uint8_t *data, uint32_t num) { + dQH_t *ptr_dqh; + + if (EP_NUM(ep_addr) > USBD_MAX_ENDPOINT_NUM) { return ARM_DRIVER_ERROR; } + if ((USB_state & USBD_DRIVER_POWERED) == 0U) { return ARM_DRIVER_ERROR; } + + ptr_dqh = &dQH[EP_QHNUM(ep_addr)]; + if (ptr_dqh->ep_active != 0U) { return ARM_DRIVER_ERROR_BUSY; } + + ptr_dqh->ep_active = 1U; + + ptr_dqh->data = data; + ptr_dqh->num = num; + ptr_dqh->num_transferred_total = 0U; + ptr_dqh->num_transferring = 0U; + /* Start transfer*/ + USBD_HW_EndpointTransfer(ep_addr); + + return ARM_DRIVER_OK; +} + +/** + * @fn uint32_t USBD_EndpointTransferGetResult (uint8_t ep_addr) + * @brief Get result of USB Endpoint transfer. + * @param[in] ep_addr : Endpoint Address + * - ep_addr.0..3: Address + * - ep_addr.7: Direction + * @return number of successfully transferred data bytes +*/ +static uint32_t USBD_EndpointTransferGetResult (uint8_t ep_addr) { + + if (EP_NUM(ep_addr) > USBD_MAX_ENDPOINT_NUM) { return 0U; } + + return (dQH[EP_QHNUM(ep_addr)].num_transferred_total); +} + +/** + * @fn int32_t USBD_EndpointTransferAbort (uint8_t ep_addr) + * @brief Abort current USB Endpoint transfer. + * @param[in] ep_addr : Endpoint Address + * - ep_addr.0..3: Address + * - ep_addr.7: Direction + * @return \ref execution_status +*/ +static int32_t USBD_EndpointTransferAbort (uint8_t ep_addr) { + dQH_t *ptr_dqh; + uint32_t ep_msk=0; + uint8_t ep_num=0, ep_sll=0; + + ep_num = EP_NUM(ep_addr); + if (ep_num > USBD_MAX_ENDPOINT_NUM) { return ARM_DRIVER_ERROR; } + if ((USB_state & USBD_DRIVER_POWERED) == 0U) { return ARM_DRIVER_ERROR; } + + ptr_dqh = &dQH[EP_QHNUM(ep_addr)]; + ep_msk = EP_MSK(ep_addr); + ep_sll = EP_SLL(ep_addr); + + USBD_HW_EndpointFlush(ep_addr); + /*Clear completed Flag*/ + USB->USB_ENDPTCOMPLETE = ep_msk; + ENDPTCTRL(ep_num) |= (USB_ENDPTCTRL_RXR << ep_sll); + + ptr_dqh->dTD_token &= ~0xFFU; + + ptr_dqh->ep_active = 0U; + + return ARM_DRIVER_OK; +} + +/** + * @fn uint16_t USBD_GetFrameNumber (void) + * @brief Get current USB Frame Number. + * @return Frame Number +*/ +static uint16_t USBD_GetFrameNumber (void) { + + if ((USB_state & USBD_DRIVER_POWERED) == 0U) { return 0U; } + + return ((USB->USB_FRINDEX_D & USB_FRINDEX_D_FRINDEX13_3_MSK) >> USB_FRINDEX_D_FRINDEX13_3_POS); +} + +/** + * @fn void USBD0_IRQ (void) + * @brief USB0 Device Interrupt Routine (IRQ). +*/ +void USBD_IRQ (void) { + dQH_t *ptr_dqh; + uint32_t status=0 , complete=0; + uint16_t ep_packet_size=0, received_data=0; + uint8_t ep_num=0, ep_addr=0; + + status = USB->USBSTS_D & USB->USBINTR_D; + /*Read the enpoint complete status*/ + complete = USB->USB_ENDPTCOMPLETE; + + /*Clear all active interrupts*/ + USB->USBSTS_D = status; + /*Endpoint complete status clear*/ + USB->USB_ENDPTCOMPLETE = complete; + + /*Reset interrupt*/ + if ((status & USB_USBSTS_D_URI) != 0U) { + USBD_Reset(); + usbd_state.speed = ARM_USB_SPEED_FULL; + SignalDeviceEvent(ARM_USBD_EVENT_RESET); + } + + /* Suspend interrupt */ + if ((status & USB_USBSTS_D_SLI) != 0U) { + SignalDeviceEvent(ARM_USBD_EVENT_SUSPEND); + +#if (RTE_USB0_IND0_PIN_EN) + USB->USB_PORTSC1_D &= ~USB_PORTSC1_D_PIC15_14(1); // Clear indicator LED0 +#endif + } + /* Port change detect interrupt*/ + if ((status & USB_USBSTS_D_PCI) != 0U) { + if ((( USB->USB_PORTSC1_D & USB_PORTSC1_D_PSPD_MSK) >> USB_PORTSC1_D_PSPD_POS) == 2U) { + usbd_state.speed = ARM_USB_SPEED_HIGH; + SignalDeviceEvent(ARM_USBD_EVENT_HIGH_SPEED); + } else { + usbd_state.speed = ARM_USB_SPEED_FULL; + } + +#if (RTE_USB0_IND0_PIN_EN) + USB->USB_PORTSC1_D |= USB_PORTSC1_D_PIC15_14(1); // Set indicator LED0 +#endif + SignalDeviceEvent(ARM_USBD_EVENT_RESUME); + } + + if ((status & USB_USBSTS_D_UI) != 0U) { /* USB interrupt on short packet rx*/ + if (( USB->USB_ENDPTSETUPSTAT) != 0U) { /* Setup Packet Received*/ + USBD_HW_ReadSetupPacket(); + setup_packet_recv = 1U; + SignalEndpointEvent(0, ARM_USBD_EVENT_SETUP); + } + + if ((complete & USB_ENDPTCOMPLETE_ETCE_MSK) != 0U) { + /*IN packet data sent*/ + for (ep_num = 0U; ep_num <= USBD_MAX_ENDPOINT_NUM; ep_num++) { + if ((complete & USB_ENDPTCOMPLETE_ETCE_MSK) & (1U << (ep_num + USB_ENDPTCOMPLETE_ETCE_POS))) { + ep_addr = ep_num | ARM_USB_ENDPOINT_DIRECTION_MASK; + ptr_dqh = &dQH[EP_QHNUM(ep_addr)]; + + ptr_dqh->num_transferred_total += ptr_dqh->num_transferring; + + /*Max packet data sent ot not*/ + if (ptr_dqh->num == ptr_dqh->num_transferred_total) { + ptr_dqh->ep_active = 0U; + SignalEndpointEvent(ep_addr, ARM_USBD_EVENT_IN); + } else if (ptr_dqh->ep_active != 0U) { + /*Transfer remaining data if max packet data is not transmitted*/ + USBD_HW_EndpointTransfer (ep_addr); + } + } + } + } + /*OUT packet data received*/ + if ((complete & USB_ENDPTCOMPLETE_ERCE_MSK) != 0U) { + for (ep_num = 0U; ep_num <= USBD_MAX_ENDPOINT_NUM; ep_num++) { + if ((complete & USB_ENDPTCOMPLETE_ERCE_MSK) & (1 << ep_num)) { + ep_addr = ep_num; + ptr_dqh = &dQH[EP_QHNUM(ep_addr)]; + ep_packet_size = (ptr_dqh->cap & USB_EPQH_CAP_MAX_PACKET_LEN_MSK) >> USB_EPQH_CAP_MAX_PACKET_LEN_POS; + + received_data = ptr_dqh->num_transferring - + ((ptr_dqh->dTD_token & USB_dTD_TOKEN_TOTAL_BYTES_MSK) >> USB_dTD_TOKEN_TOTAL_BYTES_POS); + ptr_dqh->num_transferred_total += received_data; + + /* check for the All data received and data terminated with zero length packet*/ + if (((received_data % ep_packet_size) != 0U) || (ptr_dqh->num == ptr_dqh->num_transferred_total)) { + ptr_dqh->ep_active = 0U; + SignalEndpointEvent(ep_addr, ARM_USBD_EVENT_OUT); + } else if (ptr_dqh->ep_active != 0U) { + /*if all data is not received receive next*/ + USBD_HW_EndpointTransfer (ep_addr); + } + } + } + } + } +} + + +ARM_DRIVER_USBD Driver_USBD0 = { + USBD_GetVersion, + USBD_GetCapabilities, + USBD_Initialize, + USBD_Uninitialize, + USBD_PowerControl, + USBD_DeviceConnect, + USBD_DeviceDisconnect, + USBD_DeviceGetState, + USBD_DeviceRemoteWakeup, + USBD_DeviceSetAddress, + USBD_ReadSetupPacket, + USBD_EndpointConfigure, + USBD_EndpointUnconfigure, + USBD_EndpointStall, + USBD_EndpointTransfer, + USBD_EndpointTransferGetResult, + USBD_EndpointTransferAbort, + USBD_GetFrameNumber +}; +#endif diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/USBH.c b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/USBH.c new file mode 100644 index 000000000..d1b946312 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/USBH.c @@ -0,0 +1,244 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * $Date: 01. Oct 2018 + * $Revision: V1.0 + * + * Driver: Driver_USBH0_HCI + * Configured: via RTE_Device.h configuration file + * Project: USB Host 0 HCI Controller (EHCI) Driver for Silicon Labs MCU + * -------------------------------------------------------------------------- + * Use the following configuration settings in the middleware component + * to connect to this driver. + * + * Configuration Setting Value + * --------------------- ----- + * Connect to hardware via Driver_USBH# = 0 + * USB Host controller interface = EHCI + * -------------------------------------------------------------------------- */ + +/* History: + * Version 1.0 + * - Initial CMSIS Driver API V5.4.0 release + */ +#include "rsi_ccp_user_config.h" +#if defined(CHIP_9118) +#include "Driver_USBH.h" + + +#include "USB.h" +#include "RTE_Device.h" + + +extern uint8_t USB_role; +extern uint8_t USB_state; + +#define M4SS_CLK_PWR_CTRL_BASE_ADDR 0x46000000 +#define USB_SYSCLK_CLKCLNR_ON (1 << 23) +#define M4SS_CLOCK_CONFIG_REG4 *(volatile uint32_t *)(M4SS_CLK_PWR_CTRL_BASE_ADDR + 0x24) +#define M4SS_CLOCK_CONFIG_REG5 *(volatile uint32_t *)(M4SS_CLK_PWR_CTRL_BASE_ADDR + 0x28) + +#define M4SS_MISC_REG_BASE 0x46008000 + +#define MISC_USB_CONFIG_REG *((volatile uint32_t *)(M4SS_MISC_REG_BASE + 0x1C)) +#define NWPAON_ACCESS_CTRL_CLEAR *((volatile uint32_t *)(NWPAON_MEM_HOST_ACCESS_CTRL_CLEAR)) +#define MISC_CFG_RST_LATCH_STATUS *((volatile uint32_t *)(M4SS_MISC_REG_BASE + 0x10)) +#define MISC_CFG_HOST_CTRL *((volatile uint32_t *)(M4SS_MISC_REG_BASE + 0x0C)) + +#define MISC_USB_SET_REG1 *((volatile uint32_t *)(M4SS_MISC_REG_BASE + 0xF0)) +#define MISC_USB_CLEAR_REG1 *((volatile uint32_t *)(M4SS_MISC_REG_BASE + 0xF4)) + +// USBH EHCI Driver ************************************************************ + +#define ARM_USBH_EHCI_DRIVER_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0) + +// Driver Version +static const ARM_DRIVER_VERSION usbh_ehci_driver_version = { ARM_USBH_API_VERSION, ARM_USBH_EHCI_DRIVER_VERSION }; + +// Driver Capabilities +static const ARM_USBH_HCI_CAPABILITIES usbh_ehci_driver_capabilities = { + 0x0001U // Root HUB available Ports Mask +}; + +static ARM_USBH_HCI_Interrupt_t EHCI_IRQ; + +/** + * @fn void RSI_TimerDelayUs(uint32_t delay_ms) + * @brief This API is used create delay in micro seconds. + * @param[in] delay_ms : timer delay in micro seconds + * @return None + */ +void RSI_DelayUs(uint32_t delay_us) +{ + /**/ + RSI_ULPSS_TimerClkConfig( ULPCLK ,ENABLE_STATIC_CLK,0,ULP_TIMER_32MHZ_RC_CLK,0); + + /* Sets periodic mode */ + RSI_TIMERS_SetTimerMode(TIMERS, ONESHOT_TIMER, TIMER_0); + + /* Sets timer in 1 Micro second mode */ + RSI_TIMERS_SetTimerType(TIMERS, MICRO_SEC_MODE, TIMER_0); + + /* 1 Micro second timer configuration */ + RSI_TIMERS_MicroSecTimerConfig(TIMERS, TIMER_0, 32, 0 ,MICRO_SEC_MODE); + + RSI_TIMERS_SetMatch(TIMERS, TIMER_0,delay_us); + + RSI_TIMERS_TimerStart(TIMERS, TIMER_0); + + while(!RSI_TIMERS_InterruptStatus(TIMERS,TIMER_0 )); +} + + +// USBH EHCI Driver functions + +/** + * @fn ARM_DRIVER_VERSION USBH_HCI_GetVersion (void) + * @brief Get USB Host HCI (OHCI/EHCI) driver version. + * @return \ref ARM_DRIVER_VERSION +*/ +static ARM_DRIVER_VERSION USBH_HCI_GetVersion (void) { return usbh_ehci_driver_version; } + +/** + * @fn ARM_USBH_HCI_CAPABILITIES USBH_HCI_GetCapabilities (void) + * @brief Get driver capabilities. + * @return \ref ARM_USBH_HCI_CAPABILITIES +*/ +static ARM_USBH_HCI_CAPABILITIES USBH_HCI_GetCapabilities (void) { return usbh_ehci_driver_capabilities; } + +/** + * @fn int32_t USBH_HCI_Initialize (ARM_USBH_HCI_Interrupt_t cb_interrupt) + * @brief Initialize USB Host HCI (OHCI/EHCI) Interface. + * @param[in] cb_interrupt : Pointer to Interrupt Handler Routine + * @return \ref execution_status +*/ +static int32_t USBH_HCI_Initialize (ARM_USBH_HCI_Interrupt_t cb_interrupt) { + + if ((USB_state & USBH_DRIVER_INITIALIZED) != 0U) { return ARM_DRIVER_OK; } + + EHCI_IRQ = cb_interrupt; + + USB_role = ARM_USB_ROLE_HOST; + + /*USB_PinsConfigure*/ + RSI_EGPIO_SetPinMux(EGPIO,RTE_USB_OTG_PORT,RTE_USB_OTG_PIN,EGPIO_PIN_MUX_MODE0); + + RSI_EGPIO_SetDir(EGPIO,RTE_USB_OTG_PORT,RTE_USB_OTG_PIN,EGPIO_CONFIG_DIR_OUTPUT); + + RSI_EGPIO_SetPin(EGPIO,RTE_USB_OTG_PORT,RTE_USB_OTG_PIN,RTE_USB_OTG_STATUS_HIGH); + + USB_state = USBH_DRIVER_INITIALIZED; + + return ARM_DRIVER_OK; +} + +/** + * @fn int32_t USBH_HCI_Uninitialize (void) + * @brief De-initialize USB Host HCI (OHCI/EHCI) Interface. + * @return \ref execution_status +*/ +static int32_t USBH_HCI_Uninitialize (void) { + + + USB_role = ARM_USB_ROLE_NONE; + USB_state &= ~USBH_DRIVER_INITIALIZED; + + /*Uninitialize the USB pin configuration*/ + RSI_EGPIO_SetPin(EGPIO,RTE_USB_OTG_MODE,RTE_USB_OTG_PIN,RTE_USB_OTG_STATUS_LOW); + + return ARM_DRIVER_OK; +} + +/** + * @fn int32_t USBH_HCI_PowerControl (ARM_POWER_STATE state) + * @brief Control USB Host HCI (OHCI/EHCI) Interface Power. + * @param[in] state : Power state + * @return \ref execution_status +*/ +static int32_t USBH_HCI_PowerControl (ARM_POWER_STATE state) { + + switch (state) { + case ARM_POWER_OFF: + NVIC_DisableIRQ (USB_IRQn); // Disable interrupt + NVIC_ClearPendingIRQ (USB_IRQn); // Clear pending interrupt + /*USB Host detection disable through software */ + MISC_CFG_HOST_CTRL |=(BIT(14) & (~BIT(12))); + USB_state &= ~USBH_DRIVER_POWERED; // Clear powered flag + break; + + case ARM_POWER_FULL: + if ((USB_state & USBH_DRIVER_INITIALIZED) == 0U) { return ARM_DRIVER_ERROR; } + if ((USB_state & USBH_DRIVER_POWERED) != 0U) { return ARM_DRIVER_OK; } + + /*USB configuration*/ + MISC_USB_CONFIG_REG =0x11; + /*USB Host detection through software */ + MISC_CFG_HOST_CTRL |=(BIT(14) | BIT(12)); + /*USB in m4*/ + NWPAON_ACCESS_CTRL_CLEAR = BIT(4); + /*USB is in soft reset*/ + MISC_USB_SET_REG1 =BIT(0); + /*100ms delay*/ + RSI_DelayUs(100000); + /*USB soft reset release after 100ms*/ + MISC_USB_CLEAR_REG1 =BIT(0); + + USB_state |= USBH_DRIVER_POWERED; // Set powered flag + NVIC_EnableIRQ (USB_IRQn); + + break; + + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + return ARM_DRIVER_OK; +} + +/** + * @fn int32_t USBH_HCI_PortVbusOnOff (uint8_t port, bool vbus) + * @brief USB Host HCI (OHCI/EHCI) Root HUB Port VBUS on/off. + * @param[in] port : Root HUB Port Number + * @param[in] vbus : + - \b false VBUS off + - \b true VBUS on + \return \ref execution_status +*/ +static int32_t USBH_HCI_PortVbusOnOff (uint8_t port, bool power) { + + /*VBUS signal is controlled by ehci only*/ + if (((1U << port) & usbh_ehci_driver_capabilities.port_mask) == 0U) { return ARM_DRIVER_ERROR; } + return ARM_DRIVER_OK; +} + +/** + * @fn void USBH0_IRQ (void) + * @brief USB0 Host Interrupt Routine (IRQ). +*/ +void USBH_IRQ (void) { + EHCI_IRQ(); +} + +ARM_DRIVER_USBH_HCI Driver_USBH0_HCI = { + USBH_HCI_GetVersion, + USBH_HCI_GetCapabilities, + USBH_HCI_Initialize, + USBH_HCI_Uninitialize, + USBH_HCI_PowerControl, + USBH_HCI_PortVbusOnOff +}; +#endif diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/component/cmsis_can.slcc b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/component/cmsis_can.slcc new file mode 100644 index 000000000..b86d70a87 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/component/cmsis_can.slcc @@ -0,0 +1,18 @@ +id: cmsis_can +label: CMSIS CAN +package: platform +description: > + Controller Area Network Driver API's +category: Device|Si91x|MCU|Internal|CMSIS Drivers +quality: production +component_root_path: "components/device/silabs/si91x/mcu/drivers" +ui_hints: + visibility: never +source: + - path: "cmsis_driver/CAN.c" +include: + - path: "cmsis_driver" + file_list: + - path: "CAN.h" +provides: + - name: cmsis_can \ No newline at end of file diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/component/cmsis_emac.slcc b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/component/cmsis_emac.slcc new file mode 100644 index 000000000..4f9388f2b --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/component/cmsis_emac.slcc @@ -0,0 +1,18 @@ +id: cmsis_emac +label: CMSIS EMAC +package: platform +description: > + EMAC Driver API's +category: Device|Si91x|MCU|Internal|CMSIS Drivers +quality: production +ui_hints: + visibility: never +component_root_path: "components/device/silabs/si91x/mcu/drivers" +source: + - path: "cmsis_driver/EMAC.c" +include: + - path: "cmsis_driver" + file_list: + - path: "EMAC.h" +provides: + - name: cmsis_emac \ No newline at end of file diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/component/cmsis_mci.slcc b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/component/cmsis_mci.slcc new file mode 100644 index 000000000..09b9c868b --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/component/cmsis_mci.slcc @@ -0,0 +1,18 @@ +id: cmsis_mci +label: CMSIS MCI +package: platform +description: > + MCI Driver API's +category: Device|Si91x|MCU|Internal|CMSIS Drivers +quality: production +ui_hints: + visibility: never +component_root_path: "components/device/silabs/si91x/mcu/drivers" +source: + - path: "cmsis_driver/MCI.c" +include: + - path: "cmsis_driver" + file_list: + - path: "MCI.h" +provides: + - name: cmsis_mci \ No newline at end of file diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/component/cmsis_phy_lan.slcc b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/component/cmsis_phy_lan.slcc new file mode 100644 index 000000000..3cbcc29fc --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/component/cmsis_phy_lan.slcc @@ -0,0 +1,18 @@ +id: cmsis_phy_lan +label: CMSIS PHY LAN 8742A +package: platform +description: > + CMSIS PHY LAN 8742A Driver API's +category: Device|Si91x|MCU|Internal|CMSIS Drivers +quality: production +ui_hints: + visibility: never +component_root_path: "components/device/silabs/si91x/mcu/drivers" +source: + - path: "cmsis_driver/PHY_LAN8742A.c" +include: + - path: "cmsis_driver" + file_list: + - path: "PHY_LAN8742A.h" +provides: + - name: cmsis_phy_lan \ No newline at end of file diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/component/cmsis_usb.slcc b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/component/cmsis_usb.slcc new file mode 100644 index 000000000..83c3da890 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/component/cmsis_usb.slcc @@ -0,0 +1,18 @@ +id: cmsis_usb +label: CMSIS USB +package: platform +description: > + Universal Serial Bus Driver API's +category: Device|Si91x|MCU|Internal|CMSIS Drivers +quality: production +ui_hints: + visibility: never +component_root_path: "components/device/silabs/si91x/mcu/drivers" +source: + - path: "cmsis_driver/USB.c" +include: + - path: "cmsis_driver" + file_list: + - path: "USB.h" +provides: + - name: cmsis_usb \ No newline at end of file diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/component/cmsis_usbd.slcc b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/component/cmsis_usbd.slcc new file mode 100644 index 000000000..58230c6ba --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/component/cmsis_usbd.slcc @@ -0,0 +1,14 @@ +id: cmsis_usbd +label: CMSIS USBD +package: platform +description: > + USBD Driver APIs's +category: Device|Si91x|MCU|Internal|CMSIS Drivers +quality: production +ui_hints: + visibility: never +component_root_path: "components/device/silabs/si91x/mcu/drivers" +source: + - path: "cmsis_driver/USBD.c" +provides: + - name: cmsis_usbd \ No newline at end of file diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/component/cmsis_usbh.slcc b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/component/cmsis_usbh.slcc new file mode 100644 index 000000000..222e0c6f8 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/component/cmsis_usbh.slcc @@ -0,0 +1,14 @@ +id: cmsis_usbh +label: CMSIS USBH +package: platform +description: > + USBH Driver API's +category: Device|Si91x|MCU|Internal|CMSIS Drivers +quality: production +ui_hints: + visibility: never +component_root_path: "components/device/silabs/si91x/mcu/drivers" +source: + - path: "cmsis_driver/USBH.c" +provides: + - name: cmsis_usbh \ No newline at end of file diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/component/rsilib_cci.slcc b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/component/rsilib_cci.slcc new file mode 100644 index 000000000..e066a598c --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/component/rsilib_cci.slcc @@ -0,0 +1,18 @@ +id: rsilib_cci +label: CCI +package: platform +description: > + Companion Chip Interface Peripheral API's +category: Device|Si91x|MCU|Internal|RSI Peripheral Drivers +quality: production +ui_hints: + visibility: never +component_root_path: "components/device/silabs/si91x/mcu/drivers/peripheral_drivers" +source: + - path: "src/rsi_cci.c" +include: + - path: "inc" + file_list: + - path: "rsi_cci.h" +provides: + - name: rsilib_cci \ No newline at end of file diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/component/rsilib_fim.slcc b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/component/rsilib_fim.slcc new file mode 100644 index 000000000..cde564b4f --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/component/rsilib_fim.slcc @@ -0,0 +1,18 @@ +id: rsilib_fim +label: FIM +package: platform +description: > + Filter Interpolation Matrix Multiplication Peripheral API's +category: Device|Si91x|MCU|Internal|RSI Peripheral Drivers +quality: production +ui_hints: + visibility: never +component_root_path: "components/device/silabs/si91x/mcu/drivers/peripheral_drivers" +source: + - path: "src/rsi_fim.c" +include: + - path: "inc" + file_list: + - path: "rsi_fim.h" +provides: + - name: rsilib_fim diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/component/rsilib_ir.slcc b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/component/rsilib_ir.slcc new file mode 100644 index 000000000..78d6e7ad1 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/component/rsilib_ir.slcc @@ -0,0 +1,18 @@ +id: rsilib_ir +label: IR +package: platform +description: > + Infrared Peripheral API's +category: Device|Si91x|MCU|Internal|RSI Peripheral Drivers +quality: production +ui_hints: + visibility: never +component_root_path: "components/device/silabs/si91x/mcu/drivers/peripheral_drivers" +source: + - path: "src/rsi_ir.c" +include: + - path: "inc" + file_list: + - path: "rsi_ir.h" +provides: + - name: rsilib_ir diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/component/rsilib_sdioh.slcc b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/component/rsilib_sdioh.slcc new file mode 100644 index 000000000..bbd342d98 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/component/rsilib_sdioh.slcc @@ -0,0 +1,18 @@ +id: rsilib_sdioh +label: SDIOH +package: platform +description: > + SDIOH Peripheral API's +category: Device|Si91x|MCU|Internal|RSI Peripheral Drivers +quality: production +ui_hints: + visibility: never +component_root_path: "components/device/silabs/si91x/mcu/drivers/peripheral_drivers" +source: + - path: "src/rsi_sdioh.c" +include: + - path: "inc" + file_list: + - path: "rsi_sdioh.h" +provides: + - name: rsilib_sdioh diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/component/rsilib_sdmem.slcc b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/component/rsilib_sdmem.slcc new file mode 100644 index 000000000..12fbc8268 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/component/rsilib_sdmem.slcc @@ -0,0 +1,18 @@ +id: rsilib_sdmem +label: SDMEM +package: platform +description: > + SDMEM Peripheral API's +category: Device|Si91x|MCU|Internal|RSI Peripheral Drivers +quality: production +ui_hints: + visibility: never +component_root_path: "components/device/silabs/si91x/mcu/drivers/peripheral_drivers" +source: + - path: "src/rsi_sdmem.c" +include: + - path: "inc" + file_list: + - path: "rsi_sdmem.h" +provides: + - name: rsilib_sdmem diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/component/rsilib_smih.slcc b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/component/rsilib_smih.slcc new file mode 100644 index 000000000..081f4762b --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/component/rsilib_smih.slcc @@ -0,0 +1,18 @@ +id: rsilib_smih +label: SMIH +package: platform +description: > + SMIH Peripheral API's +category: Device|Si91x|MCU|Internal|RSI Peripheral Drivers +quality: production +ui_hints: + visibility: never +component_root_path: "components/device/silabs/si91x/mcu/drivers/peripheral_drivers" +source: + - path: "src/rsi_smih.c" +include: + - path: "inc" + file_list: + - path: "rsi_smih.h" +provides: + - name: rsilib_smih \ No newline at end of file diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/component/rsilib_vad.slcc b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/component/rsilib_vad.slcc new file mode 100644 index 000000000..8619fad02 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/component/rsilib_vad.slcc @@ -0,0 +1,18 @@ +id: rsilib_vad +label: VAD +package: platform +description: > + Voice Activity Detection API's +category: Device|Si91x|MCU|Internal|RSI Peripheral Drivers +quality: production +ui_hints: + visibility: never +component_root_path: "components/device/silabs/si91x/mcu/drivers/peripheral_drivers" +source: + - path: "src/rsi_vad.c" +include: + - path: "inc" + file_list: + - path: "rsi_vad.h" +provides: + - name: rsilib_vad \ No newline at end of file diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/component/rsilib_wurx.slcc b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/component/rsilib_wurx.slcc new file mode 100644 index 000000000..5332277cf --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/component/rsilib_wurx.slcc @@ -0,0 +1,18 @@ +id: rsilib_wurx +label: WURX +package: platform +description: > + WURX Peripheral API's +category: Device|Si91x|MCU|Internal|RSI Peripheral Drivers +quality: production +ui_hints: + visibility: never +component_root_path: "components/device/silabs/si91x/mcu/drivers/peripheral_drivers" +source: + - path: "src/rsi_wurx.c" +include: + - path: "inc" + file_list: + - path: "rsi_wurx.h" +provides: + - name: rsilib_wurx \ No newline at end of file diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_cci.h b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_cci.h new file mode 100644 index 000000000..04d9bd2d4 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_cci.h @@ -0,0 +1,104 @@ +/******************************************************************************* +* @file rsi_cci.h +* @brief +******************************************************************************* +* # License +* Copyright 2022 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +// Includes Files + +#include "RS1xxxx.h" +#include "rsi_error.h" + +#ifndef RSI_CCI_H +#define RSI_CCI_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define AMS_EN *(volatile uint32_t *)(0x46008000 + 0x14) + +#define CCI_AHB_SLAVE0_ADDRESS 0x80000000 +#define CCI_AHB_SLAVE1_ADDRESS 0x60000000 + +#define CCI_LSB_ADDRESS_S0 0x00000000 +#define CCI_MSB_ADDRESS_S0 0x0001FFFF + +#define CCI_LSB_ADDRESS_S1 0x00000000 +#define CCI_MSB_ADDRESS_S1 0x00000004 // 0x0001FFFF FIXME: Out of RANGE INDEX COMPARISION + +#define CCI_LSB_ADDRESS_S2 0x00000000 +#define CCI_MSB_ADDRESS_S2 0x00000004 // 0x0001FFFF FIXME: Out of RANGE INDEX COMPARISION + +#define CCI_LSB_ADDRESS_S3 0x00000000 +#define CCI_MSB_ADDRESS_S3 0x00000004 // 0x0001FFFF FIXME: Out of RANGE INDEX COMPARISION + +// CCI configuration structure +typedef struct RSI_CCI_Init_s { + + uint8_t slave_enable; // number of CCI Slaves to be supported 1,2,3 + uint8_t early_bus_termination; // Support early bus termination + // 0 - disable + // 1 - enable + uint8_t address_width_config; // Address width configuration + // b'11 -> 40 bit width (32 bit address and 8 bit command) + // b'10 -> 32 bit width (24 bit address and 8 bit command) + // b'01 -> 24 bit width (16 bit address and 8 bit command) + // b'00 -> 16 bit width (8 bit address and 8 bit command) + uint8_t translation_enable; // Enable/Disable translation + // 0 - Disable + // 1 - Enable + uint32_t translation_address; // load translation address + uint8_t mode; // Mode of the interface + // 0 - SDR mode + // 1 - DDR mode + uint8_t prog_calib; + uint8_t interface_width; // Width of the interface + // 0 - quad mode + // 1 - octa mode + // 2 - Word mode + uint8_t slave_priority; // This bits will represents priority of the slaves + // 1 : slave 0 has highest priority + // 4 : slave 1 has highest priority + // 8 : slave 2 has highest priority + uint16_t slave_timeout; // configurable time out value for response + uint32_t slave_lsb_address[3]; // Slave lower and higher address range for the each slave by programming + uint32_t slave_msb_address[3]; // Slave lower and higher address range for the each slave by programming + uint8_t cci_cntrl_en; +} RSI_CCI_Init_t; + +void RSI_CCI_AmsEnable(void); + +rsi_error_t RSI_CCI_AMS_Initialise(RSI_CCI_Init_t *p_cci_config); + +uint32_t RSI_CCI_SetFifoThreshlod(volatile CCI_Type *pstcCCI, uint8_t val); + +uint32_t RSI_CCI_PrefetchEnable(volatile CCI_Type *pstcCCI); + +uint32_t RSI_CCI_MessageInterruptEnable(volatile CCI_Type *pstcCCI); + +void RSI_CCI_CalibMode(volatile CCI_Type *pstcCCI); + +void RSI_CCI_LowPowerMode(volatile CCI_Type *pstcCCI); + +uint32_t RSI_CCI_IntStat(volatile CCI_Type *pstcCCI); + +uint32_t RSI_CCI_IntClear(volatile CCI_Type *pstcCCI, uint8_t interrupt); + +uint32_t RSI_CCI_SlaveResetMode(volatile CCI_Type *pstcCCI); +#ifdef __cplusplus +} +#endif + +#endif // RSI_CCI_H diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_fim.h b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_fim.h new file mode 100644 index 000000000..ab47a2c01 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_fim.h @@ -0,0 +1,725 @@ +/******************************************************************************* +* @file rsi_fim.h +* @brief +******************************************************************************* +* # License +* Copyright 2022 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +// Includes Files + +#include "base_types.h" +#include "rsi_error.h" +#include "rsi_ccp_common.h" + +#ifdef ARM_MATH_DEF +#include "arm_math.h" +#endif + +#ifndef RSI_FIM_H +#define RSI_FIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef float float32_t; + +// brief 8-bit fractional data type in 1.7 format. + +typedef int8_t q7_t; + +// brief 16-bit fractional data type in 1.15 format. + +typedef int16_t q15_t; + +// brief 32-bit fractional data type in 1.31 format. +typedef int32_t q31_t; + +typedef enum { + ULP_FIM_COP_DATA_REAL_REAL = 0, + ULP_FIM_COP_DATA_CPLX_REAL, + ULP_FIM_COP_DATA_REAL_CPLX, + ULP_FIM_COP_DATA_CPLX_CPLX +} typ_data_t; + +#define ULP_FIM_COP_START_TRIG 0x01 +#define XMAX(x, y) (((x) > (y)) ? (x) : (y)) +#define MEM_BANK 0x24060000 + +// For 9117 FIM +#define ENHANCED_FIM_BANK0 0x24060000 +#define ENHANCED_FIM_BANK1 0x24060800 +#define ENHANCED_FIM_BANK2 0x24061000 +#define ENHANCED_FIM_BANK3 0x24061800 + +#define ULPSS_RAM_ADDR_SRC ENHANCED_FIM_BANK0 +#define ULPSS_RAM_ADDR_DST ENHANCED_FIM_BANK2 + +#define ULPSS_RAM_ADDR_SRC1 ENHANCED_FIM_BANK0 +#define ULPSS_RAM_ADDR_SRC2 ENHANCED_FIM_BANK1 +#define ULP_MEMORY_ADDR 0x24060000 + +// For 9116 FIM +#define BANK0 0x00 +#define BANK1 (0x0800 >> 2) +#define BANK2 (0x1000 >> 2) +#define BANK3 (0x1800 >> 2) +#define BANK4 (0x2000 >> 2) +#define BANK5 (0x2800 >> 2) +#define BANK6 (0x3000 >> 2) +#define BANK7 (0x3800 >> 2) +#define STRS(sat, trunc, round, shift) ((round << 16) | (shift << 10) | (trunc << 5) | sat) + +typedef enum mode { + FIR = 0x01, + IIR = 0x02, + INTERPOLATE = 0x63, + ADD_SCALAR = 0x44, + SUB_SCALAR = 0x45, + MUL_SCALAR = 0x46, + ADD_VECTOR = 0x47, + SUB_VECTOR = 0x49, + MUL_VECTOR = 0x4A, + NORM_SQUARE = 0xAB, + MUL_MAT = 0x4C, +#ifdef ENHANCED_FIM + CORRELATION = 0x3, + DECIMATION = 0x4, + FFT = 0x8, + ADD_MAT = 0x4D, + SUB_MAT = 0x4E, + MAT_HADAMARD = 0x4F, + MAT_TRANSPOSE = 0x50, + COR_SINE = 0x51, + COR_COSINE = 0x52, + COR_INV_TAN = 0x54, + COR_SINH = 0x55, + COR_COSH = 0x56, + COR_INV_TANH = 0x57, + SQ_ROOT = 0x58, + NAT_LOG = 0x59, +#endif +} present_mode; + +#define FORMAT_Q7 2 +#define FORMAT_Q15 3 +#define FORMAT_Q31 1 +#define FORMAT_F32 0 + +#define NOT_MATRIX 0 +#define M4SS_ADDR_SHIFT_VAL 2 + +// list of variables for matrix multiplication +typedef struct { + int16_t nRows; + int16_t nColumns; + int32_t *pData; +} arm_matrix_instance_f32_opt; + +typedef struct { + uint16_t nRows; + uint16_t nColumns; + q31_t *pData; +} arm_matrix_instance_q31_opt; + +typedef struct { + int16_t nRows; + int16_t nColumns; + q15_t *pData; +} arm_matrix_instance_q15_opt; + +// list of variables for fir filter +typedef struct { + uint16_t numTaps; + int32_t *pState; + int32_t *pCoeffs; +} arm_fir_instance_f32_opt; + +typedef struct { + uint16_t numTaps; + q31_t *pState; + q31_t *pCoeffs; +} arm_fir_instance_q31_opt; + +typedef struct { + uint16_t numTaps; + q15_t *pState; + q15_t *pCoeffs; +} arm_fir_instance_q15_opt; + +typedef struct { + uint16_t numTaps; + q7_t *pState; + q7_t *pCoeffs; +} arm_fir_instance_q7_opt; + +// list of variables for Iir filter +typedef struct { + uint16_t numStages; + int32_t *pState; + int32_t *pkCoeffs; + int32_t *pvCoeffs; +} fim_iir_instance_f32; + +typedef struct { + uint16_t numStages; + q31_t *pState; + q31_t *pkCoeffs; + q31_t *pvCoeffs; +} fim_iir_instance_q31; + +typedef struct { + uint16_t numStages; + q15_t *pState; + q15_t *pkCoeffs; + q15_t *pvCoeffs; +} fim_iir_instance_q15; + +typedef struct { + uint8_t L; // upsample factor. + uint16_t phaseLength; // length of each polyphase filter component. + int32_t *pCoeffs; // points to the coefficient array. The array is of length L*phaseLength. + int32_t *pState; // points to the state variable array. The array is of length phaseLength+numTaps-1. +} arm_fir_interpolate_instance_f32_opt; + +#ifndef ARM_MATH_DEF +typedef enum { + ARM_MATH_SUCCESS = 0, // No error + ARM_MATH_ARGUMENT_ERROR = -1, // One or more arguments are incorrect + ARM_MATH_LENGTH_ERROR = -2, // Length of data buffer is incorrect + ARM_MATH_SIZE_MISMATCH = -3, // Size of matrices is not compatible with the operation. + ARM_MATH_NANINF = -4, // Not-a-number (NaN) or infinity is generated + ARM_MATH_SINGULAR = -5, // Generated by matrix inversion if the input matrix is singular and cannot be inverted. + ARM_MATH_TEST_FAILURE = -6 // Test Failed +} arm_status; +#endif + +// brief Instance structure for the Q15 FIR interpolator. +typedef struct { + uint8_t L; // upsample factor. + uint16_t phaseLength; // length of each polyphase filter component + q15_t *pCoeffs; // points to the coefficient array. The array is of length L*phaseLength. + q15_t *pState; // points to the state variable array. The array is of length blockSize+phaseLength-1. +} arm_fir_interpolate_instance_q15_opt; + +// brief Instance structure for the Q31 FIR interpolator. +typedef struct { + uint8_t L; // upsample factor. + uint16_t phaseLength; // length of each polyphase filter component. + q31_t *pCoeffs; // points to the coefficient array. The array is of length L*phaseLength. + q31_t *pState; // points to the state variable array. The array is of length blockSize+phaseLength-1. +} arm_fir_interpolate_instance_q31_opt; + +#ifdef ENHANCED_FIM + +// brief Instance structure for the Q15 FIR decimate. +typedef struct { + uint8_t M; // decimation factor.. + uint16_t numTaps; // number of coefficients in the filter. + const q15_t *pCoeffs; // points to the coefficient array. The array is of length numTaps. + q15_t *pState; // points to the state variable array. The array is of length numTaps+blockSize-1. +} arm_fir_decimate_instance_q15; + +typedef struct { + uint8_t M; // decimation factor. + uint16_t numTaps; // number of coefficients in the filter. + const q31_t *pCoeffs; // points to the coefficient array. The array is of length numTaps. + q31_t *pState; // points to the state variable array. The array is of length numTaps+blockSize-1. +} arm_fir_decimate_instance_q31; + +typedef struct { + uint16_t fftLen; // length of the FFT. + const q15_t *pTwiddle; // points to the Twiddle factor table. + const uint16_t *pBitRevTable; // points to the bit reversal table. + uint16_t bitRevLength; // bit reversal table length. +} arm_cfft_radix2_instance_q15; +#endif + +// FIM Function Prototypes +void rsi_arm_offset_f32_opt(int32_t *pSrc, + int32_t scale, + int32_t *pDst, + uint32_t length, + uint16_t inBank, + uint16_t outBank); + +void rsi_arm_offset_q7_opt(q7_t *pSrc, q7_t scale, q7_t *pDst, uint32_t length, uint16_t inBank, uint16_t outBank); + +void rsi_arm_offset_q15_opt(q15_t *pSrc, q15_t scale, q15_t *pDst, uint32_t length, uint16_t inBank, uint16_t outBank); + +void rsi_arm_offset_q31_opt(q31_t *pSrc, q31_t scale, q31_t *pDst, uint32_t length, uint16_t inBank, uint16_t outBank); + +void rsi_fim_scalar_add_q15(q15_t *pSrc, + q15_t *scale, + uint32_t blockSize, + typ_data_t typ_data, + uint16_t inBank, + uint16_t outBank); + +void rsi_fim_scalar_sub_q7(q7_t *pSrc, q7_t scale, q7_t *pDst, uint32_t blockSize, uint16_t inBank, uint16_t outBank); + +void rsi_fim_scalar_sub_q15(q15_t *pSrc, + q15_t *scale, + q15_t *pDst, + uint32_t blockSize, + typ_data_t typ_data, + uint16_t inBank, + uint16_t outBank); + +void rsi_fim_scalar_sub_q31(q31_t *pSrc, + q31_t scale, + q31_t *pDst, + uint32_t blockSize, + uint16_t inBank, + uint16_t outBank); + +void rsi_fim_scalar_sub_f32(int32_t *pSrc, + int32_t scale, + int32_t *pDst, + uint32_t length, + uint16_t inBank, + uint16_t outBank); + +void rsi_arm_scale_f32_opt(int32_t *pSrc, + int32_t scale, + int32_t *pDst, + uint32_t length, + uint16_t inBank, + uint16_t outBank); + +void rsi_arm_scale_q7_opt(q7_t *pSrc, + q7_t scaleFract, + int8_t shift, + q7_t *pDst, + uint32_t blockSize, + uint16_t inBank, + uint16_t outBank); + +void rsi_arm_scale_q15_opt(q15_t *pSrc, + q15_t scaleFract, + int8_t shift, + q15_t *pDst, + uint32_t blockSize, + uint16_t inBank, + uint16_t outBank); + +void rsi_arm_scale_q31_opt(q31_t *pSrc, + q31_t scaleFract, + int8_t shift, + q31_t *pDst, + uint32_t blockSize, + uint16_t inBank, + uint16_t outBank); + +void rsi_fim_scalar_mul_q15(q15_t *pSrc, + q15_t *scale, + q15_t *pDst, + uint32_t blockSize, + typ_data_t typ_data, + uint16_t inBank, + uint16_t outBank); + +void rsi_fim_interrupt_handler(volatile FIM_Type *ptFim); + +void rsi_arm_add_f32_opt(int32_t *pSrcA, + int32_t *pSrcB, + int32_t *pDst, + uint32_t blockSize, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank); + +void rsi_arm_add_q7_opt(q7_t *pSrcA, + q7_t *pSrcB, + q7_t *pDst, + uint32_t blockSize, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank); + +void rsi_arm_add_q15_opt(q15_t *pSrcA, + q15_t *pSrcB, + q15_t *pDst, + uint32_t blockSize, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank); + +void rsi_arm_add_q31_opt(q31_t *pSrcA, + q31_t *pSrcB, + q31_t *pDst, + uint32_t blockSize, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank); + +void rsi_fim_vector_add_q15(q15_t *pIn1, + q15_t *pIn2, + q15_t *pDst, + uint32_t blockSize, + typ_data_t typ_data, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank); + +void rsi_arm_sub_f32_opt(int32_t *pSrcA, + int32_t *pSrcB, + int32_t *pDst, + uint32_t blockSize, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank); + +void rsi_arm_sub_q7_opt(q7_t *pSrcA, + q7_t *pSrcB, + q7_t *pDst, + uint32_t blockSize, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank); + +void rsi_arm_sub_q15_opt(q15_t *pSrcA, + q15_t *pSrcB, + q15_t *pDst, + uint32_t blockSize, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank); + +void rsi_arm_sub_q31_opt(q31_t *pSrcA, + q31_t *pSrcB, + q31_t *pDst, + uint32_t blockSize, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank); + +void rsi_fim_read_data(uint32_t bank, uint32_t length, volatile void *pDst, uint8_t data_type, typ_data_t type_data); + +void rsi_fim_vector_sub_q15(q15_t *pIn1, + q15_t *pIn2, + q15_t *pDst, + uint32_t blockSize, + typ_data_t typ_data, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank); + +void rsi_arm_mult_f32_opt(int32_t *pIn1, + int32_t *pIn2, + int32_t *pDst, + uint32_t SatTruncRound, + uint32_t length, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank); + +void rsi_arm_mult_q7_opt(q7_t *pSrcA, + q7_t *pSrcB, + q7_t *pDst, + uint32_t blockSize, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank); + +void rsi_arm_mult_q15_opt(q15_t *pSrcA, + q15_t *pSrcB, + q15_t *pDst, + uint32_t blockSize, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank); + +void rsi_arm_mult_q31_opt(q31_t *pSrcA, + q31_t *pSrcB, + q31_t *pDst, + uint32_t blockSize, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank); + +void rsi_fim_vector_mul_q15(q15_t *pIn1, + q15_t *pIn2, + q15_t *pDst, + uint32_t blockSize, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank); + +void rsi_arm_cmplx_mult_real_q15_opt(q15_t *pSrcCmplx, + q15_t *pSrcReal, + q15_t *pDst, + uint32_t numSamples, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank); + +void rsi_arm_cmplx_mult_cmplx_q15_opt(q15_t *pSrcA, + q15_t *pSrcB, + q15_t *pDst, + uint32_t numSamples, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank); + +void rsi_arm_cmplx_mag_squared_q15_opt(q15_t *pSrc, + q15_t *pDst, + uint32_t numSamples, + uint16_t inBank, + uint16_t outBank); + +void rsi_fim_absSqr_q7(q7_t *pSrc, q7_t *pDst1, uint32_t blockSize, uint16_t inBank, uint16_t outBank); +void rsi_fim_absSqr_q15(q15_t *pSrc, q15_t *pDst, uint32_t blockSize, uint16_t inBank, uint16_t outBank); +void rsi_fim_absSqr_q31(q31_t *pSrc, q31_t *pDst, uint32_t length, uint16_t inBank, uint16_t outBank); +void rsi_fim_absSqr_f32(int32_t *pSrc, int32_t *pDst, uint32_t length, uint16_t inBank, uint16_t outBank); + +rsi_error_t rsi_arm_mat_mult_f32_opt(const arm_matrix_instance_f32_opt *pSrcA, + const arm_matrix_instance_f32_opt *pSrcB, + arm_matrix_instance_f32_opt *pDst, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank); + +rsi_error_t rsi_arm_mat_mult_q31_opt(const arm_matrix_instance_q31_opt *pSrcA, + const arm_matrix_instance_q31_opt *pSrcB, + arm_matrix_instance_q31_opt *pDst, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank); + +rsi_error_t rsi_arm_mat_mult_q15_opt(const arm_matrix_instance_q15_opt *pSrcA, + const arm_matrix_instance_q15_opt *pSrcB, + arm_matrix_instance_q15_opt *pDst, + q15_t *pState, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank); + +void rsi_arm_fir_init_f32_opt(arm_fir_instance_f32_opt *S, + uint16_t numTaps, + int32_t *pCoeffs, + int32_t *pState, + uint32_t blockSize); + +void rsi_arm_fir_f32_opt(arm_fir_instance_f32_opt *S, + int32_t *pSrc, + int32_t *pDst, + uint32_t blockSize, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank); + +void rsi_arm_fir_init_q31_opt(arm_fir_instance_q31_opt *S, + uint16_t numTaps, + q31_t *pCoeffs, + q31_t *pState, + uint32_t blockSize); + +void rsi_arm_fir_q31_opt(arm_fir_instance_q31_opt *S, + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank); + +void rsi_arm_fir_init_q15_opt(arm_fir_instance_q15_opt *S, + uint16_t numTaps, + q15_t *pCoeffs, + q15_t *pState, + uint32_t blockSize); + +void rsi_arm_fir_q15_opt(arm_fir_instance_q15_opt *S, + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank); + +void rsi_fim_fir_q15(arm_fir_instance_q15_opt *S, + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize, + typ_data_t typ_data, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank); + +void rsi_arm_fir_init_q7_opt(arm_fir_instance_q7_opt *S, + uint16_t numTaps, + q7_t *pCoeffs, + q7_t *pState, + uint32_t blockSize); + +void rsi_arm_fir_q7_opt(arm_fir_instance_q7_opt *S, + q7_t *pSrc, + q7_t *pDst, + uint32_t blockSize, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank); + +void rsi_fim_Iir_init_f32(fim_iir_instance_f32 *S, + uint16_t numStages, + int32_t *pCoeffs, + int32_t *pvCoeffs, + int32_t *pState); + +void rsi_fim_Iir_init_q31(fim_iir_instance_q31 *S, + uint16_t numStages, + q31_t *pCoeffs, + q31_t *pvCoeffs, + uint32_t *pState); + +void rsi_fim_Iir_q31(fim_iir_instance_q31 *S, + int32_t *pSrc, + q31_t *pDst, + uint32_t blockSize, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank); + +void rsi_fim_Iir_init_q15(fim_iir_instance_q15 *S, uint16_t numStages, q15_t *pCoeffs, q15_t *pvCoeffs, q15_t *pState); + +void rsi_fim_Iir_q15(fim_iir_instance_q15 *S, + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize, + typ_data_t typ_data, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank); + +void rsi_fim_Iir_f32(fim_iir_instance_f32 *S, + int32_t *pSrc, + int32_t *pDst, + uint32_t length, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank); + +void rsi_arm_fir_interpolate_f32_opt(const arm_fir_interpolate_instance_f32_opt *S, + int32_t *pSrc, + int32_t *pDst, + uint32_t blockSize, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank); + +arm_status rsi_arm_fir_interpolate_init_f32_opt(arm_fir_interpolate_instance_f32_opt *S, + uint8_t L, + uint16_t numTaps, + int32_t *pCoeffs, + int32_t *pState, + uint32_t blockSize); + +arm_status rsi_arm_fir_interpolate_init_q15_opt(arm_fir_interpolate_instance_q15_opt *S, + uint8_t L, + uint16_t numTaps, + q15_t *pCoeffs, + q15_t *pState, + uint32_t blockSize); + +arm_status rsi_arm_fir_interpolate_init_q31_opt(arm_fir_interpolate_instance_q31_opt *S, + uint8_t L, + uint16_t numTaps, + q31_t *pCoeffs, + q31_t *pState, + uint32_t blockSize); + +void rsi_arm_fir_interpolate_q15_opt(arm_fir_interpolate_instance_q15_opt *S, + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank); + +void rsi_fim_fir_interpolate_q15(arm_fir_interpolate_instance_q15_opt *S, + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize, + typ_data_t typ_data, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank); + +void rsi_arm_fir_interpolate_q31_opt(const arm_fir_interpolate_instance_q31_opt *S, + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank); + +void RSI_FIM_EnableSaturation(void); +void RSI_FIM_SetSatTruncRound(uint32_t SatTruncRoundShift); + +// New feature +#ifdef ENHANCED_FIM +void rsi_arm_correlate_q15(const q15_t *pSrcA, uint32_t srcALen, const q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst); +void rsi_arm_correlate_q31(const q31_t *pSrcA, uint32_t srcALen, const q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst); +void rsi_arm_correlate_q7(const q7_t *pSrcA, uint32_t srcALen, const q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst); +arm_status arm_fir_decimate_init_q31(arm_fir_decimate_instance_q31 *S, + uint16_t numTaps, + uint8_t M, + q31_t *pCoeffs, + q31_t *pState, + uint32_t blockSize); +arm_status arm_fir_decimate_init_q15(arm_fir_decimate_instance_q15 *S, + uint16_t numTaps, + uint8_t M, + q15_t *pCoeffs, + q15_t *pState, + uint32_t blockSize); +void arm_fir_decimate_q15(const arm_fir_decimate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize); +void arm_fir_decimate_q31(const arm_fir_decimate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize); +void rsi_arm_cfft_radix2(q31_t *pSrc); +void rsi_arm_sin_q15(q15_t *pSrc, q15_t *pDst, uint32_t blocksize); +void rsi_arm_cos_q15(q15_t *pSrc, q15_t *pDst, uint32_t blocksize); +void rsi_arm_Inverse_Tan_q15(q15_t *pSrc, q15_t *pDst, uint32_t blocksize); +void rsi_arm_Sinh_q15(q15_t *pSrc, q15_t *pDst, uint32_t blocksize); +void rsi_arm_cosh_q15(q15_t *pSrc, q15_t *pDst, uint32_t blocksize); +void rsi_arm_Inverse_Tanh_q15(q15_t *pSrc, q15_t *pDst, uint32_t blocksize); +rsi_error_t rsi_arm_mat_add_q15(const arm_matrix_instance_q15_opt *pSrcA, + const arm_matrix_instance_q15_opt *pSrcB, + arm_matrix_instance_q15_opt *pDst); +rsi_error_t arm_mat_add_q31(const arm_matrix_instance_q31_opt *pSrcA, + const arm_matrix_instance_q31_opt *pSrcB, + arm_matrix_instance_q31_opt *pDst); +rsi_error_t arm_mat_sub_q15(const arm_matrix_instance_q15_opt *pSrcA, + const arm_matrix_instance_q15_opt *pSrcB, + arm_matrix_instance_q15_opt *pDst); +rsi_error_t arm_mat_sub_q31(const arm_matrix_instance_q31_opt *pSrcA, + const arm_matrix_instance_q31_opt *pSrcB, + arm_matrix_instance_q31_opt *pDst); +rsi_error_t arm_mat_trans_q15(const arm_matrix_instance_q15_opt *pSrc, arm_matrix_instance_q15_opt *pDst); +rsi_error_t rsi_arm_mat_trans_q31(const arm_matrix_instance_q31_opt *pSrc, arm_matrix_instance_q31_opt *pDst); +rsi_error_t rsi_arm_mat_Hadamard_prod_q15(const arm_matrix_instance_q15_opt *pSrcA, + const arm_matrix_instance_q15_opt *pSrcB, + arm_matrix_instance_q15_opt *pDst); +rsi_error_t arm_mat_Hadamard_prod_q31(const arm_matrix_instance_q31_opt *pSrcA, + const arm_matrix_instance_q31_opt *pSrcB, + arm_matrix_instance_q31_opt *pDst); +void rsi_arm_VSqrt_q15(q15_t *pSrc, q15_t *pDst, uint32_t blockSize); +void rsi_arm_log_q15(q15_t *pSrc, q15_t *pDst, uint16_t blockSize); +void rsi_enable_inst_buff(void); +void RSI_FIM_InputData(void *pSrcA, uint32_t bank, uint32_t blockSize, uint8_t data_type); +void rsi_fim_copy_fim_reg_to_ulp_memory(void); +#endif + +#ifdef __cplusplus +} +#endif +#endif // RSI_FIM_H diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_ir.h b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_ir.h new file mode 100644 index 000000000..e43d27703 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_ir.h @@ -0,0 +1,227 @@ +/******************************************************************************* +* @file rsi_ir.h +* @brief +******************************************************************************* +* # License +* Copyright 2022 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +// Includes Files + +#include "rsi_ccp_common.h" + +#ifndef RSI_IR_H +#define RSI_IR_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define CONFIG_SREST_IR_CORE (1U << 16) // Soft reset IR core block +#define CONFIG_EN_CONT_IR_DET (1U << 8) // Continuous IR detection enable +#define CONFIG_EN_CLK_IR_CORE (1U << 2) // Enable 32KHz clock to IR Core +#define CONFIG_EN_IR_DET_RSTART (1U << 1) // Enable IR detection Re-start Logic +#define CONFIG_EN_IR_DET (1U << 0) // Enable IR detection Logic +#define MAX_MEMORY_ADDRESS 128 +#define MAX_OFF_DURATION 131072 +#define MAX_ON_DURATION 4096 +#define MAX_FRAMEDONE_THRESHOLD 32768 +#define MAX_DETECTION_THRESHOLD 128 +/** @addtogroup SOC23 +* @{ +*/ +/*===================================================*/ +/** + * @fn rsi_error_t RSI_IR_OffDuration(IR_Type* pIr , uint32_t off_duration) + * @brief This API is used to configure the off duration of IR decoder + * @param[in] pIr : IR type pointer + * @param[in] off_duration : IR Sleep duration timer value. Programmable value for OFF duration + for power cycling on External IR Sensor. + Count to be programmed write to clock ticks of 32KHz clock. + Programmed value is (1/32K)*off_duration + * @return return zero \ref RSI_OK on success and return error code on failure. + * + * @b Example + * - RSI_IR_OffDuration(IR , 20); \n + * - In the above parameter we get off time of (1/32K)*20 = 0.625ms + */ +STATIC INLINE rsi_error_t RSI_IR_OffDuration(IR_Type *pIr, uint32_t off_duration) +{ + if (off_duration > MAX_OFF_DURATION) { + return INVALID_PARAMETERS; + } + pIr->IR_OFF_TIME_DURATION_b.IR_OFF_TIME_DURATION = (unsigned int)(off_duration & 0x1FFFF); + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_IR_OnDuration(IR_Type* pIr , uint16_t on_duration) + * @brief This API is used to configure the off duration of IR decoder + * @param[in] pIr : IR type pointer + * @param[in] on_duration : IR Sleep duration timer value. Programmable value for ON duration + * for power cycling on External IR Sensor. + * Count to be programmed write to clock ticks of 32KHz clock. + * Programmed value is (1/32K)*on_duration + * @return return zero \ref RSI_OK on success and return error code on failure. + * + * @b Example + * - RSI_IR_OnDuration(IR , 20); \n + * - In the above parameter we get off time of (1/32K)*20 = 0.625ms + */ +STATIC INLINE rsi_error_t RSI_IR_OnDuration(IR_Type *pIr, uint16_t on_duration) +{ + if (on_duration > MAX_ON_DURATION) { + return INVALID_PARAMETERS; + } + pIr->IR_ON_TIME_DURATION_b.IR_ON_TIME_DURATION = (unsigned int)(on_duration & 0x0FFF); + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn void RSI_IR_SetConfiguration(IR_Type* pIr , uint32_t flags) + * @brief This API is used set the configure the IR modes + * @param[in] pIr : IR type pointer + * @param[in] flags : Ored values of IR configuration flags + * - \ref CONFIG_SREST_IR_CORE + * - \ref CONFIG_EN_CONT_IR_DET + * - \ref CONFIG_EN_CONT_IR_DET + * - \ref CONFIG_EN_CONT_IR_DET + * - \ref CONFIG_EN_CONT_IR_DET + * @return none + * + * @b Example + * - RSI_IR_SetConfiguration(IR , (CONFIG_SREST_IR_CORE | CONFIG_EN_CONT_IR_DET)); + */ +STATIC INLINE void RSI_IR_SetConfiguration(IR_Type *pIr, uint32_t flags) +{ + pIr->IR_CONFIG |= flags; +} + +/*===================================================*/ +/** + * @fn void RSI_IR_ClrConfiguration(IR_Type* pIr , uint32_t flags) + * @brief This API is used clear configure the IR modes + * @param[in] pIr : IR type pointer + * @param[in] flags : Ored values of IR configuration flags + * - \ref CONFIG_SREST_IR_CORE + * - \ref CONFIG_EN_CONT_IR_DET + * - \ref CONFIG_EN_CONT_IR_DET + * - \ref CONFIG_EN_CONT_IR_DET + * - \ref CONFIG_EN_CONT_IR_DET + * @return none + * + * @b Example + * - RSI_IR_SetConfiguration(IR , (CONFIG_SREST_IR_CORE | CONFIG_EN_CONT_IR_DET)); + */ +STATIC INLINE void RSI_IR_ClrConfiguration(IR_Type *pIr, uint32_t flags) +{ + pIr->IR_CONFIG &= ~flags; +} + +/*===================================================*/ +/** + * @fn void RSI_IR_Restart(IR_Type* pIr) + * @brief This API is used clear configure the IR modes + * @param[in] pIr : IR type pointer + * @return none + * + * @b Example + * - RSI_IR_SetConfiguration(IR); + */ +STATIC INLINE void RSI_IR_Restart(IR_Type *pIr) +{ + pIr->IR_CONFIG_b.IR_DET_RSTART = 1U; +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_IR_Framedonethreshold(IR_Type* pIr,uint16_t frame_threshold) + * @brief This API is used count with respect to 32KHz clock after not more toggle are expected to a + * given pattern. + * @param[in] pIr : IR type pointer + * @param[in] frame_threshold : frame done threshold value. + * @return return zero \ref RSI_OK on success and return error code on failure. + * + * @b Example + * - RSI_IR_Framedonethreshold(IR,20); + */ +STATIC INLINE rsi_error_t RSI_IR_Framedonethreshold(IR_Type *pIr, uint16_t frame_threshold) +{ + if (frame_threshold > MAX_FRAMEDONE_THRESHOLD) { + return INVALID_PARAMETERS; + } + pIr->IR_FRAME_DONE_THRESHOLD_b.IR_FRAME_DONE_THRESHOLD = (unsigned int)(frame_threshold & 0x7FFF); + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_IR_Detectionthreshold(IR_Type* pIr,uint16_t detection_threshold) + * @brief This API is used minimum number of edges to detected during on-time failing which + * IR detection is re-stated. + * @param[in] pIr : IR type pointer + * @param[in] detection_threshold : detection threshold value. + * @return return zero \ref RSI_OK on success and return error code on failure. + * + * @b Example + * - RSI_IR_Detectionthreshold(IR,20); + */ +STATIC INLINE rsi_error_t RSI_IR_Detectionthreshold(IR_Type *pIr, uint16_t detection_threshold) +{ + if (detection_threshold > MAX_DETECTION_THRESHOLD) { + return INVALID_PARAMETERS; + } + pIr->IR_DET_THRESHOLD_b.IR_DET_THRESHOLD = (unsigned int)(detection_threshold & 0x7F); + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn void RSI_IR_MemoryReadEnable(IR_Type* pIr) + * @brief This API is used enable the memory read option. + * @param[in] pIr : IR type pointer + * @return return zero \ref RSI_OK on success and return error code on failure. + * + * @b Example + * - RSI_IR_MemoryReadEnable(IR); + */ +STATIC INLINE void RSI_IR_MemoryReadEnable(IR_Type *pIr) +{ + pIr->IR_MEM_ADDR_ACCESS_b.IR_MEM_RD_EN = 1U; +} + +/*===================================================*/ +/** + * @fn uint32_t RSI_IR_GetMemoryDepth(IR_Type* pIr) + * @brief This API returns the IR data samples depth + * @param[in] pIr : IR type pointer + * @return number samples received + * + * @b Example + * - memory_depth = RSI_IR_GetMemoryDepth(IR); + */ +STATIC INLINE uint32_t RSI_IR_GetMemoryDepth(IR_Type *pIr) +{ + return pIr->IR_MEM_READ_b.IR_DATA_MEM_DEPTH; +} + +uint16_t RSI_IR_ReadData(IR_Type *pIr, uint16_t memory_address); +void RSI_IR_SoftwareRestart(IR_Type *pIr); +void IRQ015_Handler(void); +#ifdef __cplusplus +} +#endif + +#endif //RSI_IR_H +/** @} */ diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_sdioh.h b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_sdioh.h new file mode 100644 index 000000000..ed810fbfb --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_sdioh.h @@ -0,0 +1,205 @@ +/******************************************************************************* +* @file rsi_sdioh.h +* @brief +******************************************************************************* +* # License +* Copyright 2022 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +// Include Files + +#include "RS1xxxx.h" +#include "base_types.h" +#include "rsi_smih.h" + +#ifndef RSI_SDIOH_H +#define RSI_SDIOH_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(__CC_ARM) +#pragma push +#pragma anon_unions +#elif defined(__ICCARM__) +#pragma language = extended +#elif defined(__GNUC__) +// anonymous unions are enabled by default +#elif defined(__TMS470__) +// anonymous unions are enabled by default +#elif defined(__TASKING__) +#pragma warning 586 +#else +#warning Not supported compiler type +#endif + +#define MAX_SD_RETRY_TIME (500) +#define BIT4_BUS_WIDTH_ARG (0x80000E82) +#define BIT4_BUS_WIDTH_SET_ARG (0x00000E00) +#define LOW_SPEED_CHECK_ARG (0x00001000) +#define IO_BLOCKSIZE_ARG (0x80022000) +#define IO_BLOCKSIZE_ARG_1 (0x80022201) +#define HIGH_SPEED_SPRT_ARG (0x00002600) +#define SELECT_FUNC_ARG (0x00001A00) +#define RESET_ARG (0x80000C08) +#define CCCR_BYTE_READ (0x04000016) +#define CD_DISABLE_ARG (0x80000E80) +// Function1 argument +#define FUCNTION1_CHECK_ARG (0x00000400) +#define FUCNTION1_ENB_ARG (0x80000402) +#define FUCNTION1_READY_ARG (0x00000600) +#define FUNCTION1_INTR_ENB_ARG (0x80000803) +#define FUNCTION1_INTR_CHECK_ARG (0x00000800) +#define FUNCTION1_READY (1 << 1) +#define FUNCTION1_ENABLE (1 << 1) +#define CSA_SUPPORT_ARG (0x00020000) +#define CSA_ENABLE_ARG (0x80020080) + +// Function2 argument +#define FUCNTION2_CHECK_ARG (0x00000400) +#define FUCNTION2_ENB_ARG (0x80000404) +#define FUCNTION2_READY_ARG (0x00000600) +#define FUNCTION2_INTR_ENB_ARG (0x80000805) +#define FUNCTION2_READY (1 << 2) +#define FUNCTION2_ENABLE (1 << 2) +#define LOW_SPEED_CHECK (1 << 6) +#define BIT4_MODE_CHECK (1 << 7) +#define BUS_BIT (1 << 1) + +#define SD_ACMD_OFFSET (0x40) +#define MMC_CMD_TAG (0x80) +#define ARG_ACMD41_BUSY (0x80000000) +#define OCR_CAPACITY_MASK (0x40000000) + +#define CHECK_HIGH_SPEED_SUPPORT (0x00002600) +#define ENABLE_HIGH_SPEED_MODE_ARG \ + (0x80002602) // SDIO_CMD52 ARG(CCR REG OFFSET IS 0X13 IE:13 LEFT SHIF BY 9,HERE 9 MEANS 8 BITS DATA AND 1 BIT STUFF IN CMD 52(SETTING BIT 1 IN 13TH PFFSET)) + +#define CHECK_UHS_SUPPORT_MODES \ + (0x00002800) // SDIO_CMD52 ARG(CCR REG OFFSET IS 0X14 IE:14 LEFT SHIF BY 9,HERE 9 MEANS 8 BITS DATA AND 1 BIT STUFF IN CMD 52) (CHECK ARGMENT) +#define UHS_1_SDR25_MODE_ARG \ + (0x80002602) // SDIO_CMD52 ARG(CCR REG OFFSET IS 0X13 IE:13 LEFT SHIF BY 9,HERE 9 MEANS 8 BITS DATA AND 1 BIT STUFF IN CMD 52(SETTING BIT 1 IN 13TH PFFSET)) +#define UHS_1_SDR50_MODE_ARG (0x80002604) // BIT 2 SETTING IN 13TH OFFSET +#define UHS_1_SDR104_MODE_ARG (0x80002606) // SETTING BIT 1 AND 2 IN 13TH OFFSET (CCCR REG) +#define UHS_1_DDR50_MODE_ARG (0x80002608) // SETTING BIT 3 IN 13TH OFFSET + +#define HIGH_SPEED_BIT BIT(0) +#define UHS_SUPPORT_BITS 0x7 // bit 0,1,2 + +#define SDIO_SET1 1 + +#if SDIO_SET1 +#define SDIO_CLK_PIN 46 +#define SDIO_CLK_PAD 11 +#define SDIO_CLK_MUX EGPIO_PIN_MUX_MODE8 + +#define SDIO_CMD_PIN 47 +#define SDIO_CMD_PAD 11 +#define SDIO_CMD_MUX EGPIO_PIN_MUX_MODE8 + +#define SDIO_D0_PIN 48 +#define SDIO_D0_PAD 11 +#define SDIO_D0_MUX EGPIO_PIN_MUX_MODE8 + +#define SDIO_D1_PIN 49 +#define SDIO_D1_PAD 12 +#define SDIO_D1_MUX EGPIO_PIN_MUX_MODE8 + +#define SDIO_D2_PIN 50 +#define SDIO_D2_PAD 12 +#define SDIO_D2_MUX EGPIO_PIN_MUX_MODE8 + +#define SDIO_D3_PIN 51 +#define SDIO_D3_PAD 12 +#define SDIO_D3_MUX EGPIO_PIN_MUX_MODE8 + +#define SDIO_CD_PIN 53 +#define SDIO_CD_PAD 13 +#define SDIO_CD_MUX EGPIO_PIN_MUX_MODE8 + +#define SDIO_WP_PIN 52 +#define SDIO_WP_PAD 13 +#define SDIO_WP_MUX EGPIO_PIN_MUX_MODE8 +#else +#define SDIO_CLK_PIN 25 +#define SDIO_CLK_PAD 0 // no pad +#define SDIO_CLK_MUX EGPIO_PIN_MUX_MODE8 + +#define SDIO_CMD_PIN 26 +#define SDIO_CMD_PAD 0 // no pad +#define SDIO_CMD_MUX EGPIO_PIN_MUX_MODE8 + +#define SDIO_D0_PIN 27 +#define SDIO_D0_PAD 0 // no pad +#define SDIO_D0_MUX EGPIO_PIN_MUX_MODE8 + +#define SDIO_D1_PIN 28 +#define SDIO_D1_PAD 0 // no pad +#define SDIO_D1_MUX EGPIO_PIN_MUX_MODE8 + +#define SDIO_D2_PIN 29 +#define SDIO_D2_PAD 0 // no pad +#define SDIO_D2_MUX EGPIO_PIN_MUX_MODE8 + +#define SDIO_D3_PIN 30 +#define SDIO_D3_PAD 0 // no pad +#define SDIO_D3_MUX EGPIO_PIN_MUX_MODE8 + +#define SDIO_CD_PIN 53 +#define SDIO_CD_PAD 13 +#define SDIO_CD_MUX EGPIO_PIN_MUX_MODE8 + +#define SDIO_WP_PIN 52 +#define SDIO_WP_PAD 13 +#define SDIO_WP_MUX EGPIO_PIN_MUX_MODE8 +#endif + +// COMMMANDS VALUE +#define CMD_53 53 +#define CMD_52 52 +#define CMD_5 5 + +#if defined(__CC_ARM) +#pragma pop +#elif defined(__ICCARM__) +// leave anonymous unions enabled +#elif defined(__GNUC__) +// anonymous unions are enabled by default +#elif defined(__TMS470__) +// anonymous unions are enabled by default +#elif defined(__TASKING__) +#pragma warning restore +#else +#warning Not supported compiler type +#endif +void RSI_SDIOH_PinMux(void); +rsi_error_t RSI_SDIOH_Enumeration(SMIH_CARD_CONFIG_T *pSmihConfig, ARM_SMIH_SignalEvent_t Event); +rsi_error_t RSI_SDIOH_RegisterInfo(SMIH_CARD_CONFIG_T *pSmihConfig, SMIH_CCCR_REG_INFO_T *pRegInfo); +rsi_error_t RSI_SDIOH_WriteCommandCmd52(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t Argument); +rsi_error_t RSI_SDIOH_ReadCommandCmd52(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t Argument); +rsi_error_t RSI_SDIOH_SetBusWidthCmd52(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t CmdArg); +rsi_error_t RSI_SDIOH_BusWidthConfig(SMIH_CARD_CONFIG_T *pSmihConfig, uint8_t BusWidth); +rsi_error_t RSI_SDIOH_GoIdleStateCmd0(SMIH_CARD_CONFIG_T *pSmihConfig); +rsi_error_t RSI_SDIOH_SendRelativeCardAddressCmd3(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t CmdArg); +rsi_error_t RSI_SDIOH_SwitchVoltageCmd11(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t CmdArg); +rsi_error_t RSI_SDIOH_SelectCardCmd7(SMIH_CARD_CONFIG_T *pSmihConfig); +rsi_error_t RSI_SDIOH_ByteBlockWriteCmd53(SMIH_CARD_CONFIG_T *pSmihConfig, uint8_t *pData, uint32_t Addr); +rsi_error_t RSI_SDIOH_ByteBlockReadCmd53(SMIH_CARD_CONFIG_T *pSmihConfig, uint8_t *pData, uint32_t Addr); +rsi_error_t RSI_SDIOH_ReInitializationCmd5(SMIH_CARD_CONFIG_T *pSmihConfig); +rsi_error_t RSI_SDIOH_InitializationCmd5(SMIH_CARD_CONFIG_T *pSmihConfig); + +#ifdef __cplusplus +} +#endif + +#endif // RSI_SDIOH_H diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_sdmem.h b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_sdmem.h new file mode 100644 index 000000000..985705257 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_sdmem.h @@ -0,0 +1,219 @@ +/******************************************************************************* +* @file rsi_sdmem.h +* @brief +******************************************************************************* +* # License +* Copyright 2022 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +// Include Files + +#include "RS1xxxx.h" +#include "base_types.h" +#include "rsi_smih.h" + +#ifndef RSI_SDMEM_H +#define RSI_SDMEM_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define MMC_CARDS 0 // Enable this if MMC card is using +#define _8BIT_MODE 0 +#define _1BIT_MODE 0 +#define GPIO_SET1 1 +#define CD_WPP_SET1 0 + +#define HIGH_SPEED_EN 0 +#define ADMA_ENABLE 0 +#define SD_CLOCK 25000000 +#define __1P8_VOLTAGE_EN 0 + +#if GPIO_SET1 +#define SD_CLK_PIN 46 +#define SD_CLK_PAD 11 +#define SD_CLK_MUX EGPIO_PIN_MUX_MODE8 + +#define SD_CMD_PIN 47 +#define SD_CMD_PAD 11 +#define SD_CMD_MUX EGPIO_PIN_MUX_MODE8 + +#define SD_D0_PIN 48 +#define SD_D0_PAD 11 +#define SD_D0_MUX EGPIO_PIN_MUX_MODE8 + +#define SD_D1_PIN 49 +#define SD_D1_PAD 12 +#define SD_D1_MUX EGPIO_PIN_MUX_MODE8 + +#define SD_D2_PIN 50 +#define SD_D2_PAD 12 +#define SD_D2_MUX EGPIO_PIN_MUX_MODE8 + +#define SD_D3_PIN 51 +#define SD_D3_PAD 12 +#define SD_D3_MUX EGPIO_PIN_MUX_MODE8 + +#if CD_WPP_SET1 +#define SD_CD_PIN 6 +#define SD_CD_PAD 1 +#define SD_CD_MUX EGPIO_PIN_MUX_MODE8 + +#define SD_WP_PIN 7 +#define SD_WP_PAD 1 +#define SD_WP_MUX EGPIO_PIN_MUX_MODE8 +#else +#define SD_CD_PIN 53 +#define SD_CD_PAD 13 +#define SD_CD_MUX EGPIO_PIN_MUX_MODE8 + +#define SD_WP_PIN 52 +#define SD_WP_PAD 13 +#define SD_WP_MUX EGPIO_PIN_MUX_MODE8 +#endif + +#else +#define SD_CLK_PIN 25 +#define SD_CLK_PAD 0 // no pad +#define SD_CLK_MUX EGPIO_PIN_MUX_MODE8 + +#define SD_CMD_PIN 26 +#define SD_CMD_PAD 0 // no pad +#define SD_CMD_MUX EGPIO_PIN_MUX_MODE8 + +#define SD_D0_PIN 27 +#define SD_D0_PAD 0 // no pad +#define SD_D0_MUX EGPIO_PIN_MUX_MODE8 + +#define SD_D1_PIN 28 +#define SD_D1_PAD 0 // no pad +#define SD_D1_MUX EGPIO_PIN_MUX_MODE8 + +#define SD_D2_PIN 29 +#define SD_D2_PAD 0 // no pad +#define SD_D2_MUX EGPIO_PIN_MUX_MODE8 + +#define SD_D3_PIN 30 +#define SD_D3_PAD 0 // no pad +#define SD_D3_MUX EGPIO_PIN_MUX_MODE8 +#if CD_WPP_SET1 +#define SD_CD_PIN 6 +#define SD_CD_PAD 1 +#define SD_CD_MUX EGPIO_PIN_MUX_MODE8 + +#define SD_WP_PIN 7 +#define SD_WP_PAD 1 +#define SD_WP_MUX EGPIO_PIN_MUX_MODE8 +#else +#define SD_CD_PIN 53 +#define SD_CD_PAD 13 +#define SD_CD_MUX EGPIO_PIN_MUX_MODE8 + +#define SD_WP_PIN 52 +#define SD_WP_PAD 13 +#define SD_WP_MUX EGPIO_PIN_MUX_MODE8 +#endif + +#endif + +#if _8BIT_MODE +#if (PACKAGE_TYPE == CC0) || (PACKAGE_TYPE == SB0N_B00) || (PACKAGE_TYPE == SB00_B00) +#define SD_D4_PIN 54 +#define SD_D4_PAD 13 +#define SD_D4_MUX EGPIO_PIN_MUX_MODE8 + +#define SD_D5_PIN 55 +#define SD_D5_PAD 13 +#define SD_D5_MUX EGPIO_PIN_MUX_MODE8 + +#define SD_D6_PIN 56 +#define SD_D6_PAD 14 +#define SD_D6_MUX EGPIO_PIN_MUX_MODE8 + +#define SD_D7_PIN 57 +#define SD_D7_PAD 14 +#define SD_D7_MUX EGPIO_PIN_MUX_MODE8 +#else +#error "8BIT mode not supported in this package" +#endif +#endif + +#define ACMD41_VOLTAGE (0x00FF8000) +#define ACMD41_UHS_REQ (0x41FF8000) +#define ACMD41_HCS (1 << 30) + +#define SD_ACMD_OFFSET (0x40) +#define MMC_CMD_TAG (0x80) +#define ACMD41_BUSY_BIT BIT(31) +#define ACMD41_OCR_BIT BIT(30) + +// COMMMANDS VALUE +#define CMD_8 8 +#define CMD_55 55 +#define CMD_11 11 +#define CMD_1 1 +#define CMD_2 2 +#define CMD_3 3 +#define CMD_9 9 +#define CMD_7 7 +#define CMD_6 6 +#define CMD_24 24 +#define CMD_25 25 +#define CMD_18 18 +#define CMD_17 17 +#define CMD_80_hex 0x80 +#define CMD_40_hex 0x40 +#define CMD_8 8 +#define CMD_41 41 + +// POSITION VALUE +#define BLOCK_SIZE_512 512 + +// SDMEM related function prototypes +void RSI_SDMEM_PinMux(void); +rsi_error_t RSI_SDMEM_GoIdleStateCmd0(SMIH_CARD_CONFIG_T *pSmihConfig); +rsi_error_t RSI_SDMEM_SendCardInterfaceConditionCmd8(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t Arg); +rsi_error_t RSI_SDMEM_SendApplicationCommandCmd55(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t Arg); +rsi_error_t RSI_SDMEM_SetCardOperationConditionAcmd41(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t Arg); +rsi_error_t RSI_SDMEM_SwitchVoltageCmd11(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t CmdArg); +rsi_error_t RSI_SDMEM_SendCidCmd2(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t Arg); +rsi_error_t RSI_SDIOH_SendRelativeAddressCmd3(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t CmdArg); +rsi_error_t RSI_SDMEM_SendCsdCmd9(SMIH_CARD_CONFIG_T *pSmihConfig); +rsi_error_t RSI_SDMEM_SelectCardCmd7(SMIH_CARD_CONFIG_T *pSmihConfig); +rsi_error_t RSI_SDMEM_SetBusWidthAcmd6(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t Arg); +rsi_error_t RSI_SDMEM_OperationSwitchFunctionReadCmd6(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t Argument); +rsi_error_t RSI_SDMEM_GetCardOperationConditionAcmd41(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t Arg); +rsi_error_t RSI_SDMEM_CardBusWidthConfig(SMIH_CARD_CONFIG_T *pSmihConfig, uint8_t BusWidth); +rsi_error_t RSI_SDMEM_OperationSwitchFunctionWriteCmd6(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t Argument); +rsi_error_t RSI_SDMEM_BlocksWrite(SMIH_CARD_CONFIG_T *pSmihConfig, + const uint8_t *DataIn, + uint32_t BlockIndex, + uint32_t BlockCount); +rsi_error_t RSI_SDMEM_BlocksRead(SMIH_CARD_CONFIG_T *pSmihConfig, + uint8_t *DataOut, + uint32_t BlockIndex, + uint32_t BlockCount); +rsi_error_t RSI_SDMEM_EnableHighSpeed(SMIH_CARD_CONFIG_T *pSmihConfig, boolean_t HighSpeed, uint32_t Clock); +rsi_error_t RSI_SDMEM_Enumeration(SMIH_CARD_CONFIG_T *pSmihConfig, ARM_SMIH_SignalEvent_t Event); +rsi_error_t RSI_SDMMC_Enumeration(SMIH_CARD_CONFIG_T *pSmihConfig, ARM_SMIH_SignalEvent_t Event); +rsi_error_t RSI_SDMMC_SendOperationConditionCmd1(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t Arg); +rsi_error_t RSI_SDMMC_SendExtentCsdCmd(SMIH_CARD_CONFIG_T *pSmihConfig); +rsi_error_t RSI_SDMMC_ChangeBusWidthMode(SMIH_CARD_CONFIG_T *pSmihConfig, uint8_t bus_wdith); +rsi_error_t RSI_SDMMC_SwitchFunctionCmd6(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t Arg); +rsi_error_t RSI_SDMMC_HighSpeedMode(SMIH_CARD_CONFIG_T *pSmihConfig, boolean_t HighSpeed, uint32_t Clock); + +#ifdef __cplusplus +} +#endif + +#endif // RSI_SDMEM_H diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_smih.h b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_smih.h new file mode 100644 index 000000000..6309cf662 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_smih.h @@ -0,0 +1,486 @@ +/******************************************************************************* +* @file rsi_smih.h +* @brief +******************************************************************************* +* # License +* Copyright 2022 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +// Include Files + +#include "RS1xxxx.h" +#include "base_types.h" + +#ifndef RSI_SMIH_H +#define RSI_SMIH_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(__CC_ARM) +#pragma push +#pragma anon_unions +#elif defined(__ICCARM__) +#pragma language = extended +#elif defined(__GNUC__) +// anonymous unions are enabled by default +#elif defined(__TMS470__) +// anonymous unions are enabled by default +#elif defined(__TASKING__) +#pragma warning 586 +#else +#warning Not supported compiler type +#endif + +#define ACMD41_VOLTAGE (0x00FF8000) +#define ACMD41_UHS_REQ (0x41FF8000) +#define ACMD41_HCS (1 << 30) + +// SMIH Controller related defines and structures +typedef void (*ARM_SMIH_SignalEvent_t)(uint32_t event); // Pointer to \ref ARM_USART_SignalEvent : Signal USART Event. + +#define LOOP_COUNT_TIME (500) + +// Normal interrupt status enable reg +#define COMMAND_COMPLETE_STATUS_ENABLE BIT(0) +#define TRANSFER_COMPLETE_STATUS_ENABLE BIT(1) +#define BLOCK_GAP_EVENT_STATUS_ENABLE BIT(2) +#define DMA_INTERRUPT_STATUS_ENABLE BIT(3) +#define BUFFER_WRITE_READY_STATUS_ENABLE BIT(4) +#define BUFFER_READ_READY_STATUS_ENABLE BIT(5) +#define CARD_INSERTION_STATUS_ENABLE BIT(6) +#define CARD_REMOVAL_STATUS_ENABLE BIT(7) +#define CARD_INTERRUPT_STATUS_ENABLE BIT(8) +#define INT_A_STATUS_ENABLE BIT(9) +#define INT_B_STATUS_ENABLE BIT(10) +#define INT_C_STATUS_ENABLE BIT(11) +#define RE_TUNING_EVENT_STATUS_ENABLE BIT(12) + +// Error interrupt status enables +#define COMMAND_TIMEOUT_ERROR_STATUS_ENABLE BIT(0) +#define COMMAND_CRC_ERROR_STATUS_ENABLE BIT(1) +#define COMMAND_END_BIT_ERROR_STATUS_ENABLE BIT(2) +#define COMMAND_INDEX_ERROR_STATUS_ENABLE BIT(3) +#define DATA_TIMEOUT_ERROR_STATUS_ENABLE BIT(4) +#define DATA_CRC_ERROR_STATUS_ENABLE BIT(5) +#define DATA_END_BIT_ERROR_STATUS_ENABLE BIT(6) +#define CURRENT_LIMIT_ERROR_STATUS_ENABLE BIT(7) +#define AUTO_CMD_ERROR_STATUS_ENABLE BIT(8) +#define ADMA_ERROR_STATUS_ENABLE BIT(9) +#define TUNING_ERROR_STATUS_ENABLE BIT(10) + +// Normal interrupt status enable reg +#define COMMAND_COMPLETE_SIGNAL_ENABLE BIT(0) +#define TRANSFER_COMPLETE_SIGNAL_ENABLE BIT(1) +#define BLOCK_GAP_EVENT_SIGNAL_ENABLE BIT(2) +#define DMA_INTERRUPT_SIGNAL_ENABLE BIT(3) +#define BUFFER_WRITE_READY_SIGNAL_ENABLE BIT(4) +#define BUFFER_READ_READY_SIGNAL_ENABLE BIT(5) +#define CARD_INSERTION_SIGNAL_ENABLE BIT(6) +#define CARD_REMOVAL_SIGNAL_ENABLE BIT(7) +#define CARD_INTERRUPT_SIGNAL_ENABLE BIT(8) +#define INT_A_SIGNAL_ENABLE BIT(9) +#define INT_B_SIGNAL_ENABLE BIT(10) +#define INT_C_SIGNALS_ENABLE BIT(11) +#define RE_TUNING_EVENT_SIGNAL_ENABLE BIT(12) + +#define DISABLE_AUTO_CMD 0 +#define ENABLE_AUTO_CMD12 1 +#define ENABLE_AUTO_CMD23 2 + +// Command type defines +#define ABORT_CMD 0 +#define RESUME_CMD 1 +#define SUSPEND_CMD 2 +#define NORMAL_CMD 3 + +// response type defines +#define SMIH_NO_RESPONSE 0 +#define SMIH_RESPONSE_LENGTH_136 1 +#define SMIH_RESPONSE_LENGTH_48 2 +#define SMIH_RESPONSE_LENGTH_48BIT_BUSY_CHECK 3 + +// ultra high speed mode defines +#define UHS_NONE 0x0 +#define UHS_SDR12 0x1 +#define UHS_SDR25 0x2 +#define UHS_SDR50 0x3 +#define UHS_SDR104 0x4 +#define UHS_DDR50 0x5 + +// response types to the commands +#define SMIH_RESPONSE_NONE 0x0 +#define SMIH_RESPONSE_R2 0x1 +#define SMIH_RESPONSE_R3R4 0x2 +#define SMIH_RESPONSE_R1R5R6R7 0x3 +#define SMIH_RESPONSE_R1BR5B 0x5 + +// smih volatge level defines +#define VOLTAGE_18V 0x0 +#define VOLTAGE_30V 0x1 +#define VOLTAGE_33V 0x2 + +// reset defines +#define SMIH_DATA_LINE_RESET 0x0 +#define SMIH_COMMAND_LINE_RESET 0x1 +#define SMIH_ALL_RESET 0x2 + +#define SMIH_CARD_STANDARD 0x0 +#define SMIH_CARD_HIGH_CAPACITY 0x1 + +// data direction defines +#define SMIH_WRITE_DIRECTION 0x0 +#define SMIH_READ_DIRECTION 0x1 + +// command events defines +#define SMIH_CMD_COMPLETE_EVENT 0x1 +#define SMIH_TRANSFER_COMPLETE_EVENT 0x2 +#define SMIH_BUFFER_READ_READY_EVENT 0x3 +#define SMIH_BUFFER_WRITE_READY_EVENT 0x4 + +// bus width mode defines +#define SMIH_BUS_WIDTH1 0x0 +#define SMIH_BUS_WIDTH4 0x1 +#define SMIH_BUS_WIDTH8 0x2 +typedef struct SMIH_COMMAND_REG { + uint16_t respType : 2; + uint16_t resrvd : 1; + uint16_t cmdCrcCheckEnable : 1; + uint16_t cmdIndexCheckEnable : 1; + uint16_t dataPresentSelect : 1; + uint16_t cmdType : 2; + uint16_t cmdIndex : 6; +} SMIH_COMMAND_REG_T; + +typedef struct SMIH_COMMAND_FRAME_CONFIG { + uint8_t cmdIndex; + uint32_t cmdArgument; + uint8_t cmdType; + boolean_t dataPresentSelect; + boolean_t cmdIndexCheckEn; + boolean_t cmdCrcCheckEn; + uint8_t responseTypeSelect; + uint8_t autoCmdType; +} SMIH_COMMAND_FRAME_CONFIG_T; + +typedef struct SMIH_EVENT { + uint8_t commandComplete; + uint8_t transferComplete; + uint8_t dmaInterrupt; + uint8_t bufferWriteReady; + uint8_t bufferReadReady; + uint8_t cardInsertion; + uint8_t cardRemoval; + uint8_t cardInterrupt; + uint8_t commandTimeoutError; + uint8_t commandCrcError; + uint8_t commandEndBitError; + uint8_t commandIndexError; + uint8_t dataTimeoutError; + uint8_t dataEndbitError; + uint8_t dataCrcError; + uint8_t currentLimitError; + uint8_t autoCommandError; + uint8_t admaError; + uint8_t tuningError; + ARM_SMIH_SignalEvent_t callb_event; +} SMIH_EVENT_T; + +#define COMMAND_COMPLETE 0 +#define TRANSFER_COMPLETE 1 +#define DMA_INTR 2 +#define BUFFER_WRITE_READY 3 +#define BUFFER_READ_READY 4 +#define CARD_INSERTION 5 +#define CARD_REMOVAL 6 +#define CARD_INTERRUPT 7 +#define CMD_TIMEOUT_ERROR 8 +#define CMD_CRC_ERROR 9 +#define CMD_END_BIT_ERROR 10 +#define CMD_INDEX_ERROR 11 +#define DATA_TIMEOUT_ERROR 12 +#define DATA_END_BIT_ERROR 13 +#define DATA_CRC_ERROR 14 +#define CURRENT_LIMIT_ERROR 15 +#define AUTO_CMD_ERROR 16 +#define ADMA_ERROR 17 +#define TUNING_ERROR 18 + +typedef struct SMIH_CMD_FEILD { + uint32_t cmdIdx; + uint32_t cmdArg; + uint8_t responseTypeSelect; + uint32_t response[4]; + SMIH_EVENT_T event; +} SMIH_CMD_FEILD_T; + +typedef struct SMIH_DATA_FEILD { + const uint8_t *data; + uint32_t blockSize; + uint32_t blockCount; + uint8_t direction; +} SMIH_DATA_FEILD_T; + +typedef struct SMIH_TRANSFER { + SMIH_CMD_FEILD_T *command; + SMIH_DATA_FEILD_T *data; + +} SMIH_TRANSFER_T; + +typedef struct SMIH_DATA_CONFIG { + boolean_t multiBlock; + boolean_t dataTransferDirection; + uint16_t blockSize; + uint16_t blockCount; + boolean_t blockCountEnable; + boolean_t dmaEnable; + uint32_t admaDespTableAddress; + uint8_t dataTimeout; +} SMIH_DATA_CONFIG_T; + +typedef struct SMIH_CONFIG_MODES { + uint8_t busWidthMode; + uint32_t clock; + boolean_t highSpeedEnable; + boolean_t admaMode; +} SMIH_CONFIG_MODES_T; + +typedef struct SMIH_ADMA_DESC_TABLE { + uint16_t attributeValid : 1; + uint16_t attributeEnd : 1; + uint16_t attributeInt : 1; + uint16_t reserved1 : 1; + uint16_t attributeAct : 2; + uint16_t reserved2 : 10; + uint16_t length; + uint32_t _32BIT_Adress; +} SMIH_ADMA_DESC_TABLE_T; + +typedef struct SMIH_CMD_OCR { + uint32_t reserved1 : 8; + uint32_t v20_21 : 1; + uint32_t v21_22 : 1; + uint32_t v22_23 : 1; + uint32_t v23_24 : 1; + uint32_t v24_25 : 1; + uint32_t v25_26 : 1; + uint32_t v26_27 : 1; + uint32_t v27_28 : 1; + uint32_t v28_29 : 1; + uint32_t v29_30 : 1; + uint32_t v30_31 : 1; + uint32_t v31_32 : 1; + uint32_t v32_33 : 1; + uint32_t v33_34 : 1; + uint32_t v34_35 : 1; + uint32_t v35_36 : 1; + uint32_t s18A : 1; + uint32_t reserved2 : 2; + uint32_t memPresent : 1; + uint32_t ioNum : 3; + uint32_t cardReady : 1; +} SMIH_CMD_OCR_T; +// command transfer function. +typedef rsi_error_t (*cmd_transfer_function_t)(SMIH_TRANSFER_T *Transfer); + +typedef struct SMIH_CARD_CONFIG { + uint8_t busWidthMode; + uint32_t clock; + boolean_t highSpeedEnable; + uint8_t uhsModeSelect; + uint32_t voltage; + boolean_t admaMode; + uint16_t byteBlockSize; + uint16_t numberOfBlocks; + uint8_t funcNum : 3; + uint8_t blockModeEnable : 1; + uint8_t opCode : 1; + SMIH_CMD_OCR_T ocr; + uint8_t cardType; + uint32_t maxSectorNum; + uint8_t cid[16]; + uint8_t csd[16]; + uint16_t rca; + uint8_t response[4]; + cmd_transfer_function_t cmd_transfer; + +} SMIH_CARD_CONFIG_T; + +typedef struct SMIH_CCCR_REG_INFO { + __IO uint8_t ccidSdioRevReg; + __IO uint8_t sdSpecRevReg; + __IO uint8_t ioEnableReg; + __IO uint8_t ioReady; + __IO uint8_t intEnable; + __IO uint8_t intrPending; + __IO uint8_t ioAbort; + __IO uint8_t busControl; + __IO uint8_t cardCapacity; + __IO uint8_t commonCisPointer; + __IO uint8_t commonCisPointer1; + __IO uint8_t commonCisPointer2; + __IO uint8_t busSped; + __IO uint8_t funcSelect; + __IO uint8_t execFlags; + __IO uint8_t redayFlags; + __IO uint16_t funcoBlockSize; + __IO uint8_t powerControl; + __IO uint8_t busSpeddSelect; + __IO uint8_t uhs1Support; + __IO uint8_t driverStrength; + __IO uint8_t intrExtension; +} SMIH_CCCR_REG_INFO_T; + +typedef struct SD_CARD_STATUS_REG { + uint32_t reserved1 : 3; + uint32_t sequenceEerror : 1; + uint32_t reserved2 : 1; + uint32_t applicationCmd : 1; + uint32_t reserved3 : 2; + uint32_t readyForData : 1; + uint32_t currentStatus : 4; + uint32_t eraseReset : 1; + uint32_t cardEccDisable : 1; + uint32_t wpEraseSkip : 1; + uint32_t csdOverwrite : 1; + uint32_t reserved4 : 2; + uint32_t error : 1; + uint32_t ccError : 1; + uint32_t cardEccFail : 1; + uint32_t illegalCmd : 1; + uint32_t commandCrcError : 1; + uint32_t lockUnlockFail : 1; + uint32_t cradIsLOcked : 1; + uint32_t wpViolation : 1; + uint32_t erasePram : 1; + uint32_t eraseSeqError : 1; + uint32_t blockLenghtError : 1; + uint32_t addressError : 1; + uint32_t outOfRange : 1; +} SD_CARD_STATUS_REG_T; + +typedef struct CSD_REG_VERSION1 { + uint8_t reserved1 : 2; + uint8_t fileFormat : 2; + uint8_t temporaryWriteProtect : 1; + uint8_t permanantWriteProtect : 1; + uint8_t copy : 1; + uint8_t fileFormatGroup : 1; + uint8_t reserved2 : 5; + uint8_t writeBlockLengthPartial : 1; + uint8_t writeBlockLength : 4; + uint8_t R2WFactor : 3; + uint8_t reserved3 : 2; + uint8_t wpGrpEnable : 1; + uint8_t wpGrpSize : 7; + uint8_t sectorSize : 7; + uint8_t eraseBlockEn : 1; + uint8_t deviceSizeMultiplier1 : 1; + uint8_t deviceSizeMultiplier2 : 2; + uint8_t vddWCrrMax : 3; + uint8_t vddWcurrMin : 3; + uint8_t vddRcurrMax : 3; + uint8_t vddRcurrmin : 3; + uint8_t deviceSize1 : 2; + uint8_t deviceSize2 : 8; + uint8_t deviceSize3 : 2; + uint8_t reserved4 : 2; + uint8_t dsrIMP : 1; + uint8_t readBlockMisallign : 1; + uint8_t writeBlockMisallign : 1; + uint8_t readBlockPartial : 1; + uint8_t readBlockLength : 4; + uint8_t ccc1 : 4; + uint8_t ccc2 : 8; + uint8_t transferSpeed : 8; + uint8_t nsac : 8; + uint8_t taac : 8; + uint8_t RESERVE5 : 6; + uint8_t csdStructure : 2; +} CSD_REG_VERSION1_T; + +typedef struct CSD_REG_VERSION2 { + uint8_t RESERVED1 : 2; + uint8_t fileFormat : 2; + uint8_t temporaryWriteProtect : 1; + uint8_t permanantWriteProtect : 1; + uint8_t copy : 1; + uint8_t fileFormatGroup : 1; + uint8_t reserved2 : 5; + uint8_t writeBlockLengthPartial : 1; + uint8_t writeBlockLength : 4; + uint8_t R2WFactor : 3; + uint8_t reserved3 : 2; + uint8_t wpGrpEnable : 1; + uint8_t wpGrpSize : 7; + uint8_t sectorSize : 7; + uint8_t eraseBlockEnable : 1; + uint8_t reserved4 : 1; + uint8_t deviceSize1 : 8; + uint8_t deviceSize2 : 8; + uint8_t deviceSize3 : 6; + uint8_t reserved5 : 2; + uint8_t reserved6 : 4; + uint8_t dsrIMP : 1; + uint8_t readBlockMisallign : 1; + uint8_t writeBlockMisallign : 1; + uint8_t readBlockPartial : 1; + uint8_t readBlockLength : 4; + uint8_t ccc1 : 4; + uint8_t ccc2 : 8; + uint8_t transferSpeed : 8; + uint8_t nsac : 8; + uint8_t taac : 8; + uint8_t reserved7 : 6; + uint8_t csdStructure : 2; +} CSD_REG_VERSION2_T; + +#if defined(__CC_ARM) +#pragma pop +#elif defined(__ICCARM__) +// leave anonymous unions enabled +#elif defined(__GNUC__) +// anonymous unions are enabled by default +#elif defined(__TMS470__) +// anonymous unions are enabled by default +#elif defined(__TASKING__) +#pragma warning restore +#else +#warning Not supported compiler type +#endif + +rsi_error_t RSI_SD_HostInit(SMIH_CARD_CONFIG_T *pSmihConfig, ARM_SMIH_SignalEvent_t Event, uint8_t MemType); +rsi_error_t Smih_DeInitialization(void); +rsi_error_t smih_bus_width_set(uint8_t BusWidthMode); +rsi_error_t smih_bus_voltage_select(uint8_t enVoltage); +rsi_error_t smih_send_command(SMIH_COMMAND_FRAME_CONFIG_T *pConfig); +rsi_error_t smih_get_response(uint16_t *pResponseData, uint8_t ResponseRegCount); +rsi_error_t smih_stop_at_block_gap(void); +rsi_error_t smih_transfer_restart(void); +void smih_18v_signal_enable(void); +rsi_error_t smih_uhs_mode_select(uint8_t UhsMode); +void smih_irq_handler(void); +rsi_error_t smih_modes_configuration(SMIH_CONFIG_MODES_T *pSmihConfig); +rsi_error_t smih_clock_config(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t freq); +rsi_error_t smih_check_for_error_interrupt(void); +rsi_error_t smih_send_data(SMIH_TRANSFER_T *pTransfer); +rsi_error_t smih_receive_data(SMIH_TRANSFER_T *pTransfer); +rsi_error_t smih_memory_command_transfer(SMIH_TRANSFER_T *pTransfer); +rsi_error_t smih_io_command_transfer(SMIH_TRANSFER_T *pTransfer); +void RegisterCallBack(ARM_SMIH_SignalEvent_t Event); + +#ifdef __cplusplus +} +#endif + +#endif // RSI_SMIH_H diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_vad.h b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_vad.h new file mode 100644 index 000000000..87fcd3bbc --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_vad.h @@ -0,0 +1,164 @@ +/******************************************************************************* +* @file rsi_vad.h +* @brief +******************************************************************************* +* # License +* Copyright 2022 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +//Include Files + +#include "rsi_ccp_common.h" +#include "rsi_error.h" + +#ifndef RSI_VAD_H +#define RSI_VAD_H + +#ifdef __cplusplus +extern "C" { +#endif + +// VAD algorithm select enum +typedef enum VAD_ALGORITHM_SELECT { + ZCR, // select the ZCR algorithm for VAD detection + ACF, // select the ACF algorithm for VAD detection + AMDF, // select the AMDF algorithm for VAD detection + WACF, // select the WACF algorithm for VAD detection + ZCR_ACF_AMDF_WACF, // select the ZCR,ACF,AMDF and WACF algorithm for VAD detection + ZCR_ACF, // select the ZCR and ACF algorithm for VAD detection + ZCR_AMDF, // select the ZCR and ACF algorithm for VAD detection + ZCR_WACF // select the ZCR and WACF algorithm for VAD detection +} VAD_ALGORITHM_SELECT_T; + +// AMDF threshold configuration structure (Future usage) +typedef struct { + uint32_t null_threshold : 12; + uint32_t null_threshold_count : 10; + uint32_t peak_threshold : 10; + uint32_t peak_threshold_count : 10; +} VAD_AMDF_THRESHOLD_T; + +typedef VAD_Type RSI_VAD_T; + +#define VAD_PING_IRQHandler IRQ000_Handler // VAD ping interrupt +#define VAD_1SMPLS_PER_ADDR 0x2 +#define VAD_2SMPLS_PER_ADDR 0x1 +#define VAD_4SMPLS_PER_ADDR 0x0 +#define VAD_INTREG_SOURCE 0x0 // Feed voice data to VAD through VAD input register +#define VAD_AUXADC_SOURCE 0x3 // Directly feed ADC data to VAD (This feature not available) +#define VAD_METHOD_ZCR 0x0 +#define VAD_METHOD_ACF 0x1 +#define VAD_METHOD_AMDF 0x2 +#define VAD_METHOD_WACF 0x3 +#define VAD_METHOD_ZCR_ACF_AMDF_WACF 0x4 +#define VAD_METHOD_ZCR_ACF 0x5 +#define VAD_METHOD_ZCR_AMDF 0x6 +#define VAD_METHOD_ZCR_WACF 0x7 + +// Algorithm level threshold +#define VAD_ACF_START 0x05 +#define VAD_ACF_END 0x50 +#define VAD_ACF_THRSHOLD 1000 +#define VAD_ZCR_THRSHOLD 0x190 + +// Energy detection threshold +#define VAD_ENERGY_THRSHOLD 0x32 + +#define MAXIMUM_VALUE_1024 1024 +#define MAXIMUM_VALUE_4096 4096 +#define MAXIMUM_VALUE_4 4 +#define MAXIMUM_VALUE_8 8 + +#define VAD_DIGITAL_GAIN_FAC \ + 4 /*Digital multiplication value,if this value is 5 then each ADC sample will multiply by 32. + data = data << VAD_DIGITAL_GAIN_FAC */ +#define ULP_MEMORY_BASE 0x24060000 +#define TEST_SAMPL_VAL 32 +#define VAD_MASK_VALUE 0xFC00 + +#define DATA_FROM_INTER_ADC \ + 1 /* For feeding voice data to VAD from Si917 ADC then make this macro as 1, + This macro will enable the conversion of 12 bit ADC data to 16 bit data, + VAD is required 16 bit 2s complement data so if input to VAD not using + Si917 ADC output then make this macro as 0 and give proper input data to VAD */ +#define VAD_INTR 0 // VAD interrupt event +#define VAD_ENERGY_DETECT 1 // energy detection event +#define NUMBER_OF_SAMPLE_IN_FRAME 1023 // Maximum number of samples can process in VAD block +#define VAD_SCRT_PAD 0x1800 // Configure the BANK3 for VAD data processing + +typedef void (*VAD_SignalEvent_t)(uint32_t event); // Pointer to VAD Event. + +typedef struct VAD_EVENT { + uint8_t vad_intr; + uint8_t energy_detect; + uint8_t clk_config; + VAD_SignalEvent_t callb_event; +} VAD_EVENT_T; + +// User APIs +rsi_error_t VAD_Init(VAD_SignalEvent_t Event); + +int32_t VAD_Process(int16_t *wr_buf, int32_t dc_est); + +rsi_error_t VAD_Deinit(void); + +// Internal APIs +void RSI_VAD_PingPongMemoryAddrConfig(RSI_VAD_T *pVAD, + uint32_t ping_addr, + uint32_t pong_addr, + uint8_t ping_enable, + uint8_t pong_enable); + +rsi_error_t RSI_VAD_Config(RSI_VAD_T *ptrvad, + uint16_t samples_per_frame, + uint16_t samples_per_address, + bool fullwidth, + uint8_t datasourceselect); + +void RSI_VAD_Enable(RSI_VAD_T *ptrvad); + +void RSI_VAD_InterruptClr(RSI_VAD_T *ptrvad, uint16_t ping_interrupt); + +rsi_error_t RSI_VAD_SetAlgorithmThreshold(RSI_VAD_T *ptrvad, + uint16_t algorithm_type, + uint32_t zcr_threshold, + uint32_t acf_threshold, + uint32_t wacf_threshold, + VAD_AMDF_THRESHOLD_T *config); + +rsi_error_t RSI_VAD_Set_Delay(RSI_VAD_T *ptrvad, uint16_t startdelayval, uint16_t enddelayval); + +rsi_error_t RSI_VAD_Input(RSI_VAD_T *ptrVad, int16_t data); + +rsi_error_t RSI_VAD_FrameEnergyConfig(RSI_VAD_T *ptrvad, + uint32_t threshold_frame_energy, + uint32_t threshold_smpl_collect, + uint32_t prog_smpls_for_energy_check); + +void RSI_VAD_Stop(RSI_VAD_T *pVAD); + +uint8_t RSI_VAD_ProccessDone(RSI_VAD_T *pVAD); + +void RSI_VAD_FastClkEnable(uint16_t fast_clk_sel, uint16_t clk_div_factor); + +int32_t RSI_VAD_ProcessData(RSI_VAD_T *pVAD, + uint32_t vad_addr, + uint32_t adc_data_addr, + int32_t dc_est, + uint32_t dig_scale, + uint32_t sample_len); + +#ifdef __cplusplus +} +#endif + +#endif // RSI_VAD_H diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_wurx.h b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_wurx.h new file mode 100644 index 000000000..3ed64f256 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_wurx.h @@ -0,0 +1,143 @@ +/******************************************************************************* +* @file rsi_wurx.h +* @brief +******************************************************************************* +* # License +* Copyright 2022 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +//Include Files + +#ifndef RSI_WURX_H +#define RSI_WURX_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define PMU_SPI_BASE_ADDR 0x24050000 + +#define WURX_COMP_OFFSET_CALIB_REG *(volatile uint32_t *)(PMU_SPI_BASE_ADDR + 0xa000 + (0x080) * 4) +#define WURX_LCO_FREQ_CALIB_REG *(volatile uint32_t *)(PMU_SPI_BASE_ADDR + 0xa000 + (0x081) * 4) +#define WURX_AAC_MODE_REG *(volatile uint32_t *)(PMU_SPI_BASE_ADDR + 0xa000 + (0x082) * 4) +#define WURX_CLK_GEN_REG *(volatile uint32_t *)(PMU_SPI_BASE_ADDR + 0xa000 + (0x083) * 4) +#define WURX_LNA_IF_REG *(volatile uint32_t *)(PMU_SPI_BASE_ADDR + 0xa000 + (0x084) * 4) +#define WURX_ENABLE_AND_AAC_DET_REG *(volatile uint32_t *)(PMU_SPI_BASE_ADDR + 0xa000 + (0x085) * 4) +#define WURX_TEST_MUX_REG *(volatile uint32_t *)(PMU_SPI_BASE_ADDR + 0xa000 + (0x086) * 4) +#define WURX_TEST_MODE_REG *(volatile uint32_t *)(PMU_SPI_BASE_ADDR + 0xa000 + (0x087) * 4) + +#define WURX_PATTERN1_REG_MSB *(volatile uint32_t *)(PMU_SPI_BASE_ADDR + 0xa000 + (0x089) * 4) +#define WURX_PATTERN1_REG_MID *(volatile uint32_t *)(PMU_SPI_BASE_ADDR + 0xa000 + (0x08A) * 4) +#define WURX_PATTERN1_REG_LSB *(volatile uint32_t *)(PMU_SPI_BASE_ADDR + 0xa000 + (0x08B) * 4) +#define WURX_PATTERN2_REG_MSB *(volatile uint32_t *)(PMU_SPI_BASE_ADDR + 0xa000 + (0x08C) * 4) +#define WURX_PATTERN2_REG_MID *(volatile uint32_t *)(PMU_SPI_BASE_ADDR + 0xa000 + (0x08D) * 4) +#define WURX_PATTERN2_REG_LSB *(volatile uint32_t *)(PMU_SPI_BASE_ADDR + 0xa000 + (0x08E) * 4) +#define WURX_CORR_DET_READ_REG *(volatile uint32_t *)(PMU_SPI_BASE_ADDR + 0xa000 + (0x08F) * 4) +#define WURX_ODD_PATTERN1_REG_LSB *(volatile uint32_t *)(PMU_SPI_BASE_ADDR + 0xa000 + (0x090) * 4) +#define WURX_ODD_PATTERN1_REG_MID *(volatile uint32_t *)(PMU_SPI_BASE_ADDR + 0xa000 + (0x091) * 4) +#define WURX_ODD_PATTERN1_REG_MSB *(volatile uint32_t *)(PMU_SPI_BASE_ADDR + 0xa000 + (0x092) * 4) +#define WURX_EVEN_PATTERN1_REG_LSB *(volatile uint32_t *)(PMU_SPI_BASE_ADDR + 0xa000 + (0x093) * 4) +#define WURX_EVEN_PATTERN1_REG_MID *(volatile uint32_t *)(PMU_SPI_BASE_ADDR + 0xa000 + (0x094) * 4) +#define WURX_EVEN_PATTERN1_REG_MSB *(volatile uint32_t *)(PMU_SPI_BASE_ADDR + 0xa000 + (0x095) * 4) +#define WURX_ODD_PATTERN2_REG_LSB *(volatile uint32_t *)(PMU_SPI_BASE_ADDR + 0xa000 + (0x096) * 4) +#define WURX_ODD_PATTERN2_REG_MID *(volatile uint32_t *)(PMU_SPI_BASE_ADDR + 0xa000 + (0x097) * 4) +#define WURX_ODD_PATTERN2_REG_MSB *(volatile uint32_t *)(PMU_SPI_BASE_ADDR + 0xa000 + (0x098) * 4) +#define WURX_EVEN_PATTERN2_REG_LSB *(volatile uint32_t *)(PMU_SPI_BASE_ADDR + 0xa000 + (0x099) * 4) +#define WURX_EVEN_PATTERN2_REG_MID *(volatile uint32_t *)(PMU_SPI_BASE_ADDR + 0xa000 + (0x09A) * 4) +#define WURX_EVEN_PATTERN2_REG_MSB *(volatile uint32_t *)(PMU_SPI_BASE_ADDR + 0xa000 + (0x09B) * 4) +#define WURX_LEVEL1_PATTERN_REG *(volatile uint32_t *)(PMU_SPI_BASE_ADDR + 0xa000 + (0x09C) * 4) +#define WURX_BYPASS_LEVEL1_AND_FREQ *(volatile uint32_t *)(PMU_SPI_BASE_ADDR + 0xa000 + (0x09D) * 4) +#define WURX_MANUAL_CALIB_MODE_REG1 *(volatile uint32_t *)(PMU_SPI_BASE_ADDR + 0xa000 + (0x09E) * 4) +#define WURX_MANUAL_CALIB_MODE_REG2 *(volatile uint32_t *)(PMU_SPI_BASE_ADDR + 0xa000 + (0x09F) * 4) +#define WURX_CORR_CALIB_REG *(volatile uint32_t *)(PMU_SPI_BASE_ADDR + 0xa000 + (0x088) * 4) +#define ULPCLKS_REFCLK_REG *(volatile uint32_t *)(PMU_SPI_BASE_ADDR + 0xa000 + (0x106) * 4) + +#define BG_SAMPLING_ADDR 0x41300140 +#define BG_SAMPLING_VALUE 0x3 +#define TAIL_DATA_VALUE_CHECK 0x3 +#define SYNC_32KHZ_RESET_VALUE 0x000001 +#define RESET_CALB_CLOCK 0x000002 +#define LCO_CALB_STATUS 0x000002 + +#define VAL0 0 +#define VAL1 1 +#define VAL2 2 +#define VAL3 3 +#define VAL4 4 +#define VAL5 5 +#define VAL6 6 +#define VAL7 7 +#define VAL10 10 +#define VAL100 100 + +#define POS1 1 +#define POS3 3 +#define POS4 4 +#define POS7 7 +#define POS9 9 +#define POS10 10 +#define POS9 9 +#define POS11 11 +#define POS12 12 +#define POS13 13 +#define POS16 16 +#define POS15 15 +#define POS17 17 +#define POS18 18 +#define POS19 19 +#define POS20 20 +#define POS21 21 +#define POS22 22 + +#define IPMU_SPARE_REG2 0x141 +#define DC_OFFSET_VALUE 0x40 +#define REF_CLOCK_FREQ 0x400 +#define DETECTION_REF_SHIFT 0x1FC1FF +#define TAIL_DATA_DECODE_64BIT 0x0 +#define TAIL_DATA_DECODE_128BIT 0x1 +#define TAIL_DATA_DECODE_192BIT 0x2 +#define TAIL_DATA_DECODE_256BIT 0x3 +#define LDO_ON_MODE 0xA8000020 +#define PATTERN_LEN_MASK 0x38000 +#define PATTERN_LEN_CLR_MASK 0x7 +#define THRESH_CLR_MASK_VAL 0x3F + +uint8_t RSI_WURX_GetPatternDetectedType(void); +void RSI_WURX_ConfigL2Patttern(uint8_t freq_div); +void RSI_IPMU_DCCalib(void); +uint16_t RSI_WURX_ReadPatternLength(void); +void RSI_WURX_AnalogOff(void); +void RSI_WURX_DigitalOff(void); +void RSI_WURX_Init(uint16_t bypass_l1_enable, uint16_t l1_freq_div, uint16_t l2_freq_div); +void RSI_WURX_ReadPattern2Even(uint32_t *tail_data); +void RSI_WURX_ReadPattern1Even(uint32_t *tail_data); +void RSI_WURX_ReadPattern1Odd(uint32_t *tail_data); +void RSI_WURX_ReadPattern2Odd(uint32_t *tail_data); +void RSI_WURX_Pattern1MatchValue(uint32_t *match_value); +void RSI_WURX_Pattern2MatchValue(uint32_t *match_value); +uint16_t RSI_WURX_TaildataPresent(void); +void RSI_WURX_CorrEnable(uint16_t wurx_enable); +void RSI_WURX_SetPatternLength(uint16_t enable, uint16_t l1_len, uint16_t l2_len); +void RSI_WURX_SetWakeUpThreshold(uint16_t threshold_1, uint16_t threshold_2); +void RSI_WURX_TailDataDecodeEnable(uint16_t enable, uint16_t data_len); +rsi_error_t RSI_WURX_GetTailData(uint32_t *tail_data, uint16_t tail_data_len); +void RSI_IPMU_40MhzClkCalib(uint16_t clk_enable, uint32_t channel_selection_value); +uint32_t RSI_WURX_CalThershValue(uint32_t bit_length, uint32_t percentage); +void RSI_WURX_SoftwareRestart(void); +int32_t RSI_WURX_GetPatternType(void); +void RSI_WURX_BGSamplingEnable(void); + +#ifdef __cplusplus +} +#endif + +#endif // RSI_WURX_H diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_cci.c b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_cci.c new file mode 100644 index 000000000..69bcb979d --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_cci.c @@ -0,0 +1,174 @@ +/******************************************************************************* +* @file rsi_cci.c +* @brief +******************************************************************************* +* # License +* Copyright 2022 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +// Include Files + +#if defined(CHIP_9118) + +/*==============================================*/ +/** + * @fn void RSI_CCI_AmsEnable() + * @brief This API enables the CCI in the master mode + * @return None + */ +void RSI_CCI_AmsEnable() +{ + AMS_EN |= (1 << 15); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_CCI_AMS_Initialise(RSI_CCI_Init_t *p_cci_config) + * @brief This API configures the CCI peripheral + * @param[in] p_cci_config CCI configuration structure pointer + * \n + * \ref RSI_CCI_Init_t + * \ref CCI_CONTROL_REG_b + * \ref CCI_LSB_A_S1_REG + * @return \ref RSI_OK if success full or + * else error code + */ +rsi_error_t RSI_CCI_AMS_Initialise(RSI_CCI_Init_t *p_cci_config) +{ + CCI_Type *pcci = CCI; + + //Choose the SDR or DDR mode, Address translation enable, address width config and number of slaves by programming the CCI_CONTROL register. + pcci->CCI_CONTROL_b.MODE = (p_cci_config->mode << 2); + pcci->CCI_CONTROL_b.TRANSLATE_ENABLE = p_cci_config->translation_enable; + pcci->CCI_CONTROL_b.ADDR_WIDTH_CONFIG = p_cci_config->address_width_config; + pcci->CCI_CONTROL_b.MODE = (p_cci_config->interface_width << 0); + pcci->CCI_CONTROL_b.ENABLED_SLAVES = p_cci_config->slave_enable; + pcci->CCI_CONTROL_b.SLAVE_PRIORITY = p_cci_config->slave_priority; + pcci->CCI_CONTROL_b.TIME_OUT_PRG = p_cci_config->slave_timeout; + pcci->CCI_CONTROL_b.CCI_CTRL_ENABLE = p_cci_config->cci_cntrl_en; + + if (p_cci_config->mode == 1) // if mode is ddr then load 2x clock enable + { + // 2x clock enable for ddr mode + pcci->CCI_PREFETCH_CTRL_b.CCI_2X_CLK_ENABLE_FOR_DDR_MODE = 1; + } + + // Allocate the lower and higher address range for the each slave by programming in the following registers + switch (p_cci_config->slave_enable) { + case 0: { + if (p_cci_config->slave_lsb_address[0] < p_cci_config->slave_msb_address[0]) { + // Load LSB address supportes and MSB address supported + pcci->CCI_LSB_A_S1 = p_cci_config->slave_lsb_address[0]; + pcci->CCI_MSB_A_S1 = p_cci_config->slave_msb_address[0]; + } else { + return ERROR_CCI_ADDRESS_ERR; + } + break; + } + case 1: { + if (p_cci_config->slave_lsb_address[0] < p_cci_config->slave_msb_address[0]) { + // Load LSB address supportes and MSB address supported + pcci->CCI_LSB_A_S1 = p_cci_config->slave_lsb_address[0]; + pcci->CCI_MSB_A_S1 = p_cci_config->slave_msb_address[0]; + } else { + return ERROR_CCI_ADDRESS_ERR; + } + break; + } + case 2: { + if (p_cci_config->slave_lsb_address[1] < p_cci_config->slave_msb_address[1]) { + // Load LSB address supportes and MSB address supported + pcci->CCI_LSB_A_S2 = p_cci_config->slave_lsb_address[1]; + pcci->CCI_MSB_A_S2 = p_cci_config->slave_msb_address[1]; + } else { + return ERROR_CCI_ADDRESS_ERR; + } + break; + } + + case 3: { + if (p_cci_config->slave_lsb_address[0] < p_cci_config->slave_msb_address[0]) { + // Load LSB address supportes and MSB address supported + pcci->CCI_LSB_A_S1 = p_cci_config->slave_lsb_address[0]; + pcci->CCI_MSB_A_S1 = p_cci_config->slave_msb_address[0]; + } else { + return ERROR_CCI_ADDRESS_ERR; + } + + if (p_cci_config->slave_lsb_address[1] < p_cci_config->slave_msb_address[1]) { + // Load LSB address supportes and MSB address supported + pcci->CCI_LSB_A_S2 = p_cci_config->slave_lsb_address[1]; + pcci->CCI_MSB_A_S2 = p_cci_config->slave_msb_address[1]; + } else { + return ERROR_CCI_ADDRESS_ERR; + } + break; + } + } + + // Load the translation address if address translation feature is enabled by programming the + // cci_translation_address. + if ((p_cci_config->translation_enable) == 1) { + pcci->CCI_TRANS_ADDRESS = p_cci_config->translation_address; + } + + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn uint32_t RSI_CCI_SetFifoThreshlod(volatile CCI_Type *pstcCCI,uint8_t val) + * @brief This API sets the CCI threshhold fifo value + * @param[in] pstcCCI CCI configuration structure pointer \ref CCI_Type + * \ref CCI_FIFO_THRESHOLD_REG + * @param[in] val Threshold value + * @return \ref RSI_OK if success full or + * \n else error code + */ +uint32_t RSI_CCI_SetFifoThreshlod(volatile CCI_Type *pstcCCI, uint8_t val) +{ + pstcCCI->CCI_FIFO_THRESHOLD_REG |= val; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn uint32_t RSI_CCI_PrefetchEnable(volatile CCI_Type *pstcCCI) + * @brief This API is used for prefetct enable + * @param[in] pstcCCI CCI configuration structure pointer + * \ref CCI_Type + * @return \ref RSI_OK if success full or + * \n else error code + */ + +uint32_t RSI_CCI_PrefetchEnable(volatile CCI_Type *pstcCCI) +{ + pstcCCI->CCI_PREFETCH_CTRL_b.CCI_PREFETCH_EN = 0x1; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn uint32_t RSI_CCI_IntClear(volatile CCI_Type *pstcCCI,uint8_t interrupt) + * @brief This API is used to clear the interrupts + * @param[in] pstcCCI CCI configuration structure pointer + * \ref CCI_Type + * @param[in] interrupt 0-2 for interrupt from peer chips + * \n 3 for message interrupt from slave + * @return \ref RSI_OK if success full or + * \n else error code + */ +uint32_t RSI_CCI_IntClear(volatile CCI_Type *pstcCCI, uint8_t interrupt) +{ + return pstcCCI->CCI_MODE_INTR_STATUS_b.INTR_CLEAR = (0x1 << interrupt); +} +#endif diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_fim.c b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_fim.c new file mode 100644 index 000000000..189b37e45 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_fim.c @@ -0,0 +1,4223 @@ +/******************************************************************************* +* @file rsi_fim.c +* @brief +******************************************************************************* +* # License +* Copyright 2022 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +// Include files + +#ifdef ENHANCED_FIM +#include "rsi_enhanced_fim.h" +#endif + +#ifdef ENHANCED_FIM +/*==============================================*/ +/** + *@fn void RSI_FIM_EnableSaturation(void) + *@brief This API is used to enable saturation . + *@return none + */ +void RSI_FIM_EnableSaturation(void) +{ + FIM->FIM_SAT_SHIFT_b.SAT_EN = ENABLE; +} +#endif +/*==============================================*/ +/** + *@fn static void RSI_FIM_InputData(void *pSrcA,uint32_t bank,uint32_t blockSize,uint8_t data_type) + *@brief This API is used to store data in ulp memories + *@param[in] :pSrcA is input vector + *@param[in] :bank is in which memory data samples are stored + *@param[in] :data_type specifies q7,q15 , q31 formats + * \ref FORMAT_F32 + * \ref FORMAT_Q31 + * \ref FORMAT_Q7 + * \ref FORMAT_Q15 + *@param[in] :blockSize is size of the input array + *@return none +*/ +void RSI_FIM_InputData(void *pSrcA, uint32_t bank, uint32_t blockSize, uint8_t data_type) +{ + uint32_t var; + q31_t *pSrcA32; + q15_t *pSrcA16; + q7_t *pSrcA8; + + switch (data_type) { + case FORMAT_F32: + case FORMAT_Q31: + pSrcA32 = (q31_t *)pSrcA; + for (var = 0; var < blockSize; var++) { +#ifdef ENHANCED_FIM + *(volatile uint32_t *)(bank + (var * 4)) = *pSrcA32; +#else + *(volatile uint32_t *)((MEM_BANK + (bank << 2)) + (var * 4)) = *pSrcA32; +#endif + pSrcA32++; + } + break; + + case FORMAT_Q7: + pSrcA8 = (q7_t *)pSrcA; + for (var = 0; var < blockSize; var++) { +#ifdef ENHANCED_FIM + *(volatile uint32_t *)(bank + (var * 4)) = *pSrcA8; +#else + *(volatile uint32_t *)((MEM_BANK + (bank << 2)) + (var * 4)) = *pSrcA8; +#endif + pSrcA8++; + } + break; + + case FORMAT_Q15: + pSrcA16 = (q15_t *)pSrcA; + + for (var = 0; var < blockSize; var++) { +#ifdef ENHANCED_FIM + *(volatile uint32_t *)(bank + (var * 4)) = *pSrcA16; +#else + *(volatile uint32_t *)((MEM_BANK + (bank << 2)) + (var * 4)) = *pSrcA16; +#endif + pSrcA16++; + } + break; + } +} +/*==============================================*/ +/** + *@fn static void RSI_FIM_InputDataCmplx(volatile q15_t *pReal,uint32_t bank,volatile uint32_t var,uint8_t flag) + *@brief This API is used to store data in ulp memories + *@param[in] :pReal is input vector + *@param[in] :bank is in which memory data samples are stored + *@param[in] :flag is set depending on complex-real and real-complex values + *@param[in] :var is for address increment +**/ +static void RSI_FIM_InputDataCmplx(volatile q15_t *pReal, uint32_t bank, volatile uint32_t var, uint8_t flag) +{ + + if (flag) { +#ifdef ENHANCED_FIM + *(volatile uint16_t *)((bank) + ((var + 1) * 2)) = *pReal; +#else + *(volatile uint16_t *)((MEM_BANK + (bank << 2)) + ((var + 1) * 2)) = *pReal; +#endif + pReal++; +#ifdef ENHANCED_FIM + *(volatile uint16_t *)((bank) + (var)*2) = *pReal; +#else + *(volatile uint16_t *)((MEM_BANK + (bank << 2)) + (var)*2) = *pReal; +#endif + pReal++; + } else { +#ifdef ENHANCED_FIM + *(volatile uint16_t *)((bank) + ((var + 1) * 2)) = *pReal; + *(volatile uint16_t *)((bank) + (var)*2) = 0x0000; +#else + *(volatile uint16_t *)((MEM_BANK + (bank << 2)) + ((var + 1) * 2)) = *pReal; + *(volatile uint16_t *)((MEM_BANK + (bank << 2)) + (var)*2) = 0x0000; +#endif + } +} +/*==============================================*/ +/** + *@fn static void RSI_FIM_ComplxOutputConvert(uint32_t blockSize, uint32_t bank,volatile q15_t *pDst) + *@brief This API is used to set the FIM to convert the complex output + *@param[in] :bank is output bank address + *@param[out] :pDst is required output array + *@param[in] :blockSize is size of the input array + *@return :none + */ +static void RSI_FIM_ComplxOutputConvert(uint32_t blockSize, uint32_t bank, volatile q15_t *pDst) +{ + volatile uint32_t i, a; + + for (i = 0; i < blockSize; i++) { + a = i * 2; +#ifdef ENHANCED_FIM + *pDst = *(volatile uint16_t *)((bank) + ((a + 1)) * 2); +#else + *pDst = *(volatile uint16_t *)((MEM_BANK + (bank << 2)) + ((a + 1)) * 2); +#endif + pDst++; +#ifdef ENHANCED_FIM + *pDst = *(volatile uint16_t *)((bank) + (a)*2); +#else + *pDst = *(volatile uint16_t *)((MEM_BANK + (bank << 2)) + (a)*2); +#endif + *pDst++; + } +} +/*==============================================*/ +/** + *@fn void rsi_fim_read_data(uint32_t bank, uint32_t blockSize, volatile void *pDst, uint8_t data_type, typ_data_t type_data) + *@brief This API is used to set the FIM to read the output + *@param[in] bank : is output bank address + *@param[out] pDst : is required output array + *@param[in] data_type : specifies q7,q15 , q31 formats + *@param[in] type_data : is to specify real-complex , complex-real or complex-complex data + *@param[in] length : is size of the input array + *@return none + */ + +void rsi_fim_read_data(uint32_t bank, uint32_t blockSize, volatile void *pDst, uint8_t data_type, typ_data_t type_data) +{ + volatile uint32_t var; + + if ((data_type == FORMAT_F32) || (data_type == FORMAT_Q31)) { + for (var = 0; var < blockSize; var++) { +#ifdef ENHANCED_FIM + ((q31_t *)pDst)[var] = *(volatile uint32_t *)(bank + (var * 4)); +#else + ((q31_t *)pDst)[var] = *(volatile uint32_t *)((MEM_BANK + (bank << 2)) + (var * 4)); +#endif + } + } + + if (data_type == FORMAT_Q7) { + for (var = 0; var < blockSize; var++) { +#ifdef ENHANCED_FIM + ((q7_t *)pDst)[var] = *(volatile uint32_t *)(bank + (var * 4)); +#else + ((q7_t *)pDst)[var] = *(volatile uint32_t *)((MEM_BANK + (bank << 2)) + (var * 4)); +#endif + } + } + if (data_type == FORMAT_Q15) { + if (type_data) { + RSI_FIM_ComplxOutputConvert(blockSize, bank, (q15_t *)pDst); + } else { + for (var = 0; var < blockSize; var++) { +#ifdef ENHANCED_FIM + ((q15_t *)pDst)[var] = *(volatile uint32_t *)(bank) + (var * 4); +#else + ((q15_t *)pDst)[var] = *(volatile uint32_t *)((MEM_BANK + (bank << 2)) + (var * 4)); +#endif + } + } + } +} + +/*==============================================*/ +/** + *@fn static void RSI_FIM_SetDataLen(uint32_t ColAorfilterLen,uint32_t bufferLen1,uint32_t bufferLen2) + *@brief RSI_FIM_SetDataLen API is used to set data blockSize of buffers in the FIM module + *@param[in] :ColAorfilterLen is used for configuring number of columns of first matrix or + * \n filter coefficients for fir , iir and fir interpolator filters. + *@param[in] :bufferLen1 is the blockSize of data used for input1 + * \n for scalar only bufferLen1 need to be configured. + * \n for filter + *@param[in] :bufferLen2 is the blockSize of data used for input2 i.e. only for vector operations this is used. + *@return none + * + */ +static void RSI_FIM_SetDataLen(uint32_t ColAorfilterLen, uint32_t bufferLen1, uint32_t bufferLen2) +{ + FIM->FIM_CONFIG_REG1_b.INP1_LEN = bufferLen1; + FIM->FIM_CONFIG_REG1_b.INP2_LEN = bufferLen2; + FIM->FIM_CONFIG_REG1_b.MAT_LEN = ColAorfilterLen; +} + +/*==============================================*/ +/** + *@fn static void RSI_FIM_SetSatTruncRound(uint32_t SatTruncRoundShift) + *@brief RSI_FIM_SetSatTruncRound API is used to set sat trunc values to FIM module for corresponding inputs + *@param[in] :SatTruncRoundShift is saturate truncation and round value that need to be to get appropriate output + * saturate - to confine msb to limited value + * truncate - to confine lsb to limited value + * + * round - approximating to near value + *@return none + */ +void RSI_FIM_SetSatTruncRound(uint32_t SatTruncRoundShift) +{ + // Shift truncate saturate and round + FIM->FIM_SAT_SHIFT |= SatTruncRoundShift; +} + +/*==============================================*/ +/** + *@fn :static void RSI_FIM_DatTypTrig(uint32_t numRow1, uint32_t numCol2, typ_data_t typData) + *@brief :RSI_FIM_DatTypTrig API is used to trigger the FIM module + *@param[in] :numRow1 is number of rows of first matrix + *@param[in] :numCol2 is number of columns of second matrix + *@param[in] :typData is to select which type of data is given as input i.e. real-real , real-complex , complex-real and complex-complex + * In case of vectors, for real-complx, data in second memory is considered as real and 1st as cmplx. + * for complx-real, data in 1st memory is considered as real and second as cmplx. + * In case of scalar, for real-complx, data in memory is taken as complex and scalar as real. + *@return none +*/ +static void RSI_FIM_DatTypTrig(uint32_t numRow1, uint32_t numCol2, typ_data_t typData) +{ + uint32_t x; + x = 0x0FC00000 & FIM->FIM_CONFIG_REG2; + switch (typData) { + case ULP_FIM_COP_DATA_REAL_REAL: + FIM->FIM_CONFIG_REG2 = x | (numRow1 << 16) | (numCol2 << 10) | typData << 8 | ULP_FIM_COP_START_TRIG; + break; + case ULP_FIM_COP_DATA_CPLX_REAL: + FIM->FIM_CONFIG_REG2 = x | (numRow1 << 16) | (numCol2 << 10) | typData << 8 | ULP_FIM_COP_START_TRIG; + break; + case ULP_FIM_COP_DATA_REAL_CPLX: + FIM->FIM_CONFIG_REG2 = x | (numRow1 << 16) | (numCol2 << 10) | typData << 8 | ULP_FIM_COP_START_TRIG; + break; + case ULP_FIM_COP_DATA_CPLX_CPLX: + FIM->FIM_CONFIG_REG2 = x | (numRow1 << 16) | (numCol2 << 10) | typData << 8 | ULP_FIM_COP_START_TRIG; + break; + } +} + +/*==============================================*/ +/** + *@fn void rsi_arm_offset_f32_opt(int32_t *pSrc, + int32_t scale, + int32_t *pDst, + uint32_t blockSize, + uint16_t inBank, + uint16_t outBank) + *@brief This API is used to set the FIM Scalar Multiplication for real data + *@param[in] *pSrc : points to input vector + *@param[out] *pDst : points to output vector + *@param[in] scale : is constant value that need to be addedd for each elements of vector array. + *@param[in] length : is size of the input array + *@return none + * + */ +void rsi_arm_offset_f32_opt(int32_t *pSrc, + int32_t scale, + int32_t *pDst, + uint32_t blockSize, + uint16_t inBank, + uint16_t outBank) +{ + RSI_FIM_SetDataLen(NOT_MATRIX, blockSize, 0); + RSI_FIM_SetSatTruncRound(STRS(0x1F, 0, 0, 0)); + FIM->FIM_SCALAR_POLE_DATA1_b.SCALAR_POLE_DATA1 = scale; +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + RSI_FIM_InputData(pSrc, ULPSS_RAM_ADDR_SRC, blockSize, FORMAT_F32); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrc; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif +#else + // For 9116 + RSI_FIM_InputData(pSrc, inBank, blockSize, FORMAT_F32); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((ADD_SCALAR << 1) | 1); + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + *@fn void rsi_arm_offset_q7_opt(q7_t *pSrc, q7_t scale, q7_t *pDst, uint32_t blockSize, uint16_t inBank, uint16_t outBank) + *@brief This API is used to set the FIM Scalar Multiplication for real data + *@param[in] *pSrc : points to input vector + *@param[out] *pDst : points to output vector + *@param[in] scale : is constant value that need to be addedd for each elements of vector array. + *@param[in] length : is size of the input array + *@return none + * + */ +void rsi_arm_offset_q7_opt(q7_t *pSrc, q7_t scale, q7_t *pDst, uint32_t blockSize, uint16_t inBank, uint16_t outBank) +{ + RSI_FIM_SetDataLen(NOT_MATRIX, blockSize, 0); + RSI_FIM_SetSatTruncRound(STRS(0x1F, 0, 0, 0)); + FIM->FIM_SCALAR_POLE_DATA1_b.SCALAR_POLE_DATA1 = scale; +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + RSI_FIM_InputData(pSrc, ULPSS_RAM_ADDR_SRC, blockSize, FORMAT_Q7); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrc; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif +#else + // For 9116 + RSI_FIM_InputData(pSrc, inBank, blockSize, FORMAT_Q7); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((ADD_SCALAR << 1) | 1); + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} +/*==============================================*/ + +/** + *@fn void rsi_arm_offset_q15_opt(q15_t *pSrc, + * q15_t scale, + * q15_t *pDst, + * uint32_t blockSize, + * uint16_t inBank, + * uint16_t outBank) + *@brief This API is used to set the FIM Scalar Multiplication for real data + *@param[in] *pSrc : points to input vector + *@param[out] *pDst : points to output vector + *@param[in] scale : is constant value that need to be addedd for each elements of vector array. + *@param[in] length : is size of the input array + *@return none + * + */ + +void rsi_arm_offset_q15_opt(q15_t *pSrc, + q15_t scale, + q15_t *pDst, + uint32_t blockSize, + uint16_t inBank, + uint16_t outBank) +{ + RSI_FIM_SetDataLen(NOT_MATRIX, blockSize, 0); + RSI_FIM_SetSatTruncRound(STRS(0x1F, 0, 0, 0)); + FIM->FIM_SCALAR_POLE_DATA1_b.SCALAR_POLE_DATA1 = scale; +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + RSI_FIM_InputData(pSrc, ULPSS_RAM_ADDR_SRC, blockSize, FORMAT_Q15); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrc; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif +#else + // For 9116 + RSI_FIM_InputData(pSrc, inBank, blockSize, FORMAT_Q15); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((ADD_SCALAR << 1) | 1); + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + *@fn void rsi_arm_offset_q31_opt(q31_t *pSrc, + * q31_t scale, + * q31_t *pDst, + * uint32_t blockSize, + * uint16_t inBank, + * uint16_t outBank) + *@brief This API is used to set the FIM Scalar Multiplication for real data + *@param[in] *pSrc : points to input vector + *@param[out] *pDst : points to output vector + *@param[in] scale : is constant value that need to be addedd for each elements of vector array. + *@param[in] length : is size of the input array + *return none + * + */ +void rsi_arm_offset_q31_opt(q31_t *pSrc, + q31_t scale, + q31_t *pDst, + uint32_t blockSize, + uint16_t inBank, + uint16_t outBank) +{ + RSI_FIM_SetDataLen(NOT_MATRIX, blockSize, 0); + RSI_FIM_SetSatTruncRound(STRS(0x1F, 0, 0, 0)); + FIM->FIM_SCALAR_POLE_DATA1_b.SCALAR_POLE_DATA1 = scale; +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + RSI_FIM_InputData(pSrc, ULPSS_RAM_ADDR_SRC, blockSize, FORMAT_Q31); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrc; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif +#else + // For 9116 + RSI_FIM_InputData(pSrc, inBank, blockSize, FORMAT_Q31); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((ADD_SCALAR << 1) | 1); + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + *@fn void rsi_fim_scalar_sub_f32(int32_t *pSrc, + * int32_t scale, + * int32_t *pDst, + * uint32_t blockSize, + * uint16_t inBank, + * uint16_t outBank) + *@brief This API is used to set the FIM Scalar Subtraction + *@param[in] *pSrc :points to input vector + *@param[out] *pDst : points to output vector + *@param[in] scale : is constant value that need to be subtracted from each elements of vector array. + *@param[in] length :is size of the input array + *@return none + */ +void rsi_fim_scalar_sub_f32(int32_t *pSrc, + int32_t scale, + int32_t *pDst, + uint32_t blockSize, + uint16_t inBank, + uint16_t outBank) +{ + RSI_FIM_SetDataLen(NOT_MATRIX, blockSize, 0); + RSI_FIM_SetSatTruncRound(STRS(0x1F, 0, 0, 0)); + FIM->FIM_SCALAR_POLE_DATA1_b.SCALAR_POLE_DATA1 = scale; +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + RSI_FIM_InputData(pSrc, ULPSS_RAM_ADDR_SRC, blockSize, FORMAT_F32); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrc; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif +#else + // For 9116 + RSI_FIM_InputData(pSrc, inBank, blockSize, FORMAT_F32); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((SUB_SCALAR << 1) | 1); + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ + +/** + *@fn void rsi_fim_scalar_sub_q7(q7_t *pSrc, q7_t scale, q7_t *pDst, uint32_t blockSize, uint16_t inBank, uint16_t outBank) + *@brief This API is used to set the FIM Scalar Subtraction + *@param[in] *pSrc :points to input vector + *@param[out] *pDst : points to output vector + *@param[in] scale : is constant value that need to be subtracted from each elements of vector array. + *@param[in] length :is size of the input array + *@return none + */ + +void rsi_fim_scalar_sub_q7(q7_t *pSrc, q7_t scale, q7_t *pDst, uint32_t blockSize, uint16_t inBank, uint16_t outBank) +{ + RSI_FIM_SetDataLen(NOT_MATRIX, blockSize, 0); + RSI_FIM_SetSatTruncRound(STRS(0x1F, 0, 0, 0)); + FIM->FIM_SCALAR_POLE_DATA1_b.SCALAR_POLE_DATA1 = scale; +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + RSI_FIM_InputData(pSrc, ULPSS_RAM_ADDR_SRC, blockSize, FORMAT_Q15); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrc; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif +#else + // For 9116 + RSI_FIM_InputData(pSrc, inBank, blockSize, FORMAT_Q15); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((SUB_SCALAR << 1) | 1); + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + *@fn void rsi_fim_scalar_sub_q31(q31_t *pSrc, + * q31_t scale, + * q31_t *pDst, + * uint32_t blockSize, + * uint16_t inBank, + * uint16_t outBank) + *@brief This API is used to set the FIM Scalar Subtraction + *@param[in] *pSrc :points to input vector + *@param[out] *pDst : points to output vector + *@param[in] scale : is constant value that need to be subtracted from each elements of vector array. + *@param[in] length :is size of the input array + *@return none + */ +void rsi_fim_scalar_sub_q31(q31_t *pSrc, + q31_t scale, + q31_t *pDst, + uint32_t blockSize, + uint16_t inBank, + uint16_t outBank) +{ + RSI_FIM_SetDataLen(NOT_MATRIX, blockSize, 0); + RSI_FIM_SetSatTruncRound(STRS(0x1F, 0, 0, 0)); + FIM->FIM_SCALAR_POLE_DATA1_b.SCALAR_POLE_DATA1 = scale; +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + RSI_FIM_InputData(pSrc, ULPSS_RAM_ADDR_SRC, blockSize, FORMAT_Q31); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrc; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif +#else + // For 9116 + RSI_FIM_InputData(pSrc, inBank, blockSize, FORMAT_Q31); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((SUB_SCALAR << 1) | 1); + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + *@fn void rsi_arm_scale_f32_opt(int32_t *pSrc, + * int32_t scale, + * int32_t *pDst, + * uint32_t blockSize, + * uint16_t inBank, + * uint16_t outBank) + *@brief This API is used to set the FIM Scalar Multiplication for real data + *@param[in] *pSrc : points to input vector + *@param[out] *pDst : points to output vector + *@param[in] scale : is constant value that need to be multiplied for each elements of vector array. + *@param[in] length : is size of the input array + *@return none + * + */ +void rsi_arm_scale_f32_opt(int32_t *pSrc, + int32_t scale, + int32_t *pDst, + uint32_t blockSize, + uint16_t inBank, + uint16_t outBank) +{ + RSI_FIM_SetDataLen(NOT_MATRIX, blockSize, 0); + RSI_FIM_SetSatTruncRound(STRS(0x9, 0, 0, 0)); + FIM->FIM_SCALAR_POLE_DATA1_b.SCALAR_POLE_DATA1 = scale; +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + RSI_FIM_InputData(pSrc, ULPSS_RAM_ADDR_SRC, blockSize, FORMAT_F32); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrc; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif +#else + // For 9116 + RSI_FIM_InputData(pSrc, inBank, blockSize, FORMAT_F32); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((MUL_SCALAR << 1) | 1); + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + *@fn void rsi_arm_scale_q7_opt(q7_t *pSrc, + * q7_t scaleFract, + * int8_t shift, + * q7_t *pDst, + * uint32_t blockSize, + * uint16_t inBank, + * uint16_t outBank) + *@brief This API is used to set the FIM Scalar Multiplication + *@param[in] pSrc : is input vector A + *@param[in] scale : is constant value that need to be multiplied for each elements of vector array. + *@param[in] blockSize : is size of the input array + *@param[in] typ_data : is to select which type of data is given as input + * \n i.e. real complex , complex real and complex complex + * \n real complex real vector, complex scalar + * \n complex real real scalar, complex vector + *@return none + */ +void rsi_arm_scale_q7_opt(q7_t *pSrc, + q7_t scaleFract, + int8_t shift, + q7_t *pDst, + uint32_t blockSize, + uint16_t inBank, + uint16_t outBank) +{ + RSI_FIM_SetDataLen(NOT_MATRIX, blockSize, 0); + RSI_FIM_SetSatTruncRound(shift + 0x19); + FIM->FIM_SCALAR_POLE_DATA1_b.SCALAR_POLE_DATA1 = scaleFract; +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + RSI_FIM_InputData(pSrc, ULPSS_RAM_ADDR_SRC, blockSize, FORMAT_Q7); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrc; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif +#else + // For 9116 + RSI_FIM_InputData(pSrc, inBank, blockSize, FORMAT_Q7); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((MUL_SCALAR << 1) | 1); + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + *@fn void rsi_arm_scale_q15_opt(q15_t *pSrc, + * q15_t scaleFract, + * int8_t shift, + * q15_t *pDst, + * uint32_t blockSize, + * uint16_t inBank, + * uint16_t outBank) + *@brief This API is used to set the FIM Scalar Multiplication + *@param[in] pSrc : is input vector A + *@param[in] scale : is constant value that need to be multiplied for each elements of vector array. + *@param[in] blockSize : is size of the input array + *@param[in] typ_data : is to select which type of data is given as input + * \n i.e. real complex , complex real and complex complex + * \n real complex real vector, complex scalar + * \n complex real real scalar, complex vector + *@return none + */ +void rsi_arm_scale_q15_opt(q15_t *pSrc, + q15_t scaleFract, + int8_t shift, + q15_t *pDst, + uint32_t blockSize, + uint16_t inBank, + uint16_t outBank) +{ + RSI_FIM_SetDataLen(NOT_MATRIX, blockSize, 0); + RSI_FIM_SetSatTruncRound(shift + 0x11); + FIM->FIM_SCALAR_POLE_DATA1_b.SCALAR_POLE_DATA1 = scaleFract; +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + RSI_FIM_InputData(pSrc, ULPSS_RAM_ADDR_SRC, blockSize, FORMAT_Q15); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrc; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif +#else + // For 9116 + RSI_FIM_InputData(pSrc, inBank, blockSize, FORMAT_Q15); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((MUL_SCALAR << 1) | 1); + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + *@fn void rsi_arm_scale_q31_opt(q31_t *pSrc, + * q31_t scaleFract, + * int8_t shift, + * q31_t *pDst, + * uint32_t blockSize, + * uint16_t inBank, + * uint16_t outBank) + *@brief This API is used to set the FIM Scalar Multiplication + *@param[in] pSrc : is input vector A + *@param[in] scale : is constant value that need to be multiplied for each elements of vector array. + *@param[in] blockSize : is size of the input array + *@param[in] typ_data : is to select which type of data is given as input + * \n i.e. real complex , complex real and complex complex + * \n real complex real vector, complex scalar + * \n complex real real scalar, complex vector + *@return none + */ + +void rsi_arm_scale_q31_opt(q31_t *pSrc, + q31_t scaleFract, + int8_t shift, + q31_t *pDst, + uint32_t blockSize, + uint16_t inBank, + uint16_t outBank) +{ + RSI_FIM_SetDataLen(NOT_MATRIX, blockSize, 0); + RSI_FIM_SetSatTruncRound(shift + 0x1); + FIM->FIM_SCALAR_POLE_DATA1_b.SCALAR_POLE_DATA1 = scaleFract; +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + RSI_FIM_InputData(pSrc, ULPSS_RAM_ADDR_SRC, blockSize, FORMAT_Q31); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrc; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif +#else + // For 9116 + RSI_FIM_InputData(pSrc, inBank, blockSize, FORMAT_Q31); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((MUL_SCALAR << 1) | 1); + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + *@fn void rsi_fim_scalar_mul_q15(q15_t *pSrc, + * q15_t *scale, + * q15_t *pDst, + * uint32_t blockSize, + * typ_data_t typ_data, + * uint16_t inBank, + * uint16_t outBank) + *@brief This API is used to set the FIM Scalar Multiplication + *@param[in] pSrc : is input vector A + *@param[in] scale : is constant value that need to be multiplied for each elements of vector array. + *@param[in] blockSize : is size of the input array + *@param[in] typ_data : is to select which type of data is given as input + * \n i.e. real complex , complex real and complex complex + * \n real complex real vector, complex scalar + * \n complex real real scalar, complex vector + *@return none + */ +void rsi_fim_scalar_mul_q15(q15_t *pSrc, + q15_t *scale, + q15_t *pDst, + uint32_t blockSize, + typ_data_t typ_data, + uint16_t inBank, + uint16_t outBank) +{ + uint32_t i; + q15_t scalarReal; + RSI_FIM_SetDataLen(NOT_MATRIX, blockSize / 2, 0); + RSI_FIM_SetSatTruncRound(STRS(0x11, 0, 0, 0)); + + switch (typ_data) { + case ULP_FIM_COP_DATA_CPLX_REAL: + for (i = 0; i < blockSize / 2; i++) { +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + RSI_FIM_InputDataCmplx(pSrc, ULPSS_RAM_ADDR_SRC, i * 2, 1); +#endif +#else + // For 9116 + RSI_FIM_InputDataCmplx(pSrc, inBank, i * 2, 1); +#endif + pSrc++; + pSrc++; + } + scalarReal = *scale; + FIM->FIM_SCALAR_POLE_DATA1_b.SCALAR_POLE_DATA1 = (scalarReal << 16) | 0x0000; + break; + + case ULP_FIM_COP_DATA_REAL_CPLX: + for (i = 0; i < blockSize / 2; i++) { +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + RSI_FIM_InputDataCmplx(pSrc, ULPSS_RAM_ADDR_SRC, i * 2, 1); +#endif +#else + RSI_FIM_InputDataCmplx(pSrc, inBank, i * 2, 0); +#endif + pSrc++; + } + scalarReal = *scale; + scale++; + FIM->FIM_SCALAR_POLE_DATA1_b.SCALAR_POLE_DATA1 = (scalarReal << 16) | *scale; + break; + + case ULP_FIM_COP_DATA_CPLX_CPLX: + for (i = 0; i < blockSize / 2; i++) { +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + RSI_FIM_InputDataCmplx(pSrc, ULPSS_RAM_ADDR_SRC, i * 2, 1); +#endif +#else + RSI_FIM_InputDataCmplx(pSrc, inBank, i * 2, 1); +#endif + pSrc++; + pSrc++; + } + scalarReal = *scale; + scale++; + FIM->FIM_SCALAR_POLE_DATA1_b.SCALAR_POLE_DATA1 = (scalarReal << 16) | *scale; + + break; + + default: + break; + } +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrc; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif +#else + // For 9116 + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((MUL_SCALAR << 1) | 1); + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, typ_data); +} + +/*==============================================*/ +/** + *@fn void rsi_arm_add_f32_opt(int32_t *pSrcA, + * int32_t *pSrcB, + * int32_t *pDst, + * uint32_t blockSize, + * uint16_t inBank1, + * uint16_t inBank2, + * uint16_t outBank) + *@brief This API is used to set the FIM Vector Addition for real data + *@param[in] pSrcA : points to input vector A + *@param[in] pSrcB : points to input vector B + *@param[out] pDst : points to output vector + *@param[in] blockSize : is size of the input array + *@return none + */ +void rsi_arm_add_f32_opt(int32_t *pSrcA, + int32_t *pSrcB, + int32_t *pDst, + uint32_t blockSize, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank) +{ + RSI_FIM_SetDataLen(NOT_MATRIX, blockSize, blockSize); + RSI_FIM_SetSatTruncRound(STRS(0x1F, 0, 0, 0)); +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + RSI_FIM_InputData(pSrcA, ULPSS_RAM_ADDR_SRC1, blockSize, FORMAT_F32); + RSI_FIM_InputData(pSrcB, ULPSS_RAM_ADDR_SRC2, blockSize, FORMAT_F32); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrcA; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = (uint32_t)pSrcB; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif +#else + // For 9116 + RSI_FIM_InputData(pSrcA, inBank1, blockSize, FORMAT_F32); + RSI_FIM_InputData(pSrcB, inBank2, blockSize, FORMAT_F32); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = inBank2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((ADD_VECTOR << 1) | 1); + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + *@fn void rsi_arm_add_q7_opt(q7_t *pSrcA, + * q7_t *pSrcB, + * q7_t *pDst, + * uint32_t blockSize, + * uint16_t inBank1, + * uint16_t inBank2, + * uint16_t outBank) + *@brief This API is used to set the FIM Vector Addition for real data + *@param[in] pSrcA : points to input vector A + *@param[in] pSrcB : points to input vector B + *@param[out] pDst : points to output vector + *@param[in] blockSize : is size of the input array + *@return none + */ +void rsi_arm_add_q7_opt(q7_t *pSrcA, + q7_t *pSrcB, + q7_t *pDst, + uint32_t blockSize, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank) +{ + RSI_FIM_SetDataLen(NOT_MATRIX, blockSize, blockSize); + RSI_FIM_SetSatTruncRound(STRS(0x1F, 0, 0, 0)); +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + RSI_FIM_InputData(pSrcA, ULPSS_RAM_ADDR_SRC1, blockSize, FORMAT_Q7); + RSI_FIM_InputData(pSrcB, ULPSS_RAM_ADDR_SRC2, blockSize, FORMAT_Q7); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrcA; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = (uint32_t)pSrcB; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif +#else + // For 9116 + RSI_FIM_InputData(pSrcA, inBank1, blockSize, FORMAT_Q7); + RSI_FIM_InputData(pSrcB, inBank2, blockSize, FORMAT_Q7); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = inBank2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((ADD_VECTOR << 1) | 1); + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + *@fn void rsi_arm_add_q15_opt(q15_t *pSrcA, + * q15_t *pSrcB, + * q15_t *pDst, + * uint32_t blockSize, + * uint16_t inBank1, + * uint16_t inBank2, + * uint16_t outBank) + *@brief This API is used to set the FIM Vector Addition for real data + *@param[in] pSrcA : points to input vector A + *@param[in] pSrcB : points to input vector B + *@param[out] pDst : points to output vector + *@param[in] blockSize : is size of the input array + *@return none + */ +void rsi_arm_add_q15_opt(q15_t *pSrcA, + q15_t *pSrcB, + q15_t *pDst, + uint32_t blockSize, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank) +{ + RSI_FIM_SetDataLen(NOT_MATRIX, blockSize, blockSize); + RSI_FIM_SetSatTruncRound(STRS(0x1F, 0, 0, 0)); +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + RSI_FIM_InputData(pSrcA, ULPSS_RAM_ADDR_SRC1, blockSize, FORMAT_Q15); + RSI_FIM_InputData(pSrcB, ULPSS_RAM_ADDR_SRC2, blockSize, FORMAT_Q15); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrcA; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = (uint32_t)pSrcB; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif +#else + // For 9116 + RSI_FIM_InputData(pSrcA, inBank1, blockSize, FORMAT_Q15); + RSI_FIM_InputData(pSrcB, inBank2, blockSize, FORMAT_Q15); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = inBank2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((ADD_VECTOR << 1) | 1); + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + *@fn void rsi_arm_add_q31_opt(q31_t *pSrcA, + * q31_t *pSrcB, + * q31_t *pDst, + * uint32_t blockSize, + * uint16_t inBank1, + * uint16_t inBank2, + * uint16_t outBank) + *@brief This API is used to set the FIM Vector Addition for real data + *@param[in] pSrcA : points to input vector A + *@param[in] pSrcB : points to input vector B + *@param[out] pDst : points to output vector + *@param[in] blockSize : is size of the input array + *@return none + */ +void rsi_arm_add_q31_opt(q31_t *pSrcA, + q31_t *pSrcB, + q31_t *pDst, + uint32_t blockSize, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank) +{ + RSI_FIM_SetDataLen(NOT_MATRIX, blockSize, blockSize); + RSI_FIM_SetSatTruncRound(STRS(0x1F, 0, 0, 0)); +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + RSI_FIM_InputData(pSrcA, ULPSS_RAM_ADDR_SRC1, blockSize, FORMAT_Q31); + RSI_FIM_InputData(pSrcB, ULPSS_RAM_ADDR_SRC2, blockSize, FORMAT_Q31); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrcA; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = (uint32_t)pSrcB; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif +#else + // For 9116 + RSI_FIM_InputData(pSrcA, inBank1, blockSize, FORMAT_Q31); + RSI_FIM_InputData(pSrcB, inBank2, blockSize, FORMAT_Q31); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = inBank2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((ADD_VECTOR << 1) | 1); + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + *@fn void rsi_fim_vector_add_q15(q15_t *pIn1, + * q15_t *pIn2, + * q15_t *pDst, + * uint32_t blockSize, + * typ_data_t typ_data, + * uint16_t inBank1, + * uint16_t inBank2, + * uint16_t outBank) + *@brief This API is used to set the FIM Vector Addition + *@param[in] pIn1 : points to input vector A + *@param[in] pIn2 : points to input vector B + *@param[in] blockSize : is size of the input array + *@param[out] pDst : points to output vector + *@param[in] typ_data : is to select which type of data is given as input + * \n i.e. real complex , complex real and complex complex + * \n real complex 1st vector is real vector i.e pIn1, 2nd vector is complex i.e pIn2 + * \n complex real 1st vector is complex vector i.e pIn1, 2nd vector is real i.e pIn2 + *@return none + */ +void rsi_fim_vector_add_q15(q15_t *pIn1, + q15_t *pIn2, + q15_t *pDst, + uint32_t blockSize, + typ_data_t typ_data, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank) +{ + uint32_t i; + RSI_FIM_SetDataLen(NOT_MATRIX, blockSize / 2, blockSize / 2); + RSI_FIM_SetSatTruncRound(STRS(0x1F, 0, 0, 0)); + + switch (typ_data) { + case ULP_FIM_COP_DATA_CPLX_REAL: + for (i = 0; i < blockSize / 2; i++) { +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + RSI_FIM_InputDataCmplx(pIn2, ULPSS_RAM_ADDR_SRC2, i * 2, 0); +#endif +#else + RSI_FIM_InputDataCmplx(pIn2, inBank2, i * 2, 0); +#endif + pIn2++; +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + RSI_FIM_InputDataCmplx(pIn1, ULPSS_RAM_ADDR_SRC1, i * 2, 1); +#endif +#else + RSI_FIM_InputDataCmplx(pIn1, inBank1, i * 2, 1); +#endif + pIn1++; + pIn1++; + } + break; + + case ULP_FIM_COP_DATA_REAL_CPLX: + for (i = 0; i < blockSize / 2; i++) { +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + RSI_FIM_InputDataCmplx(pIn1, ULPSS_RAM_ADDR_SRC1, i * 2, 0); +#endif +#else + RSI_FIM_InputDataCmplx(pIn1, inBank1, i * 2, 0); +#endif + pIn1++; +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + RSI_FIM_InputDataCmplx(pIn2, ULPSS_RAM_ADDR_SRC2, i * 2, 1); +#endif +#else + RSI_FIM_InputDataCmplx(pIn2, inBank2, i * 2, 1); +#endif + pIn2++; + pIn2++; + } + break; + + case ULP_FIM_COP_DATA_CPLX_CPLX: + for (i = 0; i < blockSize / 2; i++) { +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + RSI_FIM_InputDataCmplx(pIn1, ULPSS_RAM_ADDR_SRC1, i * 2, 1); +#endif +#else + RSI_FIM_InputDataCmplx(pIn1, inBank1, i * 2, 1); +#endif + pIn1++; + pIn1++; +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + RSI_FIM_InputDataCmplx(pIn1, ULPSS_RAM_ADDR_SRC2, i * 2, 1); +#endif +#else + RSI_FIM_InputDataCmplx(pIn2, inBank2, i * 2, 1); +#endif + pIn2++; + pIn2++; + } + + break; + + default: + break; + } +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pIn1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = (uint32_t)pIn2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif +#else + // For 9116 + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = inBank2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((ADD_VECTOR << 1) | 1); + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, typ_data); +} + +/*==============================================*/ +/** + *@fn void rsi_arm_sub_f32_opt(int32_t *pSrcA, + * int32_t *pSrcB, + * int32_t *pDst, + * uint32_t blockSize, + * uint16_t inBank1, + * uint16_t inBank2, + * uint16_t outBank) + *@brief This API is used to set the FIM Vector Subtraction for real data + *@param[in] pSrcA : points to input vector A + *@param[in] pSrcB : points to input vector B + *@param[out] pDst : points to output vector + *@param[in] blockSize : is size of the input array + *@return none + * + */ +void rsi_arm_sub_f32_opt(int32_t *pSrcA, + int32_t *pSrcB, + int32_t *pDst, + uint32_t blockSize, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank) +{ + RSI_FIM_SetDataLen(NOT_MATRIX, blockSize, blockSize); + RSI_FIM_SetSatTruncRound(STRS(0x1F, 0, 0, 0)); +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + RSI_FIM_InputData(pSrcA, ULPSS_RAM_ADDR_SRC1, blockSize, FORMAT_F32); + RSI_FIM_InputData(pSrcB, ULPSS_RAM_ADDR_SRC2, blockSize, FORMAT_F32); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrcA; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = (uint32_t)pSrcB; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif +#else + // For 9116 + RSI_FIM_InputData(pSrcA, inBank1, blockSize, FORMAT_F32); + RSI_FIM_InputData(pSrcB, inBank2, blockSize, FORMAT_F32); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = inBank2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((SUB_VECTOR << 1) | 1); + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + *@fn void rsi_arm_sub_q7_opt(q7_t *pSrcA, + * q7_t *pSrcB, + * q7_t *pDst, + * uint32_t blockSize, + * uint16_t inBank1, + * uint16_t inBank2, + * uint16_t outBank) + *@brief This API is used to set the FIM Vector Subtraction for real data + *@param[in] pSrcA : points to input vector A + *@param[in] pSrcB : points to input vector B + *@param[out] pDst : points to output vector + *@param[in] blockSize : is size of the input array + *@return none + */ +void rsi_arm_sub_q7_opt(q7_t *pSrcA, + q7_t *pSrcB, + q7_t *pDst, + uint32_t blockSize, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank) +{ + RSI_FIM_SetDataLen(NOT_MATRIX, blockSize, blockSize); + RSI_FIM_SetSatTruncRound(STRS(0x1F, 0, 0, 0)); +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + RSI_FIM_InputData(pSrcA, ULPSS_RAM_ADDR_SRC1, blockSize, FORMAT_Q7); + RSI_FIM_InputData(pSrcB, ULPSS_RAM_ADDR_SRC2, blockSize, FORMAT_Q7); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrcA; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = (uint32_t)pSrcB; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif +#else + // For 9116 + RSI_FIM_InputData(pSrcA, inBank1, blockSize, FORMAT_Q7); + RSI_FIM_InputData(pSrcB, inBank2, blockSize, FORMAT_Q7); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = inBank2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((SUB_VECTOR << 1) | 1); + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + *@fn void rsi_arm_sub_q15_opt(q15_t *pSrcA, + * q15_t *pSrcB, + * q15_t *pDst, + * uint32_t blockSize, + * uint16_t inBank1, + * uint16_t inBank2, + * uint16_t outBank) + *@brief This API is used to set the FIM Vector Subtraction for real data + *@param[in] pSrcA : points to input vector A + *@param[in] pSrcB : points to input vector B + *@param[out] pDst : points to output vector + *@param[in] blockSize : is size of the input array + *@return none + * + */ +void rsi_arm_sub_q15_opt(q15_t *pSrcA, + q15_t *pSrcB, + q15_t *pDst, + uint32_t blockSize, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank) +{ + RSI_FIM_SetDataLen(NOT_MATRIX, blockSize, blockSize); + RSI_FIM_SetSatTruncRound(STRS(0x1F, 0, 0, 0)); +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + RSI_FIM_InputData(pSrcA, ULPSS_RAM_ADDR_SRC1, blockSize, FORMAT_Q15); + RSI_FIM_InputData(pSrcB, ULPSS_RAM_ADDR_SRC2, blockSize, FORMAT_Q15); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrcA; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = (uint32_t)pSrcB; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif +#else + // For 9116 + RSI_FIM_InputData(pSrcA, inBank1, blockSize, FORMAT_Q15); + RSI_FIM_InputData(pSrcB, inBank2, blockSize, FORMAT_Q15); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = inBank2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((SUB_VECTOR << 1) | 1); + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + *@fn void rsi_arm_sub_q31_opt(q31_t *pSrcA, + * q31_t *pSrcB, + * q31_t *pDst, + * uint32_t blockSize, + * uint16_t inBank1, + * uint16_t inBank2, + * uint16_t outBank) + *@brief This API is used to set the FIM Vector Subtraction for real data + *@param[in] pSrcA : points to input vector A + *@param[in] pSrcB : points to input vector B + *@param[out] pDst : points to output vector + *@param[in] blockSize : is size of the input array + *@return none + */ +void rsi_arm_sub_q31_opt(q31_t *pSrcA, + q31_t *pSrcB, + q31_t *pDst, + uint32_t blockSize, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank) +{ + RSI_FIM_SetDataLen(NOT_MATRIX, blockSize, blockSize); + RSI_FIM_SetSatTruncRound(STRS(0x1F, 0, 0, 0)); +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + RSI_FIM_InputData(pSrcA, ULPSS_RAM_ADDR_SRC1, blockSize, FORMAT_Q31); + RSI_FIM_InputData(pSrcB, ULPSS_RAM_ADDR_SRC2, blockSize, FORMAT_Q31); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrcA; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = (uint32_t)pSrcB; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif +#else + // For 9116 + RSI_FIM_InputData(pSrcA, inBank1, blockSize, FORMAT_Q31); + RSI_FIM_InputData(pSrcB, inBank2, blockSize, FORMAT_Q31); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = inBank2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((SUB_VECTOR << 1) | 1); + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + *@fn void rsi_fim_vector_sub_q15(q15_t *pIn1, + * q15_t *pIn2, + * q15_t *pDst, + * uint32_t blockSize, + * typ_data_t typ_data, + * uint16_t inBank1, + * uint16_t inBank2, + * uint16_t outBank) + *@brief This API is used to set the FIM Vector Subtraction + *@param[in] pIn1 : is input vector A + *@param[in] pIn2 : is input vector B + *@param[out] pDst : is required output array + *@param[in] typ_data : is to specify real-complex , complex-real or complex-complex data + *@param[in] blockSize : is size of the input array + *@return none + */ +void rsi_fim_vector_sub_q15(q15_t *pIn1, + q15_t *pIn2, + q15_t *pDst, + uint32_t blockSize, + typ_data_t typ_data, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank) +{ + uint32_t i; + RSI_FIM_SetDataLen(NOT_MATRIX, blockSize / 2, blockSize / 2); + RSI_FIM_SetSatTruncRound(STRS(0x1F, 0, 0, 0)); + + switch (typ_data) { + case ULP_FIM_COP_DATA_CPLX_REAL: + + for (i = 0; i < (blockSize / 2); i++) { +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + RSI_FIM_InputDataCmplx(pIn2, ULPSS_RAM_ADDR_SRC2, i * 2, 0); +#endif +#else + RSI_FIM_InputDataCmplx(pIn2, inBank2, i * 2, 0); +#endif + pIn2++; +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + RSI_FIM_InputDataCmplx(pIn1, ULPSS_RAM_ADDR_SRC1, i * 2, 1); +#endif +#else + RSI_FIM_InputDataCmplx(pIn1, inBank1, i * 2, 1); +#endif + pIn1++; + pIn1++; + } + break; + + case ULP_FIM_COP_DATA_REAL_CPLX: + for (i = 0; i < (blockSize / 2); i++) { +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + RSI_FIM_InputDataCmplx(pIn1, ULPSS_RAM_ADDR_SRC1, i * 2, 0); +#endif +#else + RSI_FIM_InputDataCmplx(pIn1, inBank1, i * 2, 0); +#endif + pIn1++; +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + RSI_FIM_InputDataCmplx(pIn2, ULPSS_RAM_ADDR_SRC2, i * 2, 1); +#endif +#else + RSI_FIM_InputDataCmplx(pIn2, inBank2, i * 2, 1); +#endif + pIn2++; + pIn2++; + } + break; + + case ULP_FIM_COP_DATA_CPLX_CPLX: + for (i = 0; i < blockSize / 2; i++) { +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + RSI_FIM_InputDataCmplx(pIn1, ULPSS_RAM_ADDR_SRC1, i * 2, 1); +#endif +#else + RSI_FIM_InputDataCmplx(pIn1, inBank1, i * 2, 1); +#endif + pIn1++; + pIn1++; +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + RSI_FIM_InputDataCmplx(pIn2, ULPSS_RAM_ADDR_SRC2, i * 2, 1); +#endif + RSI_FIM_InputDataCmplx(pIn2, inBank2, i * 2, 1); +#endif + pIn2++; + pIn2++; + } + + break; + + default: + break; + } +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pIn1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = (uint32_t)pIn2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif +#else + // For 9116 + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = inBank2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((SUB_VECTOR << 1) | 1); + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, typ_data); +} + +/*==============================================*/ +/** + *@fn void rsi_arm_mult_f32_opt(int32_t *pIn1, + * int32_t *pIn2, + * int32_t *pDst, + * uint32_t SatTruncRound, + * uint32_t blockSize, + * uint16_t inBank1, + * uint16_t inBank2, + * uint16_t outBank) + *@brief This API is used to set the FIM Vector Multiplication for real data + *@param[in] pIn1 : is input vector A + *@param[in] pIn2 : is input vector B + *@param[in] length : is size of the input array + *@param[in] SatTruncRound : is used to limit the output as required + *@return none + */ +void rsi_arm_mult_f32_opt(int32_t *pIn1, + int32_t *pIn2, + int32_t *pDst, + uint32_t SatTruncRound, + uint32_t blockSize, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank) +{ + RSI_FIM_SetDataLen(NOT_MATRIX, blockSize, blockSize); + RSI_FIM_SetSatTruncRound(SatTruncRound); +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + RSI_FIM_InputData(pIn1, ULPSS_RAM_ADDR_SRC1, blockSize, FORMAT_F32); + RSI_FIM_InputData(pIn2, ULPSS_RAM_ADDR_SRC2, blockSize, FORMAT_F32); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pIn1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = (uint32_t)pIn2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif +#else + // For 9116 + RSI_FIM_InputData(pIn1, inBank1, blockSize, FORMAT_F32); + RSI_FIM_InputData(pIn2, inBank2, blockSize, FORMAT_F32); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = inBank2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((MUL_VECTOR << 1) | 1); + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + *@fn void rsi_arm_mult_q7_opt(q7_t *pSrcA, + * q7_t *pSrcB, + * q7_t *pDst, + * uint32_t blockSize, + * uint16_t inBank1, + * uint16_t inBank2, + * uint16_t outBank) + *@brief This API is used for Q7 vector multiplication + *@param[in] *pSrcA : points to the first input vector + *@param[in] *pSrcB : points to the second input vector + *@param[out] *pDst : points to the output vector + *@param[in] blockSize : number of samples in each vector + *@return none + */ +void rsi_arm_mult_q7_opt(q7_t *pSrcA, + q7_t *pSrcB, + q7_t *pDst, + uint32_t blockSize, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank) +{ + RSI_FIM_SetDataLen(NOT_MATRIX, blockSize, blockSize); + RSI_FIM_SetSatTruncRound(STRS(0x19, 0, 0, 0)); +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + RSI_FIM_InputData(pSrcA, ULPSS_RAM_ADDR_SRC1, blockSize, FORMAT_Q7); + RSI_FIM_InputData(pSrcB, ULPSS_RAM_ADDR_SRC2, blockSize, FORMAT_Q7); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrcA; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = (uint32_t)pSrcB; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif +#else + // For 9116 + RSI_FIM_InputData(pSrcA, inBank1, blockSize, FORMAT_Q7); + RSI_FIM_InputData(pSrcB, inBank2, blockSize, FORMAT_Q7); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = inBank2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((MUL_VECTOR << 1) | 1); + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + *@fn void rsi_arm_mult_q15_opt(q15_t *pSrcA, + * q15_t *pSrcB, + * q15_t *pDst, + * uint32_t blockSize, + * uint16_t inBank1, + * uint16_t inBank2, + * uint16_t outBank) + *@brief This API is used for Q15 vector multiplication + *@param[in] *pSrcA : points to the first input vector + *@param[in] *pSrcB : points to the second input vector + *@param[out] *pDst : points to the output vector + *@param[in] blockSize : number of samples in each vector + *@return none + */ + +void rsi_arm_mult_q15_opt(q15_t *pSrcA, + q15_t *pSrcB, + q15_t *pDst, + uint32_t blockSize, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank) +{ + RSI_FIM_SetDataLen(NOT_MATRIX, blockSize, blockSize); + RSI_FIM_SetSatTruncRound(STRS(0x11, 0, 0, 0)); +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + RSI_FIM_InputData(pSrcA, ULPSS_RAM_ADDR_SRC1, blockSize, FORMAT_Q15); + RSI_FIM_InputData(pSrcB, ULPSS_RAM_ADDR_SRC2, blockSize, FORMAT_Q15); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrcA; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = (uint32_t)pSrcB; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif +#else + // For 9116 + RSI_FIM_InputData(pSrcA, inBank1, blockSize, FORMAT_Q15); + RSI_FIM_InputData(pSrcB, inBank2, blockSize, FORMAT_Q15); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = inBank2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((MUL_VECTOR << 1) | 1); + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + *@fn void rsi_arm_mult_q31_opt(q31_t *pSrcA, + * q31_t *pSrcB, + * q31_t *pDst, + * uint32_t blockSize, + * uint16_t inBank1, + * uint16_t inBank2, + * uint16_t outBank) + *@brief This API is used for Vector Multiplication for complex-real data + *@param[in] pIn1 : is input vector A + *@param[in] pIn2 : is input vector B + *@param[out] *pDst : points to the output vector + *@param[in] blockSize : is size of the input array + *@return none + */ +void rsi_arm_mult_q31_opt(q31_t *pSrcA, + q31_t *pSrcB, + q31_t *pDst, + uint32_t blockSize, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank) +{ + RSI_FIM_SetDataLen(NOT_MATRIX, blockSize, blockSize); + RSI_FIM_SetSatTruncRound(STRS(0x1, 0, 0, 0)); +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + RSI_FIM_InputData(pSrcA, ULPSS_RAM_ADDR_SRC1, blockSize, FORMAT_Q31); + RSI_FIM_InputData(pSrcB, ULPSS_RAM_ADDR_SRC2, blockSize, FORMAT_Q31); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrcA; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = (uint32_t)pSrcB; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif +#else + // For 9116 + RSI_FIM_InputData(pSrcA, inBank1, blockSize, FORMAT_Q31); + RSI_FIM_InputData(pSrcB, inBank2, blockSize, FORMAT_Q31); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = inBank2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((MUL_VECTOR << 1) | 1); + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + *@fn void rsi_arm_cmplx_mult_real_q15_opt(q15_t *pSrcCmplx, + * q15_t *pSrcReal, + * q15_t *pDst, + * uint32_t numSamples, + * uint16_t inBank1, + * uint16_t inBank2, + * uint16_t outBank) + *@brief This API is used to set the FIM Vector Multiplication for complex-real data + *@param[in] pSrcCmplx : is input vector A + *@param[in] pSrcReal : is input vector B + *@param *pDst : points to the real output vector + *@param numSamples : number of complex samples in the input vector + *@return none + */ +void rsi_fim_vector_mul_q15(q15_t *pIn1, + q15_t *pIn2, + q15_t *pDst, + uint32_t blockSize, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank) +{ + uint32_t i; + RSI_FIM_SetDataLen(NOT_MATRIX, blockSize / 2, blockSize / 2); + RSI_FIM_SetSatTruncRound(STRS(0x11, 0, 0, 0)); + for (i = 0; i < (blockSize / 2); i++) { +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + RSI_FIM_InputDataCmplx(pIn2, ULPSS_RAM_ADDR_SRC2, i * 2, 1); +#endif +#else + RSI_FIM_InputDataCmplx(pIn2, inBank2, i * 2, 1); +#endif + pIn2++; + pIn2++; +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + RSI_FIM_InputDataCmplx(pIn1, ULPSS_RAM_ADDR_SRC1, i * 2, 0); +#endif +#else + RSI_FIM_InputDataCmplx(pIn1, inBank1, i * 2, 0); +#endif + pIn1++; + } +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pIn2; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = (uint32_t)pIn2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif +#else + // For 9116 + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = inBank2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((MUL_VECTOR << 1) | 1); + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_CPLX); +} + +/*==============================================*/ +/** + *@fn void rsi_arm_cmplx_mult_real_q15_opt(q15_t *pSrcCmplx, + * q15_t *pSrcReal, + * q15_t *pDst, + * uint32_t numSamples, + * uint16_t inBank1, + * uint16_t inBank2, + * uint16_t outBank) + *@brief This API is used to set the FIM Vector Multiplication for complex-real data + *@param[in] pSrcCmplx : is input vector A + *@param[in] pSrcReal : is input vector B + *@param *pDst : points to the real output vector + *@param numSamples : number of complex samples in the input vector + *@return none + */ + +void rsi_arm_cmplx_mult_real_q15_opt(q15_t *pSrcCmplx, + q15_t *pSrcReal, + q15_t *pDst, + uint32_t numSamples, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank) +{ + uint32_t i; + RSI_FIM_SetDataLen(NOT_MATRIX, numSamples / 2, numSamples / 2); + RSI_FIM_SetSatTruncRound(STRS(0x11, 0, 0, 0)); + for (i = 0; i < (numSamples / 2); i++) { +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + RSI_FIM_InputDataCmplx(pSrcCmplx, ULPSS_RAM_ADDR_SRC1, i * 2, 1); +#endif +#else + RSI_FIM_InputDataCmplx(pSrcCmplx, inBank1, i * 2, 1); +#endif + pSrcCmplx++; + pSrcCmplx++; +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + RSI_FIM_InputDataCmplx(pSrcReal, ULPSS_RAM_ADDR_SRC2, i * 2, 0); +#endif +#else + RSI_FIM_InputDataCmplx(pSrcReal, inBank2, i * 2, 0); +#endif + pSrcReal++; + } +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrcCmplx; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = (uint32_t)pSrcReal; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif +#else + // For 9116 + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = inBank2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((MUL_VECTOR << 1) | 1); + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_CPLX_REAL); +} + +/*==============================================*/ +/** + *@fn void rsi_arm_cmplx_mult_cmplx_q15_opt(q15_t *pSrcA, + * q15_t *pSrcB, + * q15_t *pDst, + * uint32_t numSamples, + * uint16_t inBank1, + * uint16_t inBank2, + * uint16_t outBank) + *@brief This API is used for Q15 complex-by-complex multiplication + *@param[in] *pSrcA : points to the first input vector + *@param[in] *pSrcB : points to the second input vector + *@param[out] *pDst : points to the output vector + *@param[in] numSamples : number of complex samples in each vector + *@return none + */ +void rsi_arm_cmplx_mult_cmplx_q15_opt(q15_t *pSrcA, + q15_t *pSrcB, + q15_t *pDst, + uint32_t numSamples, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank) +{ + uint32_t i; + RSI_FIM_SetDataLen(NOT_MATRIX, numSamples / 2, numSamples / 2); + RSI_FIM_SetSatTruncRound(STRS(0x10, 0, 0, 1)); + for (i = 0; i < (numSamples / 2); i++) { +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + RSI_FIM_InputDataCmplx(pSrcA, ULPSS_RAM_ADDR_SRC1, i * 2, ULP_FIM_COP_DATA_CPLX_CPLX); +#endif +#else + RSI_FIM_InputDataCmplx(pSrcA, inBank1, i * 2, ULP_FIM_COP_DATA_CPLX_CPLX); +#endif + pSrcA++; + pSrcA++; +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + RSI_FIM_InputDataCmplx(pSrcB, ULPSS_RAM_ADDR_SRC2, i * 2, ULP_FIM_COP_DATA_CPLX_CPLX); +#endif +#else + RSI_FIM_InputDataCmplx(pSrcB, inBank2, i * 2, ULP_FIM_COP_DATA_CPLX_CPLX); +#endif + pSrcB++; + pSrcB++; + } +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrcA; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = (uint32_t)pSrcB; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif +#else + // For 9116 + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = inBank2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((MUL_VECTOR << 1) | 1); + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_CPLX_CPLX); +} + +/*==============================================*/ +/** + *@fn void rsi_arm_cmplx_mag_squared_q15_opt(q15_t *pSrc, q15_t *pDst, uint32_t numSamples, uint16_t inBank, uint16_t outBank) + *@brief This API is used to set the FIM Absolute Squaring for real number + *@param[in] pSrc : is input for squaring a number + *@param[in] length : is size of the input array + *@return none + */ + +void rsi_arm_cmplx_mag_squared_q15_opt(q15_t *pSrc, q15_t *pDst, uint32_t numSamples, uint16_t inBank, uint16_t outBank) +{ + uint32_t i; + RSI_FIM_SetDataLen(NOT_MATRIX, numSamples / 2, numSamples / 2); + RSI_FIM_SetSatTruncRound(STRS(0x10, 0, 0, 1)); + for (i = 0; i < (numSamples / 2); i++) { +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + RSI_FIM_InputDataCmplx(pSrc, ULPSS_RAM_ADDR_SRC, i * 2, ULP_FIM_COP_DATA_CPLX_CPLX); +#endif +#else + RSI_FIM_InputDataCmplx(pSrc, inBank, i * 2, ULP_FIM_COP_DATA_CPLX_CPLX); +#endif + pSrc++; + pSrc++; + } +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrc; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif +#else + // For 9116 + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((NORM_SQUARE << 1) | 1); + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_CPLX_CPLX); +} + +/*==============================================*/ +/** + *@fn void rsi_fim_absSqr_q7(q7_t *pSrc, q7_t *pDst, uint32_t blockSize, uint16_t inBank, uint16_t outBank) + *@brief This API is used to set the FIM Absolute Squaring for real number + *@param[in] pSrc : is input for squaring a number + *@param[in] length : is size of the input array + *@return none + */ + +void rsi_fim_absSqr_q7(q7_t *pSrc, q7_t *pDst, uint32_t blockSize, uint16_t inBank, uint16_t outBank) +{ + RSI_FIM_SetDataLen(NOT_MATRIX, blockSize, blockSize); + RSI_FIM_SetSatTruncRound(STRS(0x19, 0, 0, 0)); +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + RSI_FIM_InputData(pSrc, ULPSS_RAM_ADDR_SRC, blockSize, FORMAT_Q7); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrc; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif +#else + // For 9116 + RSI_FIM_InputData(pSrc, inBank, blockSize, FORMAT_Q7); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((NORM_SQUARE << 1) | 1); + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + *@fn void rsi_fim_absSqr_q15(q15_t *pSrc, q15_t *pDst, uint32_t blockSize, uint16_t inBank, uint16_t outBank) + *@brief This API is used to set the FIM Absolute Squaring for real number + *@param[in] pSrc : is input for squaring a number + *@param[in] length : is size of the input array + *@return none + */ +void rsi_fim_absSqr_q15(q15_t *pSrc, q15_t *pDst, uint32_t blockSize, uint16_t inBank, uint16_t outBank) +{ + RSI_FIM_SetDataLen(NOT_MATRIX, blockSize, blockSize); + RSI_FIM_SetSatTruncRound(STRS(0x11, 0, 0, 0)); +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + RSI_FIM_InputData(pSrc, ULPSS_RAM_ADDR_SRC, blockSize, FORMAT_Q15); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrc; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif +#else + // For 9116 + RSI_FIM_InputData(pSrc, inBank, blockSize, FORMAT_Q15); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((NORM_SQUARE << 1) | 1); + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + *@fn void rsi_fim_absSqr_q31(q31_t *pSrc, q31_t *pDst, uint32_t blockSize, uint16_t inBank, uint16_t outBank) + *@brief This API is used to set the FIM Absolute Squaring for real number + *@param[in] pSrc : is input for squaring a number + *@param[in] length : is size of the input array + *@return none + */ +void rsi_fim_absSqr_q31(q31_t *pSrc, q31_t *pDst, uint32_t blockSize, uint16_t inBank, uint16_t outBank) +{ + RSI_FIM_SetDataLen(NOT_MATRIX, blockSize, blockSize); + RSI_FIM_SetSatTruncRound(STRS(0x1, 0, 0, 0)); +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + RSI_FIM_InputData(pSrc, ULPSS_RAM_ADDR_SRC, blockSize, FORMAT_Q31); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrc; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif +#else + // For 9116 + RSI_FIM_InputData(pSrc, inBank, blockSize, FORMAT_Q31); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((NORM_SQUARE << 1) | 1); + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + *@fn void rsi_fim_absSqr_f32(int32_t *pSrc, int32_t *pDst, uint32_t blockSize, uint16_t inBank, uint16_t outBank) + *@brief This API is used to set the FIM Absolute Squaring for real number + *@param[in] pSrc : is input for squaring a number + *@param[in] length : is size of the input array + *@return none + */ +void rsi_fim_absSqr_f32(int32_t *pSrc, int32_t *pDst, uint32_t blockSize, uint16_t inBank, uint16_t outBank) +{ + RSI_FIM_SetDataLen(NOT_MATRIX, blockSize, blockSize); + RSI_FIM_SetSatTruncRound(STRS(0x9, 0, 0, 0)); +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + RSI_FIM_InputData(pSrc, ULPSS_RAM_ADDR_SRC, blockSize, FORMAT_F32); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrc; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif +#else + // For 9116 + RSI_FIM_InputData(pSrc, inBank, blockSize, FORMAT_F32); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((NORM_SQUARE << 1) | 1); + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + *@fn rsi_error_t rsi_arm_mat_mult_q31_opt(const arm_matrix_instance_q31_opt *pSrcA, + * const arm_matrix_instance_q31_opt *pSrcB, + * arm_matrix_instance_q31_opt *pDst, + * uint16_t inBank1, + * uint16_t inBank2, + * uint16_t outBank) + *@brief This API is used to set the FIM Matrix Multiplication for real numbers + *@param[in] *pSrcA : points to the first input matrix structure + *@param[in] *pSrcB : points to the second input matrix structure + *@param[out] *pDst : points to output matrix structure + *@return none + */ + +rsi_error_t rsi_arm_mat_mult_f32_opt(const arm_matrix_instance_f32_opt *pSrcA, + const arm_matrix_instance_f32_opt *pSrcB, + arm_matrix_instance_f32_opt *pDst, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank) +{ + // Number of rows of input matrix A + uint16_t numRowsA = pSrcA->nRows; + // Number of columns of input matrix B + uint16_t numColsB = pSrcB->nColumns; + // Number of columns of input matrix A + uint16_t numColsA = pSrcA->nColumns; + if ((pSrcA != NULL) && (pSrcB != NULL)) { + if (pSrcA->nColumns == pSrcB->nRows) { + RSI_FIM_SetDataLen(numColsA, 0, 0); + RSI_FIM_SetSatTruncRound(STRS(0x9, 0, 0, 0)); +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + RSI_FIM_InputData((pSrcA->pData), ULPSS_RAM_ADDR_SRC1, ((pSrcA->nRows) * (pSrcA->nColumns)), FORMAT_Q31); + RSI_FIM_InputData((pSrcB->pData), ULPSS_RAM_ADDR_SRC2, ((pSrcB->nRows) * (pSrcB->nColumns)), FORMAT_Q31); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ((uint32_t)pSrcA->pData); + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ((uint32_t)pSrcB->pData); + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ((uint32_t)pDst->pData); +#endif +#else + // For 9116 + RSI_FIM_InputData((pSrcA->pData), inBank1, ((pSrcA->nRows) * (pSrcA->nColumns)), FORMAT_F32); + RSI_FIM_InputData((pSrcB->pData), inBank2, ((pSrcB->nRows) * (pSrcB->nColumns)), FORMAT_F32); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = inBank2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((MUL_MAT << 1) | 1); + RSI_FIM_DatTypTrig(numRowsA, numColsB, ULP_FIM_COP_DATA_REAL_REAL); + } else { + return ERROR_FIM_MATRIX_INVALID_ARG; + } + } + return RSI_OK; +} + +/*==============================================*/ +/** + *@fn rsi_error_t rsi_arm_mat_mult_q31_opt(const arm_matrix_instance_q31_opt *pSrcA, + * const arm_matrix_instance_q31_opt *pSrcB, + * arm_matrix_instance_q31_opt *pDst, + * uint16_t inBank1, + * uint16_t inBank2, + * uint16_t outBank) + *@brief This API is used to set the FIM Matrix Multiplication for real numbers + *@param[in] *pSrcA : points to the first input matrix structure + *@param[in] *pSrcB : points to the second input matrix structure + *@param[out] *pDst : points to output matrix structure + *@return none + */ +rsi_error_t rsi_arm_mat_mult_q31_opt(const arm_matrix_instance_q31_opt *pSrcA, + const arm_matrix_instance_q31_opt *pSrcB, + arm_matrix_instance_q31_opt *pDst, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank) +{ + // Number of rows of input matrix A + uint16_t numRowsA = pSrcA->nRows; + // Number of columns of input matrix B + uint16_t numColsB = pSrcB->nColumns; + // Number of columns of input matrix A + uint16_t numColsA = pSrcA->nColumns; + if ((pSrcA != NULL) && (pSrcB != NULL)) { + if (pSrcA->nColumns == pSrcB->nRows) { + RSI_FIM_SetDataLen(numColsA, 0, 0); + RSI_FIM_SetSatTruncRound(STRS(0x1, 0, 0, 0)); +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + RSI_FIM_InputData((pSrcA->pData), ULPSS_RAM_ADDR_SRC1, ((pSrcA->nRows) * (pSrcA->nColumns)), FORMAT_Q31); + RSI_FIM_InputData((pSrcB->pData), ULPSS_RAM_ADDR_SRC2, ((pSrcB->nRows) * (pSrcB->nColumns)), FORMAT_Q31); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ((uint32_t)pSrcA->pData); + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ((uint32_t)pSrcB->pData); + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ((uint32_t)pDst->pData); +#endif +#else + // For 9116 + RSI_FIM_InputData((pSrcA->pData), inBank1, ((pSrcA->nRows) * (pSrcA->nColumns)), FORMAT_Q31); + RSI_FIM_InputData((pSrcB->pData), inBank2, ((pSrcB->nRows) * (pSrcB->nColumns)), FORMAT_Q31); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = inBank2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((MUL_MAT << 1) | 1); + RSI_FIM_DatTypTrig(numRowsA, numColsB, ULP_FIM_COP_DATA_REAL_REAL); + } else { + return ERROR_FIM_MATRIX_INVALID_ARG; + } + } + return RSI_OK; +} + +/*==============================================*/ +/** + *@fn rsi_error_t rsi_arm_mat_mult_q15_opt(const arm_matrix_instance_q15_opt *pSrcA, + * const arm_matrix_instance_q15_opt *pSrcB, + * arm_matrix_instance_q15_opt *pDst, + * q15_t *pState, + * uint16_t inBank1, + * uint16_t inBank2, + * uint16_t outBank) + *@brief This API is used to set the FIM Matrix Multiplication for real numbers + *@param[in] *pSrcA : points to the first input matrix structure + *@param[in] *pSrcB : points to the second input matrix structure + *@param[out] *pDst : points to output matrix structure + *@param[in] *pState : points to the array for storing intermediate results (Unused) + *@return none + */ +rsi_error_t rsi_arm_mat_mult_q15_opt(const arm_matrix_instance_q15_opt *pSrcA, + const arm_matrix_instance_q15_opt *pSrcB, + arm_matrix_instance_q15_opt *pDst, + q15_t *pState, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank) +{ + // Number of rows of input matrix A + uint16_t numRowsA = pSrcA->nRows; + // Number of columns of input matrix B + uint16_t numColsB = pSrcB->nColumns; + // Number of columns of input matrix A + uint16_t numColsA = pSrcA->nColumns; + if ((pSrcA != NULL) && (pSrcB != NULL)) { + if (pSrcA->nColumns == pSrcB->nRows) { + RSI_FIM_SetDataLen(numColsA, 0, 0); + RSI_FIM_SetSatTruncRound(STRS(0x11, 0, 0, 0)); +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + RSI_FIM_InputData((pSrcA->pData), ULPSS_RAM_ADDR_SRC1, ((pSrcA->nRows) * (pSrcA->nColumns)), FORMAT_Q15); + RSI_FIM_InputData((pSrcB->pData), ULPSS_RAM_ADDR_SRC2, ((pSrcB->nRows) * (pSrcB->nColumns)), FORMAT_Q15); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ((uint32_t)pSrcA->pData); + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ((uint32_t)pSrcB->pData); + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ((uint32_t)pDst->pData); +#endif +#else + // For 9116 + RSI_FIM_InputData((pSrcA->pData), inBank1, ((pSrcA->nRows) * (pSrcA->nColumns)), FORMAT_Q15); + RSI_FIM_InputData((pSrcB->pData), inBank2, ((pSrcB->nRows) * (pSrcB->nColumns)), FORMAT_Q15); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = inBank2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + + FIM->FIM_MODE_INTERRUPT = ((MUL_MAT << 1) | 1); + RSI_FIM_DatTypTrig(numRowsA, numColsB, ULP_FIM_COP_DATA_REAL_REAL); + } else { + return ERROR_FIM_MATRIX_INVALID_ARG; + } + } + return RSI_OK; +} + +/*==============================================*/ +/** + *@fn void rsi_arm_fir_init_f32_opt(arm_fir_instance_f32_opt *S, + * uint16_t numTaps, + * int32_t *pCoeffs, + * int32_t *pState, + * uint32_t blockSize) + *@brief This API is used to initialize the FIM filters + *@param[in,out] *S : points to an instance of the floating-point FIR filter structure. + *@param[in] numTaps : Number of filter coefficients in the filter. + *@param[in] *pCoeffs : points to the filter coefficients buffer. + *@param[in] *pState : points to the state buffer. + *@param[in] blockSize : number of samples that are processed per call. + *@return none + */ +void rsi_arm_fir_init_f32_opt(arm_fir_instance_f32_opt *S, + uint16_t numTaps, + int32_t *pCoeffs, + int32_t *pState, + uint32_t blockSize) +{ + // Assign filter taps + S->numTaps = numTaps; + + // Assign coefficient pointer + S->pCoeffs = pCoeffs; + // Assign state pointer + S->pState = pState; +} + +/*==============================================*/ +/** + *@fn void rsi_arm_fir_f32_opt(arm_fir_instance_f32_opt *S, + * int32_t *pSrc, + * int32_t *pDst, + * uint32_t blockSize, + * uint16_t inBank1, + * uint16_t inBank2, + * uint16_t outBank) + *@brief This API is used to set the FIM FIR Filter + *@param[in] *S : points to an instance of the floating-point FIR filter structure. + *@param[in] *pSrc : points to the block of input data. + *@param[out] *pDst : points to the block of output data. + *@param[in] blockSize : number of samples to process per call. + *@return none + */ +void rsi_arm_fir_f32_opt(arm_fir_instance_f32_opt *S, + int32_t *pSrc, + int32_t *pDst, + uint32_t blockSize, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank) +{ + if (S->numTaps > blockSize) { + RSI_FIM_SetDataLen(blockSize, blockSize, (S->numTaps)); +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + RSI_FIM_InputData(pSrc, ULPSS_RAM_ADDR_SRC1, blockSize, FORMAT_F32); + RSI_FIM_InputData(S->pCoeffs, ULPSS_RAM_ADDR_SRC2, S->numTaps, FORMAT_F32); +#endif +#else + RSI_FIM_InputData(pSrc, inBank1, blockSize, FORMAT_F32); + RSI_FIM_InputData(S->pCoeffs, inBank2, S->numTaps, FORMAT_F32); +#endif + } else { + RSI_FIM_SetDataLen((S->numTaps), (S->numTaps), blockSize); +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + RSI_FIM_InputData(pSrc, ULPSS_RAM_ADDR_SRC2, blockSize, FORMAT_F32); + RSI_FIM_InputData(S->pCoeffs, ULPSS_RAM_ADDR_SRC1, S->numTaps, FORMAT_F32); +#endif +#else + RSI_FIM_InputData(pSrc, inBank2, blockSize, FORMAT_F32); + RSI_FIM_InputData(S->pCoeffs, inBank1, S->numTaps, FORMAT_F32); +#endif + } + RSI_FIM_SetSatTruncRound(STRS(0x9, 0, 0, 0)); +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrc; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = (uint32_t)S->pCoeffs; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif +#else + // For 9116 + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = inBank2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((FIR << 1) | 1); + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + *@fn void rsi_arm_fir_init_q31_opt(arm_fir_instance_q31_opt *S, + * uint16_t numTaps, + * q31_t *pCoeffs, + * q31_t *pState, + * uint32_t blockSize) + *@brief This API is used to initialize the FIM filters + *@param[in,out] *S : points to an instance of the Q31 FIR filter structure. + *@param[in] numTaps : Number of filter coefficients in the filter. + *@param[in] *pCoeffs : points to the filter coefficients buffer. + *@param[in] *pState : points to the state buffer. + *@param[in] blockSize : number of samples that are processed per call. + *@return none + */ + +void rsi_arm_fir_init_q31_opt(arm_fir_instance_q31_opt *S, + uint16_t numTaps, + q31_t *pCoeffs, + q31_t *pState, + uint32_t blockSize) +{ + // Assign filter taps + S->numTaps = numTaps; + // Assign coefficient pointer + S->pCoeffs = pCoeffs; + // Assign state pointer + S->pState = pState; +} + +/*==============================================*/ +/** + *@fn void rsi_arm_fir_q31_opt(arm_fir_instance_q31_opt *S, + * q31_t *pSrc, + * q31_t *pDst, + * uint32_t blockSize, + * uint16_t inBank1, + * uint16_t inBank2, + * uint16_t outBank) + *@brief This API is used to set the FIM FIR Filter + *@param[in] *S : points to an instance of the Q31 FIR filter structure. + *@param[in] *pSrc : points to the block of input data. + *@param[out] *pDst : points to the block of output data. + *@param[in] blockSize : number of samples to process per call + *@return none + */ +void rsi_arm_fir_q31_opt(arm_fir_instance_q31_opt *S, + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank) +{ + if (S->numTaps > blockSize) { + RSI_FIM_SetDataLen(blockSize, blockSize, (S->numTaps)); +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + RSI_FIM_InputData(pSrc, ULPSS_RAM_ADDR_SRC1, blockSize, FORMAT_Q31); + RSI_FIM_InputData(S->pCoeffs, ULPSS_RAM_ADDR_SRC2, S->numTaps, FORMAT_Q31); +#endif +#else + RSI_FIM_InputData(pSrc, inBank1, blockSize, FORMAT_Q31); + RSI_FIM_InputData(S->pCoeffs, inBank2, S->numTaps, FORMAT_Q31); +#endif + } else { + RSI_FIM_SetDataLen((S->numTaps), (S->numTaps), blockSize); +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + RSI_FIM_InputData(pSrc, ULPSS_RAM_ADDR_SRC2, blockSize, FORMAT_Q31); + RSI_FIM_InputData(S->pCoeffs, ULPSS_RAM_ADDR_SRC1, S->numTaps, FORMAT_Q31); +#endif +#else + RSI_FIM_InputData(pSrc, inBank2, blockSize, FORMAT_Q31); + RSI_FIM_InputData(S->pCoeffs, inBank1, S->numTaps, FORMAT_Q31); +#endif + } + RSI_FIM_SetSatTruncRound(STRS(0x1, 0, 0, 0)); +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrc; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = (uint32_t)S->pCoeffs; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif +#else + // For 9116 + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = inBank2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((FIR << 1) | 1); + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + *fn void rsi_arm_fir_init_q15_opt(arm_fir_instance_q15_opt *S, + * uint16_t numTaps, + * q15_t *pCoeffs, + * q15_t *pState, + * uint32_t blockSize) + *@brief This API is used to initialise the FIM filters + *@param[in,out] *S : points to an instance of the Q15 FIR filter structure. + *@param[in] numTaps : Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + *@param[in] *pCoeffs : points to the filter coefficients buffer. + *@param[in] *pState : points to the state buffer. + *@param[in] blockSize : is number of samples processed per call. + *@return none + * + */ +void rsi_arm_fir_init_q15_opt(arm_fir_instance_q15_opt *S, + uint16_t numTaps, + q15_t *pCoeffs, + q15_t *pState, + uint32_t blockSize) +{ + // Assign filter taps + S->numTaps = numTaps; + + // Assign coefficient pointer + S->pCoeffs = pCoeffs; + // Assign state pointer + S->pState = pState; +} + +/*==============================================*/ +/** + *@fn void rsi_arm_fir_q15_opt(arm_fir_instance_q15_opt *S, + * q15_t *pSrc, + * q15_t *pDst, + * uint32_t blockSize, + * uint16_t inBank1, + * uint16_t inBank2, + * uint16_t outBank) + *@brief This API is used to set the FIM FIR Filter + *@param[in] *S : points to an instance of the Q15 FIR structure. + *@param[in] *pSrc : points to the block of input data. + *@param[out] *pDst : points to the block of output data. + *@param[in] blockSize : number of samples to process per call. + *@return none + */ + +void rsi_arm_fir_q15_opt(arm_fir_instance_q15_opt *S, + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank) +{ + + if (S->numTaps > blockSize) { + RSI_FIM_SetDataLen(blockSize, blockSize, (S->numTaps)); +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + RSI_FIM_InputData(pSrc, ULPSS_RAM_ADDR_SRC1, blockSize, FORMAT_Q15); + RSI_FIM_InputData(S->pCoeffs, ULPSS_RAM_ADDR_SRC2, S->numTaps, FORMAT_Q15); +#endif +#else + RSI_FIM_InputData(pSrc, inBank1, blockSize, FORMAT_Q15); + RSI_FIM_InputData(S->pCoeffs, inBank2, S->numTaps, FORMAT_Q15); +#endif + } else { + RSI_FIM_SetDataLen((S->numTaps), (S->numTaps), blockSize); +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + RSI_FIM_InputData(pSrc, ULPSS_RAM_ADDR_SRC2, blockSize, FORMAT_Q15); + RSI_FIM_InputData(S->pCoeffs, ULPSS_RAM_ADDR_SRC1, S->numTaps, FORMAT_Q15); +#endif +#else + RSI_FIM_InputData(pSrc, inBank2, blockSize, FORMAT_Q15); + RSI_FIM_InputData(S->pCoeffs, inBank1, S->numTaps, FORMAT_Q15); +#endif + } + RSI_FIM_SetSatTruncRound(STRS(0x11, 0, 0, 0)); +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrc; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = (uint32_t)S->pCoeffs; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif +#else + // For 9116 + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = inBank2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((FIR << 1) | 1); + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + *@fn void rsi_arm_fir_init_q7_opt(arm_fir_instance_q7_opt *S, + * uint16_t numTaps, + * q7_t *pCoeffs, + * q7_t *pState, + * uint32_t blockSize) + *@brief This API is used to initialise the FIM filters + *@param[in,out] *S : points to an instance of the Q7 FIR filter structure. + *@param[in] numTaps : Number of filter coefficients in the filter. + *@param[in] *pCoeffs : points to the filter coefficients buffer. + *@param[in] *pState : points to the state buffer. + *@param[in] blockSize : number of samples that are processed per call. + *@return none + */ +void rsi_arm_fir_init_q7_opt(arm_fir_instance_q7_opt *S, + uint16_t numTaps, + q7_t *pCoeffs, + q7_t *pState, + uint32_t blockSize) +{ + // Assign filter taps + S->numTaps = numTaps; + // Assign coefficient pointer + S->pCoeffs = pCoeffs; + // Assign state pointer + S->pState = pState; +} + +/*==============================================*/ +/** + *@fn void rsi_arm_fir_q7_opt(arm_fir_instance_q7_opt *S, + * q7_t *pSrc, + * q7_t *pDst, + * uint32_t blockSize, + * uint16_t inBank1, + * uint16_t inBank2, + * uint16_t outBank) + *@brief This API is used to set the FIM FIR Filter + *@param[in] *S : points to an instance of the Q7 FIR filter structure. + *@param[in] *pSrc : points to the block of input data. + *@param[out] *pDst : points to the block of output data. + *@param[in] blockSize : number of samples to process per call. + *@return none + */ +void rsi_arm_fir_q7_opt(arm_fir_instance_q7_opt *S, + q7_t *pSrc, + q7_t *pDst, + uint32_t blockSize, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank) +{ + if (S->numTaps > blockSize) { + RSI_FIM_SetDataLen(blockSize, blockSize, (S->numTaps)); +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + RSI_FIM_InputData(pSrc, ULPSS_RAM_ADDR_SRC1, blockSize, FORMAT_Q7); + RSI_FIM_InputData(S->pCoeffs, ULPSS_RAM_ADDR_SRC2, S->numTaps, FORMAT_Q7); +#endif +#else + RSI_FIM_InputData(pSrc, inBank1, blockSize, FORMAT_Q7); + RSI_FIM_InputData(S->pCoeffs, inBank2, S->numTaps, FORMAT_Q7); +#endif + } else { + RSI_FIM_SetDataLen((S->numTaps), (S->numTaps), blockSize); +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + RSI_FIM_InputData(pSrc, ULPSS_RAM_ADDR_SRC2, blockSize, FORMAT_Q7); + RSI_FIM_InputData(S->pCoeffs, ULPSS_RAM_ADDR_SRC1, S->numTaps, FORMAT_Q7); +#endif +#else + RSI_FIM_InputData(pSrc, inBank2, blockSize, FORMAT_Q7); + RSI_FIM_InputData(S->pCoeffs, inBank1, S->numTaps, FORMAT_Q7); +#endif + } + RSI_FIM_SetSatTruncRound(STRS(0x19, 0, 0, 0)); +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrc; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = (uint32_t)S->pCoeffs; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif +#else + // For 9116 + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = inBank2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((FIR << 1) | 1); + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + *@fn arm_status rsi_arm_fir_interpolate_init_f32_opt(arm_fir_interpolate_instance_f32_opt *S, + * uint8_t L, + * uint16_t numTaps, + * int32_t *pCoeffs, + * int32_t *pState, + * uint32_t blockSize) + *@brief This API is used to initialization function for the floating-point FIR interpolator. + *@param[in,out] *S : points to an instance of the floating-point FIR interpolator structure. + *@param[in] L :upsample factor. + *@param[in] numTaps : number of filter coefficients in the filter. + *@param[in] *pCoeffs : points to the filter coefficient buffer. + *@param[in] *pState : points to the state buffer. + *@param[in] blockSize : number of input samples to process per call. + * + *@return The function returns \ref ARM_MATH_SUCCESS if initialization was successful or \ref ARM_MATH_LENGTH_ERROR if the filter length numTaps is not a multiple of the interpolation factor L. + */ +arm_status rsi_arm_fir_interpolate_init_f32_opt(arm_fir_interpolate_instance_f32_opt *S, + uint8_t L, + uint16_t numTaps, + int32_t *pCoeffs, + int32_t *pState, + uint32_t blockSize) +{ + arm_status status; + + // The filter length must be a multiple of the interpolation factor + if ((numTaps % L) != 0u) { + // Set status as ARM_MATH_LENGTH_ERROR + status = ARM_MATH_LENGTH_ERROR; + } else { + // Assign coefficient pointer + S->pCoeffs = pCoeffs; + // Assign Interpolation factor + S->L = L; + // Assign polyPhaseLength + S->phaseLength = numTaps / L; + // Assign state pointer + S->pState = pState; + status = ARM_MATH_SUCCESS; + } + return (status); +} + +/*==============================================*/ +/** + *@fn void rsi_arm_fir_interpolate_f32_opt(const arm_fir_interpolate_instance_f32_opt *S, + * int32_t *pSrc, + * int32_t *pDst, + * uint32_t blockSize, + * uint16_t inBank1, + * uint16_t inBank2, + * uint16_t outBank) + *@brief This API is used Processing function for the floating-point FIR interpolator. + *@param[in] *S : points to an instance of the floating-point FIR interpolator structure. + *@param[in] *pSrc : points to the block of input data. + *@param[out] *pDst : points to the block of output data. + *@param[in] blockSize : number of input samples to process per call. + *@return none + */ +void rsi_arm_fir_interpolate_f32_opt(const arm_fir_interpolate_instance_f32_opt *S, + int32_t *pSrc, + int32_t *pDst, + uint32_t blockSize, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank) +{ + + uint32_t numTaps; + numTaps = (S->phaseLength) * (S->L); + + RSI_FIM_SetDataLen(numTaps, blockSize, numTaps); + RSI_FIM_SetSatTruncRound(STRS(0x9, 0, 0, 0)); +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + RSI_FIM_InputData(pSrc, ULPSS_RAM_ADDR_SRC1, blockSize, FORMAT_F32); + RSI_FIM_InputData(S->pCoeffs, ULPSS_RAM_ADDR_SRC2, numTaps, FORMAT_F32); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrc; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = (uint32_t)S->pCoeffs; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif +#else + // For 9116 + RSI_FIM_InputData(pSrc, inBank1, blockSize, FORMAT_F32); + RSI_FIM_InputData(S->pCoeffs, inBank2, numTaps, FORMAT_F32); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = inBank2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_CONFIG_REG2 |= (S->L) << 22; + FIM->FIM_MODE_INTERRUPT = ((INTERPOLATE << 1) | 1); + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + *@fn arm_status rsi_arm_fir_interpolate_init_q15_opt(arm_fir_interpolate_instance_q15_opt *S, + * uint8_t L, + * uint16_t numTaps, + * q15_t *pCoeffs, + * q15_t *pState, + * uint32_t blockSize) + *@brief This API is used to initialization function for the Q31 FIR interpolator. + *@param[in,out] *S : points to an instance of the Q31 FIR interpolator structure. + *@param[in] L : upsample factor. + *@param[in] numTaps : number of filter coefficients in the filter. + *@param[in] *pCoeffs : points to the filter coefficient buffer. + *@param[in] *pState : points to the state buffer. + *@param[in] blockSize : number of input samples to process per call. + *@return The function returns \ref ARM_MATH_SUCCESS if initialization was successful or \ref ARM_MATH_LENGTH_ERROR if the filter length numTaps is not a multiple of the interpolation factor L. + * + */ +arm_status rsi_arm_fir_interpolate_init_q15_opt(arm_fir_interpolate_instance_q15_opt *S, + uint8_t L, + uint16_t numTaps, + q15_t *pCoeffs, + q15_t *pState, + uint32_t blockSize) +{ + arm_status status; + + // The filter length must be a multiple of the interpolation factor + if ((numTaps % L) != 0u) { + // Set status as ARM_MATH_LENGTH_ERROR + status = ARM_MATH_LENGTH_ERROR; + } else { + // Assign coefficient pointer + S->pCoeffs = pCoeffs; + + // Assign Interpolation factor + S->L = L; + + // Assign polyPhaseLength + S->phaseLength = numTaps / L; + + // Assign state pointer + S->pState = pState; + status = ARM_MATH_SUCCESS; + } + return (status); +} + +/*==============================================*/ +/** + *@fn void rsi_arm_fir_interpolate_q15_opt(arm_fir_interpolate_instance_q15_opt *S, + * q15_t *pSrc, + * q15_t *pDst, + * uint32_t blockSize, + * uint16_t inBank1, + * uint16_t inBank2, + * uint16_t outBank) + *@brief This API is used to Processing function for the Q15 FIR interpolator + *@param[in] *S : points to an instance of the Q15 FIR interpolator structure. + *@param[in] *pSrc : points to the block of input data. + *@param[out] *pDst : points to the block of output data. + *@param[in] blockSize : number of input samples to process per call. + *@return none + */ +void rsi_arm_fir_interpolate_q15_opt(arm_fir_interpolate_instance_q15_opt *S, + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank) +{ + + uint32_t numTaps; + numTaps = (S->phaseLength) * (S->L); + + RSI_FIM_SetDataLen(numTaps, blockSize, numTaps); + RSI_FIM_SetSatTruncRound(STRS(0x11, 0, 0, 0)); +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + RSI_FIM_InputData(pSrc, ULPSS_RAM_ADDR_SRC1, blockSize, FORMAT_Q15); + RSI_FIM_InputData(S->pCoeffs, ULPSS_RAM_ADDR_SRC2, numTaps, FORMAT_Q15); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrc; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = (uint32_t)S->pCoeffs; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif +#else + // For 9116 + RSI_FIM_InputData(pSrc, inBank1, blockSize, FORMAT_Q15); + RSI_FIM_InputData(S->pCoeffs, inBank2, numTaps, FORMAT_Q15); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = inBank2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((INTERPOLATE << 1) | 1); + FIM->FIM_CONFIG_REG2 |= (S->L) << 22; + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + *@fn arm_status rsi_arm_fir_interpolate_init_q31_opt(arm_fir_interpolate_instance_q31_opt *S, + * uint8_t L, + * uint16_t numTaps, + * q31_t *pCoeffs, + * q31_t *pState, + * uint32_t blockSize) + *@brief This API is used to initialization function for the Q31 FIR interpolator. + *@param[in,out] *S : points to an instance of the Q31 FIR interpolator structure. + *@param[in] L : upsample factor. + *@param[in] numTaps : number of filter coefficients in the filter. + *@param[in] *pCoeffs : points to the filter coefficient buffer. + *@param[in] *pState : points to the state buffer. + *@param[in] blockSize : number of input samples to process per call. + *@return The function returns \ref ARM_MATH_SUCCESS if initialization was successful or \ref ARM_MATH_LENGTH_ERROR if the filter length numTaps is not a multiple of the interpolation factor L. + * + */ +arm_status rsi_arm_fir_interpolate_init_q31_opt(arm_fir_interpolate_instance_q31_opt *S, + uint8_t L, + uint16_t numTaps, + q31_t *pCoeffs, + q31_t *pState, + uint32_t blockSize) +{ + arm_status status; + // The filter length must be a multiple of the interpolation factor + if ((numTaps % L) != 0u) { + // Set status as ARM_MATH_LENGTH_ERROR + status = ARM_MATH_LENGTH_ERROR; + } else { + // Assign coefficient pointer + S->pCoeffs = pCoeffs; + + // Assign Interpolation factor + S->L = L; + + // Assign polyPhaseLength + S->phaseLength = numTaps / L; + + // Assign state pointer + S->pState = pState; + + status = ARM_MATH_SUCCESS; + } + + return (status); +} + +/*==============================================*/ +/** + *@fn rsi_arm_fir_interpolate_q31_opt(const arm_fir_interpolate_instance_q31_opt *S, + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank) + *@brief This API is used for Q31 FIR interpolator. + *@param[in,out] *S : points to an instance of the Q31 FIR interpolator structure. + *@param[in] *pSrc : Source Pointer. + *@param[in] *pDst : Destination pointer + *@param[in] blockSize : number of input samples to process per call + *@param[in] inBank1 + *@param[in] inBank2 + *@param[in] outBank + *@return None + * + */ +void rsi_arm_fir_interpolate_q31_opt(const arm_fir_interpolate_instance_q31_opt *S, + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize, + uint16_t inBank1, + uint16_t inBank2, + uint16_t outBank) +{ + uint32_t numTaps; + numTaps = (S->phaseLength) * (S->L); + + RSI_FIM_SetDataLen(numTaps, blockSize, numTaps); + RSI_FIM_SetSatTruncRound(STRS(0x1, 0, 0, 0)); +#ifdef ENHANCED_FIM +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + RSI_FIM_InputData(pSrc, ULPSS_RAM_ADDR_SRC1, blockSize, FORMAT_Q31); + RSI_FIM_InputData(S->pCoeffs, ULPSS_RAM_ADDR_SRC2, numTaps, FORMAT_Q31); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrc; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = (uint32_t)S->pCoeffs; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif +#else + // For 9116 + RSI_FIM_InputData(pSrc, inBank1, blockSize, FORMAT_Q31); + RSI_FIM_InputData(S->pCoeffs, inBank2, numTaps, FORMAT_Q31); + FIM->FIM_INP1_ADDR_b.INP1_ADDR = inBank1; + FIM->FIM_INP2_ADDR_b.INP2_ADDR = inBank2; + FIM->FIM_OUT_ADDR_b.OUT_ADDR = outBank; +#endif + FIM->FIM_MODE_INTERRUPT = ((INTERPOLATE << 1) | 1); + FIM->FIM_CONFIG_REG2 |= (S->L) << 22; + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + *@fn void rsi_fim_interrupt_handler(volatile FIM_Type *ptFim) + *@brief This API Clears interrupt status of fim + *@param[in] ptFim is pointer to the FIM register instance + *@return none + */ +void rsi_fim_interrupt_handler(volatile FIM_Type *ptFim) +{ + ptFim->FIM_MODE_INTERRUPT_b.INTR_CLEAR = 0x1; +} + +#ifdef ENHANCED_FIM + +/*==============================================*/ +/** + * @fn void rsi_arm_correlate_q15(const q15_t *pSrcA, uint32_t srcALen, const q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst) + * @brief This API is used to set FIM Correlation Operation of Q15 sequence. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ +void rsi_arm_correlate_q15(const q15_t *pSrcA, uint32_t srcALen, const q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst) +{ + // Set data blockSize of buffers in the FIM module + RSI_FIM_SetDataLen(NOT_MATRIX, srcALen, srcBLen); + // Set saturation,trunc values to FIM module for corresponding inputs + RSI_FIM_SetSatTruncRound(STRS(0x01, 0, 0, 0)); +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + // Store Input data1 in ulp memories + RSI_FIM_InputData((void *)pSrcA, ULPSS_RAM_ADDR_SRC1, srcALen, FORMAT_Q15); + // Store Input data2 in ulp memories + RSI_FIM_InputData((void *)pSrcB, ULPSS_RAM_ADDR_SRC2, srcBLen, FORMAT_Q15); + // Start Address of 1st Input Data for FIM Operations + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + // Start Address of 2nd Input Data for FIM Operations + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + // Start Address of 1st Input Data for FIM Operations + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrcA; + // Start Address of 2nd Input Data for FIM Operations + FIM->FIM_INP2_ADDR_b.INP2_ADDR = (uint32_t)pSrcB; + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif + // Set the Mode of Operation to be performed.Enable latch mode + FIM->FIM_MODE_INTERRUPT = ((CORRELATION << 1) | 1); + // Set the data type and Trigger the FIM module + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + * @fn void rsi_arm_correlate_q31(const q31_t *pSrcA, uint32_t srcALen, const q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst) + * @brief This API is used to set FIM Correlation Operation of Q31 sequence. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ +void rsi_arm_correlate_q31(const q31_t *pSrcA, uint32_t srcALen, const q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst) +{ + // Set data blockSize of buffers in the FIM module + RSI_FIM_SetDataLen(NOT_MATRIX, srcALen, srcBLen); + // Set saturation,trunc values to FIM module for corresponding inputs + RSI_FIM_SetSatTruncRound(STRS(0x01, 0, 0, 0)); +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + // Store Input data1 in ulp memories + RSI_FIM_InputData((void *)pSrcA, ULPSS_RAM_ADDR_SRC1, srcALen, FORMAT_Q31); + // Store Input data1 in ulp memories + RSI_FIM_InputData((void *)pSrcB, ULPSS_RAM_ADDR_SRC2, srcBLen, FORMAT_Q31); + // Start Address of 1st Input Data for FIM Operations + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + // Start Address of 2nd Input Data for FIM Operations + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + // Start Address of 1st Input Data for FIM Operations + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrcA; + // Start Address of 2nd Input Data for FIM Operations + FIM->FIM_INP2_ADDR_b.INP2_ADDR = (uint32_t)pSrcB; + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif + // Set the Mode of Operation to be performed.Enable latch mode + FIM->FIM_MODE_INTERRUPT = ((CORRELATION << 1) | 1); + // Set the data type and Trigger the FIM module + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + * @fn void rsi_arm_correlate_q7(const q7_t *pSrcA, uint32_t srcALen, const q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst) + * @brief This API is used to set FIM Correlation Operation of Q7 sequence. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ +void rsi_arm_correlate_q7(const q7_t *pSrcA, uint32_t srcALen, const q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst) +{ + // Set data blockSize of buffers in the FIM module + RSI_FIM_SetDataLen(NOT_MATRIX, srcALen, srcBLen); + // Set saturation,trunc values to FIM module for corresponding inputs + RSI_FIM_SetSatTruncRound(STRS(0x01, 0, 0, 0)); +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + // Store Input data1 in ulp memories + RSI_FIM_InputData((void *)pSrcA, ULPSS_RAM_ADDR_SRC1, srcALen, FORMAT_Q7); + // Store Input data2 in ulp memories + RSI_FIM_InputData((void *)pSrcB, ULPSS_RAM_ADDR_SRC2, srcBLen, FORMAT_Q7); + // Start Address of 1st Input Data for FIM Operations + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + // Start Address of 2nd Input Data for FIM Operations + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + // Start Address of 1st Input Data for FIM Operations + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrcA; + // Start Address of 2nd Input Data for FIM Operations + FIM->FIM_INP2_ADDR_b.INP2_ADDR = (uint32_t)pSrcB; + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif + // Set the Mode of Operation to be performed.Enable latch mode + FIM->FIM_MODE_INTERRUPT = ((CORRELATION << 1) | 1); + // Set the data type and Trigger the FIM module + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + * @fn arm_status arm_fir_decimate_init_q31(arm_fir_decimate_instance_q31 *S, + * uint16_t numTaps, + * uint8_t M, + * q31_t *pCoeffs, + * q31_t *pState, + * uint32_t blockSize) + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ +arm_status arm_fir_decimate_init_q31(arm_fir_decimate_instance_q31 *S, + uint16_t numTaps, + uint8_t M, + q31_t *pCoeffs, + q31_t *pState, + uint32_t blockSize) +{ + arm_status status; + + // The size of the input block must be a multiple of the decimation factor + if ((blockSize % M) != 0u) { + // Set status as ARM_MATH_LENGTH_ERROR + status = ARM_MATH_LENGTH_ERROR; + } else { + // Assign filter taps + S->numTaps = numTaps; + + // Assign coefficient pointer + S->pCoeffs = pCoeffs; + + // Clear the state buffer. The size is always (blockSize + numTaps - 1) + memset(pState, 0, (numTaps + (blockSize - 1)) * sizeof(q31_t)); + + // Assign state pointer + S->pState = pState; + + // Assign Decimation factor + S->M = M; + + status = ARM_MATH_SUCCESS; + } + return (status); +} + +/*==============================================*/ +/** + * @fn arm_status arm_fir_decimate_init_q15(arm_fir_decimate_instance_q15 *S, + * uint16_t numTaps, + * uint8_t M, + * q15_t *pCoeffs, + * q15_t *pState, + * uint32_t blockSize) + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ +arm_status arm_fir_decimate_init_q15(arm_fir_decimate_instance_q15 *S, + uint16_t numTaps, + uint8_t M, + q15_t *pCoeffs, + q15_t *pState, + uint32_t blockSize) +{ + + arm_status status; + + // The size of the input block must be a multiple of the decimation factor + if ((blockSize % M) != 0u) { + // Set status as ARM_MATH_LENGTH_ERROR + status = ARM_MATH_LENGTH_ERROR; + } else { + // Assign filter taps + S->numTaps = numTaps; + + // Assign coefficient pointer + S->pCoeffs = pCoeffs; + + // Clear the state buffer. The size of buffer is always (blockSize + numTaps - 1) + memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t)); + + // Assign state pointer + S->pState = pState; + + // Assign Decimation factor + S->M = M; + + status = ARM_MATH_SUCCESS; + } + return (status); +} + +/*==============================================*/ +/** + * @fn void arm_fir_decimate_q15(const arm_fir_decimate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize) + * @brief Processing function for the Q15 FIR decimator. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the location where the output result is written. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ +void arm_fir_decimate_q15(const arm_fir_decimate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize) +{ + uint32_t numTaps; + numTaps = (S->numTaps); + // Set data blockSize of buffers in the FIM module + RSI_FIM_SetDataLen(NOT_MATRIX, blockSize, numTaps); + // Set sat trunc values to FIM module for corresponding inputs + RSI_FIM_SetSatTruncRound(STRS(0x1, 0, 0, 0)); +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + RSI_FIM_InputData(pSrc, ULPSS_RAM_ADDR_SRC1, blockSize, FORMAT_Q15); + RSI_FIM_InputData((void *)S->pCoeffs, ULPSS_RAM_ADDR_SRC2, numTaps, FORMAT_Q15); + // Start Address of 1st Input Data for FIM Operations + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + // Start Address of 2nd Input Data for FIM Operations + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + // Start Address of 1st Input Data for FIM Operations + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrc; + // Start Address of 1st coefficient for FIM Operations + FIM->FIM_INP2_ADDR_b.INP2_ADDR = (uint32_t)S->pCoeffs; + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif + // Set the Mode of Operation to be performed. + FIM->FIM_MODE_INTERRUPT = ((DECIMATION << 1) | 1); + /* Set Decimation Factor */ + FIM->FIM_CONFIG_REG1_b.DECIM_FAC = S->M; + // Set the data type and Trigger the FIM module + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + * @fn void arm_fir_decimate_q31(const arm_fir_decimate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize) + * @brief Processing function for the Q31 FIR decimator. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ +void arm_fir_decimate_q31(const arm_fir_decimate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize) +{ + uint32_t numTaps; + numTaps = (S->numTaps); + // Set data blockSize of buffers in the FIM module + RSI_FIM_SetDataLen(NOT_MATRIX, blockSize, numTaps); + // Set sat trunc values to FIM module for corresponding inputs + RSI_FIM_SetSatTruncRound(STRS(0x1, 0, 0, 0)); +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + // Store data in ulp memories + RSI_FIM_InputData(pSrc, ULPSS_RAM_ADDR_SRC1, blockSize, FORMAT_Q31); + /* Store pCoeffs in ulp memories */ + RSI_FIM_InputData((void *)S->pCoeffs, ULPSS_RAM_ADDR_SRC2, numTaps, FORMAT_Q31); + // Start Address of 1st Input Data for FIM Operations + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + // Start Address of 1st coefficients for FIM Operations + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + // Start Address of 1st Input Data for FIM Operations + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrc; + // Start Address of 1st coefficients for FIM Operations + FIM->FIM_INP2_ADDR_b.INP2_ADDR = (uint32_t)S->pCoeffs; + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif + // Set the Mode of Operation to be performed. + FIM->FIM_MODE_INTERRUPT = ((DECIMATION << 1) | 1); + // Set Decimation Factor + FIM->FIM_CONFIG_REG1_b.DECIM_FAC = S->M; + // Set the data type and Trigger the FIM module + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** +* @details +* @fn void rsi_arm_cfft_radix2(q31_t *pSrc) +* @brief Processing function for complex FFT. +* @param[in] *S points to an instance of the CFFT structure. +* @param[in, out] *pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place. +* @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. +* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. +* @return none. +*/ +void rsi_arm_cfft_radix2(q31_t *pSrc) +{ + uint32_t i = 0; + q31_t pSrc_even[LOOKUP_LENGTH]; + q31_t pSrc_odd[LOOKUP_LENGTH]; + uint32_t pSrc_even_len = LOOKUP_LENGTH; +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + uint32_t pSrc_odd_len = LOOKUP_LENGTH; +#endif + // Set data blockSize of buffers in the FIM module + RSI_FIM_SetDataLen(NOT_MATRIX, FFT_LENGTH, NO_OF_STAGES); + // Set sat trunc values to FIM module for corresponding inputs + RSI_FIM_SetSatTruncRound(STRS(0x1, 0, 0, 0)); + for (i = 0; i < pSrc_even_len; i++) { + pSrc_even[i] = (pSrc[LOOKUP_TABLE_EVEN_BANK[i]]); + pSrc_odd[i] = (pSrc[LOOKUP_TABLE_ODD_BANK[i]]); + } +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + // Store even address data in ulp memories + RSI_FIM_InputData(pSrc_even, ULPSS_RAM_ADDR_SRC1, pSrc_even_len, FORMAT_Q31); + // Store odd address data in ulp memories + RSI_FIM_InputData((void *)pSrc_odd, ULPSS_RAM_ADDR_SRC2, pSrc_odd_len, FORMAT_Q31); + // Twiddle factor + RSI_FIM_InputData((void *)TWIDDLE_FACTOR_TABLE, ULPSS_RAM_ADDR_DST, TWIDDLE_FACTOR_LEN, FORMAT_Q31); + // Start Address of even address Input Data for FIM Operations + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + // Start Address of odd address for FIM Operations + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + // Start Address of twiddle factor Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; //twiddle +#endif + // Set the Mode of Operation to be performed. + FIM->FIM_MODE_INTERRUPT = ((FFT << 1) | 1); + // Set the data type and Trigger the FIM module + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_CPLX_CPLX); +} + +/*==============================================*/ +/** + * @fn void rsi_arm_sin_q15(q15_t *pSrc, q15_t *pDst, uint32_t blocksize) + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] *pSrc Scaled input value in radians. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ +void rsi_arm_sin_q15(q15_t *pSrc, q15_t *pDst, uint32_t blocksize) +{ + // Set data blockSize of buffers in the FIM module + RSI_FIM_SetDataLen(NOT_MATRIX, blocksize, TRIG_LUT_LEN); + // Set sat trunc values to FIM module for corresponding inputs + RSI_FIM_SetSatTruncRound(STRS(0x1F, 0, 0, 0)); +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + // Store data in ulp memories + RSI_FIM_InputData(pSrc, ULPSS_RAM_ADDR_SRC1, blocksize, FORMAT_Q15); + // Store data in ulp memories + RSI_FIM_InputData(Trig_lut1, ULPSS_RAM_ADDR_SRC2, TRIG_LUT_LEN, FORMAT_Q15); + // Start Address of 1st Input Data for FIM Operations + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + // Start Address of lookup table Data for FIM Operations + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + // Start Address of 1st Input Data for FIM Operations + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrc; + // Start Address of lookup table Data for FIM Operations + FIM->FIM_INP2_ADDR_b.INP2_ADDR = (uint32_t)Trig_lut1; + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; + +#endif + // Set the Mode of Operation to be performed. + FIM->FIM_MODE_INTERRUPT = ((COR_SINE << 1) | 1); + // Set the data type and Trigger the FIM module + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + * @fn void rsi_arm_cos_q15(q15_t *pSrc, q15_t *pDst, uint32_t blocksize) + * @brief Fast approximation to the trigonometric Cosine function for Q15 data. + * @param[in] *pSrc Scaled input value in radians. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ +void rsi_arm_cos_q15(q15_t *pSrc, q15_t *pDst, uint32_t blocksize) +{ + // Set data blockSize of buffers in the FIM module + RSI_FIM_SetDataLen(NOT_MATRIX, blocksize, TRIG_LUT_LEN); + // Set sat trunc values to FIM module for corresponding inputs + RSI_FIM_SetSatTruncRound(STRS(0x1F, 0, 0, 0)); +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + // Store data in ulp memories + RSI_FIM_InputData(pSrc, ULPSS_RAM_ADDR_SRC1, blocksize, FORMAT_Q15); + // Store data in ulp memories + RSI_FIM_InputData(Trig_lut1, ULPSS_RAM_ADDR_SRC2, TRIG_LUT_LEN, FORMAT_Q15); + // Start Address of 1st Input Data for FIM Operations + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + // Start Address of lookup table Data for FIM Operations + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + // Start Address of 1st Input Data for FIM Operations + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrc; + // Start Address of lookup table Data for FIM Operations + FIM->FIM_INP2_ADDR_b.INP2_ADDR = (uint32_t)Trig_lut1; + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif + // Set the Mode of Operation to be performed. + FIM->FIM_MODE_INTERRUPT = ((COR_COSINE << 1) | 1); + // Set the data type and Trigger the FIM module + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + * @fn void rsi_arm_Inverse_Tan_q15(q15_t *pSrc, q15_t *pDst, uint32_t blocksize) + * @brief Fast approximation to the trigonometric Inverse Tan function for Q15 data. + * @param[in] *pSrc Scaled input value in radians. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ +void rsi_arm_Inverse_Tan_q15(q15_t *pSrc, q15_t *pDst, uint32_t blocksize) +{ + // Set data blockSize of buffers in the FIM module + RSI_FIM_SetDataLen(NOT_MATRIX, blocksize, TRIG_LUT_LEN); + // Set sat trunc values to FIM module for corresponding inputs + RSI_FIM_SetSatTruncRound(STRS(0x1F, 0, 0, 0)); +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + // Store data in ulp memories + RSI_FIM_InputData(pSrc, ULPSS_RAM_ADDR_SRC1, blocksize, FORMAT_Q15); + // Store data in ulp memories + RSI_FIM_InputData(Trig_lut1, ULPSS_RAM_ADDR_SRC2, TRIG_LUT_LEN, FORMAT_Q15); + // Start Address of 1st Input Data for FIM Operations + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + // Start Address of lookup table Data for FIM Operations + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + // Start Address of 1st Input Data for FIM Operations + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrc; + // Start Address of lookup table Data for FIM Operations + FIM->FIM_INP2_ADDR_b.INP2_ADDR = (uint32_t)Trig_lut1; + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif + // Set the Mode of Operation to be performed. + FIM->FIM_MODE_INTERRUPT = ((COR_INV_TAN << 1) | 1); + // Set the data type and Trigger the FIM module + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + * @fn void rsi_arm_Sinh_q15(q15_t *pSrc, q15_t *pDst, uint32_t blocksize) + * @brief Fast approximation to the trigonometric Sinh function for Q15 data. + * @param[in] *pSrc Scaled input value in radians. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ +void rsi_arm_Sinh_q15(q15_t *pSrc, q15_t *pDst, uint32_t blocksize) +{ + // Set data blockSize of buffers in the FIM module + RSI_FIM_SetDataLen(NOT_MATRIX, blocksize, TRIG_LUT_LEN); + // Set sat trunc values to FIM module for corresponding inputs + RSI_FIM_SetSatTruncRound(STRS(0x1F, 0, 0, 0)); +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + // Store data in ulp memories + RSI_FIM_InputData(pSrc, ULPSS_RAM_ADDR_SRC1, blocksize, FORMAT_Q15); + // Store data in ulp memories + RSI_FIM_InputData(Trig_lut2, ULPSS_RAM_ADDR_SRC2, TRIG_LUT_LEN, FORMAT_Q15); + // Start Address of 1st Input Data for FIM Operations + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + // Start Address of lookup table Data for FIM Operations + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + // Start Address of 1st Input Data for FIM Operations + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrc; + // Start Address of lookup table Data for FIM Operations + FIM->FIM_INP2_ADDR_b.INP2_ADDR = (uint32_t)Trig_lut2; + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; + +#endif + // Set the Mode of Operation to be performed. + FIM->FIM_MODE_INTERRUPT = ((COR_SINH << 1) | 1); + // Set the data type and Trigger the FIM module + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + * @fn void rsi_arm_cosh_q15(q15_t *pSrc, q15_t *pDst, uint32_t blocksize) + * @brief Fast approximation to the trigonometric cosh function for Q15 data. + * @param[in] *pSrc Scaled input value in radians. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ +void rsi_arm_cosh_q15(q15_t *pSrc, q15_t *pDst, uint32_t blocksize) +{ + // Set data blockSize of buffers in the FIM module + RSI_FIM_SetDataLen(NOT_MATRIX, blocksize, TRIG_LUT_LEN); + // Set sat trunc values to FIM module for corresponding inputs + RSI_FIM_SetSatTruncRound(STRS(0x1F, 0, 0, 0)); +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + // Store data in ulp memories + RSI_FIM_InputData(pSrc, ULPSS_RAM_ADDR_SRC1, blocksize, FORMAT_Q15); + // Store data in ulp memories + RSI_FIM_InputData(Trig_lut2, ULPSS_RAM_ADDR_SRC2, TRIG_LUT_LEN, FORMAT_Q15); + // Start Address of 1st Input Data for FIM Operations + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + // Start Address of lookup table Data for FIM Operations + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + // Start Address of 1st Input Data for FIM Operations + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrc; + // Start Address of lookup table Data for FIM Operations + FIM->FIM_INP2_ADDR_b.INP2_ADDR = (uint32_t)Trig_lut2; + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif + // Set the Mode of Operation to be performed. + FIM->FIM_MODE_INTERRUPT = ((COR_COSH << 1) | 1); + // Set the data type and Trigger the FIM module + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + * @fn void rsi_arm_Inverse_Tanh_q15(q15_t *pSrc, q15_t *pDst, uint32_t blocksize) + * @brief Fast approximation to the trigonometric Inverse Tanh function for Q15 data. + * @param[in] *pSrc Scaled input value in radians. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ +void rsi_arm_Inverse_Tanh_q15(q15_t *pSrc, q15_t *pDst, uint32_t blocksize) +{ + // Set data blockSize of buffers in the FIM module + RSI_FIM_SetDataLen(NOT_MATRIX, blocksize, TRIG_LUT_LEN); + // Set sat trunc values to FIM module for corresponding inputs + RSI_FIM_SetSatTruncRound(STRS(0x1F, 0, 0, 0)); +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + // Store data in ulp memories + RSI_FIM_InputData(pSrc, ULPSS_RAM_ADDR_SRC1, blocksize, FORMAT_Q15); + // Store data in ulp memories + RSI_FIM_InputData(Trig_lut2, ULPSS_RAM_ADDR_SRC2, TRIG_LUT_LEN, FORMAT_Q15); + // Start Address of 1st Input Data for FIM Operations + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + // Start Address of lookup table Data for FIM Operations + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + // Start Address of 1st Input Data for FIM Operations + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrc; + // Start Address of lookup table Data for FIM Operations + FIM->FIM_INP2_ADDR_b.INP2_ADDR = (uint32_t)Trig_lut2; + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif + // Set the Mode of Operation to be performed. + FIM->FIM_MODE_INTERRUPT = ((COR_INV_TANH << 1) | 1); + // Set the data type and Trigger the FIM module + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + * @fn rsi_error_t rsi_arm_mat_add_q15(const arm_matrix_instance_q15_opt *pSrcA, + const arm_matrix_instance_q15_opt *pSrcB, + arm_matrix_instance_q15_opt *pDst) + * @brief Q15 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ERROR_FIM_MATRIX_INVALID_ARG or RSI_OK based on the outcome of size checking. + * + */ +rsi_error_t rsi_arm_mat_add_q15(const arm_matrix_instance_q15_opt *pSrcA, + const arm_matrix_instance_q15_opt *pSrcB, + arm_matrix_instance_q15_opt *pDst) +{ + + // Number of rows of input matrix A + uint16_t numRowsA = pSrcA->nRows; + // Number of columns of input matrix B + uint16_t numColsB = pSrcB->nColumns; + // Number of columns of input matrix A + uint16_t numColsA = pSrcA->nColumns; + if ((pSrcA != NULL) && (pSrcB != NULL)) { + if ((pSrcA->nColumns == pSrcB->nColumns) && (pSrcA->nRows == pSrcB->nRows)) { + /* Set column size of buffers in the FIM module */ + RSI_FIM_SetDataLen(numColsA, 0, 0); + // Set sat trunc values to FIM module for corresponding inputs + RSI_FIM_SetSatTruncRound(STRS(0x1F, 0, 0, 0)); +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + // Store data in ulp memories + RSI_FIM_InputData((pSrcA->pData), ULPSS_RAM_ADDR_SRC1, ((pSrcA->nRows) * (pSrcA->nColumns)), FORMAT_Q15); + // Store data in ulp memories + RSI_FIM_InputData((pSrcB->pData), ULPSS_RAM_ADDR_SRC2, ((pSrcB->nRows) * (pSrcB->nColumns)), FORMAT_Q15); + // Start Address of 1st Input Data for FIM Operations + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + // Start Address of 2nd Input Data for FIM Operations + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + // Start Address of 1st Input Data for FIM Operations + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ((uint32_t)pSrcA->pData); + // Start Address of 2nd Input Data for FIM Operations + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ((uint32_t)pSrcB->pData); + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ((uint32_t)pDst->pData); +#endif + // Set the Mode of Operation to be performed. + FIM->FIM_MODE_INTERRUPT = ((ADD_MAT << 1) | 1); + // Set the data type and Trigger the FIM module + RSI_FIM_DatTypTrig(numRowsA, numColsB, ULP_FIM_COP_DATA_REAL_REAL); + } else { + return ERROR_FIM_MATRIX_INVALID_ARG; + } + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t arm_mat_add_q31(const arm_matrix_instance_q31_opt *pSrcA, + const arm_matrix_instance_q31_opt *pSrcB, + arm_matrix_instance_q31_opt *pDst) + * @brief Q31 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ERROR_FIM_MATRIX_INVALID_ARG or RSI_OK based on the outcome of size checking. + */ +rsi_error_t arm_mat_add_q31(const arm_matrix_instance_q31_opt *pSrcA, + const arm_matrix_instance_q31_opt *pSrcB, + arm_matrix_instance_q31_opt *pDst) +{ + + // Number of rows of input matrix A + uint16_t numRowsA = pSrcA->nRows; + // Number of columns of input matrix B + uint16_t numColsB = pSrcB->nColumns; + // Number of columns of input matrix A + uint16_t numColsA = pSrcA->nColumns; + if ((pSrcA != NULL) && (pSrcB != NULL)) { + if ((pSrcA->nColumns == pSrcB->nColumns) && (pSrcA->nRows == pSrcB->nRows)) { + /* Set column size of buffers in the FIM module */ + RSI_FIM_SetDataLen(numColsA, 0, 0); + // Set sat trunc values to FIM module for corresponding inputs + RSI_FIM_SetSatTruncRound(STRS(0x11, 0, 0, 0)); +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + // Store data in ulp memories + RSI_FIM_InputData((pSrcA->pData), ULPSS_RAM_ADDR_SRC1, ((pSrcA->nRows) * (pSrcA->nColumns)), FORMAT_Q31); + // Store data in ulp memories + RSI_FIM_InputData((pSrcB->pData), ULPSS_RAM_ADDR_SRC2, ((pSrcB->nRows) * (pSrcB->nColumns)), FORMAT_Q31); + // Start Address of 1st Input Data for FIM Operations + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + // Start Address of 2nd Input Data for FIM Operations + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + // Start Address of 1st Input Data for FIM Operations + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ((uint32_t)pSrcA->pData); + // Start Address of 2nd Input Data for FIM Operations + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ((uint32_t)pSrcB->pData); + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ((uint32_t)pDst->pData); +#endif + + // Set the Mode of Operation to be performed. + FIM->FIM_MODE_INTERRUPT = ((ADD_MAT << 1) | 1); + // Set the data type and Trigger the FIM module + RSI_FIM_DatTypTrig(numRowsA, numColsB, ULP_FIM_COP_DATA_REAL_REAL); + } else { + return ERROR_FIM_MATRIX_INVALID_ARG; + } + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t arm_mat_sub_q15(const arm_matrix_instance_q15_opt *pSrcA, + const arm_matrix_instance_q15_opt *pSrcB, + arm_matrix_instance_q15_opt *pDst) + * @brief Q15 matrix subtraction. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ERROR_FIM_MATRIX_INVALID_ARG or RSI_OK based on the outcome of size checking. + */ +rsi_error_t arm_mat_sub_q15(const arm_matrix_instance_q15_opt *pSrcA, + const arm_matrix_instance_q15_opt *pSrcB, + arm_matrix_instance_q15_opt *pDst) +{ + // Number of rows of input matrix A + uint16_t numRowsA = pSrcA->nRows; + // Number of columns of input matrix B + uint16_t numColsB = pSrcB->nColumns; + // Number of columns of input matrix A + uint16_t numColsA = pSrcA->nColumns; + if ((pSrcA != NULL) && (pSrcB != NULL)) { + if ((pSrcA->nColumns == pSrcB->nColumns) && (pSrcA->nRows == pSrcB->nRows)) { + /* Set column size of buffers in the FIM module */ + RSI_FIM_SetDataLen(numColsA, 0, 0); + // Set sat trunc values to FIM module for corresponding inputs + RSI_FIM_SetSatTruncRound(STRS(0x11, 0, 0, 0)); +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + // Store data in ulp memories + RSI_FIM_InputData((pSrcA->pData), ULPSS_RAM_ADDR_SRC1, ((pSrcA->nRows) * (pSrcA->nColumns)), FORMAT_Q15); + // Store data in ulp memories + RSI_FIM_InputData((pSrcB->pData), ULPSS_RAM_ADDR_SRC2, ((pSrcB->nRows) * (pSrcB->nColumns)), FORMAT_Q15); + // Start Address of 1st Input Data for FIM Operations + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + // Start Address of 2nd Input Data for FIM Operations + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + // Start Address of 1st Input Data for FIM Operations + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ((uint32_t)pSrcA->pData); + // Start Address of 2nd Input Data for FIM Operations + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ((uint32_t)pSrcB->pData); + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ((uint32_t)pDst->pData); +#endif + // Set the Mode of Operation to be performed. + FIM->FIM_MODE_INTERRUPT = ((SUB_MAT << 1) | 1); + // Set the data type and Trigger the FIM module + RSI_FIM_DatTypTrig(numRowsA, numColsB, ULP_FIM_COP_DATA_REAL_REAL); + } else { + return ERROR_FIM_MATRIX_INVALID_ARG; + } + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t arm_mat_sub_q31(const arm_matrix_instance_q31_opt *pSrcA, + const arm_matrix_instance_q31_opt *pSrcB, + arm_matrix_instance_q31_opt *pDst) + * @brief Q31 matrix subtraction. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ERROR_FIM_MATRIX_INVALID_ARG or RSI_OK based on the outcome of size checking. + */ +rsi_error_t arm_mat_sub_q31(const arm_matrix_instance_q31_opt *pSrcA, + const arm_matrix_instance_q31_opt *pSrcB, + arm_matrix_instance_q31_opt *pDst) +{ + // Number of rows of input matrix A + uint16_t numRowsA = pSrcA->nRows; + // Number of columns of input matrix B + uint16_t numColsB = pSrcB->nColumns; + // Number of columns of input matrix A + uint16_t numColsA = pSrcA->nColumns; + if ((pSrcA != NULL) && (pSrcB != NULL)) { + if ((pSrcA->nColumns == pSrcB->nColumns) && (pSrcA->nRows == pSrcB->nRows)) { + /* Set column size of buffers in the FIM module */ + RSI_FIM_SetDataLen(numColsA, 0, 0); + // Set sat trunc values to FIM module for corresponding inputs + RSI_FIM_SetSatTruncRound(STRS(0x11, 0, 0, 0)); +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + // Store data in ulp memories + RSI_FIM_InputData((pSrcA->pData), ULPSS_RAM_ADDR_SRC1, ((pSrcA->nRows) * (pSrcA->nColumns)), FORMAT_Q31); + // Store data in ulp memories + RSI_FIM_InputData((pSrcB->pData), ULPSS_RAM_ADDR_SRC2, ((pSrcB->nRows) * (pSrcB->nColumns)), FORMAT_Q31); + // Start Address of 1st Input Data for FIM Operations + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + // Start Address of 2nd Input Data for FIM Operations + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + /* ULPSS buffers from application */ + // Start Address of 1st Input Data for FIM Operations + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ((uint32_t)pSrcA->pData); + // Start Address of 2nd Input Data for FIM Operations + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ((uint32_t)pSrcB->pData); + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ((uint32_t)pDst->pData); +#endif + // Set the Mode of Operation to be performed. + FIM->FIM_MODE_INTERRUPT = ((SUB_MAT << 1) | 1); + // Set the data type and Trigger the FIM module + RSI_FIM_DatTypTrig(numRowsA, numColsB, ULP_FIM_COP_DATA_REAL_REAL); + } else { + return ERROR_FIM_MATRIX_INVALID_ARG; + } + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t arm_mat_trans_q15(const arm_matrix_instance_q15_opt *pSrc, arm_matrix_instance_q15_opt *pDst) + * @brief Q15 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ERROR_FIM_MATRIX_INVALID_ARG + * or RSI_OK based on the outcome of size checking. + */ +rsi_error_t arm_mat_trans_q15(const arm_matrix_instance_q15_opt *pSrc, arm_matrix_instance_q15_opt *pDst) +{ + // Number of rows of input matrix A + uint16_t numRows = pSrc->nRows; + // Number of columns of input matrix B + uint16_t numCols = pSrc->nColumns; + if (pSrc == NULL) { + return ERROR_FIM_MATRIX_INVALID_ARG; + } else { + // Set column size of buffers in the FIM module + RSI_FIM_SetDataLen(numCols, 0, 0); + // Set sat trunc values to FIM module for corresponding inputs + RSI_FIM_SetSatTruncRound(STRS(0x11, 0, 0, 0)); +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + // Store data in ulp memories + RSI_FIM_InputData((pSrc->pData), ULPSS_RAM_ADDR_SRC1, ((pSrc->nRows) * (pSrc->nColumns)), FORMAT_Q15); + // Start Address of 1st Input Data for FIM Operations + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + // ULPSS buffers from application + // Start Address of 1st Input Data for FIM Operations + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ((uint32_t)pSrc->pData); + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ((uint32_t)pDst->pData); + +#endif + // Set the Mode of Operation to be performed. + FIM->FIM_MODE_INTERRUPT = ((MAT_TRANSPOSE << 1) | 1); + // Set the data type and Trigger the FIM module + RSI_FIM_DatTypTrig(numRows, numCols, ULP_FIM_COP_DATA_REAL_REAL); + return RSI_OK; + } +} + +/*==============================================*/ +/** + * @fn rsi_error_t rsi_arm_mat_trans_q31(const arm_matrix_instance_q31_opt *pSrc, arm_matrix_instance_q31_opt *pDst) + * @brief Q31 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ERROR_FIM_MATRIX_INVALID_ARG + * or RSI_OK based on the outcome of size checking. + */ + +rsi_error_t rsi_arm_mat_trans_q31(const arm_matrix_instance_q31_opt *pSrc, arm_matrix_instance_q31_opt *pDst) +{ + // Number of rows of input matrix A + uint16_t numRows = pSrc->nRows; + // Number of columns of input matrix B + uint16_t numCols = pSrc->nColumns; + if (pSrc == NULL) { + return ERROR_FIM_MATRIX_INVALID_ARG; + } else { + /* Set column size of buffers in the FIM module */ + RSI_FIM_SetDataLen(numCols, 0, 0); + // Set sat trunc values to FIM module for corresponding inputs + RSI_FIM_SetSatTruncRound(STRS(0x11, 0, 0, 0)); +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + // Store data in ulp memories + RSI_FIM_InputData((pSrc->pData), ULPSS_RAM_ADDR_SRC1, ((pSrc->nRows) * (pSrc->nColumns)), FORMAT_Q31); + /* Start Address of 1st Input Data for FIM Operations */ + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + /* ULPSS buffers from application */ + /* Start Address of 1st Input Data for FIM Operations */ + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ((uint32_t)pSrc->pData); + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ((uint32_t)pDst->pData); +#endif + // Set the Mode of Operation to be performed. + FIM->FIM_MODE_INTERRUPT = ((MAT_TRANSPOSE << 1) | 1); + // Set the data type and Trigger the FIM module + RSI_FIM_DatTypTrig(numRows, numCols, ULP_FIM_COP_DATA_REAL_REAL); + return RSI_OK; + } +} + +/*==============================================*/ +/** + * @fn rsi_error_t rsi_arm_mat_Hadamard_prod_q15(const arm_matrix_instance_q15_opt *pSrcA, + const arm_matrix_instance_q15_opt *pSrcB, + arm_matrix_instance_q15_opt *pDst) + * @brief Q15 matrix Hadamard product. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ERROR_FIM_MATRIX_INVALID_ARG or RSI_OK based on the outcome of size checking. + */ +rsi_error_t rsi_arm_mat_Hadamard_prod_q15(const arm_matrix_instance_q15_opt *pSrcA, + const arm_matrix_instance_q15_opt *pSrcB, + arm_matrix_instance_q15_opt *pDst) +{ + // Number of rows of input matrix A + uint16_t numRowsA = pSrcA->nRows; + // Number of columns of input matrix B + uint16_t numColsB = pSrcB->nColumns; + // Number of columns of input matrix A + uint16_t numColsA = pSrcA->nColumns; + if ((pSrcA != NULL) && (pSrcB != NULL)) { + if ((pSrcA->nColumns == pSrcB->nColumns) && (pSrcA->nRows == pSrcB->nRows)) { + /* Set column size of buffers in the FIM module */ + RSI_FIM_SetDataLen(numColsA, 0, 0); + // Set sat trunc values to FIM module for corresponding inputs + RSI_FIM_SetSatTruncRound(STRS(0x11, 0, 0, 0)); +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + // Store data in ulp memories + RSI_FIM_InputData((pSrcA->pData), ULPSS_RAM_ADDR_SRC1, ((pSrcA->nRows) * (pSrcA->nColumns)), FORMAT_Q15); + // Store data in ulp memories + RSI_FIM_InputData((pSrcB->pData), ULPSS_RAM_ADDR_SRC2, ((pSrcB->nRows) * (pSrcB->nColumns)), FORMAT_Q15); + // Start Address of 1st Input Data for FIM Operations + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + // Start Address of 2nd Input Data for FIM Operations + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + // Start Address of 1st Input Data for FIM Operations + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ((uint32_t)pSrcA->pData); + // Start Address of 2nd Input Data for FIM Operations + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ((uint32_t)pSrcB->pData); + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ((uint32_t)pDst->pData); +#endif + // Set the Mode of Operation to be performed. + FIM->FIM_MODE_INTERRUPT = ((MAT_HADAMARD << 1) | 1); + // Set the data type and Trigger the FIM module + RSI_FIM_DatTypTrig(numRowsA, numColsB, ULP_FIM_COP_DATA_REAL_REAL); + } else { + return ERROR_FIM_MATRIX_INVALID_ARG; + } + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t arm_mat_Hadamard_prod_q31(const arm_matrix_instance_q31_opt *pSrcA, + const arm_matrix_instance_q31_opt *pSrcB, + arm_matrix_instance_q31_opt *pDst) + * @brief Q31 matrix Hadamard product. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ERROR_FIM_MATRIX_INVALID_ARG or RSI_OK based on the outcome of size checking. + */ +rsi_error_t arm_mat_Hadamard_prod_q31(const arm_matrix_instance_q31_opt *pSrcA, + const arm_matrix_instance_q31_opt *pSrcB, + arm_matrix_instance_q31_opt *pDst) +{ + + // Number of rows of input matrix A + uint16_t numRowsA = pSrcA->nRows; + // Number of columns of input matrix B + uint16_t numColsB = pSrcB->nColumns; + // Number of columns of input matrix A + uint16_t numColsA = pSrcA->nColumns; + if ((pSrcA != NULL) && (pSrcB != NULL)) { + if ((pSrcA->nColumns == pSrcB->nColumns) && (pSrcA->nRows == pSrcB->nRows)) { + /* Set column size of buffers in the FIM module */ + RSI_FIM_SetDataLen(numColsA, 0, 0); + // Set sat trunc values to FIM module for corresponding inputs + RSI_FIM_SetSatTruncRound(STRS(0x11, 0, 0, 0)); +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + // Store data in ulp memories + RSI_FIM_InputData((pSrcA->pData), ULPSS_RAM_ADDR_SRC1, ((pSrcA->nRows) * (pSrcA->nColumns)), FORMAT_Q31); + // Store data in ulp memories + RSI_FIM_InputData((pSrcB->pData), ULPSS_RAM_ADDR_SRC2, ((pSrcB->nRows) * (pSrcB->nColumns)), FORMAT_Q31); + /* Start Address of 1st Input Data for FIM Operations */ + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + /* Start Address of 2nd Input Data for FIM Operations */ + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + /* Start Address of 1st Input Data for FIM Operations */ + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ((uint32_t)pSrcA->pData); + /* Start Address of 2nd Input Data for FIM Operations */ + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ((uint32_t)pSrcB->pData); + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ((uint32_t)pDst->pData); +#endif + // Set the Mode of Operation to be performed. + FIM->FIM_MODE_INTERRUPT = ((MAT_HADAMARD << 1) | 1); + // Set the data type and Trigger the FIM module + RSI_FIM_DatTypTrig(numRowsA, numColsB, ULP_FIM_COP_DATA_REAL_REAL); + } else { + return ERROR_FIM_MATRIX_INVALID_ARG; + } + } + return RSI_OK; +} + +/*==============================================*/ +/** + *@fn void rsi_arm_VSqrt_q15(q15_t *pSrc, q15_t *pDst, uint32_t blockSize) + *@brief This API is used to set the FIM Q15 Square root for real number + *@param[in] *pSrc points input for squaring a number + *@param[in] *pDst points to the block of output data + *@param[in] blockSize is size of the input array + *@return none + */ +void rsi_arm_VSqrt_q15(q15_t *pSrc, q15_t *pDst, uint32_t blockSize) +{ + // Set data blockSize of buffers in the FIM module + RSI_FIM_SetDataLen(NOT_MATRIX, blockSize, TRIG_LUT_LEN); + // Set sat trunc values to FIM module for corresponding inputs + RSI_FIM_SetSatTruncRound(STRS(0x1F, 0, 0, 0)); +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + // Store data in ulp memories + RSI_FIM_InputData(pSrc, ULPSS_RAM_ADDR_SRC1, blockSize, FORMAT_Q15); + // Store data in ulp memories + RSI_FIM_InputData(Trig_lut2, ULPSS_RAM_ADDR_SRC2, TRIG_LUT_LEN, FORMAT_Q15); + // Start Address of 1st Input Data for FIM Operations + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + // Start Address of lookup table Data for FIM Operations + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + // Start Address of 1st Input Data for FIM Operations + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrc; + /* Start Address of lookup table Data for FIM Operations */ + FIM->FIM_INP2_ADDR_b.INP2_ADDR = (uint32_t)Trig_lut2; + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif + // Set the Mode of Operation to be performed. + FIM->FIM_MODE_INTERRUPT = ((SQ_ROOT << 1) | 1); + // Set the data type and Trigger the FIM module + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + *@fn void rsi_arm_log_q15(q15_t *pSrc, q15_t *pDst, uint16_t blockSize) + *@brief This API is used to set the FIM Q15 Natural Log Operation for real number + *@param[in] *pSrc points input for squaring a number + *@param[in] *pDst points to the block of output data + *@param[in] blockSize is size of the input array + *@return none + */ +void rsi_arm_log_q15(q15_t *pSrc, q15_t *pDst, uint16_t blockSize) +{ + // Set data blockSize of buffers in the FIM module + RSI_FIM_SetDataLen(NOT_MATRIX, blockSize, TRIG_LUT_LEN); + // Set sat trunc values to FIM module for corresponding inputs + RSI_FIM_SetSatTruncRound(STRS(0x1F, 0, 0, 0)); +#if ULPSS_MEMORY_WITH_M4_MEM_BUFFRS + // Use application buffer which are in M4 RAM and copy them to ulpss RAM ,point ulpss RAM address to FIM + // Store data in ulp memories + RSI_FIM_InputData(pSrc, ULPSS_RAM_ADDR_SRC1, blockSize, FORMAT_Q15); + // Store data in ulp memories + RSI_FIM_InputData(Trig_lut2, ULPSS_RAM_ADDR_SRC2, TRIG_LUT_LEN, FORMAT_Q15); + // Start Address of 1st Input Data for FIM Operations + FIM->FIM_INP1_ADDR_b.INP1_ADDR = ULPSS_RAM_ADDR_SRC1; + // Start Address of lookup table Data for FIM Operations + FIM->FIM_INP2_ADDR_b.INP2_ADDR = ULPSS_RAM_ADDR_SRC2; + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = ULPSS_RAM_ADDR_DST; +#else + // Start Address of 1st Input Data for FIM Operations + FIM->FIM_INP1_ADDR_b.INP1_ADDR = (uint32_t)pSrc; + // Start Address of lookup table Data for FIM Operations + FIM->FIM_INP2_ADDR_b.INP2_ADDR = (uint32_t)Trig_lut2; + // Start Address of Output Data for FIM Operations + FIM->FIM_OUT_ADDR_b.OUT_ADDR = (uint32_t)pDst; +#endif + // Set the Mode of Operation to be performed. + FIM->FIM_MODE_INTERRUPT = ((NAT_LOG << 1) | 1); + // Set the data type and Trigger the FIM module + RSI_FIM_DatTypTrig(NOT_MATRIX, NOT_MATRIX, ULP_FIM_COP_DATA_REAL_REAL); +} + +/*==============================================*/ +/** + *@fn void rsi_enable_inst_buff(void) + *@brief This API is used to select instruction buffer for performing more than one operations at a time. + *@return none + */ +void rsi_enable_inst_buff(void) +{ + // Instruction buffer enable + FIM->FIM_CONFIG_REG2_b.INSTR_BUFF_ENABLE = ENABLE; +} + +#ifdef INST_BUFF_ENABLE +/*==============================================*/ +/** + *@fn void rsi_fim_copy_fim_reg_to_ulp_memory(void) + *@brief This API is used to copy FIM configuration to ulpss memory when instruction buffer is enabled . + *@return none + */ +void rsi_fim_copy_fim_reg_to_ulp_memory(void) +{ + static int reg_copy_count; + memcpy((void *)(ULP_MEMORY_ADDR + (reg_copy_count * 9 * 4)), (const char *)FIM_BASE, 36); + memset((void *)(ULP_MEMORY_ADDR + (((reg_copy_count + 1) * 0x24))), 0xFFFFFFFF, sizeof(int)); + reg_copy_count++; +} +#endif +#endif diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_ir.c b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_ir.c new file mode 100644 index 000000000..8c4668c6e --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_ir.c @@ -0,0 +1,59 @@ +/******************************************************************************* +* @file rsi_ir.c +* @brief +******************************************************************************* +* # License +* Copyright 2022 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +// Include files + +#include "rsi_ir.h" + +/** @addtogroup SOC23 +* @{ +*/ +/*==============================================*/ +/** + * @fn uint16_t RSI_IR_ReadData(IR_Type* pIr,uint16_t memory_address) + * @brief This API is used read IR address. + * @param[in] pIr : IR type pointer + * @param[in] memory_address : memory address value (0 .. 128). + * @return 16-Bit IR data received (BIT[15] in received data will indicate the polarity of pulse) + * \n remaining bit will contain the incremented counter value of the pulse. + */ +uint16_t RSI_IR_ReadData(IR_Type *pIr, uint16_t memory_address) +{ + if (memory_address > MAX_MEMORY_ADDRESS) { + return INVALID_PARAMETERS; + } + pIr->IR_MEM_ADDR_ACCESS_b.IR_MEM_ADDR = (unsigned int)(memory_address & 0x007F); + pIr->IR_MEM_ADDR_ACCESS_b.IR_MEM_RD_EN = 1U; + return pIr->IR_MEM_READ_b.IR_MEM_DATA_OUT; +} + +/*==============================================*/ +/** + * @fn void RSI_IR_SoftwareRestart(IR_Type* pIr) + * @brief This API restart the IR operation. + * @param[in] pIr : IR type pointer + */ +void RSI_IR_SoftwareRestart(IR_Type *pIr) +{ + uint8_t i; + pIr->IR_CONFIG_b.SREST_IR_CORE = 1U; + for (i = 0; i < 10; i++) { + __ASM("nop"); + } + pIr->IR_CONFIG_b.SREST_IR_CORE = 0U; +} +/** @} */ \ No newline at end of file diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_sdioh.c b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_sdioh.c new file mode 100644 index 000000000..93e3a9f0c --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_sdioh.c @@ -0,0 +1,798 @@ +/******************************************************************************* +* @file rsi_sdioh.c +* @brief +******************************************************************************* +* # License +* Copyright 2022 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +// Include Files + +#include "rsi_ccp_user_config.h" +#if defined(CHIP_9118) + +#include "clock_update.h" + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_SDIOH_RegisterInfo(SMIH_CARD_CONFIG_T *pSmihConfig, SMIH_CCCR_REG_INFO_T *pRegInfo) + * @brief This API is used to know the register info of the card. + * @param[in] pSmihConfig : Pointer to the card command information structure + * @param[in] pRegInfo : Pointer to the Command info structure + * @return RSI_OK : command sent succesfully + * ERROR_SMIH : If Parameter is invalid. + */ +rsi_error_t RSI_SDIOH_RegisterInfo(SMIH_CARD_CONFIG_T *pSmihConfig, SMIH_CCCR_REG_INFO_T *pRegInfo) +{ + SMIH_TRANSFER_T transfer = { 0 }; + SMIH_CMD_FEILD_T cmd = { 0 }; + SMIH_DATA_FEILD_T data = { 0 }; + uint8_t cccr[22] = { 0 }; + + cmd.cmdIdx = CMD_53; + cmd.cmdArg = CCCR_BYTE_READ; + cmd.responseTypeSelect = SMIH_RESPONSE_R1R5R6R7; + data.data = cccr; + data.blockSize = 0x16; + data.blockCount = 1; + cmd.responseTypeSelect = SMIH_RESPONSE_R1R5R6R7; + data.direction = SMIH_READ_DIRECTION; + + transfer.command = &cmd; + transfer.data = &data; + + // transfer command to the slave + if (RSI_OK != pSmihConfig->cmd_transfer(&transfer)) { + return ERROR_SMIH; + } + memset((void *)pRegInfo, 0x0, 22); + memcpy((void *)pRegInfo, &transfer.data->data, 22); + + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_SDIOH_WriteCommandCmd52(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t Argument) + * @brief This API is used to send the SDIO_CMD52 to the card. + * @param[in] pSmihConfig : Pointer to the card command information structure + * @param[in] Argument : Argument to the command + * @return RSI_OK : command sent succesfully + * ERROR_SMIH : If Parameter is invalid. + * ERROR_TIMEOUT : If the command error timeout occures. + */ +rsi_error_t RSI_SDIOH_WriteCommandCmd52(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t Argument) +{ + SMIH_TRANSFER_T transfer = { 0 }; + SMIH_CMD_FEILD_T cmd = { 0 }; + SMIH_DATA_FEILD_T data = { 0 }; + + cmd.cmdIdx = CMD_52; + cmd.cmdArg = Argument; + cmd.responseTypeSelect = SMIH_RESPONSE_R1R5R6R7; + data.data = 0; + data.blockSize = 0; + data.blockCount = 0; + data.direction = SMIH_WRITE_DIRECTION; + + transfer.command = &cmd; + transfer.data = &data; + + memset((void *)&pSmihConfig->response[0], 0x0, sizeof(pSmihConfig->response)); + + // transfer command + if (RSI_OK != pSmihConfig->cmd_transfer(&transfer)) { + return ERROR_SMIH; + } else { + memcpy((void *)&pSmihConfig->response[0], &transfer.command->response[0], sizeof(pSmihConfig->response)); + return RSI_OK; + } +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_SDIOH_ReadCommandCmd52(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t Argument) + * @brief This API is used to send the SDIO_CMD52 to the card. + * @param[in] pcmdInfo : Pointer to the card information strut + * @param[in] Argument : Argument to the command + * @return RSI_OK : In case of command sent succesfully + * ERROR_SMIH : If Parameter is invalid. + * ERROR_TIMEOUT : If the command error timeout occures. + */ +rsi_error_t RSI_SDIOH_ReadCommandCmd52(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t Argument) +{ + SMIH_TRANSFER_T transfer = { 0 }; + SMIH_CMD_FEILD_T cmd = { 0 }; + SMIH_DATA_FEILD_T data = { 0 }; + + cmd.cmdIdx = CMD_52; + cmd.cmdArg = Argument; + cmd.responseTypeSelect = SMIH_RESPONSE_R1R5R6R7; + data.data = 0; + data.blockSize = 0; + data.blockCount = 0; + data.direction = SMIH_READ_DIRECTION; + + transfer.command = &cmd; + transfer.data = &data; + + // transfer command + if (RSI_OK != pSmihConfig->cmd_transfer(&transfer)) { + return ERROR_SMIH; + } else { + memset((void *)&pSmihConfig->response[0], 0x0, sizeof(pSmihConfig->response)); + memcpy((void *)&pSmihConfig->response[0], &transfer.command->response[0], sizeof(pSmihConfig->response)); + return RSI_OK; + } +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_SDIOH_SetBusWidthCmd52(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t CmdArg) + * @brief This API is used to send the SDIO_CMD52 to set bus width to the IO card. + * @param[in] pSmihConfig : Pointer to the card info struct + * @param[in] CmdArg : Command Argument + * @return RSI_OK : If the command sent successfully + * ERROR_TIMEOUT : If the command error timeout occures. + */ +rsi_error_t RSI_SDIOH_SetBusWidthCmd52(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t CmdArg) +{ + SMIH_TRANSFER_T transfer = { 0 }; + SMIH_CMD_FEILD_T cmd = { 0 }; + SMIH_DATA_FEILD_T data = { 0 }; + + cmd.cmdIdx = CMD_52; + cmd.cmdArg = CmdArg; + data.data = NULL; + data.blockSize = 0; + data.blockCount = 0; + cmd.responseTypeSelect = SMIH_RESPONSE_R1R5R6R7; + data.direction = SMIH_WRITE_DIRECTION; + + transfer.command = &cmd; + transfer.data = &data; + + // transfer Command + if (RSI_OK != pSmihConfig->cmd_transfer(&transfer)) { + return ERROR_SMIH; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_SDIOH_BusWidthConfig(SMIH_CARD_CONFIG_T *pSmihConfig, uint8_t BusWidth) + * @brief This API is used to change the bus width. + * @param[in] pcmdInfo : Pointer to the card information strut + * @param[in] BusWidth : Width of the bus + * \n possible values are + * \n SMIH_BUS_WIDTH1 = 0u, + * \n SMIH_BUS_WIDTH4 = 1u, + * \n SMIH_BUS_WIDTH8 = 2u, + * @return RSI_OK : If bus width set properly + * ERROR_SMIH : If Parameter is invalid. + */ +rsi_error_t RSI_SDIOH_BusWidthConfig(SMIH_CARD_CONFIG_T *pSmihConfig, uint8_t BusWidth) +{ + uint32_t cmdArg = 0; + boolean_t host4BitMode = FALSE; + + if (BusWidth == SMIH_BUS_WIDTH4) { + cmdArg = BIT4_BUS_WIDTH_ARG; + host4BitMode = TRUE; + } else { + cmdArg = 0; + host4BitMode = FALSE; + } + if (RSI_OK != RSI_SDIOH_SetBusWidthCmd52(pSmihConfig, cmdArg)) { + return ERROR_SMIH; + } else { + // host side setting + smih_bus_width_set(host4BitMode); + return RSI_OK; + } +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_SDIOH_GoIdleStateCmd0(SMIH_CARD_CONFIG_T *pSmihConfig) + * @brief This API is used to send the cmd0 to the io card. + * @param[in] pSmihConfig : Pointer to the Command info structure + * @return RSI_OK : If command sent successfully + * ERROR_TIMEOUT : If command error timeout occures. + */ +rsi_error_t RSI_SDIOH_GoIdleStateCmd0(SMIH_CARD_CONFIG_T *pSmihConfig) +{ + SMIH_TRANSFER_T transfer = { 0 }; + SMIH_CMD_FEILD_T cmd = { 0 }; + SMIH_DATA_FEILD_T data = { 0 }; + + cmd.cmdIdx = 0; + cmd.cmdArg = 0x0; + cmd.responseTypeSelect = SMIH_NO_RESPONSE; + data.data = NULL; + data.blockSize = 0x0; + data.blockCount = 0x0; + data.direction = SMIH_WRITE_DIRECTION; + + transfer.command = &cmd; + transfer.data = &data; + + // transfer Command + if (RSI_OK != pSmihConfig->cmd_transfer(&transfer)) { + return ERROR_SMIH; + } + return RSI_OK; +} +/*==============================================*/ +/** + * @fn rsi_error_t RSI_SDIOH_SendRelativeCardAddressCmd3(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t CmdArg) + * @brief This API is used to send the SDIO_CMD3(Get relative card address) to the IO card. + * @param[in] pSmihConfig : Pointer to the card info struct + * @param[in] CmdArg : Command argument to send + * @return RSI_OK : If command sent successfully + * ERROR_TIMEOUT : If command error timeout occures. + */ +rsi_error_t RSI_SDIOH_SendRelativeCardAddressCmd3(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t CmdArg) +{ + SMIH_TRANSFER_T transfer = { 0 }; + SMIH_CMD_FEILD_T cmd = { 0 }; + SMIH_DATA_FEILD_T data = { 0 }; + + cmd.cmdIdx = CMD_3; + cmd.cmdArg = CmdArg; + cmd.responseTypeSelect = SMIH_RESPONSE_R1R5R6R7; + data.data = NULL; + data.blockSize = 0; + data.blockCount = 0; + data.direction = SMIH_WRITE_DIRECTION; + + transfer.command = &cmd; + transfer.data = &data; + + // transfer Command + if (RSI_OK != pSmihConfig->cmd_transfer(&transfer)) { + return ERROR_SMIH; + } + if (CmdArg == 0x0) { + pSmihConfig->rca = transfer.command->response[0] >> 16; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_SDIOH_SwitchVoltageCmd11(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t CmdArg) + * @brief This API is used to send the SDIO_CMD11(Voltage switch command in case of uhs modes) to the io card. + * @param[in] pSmihConfig : Pointer to the card info struct + * @param[in] CmdArg : Command argument to send + * @return RSI_OK : If command sent successfully + * ERROR_TIMEOUT : If the command error timeout occures. + */ +rsi_error_t RSI_SDIOH_SwitchVoltageCmd11(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t CmdArg) +{ + SMIH_TRANSFER_T transfer = { 0 }; + SMIH_CMD_FEILD_T cmd = { 0 }; + SMIH_DATA_FEILD_T data = { 0 }; + + cmd.cmdIdx = CMD_11; + cmd.cmdArg = 0; + cmd.responseTypeSelect = SMIH_RESPONSE_R1R5R6R7; + data.data = NULL; + data.blockSize = 0; + data.blockCount = 0; + data.direction = SMIH_WRITE_DIRECTION; + + transfer.command = &cmd; + transfer.data = &data; + + // transfer Command + if (RSI_OK != pSmihConfig->cmd_transfer(&transfer)) { + return ERROR_SMIH; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_SDIOH_SelectCardCmd7(SMIH_CARD_CONFIG_T *pSmihConfig) + * @brief This API is used to send the cmd 7(select the cards) to the IO card. + * @param[in] pSmihConfig : Pointer to the Command info structure + * @return RSI_OK : If the command sent successfully + * ERROR_TIMEOUT : If the command error timeout occures. + */ +rsi_error_t RSI_SDIOH_SelectCardCmd7(SMIH_CARD_CONFIG_T *pSmihConfig) +{ + SMIH_TRANSFER_T transfer = { 0 }; + SMIH_CMD_FEILD_T cmd = { 0 }; + SMIH_DATA_FEILD_T data = { 0 }; + + cmd.cmdIdx = CMD_7; + cmd.cmdArg = pSmihConfig->rca << 16; + cmd.responseTypeSelect = SMIH_RESPONSE_R1BR5B; + data.data = NULL; + data.blockSize = 0; + data.blockCount = 0; + data.direction = SMIH_WRITE_DIRECTION; + + transfer.command = &cmd; + transfer.data = &data; + + // transfer Command + if (RSI_OK != pSmihConfig->cmd_transfer(&transfer)) { + return ERROR_SMIH; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_SDIOH_ByteBlockWriteCmd53(SMIH_CARD_CONFIG_T *pSmihConfig, uint8_t *pData, uint32_t Addr) + * @brief This API is used to send the SDIO_CMD53 to write data to the IO card. + * @param[in] pSmihConfig : Pointer to the smih config struct + * @param[in] pData : Pointer to the buffer data to write + * @param[in] Addr : Address to write the data + * @return RSI_OK : If the command sent successfully + * ERROR_TIMEOUT : If the command error timeout occured. + */ +rsi_error_t RSI_SDIOH_ByteBlockWriteCmd53(SMIH_CARD_CONFIG_T *pSmihConfig, uint8_t *pData, uint32_t Addr) +{ + SMIH_TRANSFER_T transfer = { 0 }; + SMIH_CMD_FEILD_T cmd = { 0 }; + SMIH_DATA_FEILD_T data = { 0 }; + + if ((NULL == pData)) { + return INVALID_PARAMETERS; + } + cmd.cmdIdx = CMD_53; + if (pSmihConfig->blockModeEnable) { + cmd.cmdArg = (pSmihConfig->numberOfBlocks); + } else { + cmd.cmdArg = (pSmihConfig->byteBlockSize); + } + cmd.cmdArg |= (((Addr)&0x0001FFFF) << 9); + cmd.cmdArg |= (pSmihConfig->opCode << 26); + cmd.cmdArg |= (pSmihConfig->blockModeEnable << 27); + cmd.cmdArg |= (pSmihConfig->funcNum << 28); + cmd.cmdArg |= BIT(31); + cmd.responseTypeSelect = SMIH_RESPONSE_R1R5R6R7; + data.data = pData; + data.blockSize = pSmihConfig->byteBlockSize; + data.blockCount = pSmihConfig->numberOfBlocks; + data.direction = SMIH_WRITE_DIRECTION; + + transfer.command = &cmd; + transfer.data = &data; + + // transfer Command + if (RSI_OK != pSmihConfig->cmd_transfer(&transfer)) { + return ERROR_SMIH; + } + return RSI_OK; +} +/*==============================================*/ +/** + * @fn rsi_error_t RSI_SDIOH_ByteBlockReadCmd53(SMIH_CARD_CONFIG_T *pSmihConfig, uint8_t *pData, uint32_t Addr) + * @brief This API is used to send the SDIO_CMD53 to read data from the IO card. + * @param[in] pSmihConfig : Pointer to the smih config struct + * @param[in] pData : Pointer to the buffer data to read + * @param[in] Addr : Address to read the data + * @return RSI_OK : If the command sent successfully + * ERROR_TIMEOUT : If the command error timeout occures. + */ +rsi_error_t RSI_SDIOH_ByteBlockReadCmd53(SMIH_CARD_CONFIG_T *pSmihConfig, uint8_t *pData, uint32_t Addr) +{ + SMIH_TRANSFER_T transfer = { 0 }; + SMIH_CMD_FEILD_T cmd = { 0 }; + SMIH_DATA_FEILD_T data = { 0 }; + + cmd.cmdIdx = CMD_53; + if (pSmihConfig->blockModeEnable == 1) { + cmd.cmdArg = (pSmihConfig->numberOfBlocks); + } else { + cmd.cmdArg = (pSmihConfig->byteBlockSize); + } + cmd.cmdArg |= (((Addr)&0x0001FFFF) << 9); + cmd.cmdArg |= (pSmihConfig->opCode << 26); + cmd.cmdArg |= (pSmihConfig->blockModeEnable << 27); + cmd.cmdArg |= (pSmihConfig->funcNum << 28); + cmd.cmdArg |= (((0 << 0)) << 31); + cmd.responseTypeSelect = SMIH_RESPONSE_R1R5R6R7; + data.data = pData; + data.blockSize = pSmihConfig->byteBlockSize; + data.blockCount = pSmihConfig->numberOfBlocks; + data.direction = SMIH_READ_DIRECTION; + + transfer.command = &cmd; + transfer.data = &data; + + // transfer Command + if (RSI_OK != pSmihConfig->cmd_transfer(&transfer)) { + return ERROR_SMIH; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_SDIOH_ReInitializationCmd5(SMIH_CARD_CONFIG_T *pSmihConfig) + * @brief This API is used to send the SDIO_CMD5 to reinitialize the SDIO card. + * @param[in] pSmihConfig : Pointer to the smih config struct + * @return RSI_OK : If the command sent successfully + * ERROR_TIMEOUT : If the command error timeout occures. + */ +rsi_error_t RSI_SDIOH_ReInitializationCmd5(SMIH_CARD_CONFIG_T *pSmihConfig) +{ + SMIH_TRANSFER_T transfer = { 0 }; + SMIH_CMD_FEILD_T cmd = { 0 }; + SMIH_DATA_FEILD_T data = { 0 }; + + cmd.cmdIdx = CMD_5; + cmd.cmdArg = *(uint32_t *)(&pSmihConfig->ocr); + if (pSmihConfig->voltage == 1) { + cmd.cmdArg |= 0x01100000; + } else { + cmd.cmdArg |= 0x00100000; + } + cmd.responseTypeSelect = SMIH_RESPONSE_R3R4; + data.data = NULL; + data.blockSize = 0; + data.blockCount = 0; + data.direction = SMIH_WRITE_DIRECTION; + + transfer.command = &cmd; + transfer.data = &data; + + // gtransfer Command + if (RSI_OK == pSmihConfig->cmd_transfer(&transfer)) { + memcpy((void *)&pSmihConfig->ocr, &transfer.command->response[0], sizeof(pSmihConfig->ocr)); + return RSI_OK; + } + return ERROR_SMIH; +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_SDIOH_InitializationCmd5(SMIH_CARD_CONFIG_T *pSmihConfig) + * @brief This API is used to send the SDIO_CMD5 to initialize the SDIO card. + * @param[in] pSmihConfig : Pointer to the smih card information struct + * @return RSI_OK : If the command sent successfully + * ERROR_TIMEOUT : If the command error timeout occures. + */ +rsi_error_t RSI_SDIOH_InitializationCmd5(SMIH_CARD_CONFIG_T *pSmihConfig) +{ + SMIH_TRANSFER_T transfer = { 0 }; + SMIH_CMD_FEILD_T cmd = { 0 }; + SMIH_DATA_FEILD_T data = { 0 }; + + cmd.cmdIdx = CMD_5; + cmd.cmdArg = *(uint32_t *)&pSmihConfig->ocr; + cmd.cmdArg = (cmd.cmdArg & 0x00000000); + cmd.responseTypeSelect = SMIH_RESPONSE_R3R4; + data.data = NULL; + data.blockSize = 0; + data.blockCount = 0; + data.direction = SMIH_WRITE_DIRECTION; + + transfer.command = &cmd; + transfer.data = &data; + + // transfer Command + if (RSI_OK == pSmihConfig->cmd_transfer(&transfer)) { + memcpy((void *)&pSmihConfig->ocr, &transfer.command->response[0], sizeof(pSmihConfig->ocr)); + return RSI_OK; + } + return ERROR_SMIH; +} + +/*==============================================*/ +/** + * @fn void RSI_SDIOH_PinMux(void) + * @brief This API is used to configure GPIOs for SDIOH operations. + * @return none + */ +void RSI_SDIOH_PinMux(void) +{ + // enable pads for pins +#if SDIO_SET1 + RSI_EGPIO_PadSelectionEnable(SDIO_CLK_PAD); + RSI_EGPIO_PadSelectionEnable(SDIO_CMD_PAD); + RSI_EGPIO_PadSelectionEnable(SDIO_D0_PAD); + RSI_EGPIO_PadSelectionEnable(SDIO_D1_PAD); + RSI_EGPIO_PadSelectionEnable(SDIO_D2_PAD); + RSI_EGPIO_PadSelectionEnable(SDIO_D3_PAD); +#else + // Enable Host Pad Gpio modes + // SDIO Connected to Tass + (*(volatile uint32_t *)(0x41300004)) = (0x1 << 5); + RSI_EGPIO_HostPadsGpioModeEnable(SDIO_CLK_PIN); + RSI_EGPIO_HostPadsGpioModeEnable(SDIO_CMD_PIN); + RSI_EGPIO_HostPadsGpioModeEnable(SDIO_D0_PIN); + RSI_EGPIO_HostPadsGpioModeEnable(SDIO_D1_PIN); + RSI_EGPIO_HostPadsGpioModeEnable(SDIO_D2_PIN); + RSI_EGPIO_HostPadsGpioModeEnable(SDIO_D3_PIN); +#endif + + RSI_EGPIO_PadSelectionEnable(SDIO_WP_PAD); + RSI_EGPIO_PadSelectionEnable(SDIO_CD_PAD); + + // Ren enables for Gpios + RSI_EGPIO_PadReceiverEnable(SDIO_CLK_PIN); + RSI_EGPIO_PadReceiverEnable(SDIO_CMD_PIN); + RSI_EGPIO_PadReceiverEnable(SDIO_D0_PIN); + RSI_EGPIO_PadReceiverEnable(SDIO_D1_PIN); + RSI_EGPIO_PadReceiverEnable(SDIO_D2_PIN); + RSI_EGPIO_PadReceiverEnable(SDIO_D3_PIN); + RSI_EGPIO_PadReceiverEnable(SDIO_CD_PIN); + RSI_EGPIO_PadReceiverEnable(SDIO_WP_PIN); + + // Configure software pull ups for cmd ,d0,d1,d2,d3 + RSI_EGPIO_PadDriverDisableState(SDIO_CMD_PIN, Pullup); + RSI_EGPIO_PadDriverDisableState(SDIO_D0_PIN, Pullup); + RSI_EGPIO_PadDriverDisableState(SDIO_D1_PIN, Pullup); + RSI_EGPIO_PadDriverDisableState(SDIO_D2_PIN, Pullup); + RSI_EGPIO_PadDriverDisableState(SDIO_D3_PIN, Pullup); + + RSI_EGPIO_PadDriverDisableState(SDIO_WP_PIN, Pulldown); + RSI_EGPIO_PadDriverDisableState(SDIO_CD_PIN, Pulldown); + + // Configure Mux + RSI_EGPIO_SetPinMux(EGPIO, 0, SDIO_CLK_PIN, SDIO_CLK_MUX); + RSI_EGPIO_SetPinMux(EGPIO, 0, SDIO_CMD_PIN, SDIO_CMD_MUX); + RSI_EGPIO_SetPinMux(EGPIO, 0, SDIO_D0_PIN, SDIO_D0_MUX); + RSI_EGPIO_SetPinMux(EGPIO, 0, SDIO_D1_PIN, SDIO_D1_MUX); + RSI_EGPIO_SetPinMux(EGPIO, 0, SDIO_D2_PIN, SDIO_D2_MUX); + RSI_EGPIO_SetPinMux(EGPIO, 0, SDIO_D3_PIN, SDIO_D3_MUX); + RSI_EGPIO_SetPinMux(EGPIO, 0, SDIO_CD_PIN, SDIO_CD_MUX); + RSI_EGPIO_SetPinMux(EGPIO, 0, SDIO_WP_PIN, SDIO_WP_MUX); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_SDIOH_Enumeration(SMIH_CARD_CONFIG_T *pSmihConfig, ARM_SMIH_SignalEvent_t Event) + * @brief This API is used to initialize the IO card + * @param[in] pSmihConfig : Pointer to the smih card configuration + * Event : event handler to be register + * @return RSI_OK : IO card initialized successfully + * INVALID_PARAMETERS : if pSmihConfig == NULL + */ +rsi_error_t RSI_SDIOH_Enumeration(SMIH_CARD_CONFIG_T *pSmihConfig, ARM_SMIH_SignalEvent_t Event) +{ + if (pSmihConfig == 0) { + return INVALID_PARAMETERS; + } + + // Configure gpios in smih mode + RSI_SDIOH_PinMux(); + + // initialize the host + if (RSI_OK != RSI_SD_HostInit(pSmihConfig, Event, 0)) { + return ERROR_SMIH; + } else { + // Commands for sdio enumeration + + rsi_delay_ms(5); + +init: + // Reset Card + if (RSI_OK != RSI_SDIOH_GoIdleStateCmd0(pSmihConfig)) { + goto init; + } + // Get Operational voltage + if (RSI_OK != RSI_SDIOH_InitializationCmd5(pSmihConfig)) { + goto init; + } + // Set Operational voltage and get ocr + if (RSI_OK != RSI_SDIOH_ReInitializationCmd5(pSmihConfig)) { + return ERROR_SMIH; + } + if (!(pSmihConfig->ocr.cardReady)) { + goto init; + } + if ((pSmihConfig->ocr.memPresent)) { + return CARD_TYPE_MEMCARD; + } + if (!(pSmihConfig->ocr.ioNum)) { + return ERROR_INAVLID_MODE; + } + if (pSmihConfig->highSpeedEnable == 1) { + // disable clock to the sd + M4CLK->SD_MEM_CLOCK_REG_b.SD_MEM_INTF_CLK_SEL = 0x7; + + // wait for some time + rsi_delay_ms(5); + + SMIH->SMIH_HOST_CONTROL_1_REGISTER_b.HIGH_SPEED_ENABLE = 0x1; + + // enable clock + RSI_CLK_SdMemClkConfig(M4CLK, 1, SDMEM_SOCPLLCLK, 1); + + // wait for some time + rsi_delay_ms(2); + } + if (pSmihConfig->uhsModeSelect != 0) { + // works only with 1.8 volatge level + if (!(pSmihConfig->ocr.s18A)) { + return ERROR_INAVLID_MODE; + } + // send volatge switching command in case of uhs modes + if (RSI_OK != RSI_SDIOH_SwitchVoltageCmd11(pSmihConfig, 0x0)) { + return ERROR_SMIH; + } + //disable clock to the sd + M4CLK->SD_MEM_CLOCK_REG_b.SD_MEM_INTF_CLK_SEL = 0x7; + + // wait for some time + rsi_delay_ms(5); + + // enable 1.8 volt bit in controller + smih_18v_signal_enable(); + + // select uhs mode + smih_uhs_mode_select(pSmihConfig->uhsModeSelect); + + // enable clock + RSI_CLK_SdMemClkConfig(M4CLK, 1, SDMEM_SOCPLLCLK, 1); + + // wait for some time + rsi_delay_ms(2); + } + + // Get relative card address + if (RSI_OK != RSI_SDIOH_SendRelativeCardAddressCmd3(pSmihConfig, 0x0)) { + return ERROR_SMIH; + } + + // Select Card (send cmd7) :send rca as argument + if (RSI_OK != RSI_SDIOH_SelectCardCmd7(pSmihConfig)) { + return ERROR_SMIH; + } + if (RSI_OK != RSI_SDIOH_WriteCommandCmd52(pSmihConfig, CD_DISABLE_ARG)) { + return ERROR_SMIH; + } +bus_send_again: + + if (RSI_OK != RSI_SDIOH_WriteCommandCmd52(pSmihConfig, LOW_SPEED_CHECK_ARG)) { + return ERROR_SMIH; + } + if (pSmihConfig->response[0] & LOW_SPEED_CHECK) { + if (pSmihConfig->response[0] & BIT4_MODE_CHECK) { + if (SMIH_BUS_WIDTH4 == pSmihConfig->busWidthMode) { + // configure 4bit mode + RSI_SDIOH_BusWidthConfig(pSmihConfig, SMIH_BUS_WIDTH4); + } + } else { + } + } else { + if (SMIH_BUS_WIDTH4 == pSmihConfig->busWidthMode) { + if (RSI_OK != RSI_SDIOH_BusWidthConfig(pSmihConfig, SMIH_BUS_WIDTH4)) { + return ERROR_SMIH; + } + } + } + while (1) { + // Enable function1 + if (RSI_OK == RSI_SDIOH_WriteCommandCmd52(pSmihConfig, FUCNTION1_CHECK_ARG)) { + if (!((pSmihConfig->response[0]) & FUNCTION1_ENABLE)) { + if (RSI_OK != RSI_SDIOH_WriteCommandCmd52(pSmihConfig, FUCNTION1_ENB_ARG)) { + return ERROR_SMIH; + } else { + break; + } + } else + break; + } + } + while (1) { + // Check for function ready + if (RSI_OK == RSI_SDIOH_WriteCommandCmd52(pSmihConfig, FUCNTION1_READY_ARG)) { + if (pSmihConfig->response[0] & FUNCTION1_READY) { + break; + } + } + } + // Interrupt Enable + if (RSI_OK != RSI_SDIOH_WriteCommandCmd52(pSmihConfig, FUNCTION1_INTR_ENB_ARG)) { + return ERROR_SMIH; + ; + } + // Check interrupts are enabled or not + if (RSI_OK != RSI_SDIOH_WriteCommandCmd52(pSmihConfig, FUNCTION1_INTR_CHECK_ARG)) { + return ERROR_SMIH; + } + // Check for 1bit or 4bit mode of I/O + if (RSI_OK != RSI_SDIOH_WriteCommandCmd52(pSmihConfig, BIT4_BUS_WIDTH_SET_ARG)) { + return ERROR_SMIH; + } + if (SMIH_BUS_WIDTH4 == pSmihConfig->busWidthMode) { + if (!(pSmihConfig->response[0] & BUS_BIT)) { + goto bus_send_again; + } + } + // Check for CD Disable + if (!(pSmihConfig->response[0] & (1 << 7))) { + return RSI_OK; + } + if (RSI_OK == RSI_SDIOH_WriteCommandCmd52(pSmihConfig, CSA_SUPPORT_ARG)) { + if (pSmihConfig->response[0] & (1 << 6)) { + if (RSI_OK != RSI_SDIOH_WriteCommandCmd52(pSmihConfig, CSA_ENABLE_ARG)) { + return ERROR_SMIH; + } + } + if (RSI_OK != RSI_SDIOH_WriteCommandCmd52(pSmihConfig, IO_BLOCKSIZE_ARG)) { + return ERROR_SMIH; + } + if (RSI_OK != RSI_SDIOH_WriteCommandCmd52(pSmihConfig, IO_BLOCKSIZE_ARG_1)) { + return ERROR_SMIH; + } + } + // High speed mode configuration + if (pSmihConfig->highSpeedEnable) { + while (1) { + if (RSI_OK != RSI_SDIOH_WriteCommandCmd52(pSmihConfig, CHECK_HIGH_SPEED_SUPPORT)) { + return ERROR_SMIH; + } + + if ((pSmihConfig->response[0] & HIGH_SPEED_BIT)) { + break; + } + } + // high speed mode switching command + if (RSI_OK != RSI_SDIOH_WriteCommandCmd52(pSmihConfig, ENABLE_HIGH_SPEED_MODE_ARG)) { + return ERROR_SMIH; + } + } + // uhs mode configuration + if (pSmihConfig->uhsModeSelect != 0) { + while (1) { + // ask card about uhs support modes capability + if (RSI_OK != RSI_SDIOH_WriteCommandCmd52(pSmihConfig, CHECK_UHS_SUPPORT_MODES)) { + return ERROR_SMIH; + } + if ((pSmihConfig->response[0] & UHS_SUPPORT_BITS)) { + // card supports uhs modes + break; + } + } + // Send UHS mode to the slave + switch (pSmihConfig->uhsModeSelect) { + // configure uhs modes + case UHS_SDR12: + break; + case UHS_SDR25: + if (RSI_OK != RSI_SDIOH_WriteCommandCmd52(pSmihConfig, UHS_1_SDR25_MODE_ARG)) { + return ERROR_SMIH; + } + break; + case UHS_SDR50: + if (RSI_OK != RSI_SDIOH_WriteCommandCmd52(pSmihConfig, UHS_1_SDR50_MODE_ARG)) { + return ERROR_SMIH; + } + break; + case UHS_SDR104: + if (RSI_OK != RSI_SDIOH_WriteCommandCmd52(pSmihConfig, UHS_1_SDR104_MODE_ARG)) { + return ERROR_SMIH; + } + break; + case UHS_DDR50: + if (RSI_OK != RSI_SDIOH_WriteCommandCmd52(pSmihConfig, UHS_1_DDR50_MODE_ARG)) { + return ERROR_SMIH; + } + break; + default: + return INVALID_PARAMETERS; + } + } + } + return RSI_OK; +} +#endif diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_sdmem.c b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_sdmem.c new file mode 100644 index 000000000..621253722 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_sdmem.c @@ -0,0 +1,1242 @@ +/******************************************************************************* +* @file rsi_sdmem.c +* @brief +******************************************************************************* +* # License +* Copyright 2022 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +// Include Files + +#include "rsi_ccp_user_config.h" +#if defined(CHIP_9118) + +#include "clock_update.h" + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_SDMEM_GoIdleStateCmd0(SMIH_CARD_CONFIG_T *pSmihConfig) + * @brief This API is used to send the CMD0 to the memory card. + * @param[in] pSmihConfig : Pointer to the smih config structure. + * @return RSI_OK : If the command sent successfully + * ERROR_TIMEOUT : If the command error timeout occures. + */ +rsi_error_t RSI_SDMEM_GoIdleStateCmd0(SMIH_CARD_CONFIG_T *pSmihConfig) +{ + SMIH_TRANSFER_T transfer = { 0 }; + SMIH_CMD_FEILD_T cmd = { 0 }; + SMIH_DATA_FEILD_T data = { 0 }; + + data.blockSize = 0x0; + data.blockCount = 0x0; + data.data = NULL; + data.direction = SMIH_WRITE_DIRECTION; + cmd.cmdIdx = 0; + cmd.cmdArg = 0x0; + cmd.responseTypeSelect = SMIH_NO_RESPONSE; + + transfer.command = &cmd; + transfer.data = &data; + + // transfer Command + if (RSI_OK != pSmihConfig->cmd_transfer(&transfer)) { + return ERROR_SMIH; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_SDMEM_SendCardInterfaceConditionCmd8(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t Arg) + * @brief This API is used to send interface condition command(Cmd8). + * @param[in] pSmihConfig : Pointer to the smih config structure. + * @param[in] Arg : Command argument to send + * @return RSI_OK : If command sent successfully + * ERROR_TIMEOUT : If command error timeout occures. + */ +rsi_error_t RSI_SDMEM_SendCardInterfaceConditionCmd8(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t Arg) +{ + SMIH_TRANSFER_T transfer = { 0 }; + SMIH_CMD_FEILD_T cmd = { 0 }; + SMIH_DATA_FEILD_T data = { 0 }; + + data.blockSize = 0x0; + data.blockCount = 0x0; + data.data = NULL; + data.direction = SMIH_WRITE_DIRECTION; + cmd.cmdArg = Arg; + cmd.cmdIdx = CMD_8; + cmd.responseTypeSelect = SMIH_RESPONSE_R1R5R6R7; + + transfer.command = &cmd; + transfer.data = &data; + + // transfer Command + if (RSI_OK != pSmihConfig->cmd_transfer(&transfer)) { + return ERROR_SMIH; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_SDMEM_SendApplicationCommandCmd55(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t Arg) + * @brief This API is used to send the application command(CMD55) to the memory card. + * @param[in] pSmihConfig : Pointer to the smih config structure. + * @param[in] Arg : Argument to the command + * @return RSI_OK : If the command sent successfully + * ERROR_TIMEOUT : If the command error timeout occures. + */ +rsi_error_t RSI_SDMEM_SendApplicationCommandCmd55(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t Arg) +{ + SMIH_TRANSFER_T transfer = { 0 }; + SMIH_CMD_FEILD_T cmd = { 0 }; + SMIH_DATA_FEILD_T data = { 0 }; + + data.data = NULL; + data.blockSize = 0x0; + data.blockCount = 0x0; + data.direction = SMIH_WRITE_DIRECTION; + cmd.cmdIdx = CMD_55; + cmd.cmdArg = Arg << 16; + cmd.responseTypeSelect = SMIH_RESPONSE_R1R5R6R7; + + transfer.command = &cmd; + transfer.data = &data; + + // transfer Command + if (RSI_OK != pSmihConfig->cmd_transfer(&transfer)) { + return ERROR_SMIH; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_SDMEM_SetCardOperationConditionAcmd41(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t Arg) + * @brief This API is used to send operation condition command(Acmd41). + * @param[in] Arg : Command argument to send + * @param[in] pSmihConfig : Pointer to the Command info structure + * @return RSI_OK : If the command sent successfully + * ERROR_TIMEOUT : If the command error timeout occures. + */ +rsi_error_t RSI_SDMEM_SetCardOperationConditionAcmd41(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t Arg) +{ + SMIH_TRANSFER_T transfer = { 0 }; + SMIH_CMD_FEILD_T cmd = { 0 }; + SMIH_DATA_FEILD_T data = { 0 }; + + data.data = NULL; + data.blockSize = 0x0; + data.blockCount = 0x0; + data.direction = SMIH_WRITE_DIRECTION; + cmd.cmdIdx = (CMD_40_hex + CMD_41); + cmd.cmdArg = Arg; + cmd.responseTypeSelect = SMIH_RESPONSE_R3R4; + + transfer.command = &cmd; + transfer.data = &data; + + if (RSI_OK == RSI_SDMEM_SendApplicationCommandCmd55(pSmihConfig, pSmihConfig->rca)) { + // transfer Command + if (RSI_OK != pSmihConfig->cmd_transfer(&transfer)) { + return ERROR_SMIH; + } + } else { + return ERROR_SMIH; + } + memcpy((void *)&pSmihConfig->ocr, &transfer.command->response[0], sizeof(pSmihConfig->ocr)); + if (0 == (transfer.command->response[0] & ACMD41_BUSY_BIT)) { + return ERROR_SMIH; //operation is in progress + } + pSmihConfig->cardType = SMIH_CARD_STANDARD; + if (0 != (transfer.command->response[0] & ACMD41_OCR_BIT)) { + pSmihConfig->cardType = SMIH_CARD_HIGH_CAPACITY; + } else { + pSmihConfig->cardType = SMIH_CARD_STANDARD; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_SDMEM_SwitchVoltageCmd11(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t CmdArg) + * @brief This API is used to send voltage switch command(SDIO_CMD11). + * @param[in] pSmihConfig : Pointer to the Command info structure + * @param[in] Arg : Command argument to send + * @return RSI_OK : If the command sent successfully + * ERROR_TIMEOUT : If the command error timeout occures. + */ +rsi_error_t RSI_SDMEM_SwitchVoltageCmd11(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t CmdArg) +{ + SMIH_TRANSFER_T transfer = { 0 }; + SMIH_CMD_FEILD_T cmd = { 0 }; + SMIH_DATA_FEILD_T data = { 0 }; + + data.data = NULL; + data.blockSize = 0; + data.blockCount = 0; + data.direction = SMIH_WRITE_DIRECTION; + cmd.cmdIdx = CMD_11; + cmd.cmdArg = 0; + cmd.responseTypeSelect = SMIH_RESPONSE_R1R5R6R7; + + transfer.command = &cmd; + transfer.data = &data; + + // transfer Command + if (RSI_OK != pSmihConfig->cmd_transfer(&transfer)) { + return ERROR_SMIH; + } else { + // set Relative Card Address + pSmihConfig->rca = transfer.command->response[0] >> 16; + return RSI_OK; + } +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_SDMEM_SendCidCmd2(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t Arg) + * @brief This API is used to send CMD2(to get CID of the card). + * @param[in] pSmihConfig : Pointer to the Command info structure + * @param[in] Arg : Command argument to send + * @return RSI_OK : If the command sent successfully + * ERROR_TIMEOUT : If the command error timeout occures. + */ +rsi_error_t RSI_SDMEM_SendCidCmd2(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t Arg) +{ + uint32_t i = 0; + SMIH_TRANSFER_T transfer = { 0 }; + SMIH_CMD_FEILD_T cmd = { 0 }; + SMIH_DATA_FEILD_T data = { 0 }; + + data.data = NULL; + data.blockSize = 0x0; + data.blockCount = 0x0; + data.direction = SMIH_WRITE_DIRECTION; + cmd.cmdIdx = CMD_2; + cmd.cmdArg = 0; + cmd.responseTypeSelect = SMIH_RESPONSE_R2; + + transfer.command = &cmd; + transfer.data = &data; + + // transfer Command + if (RSI_OK == pSmihConfig->cmd_transfer(&transfer)) { + for (i = 0; i < 15; i++) { + pSmihConfig->cid[i] = *((uint8_t *)(transfer.command->response) + (14 - i)); + } + return RSI_OK; + } + return ERROR_SMIH; +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_SDIOH_SendRelativeAddressCmd3(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t CmdArg) + * @brief This API is used to send CMD3(send card relative address). + * @param[in] pSmihConfig : Pointer to the Command info structure + * @param[in] CmdArg : Command argument to send + * @return RSI_OK : If command sent successfully + * ERROR_TIMEOUT : If command error timeout occures. + */ +rsi_error_t RSI_SDIOH_SendRelativeAddressCmd3(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t CmdArg) +{ + SMIH_TRANSFER_T transfer = { 0 }; + SMIH_CMD_FEILD_T cmd = { 0 }; + SMIH_DATA_FEILD_T data = { 0 }; + + data.data = NULL; + data.blockSize = 0; + data.blockCount = 0; + data.direction = SMIH_WRITE_DIRECTION; + cmd.cmdIdx = CMD_3; + cmd.cmdArg = 0; + cmd.responseTypeSelect = SMIH_RESPONSE_R1R5R6R7; + + transfer.command = &cmd; + transfer.data = &data; + + // transfer Command + if (RSI_OK == pSmihConfig->cmd_transfer(&transfer)) { + // set Relative card address + pSmihConfig->rca = (transfer.command->response[0] >> 16); + return RSI_OK; + } else { + return ERROR_SMIH; + } +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_SDMEM_SendCsdCmd9(SMIH_CARD_CONFIG_T *pSmihConfig) + * @brief This API is used to send CMD9(CSD) to the sd card + * @param[in] pSmihConfig : Pointer to the Command info structure + * @return RSI_OK : If the command sent successfully + * ERROR_TIMEOUT : If the command error timeout occures. + */ +rsi_error_t RSI_SDMEM_SendCsdCmd9(SMIH_CARD_CONFIG_T *pSmihConfig) +{ + SMIH_TRANSFER_T transfer = { 0 }; + SMIH_CMD_FEILD_T cmd = { 0 }; + SMIH_DATA_FEILD_T data = { 0 }; + CSD_REG_VERSION1_T *pSdCsd = NULL; + CSD_REG_VERSION2_T *pSdhcCsd = NULL; + uint32_t u32NumSector = 0; + uint32_t u32Csize = 0; + uint32_t u32CsizeMulti = 0; + + data.data = NULL; + data.blockSize = 0x0; + data.blockCount = 0x0; + data.direction = SMIH_WRITE_DIRECTION; + cmd.cmdIdx = CMD_9; + cmd.cmdArg = pSmihConfig->rca << 16; + cmd.responseTypeSelect = SMIH_RESPONSE_R2; + + transfer.command = &cmd; + transfer.data = &data; + + // transfer Command + if (RSI_OK != pSmihConfig->cmd_transfer(&transfer)) { + return ERROR_SMIH; + } + memcpy(pSmihConfig->csd, transfer.command->response, sizeof(transfer.command->response)); + + pSdCsd = (CSD_REG_VERSION1_T *)&pSmihConfig->csd[0]; + pSdhcCsd = (CSD_REG_VERSION2_T *)&pSmihConfig->csd[0]; + + if (pSmihConfig->cardType == SMIH_CARD_STANDARD) { + // Standard Capacity card + u32Csize = + ((unsigned int)pSdCsd->deviceSize3 << 10) + ((unsigned int)pSdCsd->deviceSize2 << 2) + pSdCsd->deviceSize1; + u32CsizeMulti = (pSdCsd->deviceSizeMultiplier2 << 1) + pSdCsd->deviceSizeMultiplier1; + u32NumSector = (u32Csize + 1) << (u32CsizeMulti + 2); + if (pSdCsd->readBlockLength == 0x0A) { + u32NumSector *= 2; + } else if (pSdCsd->readBlockLength == 0x0B) { + u32NumSector *= 4; + } + } else { + // high capacity card + u32Csize = + ((unsigned int)pSdhcCsd->deviceSize3 << 16) + ((unsigned int)pSdhcCsd->deviceSize2 << 8) + pSdhcCsd->deviceSize1; + u32NumSector = (u32Csize + 1) * 1024; + } + pSmihConfig->maxSectorNum = u32NumSector; + + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_SDMEM_SelectCardCmd7(SMIH_CARD_CONFIG_T *pSmihConfig) + * @brief This API is used to send SDIO_CMD7(to select the card). + * @param[in] pSmihConfig : Pointer to the Command info structure + * @return RSI_OK : If command sent successfully + * ERROR_TIMEOUT : If command error timeout occures. + */ +rsi_error_t RSI_SDMEM_SelectCardCmd7(SMIH_CARD_CONFIG_T *pSmihConfig) +{ + SMIH_TRANSFER_T transfer = { 0 }; + SMIH_CMD_FEILD_T cmd = { 0 }; + SMIH_DATA_FEILD_T data = { 0 }; + + data.data = NULL; + data.blockSize = 0; + data.blockCount = 0; + data.direction = SMIH_WRITE_DIRECTION; + + cmd.cmdIdx = CMD_7; + cmd.cmdArg = pSmihConfig->rca << 16; + cmd.responseTypeSelect = SMIH_RESPONSE_R1BR5B; + + transfer.command = &cmd; + transfer.data = &data; + + // transfer Command + if (RSI_OK != pSmihConfig->cmd_transfer(&transfer)) { + return ERROR_SMIH; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_SDMEM_SetBusWidthAcmd6(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t Arg) + * @brief This API is used to send ACMD6(set bus width command to the card). + * @param[in] pSmihConfig : Pointer to the Command info structure + * @param[in] Arg : Command argument to send + * @return RSI_OK : If command sent successfully + * ERROR_TIMEOUT : If command error timeout occures. + */ +rsi_error_t RSI_SDMEM_SetBusWidthAcmd6(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t Arg) +{ + SMIH_TRANSFER_T transfer = { 0 }; + SMIH_CMD_FEILD_T cmd = { 0 }; + SMIH_DATA_FEILD_T data = { 0 }; + + data.data = NULL; + data.blockSize = 0; + data.blockCount = 0; + data.direction = SMIH_WRITE_DIRECTION; + + cmd.cmdIdx = (CMD_40_hex + CMD_6); + cmd.cmdArg = Arg; + cmd.responseTypeSelect = SMIH_RESPONSE_R1R5R6R7; + + transfer.command = &cmd; + transfer.data = &data; + + // transfer Command + if (RSI_OK != RSI_SDMEM_SendApplicationCommandCmd55(pSmihConfig, pSmihConfig->rca)) { + return ERROR_SMIH; + } + // transfer Command + if (RSI_OK != pSmihConfig->cmd_transfer(&transfer)) { + return ERROR_SMIH; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_SDMEM_OperationSwitchFunctionReadCmd6(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t Argument) + * @brief This API is used to send the switch function read command(asks card about its capability). + * @param[in] pSmihConfig : Pointer to the Command info structure + * @param[in] Argument : Argument to the command + * @return RSI_OK : If the command sent successfully + * ERROR_TIMEOUT : If the command error timeout occures. + */ +rsi_error_t RSI_SDMEM_OperationSwitchFunctionReadCmd6(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t Argument) +{ + SMIH_TRANSFER_T transfer = { 0 }; + SMIH_CMD_FEILD_T cmd = { 0 }; + SMIH_DATA_FEILD_T data = { 0 }; + + data.data = 0; + data.blockSize = 1; + data.blockCount = 1; + data.direction = SMIH_READ_DIRECTION; + + cmd.cmdIdx = CMD_6; + cmd.cmdArg = Argument; + cmd.responseTypeSelect = SMIH_RESPONSE_R1R5R6R7; + + transfer.command = &cmd; + transfer.data = &data; + + // transfer command + if (RSI_OK != pSmihConfig->cmd_transfer(&transfer)) { + return ERROR_SMIH; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_SDMEM_GetCardOperationConditionAcmd41(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t Arg) + * @brief This API is used to send operation condition command(ACMD41). + * @param[in] pSmihConfig : Pointer to the smih command info structure + * @param[in] Arg : Command argument to send + * @return RSI_OK : If command sent successfully + * ERROR_TIMEOUT : If command error timeout occures. + */ +rsi_error_t RSI_SDMEM_GetCardOperationConditionAcmd41(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t Arg) +{ + SMIH_TRANSFER_T transfer = { 0 }; + SMIH_CMD_FEILD_T cmd = { 0 }; + SMIH_DATA_FEILD_T data = { 0 }; + + data.data = NULL; + data.blockSize = 0x0; + data.blockCount = 0x0; + data.direction = SMIH_WRITE_DIRECTION; + + cmd.cmdIdx = (CMD_40_hex + CMD_41); + cmd.cmdArg = Arg; + cmd.responseTypeSelect = SMIH_RESPONSE_R3R4; + + // transfer Command + if (RSI_OK != RSI_SDMEM_SendApplicationCommandCmd55(pSmihConfig, pSmihConfig->rca)) { + return ERROR_SMIH; + } + transfer.command = &cmd; + transfer.data = &data; + + // transfer Command + if (RSI_OK != pSmihConfig->cmd_transfer(&transfer)) { + return ERROR_SMIH; + } + + memcpy((void *)&pSmihConfig->ocr, &transfer.command->response[0], sizeof(pSmihConfig->ocr)); + if (0 == Arg) { + + } else if ((transfer.command->response[0] & ACMD41_BUSY_BIT) == 0) { + // set mode + return ERROR_SMIH; //operation is in progress + } + pSmihConfig->cardType = SMIH_CARD_STANDARD; + if ((transfer.command->response[0] & ACMD41_OCR_BIT) != 0) { + pSmihConfig->cardType = SMIH_CARD_HIGH_CAPACITY; + } else { + pSmihConfig->cardType = SMIH_CARD_STANDARD; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_SDMEM_CardBusWidthConfig(SMIH_CARD_CONFIG_T *pSmihConfig, uint8_t BusWidth) + * @brief This API is used to configure the bus width. + * @param[in] pSmihConfig : Pointer to the Command info structure + * @param[in] BusWidth : bus width mode + * possible values are 0-1bit + * 1-4bit + * 2-8bit + * @return RSI_OK : If command sent successfully + * ERROR_TIMEOUT : If command error timeout occures. + */ +rsi_error_t RSI_SDMEM_CardBusWidthConfig(SMIH_CARD_CONFIG_T *pSmihConfig, uint8_t BusWidth) +{ + uint32_t cmdArg = 0; + boolean_t hostMode; + if (BusWidth == SMIH_BUS_WIDTH1) { + cmdArg = 0; + hostMode = FALSE; + } else if (BusWidth == SMIH_BUS_WIDTH4) { + cmdArg = 0x2; //Need to talk with spandana + hostMode = TRUE; + } else if (BusWidth == SMIH_BUS_WIDTH8) { + cmdArg = 0x2; + hostMode = TRUE; + } + // Ask card about its capability + if (RSI_OK != RSI_SDMEM_SetBusWidthAcmd6(pSmihConfig, cmdArg)) { + return ERROR_SMIH; + } else { + // set bus width mode in controller + smih_bus_width_set(hostMode); + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_SDMEM_OperationSwitchFunctionWriteCmd6(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t Argument) + * @brief This API is used to send the switch function command. + * @param[in] pSmihConfig : Pointer to the Command info structure + * @param[in] Argument : Argument to the command + * @return RSI_OK : If the command sent successfully + * ERROR_TIMEOUT : If the command error timeout occures. + */ +rsi_error_t RSI_SDMEM_OperationSwitchFunctionWriteCmd6(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t Argument) +{ + SMIH_TRANSFER_T transfer = { 0 }; + SMIH_CMD_FEILD_T cmd = { 0 }; + SMIH_DATA_FEILD_T data = { 0 }; + + data.data = 0; + data.blockSize = 0; + data.blockCount = 0; + data.direction = SMIH_WRITE_DIRECTION; + + cmd.cmdIdx = CMD_6; + cmd.cmdArg = Argument; + cmd.responseTypeSelect = SMIH_RESPONSE_R1R5R6R7; + + transfer.command = &cmd; + transfer.data = &data; + + // transfer Command + if (RSI_OK != pSmihConfig->cmd_transfer(&transfer)) { + return ERROR_SMIH; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_SDMEM_BlocksWrite(SMIH_CARD_CONFIG_T *pSmihConfig, + const uint8_t *DataIn, + uint32_t BlockIndex, + uint32_t BlockCount) + * @brief This API is used to write multiple blocks of data to the sd card. + * @param[in] pSmihConfig : Pointer to the sd card config structure + * @param[in] DataIn : Data buffer to send + * @param[in] BlockIndex : block index value + * @param[in] BlockCount : blocks count value + * @return RSI_OK : If the command sent successfully + * ERROR_TIMEOUT : If the command error timeout occures. + */ +rsi_error_t RSI_SDMEM_BlocksWrite(SMIH_CARD_CONFIG_T *pSmihConfig, + const uint8_t *DataIn, + uint32_t BlockIndex, + uint32_t BlockCount) +{ + SMIH_TRANSFER_T transfer = { 0 }; + SMIH_CMD_FEILD_T cmd = { 0 }; + SMIH_DATA_FEILD_T data = { 0 }; + if (pSmihConfig == NULL || DataIn == NULL) { + return INVALID_PARAMETERS; + } + if (SMIH_CARD_STANDARD == pSmihConfig->cardType) { + BlockIndex = BlockIndex << 9; + } + if (BlockCount == 1) { + // single block write + if (pSmihConfig->maxSectorNum < BlockIndex) { + return INVALID_PARAMETERS; + } + data.data = DataIn; + data.blockSize = BLOCK_SIZE_512; + data.blockCount = 1; + data.direction = SMIH_WRITE_DIRECTION; + + cmd.cmdIdx = CMD_24; + cmd.cmdArg = BlockIndex; + cmd.responseTypeSelect = SMIH_RESPONSE_R1R5R6R7; + } else { + // multiple block write + if (((pSmihConfig->maxSectorNum - BlockIndex) < BlockCount) + || (pSmihConfig->maxSectorNum < (BlockIndex + BlockCount))) { + return INVALID_PARAMETERS; + } + data.data = DataIn; + data.blockSize = BLOCK_SIZE_512; + data.blockCount = BlockCount; + data.direction = SMIH_WRITE_DIRECTION; + + cmd.cmdIdx = CMD_25; + cmd.cmdArg = BlockIndex; + cmd.responseTypeSelect = SMIH_RESPONSE_R1R5R6R7; + } + transfer.command = &cmd; + transfer.data = &data; + + // transfer Command + if (RSI_OK != pSmihConfig->cmd_transfer(&transfer)) { + return ERROR_SMIH; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_SDMEM_BlocksRead(SMIH_CARD_CONFIG_T *pSmihConfig, + uint8_t *DataOut, + uint32_t BlockIndex, + uint32_t BlockCount) + * @brief This API is used to read multiple blocks of data from the sd card. + * @param[in] pSmihConfig : Pointer to the sd card config structure + * @param[in] DataIn : Data buffer to send + * @param[in] BlockIndex : block index value + * @param[in] BlockCount : blocks count value + * @return RSI_OK : Command sent successfully + * ERROR_TIMEOUT : Command error timeout occured. + */ +rsi_error_t RSI_SDMEM_BlocksRead(SMIH_CARD_CONFIG_T *pSmihConfig, + uint8_t *DataOut, + uint32_t BlockIndex, + uint32_t BlockCount) +{ + SMIH_TRANSFER_T transfer = { 0 }; + SMIH_CMD_FEILD_T cmd = { 0 }; + SMIH_DATA_FEILD_T data = { 0 }; + + if (NULL == pSmihConfig || NULL == DataOut) { + return INVALID_PARAMETERS; + } + if (SMIH_CARD_STANDARD == pSmihConfig->cardType) { + BlockIndex = BlockIndex << 9; + } + if (BlockCount == 1) { + // single block read + if (pSmihConfig->maxSectorNum < BlockIndex) { + return INVALID_PARAMETERS; + } + cmd.cmdIdx = CMD_17; + cmd.cmdArg = BlockIndex; + data.data = DataOut; + cmd.responseTypeSelect = SMIH_RESPONSE_R1R5R6R7; + + data.blockSize = BLOCK_SIZE_512; + data.blockCount = 1; + data.direction = SMIH_READ_DIRECTION; + } else { + // multiple block read + if (((pSmihConfig->maxSectorNum - BlockIndex) < BlockCount) + || (pSmihConfig->maxSectorNum < (BlockIndex + BlockCount))) { + return INVALID_PARAMETERS; + } + data.data = DataOut; + data.blockSize = BLOCK_SIZE_512; + data.blockCount = BlockCount; + data.direction = SMIH_READ_DIRECTION; + cmd.cmdIdx = CMD_18; + cmd.cmdArg = BlockIndex; + cmd.responseTypeSelect = SMIH_RESPONSE_R1R5R6R7; + } + transfer.command = &cmd; + transfer.data = &data; + + // transfer Command + if (RSI_OK != pSmihConfig->cmd_transfer(&transfer)) { + return ERROR_SMIH; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_SDMEM_EnableHighSpeed(SMIH_CARD_CONFIG_T *pSmihConfig, boolean_t HighSpeed, uint32_t Clock) + * @brief This API is used to enable high speed mode + * @param[in] pSmihConfig : Pointer to the smih card configuration structure + * @param[in] HighSpeed : High speed enable bit + * 1- for high speed enable. + * 0- for high speed disable. + * @param[in] Clock : Clock frequency + * @return RSI_OK : If the command sent successfully + * ERROR_TIMEOUT : If the command error timeout occures. + */ +rsi_error_t RSI_SDMEM_EnableHighSpeed(SMIH_CARD_CONFIG_T *pSmihConfig, boolean_t HighSpeed, uint32_t Clock) +{ + uint32_t actualClock = 0; + uint32_t highSpeedValue = 0; + uint32_t arg = 0; + + if (HighSpeed == 0) { + actualClock = 400000; + } else { + actualClock = Clock; + highSpeedValue = 1; + } + arg = (BIT(31) | 0xFFF0); + arg |= (highSpeedValue)&0xF; + + // Send switch command + if (RSI_OK != RSI_SDMEM_OperationSwitchFunctionWriteCmd6(pSmihConfig, arg)) { + return ERROR_SMIH; + } else { + smih_clock_config(pSmihConfig, actualClock); + SMIH->SMIH_HOST_CONTROL_1_REGISTER_b.HIGH_SPEED_ENABLE = 0x1; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn void RSI_SDMEM_PinMux(void) + * @brief This API is used to configure GPIOs for SDMEM operations. + * @return none + */ +void RSI_SDMEM_PinMux(void) +{ + // If GPIO_SET1 is equals to 0 then set2 gpios of sdmem will be used +#if (GPIO_SET1 == 0) + RSI_EGPIO_HostPadsGpioModeEnable(SD_CLK_PIN); + RSI_EGPIO_HostPadsGpioModeEnable(SD_CMD_PIN); + RSI_EGPIO_HostPadsGpioModeEnable(SD_D0_PIN); + RSI_EGPIO_HostPadsGpioModeEnable(SD_D1_PIN); + RSI_EGPIO_HostPadsGpioModeEnable(SD_D2_PIN); + RSI_EGPIO_HostPadsGpioModeEnable(SD_D3_PIN); +#endif + RSI_EGPIO_PadSelectionEnable(SD_CLK_PAD); + RSI_EGPIO_PadSelectionEnable(SD_CMD_PAD); + RSI_EGPIO_PadSelectionEnable(SD_D0_PAD); + RSI_EGPIO_PadSelectionEnable(SD_D1_PAD); + RSI_EGPIO_PadSelectionEnable(SD_D2_PAD); + RSI_EGPIO_PadSelectionEnable(SD_D3_PAD); + + RSI_EGPIO_PadReceiverEnable(SD_CLK_PIN); + RSI_EGPIO_PadReceiverEnable(SD_CMD_PIN); + RSI_EGPIO_PadReceiverEnable(SD_D0_PIN); + RSI_EGPIO_PadReceiverEnable(SD_D1_PIN); + RSI_EGPIO_PadReceiverEnable(SD_D2_PIN); + RSI_EGPIO_PadReceiverEnable(SD_D3_PIN); + + RSI_EGPIO_PadDriverDisableState(SD_CMD_PIN, Pullup); + RSI_EGPIO_PadDriverDisableState(SD_D0_PIN, Pullup); + RSI_EGPIO_PadDriverDisableState(SD_D1_PIN, Pullup); + RSI_EGPIO_PadDriverDisableState(SD_D2_PIN, Pullup); + RSI_EGPIO_PadDriverDisableState(SD_D3_PIN, Pullup); + + RSI_EGPIO_SetPinMux(EGPIO, 0, SD_CLK_PIN, SD_CLK_MUX); + RSI_EGPIO_SetPinMux(EGPIO, 0, SD_CMD_PIN, SD_CMD_MUX); + RSI_EGPIO_SetPinMux(EGPIO, 0, SD_D0_PIN, SD_D0_MUX); + RSI_EGPIO_SetPinMux(EGPIO, 0, SD_D1_PIN, SD_D1_MUX); + RSI_EGPIO_SetPinMux(EGPIO, 0, SD_D2_PIN, SD_D2_MUX); + RSI_EGPIO_SetPinMux(EGPIO, 0, SD_D3_PIN, SD_D3_MUX); + +#if _8BIT_MODE + RSI_EGPIO_PadSelectionEnable(SD_D4_PAD); + RSI_EGPIO_PadSelectionEnable(SD_D5_PAD); + RSI_EGPIO_PadSelectionEnable(SD_D6_PAD); + RSI_EGPIO_PadSelectionEnable(SD_D7_PAD); + + RSI_EGPIO_PadReceiverEnable(SD_D4_PIN); + RSI_EGPIO_PadReceiverEnable(SD_D5_PIN); + RSI_EGPIO_PadReceiverEnable(SD_D6_PIN); + RSI_EGPIO_PadReceiverEnable(SD_D7_PIN); + + RSI_EGPIO_PadDriverDisableState(SD_D4_PIN, Pullup); + RSI_EGPIO_PadDriverDisableState(SD_D5_PIN, Pullup); + RSI_EGPIO_PadDriverDisableState(SD_D6_PIN, Pullup); + RSI_EGPIO_PadDriverDisableState(SD_D7_PIN, Pullup); + + RSI_EGPIO_SetPinMux(EGPIO, 0, SD_D4_PIN, SD_D4_MUX); + RSI_EGPIO_SetPinMux(EGPIO, 0, SD_D5_PIN, SD_D5_MUX); + RSI_EGPIO_SetPinMux(EGPIO, 0, SD_D6_PIN, SD_D6_MUX); + RSI_EGPIO_SetPinMux(EGPIO, 0, SD_D7_PIN, SD_D7_MUX); +#endif + RSI_EGPIO_PadSelectionEnable(SD_WP_PAD); + RSI_EGPIO_PadSelectionEnable(SD_CD_PAD); + + RSI_EGPIO_PadReceiverEnable(SD_CD_PIN); + RSI_EGPIO_PadReceiverEnable(SD_WP_PIN); + + RSI_EGPIO_PadDriverDisableState(SD_WP_PIN, Pulldown); + RSI_EGPIO_PadDriverDisableState(SD_CD_PIN, Pulldown); + + RSI_EGPIO_SetPinMux(EGPIO, 0, SD_CD_PIN, SD_CD_MUX); + RSI_EGPIO_SetPinMux(EGPIO, 0, SD_WP_PIN, SD_WP_MUX); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_SDMEM_Enumeration(SMIH_CARD_CONFIG_T *pSmihConfig, ARM_SMIH_SignalEvent_t Event) + * @brief This API is used for SD memory enumeration process + * @param[in] pSmihConfig : Pointer to the smih card configuration structure + * @param[in] Event : event handler to be register + * @return RSI_OK : If commands sent successfully in enumeration process. + * ERROR_TIMEOUT : If commands error timeout occures. + */ +rsi_error_t RSI_SDMEM_Enumeration(SMIH_CARD_CONFIG_T *pSmihConfig, ARM_SMIH_SignalEvent_t Event) +{ + uint8_t val = 0; + uint32_t arg = 0; + uint32_t i; + SMIH_CARD_CONFIG_T *SmihInfo = NULL; + if (pSmihConfig == 0) { + return INVALID_PARAMETERS; + } + // Configure gpios in smih mode + RSI_SDMEM_PinMux(); + + if (RSI_OK != RSI_SD_HostInit(pSmihConfig, Event, 1)) { + return ERROR_SMIH; + } else { + // Commands for sdio enumeration + rsi_delay_ms(5); + + // Reset card(send command 0) + if (RSI_OK != RSI_SDMEM_GoIdleStateCmd0(pSmihConfig)) { + return ERROR_SMIH; + } + + // send interface condition + if (RSI_OK != RSI_SDMEM_SendCardInterfaceConditionCmd8(pSmihConfig, 0x1AA)) { + val = 0; + } else { + val = 1; + } + // send ACMD41 + if (RSI_OK != RSI_SDMEM_GetCardOperationConditionAcmd41(pSmihConfig, 0x0)) { + return ERROR_SMIH; + } + if (pSmihConfig->uhsModeSelect == 0) { + arg = ACMD41_VOLTAGE; + if (1 == val) { + arg |= ACMD41_HCS; + } + } else { + arg = ACMD41_UHS_REQ; + if (1 == val) { + arg |= ACMD41_HCS; + } + } + // send operation condition + i = 5000; + while (i != 0) { + if (RSI_SDMEM_SetCardOperationConditionAcmd41(pSmihConfig, arg) == RSI_OK) { + break; + } + i--; + } + // configure uhs mode if enabled + if (pSmihConfig->uhsModeSelect != 0) { + rsi_delay_ms(5); + RSI_SDMEM_SwitchVoltageCmd11(SmihInfo, 0x0); + M4CLK->SD_MEM_CLOCK_REG_b.SD_MEM_INTF_CLK_SEL = 0x7; + // wait for some time + rsi_delay_ms(5); + switch (pSmihConfig->uhsModeSelect) { + case UHS_NONE: + break; + case UHS_SDR12: + break; + case UHS_SDR25: + SMIH->SMIH_HOST_CONTROL_2_REGISTER_b.UHS_MODE_SELECT = 0x1; + break; + case UHS_SDR50: + SMIH->SMIH_HOST_CONTROL_2_REGISTER_b.UHS_MODE_SELECT = 0x2; + break; + case UHS_SDR104: + SMIH->SMIH_HOST_CONTROL_2_REGISTER_b.UHS_MODE_SELECT = 0x3; + break; + case UHS_DDR50: + break; + default: + return INVALID_PARAMETERS; + } + // enable 1.8v signalling bit + SMIH->SMIH_HOST_CONTROL_2_REGISTER_b._1_8V_SIGNALING_ENABLE = 0x1; + RSI_CLK_SdMemClkConfig(M4CLK, 1, SDMEM_SOCPLLCLK, 1); + + // wait for some + rsi_delay_ms(5); + } + // send cmd2 + if (RSI_OK != RSI_SDMEM_SendCidCmd2(pSmihConfig, 0x0)) { + return ERROR_SMIH; + } + // send cmd3 + if (RSI_OK != RSI_SDIOH_SendRelativeAddressCmd3(pSmihConfig, 0x0)) { + return ERROR_SMIH; + } + // send cmd9 + if (RSI_OK != RSI_SDMEM_SendCsdCmd9(pSmihConfig)) { + return ERROR_SMIH; + } + // select card :send rca as argument + if (RSI_OK != RSI_SDMEM_SelectCardCmd7(pSmihConfig)) { + return ERROR_SMIH; + } + // bus width configuration + if (pSmihConfig->busWidthMode == 1) { + if (RSI_OK != RSI_SDMEM_CardBusWidthConfig(pSmihConfig, SMIH_BUS_WIDTH4)) { + return ERROR_SMIH; + } + } + // enable high speed mode + if (TRUE == pSmihConfig->highSpeedEnable) { + rsi_delay_ms(1); + if (RSI_OK != RSI_SDMEM_EnableHighSpeed(pSmihConfig, TRUE, 20000000)) { + return ERROR_SMIH; + } + rsi_delay_ms(10); + } + if (pSmihConfig->uhsModeSelect != 0) { + switch (pSmihConfig->uhsModeSelect) { + case UHS_SDR12: + break; + case UHS_SDR25: + // uhs support asking to card + if (RSI_OK != RSI_SDMEM_OperationSwitchFunctionReadCmd6(pSmihConfig, 0x00000001)) { + return ERROR_SMIH; + } + // switching mode + if (RSI_OK != RSI_SDMEM_OperationSwitchFunctionWriteCmd6(pSmihConfig, 0x00000001)) { + return ERROR_SMIH; + } + break; + case UHS_SDR50: + // uhs support asking to card + if (RSI_OK != RSI_SDMEM_OperationSwitchFunctionReadCmd6(pSmihConfig, 0x00000002)) { + return ERROR_SMIH; + } + // switching mode + if (RSI_OK != RSI_SDMEM_OperationSwitchFunctionWriteCmd6(pSmihConfig, 0x00000002)) { + return ERROR_SMIH; + } + break; + case UHS_SDR104: + // uhs support asking to card + if (RSI_OK != RSI_SDMEM_OperationSwitchFunctionReadCmd6(pSmihConfig, 0x00000003)) { + return ERROR_SMIH; + } + // switching mode + if (RSI_OK != RSI_SDMEM_OperationSwitchFunctionWriteCmd6(pSmihConfig, 0x00000003)) { + return ERROR_SMIH; + } + break; + default: + return INVALID_PARAMETERS; + } + } + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_SDMMC_Enumeration(SMIH_CARD_CONFIG_T *pSmihConfig, ARM_SMIH_SignalEvent_t Event) + * @brief This API is used for SD MMC card enumeration process + * @param[in] pSmihConfig : Pointer to the smih card configuration structure + * @param[in] Event : event handler to be register + * @return RSI_OK : If MMC card enumeration successfully done + * ERROR_TIMEOUT : If the commands error timeout occures. + */ +rsi_error_t RSI_SDMMC_Enumeration(SMIH_CARD_CONFIG_T *pSmihConfig, ARM_SMIH_SignalEvent_t Event) +{ + if (pSmihConfig == 0) { + return INVALID_PARAMETERS; + } + // Configure gpios in smih mode + RSI_SDMEM_PinMux(); + + if (RSI_OK != RSI_SD_HostInit(pSmihConfig, Event, 1)) { + return ERROR_SMIH; + } else { + // Commands for sdio enumeration + rsi_delay_ms(5); + + // Reset card(send command 0) + if (RSI_OK != RSI_SDMEM_GoIdleStateCmd0(pSmihConfig)) { + return ERROR_SMIH; + } + while (1) { + if (RSI_OK == RSI_SDMMC_SendOperationConditionCmd1(pSmihConfig, 0x40FF8000)) { + break; + } + } + // send cmd2 + if (RSI_OK != RSI_SDMEM_SendCidCmd2(pSmihConfig, 0x0)) { + return ERROR_SMIH; + } + // send cmd3 + if (RSI_OK != RSI_SDIOH_SendRelativeAddressCmd3(pSmihConfig, 0x0)) { + return ERROR_SMIH; + } + // select card :send rca as argument + if (RSI_OK != RSI_SDMEM_SelectCardCmd7(pSmihConfig)) { + return ERROR_SMIH; + } + // send csd command to card + if (RSI_OK != RSI_SDMMC_SendExtentCsdCmd(pSmihConfig)) { + return ERROR_SMIH; + } + // bus width configuration + if (pSmihConfig->busWidthMode == 1) { + if (RSI_OK != RSI_SDMMC_ChangeBusWidthMode(pSmihConfig, SMIH_BUS_WIDTH4)) { + return ERROR_SMIH; + } + rsi_delay_ms(5); + } else if (pSmihConfig->busWidthMode == 2) { + if (RSI_OK != RSI_SDMMC_ChangeBusWidthMode(pSmihConfig, SMIH_BUS_WIDTH8)) { + return ERROR_SMIH; + } + rsi_delay_ms(5); + } + // enable high speed mode + if (TRUE == pSmihConfig->highSpeedEnable) { + rsi_delay_ms(1); + if (RSI_OK != RSI_SDMMC_HighSpeedMode(pSmihConfig, TRUE, pSmihConfig->clock)) { + return ERROR_SMIH; + } + rsi_delay_ms(1); + } + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_SDMMC_SendOperationConditionCmd1(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t Arg) + * @brief This API is used to send MMC operation condition command. + * @param[in] pSmihConfig : Pointer to the smih card configuration structure + * @param[in] Arg : Argument to the command + * @return RSI_OK : If the command sent successfully + * ERROR_TIMEOUT : If the command error timeout occures. + */ +rsi_error_t RSI_SDMMC_SendOperationConditionCmd1(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t Arg) +{ + SMIH_TRANSFER_T transfer = { 0 }; + SMIH_CMD_FEILD_T cmd = { 0 }; + SMIH_DATA_FEILD_T data = { 0 }; + + data.blockSize = 0x0; + data.blockCount = 0x0; + data.data = NULL; + data.direction = SMIH_WRITE_DIRECTION; + + cmd.cmdIdx = CMD_1; + cmd.cmdArg = Arg; + cmd.responseTypeSelect = SMIH_RESPONSE_R3R4; + + transfer.command = &cmd; + transfer.data = &data; + + // transfer Command + if (RSI_OK != pSmihConfig->cmd_transfer(&transfer)) { + return ERROR_SMIH; + } + if (transfer.command->response[0] & BIT(31)) { + pSmihConfig->cardType = SMIH_CARD_STANDARD; + if (transfer.command->response[0] & BIT(30)) { + pSmihConfig->cardType = SMIH_CARD_HIGH_CAPACITY; + } + } else { + return ERROR_SMIH; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_SDMMC_SendExtentCsdCmd(SMIH_CARD_CONFIG_T *pSmihConfig) + * @brief This API is used to send csd command to the MMC card. + * @param[in] pSmihConfig : Pointer to the smih card configuration structure + * @return RSI_OK : If the command sent successfully + * ERROR_TIMEOUT : If the command error timeout occures. + */ +rsi_error_t RSI_SDMMC_SendExtentCsdCmd(SMIH_CARD_CONFIG_T *pSmihConfig) +{ + uint8_t ext_csd[BLOCK_SIZE_512] = { 0 }; + SMIH_TRANSFER_T transfer = { 0 }; + SMIH_CMD_FEILD_T cmd = { 0 }; + SMIH_DATA_FEILD_T data = { 0 }; + uint32_t *preadVal = NULL; + + data.blockSize = BLOCK_SIZE_512; + data.blockCount = 1; + data.data = ext_csd; + data.direction = SMIH_READ_DIRECTION; + + cmd.cmdIdx = (CMD_80_hex | CMD_8); //mmc cmd 8 + cmd.cmdArg = pSmihConfig->rca << 16; + cmd.responseTypeSelect = SMIH_RESPONSE_R1R5R6R7; + + transfer.command = &cmd; + transfer.data = &data; + + // transfer Command + if (RSI_OK != pSmihConfig->cmd_transfer(&transfer)) { + return ERROR_SMIH; + } + rsi_delay_ms(10); + + preadVal = (uint32_t *)&ext_csd[212]; + pSmihConfig->maxSectorNum = *preadVal; + + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_SDMMC_ChangeBusWidthMode(SMIH_CARD_CONFIG_T *pSmihConfig, uint8_t bus_wdith) + * @brief This API is used to change bus width mode to MMC card. + * @param[in] pSmihConfig : Pointer to the smih card configuration structure + * @param[in] bus_wdith : bus width mode to be configured + * possible values are SMIH_BUS_WIDTH1 : 1 bit width + * SMIH_BUS_WIDTH4 : 4 bit width + * SMIH_BUS_WIDTH8 : 8 bit width + * @return RSI_OK : If the command sent successfully + * ERROR_TIMEOUT : If the command error timeout occures. + */ +rsi_error_t RSI_SDMMC_ChangeBusWidthMode(SMIH_CARD_CONFIG_T *pSmihConfig, uint8_t bus_wdith) +{ + uint32_t argument = 0; + switch (bus_wdith) { + case SMIH_BUS_WIDTH1: + argument = (0x3 << 24) | (0xB7 << 16) | (0x0 << 8) | (0x0 << 0); + break; + case SMIH_BUS_WIDTH4: + argument = (0x3 << 24) | (0xB7 << 16) | (0x1 << 8) | (0x0 << 0); + break; + case SMIH_BUS_WIDTH8: + argument = (0x3 << 24) | (0xB7 << 16) | (0x2 << 8) | (0x0 << 0); + break; + default: + return INVALID_PARAMETERS; + } + // send switch command + if (RSI_OK != RSI_SDMMC_SwitchFunctionCmd6(pSmihConfig, argument)) { + return ERROR_SMIH; + } + // set bus width + smih_bus_width_set(bus_wdith); + + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_SDMMC_SwitchFunctionCmd6(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t Arg) + * @brief This API is used to send switch mode function command to MMC card. + * @param[in] pSmihConfig : Pointer to the smih card configuration structure + * @param[in] Arg : Command argument to send + * @return RSI_OK : If the command sent successfully + * ERROR_TIMEOUT : If the command error timeout occures. + */ +rsi_error_t RSI_SDMMC_SwitchFunctionCmd6(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t Arg) +{ + SMIH_TRANSFER_T transfer = { 0 }; + SMIH_CMD_FEILD_T cmd = { 0 }; + SMIH_DATA_FEILD_T data = { 0 }; + + data.blockSize = 0; + data.blockCount = 0; + data.data = NULL; + data.direction = SMIH_WRITE_DIRECTION; + cmd.cmdIdx = CMD_6; + cmd.cmdArg = Arg; + cmd.responseTypeSelect = SMIH_RESPONSE_R1BR5B; + + transfer.command = &cmd; + transfer.data = &data; + + // transfer Command + if (RSI_OK != pSmihConfig->cmd_transfer(&transfer)) { + return ERROR_SMIH; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_SDMMC_HighSpeedMode(SMIH_CARD_CONFIG_T *pSmihConfig, boolean_t HighSpeed, uint32_t Clock) + * @brief This API is used to enable high speed mode to MMC card. + * @param[in] pSmihConfig : Pointer to the smih card configuration structure + * @param[in] HighSpeed : high speed value : 1 for enbale + * 0 for disable + * @param[in] Clock : Clock frequency + * @return RSI_OK : If the command sent successfully + * ERROR_TIMEOUT : If the command error timeout occures. + */ +rsi_error_t RSI_SDMMC_HighSpeedMode(SMIH_CARD_CONFIG_T *pSmihConfig, boolean_t HighSpeed, uint32_t Clock) +{ + uint32_t clk = 0; + uint32_t arg = 0; + uint32_t highspeed = 0; + if (HighSpeed == 1) { + highspeed = 1; + clk = Clock; + arg = (0x3 << 24) | (0xB9 << 16) | (0x0 << 8) | (0x0 << 0); + } else { + highspeed = 0; + clk = 400 * 1000; + arg = (0x3 << 24) | (0xB9 << 16) | (0x0 << 8) | (0x0 << 0); + } + // Send switch mode command to card + if (RSI_OK != RSI_SDMMC_SwitchFunctionCmd6(pSmihConfig, arg)) { + return ERROR_SMIH; + } + // Configure clock + smih_clock_config(pSmihConfig, clk); + + // Enable or disable high speed mode + SMIH->SMIH_HOST_CONTROL_1_REGISTER_b.HIGH_SPEED_ENABLE = highspeed; + + return RSI_OK; +} +#endif diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_smih.c b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_smih.c new file mode 100644 index 000000000..42fa7bba3 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_smih.c @@ -0,0 +1,1184 @@ +/******************************************************************************* +* @file rsi_smih.c +* @brief +******************************************************************************* +* # License +* Copyright 2022 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +// Include Files + +#include "rsi_ccp_user_config.h" +#if defined(CHIP_9118) + +static SMIH_TRANSFER_T *CommandInProgress = 0; +static SMIH_CONFIG_MODES_T *modesConfig = 0; +static SMIH_CONFIG_MODES_T modeConfig; +static SMIH_ADMA_DESC_TABLE_T Adma2DescriptorTable[2] = { 0 }; +volatile static SMIH_EVENT_T event; + +#define SD_IRQHandler IRQ068_Handler + +// SMIH CONTROLLER RELATED FUNCTIONS +/*==============================================*/ +/** + * @fn rsi_error_t RSI_SD_HostInit(SMIH_CARD_CONFIG_T *pSmihConfig, ARM_SMIH_SignalEvent_t Event, uint8_t MemType) + * @brief This API is used to initialize the smih host configuration + * @param[in] pSmihConfig : Pointer to the smih card configuration structure + * @param[in] Event : event handler to be register + * @param[in] MemType : type of operation to be pragram + * 1 for memory operations , + * 0 for IO operations + * @return RSI_OK : If host initialized successfully + */ +rsi_error_t RSI_SD_HostInit(SMIH_CARD_CONFIG_T *pSmihConfig, ARM_SMIH_SignalEvent_t Event, uint8_t MemType) +{ + SMIH_CONFIG_MODES_T commandCfg; + if (pSmihConfig == 0) { + return INVALID_PARAMETERS; + } + // sleepclock prog + *(volatile uint32_t *)(0x46000024) = (0x0 << 21); + + // wait for clock switch + while ((M4CLK->PLL_STAT_REG_b.SLEEP_CLK_SWITCHED) != 1) + ; + + // Wait until card inserts + while (SMIH->SMIH_PRESENT_STATE_REGISTER_b.CARD_STATE_STABLE != 0x1) + ; + if (SMIH->SMIH_PRESENT_STATE_REGISTER_b.CARD_INSERTED == 0) { + return ERROR_SMIH; + } + + // Register callbacks + event.callb_event = Event; + + if (MemType) { + pSmihConfig->cmd_transfer = smih_memory_command_transfer; + } else { + pSmihConfig->cmd_transfer = smih_io_command_transfer; + } + + // Set bus violtage + if (pSmihConfig->voltage) { + smih_bus_voltage_select(VOLTAGE_18V); + } else { + smih_bus_voltage_select(VOLTAGE_33V); + } + + SMIH->SMIH_POWER_CONTROL_REGISTER_b.SD_BUS_POWER = 0x1; + + if (pSmihConfig->busWidthMode) { + // SMIH->SMIH_HOST_CONTROL_1_REGISTER_b.DATA_TRANSFER_WIDTH = 0x1; //fix for MMC + } else { + SMIH->SMIH_HOST_CONTROL_1_REGISTER_b.DATA_TRANSFER_WIDTH = 0x0; + } + + // Configure ADMA or IO mode + if (pSmihConfig->admaMode) { + SMIH->SMIH_HOST_CONTROL_1_REGISTER_b.DMA_SELECT = 0x2; + } else { + SMIH->SMIH_HOST_CONTROL_1_REGISTER_b.DMA_SELECT = 0x0; + } + + // Configure high speed mode + if (pSmihConfig->highSpeedEnable) { + SMIH->SMIH_HOST_CONTROL_1_REGISTER_b.HIGH_SPEED_ENABLE = 0x1; + } else { + SMIH->SMIH_HOST_CONTROL_1_REGISTER_b.HIGH_SPEED_ENABLE = 0x0; + } + + smih_clock_config(pSmihConfig, 400000); + + // Enable normal interrupts + SMIH->SMIH_NORMAL_INTERRUPT_STATUS_ENABLE_REGISTER = + (COMMAND_COMPLETE_STATUS_ENABLE | TRANSFER_COMPLETE_STATUS_ENABLE | BLOCK_GAP_EVENT_STATUS_ENABLE + | DMA_INTERRUPT_STATUS_ENABLE | BUFFER_WRITE_READY_STATUS_ENABLE | BUFFER_READ_READY_STATUS_ENABLE + | CARD_INSERTION_STATUS_ENABLE | CARD_REMOVAL_STATUS_ENABLE | CARD_INTERRUPT_STATUS_ENABLE | INT_A_STATUS_ENABLE + | INT_B_STATUS_ENABLE | INT_C_STATUS_ENABLE | RE_TUNING_EVENT_STATUS_ENABLE); + + // Enable error interrupts + SMIH->SMIH_ERROR_INTERRUPT_STATUS_ENABLE_REGISTER = + (COMMAND_TIMEOUT_ERROR_STATUS_ENABLE | COMMAND_CRC_ERROR_STATUS_ENABLE | COMMAND_END_BIT_ERROR_STATUS_ENABLE + | COMMAND_INDEX_ERROR_STATUS_ENABLE | DATA_TIMEOUT_ERROR_STATUS_ENABLE | DATA_CRC_ERROR_STATUS_ENABLE + | DATA_END_BIT_ERROR_STATUS_ENABLE | CURRENT_LIMIT_ERROR_STATUS_ENABLE | AUTO_CMD_ERROR_STATUS_ENABLE + | ADMA_ERROR_STATUS_ENABLE | TUNING_ERROR_STATUS_ENABLE); + + // Enable normal interrupts signals + SMIH->SMIH_NORMAL_INTERRUPT_SIGNAL_ENABLE_REGISTER = + (COMMAND_COMPLETE_SIGNAL_ENABLE | TRANSFER_COMPLETE_SIGNAL_ENABLE | BUFFER_WRITE_READY_SIGNAL_ENABLE + | BUFFER_READ_READY_SIGNAL_ENABLE | CARD_REMOVAL_SIGNAL_ENABLE | CARD_INTERRUPT_SIGNAL_ENABLE); + SMIH->SMIH_ERROR_INTERRUPT_SIGNAL_ENABLE_REGISTER = 0x1; + + // Enable Irq + NVIC_EnableIRQ(SDMEM_IRQn); + + memset(&commandCfg, 0, sizeof(commandCfg)); + commandCfg.highSpeedEnable = pSmihConfig->highSpeedEnable; + commandCfg.admaMode = pSmihConfig->admaMode; + commandCfg.busWidthMode = pSmihConfig->busWidthMode; + commandCfg.clock = pSmihConfig->clock; + + if (RSI_OK != smih_modes_configuration(&commandCfg)) { + return ERROR_SMIH; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t Smih_DeInitialization(void) + * @brief This API is used to Deinitialize the host controller. * + * @return RSI_OK : If host deinitialized successfully. + */ +rsi_error_t Smih_DeInitialization(void) +{ + // Clear clock control and power control registers + SMIH->SMIH_CLOCK_CONTROL_REGISTER = 0x0000; + SMIH->SMIH_POWER_CONTROL_REGISTER = 0x00; + + SMIH->SMIH_NORMAL_INTERRUPT_SIGNAL_ENABLE_REGISTER = 0x0000; + SMIH->SMIH_ERROR_INTERRUPT_SIGNAL_ENABLE_REGISTER = 0x0000; + + // disable nvic + NVIC_DisableIRQ(SDMEM_IRQn); + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t smih_bus_width_set(uint8_t BusWidthMode) + * @brief This API is used to set the smih bus width. + * @param[in] BusWidthMode : bus width mode + * possible values are 0 for 1bit mode + * 1 for 4bit mode + * 2 for 8bit mode + * @return RSI_OK : If bus width set successfully. + */ +rsi_error_t smih_bus_width_set(uint8_t BusWidthMode) +{ + // Configure bus width + if (BusWidthMode == 0) { + SMIH->SMIH_HOST_CONTROL_1_REGISTER_b.DATA_TRANSFER_WIDTH = 0x0; + } else if (BusWidthMode == 1) { + SMIH->SMIH_HOST_CONTROL_1_REGISTER_b.DATA_TRANSFER_WIDTH = 0x1; + } else if (BusWidthMode == 2) { + SMIH->SMIH_HOST_CONTROL_1_REGISTER_b.EXTENDED_DATA_TRANSFER_WIDTH = 0x1; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t smih_bus_voltage_select(uint8_t enVoltage) + * @brief This API is used to select the smih voltage. + * @param[in] enVoltage : voltage selection + * possbile selections are + * VOLTAGE_18V 1.8v voltage selection for sdio interface + * VOLTAGE_30V 3.0v voltage selection for sdio interface + * VOLTAGE_33V 3.3v voltage selection for sdio interface + * @return RSI_OK : If voltage configured Successfully. + */ +rsi_error_t smih_bus_voltage_select(uint8_t enVoltage) +{ + if (enVoltage == VOLTAGE_18V) { + SMIH->SMIH_POWER_CONTROL_REGISTER_b.SD_BUS_VOLTAGE_SELECT = 0x5; + } else if (enVoltage == VOLTAGE_30V) { + SMIH->SMIH_POWER_CONTROL_REGISTER_b.SD_BUS_VOLTAGE_SELECT = 0x6; + } else if (enVoltage == VOLTAGE_33V) { + SMIH->SMIH_POWER_CONTROL_REGISTER_b.SD_BUS_VOLTAGE_SELECT = 0x7; + } else { + return INVALID_PARAMETERS; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t smih_command_xfer(SMIH_COMMAND_FRAME_CONFIG_T *pConfig) + * @brief This API is used to send the command. + * @param[in] pConfig : pointer to the command structure + * @return RSI_OK : If command sent properly. + * INVALID_PARAMETERS : If pConfig == NULL + */ +rsi_error_t smih_command_xfer(SMIH_COMMAND_FRAME_CONFIG_T *pConfig) +{ + SMIH_COMMAND_REG_T cmdData; + + memset(&cmdData, 0, sizeof(cmdData)); + + if (pConfig == NULL) { + return INVALID_PARAMETERS; + } + + // Set command response type + switch (pConfig->responseTypeSelect) { + case SMIH_NO_RESPONSE: + cmdData.respType = 0x0; + break; + case SMIH_RESPONSE_LENGTH_136: + cmdData.respType = 0x1; + break; + case SMIH_RESPONSE_LENGTH_48: + cmdData.respType = 0x2; + break; + case SMIH_RESPONSE_LENGTH_48BIT_BUSY_CHECK: + cmdData.respType = 0x3; + break; + default: + return INVALID_PARAMETERS; + } + + // Set command CRC check + if (pConfig->cmdCrcCheckEn) { + cmdData.cmdCrcCheckEnable = 0x1; + } else { + cmdData.cmdCrcCheckEnable = 0x0; + } + + // Set command index check + if (pConfig->cmdIndexCheckEn) { + cmdData.cmdIndexCheckEnable = 0x1; + } else { + cmdData.cmdIndexCheckEnable = 0x0; + } + + // Set data present or not when sending the command + if (pConfig->dataPresentSelect) { + cmdData.dataPresentSelect = 0x1; + } else { + cmdData.dataPresentSelect = 0x0; + } + + // Configure command type + switch (pConfig->cmdType) { + case NORMAL_CMD: + cmdData.cmdType = 0x0; + break; + case SUSPEND_CMD: + cmdData.cmdType = 0x1; + break; + case RESUME_CMD: + cmdData.cmdType = 0x2; + break; + case ABORT_CMD: + cmdData.cmdType = 0x3; + break; + default: + return INVALID_PARAMETERS; + } + + // Set command index + cmdData.cmdIndex = pConfig->cmdIndex; + + // Auto command setting + switch (pConfig->autoCmdType) { + case DISABLE_AUTO_CMD: + SMIH->TRANSFER_MODE_REGISTER_b.AUTO_CMD_ENABLE = 0x0; + break; + case ENABLE_AUTO_CMD12: + SMIH->TRANSFER_MODE_REGISTER_b.AUTO_CMD_ENABLE = 0x1; + break; + case ENABLE_AUTO_CMD23: + SMIH->TRANSFER_MODE_REGISTER_b.AUTO_CMD_ENABLE = 0x2; + break; + default: + return INVALID_PARAMETERS; + } + // Configure argument register + SMIH->SMIH_ARGUMENT1_REGISTER = pConfig->cmdArgument; + + if (pConfig->cmdIndex == 5) { + if ((pConfig->cmdArgument & (1 << 24))) { + SMIH->SMIH_HOST_CONTROL_2_REGISTER = (1 << 3); + } + } + // assign fiiled data to the command register + SMIH->SMIH_COMMAND_REGISTER = *((uint16_t *)&cmdData); + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t smih_get_response(uint16_t *pResponseData, uint8_t ResponseRegCount) + * @brief This API is used to receive response on cmd line. + * @param[in] pResponseData : pointer to the response data + * @return RSI_OK : If command sent properly. + * INVALID_PARAMETERS : If pConfig==NULL or ResponseRegCount >8 + */ +rsi_error_t smih_get_response(uint16_t *pResponseData, uint8_t ResponseRegCount) +{ + uint16_t *pResponseBaseAddr; + uint8_t i; + + if ((pResponseData == 0) || (ResponseRegCount > 8u)) { + return INVALID_PARAMETERS; + } + pResponseBaseAddr = (uint16_t *)&SMIH->SMIH_RESPONSE_REGISTER0; + + for (i = 0; i < ResponseRegCount; i++) { + *pResponseData++ = *pResponseBaseAddr++; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t smih_stop_at_block_gap(void) + * @brief This API is used to stop multiple block transfer. + * @return RSI_OK : Stops data transfer. + */ +rsi_error_t smih_stop_at_block_gap(void) +{ + SMIH->SMIH_BLOCK_GAP_CONTROL_REGISTER_b.STOP_AT_BLOCK_GAP_REQUEST = 0x1; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t smih_transfer_restart(void) + * @brief This API is used to restart the transfer when the transfer is pending. + * @return RSI_OK : If data restarts transfer successfully. + */ +rsi_error_t smih_transfer_restart(void) +{ + SMIH->SMIH_BLOCK_GAP_CONTROL_REGISTER_b.CONTINUE_REQUEST = 0x1; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn void smih_18v_signal_enable(void) + * @brief This API is used to enable 1.8v signal enable bit. + * @return void + */ +void smih_18v_signal_enable(void) +{ + SMIH->SMIH_HOST_CONTROL_2_REGISTER_b._1_8V_SIGNALING_ENABLE = 0x1; +} + +/*==============================================*/ +/** + * @fn rsi_error_t smih_uhs_mode_select(uint8_t UhsMode) + * @brief This API is used to select the smih UHS(ULTRA HIGH SPEED) mode. + * @param[in] UhsMode : Uhs mode selection + * possbile selections are + * UHS_NONE no uhs mode + * UHS_SDR12 in case of SDR12 mode requirement + * UHS_SDR25 in case of SDR25 mode requirement + * UHS_SDR50 in case of SDR50 mode requirement + * UHS_SDR104 in case of SDR104 mode requirement + * UHS_DDR50 in case of DDR50 mode requirement + * @return RSI_OK : If uhs mode configured properly. + */ +rsi_error_t smih_uhs_mode_select(uint8_t UhsMode) +{ + switch (UhsMode) { + case UHS_SDR12: + SMIH->SMIH_HOST_CONTROL_2_REGISTER_b.UHS_MODE_SELECT = 0x0; + break; + case UHS_SDR25: + SMIH->SMIH_HOST_CONTROL_2_REGISTER_b.UHS_MODE_SELECT = 0x1; + break; + case UHS_SDR50: + SMIH->SMIH_HOST_CONTROL_2_REGISTER_b.UHS_MODE_SELECT = 0x2; + break; + case UHS_SDR104: + SMIH->SMIH_HOST_CONTROL_2_REGISTER_b.UHS_MODE_SELECT = 0x3; + break; + case UHS_DDR50: + SMIH->SMIH_HOST_CONTROL_2_REGISTER_b.UHS_MODE_SELECT = 0x4; + break; + default: + return INVALID_PARAMETERS; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn void smih_irq_handler(void) + * @brief This is smih Irq Handler + * @return none +*/ +void smih_irq_handler(void) +{ + uint32_t normal_intr_status; + uint32_t error_intr_status; + + // read normal interrupt status reg + normal_intr_status = SMIH->SMIH_NORMAL_INTERRUPT_STATUS_REGISTER; + + // read error interrupt status reg + error_intr_status = SMIH->SMIH_ERROR_INTERRUPT_STATUS_REGISTER; + + // Command complete + if (normal_intr_status & BIT(0)) { + event.commandComplete = 1; + if (event.callb_event != NULL) { + event.callb_event(COMMAND_COMPLETE); + } + SMIH->SMIH_NORMAL_INTERRUPT_STATUS_REGISTER = BIT(0); + } + // Transfer complete + if (normal_intr_status & BIT(1)) { + event.transferComplete = 1; + if (event.callb_event != NULL) { + event.callb_event(TRANSFER_COMPLETE); + } + SMIH->SMIH_NORMAL_INTERRUPT_STATUS_REGISTER = BIT(1); + } + // block gap event + if (normal_intr_status & BIT(2)) { + SMIH->SMIH_NORMAL_INTERRUPT_STATUS_REGISTER = BIT(2); + } + // DMA event + if (normal_intr_status & BIT(3)) { + if (event.callb_event != NULL) { + event.callb_event(DMA_INTR); + } + SMIH->SMIH_NORMAL_INTERRUPT_STATUS_REGISTER = BIT(3); + } + // Buffer write ready + if (normal_intr_status & BIT(4)) { + event.bufferWriteReady = 1; + if (event.callb_event != NULL) { + event.callb_event(BUFFER_WRITE_READY); + } + SMIH->SMIH_NORMAL_INTERRUPT_STATUS_REGISTER = BIT(4); + } + // Buffer read ready + if (normal_intr_status & BIT(5)) { + event.bufferReadReady = 1; + if (event.callb_event != NULL) { + event.callb_event(BUFFER_READ_READY); + } + SMIH->SMIH_NORMAL_INTERRUPT_STATUS_REGISTER = BIT(5); + } + // Card insetion + if (normal_intr_status & BIT(6)) { + if (event.callb_event != NULL) { + event.callb_event(CARD_INSERTION); + } + SMIH->SMIH_NORMAL_INTERRUPT_STATUS_REGISTER = BIT(6); + } + // Card removal + if (normal_intr_status & BIT(7)) { + event.cardRemoval = 1; + if (event.callb_event != NULL) { + event.callb_event(CARD_REMOVAL); + } + SMIH->SMIH_NORMAL_INTERRUPT_STATUS_REGISTER = BIT(7); + } + // Card interrupt + if (normal_intr_status & BIT(8)) { + event.cardInterrupt = 1; + if (event.callb_event != NULL) { + event.callb_event(CARD_INTERRUPT); + } + SMIH->SMIH_NORMAL_INTERRUPT_STATUS_REGISTER = BIT(8); + } + // Command timeout error + if (error_intr_status & BIT(0)) { + event.commandTimeoutError = 1; + if (event.callb_event != NULL) { + event.callb_event(CMD_TIMEOUT_ERROR); + } + SMIH->SMIH_ERROR_INTERRUPT_STATUS_REGISTER = BIT(0); + } + // Command CRC error + if (error_intr_status & BIT(1)) { + event.commandCrcError = 1; + if (event.callb_event != NULL) { + event.callb_event(CMD_CRC_ERROR); + } + SMIH->SMIH_ERROR_INTERRUPT_STATUS_REGISTER = BIT(1); + } + // Command end bit error + if (error_intr_status & BIT(2)) { + event.commandEndBitError = 1; + if (event.callb_event != NULL) { + event.callb_event(CMD_END_BIT_ERROR); + } + SMIH->SMIH_ERROR_INTERRUPT_STATUS_REGISTER = BIT(2); + } + // Command index error + if (error_intr_status & BIT(3)) { + event.commandIndexError = 1; + if (event.callb_event != NULL) { + event.callb_event(CMD_INDEX_ERROR); + } + SMIH->SMIH_ERROR_INTERRUPT_STATUS_REGISTER = BIT(3); + } + // data timeout error + if (error_intr_status & BIT(4)) { + event.dataTimeoutError = 1; + if (event.callb_event != NULL) { + event.callb_event(DATA_TIMEOUT_ERROR); + } + SMIH->SMIH_ERROR_INTERRUPT_STATUS_REGISTER = BIT(4); + } + // data end bit error + if (error_intr_status & BIT(5)) { + event.dataEndbitError = 1; + if (event.callb_event != NULL) { + event.callb_event(DATA_END_BIT_ERROR); + } + SMIH->SMIH_ERROR_INTERRUPT_STATUS_REGISTER = BIT(5); + } + // data CRC error + if (error_intr_status & BIT(6)) { + event.dataCrcError = 1; + if (event.callb_event != NULL) { + event.callb_event(DATA_CRC_ERROR); + } + SMIH->SMIH_ERROR_INTERRUPT_STATUS_REGISTER = BIT(6); + } + // Current limitation error + if (error_intr_status & BIT(7)) { + event.currentLimitError = 1; + if (event.callb_event != NULL) { + event.callb_event(CURRENT_LIMIT_ERROR); + } + SMIH->SMIH_ERROR_INTERRUPT_STATUS_REGISTER = BIT(7); + } + // Auto CMD12 error + if (error_intr_status & BIT(8)) { + event.autoCommandError = 1; + if (event.callb_event != NULL) { + event.callb_event(AUTO_CMD_ERROR); + } + SMIH->SMIH_ERROR_INTERRUPT_STATUS_REGISTER = BIT(8); + } + // ADMA error + if (error_intr_status & BIT(9)) { + event.admaError = 1; + if (event.callb_event != NULL) { + event.callb_event(ADMA_ERROR); + } + SMIH->SMIH_ERROR_INTERRUPT_STATUS_REGISTER = BIT(9); + } + // Tuning error + if (error_intr_status & BIT(10)) { + event.tuningError = 1; + if (event.callb_event != NULL) { + event.callb_event(TUNING_ERROR); + } + SMIH->SMIH_ERROR_INTERRUPT_STATUS_REGISTER = BIT(10); + } + return; +} + +/*==============================================*/ +/** + * @fn void SD_IRQHandler(void) + * @brief SMIH Interrupt Handler + * @return none +*/ +void SD_IRQHandler(void) +{ + smih_irq_handler(); +} + +/*==============================================*/ +/** + * @fn rsi_error_t smih_modes_configuration(SMIH_CONFIG_MODES_T *pSmihConfig) + * @brief This API is used to configure modes to SMIH + * @param[in] pSmihConfig : Pointer to the IO card configuration + * @return RSI_OK : IO command configuration structure initialized successfully + * INVALID_PARAMETERS : In case of Invalid parameter + */ +rsi_error_t smih_modes_configuration(SMIH_CONFIG_MODES_T *pSmihConfig) +{ + if (modesConfig == NULL) { + modesConfig = &modeConfig; + } + if (pSmihConfig != NULL) { + memcpy(modesConfig, pSmihConfig, sizeof(SMIH_CONFIG_MODES_T)); + return RSI_OK; + } + return ERROR_SMIH; +} + +/*==============================================*/ +/** + * @fn rsi_error_t smih_clock_config(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t freq) + * @brief This API is used to configure the host controller clock + * @param[in] freq : clock frequency to the host + * @return RSI_OK : If new frequency is set + */ +rsi_error_t smih_clock_config(SMIH_CARD_CONFIG_T *pSmihConfig, uint32_t freq) +{ + uint16_t Div = 0; + uint32_t clockInput = pSmihConfig->clock; + Div = clockInput / 2 / (freq); + + // disables smih clock + SMIH->SMIH_CLOCK_CONTROL_REGISTER_b.SD_CLOCK_ENABLE = 0u; + + // set division value to the clock + SMIH->SMIH_CLOCK_CONTROL_REGISTER_b.SDCLK_FREQUENCY_SELECT = (Div & 0xFF); + SMIH->SMIH_CLOCK_CONTROL_REGISTER_b.UPPER_BITS_OF_SDCLK_FREQUENCY_SELECT = ((Div >> 8) & 0x03); + + // Enable Smih internal clock + SMIH->SMIH_CLOCK_CONTROL_REGISTER_b.INTERNAL_CLOCK_ENABLE = 0x1; + + // wait for inter clock to be stable + while (0x1 != SMIH->SMIH_CLOCK_CONTROL_REGISTER_b.INTERNAL_CLOCK_STABLE) + ; + + // enables smih clock + SMIH->SMIH_CLOCK_CONTROL_REGISTER_b.SD_CLOCK_ENABLE = 0x1; + + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t smih_check_for_error_interrupt(void) + * @brief This API is used to check perticular error event happend or not. + * @return RSI_OK : If error event not occured. + * ERROR_TIMEOUT : If event occured + */ +rsi_error_t smih_check_for_error_interrupt(void) +{ + if (event.cardRemoval) { + event.cardRemoval = 0; + return ERROR_ACCESS_RIGHTS; + } + if (event.commandTimeoutError || event.commandCrcError || event.commandEndBitError || event.commandIndexError + || event.dataTimeoutError || event.dataEndbitError || event.dataCrcError) { + return ERROR_TIMEOUT; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t smih_send_data(SMIH_TRANSFER_T *pTransfer) + * @brief This API is used to write the data to the SMIH FIFO + * @param[in] pTransfer : Pointer to the command and data structure + * @return RSI_OK : If the data sent properly. + * ERROR_TIMEOUT : If the write data time out occurs. + */ +rsi_error_t smih_send_data(SMIH_TRANSFER_T *pTransfer) +{ + uint32_t blocksize = 0; + uint32_t blockcnt = 0; + uint32_t i = 0; + uint32_t *pBuffer = NULL; + + if (modesConfig->admaMode != 1) // IO mode + { + while (1) { + if (event.bufferWriteReady) { + event.bufferWriteReady = 0; + break; + } + // check for error interrupt + if (RSI_OK != smih_check_for_error_interrupt()) { + return ERROR_TIMEOUT; + } + // wait until card inserts + while (SMIH->SMIH_PRESENT_STATE_REGISTER_b.CARD_STATE_STABLE != 0x1) + ; + + if (SMIH->SMIH_PRESENT_STATE_REGISTER_b.CARD_INSERTED == 0) { + return ERROR_SMIH; + } + } + blockcnt = pTransfer->data->blockCount; + blocksize = pTransfer->data->blockSize; + pBuffer = (uint32_t *)pTransfer->data->data; + + while (blockcnt > 0) { + while (0x0 == SMIH->SMIH_PRESENT_STATE_REGISTER_b.BUFFER_WRITE_ENABLE) + ; + if (0x0 == SMIH->SMIH_PRESENT_STATE_REGISTER_b.BUFFER_WRITE_ENABLE) { + return ERROR_TIMEOUT; + } + // write data to the fifo + for (i = 0; i < (blocksize >> 2); i++) { + SMIH->SMIH_BUFFER_DATA_PORT_REGISTER = (*pBuffer++); + } + blockcnt--; + } + // wait for transfer completion event to be occur + while (1) { + if (event.transferComplete) { + event.transferComplete = 0; + break; + } + // check for error interrupt + if (RSI_OK != smih_check_for_error_interrupt()) { + return ERROR_TIMEOUT; + } + // wait until card inserts + while (SMIH->SMIH_PRESENT_STATE_REGISTER_b.CARD_STATE_STABLE != 0x1) + ; + + if (SMIH->SMIH_PRESENT_STATE_REGISTER_b.CARD_INSERTED == 0) { + return ERROR_SMIH; + } + } + } else //adm2 mode + { + // wait for transfer done + while (1) { + if (event.transferComplete) { + event.transferComplete = 0; + break; + } + // check for error interrupt + if (RSI_OK != smih_check_for_error_interrupt()) { + return ERROR_TIMEOUT; + } + // wait until card inserts + while (SMIH->SMIH_PRESENT_STATE_REGISTER_b.CARD_STATE_STABLE != 0x1) + ; + + if (SMIH->SMIH_PRESENT_STATE_REGISTER_b.CARD_INSERTED == 0) { + return ERROR_SMIH; + } + } + } + // Wait for data line to be free + while ((SMIH->SMIH_PRESENT_STATE_REGISTER_b.DAT_LINE_ACTIVE) != 0) + ; + + if ((SMIH->SMIH_PRESENT_STATE_REGISTER_b.DAT_LINE_ACTIVE) == 0x1) { + return ERROR_SMIH; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t smih_receive_data(SMIH_TRANSFER_T *pTransfer) + * @brief This API is used to read the data from SMIH FIFO + * @param[in] pTransfer : Pointer to the command and data structure + * @return RSI_OK : If the data read properly. + * ERROR_TIMEOUT : If data timeout occurs. + */ +rsi_error_t smih_receive_data(SMIH_TRANSFER_T *pTransfer) +{ + uint32_t blocksize = 0; + static uint32_t blockcnt = 0; + uint32_t i = 0; + uint32_t *pBuffer = NULL; + + if (modesConfig->admaMode != 1) // IO mode + { + // wait for read ready event + while (1) { + if (event.bufferReadReady) { + event.bufferReadReady = 0; + break; + } + // check for error interrupt + if (RSI_OK != smih_check_for_error_interrupt()) { + return ERROR_TIMEOUT; + } + + // wait until card inserts + while (SMIH->SMIH_PRESENT_STATE_REGISTER_b.CARD_STATE_STABLE != 0x1) + ; + + if (SMIH->SMIH_PRESENT_STATE_REGISTER_b.CARD_INSERTED == 0) { + return ERROR_SMIH; + } + } + pBuffer = (uint32_t *)pTransfer->data->data; + blockcnt = pTransfer->data->blockCount; + blocksize = pTransfer->data->blockSize; + + // read data from fifo + while (blockcnt > 0) { + while (SMIH->SMIH_PRESENT_STATE_REGISTER_b.BUFFER_READ_ENABLE == 0) + ; + if (SMIH->SMIH_PRESENT_STATE_REGISTER_b.BUFFER_READ_ENABLE == 0) { + break; + } + for (i = 0; i < (blocksize >> 2); i++) { + *pBuffer++ = SMIH->SMIH_BUFFER_DATA_PORT_REGISTER; + } + blockcnt--; + } + + // wait until data transfer done + while (1) { + if (event.transferComplete) { + event.transferComplete = 0; + break; + } + // check for error interrupt + if (RSI_OK != smih_check_for_error_interrupt()) { + return ERROR_TIMEOUT; + } + // wait until card inserts + while (SMIH->SMIH_PRESENT_STATE_REGISTER_b.CARD_STATE_STABLE != 0x1) + ; + if (SMIH->SMIH_PRESENT_STATE_REGISTER_b.CARD_INSERTED == 0) { + return ERROR_SMIH; + } + } + } else // adma2 mode + { + while (1) { + if (event.transferComplete) { + event.transferComplete = 0; + break; + } + // check for error interrupt + if (RSI_OK != smih_check_for_error_interrupt()) { + return ERROR_TIMEOUT; + } + // wait until card inserts + while (SMIH->SMIH_PRESENT_STATE_REGISTER_b.CARD_STATE_STABLE != 0x1) + ; + if (SMIH->SMIH_PRESENT_STATE_REGISTER_b.CARD_INSERTED == 0) { + return ERROR_SMIH; + } + } + } + // Wait for data line to be free + while ((SMIH->SMIH_PRESENT_STATE_REGISTER_b.DAT_LINE_ACTIVE) != 0) + ; + + if ((SMIH->SMIH_PRESENT_STATE_REGISTER_b.DAT_LINE_ACTIVE) == 0x1) { + return ERROR_SMIH; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t smih_memory_command_transfer(SMIH_TRANSFER_T *pTransfer) + * @brief This API is used to send memory command. + * @param[in] pTransfer : Pointer to the command and data structure + * @return ERROR_SMIH : If Parameter is invalid. + * ERROR_TIMEOUT : If the command error timeout occures. + * RSI_OK : If command sent succesfully. + */ +rsi_error_t smih_memory_command_transfer(SMIH_TRANSFER_T *pTransfer) +{ + uint32_t admaDespTableAddress; + SMIH_COMMAND_FRAME_CONFIG_T commandCfg = { 0 }; + + if (NULL == modesConfig) { + return INVALID_PARAMETERS; + } + // wait for command line to be stable + while (SMIH->SMIH_PRESENT_STATE_REGISTER_b.COMMAND_INHIBIT_CMD != 0) + ; + + // wait for data line to be stable + while (SMIH->SMIH_PRESENT_STATE_REGISTER_b.COMMAND_INHIBIT_DAT != 0) + ; + + // cnfigure adma2 descriptor table + if ((modesConfig->admaMode) && (pTransfer->data->data != NULL)) { + memset(Adma2DescriptorTable, 0x0, sizeof(Adma2DescriptorTable)); + + Adma2DescriptorTable[0].attributeValid = 1; + Adma2DescriptorTable[0].attributeEnd = 1; + Adma2DescriptorTable[0].attributeInt = 0; + Adma2DescriptorTable[0].attributeAct = 2; + Adma2DescriptorTable[0].length = (pTransfer->data->blockSize * pTransfer->data->blockCount); + Adma2DescriptorTable[0]._32BIT_Adress = (uint32_t)pTransfer->data->data; + admaDespTableAddress = (uint32_t)&Adma2DescriptorTable[0]; + SMIH->SMIH_ADMA_SYSTEM_ADDRESS0_REGISTER = (uint16_t)admaDespTableAddress; + SMIH->SMIH_ADMA_SYSTEM_ADDRESS1_REGISTER = (uint16_t)(admaDespTableAddress >> 16u); + } + SMIH->SMIH_BLOCK_SIZE_REGISTER_b.TRANSFER_BLOCK_SIZE = pTransfer->data->blockSize; + SMIH->TRANSFER_MODE_REGISTER_b.DATA_TRANSFER_DIRECTION_SELECT = pTransfer->data->direction; + commandCfg.cmdArgument = pTransfer->command->cmdArg; + + // Configure the CMD register to send the command. + if (pTransfer->data->data == NULL) { + commandCfg.dataPresentSelect = 0; + } else { + commandCfg.dataPresentSelect = 1; + } + if ((modesConfig->admaMode) && (pTransfer->data->data != NULL)) { + SMIH->TRANSFER_MODE_REGISTER_b.DMA_ENABLE = 1; + } else { + SMIH->TRANSFER_MODE_REGISTER_b.DMA_ENABLE = 0; + } + commandCfg.cmdIndex = pTransfer->command->cmdIdx & 0x3F; + if ((commandCfg.cmdIndex == 18) || (commandCfg.cmdIndex == 25)) { + // multiple block mode + commandCfg.autoCmdType = ENABLE_AUTO_CMD12; + SMIH->TRANSFER_MODE_REGISTER_b.BLOCK_COUNT_ENABLE = 0x1; + SMIH->TRANSFER_MODE_REGISTER_b.MULTI_OR_SINGLE_BLOCK_SELECT = 0x1; + SMIH->SMIH_BLOCK_COUNT_REGISTER = pTransfer->data->blockCount; + } else { + // single block mode + commandCfg.autoCmdType = DISABLE_AUTO_CMD; + SMIH->TRANSFER_MODE_REGISTER_b.BLOCK_COUNT_ENABLE = 0x0; + SMIH->TRANSFER_MODE_REGISTER_b.MULTI_OR_SINGLE_BLOCK_SELECT = 0x0; + SMIH->SMIH_BLOCK_COUNT_REGISTER = pTransfer->data->blockCount; + } + switch (pTransfer->command->responseTypeSelect) { + case SMIH_NO_RESPONSE: + commandCfg.responseTypeSelect = SMIH_NO_RESPONSE; + commandCfg.cmdIndexCheckEn = 0; + commandCfg.cmdCrcCheckEn = 0; + break; + case SMIH_RESPONSE_R2: + commandCfg.responseTypeSelect = SMIH_RESPONSE_LENGTH_136; + commandCfg.cmdIndexCheckEn = 0; + commandCfg.cmdCrcCheckEn = 1; + break; + case SMIH_RESPONSE_R3R4: + commandCfg.responseTypeSelect = SMIH_RESPONSE_LENGTH_48; + commandCfg.cmdIndexCheckEn = 0; + commandCfg.cmdCrcCheckEn = 0; + break; + case SMIH_RESPONSE_R1R5R6R7: + commandCfg.responseTypeSelect = SMIH_RESPONSE_LENGTH_48; + commandCfg.cmdIndexCheckEn = 1; + commandCfg.cmdCrcCheckEn = 1; + break; + case SMIH_RESPONSE_R1BR5B: + commandCfg.responseTypeSelect = SMIH_RESPONSE_LENGTH_48BIT_BUSY_CHECK; + commandCfg.cmdIndexCheckEn = 1; + commandCfg.cmdCrcCheckEn = 1; + break; + default: + return INVALID_PARAMETERS; + } + + if (CommandInProgress != NULL) { + return ERROR_OPERATION_INPROGRESS; + } + + SMIH->SMIH_TIMEOUT_CONTROL_REGISTER_b.DATA_TIMEOUT_COUNTER_VALUE = 0xC; + + commandCfg.cmdType = NORMAL_CMD; + + // set current command to global value for callback + CommandInProgress = pTransfer; + + // send command + smih_command_xfer(&commandCfg); + + // wait command line to be stable + while (1) { + if (event.commandComplete) { + event.commandComplete = 0; + break; + } + // check for error interrupt + if (RSI_OK != smih_check_for_error_interrupt()) { + return ERROR_SMIH; + } + // wait until card inserts + while (SMIH->SMIH_PRESENT_STATE_REGISTER_b.CARD_STATE_STABLE != 0x1) + ; + + if (SMIH->SMIH_PRESENT_STATE_REGISTER_b.CARD_INSERTED == 0) { + return ERROR_TIMEOUT; + } + } + + // get response data + if (RSI_OK != smih_get_response((uint16_t *)pTransfer->command->response, sizeof(pTransfer->command->response) / 2)) { + return ERROR_SMIH; + } + if (pTransfer->data->data != 0) { + if ((pTransfer->command->cmdIdx == 24) || (pTransfer->command->cmdIdx == 25)) { + // send data to card + if (RSI_OK != smih_send_data(pTransfer)) { + return ERROR_SMIH; + } + } + if ((pTransfer->command->cmdIdx == 17) || (pTransfer->command->cmdIdx == 18) + || (pTransfer->command->cmdIdx == (0x80 | 8) /*mmc command 8*/) + || (pTransfer->command->cmdIdx == (0x40 + 51) /*sd ACMD51*/)) { + /* read data from card */ + if (RSI_OK != smih_receive_data(pTransfer)) { + return ERROR_SMIH; + } + } + } + CommandInProgress = NULL; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t smih_io_command_transfer(SMIH_TRANSFER_T *pTransfer) + * @brief This API is used to transfer SMIH command. + * @param[in] pTransfer : Pointer to the command and data structure + * @return ERROR_SMIH : If Parameter is invalid. + * ERROR_TIMEOUT : If the command error timeout occures. + */ +rsi_error_t smih_io_command_transfer(SMIH_TRANSFER_T *pTransfer) +{ + SMIH_COMMAND_FRAME_CONFIG_T commandCfg = { 0 }; + uint32_t admaDespTableAddress; + if (NULL == modesConfig) { + return INVALID_PARAMETERS; + } + // wait for command line to be stable + while (SMIH->SMIH_PRESENT_STATE_REGISTER_b.COMMAND_INHIBIT_CMD != 0) + ; + + // wait for data line to be stable + while (SMIH->SMIH_PRESENT_STATE_REGISTER_b.COMMAND_INHIBIT_DAT != 0) + ; + + // cnfigure adma2 descriptor table + if ((modesConfig->admaMode) && (pTransfer->data->data != NULL)) { + memset(Adma2DescriptorTable, 0x0, sizeof(Adma2DescriptorTable)); + Adma2DescriptorTable[0].attributeValid = 1; + Adma2DescriptorTable[0].attributeEnd = 1; + Adma2DescriptorTable[0].attributeInt = 0; + Adma2DescriptorTable[0].attributeAct = 2; + Adma2DescriptorTable[0].length = pTransfer->data->blockSize * pTransfer->data->blockCount; + Adma2DescriptorTable[0]._32BIT_Adress = (uint32_t)pTransfer->data->data; + admaDespTableAddress = (uint32_t)&Adma2DescriptorTable[0]; + // Update descriptor address + SMIH->SMIH_ADMA_SYSTEM_ADDRESS0_REGISTER = (uint16_t)admaDespTableAddress; + SMIH->SMIH_ADMA_SYSTEM_ADDRESS1_REGISTER = (uint16_t)(admaDespTableAddress >> 16u); + } + // Configure block size + SMIH->SMIH_BLOCK_SIZE_REGISTER_b.TRANSFER_BLOCK_SIZE = pTransfer->data->blockSize; + SMIH->TRANSFER_MODE_REGISTER_b.DATA_TRANSFER_DIRECTION_SELECT = pTransfer->data->direction; + + if ((modesConfig->admaMode) && (pTransfer->data->data != NULL)) { + SMIH->TRANSFER_MODE_REGISTER_b.DMA_ENABLE = 1; + } else { + SMIH->TRANSFER_MODE_REGISTER_b.DMA_ENABLE = 0; + } + + SMIH->SMIH_TIMEOUT_CONTROL_REGISTER_b.DATA_TIMEOUT_COUNTER_VALUE = 0xC; + + // Configure the CMD register to send the command. + if (pTransfer->data->data == NULL) { + commandCfg.dataPresentSelect = 0; + } else { + commandCfg.dataPresentSelect = 1; + } + commandCfg.cmdArgument = pTransfer->command->cmdArg; + commandCfg.cmdIndex = pTransfer->command->cmdIdx & 0x3F; + + if ((commandCfg.cmdIndex == 53) && (pTransfer->command->cmdArg & BIT(27))) { + // multiple block mode + SMIH->TRANSFER_MODE_REGISTER_b.BLOCK_COUNT_ENABLE = 0x1; + SMIH->TRANSFER_MODE_REGISTER_b.MULTI_OR_SINGLE_BLOCK_SELECT = 0x1; + SMIH->SMIH_BLOCK_COUNT_REGISTER = pTransfer->data->blockCount; + } else { + // single block mode + SMIH->TRANSFER_MODE_REGISTER_b.BLOCK_COUNT_ENABLE = 0x0; + SMIH->TRANSFER_MODE_REGISTER_b.MULTI_OR_SINGLE_BLOCK_SELECT = 0x0; + SMIH->SMIH_BLOCK_COUNT_REGISTER = pTransfer->data->blockCount; + } + + switch (pTransfer->command->responseTypeSelect) { + case SMIH_NO_RESPONSE: + commandCfg.responseTypeSelect = SMIH_NO_RESPONSE; + commandCfg.cmdIndexCheckEn = 0; + commandCfg.cmdCrcCheckEn = 0; + break; + case SMIH_RESPONSE_R2: + commandCfg.responseTypeSelect = SMIH_RESPONSE_LENGTH_136; + commandCfg.cmdIndexCheckEn = 0; + commandCfg.cmdCrcCheckEn = 1; + break; + case SMIH_RESPONSE_R3R4: + commandCfg.responseTypeSelect = SMIH_RESPONSE_LENGTH_48; + commandCfg.cmdIndexCheckEn = 0; + commandCfg.cmdCrcCheckEn = 0; + break; + case SMIH_RESPONSE_R1R5R6R7: + commandCfg.responseTypeSelect = SMIH_RESPONSE_LENGTH_48; + commandCfg.cmdIndexCheckEn = 1; + commandCfg.cmdCrcCheckEn = 1; + break; + case SMIH_RESPONSE_R1BR5B: + commandCfg.responseTypeSelect = SMIH_RESPONSE_LENGTH_48BIT_BUSY_CHECK; + commandCfg.cmdIndexCheckEn = 1; + commandCfg.cmdCrcCheckEn = 1; + break; + default: + return INVALID_PARAMETERS; + } + + commandCfg.autoCmdType = DISABLE_AUTO_CMD; + + if (CommandInProgress != NULL) { + return ERROR_OPERATION_INPROGRESS; + } + commandCfg.cmdType = NORMAL_CMD; + + // set current command to global value for callback + CommandInProgress = pTransfer; + + // send command + smih_command_xfer(&commandCfg); + + // wait command line to be stable + while (1) { + if (event.commandComplete) { + event.commandComplete = 0; + break; + } + // check for error interrupt + if (RSI_OK != smih_check_for_error_interrupt()) { + return ERROR_SMIH; + } + + // wait until card inserts + while (SMIH->SMIH_PRESENT_STATE_REGISTER_b.CARD_STATE_STABLE != 0x1) + ; + if (SMIH->SMIH_PRESENT_STATE_REGISTER_b.CARD_INSERTED == 0) { + return ERROR_TIMEOUT; + } + } + // get response data + if (RSI_OK != smih_get_response((uint16_t *)pTransfer->command->response, sizeof(pTransfer->command->response) / 2)) { + return ERROR_SMIH; + } + if (pTransfer->data->data != 0) { + if (pTransfer->command->cmdIdx == 53) { + if ((pTransfer->command->cmdArg) & BIT(31)) { + // send data to card + if (RSI_OK != smih_send_data(pTransfer)) { + return ERROR_SMIH; + } + } else { + // read data from card + if (RSI_OK != smih_receive_data(pTransfer)) { + return ERROR_SMIH; + } + } + } + } + CommandInProgress = NULL; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn void RegisterCallBack(ARM_SMIH_SignalEvent_t Event) + * @brief This API is used to register the call back handler + * @param[in] Event : Call back handler to register + * @return none + */ +void RegisterCallBack(ARM_SMIH_SignalEvent_t Event) +{ + event.callb_event = Event; +} +#endif diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_vad.c b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_vad.c new file mode 100644 index 000000000..16a9b4eb0 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_vad.c @@ -0,0 +1,516 @@ +/******************************************************************************* +* @file rsi_vad.c +* @brief +******************************************************************************* +* # License +* Copyright 2022 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +// Include Files + +#include "rsi_ccp_user_config.h" + +volatile static VAD_EVENT_T event; +#if 1 + +/*==============================================*/ +/** + * @fn VAD_PING_IRQHandler() + * @brief VAD IRQ handler , clear the VAD interrupt. + * @return none + */ +void VAD_PING_IRQHandler() +{ + RSI_VAD_InterruptClr(VAD, 1); + event.callb_event(VAD_INTR); +} +#endif + +/*==============================================*/ +/** + * @fn rsi_error_t VAD_Init(VAD_SignalEvent_t Event) + * @brief This API is used to configure the VAD related parameters. + * @param[in] Event : Register callback event. + * @return Execution status - If success + */ +rsi_error_t VAD_Init(VAD_SignalEvent_t Event) +{ + // Register callback event + event.callb_event = Event; +#if defined(CHIP_9118) + RSI_PS_UlpssPeriPowerUp(ULPSS_PWRGATE_ULP_VAD); +#endif + + if (!(event.clk_config)) { + // Configure the fast and slow clock for VAD + RSI_ULPSS_VadClkConfig(ULPCLK, ULP_VAD_32KHZ_RC_CLK, ULP_VAD_32MHZ_RC_CLK, 4); + event.clk_config = 1U; + } + + // Select the algorithm and algorithm threshold for VAD + RSI_VAD_SetAlgorithmThreshold(VAD, VAD_METHOD_ZCR_ACF, VAD_ZCR_THRSHOLD, VAD_ACF_THRSHOLD, 0, 0); + + // Configure the sample per frame and sample per address for VAD + RSI_VAD_Config(VAD, NUMBER_OF_SAMPLE_IN_FRAME, VAD_2SMPLS_PER_ADDR, 1, VAD_INTREG_SOURCE); + + // Set the start delay and end delay for ACF algorithm + RSI_VAD_Set_Delay(VAD, VAD_ACF_START, VAD_ACF_END); + + // Set energy threshold value */ + RSI_VAD_FrameEnergyConfig(VAD, VAD_ENERGY_THRSHOLD, 1, 1); + + RSI_VAD_PingPongMemoryAddrConfig(VAD, VAD_SCRT_PAD, 0, 1, 0); + + // Enable Nvic + NVIC_EnableIRQ(VAD_INTR_PING_IRQn); + + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn int32_t VAD_Process(int16_t *wr_buf, int32_t dc_est) + * @brief This API is used to process VAD data. + * @param[in] wr_buf : Input data buffer + * @param[in] dc_est : dc estimation value of previous 1023 samples. + * @return The dc estimation value of current 1023 samples - If success + */ +int32_t VAD_Process(int16_t *wr_buf, int32_t dc_est) +{ + uint8_t energy_status = 0; + uint16_t index; + int32_t dc_est1 = 0; + int16_t temp_data = 0, data_in1 = 0; + static uint8_t flag = 1; + RSI_VAD_Stop(VAD); + dc_est = dc_est >> 10; + + for (index = 0; index < (NUMBER_OF_SAMPLE_IN_FRAME); index++) { + data_in1 = wr_buf[index]; +#if DATA_FROM_INTER_ADC + if (data_in1 & BIT(11)) { + data_in1 = data_in1 | (VAD_MASK_VALUE); + } else { + data_in1 = data_in1; + } +#else + data_in1 = data_in1; +#endif + dc_est1 = dc_est1 + data_in1; + temp_data = data_in1 - dc_est; + temp_data = temp_data << VAD_DIGITAL_GAIN_FAC; + // fill data in VAD ping memory + ((*(volatile uint16_t *)(ULP_MEMORY_BASE + VAD_SCRT_PAD + index * 2))) = temp_data; + } + + if ((dc_est == 0) && (flag == 1)) { + RSI_VAD_Stop(VAD); + flag = 0; + } else { + for (index = 0; index < (32); index++) { + // fill data in VAD register + VAD->VAD_CONF_REG8 = ((*(volatile uint16_t *)(ULP_MEMORY_BASE + VAD_SCRT_PAD + index * 2))) | BIT(10); + } + for (index = 0; index < (NUMBER_OF_SAMPLE_IN_FRAME); index++) { + // fill data in VAD register + VAD->VAD_CONF_REG8 = ((*(volatile uint16_t *)(ULP_MEMORY_BASE + VAD_SCRT_PAD + index * 2))) | BIT(10); + } + } + + energy_status = RSI_VAD_ProccessDone(VAD); + + if (energy_status) { + // Enable Fast clock for VAD for fast post processing + RSI_VAD_FastClkEnable(ULP_VAD_32MHZ_RC_CLK, 0); + event.callb_event(VAD_ENERGY_DETECT); + } + return dc_est1; +} + +/*==============================================*/ +/** + * @fn rsi_error_t VAD_Deinit(void) + * @brief This API is used to deinitialize the VAD related parameters. + * @return Execution status - If success + */ +rsi_error_t VAD_Deinit(void) +{ + RSI_ULPSS_PeripheralDisable(ULPCLK, ULP_VAD_CLK); +#if defined(CHIP_9118) + RSI_PS_UlpssPeriPowerDown(ULPSS_PWRGATE_ULP_VAD); +#endif + event.clk_config = 0U; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn void RSI_VAD_PingPongMemoryAddrConfig(RSI_VAD_T *pVAD, + * uint32_t ping_addr, + * uint32_t pong_addr, + * uint8_t ping_enable, + * uint8_t pong_enable) + * @brief This API is used to write the ulp mem address for pong buffer and ping buffer + * @param[in] pVAD : Pointer to the VAD_Type structure. + * @param[in] ping_addr : 13 bit ulp mem address offset for ping buffer + * @param[in] pong_addr : 13 bit ulp mem address offset for pong buffer + * @param[in] ping_enable : This parameter enable the ping address configuration. + * @param[in] pong_enable : This parameter enable the pong address configuration. + * @return none + */ +void RSI_VAD_PingPongMemoryAddrConfig(RSI_VAD_T *pVAD, + uint32_t ping_addr, + uint32_t pong_addr, + uint8_t ping_enable, + uint8_t pong_enable) +{ + if (ping_enable) { + pVAD->VAD_CONF_REG9_b.PING_ADDR = (ping_addr >> 2); + } + if (pong_enable) { + pVAD->VAD_CONF_REG9_b.PONG_ADDR = (pong_addr >> 2); + } +} + +/*==============================================*/ +/** + * @fn RSI_VAD_Config() + * @brief This API is used to configure the VAD parameter + * @param[in] pVAD : Pointer to the VAD_Type structure. + * @param[in] samples_per_frame : Number of samples in one processing frame, maximum value is 1023 and + * default is 512 + * @param[in] samples_per_address : Number of samples for address \n + * 0 - 4 samples per address + * 1 - 2 Samples per address + * 2 - 1 Sample per address + * @param[in] fullwidth : 0 - 12/24 when VAD_REG1_ADDR[21:20] + * 1 - 2 Samples per address + * @param[in] datasourceselect : Source of Data for VAD processing + * 00/10: Internal Register + * 11: ADC as source + * 01: Reserved + * @return RSI_OK - If success + */ +rsi_error_t RSI_VAD_Config(RSI_VAD_T *pVAD, + uint16_t samples_per_frame, + uint16_t samples_per_address, + bool fullwidth, + uint8_t datasourceselect) +{ + if ((samples_per_frame > MAXIMUM_VALUE_1024) || (samples_per_address > MAXIMUM_VALUE_4) + || (datasourceselect > MAXIMUM_VALUE_4)) { + return INVALID_PARAMETERS; + } + // Set the samples_per_frame and samples per address for VAD + pVAD->VAD_CONF_REG1_b.SAMPLS_PER_FRAME = samples_per_frame; + pVAD->VAD_CONF_REG1_b.SMPLS_PER_ADDR = samples_per_address; + pVAD->VAD_CONF_REG1_b.FULL_WIDTH = fullwidth; //need to be review this parameter + // selecting the Source of Data for VAD processing + pVAD->VAD_CONF_REG7_b.DATA_SOURCE_SELECT = datasourceselect; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn void RSI_VAD_Enable(RSI_VAD_T *pVAD) + * @brief This API is used to Enable Processing of VAD + * @param[in] pVAD : Pointer to the VAD_Type structure. + * @return none + */ +void RSI_VAD_Enable(RSI_VAD_T *pVAD) +{ + pVAD->VAD_CONF_REG8_b.EN_VAD_PROCESS = 1U; +} + +/*==============================================*/ +/** + * @fn RSI_VAD_InterruptClr() + * @brief This API is used to clear the interrupt of VAD + * @param[in] pVAD : Pointer to the VAD_Type structure. + * @param[in] ping_interrupt : This parameter define which interrupt want to be clear. + * ping_interrupt = 1 , To clear the VAD ping interrupt. + * ping_interrupt = 0 , To clear the VAD pong interrupt. + * @return none + */ +void RSI_VAD_InterruptClr(RSI_VAD_T *pVAD, uint16_t ping_interrupt) +{ + if (ping_interrupt) { + // clear the ping interrupt in VAD_CONF_REG9 register + pVAD->VAD_CONF_REG9_b.PING_INT_CLEAR = 1U; + } else { + // clear the pong interrupt in VAD_CONF_REG9 register + pVAD->VAD_CONF_REG9_b.PONG_INT_CLEAR = 1U; + } +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_VAD_SetAlgorithmThreshold(RSI_VAD_T *pVAD, + * uint16_t algorithm_type, + * uint32_t zcr_threshold, + * uint32_t acf_threshold, + * uint32_t wacf_threshold, + * VAD_AMDF_THRESHOLD_T *config) + * @brief This API is used to set algorithm and threshold value for that algorithm. + * @param[in] pVAD : Pointer to the VAD_Type structure. + * @param[in] algorithm_type : Select the algorithm type here refer this #VAD_ALGORITHM_SELECT_T enum. + * pass the specific value for selection of algorithm + * @param[in] zcr_threshold : This parameter define threshold value for zcr algorithm maximum value is 1023 + * and default value is 50. + * @param[in] acf_threshold : This parameter define threshold value for acf algorithm maximum value is 4095 + * and default value is 1024. + * @param[in] admf_threshold : This parameter define threshold value for acf algorithm maximum value is 4095 + * and default value is 1024. + * @param[in] wacf_threshold : This parameter define threshold value for wacf_threshold algorithm maximum value is 4095 + * and default value is 51. + * @param[in] config : VAD_AMDF_THRESHOLD_T structure veriable, configure this structure + * for AMDF algorithm delay. + * @return RSI_OK - If success + */ +rsi_error_t RSI_VAD_SetAlgorithmThreshold(RSI_VAD_T *pVAD, + uint16_t algorithm_type, + uint32_t zcr_threshold, + uint32_t acf_threshold, + uint32_t wacf_threshold, + VAD_AMDF_THRESHOLD_T *config) +{ + if ((algorithm_type > MAXIMUM_VALUE_8) || (zcr_threshold > MAXIMUM_VALUE_1024) || (acf_threshold > MAXIMUM_VALUE_4096) + || (wacf_threshold > MAXIMUM_VALUE_4096)) { + return INVALID_PARAMETERS; + } + // set the required the algorithm for detection purpose + pVAD->VAD_CONF_REG7_b.CHOOSE_VAD_METHOD = algorithm_type; + + switch (algorithm_type) { + case ZCR: + // write the threshold value to smpls_zero_cross bits + pVAD->VAD_CONF_REG2_b.SMPLS_ZERO_CROSS = zcr_threshold; + break; + case ACF: + // To clear the threshold_acf bits + pVAD->VAD_CONF_REG4_b.THRESHOLD_ACF = acf_threshold; + break; + case AMDF: + pVAD->VAD_CONF_REG5_b.THRESHOLD_NULL = config->null_threshold; + pVAD->VAD_CONF_REG5_b.THRESHOLD_NULL_COUNT = config->null_threshold_count; + pVAD->VAD_CONF_REG6_b.THRESHOLD_PEAK = config->peak_threshold; + pVAD->VAD_CONF_REG6_b.THRESHOLD_PEAK = config->peak_threshold_count; + break; + case WACF: + // write the threshold value to smpls_zero_cross bits + pVAD->VAD_CONF_REG4_b.THRESHOLD_WACF = wacf_threshold; + break; + case ZCR_ACF_AMDF_WACF: + pVAD->VAD_CONF_REG2_b.SMPLS_ZERO_CROSS = zcr_threshold; + pVAD->VAD_CONF_REG4_b.THRESHOLD_ACF = acf_threshold; + pVAD->VAD_CONF_REG5_b.THRESHOLD_NULL = config->null_threshold; + pVAD->VAD_CONF_REG5_b.THRESHOLD_NULL_COUNT = config->null_threshold_count; + pVAD->VAD_CONF_REG6_b.THRESHOLD_PEAK = config->peak_threshold; + pVAD->VAD_CONF_REG6_b.THRESHOLD_PEAK = config->peak_threshold_count; + pVAD->VAD_CONF_REG4_b.THRESHOLD_WACF = wacf_threshold; + break; + case ZCR_ACF: + pVAD->VAD_CONF_REG2_b.SMPLS_ZERO_CROSS = zcr_threshold; + pVAD->VAD_CONF_REG4_b.THRESHOLD_ACF = acf_threshold; + break; + case ZCR_AMDF: + pVAD->VAD_CONF_REG2_b.SMPLS_ZERO_CROSS = zcr_threshold; + pVAD->VAD_CONF_REG5_b.THRESHOLD_NULL = config->null_threshold; + pVAD->VAD_CONF_REG5_b.THRESHOLD_NULL_COUNT = config->null_threshold_count; + pVAD->VAD_CONF_REG6_b.THRESHOLD_PEAK = config->peak_threshold; + pVAD->VAD_CONF_REG6_b.THRESHOLD_PEAK = config->peak_threshold_count; + break; + case ZCR_WACF: + pVAD->VAD_CONF_REG2_b.SMPLS_ZERO_CROSS = zcr_threshold; + pVAD->VAD_CONF_REG4_b.THRESHOLD_WACF = wacf_threshold; + break; + default: + return INVALID_PARAMETERS; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_VAD_Set_Delay(RSI_VAD_T *pVAD, uint16_t startdelayval, uint16_t enddelayval) + * @brief This API is used to set start the end delay value for ACF,WACF,AMDF algorithm . + * @param[in] pVAD : Pointer to the VAD_Type structure. + * @param[in] startdelayval : This parameter define the start delay value for ACF,WACF,AMDF algorithm. + * maximum value is 1023 and default value is 2 + * @param[in] enddelayval : This parameter define the end delay value for ACF,WACF,AMDF algorithm. + * maximum value is 1023 and default value is 16 + * @return RSI_OK - If success + */ +rsi_error_t RSI_VAD_Set_Delay(RSI_VAD_T *pVAD, uint16_t startdelayval, uint16_t enddelayval) +{ + if ((startdelayval > MAXIMUM_VALUE_1024) || (enddelayval > MAXIMUM_VALUE_1024)) { + return INVALID_PARAMETERS; + } + // start delay + pVAD->VAD_CONF_REG7_b.START_DELAY_VAL = startdelayval; + // End delay + pVAD->VAD_CONF_REG7_b.END_DELAY_VAL = enddelayval; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_VAD_Input(RSI_VAD_T *pVAD, int16_t data) + * @brief This API is used to give the input for VAD. + * @param[in] pVAD : Pointer to the VAD_Type structure. + * @param[in] data : This parameter input for VAD block input is 1023 and default value is 16 + * @return RSI_OK - If success + */ +rsi_error_t RSI_VAD_Input(RSI_VAD_T *pVAD, int16_t data) +{ + if (data > MAXIMUM_VALUE_1024) { + return INVALID_PARAMETERS; + } + pVAD->VAD_CONF_REG8_b.EN_VAD_PROCESS = 1U; + /* Writing the data used as source for VAD */ + pVAD->VAD_CONF_REG8_b.INP_DATA = data; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_VAD_FrameEnergyConfig(RSI_VAD_T *pVAD, + * uint32_t threshold_frame_energy, + * uint32_t threshold_smpl_collect, + * uint32_t prog_smpls_for_energy_check) + * @brief This API is used to configure the frame energy. + * @param[in] pVAD : Pointer to the VAD_Type structure. + * @param[in] threshold_frame_energy : This parameter give the threshold frame energy, + * maximum value is 1023 and default value is 0. + * @param[in] threshold_smpl_collect : This parameter give the number of threshold sample collect, + * maximum value is 1023 and default value is 1. + * @param[in] prog_smpls_for_energy_check : This parameter define the sample for energy check, + * maximum value is 3 and default value is 1. + * @return RSI_OK - If success + */ +rsi_error_t RSI_VAD_FrameEnergyConfig(RSI_VAD_T *pVAD, + uint32_t threshold_frame_energy, + uint32_t threshold_smpl_collect, + uint32_t prog_smpls_for_energy_check) +{ + if ((threshold_frame_energy > MAXIMUM_VALUE_1024) || (threshold_smpl_collect > MAXIMUM_VALUE_1024) + || (prog_smpls_for_energy_check > MAXIMUM_VALUE_4)) { + return INVALID_PARAMETERS; + } + pVAD->VAD_CONF_REG3_b.THRESHOLD_FRAME_ENERGY = threshold_frame_energy; + pVAD->VAD_CONF_REG3_b.THRESHOLD_SMPL_COLLECT = threshold_smpl_collect; + pVAD->VAD_CONF_REG3_b.PROG_SMPLS_FOR_ENERGY_CHECK = prog_smpls_for_energy_check; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn void RSI_VAD_Stop(RSI_VAD_T *pVAD) + * @brief This API is used to disable VAD functionality. + * @param[in] pVAD : Pointer to the VAD_Type structure. + * @return none + */ +void RSI_VAD_Stop(RSI_VAD_T *pVAD) +{ + pVAD->VAD_CONF_REG8_b.EN_VAD_PROCESS = 0; +} + +/*==============================================*/ +/** + * @fn uint8_t RSI_VAD_ProccessDone(RSI_VAD_T *pVAD) + * @brief This API is used show the VAD energy detect. + * @param[in] pVAD : Pointer to the VAD_Type structure. + * @return The VAD energy detection status. + * If 1 - Energy detect. + * If 0 - No energy detect. + */ +uint8_t RSI_VAD_ProccessDone(RSI_VAD_T *pVAD) +{ + return pVAD->VAD_CONF_REG8_b.VAD_PROC_DONE; +} + +/*==============================================*/ +/** + * @fn void RSI_VAD_FastClkEnable(uint16_t fast_clk_sel, uint16_t clk_div_factor) + * @brief This API is used enable fast clock for VAD peripheral. + * @param[in] fast_clk_sel : fast clock select for VAD peripheral + * @param[in] clk_div_factor : Select the clock division factor for VAD peripheral + * @return none + */ +void RSI_VAD_FastClkEnable(uint16_t fast_clk_sel, uint16_t clk_div_factor) +{ + ULPCLK->ULP_VAD_CLK_GEN_REG_b.ULP_VAD_FCLK_EN = 1U; + ULPCLK->ULP_VAD_CLK_GEN_REG_b.ULP_VAD_FCLK_SEL = fast_clk_sel; + ULPCLK->ULP_VAD_CLK_GEN_REG_b.ULP_VAD_CLKDIV_FACTOR = clk_div_factor; +} + +/*==============================================*/ +/** + * @fn int32_t RSI_VAD_ProcessData(RSI_VAD_T *pVAD, + * uint32_t vad_addr, + * uint32_t adc_data_addr, + * int32_t dc_est, + * uint32_t dig_scale, + * uint32_t sample_len) + * @brief This API is used process data for input to VAD. + * @param[in] pVAD : Pointer to the VAD_Type structure. + * @param[in] vad_addr : VAD ULPSS memory address + * @param[in] adc_data_addr : ADC output data address + * @param[in] dc_est : dc estimation value. + * @param[in] dig_scale : Scaling the ADC output. + * @param[in] sample_len : Number of samples to process in VAD engine. + * @return dc estimation value - If success + */ +int32_t RSI_VAD_ProcessData(RSI_VAD_T *pVAD, + uint32_t vad_addr, + uint32_t adc_data_addr, + int32_t dc_est, + uint32_t dig_scale, + uint32_t sample_len) +{ + uint32_t index; + int32_t dc_est1 = 0; + int16_t temp_data = 0, data_in1 = 0; + static uint8_t flag = 1; + RSI_VAD_Stop(VAD); + + // processing the adc sample + for (index = 0; index < (sample_len); index++) { + data_in1 = ((*(volatile uint16_t *)(adc_data_addr + index * 2))); + + if (data_in1 & BIT(11)) { + data_in1 = data_in1 | (VAD_MASK_VALUE); + } else { + data_in1 = data_in1; + } + dc_est1 = dc_est1 + data_in1; + temp_data = data_in1 - dc_est; + temp_data = temp_data << dig_scale; + // fill data in VAD ping memory + ((*(volatile uint16_t *)(ULP_MEMORY_BASE + vad_addr + index * 2))) = temp_data; + } + + if ((dc_est == 0) && (flag == 1)) { + RSI_VAD_Stop(VAD); + flag = 0; + } else { + for (index = 0; index < (32); index++) { + /* fill data in VAD register */ + pVAD->VAD_CONF_REG8 = ((*(volatile uint16_t *)(ULP_MEMORY_BASE + vad_addr + index * 2))) | BIT(10); + } + for (index = 0; index < (sample_len); index++) { + // fill data in VAD register + pVAD->VAD_CONF_REG8 = ((*(volatile uint16_t *)(ULP_MEMORY_BASE + vad_addr + index * 2))) | BIT(10); + } + } + return dc_est1; +} diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_wurx.c b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_wurx.c new file mode 100644 index 000000000..cb1e44ba1 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_wurx.c @@ -0,0 +1,716 @@ +/******************************************************************************* +* @file rsi_wurx.c +* @brief +******************************************************************************* +* # License +* Copyright 2022 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +// Include Files + +/*==============================================*/ +/** + * @fn void RSI_WURX_Init(uint16_t bypass_l1_enable, uint16_t l1_freq_div, uint16_t l2_freq_div) + * @brief This API is used to initialization of l1 and l2 frequency as well as enable wurx. + * @param[in] bypass_l1_enable : Enable or disable the bypass functionality of level1 + * @param[in] l1_freq_div : Set the level1 frequency by using division factor ,This parameter define frequency. + * Ranges : 32 khz incoming clock then following option + * 0 : 0.125 khz, 1: 0.250 Khz, 2: 0.5 khz ,3: 1 khz, default : 2 khz + * Ranges : 64 khz incoming clock then following option + * 0 : 0.25 khz, 1: 0.5 Khz, 2: 1 khz ,3: 2 khz + * @param[in] l2_freq_div : Set the level2 frequency by using division factor ,This parameter define frequency. + * Ranges : 32 khz incoming clock then following option + * 0 : 4 khz, 1: 8 Khz, 2: 16 khz ,3: 32 khz + * Ranges : 64 khz incoming clock then following option + * 0 : 8 khz, 1: 16 Khz, 2: 32 khz ,3: 64 khz + * @return none + */ +void RSI_WURX_Init(uint16_t bypass_l1_enable, uint16_t l1_freq_div, uint16_t l2_freq_div) +{ + // Wait for Out of reset + while (!(WURX_MANUAL_CALIB_MODE_REG2 & 0x000001)) + ; + while (!(WURX_CORR_DET_READ_REG & 0x000002)) + ; + + // Bypass L1 pattern + WURX_BYPASS_LEVEL1_AND_FREQ |= (bypass_l1_enable << POS21); + + if (bypass_l1_enable) { + // Do nothing here + } else { + // Clear the frequency for L1 level pattern + WURX_BYPASS_LEVEL1_AND_FREQ &= ~(0x7 << POS18); + // Freq L1 pattern (3 : 32Khz, 2 : 16Khz, 1 : 8Khz, 0 : 4Khz) for 32KHz Clock + WURX_BYPASS_LEVEL1_AND_FREQ |= (l1_freq_div << POS18); + } + // Configure L2 pattern + // Clear the frequency for L2 pattern + WURX_BYPASS_LEVEL1_AND_FREQ &= ~(0x3 << POS16); + // Freq L2 pattern (3 : 32Khz, 2 : 16Khz, 1 : 8Khz, 0 : 4Khz) for 32KHz Clock + WURX_BYPASS_LEVEL1_AND_FREQ |= (l2_freq_div << POS16); + + WURX_ENABLE_AND_AAC_DET_REG |= (BIT(1) | BIT(0)); +} + +/*==============================================*/ +/** + * @fn void RSI_IPMU_40MhzClkCalib(uint16_t clk_enable, uint32_t channel_selection_value) + * @brief This API is used to calculate the 40MHZ VCO calibration. + * @param[in] clk_enable : Clock enable + * @param[in] channel_selection_value : This parameter define on which channel frequency use for transmission. + * E.g. If channel 11 use for transmission the channel_11 = 2475. + * channel_selection_value = (((channel_11)/(cal_clock*2)) * 2^6) + * So [channel_selection_value =(((2475)/(40*2)) * 2^6) + * Note : Refer RSI_WURX_CalVCOCalFreq() API ,its return calculated value. + * @return none + */ +void RSI_IPMU_40MhzClkCalib(uint16_t clk_enable, uint32_t channel_selection_value) +{ + volatile uint32_t cntr = 0, lco_coarse = 0, lco_fine = 0, chnl_freq = 0, coarse_word = 0, fine_word = 0; + + if (clk_enable) { + chnl_freq = channel_selection_value; + // vco manual + WURX_MANUAL_CALIB_MODE_REG1 &= ~(BIT(21)); + // NPSS REF Clock Cleaner OFF = 1 + ULPCLKS_REFCLK_REG |= (BIT(17)); + // NPSS REF Clock Cleaner ON = 0 by default is one + ULPCLKS_REFCLK_REG &= ~(BIT(18)); + // NPSS REF CLOCK Mux to SPI + ULPCLKS_REFCLK_REG &= ~(BIT(16)); + // Ulp_clk 32Mhz clock for Calibration + ULPCLKS_REFCLK_REG |= (BIT(21)); + // wait + for (cntr = 0; cntr < (10 * 4); cntr++) { + __ASM("nop"); + } + // NPSS REF Clock Cleaner ON = 1 + ULPCLKS_REFCLK_REG |= (BIT(18)); + // NPSS REF Clock Cleaner OFF = 0 + ULPCLKS_REFCLK_REG &= ~(BIT(17)); + + // Configure the frequency of reference clock as 0x400 + WURX_AAC_MODE_REG |= ((0x1 << POS20) | (REF_CLOCK_FREQ << POS7)); + + // Configure the receive channel frequency + WURX_LCO_FREQ_CALIB_REG |= ((BIT(13) | channel_selection_value)); + + // Checking the calibration done + while (!(WURX_TEST_MODE_REG & 0x000002)) + ; + while ((WURX_TEST_MODE_REG & 0x000002)) + ; + + // Read the LCO coarse and fine word + lco_coarse = ((WURX_MANUAL_CALIB_MODE_REG2) & (0x3E00)); + lco_fine = ((WURX_MANUAL_CALIB_MODE_REG2) & (0x3FC000)); + coarse_word = lco_coarse >> 9; + fine_word = lco_fine >> 14; + + // Calculating proper LCO fine word + while (fine_word == 255) { + chnl_freq = (chnl_freq - 4); + + WURX_MANUAL_CALIB_MODE_REG1 &= ~(BIT(21)); + // NPSS REF Clock Cleaner OFF = 1 + ULPCLKS_REFCLK_REG |= (BIT(17)); + // NPSS REF Clock Cleaner ON = 0 by default is one + ULPCLKS_REFCLK_REG &= ~(BIT(18)); + // NPSS REF CLOCK Mux to SPI + ULPCLKS_REFCLK_REG &= ~(BIT(16)); + // Ulp_clk 32Mhz clock for Calibration + ULPCLKS_REFCLK_REG |= (BIT(21)); + // wait + for (cntr = 0; cntr < (10 * 4); cntr++) { + __ASM("nop"); + } + // NPSS REF Clock Cleaner ON = 1 + ULPCLKS_REFCLK_REG |= (BIT(18)); + // NPSS REF Clock Cleaner OFF = 0 + ULPCLKS_REFCLK_REG &= ~(BIT(17)); + + // Configure the frequency of reference clock as 0x400 + WURX_AAC_MODE_REG |= ((0x1 << POS20) | (REF_CLOCK_FREQ << POS7)); + WURX_LCO_FREQ_CALIB_REG &= ~(0x000fff); + + // Configure new receive channel frequency + WURX_LCO_FREQ_CALIB_REG |= ((BIT(13) | (chnl_freq))); + + // Checking the calibration done + while (!(WURX_TEST_MODE_REG & 0x000002)) + ; + while ((WURX_TEST_MODE_REG & 0x000002)) + ; + + fine_word = ((WURX_MANUAL_CALIB_MODE_REG2) & (0x3FC000)) >> 14; + + if (fine_word < 255) { + coarse_word = (coarse_word + 1); + fine_word = (fine_word - 7 * (channel_selection_value - chnl_freq)); + } + } + // Modified the LCO fine and coarse word + lco_fine = fine_word - 6; + lco_coarse = coarse_word; + + // Write the LCO fine and coarse word manual calibration register + ULP_SPI_MEM_MAP(0x87) = 0x3F8000; + WURX_MANUAL_CALIB_MODE_REG1 = BIT(21) | lco_fine << POS13 | lco_coarse << POS8; + ULP_SPI_MEM_MAP(0x87) = 0x000000; + + for (cntr = 0; cntr < 4000 * 4; cntr++) { + __ASM("nop"); + } + + // Disable the calibration clock + WURX_AAC_MODE_REG &= ~(BIT(19) | BIT(20)); + ULPCLKS_REFCLK_REG |= (BIT(17)); + ULPCLKS_REFCLK_REG &= ~(BIT(18)); + } else { + WURX_AAC_MODE_REG &= ~(BIT(19) | BIT(20)); + /* NPSS Ref Clock CLeaner OFF */ + ULPCLKS_REFCLK_REG |= (BIT(17)); + ULPCLKS_REFCLK_REG &= ~(BIT(18)); + } + return; +} + +/*==============================================*/ +/** + * @fn void RSI_IPMU_DCCalib() + * @brief This API is used to calculate the manual DC calibration as well as enable periodic detection enable + * @return none + */ +void RSI_IPMU_DCCalib() +{ + uint16_t j, cal_val_ref = 0, det_ref = 0, cal_val = 0, i; + uint32_t cntr = 0; + + // Set manual dc calibration mode + WURX_COMP_OFFSET_CALIB_REG |= ((VAL1 << POS10) | (DC_OFFSET_VALUE << POS3) | (VAL2 << POS1)); + + // Enable the continuous calibration mode + WURX_ENABLE_AND_AAC_DET_REG |= BIT(2); + + // Calculate the appropriate detection reference shift value + for (i = 0; i <= 15; i++) { + WURX_LNA_IF_REG = (DETECTION_REF_SHIFT - i); + for (cntr = 0; cntr < 120000; cntr++) { + __ASM("nop"); + } + cal_val_ref = ((WURX_MANUAL_CALIB_MODE_REG1 & 0xFE) >> 1); + + if (cal_val_ref <= 100 && cal_val_ref >= 50) { + det_ref = 0; + for (j = 0; j <= 5; j++) { + for (cntr = 0; cntr < 120000; cntr++) { + __ASM("nop"); + } + cal_val = ((WURX_MANUAL_CALIB_MODE_REG1 & 0xFE) >> 1); + if (cal_val >= cal_val_ref - 3 && cal_val <= cal_val_ref + 3) { + det_ref++; + } + } + if (j == det_ref) { + break; + } + } + } +} + +/*==============================================*/ +/** + * @fn void RSI_WURX_CorrEnable(uint16_t wurx_enable) + * @brief This API is used enable wurx correlation. + * @param[in] wurx_enable : Enable wurx correlation + * @return none + */ +void RSI_WURX_CorrEnable(uint16_t wurx_enable) +{ + if (wurx_enable) { + // Correlation Enable + MCU_FSM->MCU_FSM_CRTL_PDM_AND_ENABLES |= (BIT(1)); + } else { + // Disable wurx and clk_en + MCU_FSM->MCU_FSM_CRTL_PDM_AND_ENABLES &= ~(BIT(1)); + } +} + +/*==============================================*/ +/** + * @fn void RSI_WURX_SetWakeUpThreshold(uint16_t threshold_1, uint16_t threshold_2) + * @brief This API is used set up threshold value for operation. + * @param[in] threshold_1 : Threshold value for pattern1. + * @param[in] threshold_2 : Threshold value for pattern2. + * @return none + */ +void RSI_WURX_SetWakeUpThreshold(uint16_t threshold_1, uint16_t threshold_2) +{ + // clear bit9 to 14 + WURX_CORR_CALIB_REG &= ~(THRESH_CLR_MASK_VAL << POS9); + // Set threshold value for pattern1 + WURX_CORR_CALIB_REG |= (threshold_1 << POS9); + + // clear bit3 to 8 + WURX_CORR_CALIB_REG &= ~(THRESH_CLR_MASK_VAL << POS3); + // Set threshold value for pattern2 + WURX_CORR_CALIB_REG |= (threshold_2 << POS3); +} + +/*==============================================*/ +/** + * @fn void RSI_WURX_Pattern2DetectionEnable(uint16_t enable) + * @brief This API is used enable pattern2. + * @param[in] enable : Enable the pattern2 detection bit . + * @return none + */ +void RSI_WURX_Pattern2DetectionEnable(uint16_t enable) +{ + if (enable) { + // Pattern2 detection enable + WURX_CORR_CALIB_REG |= BIT(18); + } else { + // Pattern2 detection disable + WURX_CORR_CALIB_REG &= ~BIT(18); + } +} + +/*==============================================*/ +/** + * @fn void RSI_WURX_TailDataDecodeEnable(uint16_t enable, uint16_t data_len) + * @brief This API is used to enable the Tail data decode. + * @param[in] enable : Enable the tail data decode bit. + * @param[in] data_len : Set the detection bit length. + * - 0 for 64 bit + * - 1 for 128 bit + * - 2 for 192 bit + * - 3 for 256 bit + * @return none + */ +void RSI_WURX_TailDataDecodeEnable(uint16_t enable, uint16_t data_len) +{ + if (enable) { + WURX_CORR_CALIB_REG &= ~VAL3; + // WURX Decode Tail bits + WURX_CORR_CALIB_REG |= BIT(2) | data_len; + } else { + WURX_CORR_CALIB_REG &= ~BIT(2); + } +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_WURX_GetTailData(uint32_t *tail_data, uint16_t tail_data_len) + * @brief This API is used get the tail data + * @param[in] tail_data : Pointer to store the tail data. + * @param[in] tail_data_len : This parameter define number of bit read in tail data. + * - 0 for 64 bit + * - 1 for 128 bit + * - 2 for 192 bit + * - 3 for 256 bit + * @return Receive pattern tail data - If Success + */ +rsi_error_t RSI_WURX_GetTailData(uint32_t *tail_data, uint16_t tail_data_len) +{ + if (tail_data_len == TAIL_DATA_DECODE_64BIT) { + // get 64 bit tail data + while (!(WURX_CORR_DET_READ_REG & BIT(16))) + ; + RSI_WURX_ReadPattern1Odd(tail_data); + } else if (tail_data_len == TAIL_DATA_DECODE_128BIT) { + // get 128 bit tail data + while (!(WURX_CORR_DET_READ_REG & BIT(17))) + ; + RSI_WURX_ReadPattern1Odd(tail_data); + while (!(WURX_CORR_DET_READ_REG & BIT(16))) + ; + RSI_WURX_ReadPattern1Even(tail_data); + } else if (tail_data_len == TAIL_DATA_DECODE_192BIT) { + // get 192 bit tail data + while (!(WURX_CORR_DET_READ_REG & BIT(17))) + ; + RSI_WURX_ReadPattern1Odd(tail_data); + while (!(WURX_CORR_DET_READ_REG & BIT(16))) + ; + RSI_WURX_ReadPattern1Even(tail_data); + while (!(WURX_CORR_DET_READ_REG & BIT(15))) + ; + RSI_WURX_ReadPattern2Odd(tail_data); + } else if (tail_data_len == TAIL_DATA_DECODE_256BIT) { + // get 256 bit tail data + while (!(WURX_CORR_DET_READ_REG & BIT(17))) + ; + RSI_WURX_ReadPattern1Odd(tail_data); + while (!(WURX_CORR_DET_READ_REG & BIT(16))) + ; + RSI_WURX_ReadPattern1Even(tail_data); + while (!(WURX_CORR_DET_READ_REG & BIT(15))) + ; + RSI_WURX_ReadPattern2Odd(tail_data); + while (!(WURX_CORR_DET_READ_REG & BIT(14))) + ; + RSI_WURX_ReadPattern2Even(tail_data); + } else { + return INVALID_PARAMETERS; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn uint32_t RSI_WURX_CalThershValue(uint32_t bit_length, uint32_t percentage) + * @brief This API is used to calculate the threshold value. + * @param[in] bit_length : Bit length 64 or 32 bit. + * @param[in] percentage : Percentage the calculate the threshold value. + * @return If success - the threshold value. + */ +uint32_t RSI_WURX_CalThershValue(uint32_t bit_length, uint32_t percentage) +{ + return ((percentage * bit_length) / VAL100); +} + +/*==============================================*/ +/** + * @fn void RSI_WURX_Pattern1MatchValue(uint32_t *match_value) + * @brief This API is used set the match value for detection pattern1 purpose. + * @param[in] match_value : Pointer to the Match value. + * @return none + */ +void RSI_WURX_Pattern1MatchValue(uint32_t *match_value) +{ + // Configure MSB match value for pattern1 + WURX_PATTERN1_REG_MSB = match_value[VAL0]; + + // Configure MID match value for pattern1 + WURX_PATTERN1_REG_MID = match_value[VAL1]; + + // Configure LSB match value for pattern1 + WURX_PATTERN1_REG_LSB = match_value[VAL2]; +} + +/*==============================================*/ +/** + * @fn void RSI_WURX_Pattern2MatchValue(uint32_t *match_value) + * @brief This API is used set the match value for detection pattern2 purpose. + * @param[in] match_value : Pointer to the Match value. + * @return none + */ +void RSI_WURX_Pattern2MatchValue(uint32_t *match_value) +{ + // Configure MSB match value for pattern2 + WURX_PATTERN2_REG_MSB = match_value[VAL0]; + + // Configure MID match value for pattern2 + WURX_PATTERN2_REG_MID = match_value[VAL1]; + + // Configure LSB match value for pattern2 + WURX_PATTERN2_REG_LSB = match_value[VAL2]; +} + +/*==============================================*/ +/** + * @fn void RSI_WURX_SetPatternLength(uint16_t enable, uint16_t l1_len, uint16_t l2_len) + * @brief This API is used set pattern length for wakeup + * @param[in] enable : Enable the set pattern length API. + * @param[in] l1_len : value to decide the l1 pattern length. + * Ranges 0: 2 bits , 1: 4 bits , 2:8 bits 3: 16 bits + * @param[in] l2_len : value to decide the l2 pattern length . + * Ranges 1 : 1 bits, 2: 2 bits, 3: 4 bits + * 4 : 8 bits, 5: 16 bits, 6: 32 bits + * 0,7: 64 bits + * @return none + */ +void RSI_WURX_SetPatternLength(uint16_t enable, uint16_t l1_len, uint16_t l2_len) +{ + if (enable) { + // clear pattern length + WURX_CORR_CALIB_REG &= ~(PATTERN_LEN_CLR_MASK << POS15); + // pattern length + WURX_CORR_CALIB_REG |= l2_len << POS15; + // set pattern length for l1 + WURX_LEVEL1_PATTERN_REG |= (l1_len << POS20); //2 bits pass 1 for 4 bit + } else { + // disable + WURX_CORR_CALIB_REG &= ~(l2_len << POS15); + } +} + +/*==============================================*/ +/** + * @fn uint16_t RSI_WURX_ReadPatternLength() + * @brief This API is used read pattern length + * @return If success - pattern length value + */ +uint16_t RSI_WURX_ReadPatternLength() +{ + uint16_t value; + + // pattern length + value = (WURX_CORR_CALIB_REG & (PATTERN_LEN_MASK)) >> POS15; + + return value; +} + +/*==============================================*/ +/** + * @fn void RSI_WURX_AnalogOff() + * @brief This API is used to off the wurx analog block. + * @return none + */ +void RSI_WURX_AnalogOff() +{ + volatile uint32_t spareReg = 0; + + WURX_ENABLE_AND_AAC_DET_REG &= ~(BIT(0)); + spareReg = ULP_SPI_MEM_MAP(IPMU_SPARE_REG2); + spareReg &= ~BIT(20); + ULP_SPI_MEM_MAP(IPMU_SPARE_REG2) = spareReg; + ULP_SPI_MEM_MAP(IPMU_SPARE_REG2) &= ~BIT(21); + WURX_TEST_MODE_REG |= BIT(19); +} + +/*==============================================*/ +/** + * @fn void RSI_WURX_DigitalOff() + * @brief This API is used to off the digital block. + * @return none + */ +void RSI_WURX_DigitalOff() +{ + RSI_IPMU_PowerGateClr(WURX_CORR_PG_ENB | WURX_PG_ENB); +} + +/*==============================================*/ +/** + * @fn void RSI_WURX_ReadPattern1Odd(uint32_t *tail_data) + * @brief This API is used read odd 64 bit in pattern1. + * @param[in] tail_data : Its data where we store the tail data. + * @return none + */ +void RSI_WURX_ReadPattern1Odd(uint32_t *tail_data) +{ + uint32_t read_tail_data = 0; + + // Read 22 LSB bits of odd pattern1 + tail_data[VAL0] = WURX_ODD_PATTERN1_REG_LSB; + + // Read 22 MID bits of odd pattern1 + read_tail_data = WURX_ODD_PATTERN1_REG_MID; + read_tail_data = (read_tail_data << POS22); + + // Write first 10 bits of odd pattern1 MID register in output buffer + tail_data[VAL0] = tail_data[VAL0] | read_tail_data; + read_tail_data = 0; + + // Read MID bits of odd pattern1 + read_tail_data = WURX_ODD_PATTERN1_REG_MID; + read_tail_data = (read_tail_data >> POS10); + + // Write last 12 bits of odd pattern1 MID register in output buffer + tail_data[VAL1] = read_tail_data; + read_tail_data = 0; + + // Read 20 MSB bits of odd pattern1 + read_tail_data = WURX_ODD_PATTERN1_REG_MSB; + read_tail_data = read_tail_data << POS12; + tail_data[VAL1] = tail_data[VAL1] | read_tail_data; +} + +/*==============================================*/ +/** + * @fn void RSI_WURX_ReadPattern1Even(uint32_t *tail_data) + * @brief This API is used read even 64 bit in pattern1. + * @param[in] tail_data : Its data where we store the tail data. + * @return none + */ +void RSI_WURX_ReadPattern1Even(uint32_t *tail_data) +{ + uint32_t read_tail_data = 0; + + // Read 22 LSB bits of even pattern1 + tail_data[VAL2] = WURX_EVEN_PATTERN1_REG_LSB; + + // Read 22 MID bits of even pattern1 + read_tail_data = WURX_EVEN_PATTERN1_REG_MID; + read_tail_data = (read_tail_data << POS22); + + // Write first 10 bits of even pattern1 MID register in output buffer + tail_data[VAL2] = tail_data[VAL2] | read_tail_data; + read_tail_data = 0; + + // Read MID bits of even pattern1 + read_tail_data = WURX_EVEN_PATTERN1_REG_MID; + read_tail_data = (read_tail_data >> POS10); + + // Write last 12 bits of even pattern1 MID register in output buffer + tail_data[VAL3] = read_tail_data; + read_tail_data = 0; + + // Read 20 MSB bits of even pattern1 + read_tail_data = WURX_EVEN_PATTERN1_REG_MSB; + read_tail_data = read_tail_data << POS12; + tail_data[VAL3] = tail_data[VAL3] | read_tail_data; +} + +/*==============================================*/ +/** + * @fn void RSI_WURX_ReadPattern2Odd(uint32_t *tail_data) + * @brief This API is used read odd 64 bit in pattern2. + * @param[in] tail_data : Its data where we store the tail data. + * @return none + */ +void RSI_WURX_ReadPattern2Odd(uint32_t *tail_data) +{ + uint32_t read_tail_data = 0; + + // Read 22 LSB bits of odd pattern2 + tail_data[VAL4] = WURX_ODD_PATTERN2_REG_LSB; + + // Read 22 MID bits of odd pattern2 + read_tail_data = WURX_ODD_PATTERN2_REG_MID; + read_tail_data = (read_tail_data << POS22); + + // Write first 10 bits of odd pattern1 MID register in output buffer + tail_data[VAL4] = tail_data[VAL4] | read_tail_data; + read_tail_data = 0; + + // Read MID bits of odd pattern2 + read_tail_data = WURX_ODD_PATTERN2_REG_MID; + read_tail_data = (read_tail_data >> POS10); + + // Write last 12 bits of odd pattern2 MID register in output buffer + tail_data[VAL5] = read_tail_data; + read_tail_data = 0; + + // Read 20 MSB bits of odd pattern2 + read_tail_data = WURX_ODD_PATTERN2_REG_MSB; + read_tail_data = read_tail_data << POS12; + tail_data[VAL5] = tail_data[VAL5] | read_tail_data; +} + +/*==============================================*/ +/** + * @fn void RSI_WURX_ReadPattern2Even(uint32_t *tail_data) + * @brief This API is used read even 64 bit in pattern2. + * @param[in] tail_data : Its data where we store the tail data. + * @return none + */ +void RSI_WURX_ReadPattern2Even(uint32_t *tail_data) +{ + uint32_t read_tail_data = 0; + + // Read 22 LSB bits of even pattern2 + tail_data[VAL6] = WURX_ODD_PATTERN2_REG_LSB; + + // Read 22 MID bits of even pattern2 + read_tail_data = WURX_ODD_PATTERN2_REG_MID; + read_tail_data = (read_tail_data << POS22); + + // Write first 10 bits of even pattern2 MID register in output buffer + tail_data[VAL6] = tail_data[VAL6] | read_tail_data; + read_tail_data = 0; + + // Read MID bits of even pattern2 + read_tail_data = WURX_ODD_PATTERN2_REG_MID; + + // Write last 12 bits of even pattern2 MID register in output buffer + read_tail_data = (read_tail_data >> POS10); + tail_data[VAL7] = read_tail_data; + read_tail_data = 0; + + // Read 20 MSB bits of even pattern2 + read_tail_data = WURX_ODD_PATTERN2_REG_MSB; + read_tail_data = read_tail_data << POS12; + tail_data[VAL7] = tail_data[VAL7] | read_tail_data; +} + +/*==============================================*/ +/** + * @fn uint16_t RSI_WURX_TaildataPresent() + * @brief This API is used to verify the tail data detection is present or not. + * @return the number which contain how much data we want to read in tail data e.g if return 0 then 64bit , if 1 then 128 bit and so on. + */ +uint16_t RSI_WURX_TaildataPresent() +{ + uint16_t read; + read = WURX_CORR_CALIB_REG; + read = read & TAIL_DATA_VALUE_CHECK; + return read; +} + +/*==============================================*/ +/** + * @fn void RSI_WURX_SoftwareRestart(void) + * @brief This API is used to do software restart. + * @return none + */ +void RSI_WURX_SoftwareRestart(void) +{ + uint32_t i; + // soft_reset_corr set + WURX_CORR_CALIB_REG |= BIT(21); + while (GSPI_CTRL_REG1 & SPI_ACTIVE) + ; + for (i = 0; i < 400; i++) { + __ASM("nop"); + } + // soft_reset_corr clear + WURX_CORR_CALIB_REG &= ~BIT(21); + while (GSPI_CTRL_REG1 & SPI_ACTIVE) + ; +} + +/*==============================================*/ +/** + * @fn int32_t RSI_WURX_GetPatternType(void) + * @brief This API is use to get pattern type . e.g pattern1 or pattern2 or false wakeup. + * @return If success - Pattern type + * If fails - -1 + */ +int32_t RSI_WURX_GetPatternType(void) +{ + if ((WURX_CORR_DET_READ_REG & BIT(20)) | (WURX_CORR_DET_READ_REG & BIT(21))) { + return 1; + } else if ((WURX_CORR_DET_READ_REG & BIT(19)) | (WURX_CORR_DET_READ_REG & BIT(18))) { + return 2; + } else { + return -1; + } +} + +/*==============================================*/ +/** + * @fn uint32_t RSI_WURX_CalVCOCalFreq(uint32_t frequncy_value) + * @brief This API is use VCO calibration frequency value. + * @param[in] frequncy_value : Transmission channel frequency value. + * @return If success - the VCO calibration frequency value. + */ +uint32_t RSI_WURX_CalVCOCalFreq(uint32_t frequncy_value) +{ + frequncy_value = (((float)frequncy_value / (80)) * 64); + return frequncy_value; +} + +/*==============================================*/ +/** + * @fn void RSI_WURX_BGSamplingEnable() + * @brief This API is use enable BG sampling mode. + * @return none + */ +void RSI_WURX_BGSamplingEnable() +{ + *(volatile uint32_t *)BG_SAMPLING_ADDR = BG_SAMPLING_VALUE; + + // Moving to BG sampling mode + *(volatile uint32_t *)0x24048140 = 0x3; +} diff --git a/demos/brd2605a/out_of_box_demo.rps b/demos/brd2605a/out_of_box_demo.rps index 95cb8068d23f58de3b65c7167a492f6ac5a84593..0d3978b46a5337027e1ade8e2fcff2e7f1d8660d 100644 GIT binary patch delta 147 zcmca|lL z&5RR~*h15_S{Uy_1hlprwK94#LOIiywK2|wu&+TVgYE7ejABrE&F$@-jH`g0?MB^< Gi^Ku)oiN4# delta 147 zcmca|lL z&5RR~*h15_S{Uy_1hlprwK94#LOIiywK2|wu&+TVgYE7ejABrE&F$@-jH`g0?MB^< Gi^Ku^P%zX0 diff --git a/demos/brd2605a/siwx917_dev_kit.rps b/demos/brd2605a/siwx917_dev_kit.rps index e2b6e395237cfaf87a89b1eca7b9771aa4f79d56..104211215319d523ac757873f29f2db54ad3e194 100644 GIT binary patch delta 168 zcmdn8ntjV^_6Z^^F>KstCI+fB+HAF9tPN%~nLa<1QDOS6V8&h~w)*t-A&e#v0qg1V zp^Wtq_7@1HHGN+g<7)_8bNc0Q##cZ#e>9`k^cN9~-7xmNNXD5Ew!!p_D8^-sCfk8( b+!&$yw%5lno&j>U`@}Jdg6O1p#-K6)uAVj( delta 168 zcmdn8ntjV^_6Z^^qVA1(69ZKmZMNDl)&?^gPoE#ks4)FjFk>$gTYdWa5JnS-fc13w zP{w))`wN89n!YcL@im04IsI}t<0~MWKblc%`ilt0ZWw!BB;!m7+hBS|6yq{R*rqv*YoYAzJh_aqj4;mRJjM*rqv*YoYAzJh_aqj4;mRJjME)PKK*nXqY0S53rt#1 z|JKfU7tGY${mFGdJ^dSMsiEGW~on{h2v1y2v7EL6qz;9ka6K=$^3eT?(O0dmhR As{jB1 diff --git a/demos/brd4342a/out_of_box_demo.rps b/demos/brd4342a/out_of_box_demo.rps index 7f23be095b463baf414905dccc2f38594f3a5251..a6fff35df5d05420b4ae37385e550b5153f883cd 100644 GIT binary patch delta 142 zcmca}j_uAlwh1CEHB&#Xni#0kXtULZvAd1YWcq=2Muq7w+8Cpe*y_`}+ZjzD0=poT z_4I8WjCUby&Fyxoau($jI&_uuicDmVT#W5Fv`LdZ5QriTm|H8-`CGLPaFW? CfHrLa delta 142 zcmca}j_uAlwh1CE>vwF5oEWImXtULZvAd1Yc=~~MMuq7w+8Cpe*y_`}+ZjzD0=poT z_4I8WjCUby&Fyxoau($jI&_uuicDmVT#W5Fv`LdZ5QriTm|H8-`CGLPaFWj CIW{Q( diff --git a/demos/brd4343a/out_of_box_demo.rps b/demos/brd4343a/out_of_box_demo.rps index dda40dda117f2678156088bb8f864055a4c8f5c9..60c56e51acc6a74a78a75a1eb07b512e2cc36a35 100644 GIT binary patch delta 142 zcmX?ehV9H5wh1CE8!j_`ni#0kXtULZvAUJfWcr3SMuq7&S{b8}*y_`(+ZatC0=poT z_4H-!jCUby&FyPD7`+&woau^PjI&_ur(KL|VT$&2Gs?mgZD;OfTm|H8U)RStPaFVS CaWuaG delta 142 zcmX?ehV9H5wh1CE$^V=fCkCoC+HAF9tZrpAp1z@tQDORxR>o)~w)*tyHbxVOz%B@7 zJ$+d_<6Q__bNkv3MlVJvXS!k+<185aX&2*Kn4&%1jIuCA+nIYAR{=TO*Yz>Z69)k8 C`!nMJ diff --git a/docs/release-notes/index_ncp.md b/docs/release-notes/index_ncp.md index 7a7d5786f..652b927e6 100644 --- a/docs/release-notes/index_ncp.md +++ b/docs/release-notes/index_ncp.md @@ -1,3 +1,459 @@ +# **WiSeConnect3\_SDK\_3.3.4 NCP Release Notes**    + +## **Release Details** + +|**Item**|**Details**| +| :- | :- | +|Release date|18th October 2024| +|SDK Version|3\.3.4| +|Firmware Version|Standard: 1711.2.12.3.3.0.3| +|GSDK/SiSDK Version|SiSDK 2024.6.2 | +|Studio Version|5\.9.3.0| +|Release Package Name|WiSeConnect3\_SDK\_3.3.4| +|Operating Modes Supported|Wi-Fi STA, Wi-Fi AP, Wi-Fi STA+BLE, Wi-Fi STA+AP| + +- SiWx917 release consists of two components + - Standard Wireless Firmware -  SiWx917 Firmware Binary available as SiWG917-B.2.12.3.3.0.3.rps + - Wiseconnect3 Library - Wiseconnect3 SDK library runs on the external host in NCP mode. + +Note: + +- The release packages will have bug-fixes, enhancements, and new features in both 'SDK' and 'Firmware'. Customer shall update and use 'SDK' and 'Firmware' of same release package. SDK and FW combinations that are not released together are not supported. + +## **Supported Hardware OPNs** + +|**Hardware**|**OPN (Ordering Part Number)**| +| :- | :- | +|IC OPN|

QFN OPN: SiWN917M100LGTBA (Wi-Fi 6 NCP IC, QFN 7x7, 2.4 GHz, 4MB stacked flash, -40 to +85C​) 

Module OPN: SiWN917Y100LGNBx

| +|Expansion kits:|

SiWx917-EB4346A (based on Radio board SiWx917-4346A + 8045A Co-Processor Adapter board)

Module Board: SiW917Y-RB4357A (SiWN917Y Module Wi-Fi 6 and Bluetooth LE 4MB Flash RF-Pin Co-Processor Radio Board)

| + +## **Supported Features**  + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
SectionSub-SectionFeature
SystemOperating modesWi-Fi STA (802.11ax, 802.11n)
Wi-Fi 802.11n AP
Wi-Fi STA (802.11ax, 802.11n) + 802.11n AP
Wi-Fi STA (802.11ax, 802.11n) + BLE
Wi-Fi Transceiver (802.11 b/g)
Security Secure Boot, Secure Key storage and HW device identity with PUF, Secure Zone, Secure XIP (Execution in place) from flash, Secure Attestation, Anti Rollback, Debug Lock, Flash Protection
Secure firmware upgrade options

- Firmware loading through UART, SPI Interface

- Secure Over the Air (OTA) Upgrade

- Firmware update via Bootloader

Crypto Support

- Crypto API's for Hardware Accelerators: Advanced Encryption Standard (AES) 128/256/192, Secure Hash Algorithm (SHA) 256/384/512, Hash Message Authentication Code (HMAC), Random Number Generator (RNG), SHA3, AES-Galois Counter Mode (GCM)/ Cipher based Message Authentication Code (CMAC), ChaCha-poly, True Random Number Generator (TRNG)

- Software Accelerators: RSA, ECC

- Wrapping Secret keys (Symmetric crypto). 

- Added ECDSA Sign and Verify APIs

System Power Save

- Deep Sleep with RAM retention and without RAM retention. 

- Wireless Power Save: Connected Sleep (Wi-Fi Standby Associated), BLE Advertising with powersave, BLE Scan with powersave ,  BLE connection with powersave. Only Max PSP power save mode is supported in BLE. 

Wi-FiWi-Fi ProtocolsIEEE 802.11 b/g/n/ax (2.4GHz)
Access Point (AP) Mode

- 4 Client Support, Hidden SSID Mode, Auto Channel Selection, Scan in AP mode (Alpha)

- Wi-Fi Security 

- WPA2 Personal, WPA3 Personal (H2E method only) (Alpha), WPA Mixed mode (WPA/WPA2) 

Wi-Fi ScanSelective Scan, Active/Passive Scan
Wi-Fi STA (Security Modes)Open Mode, WPA2 Personal, WPA2 Enhancements, WPA3 Personal, Mixed Mode (WPA/WPA2), WPA3 Personal Transition Mode (WPA2/WPA3)
WPA2 Enterprise security (STA)Method: PEAP/TTLS/TLS 1.0/TLS 1.2/FAST/LEAP
Wi-Fi STA Rejoin
Wi-Fi STA Roaming BG Scan, OKC (Opportunistic Key caching), PMK (Pairwise Master Key) caching, Pre-Authentication
Wi-Fi Protocol Power Save Deep sleep (unconnected state), Max PSP, Enhanced Max PSP, Fast PSP, TWT
QoSWMM-QoS
Wi-Fi 6 FeatureMU-MIMO (DL), OFDMA (UL/DL), iTWT, TWT I-Frame & TWT Enhancements (Automatic TWT Configuration), BSS coloring, MBSSID
Wi-Fi Concurrency AP+STA (Same channel)
Wi-Fi Band/Channels2\.4GHz CH1-11, 2.4GHz CH1-13, 2.4GHz CH1-14
Known Security Vulnerabilities HandledWPA2 KRACK Attacks, Fragment and Forge Vulnerability
Network stackCore Networking Features

- IPv4/IPv6/UDP/TCP/ARP/ICMP/ICMPv6

- SSL client versions TLSV1.0, TLSV1.2, TLSV1.3 

- SSL server versions TLSV1.0 and TLSV1.2

- DHCPv4 Client,DHCPv6 Client

- DHCPv4 Server,DHCPv6 Server

- TCP/IP Bypass (LWIP as Hosted stack for reference)

Advanced Network Features- HTTP Client/HTTPS Client/DNS Client/SNTP Client, Embedded MQTT, MQTT on host, IGMP
Wi-Fi IoT Cloud Integration

- AWS IoT Core

- Azure IoT Core

BSD and IoT sockets application programming interface(API)
BLE Legacy features

- GAP(Advertising, Scanning, initiation, Connection and Bonding)

- Generic Attribute Protocol(GATT)

- Attribute protocol(ATT)

- Security

- LL Privacy 1.2

- Accept list

- Directed Advertising

- LE PHY(1Mbps, 2Mbps) & Coded PHY(125kbps, 500kbps)

- Simultaneous scanning on 1Mbps and Coded PHY

- LE dual role topology

- LE data packet length extensions(DLE)

- Asymmetric PHYs

- LE channel selection algorithm 2 (CSA#2)

- LE Secure connections

- Bluetooth 5.4 Qualified

Advertising Extensions 

- Extended Advertising

- Periodic Advertising

- Periodic Advertising scanning

- Extended Advertising scanning

- Periodic Advertising list

- LE periodic advertising synchronization

+ +### **Development Environment** + +- Simplicity Studio IDE (SV5.9.3.0 version) and Debugger Integration. Refer to the latest version of the NCP "Getting-Started-with-SiWx917" guide for more details +- Recommended to install and use Silicon labs Simplicity SDK (Previously known as Gecko SDK), Git hub based version 2024.6.2 +- Simplicity Commander to supports Flash loading, provision of MBR programming, security key management, and calibration support for crystal and gain offsets. refer "siwx917-ncp-manufacturing-utility-user-guide" for more details +- Advanced Energy Monitoring (AEM) to measure ultra-low power capability on Development boards (Radio board SiWx917-4346A + 8045A Co-Processor Adapter board) + +### **SDK** + +- Simplified and Unified DX for Wi-Fi API  +- Simplifies application development and presents clean and standardized APIs +- BSD and ARM IoT-compliant socket API +- Available through Simplicity Studio and GitHub + +### **Multi-protocol** + +- Wi-Fi STA + BLE + +### **PTA CoExistence** + +- 3 wire CoEx acting as Wi-Fi with external Bluetooth  +- 3 wire CoEx acting as Wi-Fi with external Zigbee/OT + +## **Changes in this release compared to v3.3.3 Release** + +### **System** + +- **Enhancements / New features** + - None +- **Fixed Issues** + - None +- **Documentation** + - **None** + +### **SDK** + +- **Enhancements / New features** + - None +- **Fixed Issues** + - None +- **Documentation** + - None + +### **Wi-Fi/Network Stack** + +- **Enhancements / New features** + - None +- **Fixed Issues** + - None +- **Documentation** + - None + +### **BLE** + +- **Enhancements / New features** + - None +- **Fixed Issues** + - None +- **Documentation** + - None + +### **Multi-protocol** + +- **Enhancements / New features** + - None +- **Fixed Issues** + - None +- **Documentation** + - None + +## **Recommendations** + +### **System** + +- Set the recommended Power Save Profile (PSP) type to Enhanced Max PSP +- Memory configuration for NCP mode is 672K\_M4SS\_0K +- Set the following recommended FreeRTOS configuration in FreeRTOSConfig.h + - configTIMER\_TASK\_PRIORITY to 55  + - configTOTAL\_HEAP\_SIZE to 51200 + - configUSE\_POSIX\_ERRNO to 1 + +### **Wi-Fi/Network Stack** + +- It is recommended to enable SL\_SI91X\_EXT\_TCP\_IP\_WAIT\_FOR\_SOCKET\_CLOSE BIT(16) of the 'Extended TCP IP Feature' bit map in the opermode command for all Wi-Fi Socket operations from the host to ensure graceful handling during asynchronous closures from the peer +- For high throughputs,  it is recommended to enable BIT(2) - SL\_SI91X\_FEAT\_AGGREGATION  of feature\_bit\_map in opermode.  +- Users can enable SL\_SI91X\_EXT\_TCP\_IP\_SSL\_16K\_RECORD in 'Extended TCP IP Feature' bit map in opermode for (HTTPS server) supporting 16k record +- **TWT** + - Recommendation is to use sl\_wifi\_target\_wake\_time\_auto\_selection() API for all TWT applications + - It is recommended to issue iTWT setup command once IP assignment, TCP connection, application specific socket connections are done + - When using sl\_wifi\_enable\_target\_wake\_time API, increase TCP / ARP Timeouts at the remote side depending upon the configured TWT interval configured. It's highly recommended to use sl\_wifi\_target\_wake\_time\_auto\_selection() as an alternative + - In case of TWT in CoEx mode, when using sl\_wifi\_enable\_target\_wake\_time API, use TWT wake duration <= 16 ms and TWT wake interval >= 1 sec. If wake duration > 16 ms or TWT wake interval < 1sec, there might be performance issues + - For iTWT GTK interval in AP should be configured to max possible value or zero. If GTK interval is not configurable on AP side, recommended TWT interval (in case of sl\_wifi\_enable\_target\_wake\_time API) or RX Latency (in case of sl\_wifi\_target\_wake\_time\_auto\_selection API) is less than 4sec + - When sl\_wifi\_enable\_target\_wake\_time API is used, configuring TWT Wake interval beyond 1 min might lead to disconnections from the AP. Recommended to use TWT wake interval of less than or equal to 1 min + - When using sl\_wifi\_enable\_target\_wake\_time API, it is recommended to set missed\_beacon\_count of sl\_wifi\_set\_advanced\_client\_configuration API greater than 2 times of the configured TWT Interval. + - DUT keepalive should be configured aligned with AP keepalive in TWT modes. +- Disable power save for high throughput applications or use FAST PSP power save mode as per application requirement +- The application needs to ensure that it sets RTC with the correct timestamp before establishing the SSL/EAP connection +- The minimum timeout value should not be less than 1 second for socket select and socket receive calls +- Please refer Keep alive intervals supported by MQTT broker and configure keep alive interval values accordingly +- The minimum keep alive interval  value recommended for embedded MQTT is 10 Seconds +- Disable power save and suspend any active TWT sessions before triggering HTTP OTAF +- Randomize the client port if using rapid connect/disconnect of the MQTT session on the same client port with the power save +- Recommended to configure VAP\_ID properly for Si91x STA and AP using sl\_si91x\_setsockopt\_async(), in case of data transfer. +- Recommended to use valid length(<= 202 bytes) for topic to be published while using Embedded MQTT, else it leads to return wrong error code(0x21). +- In concurrent mode with dual IP, it is advised to bring up STA first (IP configuration) and AP later +- It is recommended to configure Tx, Rx, Global buffer pool ratio in the buffer config command for all Wi-Fi Socket operations from the host +- It is recommended to use "TCP exponential backoff" configuration for congested channels +- It is recommended is to disable broadcast filter during TCP connection to avoid ARP resolution issues +- To avoid IOP issues, it is recommended to disable power save before Wi-Fi connection +- Enable BIT(10)  SL\_SI91X\_FEAT\_SSL\_HIGH\_STREAMING\_BIT in feature bitmap to increase TLS\_Rx throughputs. +- It is recommended to set region\_code as `IGNORE\_REGION` in boot configurations for ACx module boards except for PER mode. + +### **BLE** + +- In BLE, the recommended range of Connection Interval in + - Power Save (BLE Only) - 100 ms to 1.28 s +- In BLE, during Connection, the configuration of Scan Interval and Scan Window with the same value is not recommended. The suggested ratio of Scan Window to Scan Interval is 3:4 +- In BLE, if a device is acting as Central, the scan window (in set\_scan\_params and create\_connection commands) must be less than the existing Connection Interval. The suggested ratio of Scan Window to Connection Interval is 2:3 +- In BLE mode, if scanning and advertising are in progress on the SiWx91x module and it subsequently gets connected and moves to the central role, scanning stops else if it moves to the peripheral role, advertising stops. To further establish a connection to another peripheral device or to a central device, the application should give a command for starting advertising and scanning again + +### **Multi-protocol** + +- For concurrent Wi-Fi + BLE, and while a Wi-Fi connection is active, we recommend setting the ratio of the BLE scan window to BLE scan interval to 1:3 or 1:4 +- Wi-Fi + BLE Advertising + - All standard advertising intervals are supported. As Wi-Fi throughput is increased, a slight difference in on-air advertisements compared to configured intervals may be observed + - BLE advertising is skipped if the advertising interval collides with Wi-Fi activity +- Wi-Fi + BLE scanning + - All standard scan intervals are supported. For better scan results, we recommend setting the ratio of the BLE scan window to BLE scan interval to 1:3 or 1:4 + - BLE scanning will be stopped for intervals that collide with Wi-Fi activity +- Wi-Fi + BLE Central/Peripheral Connections + - All standard connection intervals are supported + - For a stable connection, use optimal connection intervals and max supervision timeout in the presence of Wi-Fi activity +- Wi-Fi + BLE Central/Peripheral Data Transfer + - To achieve higher throughput for both Wi-Fi and BLE, use medium connection intervals, such as 45 to 80 ms with maximum supervision timeout + - Ensure Wi-Fi activity consumes lower intervals + +## **Known Issues of WiSeConnect3\_SDK\_3.3.4 Release** + +### **System** + +- None + +### **SDK** + +- Observed Wi-Fi connection is successful even after deleting the stored network credentials using sl\_net\_delete\_credential and responding with SL\_NET\_INVALID\_CREDENTIAL\_TYPE for sl\_net\_get\_credential. +- Enhanced sl\_wifi\_get\_firmware\_version() API to provide more details (ROM ID, chip ID, security version, etc) which is not backward compatible with firmware older than 1711.2.10.1.0.0.4. Firmware binary notation does not include security version number +- Matter extension based applications are experiencing compatibility issues with WiseConnect SDK 3.2.0. It is recommended to use WiseConnect SDK 3.1.1 for matter-related applications. This will be addressed in up coming release(s) +- Asynchronous Azure MQTT is not supported, this will be addressed in up coming release(s) +- mDNS with IPV6 is not supported +- Power Save with TCP/IP is not supported for UART interface +- Recommended to configure VAP\_ID properly for Si91x STA and AP using sl\_si91x\_setsockopt\_async(), in case of data transfer +- Recommended to use valid length(<= 202 bytes) for topic to be published in the "Embedded MQTT" demo, else it leads to return wrong error code(0x21) +- Observed AWS\_DEVICE SHADOW LOGGING STATS is not working with Power Save enable +- Bus thread stack may need to increase if local variables are used in user callback to avoid stack overflow +- Low Power examples usage and documentation still under scope of improvement. +- In WPA3 transition security mode, observed sl\_wifi\_get\_wireless\_info() API is giving wrong security type and PSK in both client and AP mode +- Observed sl\_wifi\_get\_operational\_statistics() API is giving wrong opermode and wrong beacon details in AP mode +- Observed MQTT Rx is not able to resume after rejoin in wifi\_station\_ble\_provisioning\_aws demo +- In Power save, user needs to increase application stack size for the Wi-Fi - AWS Device Shadow demo +- Observed DUT unable to wake up from Wi-Fi powersave deep sleep in case of without RAM retention over NCP UART +- Observed issue with the firmware update over the TCP in dense environment +- Observed socket close is not working as expected for TLS socket when socket connect, send data and socket close are performing in a continuous loop +- firmware\_flashing\_from\_host\_uart\_xmodem example fails to communicate over UART +- Observed UDP sendto API failure in wifi\_concurrent\_http\_server\_provisioning\_ncp application +- Observed connection issue with 3rd party AP In concurrent mode using webpage +- Documentation not added for customized socket options +- Observed data not received simultaneously when two sockets call recv() from two different RTOS tasks. +- WMM-PS/UAPSD is not supported + +### **Wi-Fi/Network Stack** + +**Wi-Fi STA** + +- STA connection with the WPA3 using the Hunting and Pecking algorithm takes approximately 3-4 seconds. +- Connection failures have been observed with certain APs in environments with high channel congestion (~50-60% occupancy in an open lab). +- Region selection based on country IE in the beacon is not supported for ICs. +- Intermittent beacon reception from Access Point (beacon misses) occurs when channel congestion exceeds 85%. +- Uplink MU-MIMO is not supported +- When scanning with low power mode enabled, a sensitivity degradation of 3-6dB is observed, which may prevent APs at longer ranges from appearing in the scan results. +- For ICs, the region codes DEFAULT\_REGION and IGNORE\_REGION are not supported +- For modules, the region codes DEFAULT\_REGION and IGNORE\_REGION are not supported in PER mode. +- Observed ~2% increase in listen current and ~1% increase in standby associated current. +- Tx max powers for EVM limited data rates (like MCS7, MCS6, 54M, etc) will be reduced by 0.5dB. + +**Access Point (AP) Mode** + +- Fixed rate configuration in AP mode using sl\_wifi\_set\_transmit\_rate API is not being set as expected + +**WPA2 Enterprise security (STA)** + +- Observed issue with configuring certificate key and programming 4096 bit key and SHA384/SHA512 certificates +- Observing DUT is throwing 0x1001c when configuring .data.certificate\_key as "123456789" + +**Wi-Fi Concurrency ( AP + STA in same channel)** + +- Observed 3rd party STA association fail with 917 AP while 917 STA mode is connecting/reconnecting to configured 3rd party AP. Reconnect 3rd party STA to 917 AP in such scenarios +- In concurrent mode, if IP is configured for AP mode ahead of STA mode then IPv6 configuration may fail for STA mode +- In concurrent mode, data transfer using the Link-local address will always use the first IP interface created by the application. +- In concurrent mode, 917 AP cannot process de-authentication frames sent by third-party STA if 917 STA is connected to WPA2+WPA3 enabled AP. + +**OFDMA (UL/DL)** + +- Less throughput observed in DL-OFDMA with some APs that enabled Low density parity check coding + +**MU-MIMO (DL)** + +- For CoEx Scenario Wi-Fi + BLE, BLE Data transfer, MU retries (~50-60%) observed while running DL MU-MIMO test +- Observed Performance, Interop issues with MU MIMO with certain APs +- Less throughput was observed in MU-MIMO with some APs that enabled Low density parity check coding + +**MU-MIMO (UL)** + +- UL MU-MIMO is not supported + +**TWT** + +- When sl\_wifi\_enable\_target\_wake\_time() API is used, occasional MQTT disconnections may be observed if TWT is configured with longer TWT intervals (>30secs) with embedded MQTT + TWT.  As an alternative, it's highly recommended to use sl\_wifi\_target\_wake\_time\_auto\_selection() API, where these dependencies are internally handled. + +**Wi-Fi STA Rejoin** + +- observed Scanning (probe request) in all channels instead of the channels configured in selective channel(channel\_bitmap\_2g4) during rejoin process + +**IPv4/IPv6** + +- IP change notification is not indicated to the application +- In concurrent mode with dual IP, if the STA starts after AP is up, the STA IP configuration may fail for DHCP stateless mode +- concurrent\_firmware\_update\_from\_host\_uart example have stability issues during rejoin or disconnection process +- In concurrent mode, data transfer using the Link-local address will always use the first IP interface created by the application + +**BSD Socket API** + +- Every server socket created consumes a socket (maximum of 10 sockets supported) and every subsequent connection to server socket consumes an additional socket (from the same pool of 10 sockets), which limits the number of server connections supported +- Observing issues with TCP retries when power save mode is enabled, especially when the module is in idle state +- TCP maximum retry value is valid upto 31 + +**SSL Client/Server** + +- Sometimes during SSL Handshake, ECC curve parameters generated are wrong, resulting in connection failure with BBD2 error. However, this recovers in the next attempt +- Secure SSL renegotiation not supported in Embedded Networking Stack + +**HTTP Client/ HTTPS Client** + +- Observed occasional HTTPS continuous download failures when power save is enabled. Recommended to disable it before performing HTTPS continuous downloads + +**SNTP** + +- Unable to get SNTP async events when CoEx mode and power save are enabled  + +**Throughputs & Performance** + +- Observed 20% less Wi-Fi throughput with SDK 3.x compare to target throughput (depends on host and host interface), SDK refinements are in progress + +**Secure Over the Air (OTA) Upgrade** + +- Observed firmware upgrade failures after multiple iterations +- Observed OTA failures with power save enabled, So recommended to disable power save during OTA + +**Wi-Fi IOT Cloud integration** + +- **AWS IOT Core** + - Observed AWS MQTT keepalive transmission is not happening at expected intervals with power save enabled. + - Observing LAST\_WILL\_MESSAGE is random at every MQTT connection rather than the configured Message/Length +- **AZURE IOT Core** + - Observed DUT after sending the data, its not sending the MQTT keep alive packet due to this Azure HUB closing the connection when power save is enabled + +**Wi-Fi Interoperability (IOP)** + +- Observed disconnections with Amplifi (AFI-INS-R) AP with Powersave enable +- TWT session is failing due to disconnections observed in DUT if rx\_latency  is set to 55 seconds and receive data is also set to 55 seconds on MI Xiaomi RA72 and Tplink AX53 AP's +- Observed less throughput(~1Mb) while running TCP RX with Max\_PSP powersave with DLink 810 AP +- Observed interop issue (random disconnections) with few APs (EERO 6+, EERO PRO 6E, Cisco Catalyst 9120AXID) +- Disconnections observed with Netgear RAX120 AP in WPA3 security + +### **BLE** + +**GAP** + +- SPI interrupt miss issue was observed that prevents the host from receiving packets delivered by the TA, when there is continuous BLE TX/RX data transfer using the ble\_multiconnection\_gatt\_test application +- The DUT is unable to move to active state after BLE link loss using SiWN917Y100LGNB4 OPN + +**AE**  + +- Observed DUT hang issue while running TX notifications in peripheral role. + +**Performance** + +- The DUT hangs when the SRRC region is set in the ICs. However, this issue does not occur with the SiWN917Y module. + +### **Multi-protocol** + +- For CoEx Scenario Wi-Fi + BLE, BLE Data transfer, MU retries (~50-60%) observed while running DL MU-MIMO test +- Observed Wi-Fi + BLE intermittent connection failures, disconnections, and data transfer stalls in the long run when power save is enabled +- While executing Wi-Fi Commissioning using the wifi\_station\_ble\_provisioning example, BLE is disconnecting is observed with few boards +- Observed "DUT is not disconnecting to the AP when initiating disconnection from EFR connect app screen using wifi\_station\_ble\_provisioning\_aws example +- Observed DUT failed to load certificate with error "0x10026" (SL\_STATUS\_SI91X\_WRONG\_PARAMETERS) while running wifi\_https\_ble\_dual\_role\_v6 application +- Observed BLE bonding failure during continuous HTTPS download +- Observed BLE and WLAN connection failure with SMP, when WLAN connect and HTTPS GET called in a loop +- Observed BLE disconnection during wifi commissioning with few android mobiles +- Observed data stall on the remote machine during TCP/UDP transmission with power save enabled in  wifi\_throughput\_ble\_dual\_role\_ncp example +- Observed data stalls on remote server during Continuous TCP TX in wifi\_throughput\_ble\_dual\_role\_ncp example. +- For wifi\_ble\_powersave\_coex application, with 352K memory, observed 0xff2c - Memory limit exceeded in the given operating mode error. +- Observed throughput is not displaying for every interval of 'TEST\_TIMEOUT' when CONTINUOUS\_THROUGHPUT enabled for wifi\_station\_ble\_throughput\_app example. + +### **Simplicity Studio and Commander (For EFR Host)** + +- All projects in the package are compatible with **GNU ARM V12.2.1** toolchain +- Universal Configurator (UC) for EFR32xG Products in NCP Mode is not supported + +## **Limitations and Unsupported Features** + +### **System** + +- None + +### **SDK** + +- Baremetal mode is not supported +- WiSeConnect3\_SDK\_3.1.3 and later versions are not compatible with firmware versions prior to 1711.2.10.1.2.0.4, due to enhancements in max transmit power configuration during Wi-Fi join/connection, need to be cautious while doing OTA firmware upgrade +- Lite Wireless firmware image is not supported for NCP mode. +- Zephyr is not supported + +### **Wi-Fi/Network Stack** + +- TLS 1.3 Server is not supported +- 40 MHz bandwidth for 2.4 GHz band is not supported. +- A maximum of 3 SSL connections are supported in Wi-Fi alone and CoEx modes. No.of  SSL Sockets in Wi-Fi + BLE based on RAM memory configuration selected.  +- In SSL ECC Curve ID supported is 23. SSL handshake with 3rd party clients depends on the SSL ECC Curve ID. +- The number of Non-Transmitting BSSIDs processed is limited by the beacon length that can be processed by the stack (which is 1024 bytes). Beacons greater than 1024 Bytes in length will not be processed. +- UL-MU-MIMO is not supported. +- WPA3 AP supports only H2E algorithm. +- PMKSA caching is not supported in WPA3 AP mode. +- Maximum embedded MQTT Publish payload is 1 kByte. +- Timeout value for socket select and socket receive calls of less than 1 second is not currently supported. +- SA query procedure not supported in 11W AP mode. +- WPA3 AP transition mode is not supported. +- AP standalone mode does not support Tx aggregation. Rx aggregation is supported with limited number of BA sessions. +- In concurrent AP mode, aggregation (Tx/Rx) is not supported. +- Embedded HTTP Server is not supported. +- mDNS with IPV6 is not supported. +- Low power scan supports 1 Mbps packets reception only. +- Auto PAC Provisioning in EAP-FAST with TLSv1.2 is not supported. +- bTWT , Intra PPDU Power save, Spatial Re-Use, BSS coloring features not supported +- HTTPS server is not supported. +- In Wi-Fi Transceiver mode, MAC level encryption/decryption is not supported.  + +### **BLE** + +- For BLE, if the connection is established with a small connection interval (less than 15 ms), simultaneous roles (i.e., Central + Scanning and Peripheral + Advertising) are not supported +- BLE maximum two concurrent connections are supported, which can be either a connection to two peripheral devices, to one central and one peripheral device or two central devices +- BLE Slave latency value is valid up to 32 only +- BLE TX/RX throughput is less when tested with EFM as compared to EFR +- Maximum supported AE data length is 200 bytes +- Supports only two ADV\_EXT sets +- Supports only two BLE connections (1 Central and 1 Peripheral) with AE +- Advertising Extension feature is not supported in Coexistence +- Isochronous channels feature is not supported +- Connection subrating feature is not supported +- LE power controller feature is not supported +- EATT feature is not supported +- Periodic Advertising with response(PAwR) feature is not supported +- BLE Audio is not supported +- The feature of dynamically changing the TX power when extended advertising is active is not supported +- EFR Connect mobile application doesn't have support to differentiate the BLE configurators based on the Bluetooth Device address +- The maximum BLE power has been reduced by 2dB compared to the Datasheet Number, which will be addressed in the upcoming 3.3.1 patch release +- ICs do not support DEFAULT\_REGION and IGNORE\_REGION region codes. +- Modules do not support DEFAULT\_REGION and IGNORE\_REGION region codes in PER mode. + +### **Multi-protocol** + +- Wi-Fi AP + BLE currently not supported. + +> **Note:**  +> +> The following BLE Synchronous API's will be deprecated soon and the equivalent Asynchronous API's will be used instead in all BLE applications : +> +> |**S.No**|**BLE Synchronous API's** |**BLE Asynchronous API's** | +> | :- | :- | :- | +> |1|rsi\_ble\_get\_profiles|rsi\_ble\_get\_profiles\_async| +> |2|rsi\_ble\_get\_profile|rsi\_ble\_get\_profile\_async| +> |3|rsi\_ble\_get\_char\_services|rsi\_ble\_get\_char\_services\_async| +> |4|rsi\_ble\_get\_inc\_services|rsi\_ble\_get\_inc\_services\_async| +> |5|rsi\_ble\_get\_char\_value\_by\_uuid|rsi\_ble\_get\_char\_value\_by\_uuid\_async| +> |6|rsi\_ble\_get\_att\_descriptors|rsi\_ble\_get\_att\_descriptors\_async| +> |7|rsi\_ble\_get\_att\_value|rsi\_ble\_get\_att\_value\_async| +> |8|rsi\_ble\_get\_multiple\_att\_values|rsi\_ble\_get\_multiple\_att\_values\_async| +> |9|rsi\_ble\_get\_long\_att\_value|rsi\_ble\_get\_long\_att\_value\_async| +> |10|rsi\_ble\_set\_att\_value|rsi\_ble\_set\_att\_value\_async| +> |11|rsi\_ble\_set\_long\_att\_value|NA| +> |12|rsi\_ble\_prepare\_write|rsi\_ble\_prepare\_write\_async| +> |13|rsi\_ble\_execute\_write|rsi\_ble\_execute\_write\_async| +> |14|rsi\_ble\_indicate\_value\_sync|rsi\_ble\_indicate\_value| + +
+ # **WiSeConnect3\_SDK\_3.3.3 NCP Release Notes**    ## **Release Details** @@ -92,7 +548,7 @@ Note: - **Fixed Issues** - None - **Documentation** - - **None** + - None ### **SDK** diff --git a/docs/release-notes/index_soc.md b/docs/release-notes/index_soc.md index 34f8212e3..12cf89e59 100644 --- a/docs/release-notes/index_soc.md +++ b/docs/release-notes/index_soc.md @@ -1,3 +1,653 @@ +# **WiSeConnect3\_SDK\_3.3.4 SoC Release Notes** + +## **Release Details** + +|**Item**|**Details**| +| :- | :- | +|Release date|18th October 2024| +|SDK Version|3\.3.4| +|Firmware Version|

Standard: 1711.2.12.3.3.0.3

Lite Wireless: 1711.2.12.3.3.2.3

| +|GSDK/SiSDK Version|SiSDK 2024.6.2 | +|Studio Version|5\.9.3.0| +|Release Package Name|WiSeConnect3\_SDK\_3.3.4| +|Supported RTOS|FreeRTOS| +|Operating Modes Supported|Wi-Fi STA, Wi-Fi AP, Wi-Fi STA+BLE, Wi-Fi STA+AP| + +- SiWx917 release consists of two components: + - SiWx91x Connectivity Firmware: + - Standard Wireless Firmware - SiWx917 Firmware Binary available as SiWG917-B.2.12.3.3.0.3.rps + - Lite Wireless Firmware - SiWx917 Firmware Binary is available as SiWG917-B.2.12.3.3.2.3.rps, this image is with reduced features for parts with SiWG917M110LGTBA OPN.  + - Wiseconnect3 Library - Wiseconnect3 SDK library runs on internal Cortex M4 + +**Note:** + +- Mandatory to upgrade the earlier version of boards (Si917-6031A Pro kit or BRD4338A boards) or 917 Silicon ICs with instructions as outlined in this document "SiWG917–TA\_Flash\_Memory\_Map\_ChangeGuide\_v1.3.pdf" for more details.   +- The release packages will have bug-fixes, enhancements, and new features in both 'SDK' and 'Firmware'. Customer shall update and use 'SDK' and 'Firmware' of same release package. SDK and FW combinations that are not released together are not supported. +- It is recommended to update TA image first followed by M4 image and ensure application compatibility with firmware before OTA +- To use the Dev kit Demo, users need to have Simplicity Connect version 2.9.3 or higher. + +## **Supported Hardware** + +|**Hardware**|**OPN (Ordering Part Number)**| +| :- | :- | +|IC OPN|

QFN OPNs: SiWG917M111MGTBA, SiWG917M100MGTBA, SIWG917M110LGTBA(Lite Wireless Firmware), SiWG917M111XGTBA, SiWG917M121XGTBA, SiWG917M141XGTBA

Module OPNs: SIWG917Y111MGNBA , SIWG917Y110LGNBA, SIWG917Y111XGNBA, SIWG917Y121MGNBA, SIWG917Y111MGABA, SIWG917Y110LGABA, SIWG917Y111XGABA, SIWG917Y121MGABA

| +|Development Kits|

Pro Kit: SiWx917-PK6031A, Si917-PK6031A. 

(Pro Kit includes Mother board "Si-MB4002A" + Radio board)

Radio boards: SiWx917-RB4338A, SiWx91x-RB4342A, SiWx917-DK2605A

Module boards: SiW917Y-RB4343A

| + +## **Supported Features**  + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
SectionSub-SectionFeature

Lite Wireless Firmware

(4MB flash OPN
OPN No: SiWG917M110LGTBA)

Standard Wireless Firmware (For other OPNs)
SystemOperating modesWi-Fi STA (802.11ax, 802.11n)SupportedSupported
Wi-Fi 802.11n APNot SupportedSupported
Wi-Fi STA (802.11ax, 802.11n) + 802.11n APNot SupportedSupported
Wi-Fi STA (802.11ax, 802.11n) + BLESupportedSupported
Security Secure Boot, Secure Key storage and HW device identity with PUF, Secure Zone, Secure XIP (Execution in place) from flash, Secure Attestation, Anti Rollback, Debug Lock, Flash ProtectionSupportedSupported
Secure firmware upgrade options

- Firmware loading support by Commander Tool through Jlink Debugger. Jlink connected to Serial Wire Debug (SWD) 

- Firmware loading via ISP using UART (Commander or Serial terminal), SPI Interface

- Secure Over the Air (OTA) Upgrade

- Firmware update via Bootloader

SupportedSupported
Crypto Support

- Crypto API's for Hardware Accelerators: Advanced Encryption Standard (AES) 128/256/192, Secure Hash Algorithm (SHA) 256/384/512, Hash Message Authentication Code (HMAC), Random Number Generator (RNG), SHA3, AES-Galois Counter Mode (GCM)/ Cipher based Message Authentication Code (CMAC), ChaCha-poly, True Random Number Generator (TRNG)

- Software Accelerators: RSA, ECC

- PSA Crypto APIs support for all crypto operations.

- Wrapping Secret keys (Symmetric crypto). 

- Added ECDSA Sign and Verify APIs

SupportedSupported
System Power Save

- Deep Sleep with RAM retention and without RAM retention. 

- Wireless Power Save: Connected Sleep (Wi-Fi Standby Associated), BLE Advertising with powersave, BLE Scan with powersave,  BLE connection with powersave. Only Max PSP power save mode is supported in BLE. 

SupportedSupported
Wi-FiWi-Fi ProtocolsIEEE 802.11 b/g/n/ax (2.4GHz)SupportedSupported
Access Point (AP) Mode

- 4 Client Support, Hidden SSID Mode, Auto Channel Selection, Scan in AP mode (Alpha)

- Wi-Fi Security 

- WPA2 Personal, WPA3 Personal (H2E method only) (Alpha), WPA Mixed mode (WPA/WPA2) 

Not SupportedSupported
Wi-Fi ScanSelective Scan, Active/Passive ScanSupportedSupported
Wi-Fi STA (Security Modes)Open Mode, WPA2 Personal, WPA2 Enhancements, WPA3 Personal, Mixed Mode (WPA/WPA2), WPA3 Personal Transition Mode (WPA2/WPA3)SupportedSupported
WPA2 Enterprise security (STA)Method: PEAP/TTLS/TLS 1.0/TLS 1.2/FAST/LEAPNot SupportedSupported
Wi-Fi STA RejoinSupportedSupported
Wi-Fi STA Roaming BG Scan, OKC (Opportunistic Key caching), PMK (Pairwise Master Key) caching, Pre-AuthenticationSupportedSupported
Wi-Fi Protocol Power Save Deep sleep (unconnected state), Max PSP, Enhanced Max PSP, Fast PSP, TWTSupportedSupported
QoSWMM-QoSSupportedSupported
Wi-Fi 6 FeatureMU-MIMO (DL), OFDMA (UL/DL), iTWT, TWT I-Frame & TWT Enhancements (Automatic TWT Configuration), BSS coloring, MBSSIDSupportedSupported
Wi-Fi Concurrency AP+STA (Same channel)Not SupportedSupported
Wi-Fi Band/Channels2\.4GHz CH1-11, 2.4GHz CH1-13, 2.4GHz CH1-14SupportedSupported
Known Security Vulnerabilities HandledWPA2 KRACK Attacks, Fragment and Forge VulnerabilitySupportedSupported
Network stackCore Networking Features

- IPv4/IPv6/UDP/TCP/ARP/ICMP/ICMPv6

- SSL client versions TLSV1.0, TLSV1.2, TLSV1.3 

- SSL server versions TLSV1.0 and TLSV1.2

- DHCPv4/DHCPv6 Client

- TCP/IP Bypass (LWIP as Hosted stack for reference)

SupportedSupported
- DHCPv4 Server, DHCPv6 ServerNot SupportedSupported
Advanced Network FeaturesHTTP Client/HTTPS Client/DNS Client, Embedded MQTT/MQTT on host (AWS and AZURE) SupportedSupported
SNTP Client, IGMPNot SupportedSupported
Wi-Fi IoT Cloud Integration

- AWS IOT Core

- Azure IoT

SupportedSupported
BSD and IoT sockets application programming interface(API)SupportedSupported
BLE Legacy features

- GAP(Advertising, Scanning, initiation, Connection and Bonding)

- Generic Attribute Protocol(GATT)

- Attribute protocol(ATT)

- Security

- LL Privacy 1.2

- Accept list

- Directed Advertising

- LE PHY(1Mbps, 2Mbps) & Coded PHY(125kbps, 500kbps)

- Simultaneous scanning on 1Mbps and Coded PHY

- LE dual role topology

- LE data packet length extensions(DLE)

- Asymmetric PHYs

- LE channel selection algorithm 2 (CSA#2)

- LE Secure connections

SupportedSupported
Advertising Extensions 

- Extended Advertising

- Periodic Advertising

- Periodic Advertising scanning

- Extended Advertising scanning

- Periodic Advertising list

- LE periodic advertising synchronization

Not Supported Supported
+ +### **MCU** + +- **Memory** + - Common Flash: Single shared Flash for both Cortex-M4 and NWP (Wireless Processor) + - Common Flash + External PSRAM + - Stacked PSRAM + External Common Flash +- **Power States** + - Active: PS4, PS3, PS2, and PS1  + - Standby: PS4, PS3, and PS2 + - Sleep: PS4, PS3 and PS2 + - Deep Sleep (Shutdown): PS0 +- **Peripherals, Services and Hardware Drivers**  + +|**HP Peripherals**|**List**|**Notes**| +| :- | :- | :- | +| |

- ADC

- Analog Comparator

- Config Timer (CT)

- CRC

- DAC

- eFuse

- EGPIO

- GPDMA1

- GSPI

- I2C

- I2S

- MCPWM

- PSRAM

- RNG1

- SDIO Secondary

- SSI (Primary & Secondary)

- Temperature Sensor

- UART

- uDMA

- USART

|| +| |

- BoD1

- CTS (Touch Sensor)1

- OPAMP1

- QSPI1

- QEI1

|Limited Support| +|**ULP Peripherals**||| +| |

- ULP\_ADC

- ULP\_DAC

- ULP\_GPIO

- ULP\_I2C

- ULP\_I2S

- ULP\_TIMER

- ULP\_UDMA

- ULP\_UART

- ULP\_SSI\_PRIMARY

|| +|**UULP Peripherals**||| +| |

- RTC (Calendar)

- SYSRTC

- WDT

|| +|**Services**| || +| |Sleep Timer|| +| |IOSTREAM|| +| |NVM3|| +| |LittleFS (for Dual Flash)|Limited Support| +| |Power Manager|| +| |Sensor Hub|Limited Support| +| |Pin Tool|Limited Support| +|**Hardware Drivers**| || +| |LED, Button, MEMLCD, Joystick, Sensors (RHT, VEML, ICM)|| + +|The peripherals marked with superscript1 are available through RSI APIs.  Support for SL APIs for user facing peripherals will be available in future releases.| +| :- | + +|The flash write feature has been enhanced to support the NWP area, providing a 20k allocation within the NWP flash memory for storing user data. Moreover, a Read API has been introduced to retrieve data from the NWP flash region.| +| :- | + +### **Developer Environment** + +- Simplicity Studio IDE (SV5.9.3.0 version) and Debugger Integration. Refer to the latest version of the SoC "Getting-Started-with-SiWx917" guide for more details.  +- Recommended to install and use Silicon labs Simplicity SDK (Previously known as Gecko SDK), Git hub based version 2024.6.2. +- Simplicity Commander to supports Flash loading, provision of MBR programming, security key management, and calibration support for crystal and gain offsets. refer "siwx917-soc-manufacturing-utility-user-guide" for more details.  +- Advanced Energy Monitoring (AEM) to measure ultra-low power capability on Development boards (Pro Kit). +- PinTool for MCU pin configurations + +### **BLE**  + +- GAP(Advertising, Scanning, initiation, Connection and Bonding) +- Generic Attribute Protocol(GATT) +- Attribute protocol(ATT) +- Security +- LL Privacy 1.2 +- Accept list +- Directed Advertising +- Extended Advertising +- Periodic Advertising +- Periodic Advertising scanning +- Extended Advertising scanning +- Periodic Advertising list +- LE periodic advertising synchronization +- LE PHY(1Mbps, 2Mbps) & Coded PHY(125kbps, 500kbps) +- Simultaneous scanning on 1Mbps and Coded PHY +- LE dual role topology +- LE data packet length extensions(DLE) +- Asymmetric PHYs +- LE channel selection algorithm 2 (CSA#2) +- LE Secure connections +- Bluetooth 5.4 Qualified + +### **SDK** + +- Simplified and Unified DX for Wi-Fi API and Platform APIs +- Simplifies application development and presents clean and standardized APIs +- UC (Universal Configurator) enables componentization, simplifying configuration of peripherals and examples +- BSD and ARM IoT-compliant socket API +- Available through Simplicity Studio and GitHub + +### **Multi-protocol** + +- Wi-Fi STA + BLE + +### **PTA/Coexistence** + +- 3 wire CoEx acting as Wi-Fi with external Bluetooth +- 3 wire CoEx acting as Wi-Fi with external Zigbee/OT + +## **Changes in this release compared to v3.3.3 Release** + +### **System** + +- **Enhancements / New features** + - None +- **Fixed Issues** + - None +- **Documentation** + - None + +### **MCU** + +- **Enhancements / New features** + - None +- **Fixed Issues** + - Resolved the issue with Copy contents when creating projects in Simplicity Studio +- **Documentation** + - None + +### **SDK** + +- **Enhancements / New features** + - None +- **Fixed Issues** + - None +- **Documentation** + - None + +### **Wi-Fi/Network Stack** + +- **Enhancements / New features** + - None +- **Fixed Issues** + - None +- **Documentation** + - None + +### **BLE** + +- **Enhancements / New features** + - None  +- **Fixed Issues** + - None +- **Documentation** + - None + +### **Multi-protocol** + +- **Enhancements / New features** + - None +- **Fixed Issues** + - None +- **Documentation** + - None + +## **Recommendations** + +### **System** + +- The current revision of SiWx917 has: + - RAM memory of 672k bytes which can be shared between TA and M4 processors in SoC mode.  + - The below configurations are applicable in SoC mode and can be configured based on the application requirement. EXT\_FEAT\_352K\_M4SS\_320K is the default configuration, based on requirement EXT\_FEAT\_480K\_M4SS\_192K configuration is selected for SoC mode multi-protocol examples. + - EXT\_FEAT\_480K\_M4SS\_192K - This mode configures TA with 480k and M4 with 192K bytes of memory + - EXT\_FEAT\_416K\_M4SS\_256K - This mode configures TA with 416k and M4 with 256K bytes of memory + - EXT\_FEAT\_352K\_M4SS\_320K - This mode configures TA with 352k and M4 with 320K bytes of memory + - SoC mode should not use 672k\_M4SS\_0K memory configuration. +- Set the recommended Power Save Profile (PSP) type to Enhanced Max PSP. +- There are 2 Versions of Pro-Kits/Radio boards. Si917-6031A based on Si917-4338A (Rev **A01 - A11**) and SiWx917-6031A based on SiWx917-4338A (Rev A12-A14). To get optimal power numbers, enable macro "SL\_SI91X\_ENABLE\_LOWPWR\_RET\_LDO" pre-processor define for ICs or while using SiWx917-6031A Pro-kit, SiWx917-4338A version of boards. This macro should be disabled for earlier variants of the board (Si917-6031A, Si917-4338A). +- With RAM configuration (EXT\_FEAT\_352K\_M4SS\_320K), only 352K memory is available to TA  which limits the features supported, Recommended to enable EXT\_FEAT\_416K\_M4SS\_256K in Wi-Fi + BLE Multi protocol mode to enable more Network features. +- For EXT\_FEAT\_416K\_M4SS\_256K  and EXT\_FEAT\_480K\_M4SS\_192K memory configurations, it is recommended to retain both TA and M4 RAMs in power save. + +### **Wi-Fi/Network Stack** + +- It is recommended to enable SL\_SI91X\_EXT\_TCP\_IP\_WAIT\_FOR\_SOCKET\_CLOSE BIT(16) of the 'Extended TCP IP Feature' bit map in the opermode command for all Wi-Fi Socket operations from the host to ensure graceful handling during asynchronous closures from the peer. +- For high throughputs,  it is recommended to enable BIT(2) - SL\_SI91X\_FEAT\_AGGREGATION  of feature\_bit\_map in opermode.  +- Users can enable SL\_SI91X\_EXT\_TCP\_IP\_SSL\_16K\_RECORD in 'Extended TCP IP Feature' bit map in opermode for (HTTPS server) supporting 16k record. +- **TWT** + - Recommendation is to use sl\_wifi\_target\_wake\_time\_auto\_selection() API for all TWT applications.  + - It is recommended to issue iTWT setup command once IP assignment, TCP connection, application specific socket connections are done. + - When using sl\_wifi\_enable\_target\_wake\_time API, increase TCP / ARP Timeouts at the remote side depending upon the configured TWT interval configured. It's highly recommended to use sl\_wifi\_target\_wake\_time\_auto\_selection() as an alternative. + - In case of TWT in CoEx mode, when using sl\_wifi\_enable\_target\_wake\_time API, use TWT wake duration <= 16 ms and TWT wake interval >= 1 sec. If wake duration > 16 ms or TWT wake interval < 1sec, there might be performance issues. + - For iTWT GTK interval in AP should be configured to max possible value or zero. If GTK interval is not configurable on AP side, recommended TWT interval (in case of sl\_wifi\_enable\_target\_wake\_time API) or RX Latency (in case of sl\_wifi\_target\_wake\_time\_auto\_selection API) is less than 4sec. + - When sl\_wifi\_enable\_target\_wake\_time API is used, configuring TWT Wake interval beyond 1 min might lead to disconnections from the AP. Recommended to use TWT wake interval of less than or equal to 1 min. + - When using sl\_wifi\_enable\_target\_wake\_time API, it is recommended to set missed\_beacon\_count of sl\_wifi\_set\_advanced\_client\_configuration API greater than 2 times of the configured TWT Interval. + - DUT keepalive should be configured aligned with AP keepalive in TWT modes. +- Disable power save for high throughput applications or use FAST PSP power save mode as per application requirement. +- The application needs to ensure that it sets RTC with the correct timestamp before establishing the SSL/EAP connection. +- The minimum timeout value should not be less than 1 second for socket select and socket receive calls.  +- Please refer Keep alive intervals supported by MQTT broker and configure keep alive interval values accordingly. +- The minimum keep alive interval value recommended for embedded MQTT is 10 Seconds.  +- Disable power save and suspend any active TWT sessions before triggering HTTP OTAF. +- Randomize the client port if using rapid connect/disconnect of the MQTT session on the same client port with the power save. +- Recommended to configure VAP\_ID properly for Si91x STA and AP using sl\_si91x\_setsockopt\_async(), in case of data transfer. +- Recommended to use valid length(<= 202 bytes) for topic to be published while using Embedded MQTT, else it leads to return wrong error code(0x21). +- In concurrent mode with dual IP, it is advised to bring up STA first (IP configuration) and AP later. +- It is recommended to configure Tx ,Rx , Global buffer pool ratio in the buffer config command based for all Wi-Fi Socket operations from the host +- It is recommended to use "TCP exponential backoff" configuration for congested channels. +- It is recommended is to disable broadcast filter during TCP connection to avoid ARP resolution issues +- To avoid IOP issues, it is recommended to disable power save before Wi-Fi connection. +- It is recommended to set region\_code as `IGNORE_REGION` in boot configurations for SIWG917Y module boards except for PER mode. + +### **BLE** + +- In BLE, the recommended range of Connection Interval in + - Power Save (BLE Only) - 100 ms to 1.28 s. +- In BLE, during Connection, the configuration of Scan Interval and Scan Window with the same value is not recommended. The suggested ratio of Scan Window to Scan Interval is 3:4. +- In BLE, if a device is acting as Central, the scan window (in set\_scan\_params and create\_connection commands) must be less than the existing Connection Interval. The suggested ratio of Scan Window to Connection Interval is 2:3. +- In BLE mode, if scanning and advertising are in progress on the SiWx91x module and it subsequently gets connected and moves to the central role, scanning stops else if it moves to the peripheral role, advertising stops. To further establish a connection to another peripheral device or to a central device, the application should give a command for starting advertising and scanning again. + +### **Multi-protocol** + +- For concurrent Wi-Fi + BLE, and while a Wi-Fi connection is active, we recommend setting the ratio of the BLE scan window to BLE scan interval to 1:3 or 1:4. +- Wi-Fi + BLE Advertising + - All standard advertising intervals are supported. As Wi-Fi throughput is increased, a slight difference in on-air advertisements compared to configured intervals may be observed. + - BLE advertising is skipped if the advertising interval collides with Wi-Fi activity. +- Wi-Fi + BLE scanning + - All standard scan intervals are supported. For better scan results, we recommend setting the ratio of the BLE scan window to BLE scan interval to 1:3 or 1:4. + - BLE scanning will be stopped for intervals that collide with Wi-Fi activity. +- Wi-Fi + BLE Central/Peripheral Connections + - All standard connection intervals are supported. + - For a stable connection, use optimal connection intervals and max supervision timeout in the presence of Wi-Fi activity. +- Wi-Fi + BLE Central/Peripheral Data Transfer + - To achieve higher throughput for both Wi-Fi and BLE, use medium connection intervals, such as 45 to 80 ms with maximum supervision timeout. + - Ensure Wi-Fi activity consumes lower intervals. + +### **MCU** + +- The WDT manager is specifically meant for system reset recovery and should not be utilized for any other purpose. When interrupts are disabled, make sure to stop the WDT to avoid unintended resets. Once interrupts are re-enabled, restart the WDT to ensure system reliability +- It is strongly recommended to use `sl_si91x_soc_nvic_reset()` API for system soft reset rather than the `sl_si91x_soc_soft_reset()` function, since this uses the WDT for soft reset, which is specifically intended for system reset recovery +- It is strongly recommended not use switch\_m4\_frequency() for clock scaling. Refer to the migration guide for more details +- For GPIO-based wakeup, ensure the GPIO component is installed in powersave applications +- Use both CTS and RTS for UART flow control +- PSRAM examples are not supposed to be used with Non-PSRAM OPNs +- SYSRTC and wake on wireless wakeup resources are enabled by default when tickeless idle mode is enabled. Avoid installing sleeptimer component in power save applications (where FreeRTOS tickless is enabled by default) +- Minimum idle-time to sleep is configured to 100ms in FreeRTOS\_config.h +- Enable DMA to achieve better throughput numbers +- For I2C Fastplus and High speed modes, use high power instances with core clock frequencies between 80MHz and 180MHz +- Use blocking calls instead of non-blocking calls for I2C leader in ULP\_I2C while receiving data +- In RTOS environment, prefer Signaling mechanisms (Semaphore/Mutex/EventFlag etc.) instead of "Variables/Flags" from user callbacks to detect "\*Transfer Complete\*" for high speed communication peripherals + Refer Software Reference Manual for more details +- Install the 'device\_needs\_ram\_execution' component for OPN-based firmware update examples +- It is strongly recommended to use the FreeRTOS tickless based powersave instead of the sl\_si91x\_m4\_sleep\_wakeup() (legacy) API +- For ACx Modules, it is necessary to initialize the internal 32kHz RC clock specifically for the LF\_FSM domain. GPIO oscillator clock does not propagate to the LF\_FSM. This may lead to timer accuracy issues when using the 32kHz RC clock. +- If the external oscillator connected to UULP\_GPIO\_3 is used as the 32kHz clock source, make the necessary code changes as detailed in the Software Reference Manual +- It is strongly recommended not to use RO clock in MCU +- For BLE, CoEx, and high-accuracy MCU applications it is recommended to use external 32kHz crystal on XTAL\_32KHZ\_P and XTAL\_32KHZ\_N pins. + +## **Known Issues of WiSeConnect3\_SDK\_3.3.4 Release** + +### **MCU** + +**GSPI** + +- First 2 MSB bits of the first byte on MISO are garbled + +**GPIO** + +- By default, sl\_gpio\_set\_configuration() sets the GPIO to HIGH  + +**SSI** + +- In ULP SSI, non-DMA transfer is not working + +**I2C** + +- ULP\_I2C non-blocking receive in low power mode will not function as expected + +**I2S** + +- FIFO threshold configurations are not working + +**Config Timers** + +- PWM mode is not working + +**ADC** + +- ADC static mode sampling rate is supported up to 2.5Msps + +**Analog comparator** + +- opamp2, opamp3 & BOD configurable Inputs do not work + +**Temperature Sensors** + +- BJT Temperature readings are not accurate + +**QSPI** + +- QUAD mode not working + +**Power Manager** + +- BOD and Comparator wakeup sources not working +- PS2 -PS4 transition is not working in SiWG917Y110LGNBA part + +**SensorHub** + +- Power transitions with AWS are not stable in SensorHub +- SPI sensor is not working +- Button interrupt is not working + +### **SDK** + +- Observed Wi-Fi connection is successful even after deleting the stored network credentials using sl\_net\_delete\_credential and responding with SL\_NET\_INVALID\_CREDENTIAL\_TYPE for sl\_net\_get\_credential. +- Enhanced sl\_wifi\_get\_firmware\_version() API to provide more details (ROM ID, chip ID, security version, etc) which is not backward compatible with firmware older than 1711.2.10.1.0.0.4. Firmware binary notation does not include the security version number. +- In PSRAM enabled demos, moving of text, data and stack segments to PSRAM is allowed. BSS and Heap should still be in SRAM. +- Asynchronous Azure MQTT is not supported, this will be addressed in upcoming release(s). +- mDNS with IPV6 is not supported. +- Bus thread stack may need to increase if local variables are used in user callback to avoid stack overflow. +- Low Power examples usage and documentation still under scope of improvement. +- Observed sl\_wifi\_get\_wireless\_info() API is giving wrong security type and PSK for WPA3 Transition supported client mode. +- Observed socket close is not working as expected for TLS socket when socket connect, send data and socket close are performing in a continuous loop. +- Observed data not received simultaneously when two sockets call recv() from two different RTOS tasks. +- WMM-PS/UAPSD is not supported +- firmware\_flashing\_from\_host\_uart\_xmodem example fails to communicate over UART. + +### **Wi-Fi/Network Stack** + +**Wi-Fi STA** + +- STA Connection with the WPA3 Hunting and Pecking algorithm takes about 3-4 seconds. +- Connection failures have been observed with certain APs in environments with high channel congestion (~50-60% occupancy in an open lab). +- Region selection based on country IE in the beacon is not supported in ICs +- Intermittent beacon reception from Access Point (beacon misses) occurs when channel congestion exceeds 85%. +- When scanning with low power mode enabled, a sensitivity degradation of 3-6dB is observed, which may prevent APs at longer ranges from appearing in the scan results. +- Passive scan is failing when DUT is configured in world domain. +- For ICs, the region codes DEFAULT\_REGION and IGNORE\_REGION are not supported +- For modules, the region codes DEFAULT\_REGION and IGNORE\_REGION are not supported in PER mode. +- Observed ~2% increase in listen current and ~1% increase in standby associated current. +- Tx max powers for EVM limited data rates (like MCS7, MCS6, 54M, etc) will be reduced by 0.5dB. + +**Access Point (AP) Mode** + +- Fixed rate configuration in AP mode using sl\_wifi\_set\_transmit\_rate API is not being set as expected.  + +**WPA2 Enterprise security (STA)** + +- Observed connection issue with configuring certificate key and programming 4096 bit key and SHA384/SHA512 certificates. + +**Wi-Fi Concurrency (AP + STA in same channel)** + +- Observed 3rd party STA association fail with 917 AP while 917 STA mode is connecting/reconnecting to configured 3rd party AP. Reconnect 3rd party STA to 917 AP in such scenarios.  +- In concurrent mode, 917 AP cannot process de-authentication frames sent by third-party STA if 917 STA is connected to WPA2+WPA3 enabled AP. + +**OFDMA (UL/DL)** + +- Less throughput observed in DL-OFDMA with some APs that enabled Low density parity check coding. + +**MU-MIMO (DL)** + +- For CoEx Scenario Wi-Fi + BLE, BLE Data transfer, MU retries (~50-60%) observed while running DL MU-MIMO test.  +- Observed Performance, Interop issues with MU MIMO with certain APs.  +- Less throughput observed in MU-MIMO with some APs that enabled  Low density parity check coding + +**MU-MIMO (UL)** + +- UL MU-MIMO is not supported. + +**TWT** + +- When sl\_wifi\_enable\_target\_wake\_time() API is used, occasional MQTT disconnections may be observed if TWT is configured with longer TWT intervals (>30secs) with embedded MQTT + TWT.  As an alternative, it's highly recommended to use sl\_wifi\_target\_wake\_time\_auto\_selection() API, where these dependencies are internally handled. + +**Wi-Fi STA Rejoin** + +- Observed Scanning (probe request) in all channels instead of the channels configured in selective channel(channel\_bitmap\_2g4) during rejoin process.  + +**IPv4/IPv6** + +- IP change notification is not indicated to the application.  +- In concurrent mode with dual IP, if the STA starts after AP is up, the STA IP configuration may fail for DHCP stateless mode. +- In concurrent mode, data transfer using the Link-local address will always use the first IP interface created by the application. + +**BSD Socket API** + +- Every server socket created consumes a socket (maximum of 10 sockets supported) and every subsequent connection to server socket consumes an additional socket (from the same pool of 10 sockets), which limits the number of server connections supported. +- Observing issues with TCP retries when power save mode is enabled, especially when the module is in idle state. +- TCP maximum retry value is valid upto 31 + +**SSL Client/Server** + +- Sometimes during SSL Handshake, ECC curve parameters generated are wrong, resulting in connection failure with BBD2 error. However, this recovers in the next attempt. +- Secure SSL renegotiation is not supported in the Embedded Networking Stack + +**HTTP Client/ HTTPS Client** + +- Observed occasional HTTPS continuous download failures when power save is enabled. Recommended to disable it before performing HTTPS continuous downloads + +**SNTP** + +- Unable to get SNTP async events when CoEx mode and power save are enabled  + +**Throughputs & Performance** + +- Wi-Fi alone throughput is about SDK 3.x (42Mbps). SDK refinements are in progress to further improve Wi-Fi Standalone and CoEx Throughputs.  + +**Wi-Fi IOT Cloud integration** + +- **AWS IOT Core** + - Observed AWS MQTT keepalive transmission is not happening at expected intervals with power save enabled. + - Observing LAST\_WILL\_MESSAGE is random at every MQTT connection rather than the configured Message/Length +- **AZURE IOT Core** + - Observed DUT after sending the data, its not sending the MQTT keep alive packet due to this Azure HUB closing the connection when power save is enabled. + +**Wi-Fi Interoperability (IOP)** + +- Observed disconnections with Amplifi (AFI-INS-R) AP with powersave enable +- TWT session is failing due to disconnections observed in DUT if rx\_latency is set to 55 seconds and receive data is also set to 55 seconds on MI Xiaomi RA72 and Tplink AX53 AP's +- Observed less throughput(~1Mb) while running TCP RX with Max\_PSP powersave with DLink 810 AP +- Observed interop issue (random disconnections) with few APs (EERO 6+, EERO PRO 6E, Cisco Catalyst 9120AXID) +- Disconnections observed with Netgear RAX120 AP in WPA3 Security + +### **BLE**   + +**DTM/PER** + +- Recommend to limit BLE Tx Maximum power to 18 dBm.  Please don't use for 127 power\_index for BLE HP chain with this release. + +**DLE** + +- Removed the ble\_data\_length PSRAM example as it does not work with 121x and 141x OPN's.  + +**Privacy**  + +- DUT hang at the rsi\_bt\_get\_local\_device\_address API in central role, when using PSRAM boards (121x, 141x, 111M) and enabling power save in the ble\_privacy application, + +AE + +- Observed DUT hang issue while running TX notifications in peripheral role. + +**SMP**   + +- SMP is not working with 110L(Lite wireless firmware image) board.  + +**Throughput & performance**  + +- BLE throughput in LITE version is reduced compared to Standard Wireless Firmware +- The DUT hangs when the SRRC region is set in the ICs. However, this issue does not occur with the SiWG917Y module.  + + + +### **Multi-protocol** + +- For CoEx Scenario Wi-Fi + BLE, BLE Data transfer, MU retries (~50-60%) observed while running DL MU-MIMO test.  +- Observed Wi-Fi + BLE intermittent connection failures, disconnections, and data transfer stalls in the long run when power save is enabled. +- Observed "DUT is not disconnecting to the AP when initiating disconnection from EFR connect app screen using wifi\_station\_ble\_provisioning\_aws example +- Observed DUT failed to load certificate with error "0x10026" (SL\_STATUS\_SI91X\_WRONG\_PARAMETERS) while running wifi\_https\_ble\_dual\_role\_v6 application +- Observed BLE bonding failure during continuous HTTPS download. +- Observed BLE and WLAN connection failure with SMP, when WLAN connect and HTTPS GET called in a loop. +- Observed issue in displaying throughput for interval of 'TEST\_TIMEOUT' when CONTINUOUS\_THROUGHPUT enabled in wifi\_station\_ble\_throughput\_app demo +- In CoEx opermode, with memory config of TA - 480K and M4 - 192K Wi-Fi through is degrading by 10Mbps due less memory available for throughput. + +### **System** + +- Observed random hang issues with encrypted firmwares on some earlier variant of boards  (Si917-6031A, Si917-4338A) with powersave enable. +- This release addresses several issues, resulting in an additional 1K RAM usage in the NWP core. Consequently, this reduces the available heap size by 1K for the NWP core. Users with configurations that were already near the heap limit may experience either minor throughput issues OR functionality issues with this update. + +On encountering a problem, it can be mitigated by considering the following options: + +- Reduce the number of enabled features in the NWP core. +- Switch to a memory configuration that allocates more RAM to the NWP core while reducing RAM allocated to the Host processor. + +### **Simplicity Studio and Commander**  + +- Simplicity commander does not support options under "Debug Lock tools". +- All projects in the package are compatible with **GNU ARM V12.2.1** toolchain + +## **Limitations and Unsupported Features**   + +### **System** + +- 16MB Flash is not supported +- 16MB PSRAM is not supported +- Dual-Host mode is not supported + +### **SDK** + +- Baremetal mode is not supported. +- Zephyr is not supported + +### **Wi-Fi/Network Stack** + +- TLS 1.3 Server is not supported. +- 40 MHz bandwidth for 2.4 GHz band is not supported. +- Max 3 SSL sockets are supported in Wi-Fi alone and CoEx modes. No.of  SSL Sockets in Wi-Fi + BLE based on RAM memory configuration selected.  +- In SSL ECC Curve ID supported is 23. SSL handshake with 3rd party clients depends on the SSL ECC Curve ID. +- The number of Non-Transmitting BSSIDs processed is limited by the beacon length that can be processed by the stack (which is 1024 bytes). Beacons greater than 1024 Bytes in length will not be processed. +- Multiprotocol (STA +BLE) + EAP Security modes supported only with Memory configurations EXT\_FEAT\_416K\_M4SS\_256K and EXT\_FEAT\_480K\_M4SS\_192K. +- UL-MU-MIMO is not supported. +- WPA3 AP supports only H2E algorithm. +- PMKSA caching is not supported in WPA3 AP mode. +- Maximum embedded MQTT Publish payload is 1 kByte. +- Timeout value for socket select and socket receive calls of less than 1 second is not currently supported. +- SA query procedure not supported in 11W AP mode. +- WPA3 AP transition mode is not supported. +- AP standalone mode does not support Tx aggregation. Rx aggregation is supported with limited number of BA sessions. +- In concurrent AP mode, aggregation (Tx/Rx) is not supported. +- Embedded HTTP Server is not supported. +- mDNS with IPV6 is not supported. +- Low power scan supports 1 Mbps packets reception only. +- Auto PAC Provisioning in EAP-FAST with TLSv1.2 is not supported. +- bTWT , Intra PPDU Power save, Spatial Re-Use, BSS coloring features not supported +- HTTPS server is not supported. + +### **BLE** + +- For BLE, if the connection is established with a small connection interval (less than 15 ms), simultaneous roles (i.e., Central + Scanning and Peripheral + Advertising) are not supported. +- BLE maximum two concurrent connections are supported, which can be either a connection to two peripheral devices, to one central and one peripheral device or two central devices. +- BLE Slave latency value is valid up to 32 only. +- Maximum supported AE data length is 200 bytes. +- Supports only two ADV\_EXT sets. +- Supports only two BLE connections (1 Central and 1 Peripheral) with AE. +- Advertising Extension feature is not supported in Coexistence. +- The  ae\_central & ae\_peripheral applications are not supported with TA\_352K\_M4\_320K RAM configuration. +- Two BLE connections are not supported with M4 powersave. It only supports a single connection.  +- Isochronous channels feature is not supported.  +- Connection subrating feature is not supported.  +- LE power controller feature is not supported. +- EATT feature is not supported. +- Periodic Advertising with a response feature is not supported.  +- BLE Audio is not supported. +- The feature of dynamically changing the TX power when extended advertising is active is not supported. +- EFR Connect mobile application doesn't have support to differentiate the BLE configurators based on the Bluetooth Device address. +- The maximum BLE power has been reduced by 2dB compared to the Datasheet Number, which will be addressed in the upcoming 3.3.1 patch release. +- ICs do not support DEFAULT\_REGION and IGNORE\_REGION region codes. +- Modules do not support DEFAULT\_REGION and IGNORE\_REGION region codes in PER mode. + +### **MCU** + +- SensorHub supports PS1-power state with ADC sensor (FIFO mode not supported) . In this mode, the other sensor's operation is not supported. +- FreeRTOS Tickless IDLE mode is not supported in sensor hub application +- LittleFS support is intended to be used only with Dual flash +- PS1 state is not supported in Power Manager +- Power consumption is same for PS4 and PS3 states with powersave mode of power manager +- When using Button\_0 as wakeup source, it limits the button functionality at application layer. For using Button\_0 for application specific functionality, enable 'SL\_SI91X\_NPSS\_GPIO\_BTN\_HANDLER' +- Manual chip select option is not supported when using GSPI +- Mutli-slave mode is not supported in SSI Primary +- Dual and quad modes are not supported in SSI Primary +- Config timer doesn't support 32-bit timer +- Config timer features to trigger DMA and interrupts on events or counters are not supported +- UART instances does not support different FIFO Thresholds +- In UART Character Timeout feature is not supported +- Lower baud rates 110, 150, bit-width 1-4 and 9 are not supported in UART/USART +- RS485 Interface configuration is not supported +- In SDIO function2 to function5 are not supported +- Multichannel and external event based sampling are not supported in ADC +- Fast plus and High Speed modes are not supported in ULP\_I2C instance +- I2S-PCM is not supported +- MPU is not supported +- CPC is not supported +- Hardware Flow control for ULP UART is not supported +- HSPI Secondary is not supported +- Using a 32kHz external oscillator (connected to UULP GPIOs) may cause timer drift in the UULP peripherals +- Sample app and API information (in the API reference guide) for RSI based peripherals is not present + +### **Multi-protocol** + +- Wi-Fi AP + BLE currently not supported.  +- EXT\_FEAT\_352K\_M4SS\_320K RAM configuration is not supported for CoEx mode with SSL + +## **Removed/Deprecated Features** + +- Removed IR, SIO, RO temp sensor and FIM +- Removed support for WDT reset upon processor lock up +- Removed I2C SMBUS feature +- Removed hardware\_setup() from all power save application that uses sllib\_m4\_power\_save.slcc component +- sl\_si91x\_m4\_sleep\_wakeup() will be deprecated from upcoming releases +- switch\_m4\_frequency() will be deprecated from upcoming releases +- RO\_32KHZ\_CLOCK and MCU\_FSM\_\_CLOCK macros are removed + +> **Note:**  +> +> The following BLE Synchronous API's will be deprecated soon and the equivalent Asynchronous API's will be used instead in all BLE applications : +> +> |**S.NO**|**BLE Synchronous API's** |**BLE Asynchronous API's** | +> | :- | :- | :- | +> |1|rsi\_ble\_get\_profiles|rsi\_ble\_get\_profiles\_async| +> |2|rsi\_ble\_get\_profile|rsi\_ble\_get\_profile\_async| +> |3|rsi\_ble\_get\_char\_services|rsi\_ble\_get\_char\_services\_async| +> |4|rsi\_ble\_get\_inc\_services|rsi\_ble\_get\_inc\_services\_async| +> |5|rsi\_ble\_get\_char\_value\_by\_uuid|rsi\_ble\_get\_char\_value\_by\_uuid\_async| +> |6|rsi\_ble\_get\_att\_descriptors|rsi\_ble\_get\_att\_descriptors\_async| +> |7|rsi\_ble\_get\_att\_value|rsi\_ble\_get\_att\_value\_async| +> |8|rsi\_ble\_get\_multiple\_att\_values|rsi\_ble\_get\_multiple\_att\_values\_async| +> |9|rsi\_ble\_get\_long\_att\_value|rsi\_ble\_get\_long\_att\_value\_async| +> |10|rsi\_ble\_set\_att\_value|rsi\_ble\_set\_att\_value\_async| +> |11|rsi\_ble\_set\_long\_att\_value|NA| +> |12|rsi\_ble\_prepare\_write|rsi\_ble\_prepare\_write\_async| +> |13|rsi\_ble\_execute\_write|rsi\_ble\_execute\_write\_async| +> |14|rsi\_ble\_indicate\_value\_sync|rsi\_ble\_indicate\_value| + +
+ # **WiSeConnect3\_SDK\_3.3.3 SoC Release Notes** ## **Release Details** diff --git a/examples/featured/aws_device_shadow/aws_device_shadow_ncp.slcp b/examples/featured/aws_device_shadow/aws_device_shadow_ncp.slcp index b365d80d5..86f648025 100644 --- a/examples/featured/aws_device_shadow/aws_device_shadow_ncp.slcp +++ b/examples/featured/aws_device_shadow/aws_device_shadow_ncp.slcp @@ -14,7 +14,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/featured/aws_device_shadow/aws_device_shadow_psram.slcp b/examples/featured/aws_device_shadow/aws_device_shadow_psram.slcp index ef530b528..0b951f559 100644 --- a/examples/featured/aws_device_shadow/aws_device_shadow_psram.slcp +++ b/examples/featured/aws_device_shadow/aws_device_shadow_psram.slcp @@ -16,7 +16,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/featured/aws_device_shadow/aws_device_shadow_soc.slcp b/examples/featured/aws_device_shadow/aws_device_shadow_soc.slcp index f7ddfde04..355cc5874 100644 --- a/examples/featured/aws_device_shadow/aws_device_shadow_soc.slcp +++ b/examples/featured/aws_device_shadow/aws_device_shadow_soc.slcp @@ -14,7 +14,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/featured/aws_device_shadow/aws_device_shadow_uart_ncp.slcp b/examples/featured/aws_device_shadow/aws_device_shadow_uart_ncp.slcp index e1b567520..ecfa19ab5 100644 --- a/examples/featured/aws_device_shadow/aws_device_shadow_uart_ncp.slcp +++ b/examples/featured/aws_device_shadow/aws_device_shadow_uart_ncp.slcp @@ -14,7 +14,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/featured/ble_per/ble_per_ncp.slcp b/examples/featured/ble_per/ble_per_ncp.slcp index 5ab5bf2d6..44514f09a 100644 --- a/examples/featured/ble_per/ble_per_ncp.slcp +++ b/examples/featured/ble_per/ble_per_ncp.slcp @@ -16,7 +16,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/featured/ble_per/ble_per_psram.slcp b/examples/featured/ble_per/ble_per_psram.slcp index 62f3f40e5..2761d8775 100644 --- a/examples/featured/ble_per/ble_per_psram.slcp +++ b/examples/featured/ble_per/ble_per_psram.slcp @@ -16,7 +16,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/featured/ble_per/ble_per_soc.slcp b/examples/featured/ble_per/ble_per_soc.slcp index 6cb159049..8277c47d5 100644 --- a/examples/featured/ble_per/ble_per_soc.slcp +++ b/examples/featured/ble_per/ble_per_soc.slcp @@ -16,7 +16,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/featured/ble_per/ble_per_uart_ncp.slcp b/examples/featured/ble_per/ble_per_uart_ncp.slcp index 9ff735fd3..4c44a142e 100644 --- a/examples/featured/ble_per/ble_per_uart_ncp.slcp +++ b/examples/featured/ble_per/ble_per_uart_ncp.slcp @@ -16,7 +16,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/featured/firmware_update/firmware_update_fg25_ncp.slcp b/examples/featured/firmware_update/firmware_update_fg25_ncp.slcp index 0c4331f3a..0de2412ed 100644 --- a/examples/featured/firmware_update/firmware_update_fg25_ncp.slcp +++ b/examples/featured/firmware_update/firmware_update_fg25_ncp.slcp @@ -15,7 +15,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/featured/firmware_update/firmware_update_ncp.slcp b/examples/featured/firmware_update/firmware_update_ncp.slcp index 15f934c51..3d6d909a2 100644 --- a/examples/featured/firmware_update/firmware_update_ncp.slcp +++ b/examples/featured/firmware_update/firmware_update_ncp.slcp @@ -15,7 +15,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/featured/firmware_update/firmware_update_psram.slcp b/examples/featured/firmware_update/firmware_update_psram.slcp index dc5dea654..a381f4dd4 100644 --- a/examples/featured/firmware_update/firmware_update_psram.slcp +++ b/examples/featured/firmware_update/firmware_update_psram.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/featured/firmware_update/firmware_update_soc.slcp b/examples/featured/firmware_update/firmware_update_soc.slcp index dbb2d6f20..7ef11b6f6 100644 --- a/examples/featured/firmware_update/firmware_update_soc.slcp +++ b/examples/featured/firmware_update/firmware_update_soc.slcp @@ -15,7 +15,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/featured/firmware_update/firmware_update_uart_ncp.slcp b/examples/featured/firmware_update/firmware_update_uart_ncp.slcp index 706bceba6..3f7a3be98 100644 --- a/examples/featured/firmware_update/firmware_update_uart_ncp.slcp +++ b/examples/featured/firmware_update/firmware_update_uart_ncp.slcp @@ -15,7 +15,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/featured/low_power/power_save_deep_sleep/power_save_deep_sleep_ncp.slcp b/examples/featured/low_power/power_save_deep_sleep/power_save_deep_sleep_ncp.slcp index 9da5807a1..24aae4637 100644 --- a/examples/featured/low_power/power_save_deep_sleep/power_save_deep_sleep_ncp.slcp +++ b/examples/featured/low_power/power_save_deep_sleep/power_save_deep_sleep_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/featured/low_power/power_save_deep_sleep/power_save_deep_sleep_soc.slcp b/examples/featured/low_power/power_save_deep_sleep/power_save_deep_sleep_soc.slcp index eecf0d502..bcbb1d6ee 100644 --- a/examples/featured/low_power/power_save_deep_sleep/power_save_deep_sleep_soc.slcp +++ b/examples/featured/low_power/power_save_deep_sleep/power_save_deep_sleep_soc.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/featured/low_power/power_save_deep_sleep/power_save_deep_sleep_uart_ncp.slcp b/examples/featured/low_power/power_save_deep_sleep/power_save_deep_sleep_uart_ncp.slcp index ff0f11ce8..10a575bd9 100644 --- a/examples/featured/low_power/power_save_deep_sleep/power_save_deep_sleep_uart_ncp.slcp +++ b/examples/featured/low_power/power_save_deep_sleep/power_save_deep_sleep_uart_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/featured/low_power/powersave_standby_associated/powersave_standby_associated_ncp.slcp b/examples/featured/low_power/powersave_standby_associated/powersave_standby_associated_ncp.slcp index 67479d806..dc9b2ead8 100644 --- a/examples/featured/low_power/powersave_standby_associated/powersave_standby_associated_ncp.slcp +++ b/examples/featured/low_power/powersave_standby_associated/powersave_standby_associated_ncp.slcp @@ -15,7 +15,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/featured/low_power/powersave_standby_associated/powersave_standby_associated_psram.slcp b/examples/featured/low_power/powersave_standby_associated/powersave_standby_associated_psram.slcp index 82b14311a..4b4e986e2 100644 --- a/examples/featured/low_power/powersave_standby_associated/powersave_standby_associated_psram.slcp +++ b/examples/featured/low_power/powersave_standby_associated/powersave_standby_associated_psram.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/featured/low_power/powersave_standby_associated/powersave_standby_associated_soc.slcp b/examples/featured/low_power/powersave_standby_associated/powersave_standby_associated_soc.slcp index d7d983f05..912eddfbb 100644 --- a/examples/featured/low_power/powersave_standby_associated/powersave_standby_associated_soc.slcp +++ b/examples/featured/low_power/powersave_standby_associated/powersave_standby_associated_soc.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/featured/low_power/powersave_standby_associated/powersave_standby_associated_uart_ncp.slcp b/examples/featured/low_power/powersave_standby_associated/powersave_standby_associated_uart_ncp.slcp index 0ac6bfb0c..6fb7b300b 100644 --- a/examples/featured/low_power/powersave_standby_associated/powersave_standby_associated_uart_ncp.slcp +++ b/examples/featured/low_power/powersave_standby_associated/powersave_standby_associated_uart_ncp.slcp @@ -15,7 +15,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/featured/low_power/powersave_standby_associated_tcp_client/powersave_standby_associated_tcp_client_ncp.slcp b/examples/featured/low_power/powersave_standby_associated_tcp_client/powersave_standby_associated_tcp_client_ncp.slcp index 1dac6fef5..68dd64487 100644 --- a/examples/featured/low_power/powersave_standby_associated_tcp_client/powersave_standby_associated_tcp_client_ncp.slcp +++ b/examples/featured/low_power/powersave_standby_associated_tcp_client/powersave_standby_associated_tcp_client_ncp.slcp @@ -15,7 +15,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/featured/low_power/powersave_standby_associated_tcp_client/powersave_standby_associated_tcp_client_psram.slcp b/examples/featured/low_power/powersave_standby_associated_tcp_client/powersave_standby_associated_tcp_client_psram.slcp index 0433fb117..37f6e527b 100644 --- a/examples/featured/low_power/powersave_standby_associated_tcp_client/powersave_standby_associated_tcp_client_psram.slcp +++ b/examples/featured/low_power/powersave_standby_associated_tcp_client/powersave_standby_associated_tcp_client_psram.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/featured/low_power/powersave_standby_associated_tcp_client/powersave_standby_associated_tcp_client_soc.slcp b/examples/featured/low_power/powersave_standby_associated_tcp_client/powersave_standby_associated_tcp_client_soc.slcp index f17da3358..cad6128ff 100644 --- a/examples/featured/low_power/powersave_standby_associated_tcp_client/powersave_standby_associated_tcp_client_soc.slcp +++ b/examples/featured/low_power/powersave_standby_associated_tcp_client/powersave_standby_associated_tcp_client_soc.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/featured/low_power/powersave_standby_associated_tcp_client/powersave_standby_associated_tcp_client_uart_ncp.slcp b/examples/featured/low_power/powersave_standby_associated_tcp_client/powersave_standby_associated_tcp_client_uart_ncp.slcp index ec3ceb0f1..c2db0a60e 100644 --- a/examples/featured/low_power/powersave_standby_associated_tcp_client/powersave_standby_associated_tcp_client_uart_ncp.slcp +++ b/examples/featured/low_power/powersave_standby_associated_tcp_client/powersave_standby_associated_tcp_client_uart_ncp.slcp @@ -15,7 +15,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/featured/low_power/twt_tcp_client/twt_tcp_client_ncp.slcp b/examples/featured/low_power/twt_tcp_client/twt_tcp_client_ncp.slcp index 7f3bd3d77..c7d2511b8 100644 --- a/examples/featured/low_power/twt_tcp_client/twt_tcp_client_ncp.slcp +++ b/examples/featured/low_power/twt_tcp_client/twt_tcp_client_ncp.slcp @@ -16,7 +16,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/featured/low_power/twt_tcp_client/twt_tcp_client_soc.slcp b/examples/featured/low_power/twt_tcp_client/twt_tcp_client_soc.slcp index 70c38ae5f..34f176c89 100644 --- a/examples/featured/low_power/twt_tcp_client/twt_tcp_client_soc.slcp +++ b/examples/featured/low_power/twt_tcp_client/twt_tcp_client_soc.slcp @@ -16,7 +16,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/featured/wlan_throughput/wlan_throughput_ncp.slcp b/examples/featured/wlan_throughput/wlan_throughput_ncp.slcp index a60c068bc..d7aab7152 100644 --- a/examples/featured/wlan_throughput/wlan_throughput_ncp.slcp +++ b/examples/featured/wlan_throughput/wlan_throughput_ncp.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/featured/wlan_throughput/wlan_throughput_psram.slcp b/examples/featured/wlan_throughput/wlan_throughput_psram.slcp index b198d83f3..83d2dde4d 100644 --- a/examples/featured/wlan_throughput/wlan_throughput_psram.slcp +++ b/examples/featured/wlan_throughput/wlan_throughput_psram.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/featured/wlan_throughput/wlan_throughput_soc.slcp b/examples/featured/wlan_throughput/wlan_throughput_soc.slcp index ea2036e52..a7410e394 100644 --- a/examples/featured/wlan_throughput/wlan_throughput_soc.slcp +++ b/examples/featured/wlan_throughput/wlan_throughput_soc.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/featured/wlan_throughput/wlan_throughput_uart_ncp.slcp b/examples/featured/wlan_throughput/wlan_throughput_uart_ncp.slcp index 3d4e9ffe1..c39651492 100644 --- a/examples/featured/wlan_throughput/wlan_throughput_uart_ncp.slcp +++ b/examples/featured/wlan_throughput/wlan_throughput_uart_ncp.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/si91x_soc/cmsis-rtos/sl_si91x_msg_queue/sl_si91x_msg_queue.slcp b/examples/si91x_soc/cmsis-rtos/sl_si91x_msg_queue/sl_si91x_msg_queue.slcp index 2fdf619c9..15bcc846d 100644 --- a/examples/si91x_soc/cmsis-rtos/sl_si91x_msg_queue/sl_si91x_msg_queue.slcp +++ b/examples/si91x_soc/cmsis-rtos/sl_si91x_msg_queue/sl_si91x_msg_queue.slcp @@ -11,7 +11,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 readme: - path: readme.md source: diff --git a/examples/si91x_soc/cmsis-rtos/sl_si91x_mutex/sl_si91x_mutex.slcp b/examples/si91x_soc/cmsis-rtos/sl_si91x_mutex/sl_si91x_mutex.slcp index 0c306844a..17dd8d2b8 100644 --- a/examples/si91x_soc/cmsis-rtos/sl_si91x_mutex/sl_si91x_mutex.slcp +++ b/examples/si91x_soc/cmsis-rtos/sl_si91x_mutex/sl_si91x_mutex.slcp @@ -11,7 +11,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 readme: - path: readme.md source: diff --git a/examples/si91x_soc/crypto/si91x_psa_aes/si91x_psa_aes.slcp b/examples/si91x_soc/crypto/si91x_psa_aes/si91x_psa_aes.slcp index 3e093c577..8b5fe11b2 100644 --- a/examples/si91x_soc/crypto/si91x_psa_aes/si91x_psa_aes.slcp +++ b/examples/si91x_soc/crypto/si91x_psa_aes/si91x_psa_aes.slcp @@ -63,7 +63,7 @@ ui_hints: focus: true sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 toolchain_settings: - option: gcc_compiler_option value: -Wall -Werror diff --git a/examples/si91x_soc/crypto/si91x_psa_asymmetric_key_storage/si91x_psa_asymmetric_key_storage.slcp b/examples/si91x_soc/crypto/si91x_psa_asymmetric_key_storage/si91x_psa_asymmetric_key_storage.slcp index 71d383dcb..cc5a37d9d 100644 --- a/examples/si91x_soc/crypto/si91x_psa_asymmetric_key_storage/si91x_psa_asymmetric_key_storage.slcp +++ b/examples/si91x_soc/crypto/si91x_psa_asymmetric_key_storage/si91x_psa_asymmetric_key_storage.slcp @@ -29,7 +29,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 component: - id: sl_system - id: freertos diff --git a/examples/si91x_soc/crypto/si91x_psa_ccm/si91x_psa_ccm.slcp b/examples/si91x_soc/crypto/si91x_psa_ccm/si91x_psa_ccm.slcp index 7019fb25c..ffeedc0f0 100644 --- a/examples/si91x_soc/crypto/si91x_psa_ccm/si91x_psa_ccm.slcp +++ b/examples/si91x_soc/crypto/si91x_psa_ccm/si91x_psa_ccm.slcp @@ -28,7 +28,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 component: - id: sl_system - id: freertos diff --git a/examples/si91x_soc/crypto/si91x_psa_chachapoly/si91x_psa_chachapoly.slcp b/examples/si91x_soc/crypto/si91x_psa_chachapoly/si91x_psa_chachapoly.slcp index 75d75253f..2c7a9e8a6 100644 --- a/examples/si91x_soc/crypto/si91x_psa_chachapoly/si91x_psa_chachapoly.slcp +++ b/examples/si91x_soc/crypto/si91x_psa_chachapoly/si91x_psa_chachapoly.slcp @@ -28,7 +28,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 component: - id: sl_system - id: freertos diff --git a/examples/si91x_soc/crypto/si91x_psa_cmac/si91x_psa_cmac.slcp b/examples/si91x_soc/crypto/si91x_psa_cmac/si91x_psa_cmac.slcp index 5d545196a..cccdc5e02 100644 --- a/examples/si91x_soc/crypto/si91x_psa_cmac/si91x_psa_cmac.slcp +++ b/examples/si91x_soc/crypto/si91x_psa_cmac/si91x_psa_cmac.slcp @@ -10,7 +10,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: main.c - path: psa_cmac_app.c diff --git a/examples/si91x_soc/crypto/si91x_psa_ecdh/si91x_psa_ecdh.slcp b/examples/si91x_soc/crypto/si91x_psa_ecdh/si91x_psa_ecdh.slcp index e2aa565c0..792c1ff58 100644 --- a/examples/si91x_soc/crypto/si91x_psa_ecdh/si91x_psa_ecdh.slcp +++ b/examples/si91x_soc/crypto/si91x_psa_ecdh/si91x_psa_ecdh.slcp @@ -19,7 +19,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: main.c - path: psa_ecdh.c diff --git a/examples/si91x_soc/crypto/si91x_psa_ecdsa/si91x_psa_ecdsa.slcp b/examples/si91x_soc/crypto/si91x_psa_ecdsa/si91x_psa_ecdsa.slcp index f19465dee..67a606161 100644 --- a/examples/si91x_soc/crypto/si91x_psa_ecdsa/si91x_psa_ecdsa.slcp +++ b/examples/si91x_soc/crypto/si91x_psa_ecdsa/si91x_psa_ecdsa.slcp @@ -19,7 +19,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: main.c - path: app.c diff --git a/examples/si91x_soc/crypto/si91x_psa_gcm/si91x_psa_gcm.slcp b/examples/si91x_soc/crypto/si91x_psa_gcm/si91x_psa_gcm.slcp index 833f86278..14adf1c1a 100644 --- a/examples/si91x_soc/crypto/si91x_psa_gcm/si91x_psa_gcm.slcp +++ b/examples/si91x_soc/crypto/si91x_psa_gcm/si91x_psa_gcm.slcp @@ -28,7 +28,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 component: - id: sl_system - id: freertos diff --git a/examples/si91x_soc/crypto/si91x_psa_hmac/si91x_psa_hmac.slcp b/examples/si91x_soc/crypto/si91x_psa_hmac/si91x_psa_hmac.slcp index 4d9bab6a5..700880010 100644 --- a/examples/si91x_soc/crypto/si91x_psa_hmac/si91x_psa_hmac.slcp +++ b/examples/si91x_soc/crypto/si91x_psa_hmac/si91x_psa_hmac.slcp @@ -10,7 +10,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: main.c - path: psa_hmac_app.c diff --git a/examples/si91x_soc/crypto/si91x_psa_multithread/si91x_psa_multithread.slcp b/examples/si91x_soc/crypto/si91x_psa_multithread/si91x_psa_multithread.slcp index dfa9b29c2..59aaa0a7a 100644 --- a/examples/si91x_soc/crypto/si91x_psa_multithread/si91x_psa_multithread.slcp +++ b/examples/si91x_soc/crypto/si91x_psa_multithread/si91x_psa_multithread.slcp @@ -73,7 +73,7 @@ ui_hints: focus: true sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 toolchain_settings: - option: gcc_compiler_option value: -Wall -Werror diff --git a/examples/si91x_soc/crypto/si91x_psa_sha/si91x_psa_sha.slcp b/examples/si91x_soc/crypto/si91x_psa_sha/si91x_psa_sha.slcp index c04d4a8d8..7d86c4c69 100644 --- a/examples/si91x_soc/crypto/si91x_psa_sha/si91x_psa_sha.slcp +++ b/examples/si91x_soc/crypto/si91x_psa_sha/si91x_psa_sha.slcp @@ -19,7 +19,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: main.c - path: psa_sha_app.c diff --git a/examples/si91x_soc/crypto/si91x_psa_symmetric_key_storage/si91x_psa_symmetric_key_storage.slcp b/examples/si91x_soc/crypto/si91x_psa_symmetric_key_storage/si91x_psa_symmetric_key_storage.slcp index 4d6811f3b..ef58ac4d2 100644 --- a/examples/si91x_soc/crypto/si91x_psa_symmetric_key_storage/si91x_psa_symmetric_key_storage.slcp +++ b/examples/si91x_soc/crypto/si91x_psa_symmetric_key_storage/si91x_psa_symmetric_key_storage.slcp @@ -29,7 +29,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 define: - name: SL_SI91X_PRINT_DBG_LOG component: diff --git a/examples/si91x_soc/crypto/test/aead/si91x_test_aead.slcp b/examples/si91x_soc/crypto/test/aead/si91x_test_aead.slcp index c4fb3b112..4f9008749 100644 --- a/examples/si91x_soc/crypto/test/aead/si91x_test_aead.slcp +++ b/examples/si91x_soc/crypto/test/aead/si91x_test_aead.slcp @@ -29,7 +29,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 component: - id: sl_system - id: freertos diff --git a/examples/si91x_soc/crypto/test/cipher/si91x_test_cipher.slcp b/examples/si91x_soc/crypto/test/cipher/si91x_test_cipher.slcp index c6552a84d..f38c36ef7 100644 --- a/examples/si91x_soc/crypto/test/cipher/si91x_test_cipher.slcp +++ b/examples/si91x_soc/crypto/test/cipher/si91x_test_cipher.slcp @@ -21,7 +21,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 toolchain_settings: - option: gcc_compiler_option value: -Wall -Werror diff --git a/examples/si91x_soc/crypto/test/hash/si91x_test_hash.slcp b/examples/si91x_soc/crypto/test/hash/si91x_test_hash.slcp index 9d94f00af..a8e67e721 100644 --- a/examples/si91x_soc/crypto/test/hash/si91x_test_hash.slcp +++ b/examples/si91x_soc/crypto/test/hash/si91x_test_hash.slcp @@ -19,7 +19,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: main.c - path: app.c diff --git a/examples/si91x_soc/crypto/test/mac/si91x_test_mac.slcp b/examples/si91x_soc/crypto/test/mac/si91x_test_mac.slcp index aa0553876..cb0336d1f 100644 --- a/examples/si91x_soc/crypto/test/mac/si91x_test_mac.slcp +++ b/examples/si91x_soc/crypto/test/mac/si91x_test_mac.slcp @@ -10,7 +10,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: main.c - path: app.c diff --git a/examples/si91x_soc/hello_world/si91x_hello_world.slcp b/examples/si91x_soc/hello_world/si91x_hello_world.slcp index 58d3df6d7..5d579c8c0 100644 --- a/examples/si91x_soc/hello_world/si91x_hello_world.slcp +++ b/examples/si91x_soc/hello_world/si91x_hello_world.slcp @@ -10,7 +10,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/si91x_soc/peripheral/memlcd_baremetal/memlcd_baremetal.slcp b/examples/si91x_soc/peripheral/memlcd_baremetal/memlcd_baremetal.slcp index b10558d06..3c644d2ca 100644 --- a/examples/si91x_soc/peripheral/memlcd_baremetal/memlcd_baremetal.slcp +++ b/examples/si91x_soc/peripheral/memlcd_baremetal/memlcd_baremetal.slcp @@ -10,7 +10,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/si91x_soc/peripheral/psram_blinky/psram_blinky.slcp b/examples/si91x_soc/peripheral/psram_blinky/psram_blinky.slcp index 2858ca1d1..50cd13bc7 100644 --- a/examples/si91x_soc/peripheral/psram_blinky/psram_blinky.slcp +++ b/examples/si91x_soc/peripheral/psram_blinky/psram_blinky.slcp @@ -12,7 +12,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/si91x_soc/peripheral/psram_driver_example/psram_driver_example.slcp b/examples/si91x_soc/peripheral/psram_driver_example/psram_driver_example.slcp index d8c114a90..5b5b93140 100644 --- a/examples/si91x_soc/peripheral/psram_driver_example/psram_driver_example.slcp +++ b/examples/si91x_soc/peripheral/psram_driver_example/psram_driver_example.slcp @@ -14,7 +14,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 requires: - name: wiseconnect_toolchain_psram_linker source: diff --git a/examples/si91x_soc/peripheral/sl_si91x_adc_fifo_mode/sl_si91x_adc_fifo_mode.slcp b/examples/si91x_soc/peripheral/sl_si91x_adc_fifo_mode/sl_si91x_adc_fifo_mode.slcp index 325cf3617..5bfc25feb 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_adc_fifo_mode/sl_si91x_adc_fifo_mode.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_adc_fifo_mode/sl_si91x_adc_fifo_mode.slcp @@ -11,7 +11,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: adc_fifo_mode_example.c - path: app.c diff --git a/examples/si91x_soc/peripheral/sl_si91x_adc_static_mode/sl_si91x_adc_static_mode.slcp b/examples/si91x_soc/peripheral/sl_si91x_adc_static_mode/sl_si91x_adc_static_mode.slcp index e6d9e4e93..44457f7ee 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_adc_static_mode/sl_si91x_adc_static_mode.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_adc_static_mode/sl_si91x_adc_static_mode.slcp @@ -11,7 +11,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: adc_static_mode_example.c - path: app.c diff --git a/examples/si91x_soc/peripheral/sl_si91x_analog_comparator/sl_si91x_analog_comparator.slcp b/examples/si91x_soc/peripheral/sl_si91x_analog_comparator/sl_si91x_analog_comparator.slcp index 7e18cb1e0..4f85a89ff 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_analog_comparator/sl_si91x_analog_comparator.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_analog_comparator/sl_si91x_analog_comparator.slcp @@ -10,7 +10,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: main.c - path: app.c diff --git a/examples/si91x_soc/peripheral/sl_si91x_bjt_temperature_sensor/sl_si91x_bjt_temperature_sensor.slcp b/examples/si91x_soc/peripheral/sl_si91x_bjt_temperature_sensor/sl_si91x_bjt_temperature_sensor.slcp index 74ace2281..929c96c09 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_bjt_temperature_sensor/sl_si91x_bjt_temperature_sensor.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_bjt_temperature_sensor/sl_si91x_bjt_temperature_sensor.slcp @@ -11,7 +11,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: bjt_temperature_sensor_example.c - path: app.c diff --git a/examples/si91x_soc/peripheral/sl_si91x_blinky/sl_si91x_blinky.slcp b/examples/si91x_soc/peripheral/sl_si91x_blinky/sl_si91x_blinky.slcp index 505d520d5..0f7b3b56d 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_blinky/sl_si91x_blinky.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_blinky/sl_si91x_blinky.slcp @@ -10,7 +10,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/si91x_soc/peripheral/sl_si91x_button_baremetal/sl_si91x_button_baremetal.slcp b/examples/si91x_soc/peripheral/sl_si91x_button_baremetal/sl_si91x_button_baremetal.slcp index 69f4b3ca0..bdfcb08fe 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_button_baremetal/sl_si91x_button_baremetal.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_button_baremetal/sl_si91x_button_baremetal.slcp @@ -10,7 +10,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/si91x_soc/peripheral/sl_si91x_calendar/sl_si91x_calendar.slcp b/examples/si91x_soc/peripheral/sl_si91x_calendar/sl_si91x_calendar.slcp index 3bd2632c7..f776a23f9 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_calendar/sl_si91x_calendar.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_calendar/sl_si91x_calendar.slcp @@ -11,7 +11,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 readme: - path: readme.md source: diff --git a/examples/si91x_soc/peripheral/sl_si91x_combo_app/sl_si91x_combo_app.slcp b/examples/si91x_soc/peripheral/sl_si91x_combo_app/sl_si91x_combo_app.slcp index 936eaa1dc..38888006c 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_combo_app/sl_si91x_combo_app.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_combo_app/sl_si91x_combo_app.slcp @@ -11,7 +11,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 readme: - path: readme.md source: diff --git a/examples/si91x_soc/peripheral/sl_si91x_config_timer/sl_si91x_config_timer.slcp b/examples/si91x_soc/peripheral/sl_si91x_config_timer/sl_si91x_config_timer.slcp index c81eb0240..cccb5f389 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_config_timer/sl_si91x_config_timer.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_config_timer/sl_si91x_config_timer.slcp @@ -45,6 +45,6 @@ ui_hints: focus: true sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 post_build: path: ../../../../utilities/postbuild_profile/wiseconnect_soc.slpb diff --git a/examples/si91x_soc/peripheral/sl_si91x_crc/sl_si91x_crc.slcp b/examples/si91x_soc/peripheral/sl_si91x_crc/sl_si91x_crc.slcp index 11a6cb625..99af16c21 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_crc/sl_si91x_crc.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_crc/sl_si91x_crc.slcp @@ -10,7 +10,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 toolchain_settings: - option: gcc_compiler_option value: -Wall -Werror diff --git a/examples/si91x_soc/peripheral/sl_si91x_dac/sl_si91x_dac.slcp b/examples/si91x_soc/peripheral/sl_si91x_dac/sl_si91x_dac.slcp index fa92f8417..66480458a 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_dac/sl_si91x_dac.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_dac/sl_si91x_dac.slcp @@ -11,7 +11,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: dac_example.c - path: app.c diff --git a/examples/si91x_soc/peripheral/sl_si91x_dma/sl_si91x_dma.slcp b/examples/si91x_soc/peripheral/sl_si91x_dma/sl_si91x_dma.slcp index 28ba3f5d1..da8bdc81a 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_dma/sl_si91x_dma.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_dma/sl_si91x_dma.slcp @@ -10,7 +10,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 readme: - path: readme.md source: diff --git a/examples/si91x_soc/peripheral/sl_si91x_efuse/sl_si91x_efuse.slcp b/examples/si91x_soc/peripheral/sl_si91x_efuse/sl_si91x_efuse.slcp index 2b910a7c2..1b24e459a 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_efuse/sl_si91x_efuse.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_efuse/sl_si91x_efuse.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 toolchain_settings: - option: gcc_compiler_option value: -Wall -Werror diff --git a/examples/si91x_soc/peripheral/sl_si91x_gpio/sl_si91x_gpio.slcp b/examples/si91x_soc/peripheral/sl_si91x_gpio/sl_si91x_gpio.slcp index ea91c57d9..381f9ce87 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_gpio/sl_si91x_gpio.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_gpio/sl_si91x_gpio.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 toolchain_settings: - option: gcc_compiler_option value: -Wall -Werror diff --git a/examples/si91x_soc/peripheral/sl_si91x_gpio_detailed_example/sl_si91x_gpio_detailed_example.slcp b/examples/si91x_soc/peripheral/sl_si91x_gpio_detailed_example/sl_si91x_gpio_detailed_example.slcp index 70d1faa58..ba47f1f6c 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_gpio_detailed_example/sl_si91x_gpio_detailed_example.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_gpio_detailed_example/sl_si91x_gpio_detailed_example.slcp @@ -10,7 +10,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 readme: - path: readme.md source: diff --git a/examples/si91x_soc/peripheral/sl_si91x_gpio_example/sl_si91x_gpio_example.slcp b/examples/si91x_soc/peripheral/sl_si91x_gpio_example/sl_si91x_gpio_example.slcp index a71c9ac09..befcecdfa 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_gpio_example/sl_si91x_gpio_example.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_gpio_example/sl_si91x_gpio_example.slcp @@ -10,7 +10,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 readme: - path: readme.md source: diff --git a/examples/si91x_soc/peripheral/sl_si91x_gpio_group_example/sl_si91x_gpio_group_example.slcp b/examples/si91x_soc/peripheral/sl_si91x_gpio_group_example/sl_si91x_gpio_group_example.slcp index a94cd0a32..7ed541ba7 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_gpio_group_example/sl_si91x_gpio_group_example.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_gpio_group_example/sl_si91x_gpio_group_example.slcp @@ -10,7 +10,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 readme: - path: readme.md source: diff --git a/examples/si91x_soc/peripheral/sl_si91x_gpio_ulp_example/sl_si91x_gpio_ulp_example.slcp b/examples/si91x_soc/peripheral/sl_si91x_gpio_ulp_example/sl_si91x_gpio_ulp_example.slcp index a4077a181..42cac1a99 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_gpio_ulp_example/sl_si91x_gpio_ulp_example.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_gpio_ulp_example/sl_si91x_gpio_ulp_example.slcp @@ -10,7 +10,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 readme: - path: readme.md source: diff --git a/examples/si91x_soc/peripheral/sl_si91x_gpio_uulp_example/sl_si91x_gpio_uulp_example.slcp b/examples/si91x_soc/peripheral/sl_si91x_gpio_uulp_example/sl_si91x_gpio_uulp_example.slcp index e7996ed82..8fb24dd5f 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_gpio_uulp_example/sl_si91x_gpio_uulp_example.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_gpio_uulp_example/sl_si91x_gpio_uulp_example.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 toolchain_settings: - option: gcc_compiler_option value: -Wall -Werror diff --git a/examples/si91x_soc/peripheral/sl_si91x_gspi/sl_si91x_gspi.slcp b/examples/si91x_soc/peripheral/sl_si91x_gspi/sl_si91x_gspi.slcp index e7e257f10..f797983c3 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_gspi/sl_si91x_gspi.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_gspi/sl_si91x_gspi.slcp @@ -10,7 +10,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: main.c - path: app.c diff --git a/examples/si91x_soc/peripheral/sl_si91x_i2c_driver_follower/sl_si91x_i2c_driver_follower.slcp b/examples/si91x_soc/peripheral/sl_si91x_i2c_driver_follower/sl_si91x_i2c_driver_follower.slcp index 3d341086c..b6f5b0741 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_i2c_driver_follower/sl_si91x_i2c_driver_follower.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_i2c_driver_follower/sl_si91x_i2c_driver_follower.slcp @@ -10,7 +10,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: main.c - path: app.c diff --git a/examples/si91x_soc/peripheral/sl_si91x_i2c_driver_leader/sl_si91x_i2c_driver_leader.slcp b/examples/si91x_soc/peripheral/sl_si91x_i2c_driver_leader/sl_si91x_i2c_driver_leader.slcp index 98da6a93a..382211cc5 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_i2c_driver_leader/sl_si91x_i2c_driver_leader.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_i2c_driver_leader/sl_si91x_i2c_driver_leader.slcp @@ -10,7 +10,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: main.c - path: app.c diff --git a/examples/si91x_soc/peripheral/sl_si91x_i2s_loopback/sl_si91x_i2s_loopback.slcp b/examples/si91x_soc/peripheral/sl_si91x_i2s_loopback/sl_si91x_i2s_loopback.slcp index 3c4ffaf03..6838ddb3a 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_i2s_loopback/sl_si91x_i2s_loopback.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_i2s_loopback/sl_si91x_i2s_loopback.slcp @@ -10,7 +10,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: main.c - path: app.c diff --git a/examples/si91x_soc/peripheral/sl_si91x_i2s_primary/sl_si91x_i2s_primary.slcp b/examples/si91x_soc/peripheral/sl_si91x_i2s_primary/sl_si91x_i2s_primary.slcp index 2fc9dae76..1c451ca99 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_i2s_primary/sl_si91x_i2s_primary.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_i2s_primary/sl_si91x_i2s_primary.slcp @@ -10,7 +10,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: main.c - path: app.c diff --git a/examples/si91x_soc/peripheral/sl_si91x_i2s_secondary/sl_si91x_i2s_secondary.slcp b/examples/si91x_soc/peripheral/sl_si91x_i2s_secondary/sl_si91x_i2s_secondary.slcp index 7eebb1eef..e2a6b7b5e 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_i2s_secondary/sl_si91x_i2s_secondary.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_i2s_secondary/sl_si91x_i2s_secondary.slcp @@ -10,7 +10,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: main.c - path: app.c diff --git a/examples/si91x_soc/peripheral/sl_si91x_icm40627/sl_si91x_icm40627.slcp b/examples/si91x_soc/peripheral/sl_si91x_icm40627/sl_si91x_icm40627.slcp index 4a6169716..ace49b67e 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_icm40627/sl_si91x_icm40627.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_icm40627/sl_si91x_icm40627.slcp @@ -10,7 +10,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: main.c - path: app.c diff --git a/examples/si91x_soc/peripheral/sl_si91x_joystick/sl_si91x_joystick.slcp b/examples/si91x_soc/peripheral/sl_si91x_joystick/sl_si91x_joystick.slcp index f3c61744d..407d4d5a6 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_joystick/sl_si91x_joystick.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_joystick/sl_si91x_joystick.slcp @@ -11,7 +11,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: joystick_example.c - path: app.c diff --git a/examples/si91x_soc/peripheral/sl_si91x_pwm/sl_si91x_pwm.slcp b/examples/si91x_soc/peripheral/sl_si91x_pwm/sl_si91x_pwm.slcp index f01db8b4d..3af6bb676 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_pwm/sl_si91x_pwm.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_pwm/sl_si91x_pwm.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 toolchain_settings: - option: gcc_compiler_option value: -Wall -Werror diff --git a/examples/si91x_soc/peripheral/sl_si91x_rgb_led/sl_si91x_rgb_led.slcp b/examples/si91x_soc/peripheral/sl_si91x_rgb_led/sl_si91x_rgb_led.slcp index 0a54eb658..99ef15389 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_rgb_led/sl_si91x_rgb_led.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_rgb_led/sl_si91x_rgb_led.slcp @@ -10,7 +10,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/si91x_soc/peripheral/sl_si91x_sdio_secondary/sl_si91x_sdio_secondary.slcp b/examples/si91x_soc/peripheral/sl_si91x_sdio_secondary/sl_si91x_sdio_secondary.slcp index d145d5e2d..dd305860d 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_sdio_secondary/sl_si91x_sdio_secondary.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_sdio_secondary/sl_si91x_sdio_secondary.slcp @@ -10,7 +10,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: sdio_secondary_example.c - path: sdio_secondary_example.h diff --git a/examples/si91x_soc/peripheral/sl_si91x_si70xx/sl_si91x_si70xx.slcp b/examples/si91x_soc/peripheral/sl_si91x_si70xx/sl_si91x_si70xx.slcp index 59b3d536b..246aeca80 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_si70xx/sl_si91x_si70xx.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_si70xx/sl_si91x_si70xx.slcp @@ -48,6 +48,6 @@ ui_hints: focus: true sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 post_build: path: ../../../../utilities/postbuild_profile/wiseconnect_soc.slpb diff --git a/examples/si91x_soc/peripheral/sl_si91x_ssi_master/sl_si91x_ssi_master.slcp b/examples/si91x_soc/peripheral/sl_si91x_ssi_master/sl_si91x_ssi_master.slcp index 8577eb935..d49c329de 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_ssi_master/sl_si91x_ssi_master.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_ssi_master/sl_si91x_ssi_master.slcp @@ -16,7 +16,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 toolchain_settings: - option: gcc_compiler_option value: -Wall -Werror diff --git a/examples/si91x_soc/peripheral/sl_si91x_ssi_slave/sl_si91x_ssi_slave.slcp b/examples/si91x_soc/peripheral/sl_si91x_ssi_slave/sl_si91x_ssi_slave.slcp index 3abe89142..52bb64912 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_ssi_slave/sl_si91x_ssi_slave.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_ssi_slave/sl_si91x_ssi_slave.slcp @@ -16,7 +16,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 toolchain_settings: - option: gcc_compiler_option value: -Wall -Werror diff --git a/examples/si91x_soc/peripheral/sl_si91x_sysrtc/sl_si91x_sysrtc.slcp b/examples/si91x_soc/peripheral/sl_si91x_sysrtc/sl_si91x_sysrtc.slcp index 515510329..8f3772efc 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_sysrtc/sl_si91x_sysrtc.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_sysrtc/sl_si91x_sysrtc.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 toolchain_settings: - option: gcc_compiler_option value: -Wall -Werror diff --git a/examples/si91x_soc/peripheral/sl_si91x_uart/sl_si91x_uart.slcp b/examples/si91x_soc/peripheral/sl_si91x_uart/sl_si91x_uart.slcp index f5857af18..4b89c2d67 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_uart/sl_si91x_uart.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_uart/sl_si91x_uart.slcp @@ -11,7 +11,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: main.c - path: app.c diff --git a/examples/si91x_soc/peripheral/sl_si91x_ulp_adc/sl_si91x_ulp_adc.slcp b/examples/si91x_soc/peripheral/sl_si91x_ulp_adc/sl_si91x_ulp_adc.slcp index b84981775..c0d4a5394 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_ulp_adc/sl_si91x_ulp_adc.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_ulp_adc/sl_si91x_ulp_adc.slcp @@ -11,7 +11,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: sl_ulp_adc_example.c - path: app.c diff --git a/examples/si91x_soc/peripheral/sl_si91x_ulp_calendar/sl_si91x_ulp_calendar.slcp b/examples/si91x_soc/peripheral/sl_si91x_ulp_calendar/sl_si91x_ulp_calendar.slcp index 533961e2f..e49605218 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_ulp_calendar/sl_si91x_ulp_calendar.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_ulp_calendar/sl_si91x_ulp_calendar.slcp @@ -19,7 +19,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 toolchain_settings: - option: gcc_compiler_option value: -Wall -Werror diff --git a/examples/si91x_soc/peripheral/sl_si91x_ulp_dac/sl_si91x_ulp_dac.slcp b/examples/si91x_soc/peripheral/sl_si91x_ulp_dac/sl_si91x_ulp_dac.slcp index dd6cd05f0..d10baa886 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_ulp_dac/sl_si91x_ulp_dac.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_ulp_dac/sl_si91x_ulp_dac.slcp @@ -11,7 +11,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: sl_ulp_dac_example.c - path: app.c diff --git a/examples/si91x_soc/peripheral/sl_si91x_ulp_dma/sl_si91x_ulp_dma.slcp b/examples/si91x_soc/peripheral/sl_si91x_ulp_dma/sl_si91x_ulp_dma.slcp index 2bba39b46..819ae2052 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_ulp_dma/sl_si91x_ulp_dma.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_ulp_dma/sl_si91x_ulp_dma.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 toolchain_settings: - option: gcc_compiler_option value: -Wall -Werror diff --git a/examples/si91x_soc/peripheral/sl_si91x_ulp_gpio/sl_si91x_ulp_gpio.slcp b/examples/si91x_soc/peripheral/sl_si91x_ulp_gpio/sl_si91x_ulp_gpio.slcp index ab33ef1ac..db92f77ac 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_ulp_gpio/sl_si91x_ulp_gpio.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_ulp_gpio/sl_si91x_ulp_gpio.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 toolchain_settings: - option: gcc_compiler_option value: -Wall -Werror diff --git a/examples/si91x_soc/peripheral/sl_si91x_ulp_i2c_driver_leader/sl_si91x_ulp_i2c_driver_leader.slcp b/examples/si91x_soc/peripheral/sl_si91x_ulp_i2c_driver_leader/sl_si91x_ulp_i2c_driver_leader.slcp index 04e501df7..ebf538b1b 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_ulp_i2c_driver_leader/sl_si91x_ulp_i2c_driver_leader.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_ulp_i2c_driver_leader/sl_si91x_ulp_i2c_driver_leader.slcp @@ -10,7 +10,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: main.c - path: app.c diff --git a/examples/si91x_soc/peripheral/sl_si91x_ulp_i2s/sl_si91x_ulp_i2s.slcp b/examples/si91x_soc/peripheral/sl_si91x_ulp_i2s/sl_si91x_ulp_i2s.slcp index 88291433f..a4027098c 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_ulp_i2s/sl_si91x_ulp_i2s.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_ulp_i2s/sl_si91x_ulp_i2s.slcp @@ -11,7 +11,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: main.c - path: app.c diff --git a/examples/si91x_soc/peripheral/sl_si91x_ulp_ssi_master/sl_si91x_ulp_ssi_master.slcp b/examples/si91x_soc/peripheral/sl_si91x_ulp_ssi_master/sl_si91x_ulp_ssi_master.slcp index be490462f..86930d41b 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_ulp_ssi_master/sl_si91x_ulp_ssi_master.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_ulp_ssi_master/sl_si91x_ulp_ssi_master.slcp @@ -16,7 +16,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 toolchain_settings: - option: gcc_compiler_option value: -Wall -Werror diff --git a/examples/si91x_soc/peripheral/sl_si91x_ulp_timer/sl_si91x_ulp_timer.slcp b/examples/si91x_soc/peripheral/sl_si91x_ulp_timer/sl_si91x_ulp_timer.slcp index 4ca099e1e..c95359627 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_ulp_timer/sl_si91x_ulp_timer.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_ulp_timer/sl_si91x_ulp_timer.slcp @@ -19,7 +19,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 toolchain_settings: - option: gcc_compiler_option value: -Wall -Werror diff --git a/examples/si91x_soc/peripheral/sl_si91x_ulp_uart/sl_si91x_ulp_uart.slcp b/examples/si91x_soc/peripheral/sl_si91x_ulp_uart/sl_si91x_ulp_uart.slcp index e4e386465..12b346111 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_ulp_uart/sl_si91x_ulp_uart.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_ulp_uart/sl_si91x_ulp_uart.slcp @@ -11,7 +11,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: main.c - path: app.c diff --git a/examples/si91x_soc/peripheral/sl_si91x_usart_async/sl_si91x_usart_async.slcp b/examples/si91x_soc/peripheral/sl_si91x_usart_async/sl_si91x_usart_async.slcp index d07d911db..fbb995cce 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_usart_async/sl_si91x_usart_async.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_usart_async/sl_si91x_usart_async.slcp @@ -11,7 +11,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: main.c - path: app.c diff --git a/examples/si91x_soc/peripheral/sl_si91x_usart_sync_master/sl_si91x_usart_sync_master.slcp b/examples/si91x_soc/peripheral/sl_si91x_usart_sync_master/sl_si91x_usart_sync_master.slcp index 491a880d7..d59abd12d 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_usart_sync_master/sl_si91x_usart_sync_master.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_usart_sync_master/sl_si91x_usart_sync_master.slcp @@ -11,7 +11,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: main.c - path: app.c diff --git a/examples/si91x_soc/peripheral/sl_si91x_usart_sync_slave/sl_si91x_usart_sync_slave.slcp b/examples/si91x_soc/peripheral/sl_si91x_usart_sync_slave/sl_si91x_usart_sync_slave.slcp index ba538582f..130c23e5c 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_usart_sync_slave/sl_si91x_usart_sync_slave.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_usart_sync_slave/sl_si91x_usart_sync_slave.slcp @@ -11,7 +11,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: main.c - path: app.c diff --git a/examples/si91x_soc/peripheral/sl_si91x_veml6035/sl_si91x_veml6035.slcp b/examples/si91x_soc/peripheral/sl_si91x_veml6035/sl_si91x_veml6035.slcp index 064c525d4..05cf0f6fc 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_veml6035/sl_si91x_veml6035.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_veml6035/sl_si91x_veml6035.slcp @@ -21,7 +21,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 toolchain_settings: - option: gcc_compiler_option value: -Wall -Werror diff --git a/examples/si91x_soc/peripheral/sl_si91x_watchdog_timer/sl_si91x_watchdog_timer.slcp b/examples/si91x_soc/peripheral/sl_si91x_watchdog_timer/sl_si91x_watchdog_timer.slcp index a78d4af48..71a423252 100644 --- a/examples/si91x_soc/peripheral/sl_si91x_watchdog_timer/sl_si91x_watchdog_timer.slcp +++ b/examples/si91x_soc/peripheral/sl_si91x_watchdog_timer/sl_si91x_watchdog_timer.slcp @@ -10,7 +10,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: main.c - path: app.c diff --git a/examples/si91x_soc/service/iostream_usart_baremetal/iostream_usart_baremetal.slcp b/examples/si91x_soc/service/iostream_usart_baremetal/iostream_usart_baremetal.slcp index 33346cd67..19a07e6eb 100644 --- a/examples/si91x_soc/service/iostream_usart_baremetal/iostream_usart_baremetal.slcp +++ b/examples/si91x_soc/service/iostream_usart_baremetal/iostream_usart_baremetal.slcp @@ -14,7 +14,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 readme: - path: readme.md source: diff --git a/examples/si91x_soc/service/sl_si91x_littlefs/sl_si91x_file_system.slcp b/examples/si91x_soc/service/sl_si91x_littlefs/sl_si91x_file_system.slcp index ee42a754c..3dc424567 100644 --- a/examples/si91x_soc/service/sl_si91x_littlefs/sl_si91x_file_system.slcp +++ b/examples/si91x_soc/service/sl_si91x_littlefs/sl_si91x_file_system.slcp @@ -10,7 +10,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: main.c - path: app.c diff --git a/examples/si91x_soc/service/sl_si91x_nvm3_common_flash/sl_si91x_nvm3_common_flash.slcp b/examples/si91x_soc/service/sl_si91x_nvm3_common_flash/sl_si91x_nvm3_common_flash.slcp index 55c775bb3..5b58b51b5 100644 --- a/examples/si91x_soc/service/sl_si91x_nvm3_common_flash/sl_si91x_nvm3_common_flash.slcp +++ b/examples/si91x_soc/service/sl_si91x_nvm3_common_flash/sl_si91x_nvm3_common_flash.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/si91x_soc/service/sl_si91x_nvm3_dual_flash/sl_si91x_nvm3_dual_flash.slcp b/examples/si91x_soc/service/sl_si91x_nvm3_dual_flash/sl_si91x_nvm3_dual_flash.slcp index 8a843bcde..55c7ce4fd 100644 --- a/examples/si91x_soc/service/sl_si91x_nvm3_dual_flash/sl_si91x_nvm3_dual_flash.slcp +++ b/examples/si91x_soc/service/sl_si91x_nvm3_dual_flash/sl_si91x_nvm3_dual_flash.slcp @@ -21,7 +21,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 toolchain_settings: - option: gcc_compiler_option value: -Wall -Werror diff --git a/examples/si91x_soc/service/sl_si91x_power_manager_m4_wireless/sl_si91x_power_manager_m4_wireless.slcp b/examples/si91x_soc/service/sl_si91x_power_manager_m4_wireless/sl_si91x_power_manager_m4_wireless.slcp index 42e1b6f3a..369a87e69 100644 --- a/examples/si91x_soc/service/sl_si91x_power_manager_m4_wireless/sl_si91x_power_manager_m4_wireless.slcp +++ b/examples/si91x_soc/service/sl_si91x_power_manager_m4_wireless/sl_si91x_power_manager_m4_wireless.slcp @@ -10,7 +10,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 readme: - path: readme.md source: diff --git a/examples/si91x_soc/service/sl_si91x_power_manager_tickless_idle/sl_si91x_power_manager_tickless_idle.slcp b/examples/si91x_soc/service/sl_si91x_power_manager_tickless_idle/sl_si91x_power_manager_tickless_idle.slcp index 872cf6e36..f37511852 100644 --- a/examples/si91x_soc/service/sl_si91x_power_manager_tickless_idle/sl_si91x_power_manager_tickless_idle.slcp +++ b/examples/si91x_soc/service/sl_si91x_power_manager_tickless_idle/sl_si91x_power_manager_tickless_idle.slcp @@ -10,7 +10,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 readme: - path: readme.md source: diff --git a/examples/si91x_soc/service/sl_si91x_sensorhub/sl_si91x_sensorhub.slcp b/examples/si91x_soc/service/sl_si91x_sensorhub/sl_si91x_sensorhub.slcp index ec6701218..b7cd5d3be 100644 --- a/examples/si91x_soc/service/sl_si91x_sensorhub/sl_si91x_sensorhub.slcp +++ b/examples/si91x_soc/service/sl_si91x_sensorhub/sl_si91x_sensorhub.slcp @@ -10,7 +10,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: sensorhub_config.c - path: sensors/src/hub_hal_intf.c diff --git a/examples/si91x_soc/service/sl_si91x_sleeptimer/sl_si91x_sleeptimer.slcp b/examples/si91x_soc/service/sl_si91x_sleeptimer/sl_si91x_sleeptimer.slcp index 543764eaf..cdbac5298 100644 --- a/examples/si91x_soc/service/sl_si91x_sleeptimer/sl_si91x_sleeptimer.slcp +++ b/examples/si91x_soc/service/sl_si91x_sleeptimer/sl_si91x_sleeptimer.slcp @@ -10,7 +10,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/si91x_soc/siwx917_dev_kit/siwx917_dev_kit.slcp b/examples/si91x_soc/siwx917_dev_kit/siwx917_dev_kit.slcp index 5c0b81233..a9cb880fc 100644 --- a/examples/si91x_soc/siwx917_dev_kit/siwx917_dev_kit.slcp +++ b/examples/si91x_soc/siwx917_dev_kit/siwx917_dev_kit.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: ble_app.c diff --git a/examples/snippets/ble/ble_accept_list/ble_accept_list_ncp.slcp b/examples/snippets/ble/ble_accept_list/ble_accept_list_ncp.slcp index 81c0df5e2..653aafcf6 100644 --- a/examples/snippets/ble/ble_accept_list/ble_accept_list_ncp.slcp +++ b/examples/snippets/ble/ble_accept_list/ble_accept_list_ncp.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_accept_list/ble_accept_list_psram.slcp b/examples/snippets/ble/ble_accept_list/ble_accept_list_psram.slcp index 2afef0809..77761fda2 100644 --- a/examples/snippets/ble/ble_accept_list/ble_accept_list_psram.slcp +++ b/examples/snippets/ble/ble_accept_list/ble_accept_list_psram.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_accept_list/ble_accept_list_soc.slcp b/examples/snippets/ble/ble_accept_list/ble_accept_list_soc.slcp index 823ab178e..87b2f5aae 100644 --- a/examples/snippets/ble/ble_accept_list/ble_accept_list_soc.slcp +++ b/examples/snippets/ble/ble_accept_list/ble_accept_list_soc.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_ae_central/ble_ae_central_ncp.slcp b/examples/snippets/ble/ble_ae_central/ble_ae_central_ncp.slcp index 47030b166..19d7f212c 100644 --- a/examples/snippets/ble/ble_ae_central/ble_ae_central_ncp.slcp +++ b/examples/snippets/ble/ble_ae_central/ble_ae_central_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_ae_central/ble_ae_central_psram.slcp b/examples/snippets/ble/ble_ae_central/ble_ae_central_psram.slcp index eaf7523c3..53c5b1e09 100644 --- a/examples/snippets/ble/ble_ae_central/ble_ae_central_psram.slcp +++ b/examples/snippets/ble/ble_ae_central/ble_ae_central_psram.slcp @@ -12,7 +12,7 @@ filter: value: ["Advanced"] sdk: {id: simplicity_sdk, version: 2024.6.2} sdk_extension: -- {id: wiseconnect3_sdk, version: 3.3.3} +- {id: wiseconnect3_sdk, version: 3.3.4} source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_ae_central/ble_ae_central_soc.slcp b/examples/snippets/ble/ble_ae_central/ble_ae_central_soc.slcp index 0dcc3755a..ef614f966 100644 --- a/examples/snippets/ble/ble_ae_central/ble_ae_central_soc.slcp +++ b/examples/snippets/ble/ble_ae_central/ble_ae_central_soc.slcp @@ -12,7 +12,7 @@ filter: value: ["Advanced"] sdk: {id: simplicity_sdk, version: 2024.6.2} sdk_extension: -- {id: wiseconnect3_sdk, version: 3.3.3} +- {id: wiseconnect3_sdk, version: 3.3.4} source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_ae_central/ble_ae_central_uart_ncp.slcp b/examples/snippets/ble/ble_ae_central/ble_ae_central_uart_ncp.slcp index 67cdf1df9..318e18fcd 100644 --- a/examples/snippets/ble/ble_ae_central/ble_ae_central_uart_ncp.slcp +++ b/examples/snippets/ble/ble_ae_central/ble_ae_central_uart_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_ae_peripheral/ble_ae_peripheral_ncp.slcp b/examples/snippets/ble/ble_ae_peripheral/ble_ae_peripheral_ncp.slcp index 40f4f7c6c..7a5f2e7df 100644 --- a/examples/snippets/ble/ble_ae_peripheral/ble_ae_peripheral_ncp.slcp +++ b/examples/snippets/ble/ble_ae_peripheral/ble_ae_peripheral_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_ae_peripheral/ble_ae_peripheral_psram.slcp b/examples/snippets/ble/ble_ae_peripheral/ble_ae_peripheral_psram.slcp index c4b108d8c..4e4f76875 100644 --- a/examples/snippets/ble/ble_ae_peripheral/ble_ae_peripheral_psram.slcp +++ b/examples/snippets/ble/ble_ae_peripheral/ble_ae_peripheral_psram.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_ae_peripheral/ble_ae_peripheral_soc.slcp b/examples/snippets/ble/ble_ae_peripheral/ble_ae_peripheral_soc.slcp index b9b64b760..5781cfd93 100644 --- a/examples/snippets/ble/ble_ae_peripheral/ble_ae_peripheral_soc.slcp +++ b/examples/snippets/ble/ble_ae_peripheral/ble_ae_peripheral_soc.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_ae_peripheral/ble_ae_peripheral_uart_ncp.slcp b/examples/snippets/ble/ble_ae_peripheral/ble_ae_peripheral_uart_ncp.slcp index f8c524769..87da6f541 100644 --- a/examples/snippets/ble/ble_ae_peripheral/ble_ae_peripheral_uart_ncp.slcp +++ b/examples/snippets/ble/ble_ae_peripheral/ble_ae_peripheral_uart_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_central/ble_central_ncp.slcp b/examples/snippets/ble/ble_central/ble_central_ncp.slcp index be5d09df1..d44a12b94 100644 --- a/examples/snippets/ble/ble_central/ble_central_ncp.slcp +++ b/examples/snippets/ble/ble_central/ble_central_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_central/ble_central_psram.slcp b/examples/snippets/ble/ble_central/ble_central_psram.slcp index a9a0ef459..cac5437d3 100644 --- a/examples/snippets/ble/ble_central/ble_central_psram.slcp +++ b/examples/snippets/ble/ble_central/ble_central_psram.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_central/ble_central_soc.slcp b/examples/snippets/ble/ble_central/ble_central_soc.slcp index f943c47e7..ed7d9333b 100644 --- a/examples/snippets/ble/ble_central/ble_central_soc.slcp +++ b/examples/snippets/ble/ble_central/ble_central_soc.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_datalength/ble_datalength_ncp.slcp b/examples/snippets/ble/ble_datalength/ble_datalength_ncp.slcp index 5f1f2b89c..0147e530d 100644 --- a/examples/snippets/ble/ble_datalength/ble_datalength_ncp.slcp +++ b/examples/snippets/ble/ble_datalength/ble_datalength_ncp.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_datalength/ble_datalength_psram.slcp b/examples/snippets/ble/ble_datalength/ble_datalength_psram.slcp index 0ac3af4bb..9fb63ced7 100644 --- a/examples/snippets/ble/ble_datalength/ble_datalength_psram.slcp +++ b/examples/snippets/ble/ble_datalength/ble_datalength_psram.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_datalength/ble_datalength_soc.slcp b/examples/snippets/ble/ble_datalength/ble_datalength_soc.slcp index 5126266d0..db6b6fb1b 100644 --- a/examples/snippets/ble/ble_datalength/ble_datalength_soc.slcp +++ b/examples/snippets/ble/ble_datalength/ble_datalength_soc.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_heart_rate_profile/ble_heart_rate_profile_ncp.slcp b/examples/snippets/ble/ble_heart_rate_profile/ble_heart_rate_profile_ncp.slcp index 6305203fd..57705bc74 100644 --- a/examples/snippets/ble/ble_heart_rate_profile/ble_heart_rate_profile_ncp.slcp +++ b/examples/snippets/ble/ble_heart_rate_profile/ble_heart_rate_profile_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_heart_rate_profile/ble_heart_rate_profile_psram.slcp b/examples/snippets/ble/ble_heart_rate_profile/ble_heart_rate_profile_psram.slcp index 7b8cdbc26..7ecf1f7cd 100644 --- a/examples/snippets/ble/ble_heart_rate_profile/ble_heart_rate_profile_psram.slcp +++ b/examples/snippets/ble/ble_heart_rate_profile/ble_heart_rate_profile_psram.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_heart_rate_profile/ble_heart_rate_profile_soc.slcp b/examples/snippets/ble/ble_heart_rate_profile/ble_heart_rate_profile_soc.slcp index ee7e43803..3235f0113 100644 --- a/examples/snippets/ble/ble_heart_rate_profile/ble_heart_rate_profile_soc.slcp +++ b/examples/snippets/ble/ble_heart_rate_profile/ble_heart_rate_profile_soc.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_hid_on_gatt/ble_hid_on_gatt_ncp.slcp b/examples/snippets/ble/ble_hid_on_gatt/ble_hid_on_gatt_ncp.slcp index 008d9790b..da81d0d35 100644 --- a/examples/snippets/ble/ble_hid_on_gatt/ble_hid_on_gatt_ncp.slcp +++ b/examples/snippets/ble/ble_hid_on_gatt/ble_hid_on_gatt_ncp.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_hid_on_gatt/ble_hid_on_gatt_psram.slcp b/examples/snippets/ble/ble_hid_on_gatt/ble_hid_on_gatt_psram.slcp index 523df6ed9..402bcece0 100644 --- a/examples/snippets/ble/ble_hid_on_gatt/ble_hid_on_gatt_psram.slcp +++ b/examples/snippets/ble/ble_hid_on_gatt/ble_hid_on_gatt_psram.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_hid_on_gatt/ble_hid_on_gatt_soc.slcp b/examples/snippets/ble/ble_hid_on_gatt/ble_hid_on_gatt_soc.slcp index ca6fd65ed..b93323760 100644 --- a/examples/snippets/ble/ble_hid_on_gatt/ble_hid_on_gatt_soc.slcp +++ b/examples/snippets/ble/ble_hid_on_gatt/ble_hid_on_gatt_soc.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_ibeacon/ble_ibeacon_ncp.slcp b/examples/snippets/ble/ble_ibeacon/ble_ibeacon_ncp.slcp index 32688f024..83763a338 100644 --- a/examples/snippets/ble/ble_ibeacon/ble_ibeacon_ncp.slcp +++ b/examples/snippets/ble/ble_ibeacon/ble_ibeacon_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_ibeacon/ble_ibeacon_psram.slcp b/examples/snippets/ble/ble_ibeacon/ble_ibeacon_psram.slcp index d967f5300..f1c1399da 100644 --- a/examples/snippets/ble/ble_ibeacon/ble_ibeacon_psram.slcp +++ b/examples/snippets/ble/ble_ibeacon/ble_ibeacon_psram.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_ibeacon/ble_ibeacon_soc.slcp b/examples/snippets/ble/ble_ibeacon/ble_ibeacon_soc.slcp index 4765ce38e..ba10617ed 100644 --- a/examples/snippets/ble/ble_ibeacon/ble_ibeacon_soc.slcp +++ b/examples/snippets/ble/ble_ibeacon/ble_ibeacon_soc.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_longrange_2mbps/ble_longrange_2mbps_ncp.slcp b/examples/snippets/ble/ble_longrange_2mbps/ble_longrange_2mbps_ncp.slcp index d01088dea..39c497ffe 100644 --- a/examples/snippets/ble/ble_longrange_2mbps/ble_longrange_2mbps_ncp.slcp +++ b/examples/snippets/ble/ble_longrange_2mbps/ble_longrange_2mbps_ncp.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_longrange_2mbps/ble_longrange_2mbps_psram.slcp b/examples/snippets/ble/ble_longrange_2mbps/ble_longrange_2mbps_psram.slcp index 69d37deb0..942c5272f 100644 --- a/examples/snippets/ble/ble_longrange_2mbps/ble_longrange_2mbps_psram.slcp +++ b/examples/snippets/ble/ble_longrange_2mbps/ble_longrange_2mbps_psram.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_longrange_2mbps/ble_longrange_2mbps_soc.slcp b/examples/snippets/ble/ble_longrange_2mbps/ble_longrange_2mbps_soc.slcp index 3c9c5a181..9f5171cff 100644 --- a/examples/snippets/ble/ble_longrange_2mbps/ble_longrange_2mbps_soc.slcp +++ b/examples/snippets/ble/ble_longrange_2mbps/ble_longrange_2mbps_soc.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_multiconnection_gatt_test/ble_multiconnection_gatt_test_ncp.slcp b/examples/snippets/ble/ble_multiconnection_gatt_test/ble_multiconnection_gatt_test_ncp.slcp index ce104d59e..57dab3751 100644 --- a/examples/snippets/ble/ble_multiconnection_gatt_test/ble_multiconnection_gatt_test_ncp.slcp +++ b/examples/snippets/ble/ble_multiconnection_gatt_test/ble_multiconnection_gatt_test_ncp.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: ble_device_info.c - path: ble_main_task.c diff --git a/examples/snippets/ble/ble_multiconnection_gatt_test/ble_multiconnection_gatt_test_psram.slcp b/examples/snippets/ble/ble_multiconnection_gatt_test/ble_multiconnection_gatt_test_psram.slcp index 420003ee0..c99594e33 100644 --- a/examples/snippets/ble/ble_multiconnection_gatt_test/ble_multiconnection_gatt_test_psram.slcp +++ b/examples/snippets/ble/ble_multiconnection_gatt_test/ble_multiconnection_gatt_test_psram.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: ble_device_info.c - path: ble_main_task.c diff --git a/examples/snippets/ble/ble_multiconnection_gatt_test/ble_multiconnection_gatt_test_soc.slcp b/examples/snippets/ble/ble_multiconnection_gatt_test/ble_multiconnection_gatt_test_soc.slcp index cafed0d54..c23d73d49 100644 --- a/examples/snippets/ble/ble_multiconnection_gatt_test/ble_multiconnection_gatt_test_soc.slcp +++ b/examples/snippets/ble/ble_multiconnection_gatt_test/ble_multiconnection_gatt_test_soc.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: ble_device_info.c - path: ble_main_task.c diff --git a/examples/snippets/ble/ble_power_save/ble_power_save_ncp.slcp b/examples/snippets/ble/ble_power_save/ble_power_save_ncp.slcp index 0eb8f46a2..7ff9c5ec3 100644 --- a/examples/snippets/ble/ble_power_save/ble_power_save_ncp.slcp +++ b/examples/snippets/ble/ble_power_save/ble_power_save_ncp.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_power_save/ble_power_save_psram.slcp b/examples/snippets/ble/ble_power_save/ble_power_save_psram.slcp index cd380bb47..69376a526 100644 --- a/examples/snippets/ble/ble_power_save/ble_power_save_psram.slcp +++ b/examples/snippets/ble/ble_power_save/ble_power_save_psram.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_power_save/ble_power_save_soc.slcp b/examples/snippets/ble/ble_power_save/ble_power_save_soc.slcp index 9742caa23..94d9a66c7 100644 --- a/examples/snippets/ble/ble_power_save/ble_power_save_soc.slcp +++ b/examples/snippets/ble/ble_power_save/ble_power_save_soc.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_power_save/ble_power_save_uart_ncp.slcp b/examples/snippets/ble/ble_power_save/ble_power_save_uart_ncp.slcp index 648f98c86..eb9aa8758 100644 --- a/examples/snippets/ble/ble_power_save/ble_power_save_uart_ncp.slcp +++ b/examples/snippets/ble/ble_power_save/ble_power_save_uart_ncp.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_privacy/ble_privacy_ncp.slcp b/examples/snippets/ble/ble_privacy/ble_privacy_ncp.slcp index 7097654b9..a520accdc 100644 --- a/examples/snippets/ble/ble_privacy/ble_privacy_ncp.slcp +++ b/examples/snippets/ble/ble_privacy/ble_privacy_ncp.slcp @@ -19,7 +19,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_privacy/ble_privacy_psram.slcp b/examples/snippets/ble/ble_privacy/ble_privacy_psram.slcp index de6b4a707..d84ff1955 100644 --- a/examples/snippets/ble/ble_privacy/ble_privacy_psram.slcp +++ b/examples/snippets/ble/ble_privacy/ble_privacy_psram.slcp @@ -19,7 +19,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_privacy/ble_privacy_soc.slcp b/examples/snippets/ble/ble_privacy/ble_privacy_soc.slcp index 1f27b8cb2..1ace94cf7 100644 --- a/examples/snippets/ble/ble_privacy/ble_privacy_soc.slcp +++ b/examples/snippets/ble/ble_privacy/ble_privacy_soc.slcp @@ -19,7 +19,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_secureconnection/ble_secureconnection_ncp.slcp b/examples/snippets/ble/ble_secureconnection/ble_secureconnection_ncp.slcp index 99497b44b..c38e4178b 100644 --- a/examples/snippets/ble/ble_secureconnection/ble_secureconnection_ncp.slcp +++ b/examples/snippets/ble/ble_secureconnection/ble_secureconnection_ncp.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_secureconnection/ble_secureconnection_psram.slcp b/examples/snippets/ble/ble_secureconnection/ble_secureconnection_psram.slcp index 4c52982a0..d95e21237 100644 --- a/examples/snippets/ble/ble_secureconnection/ble_secureconnection_psram.slcp +++ b/examples/snippets/ble/ble_secureconnection/ble_secureconnection_psram.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_secureconnection/ble_secureconnection_soc.slcp b/examples/snippets/ble/ble_secureconnection/ble_secureconnection_soc.slcp index aeabcf020..a41ec4da6 100644 --- a/examples/snippets/ble/ble_secureconnection/ble_secureconnection_soc.slcp +++ b/examples/snippets/ble/ble_secureconnection/ble_secureconnection_soc.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_testmodes/ble_testmodes_ncp.slcp b/examples/snippets/ble/ble_testmodes/ble_testmodes_ncp.slcp index d6296ce00..1cb97f530 100644 --- a/examples/snippets/ble/ble_testmodes/ble_testmodes_ncp.slcp +++ b/examples/snippets/ble/ble_testmodes/ble_testmodes_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_testmodes/ble_testmodes_psram.slcp b/examples/snippets/ble/ble_testmodes/ble_testmodes_psram.slcp index fb17dd434..739c5f4f3 100644 --- a/examples/snippets/ble/ble_testmodes/ble_testmodes_psram.slcp +++ b/examples/snippets/ble/ble_testmodes/ble_testmodes_psram.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_testmodes/ble_testmodes_soc.slcp b/examples/snippets/ble/ble_testmodes/ble_testmodes_soc.slcp index c8164ec58..3926269ce 100644 --- a/examples/snippets/ble/ble_testmodes/ble_testmodes_soc.slcp +++ b/examples/snippets/ble/ble_testmodes/ble_testmodes_soc.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_throughput_app/ble_throughput_app_ncp.slcp b/examples/snippets/ble/ble_throughput_app/ble_throughput_app_ncp.slcp index 5e16f3384..30287f3be 100644 --- a/examples/snippets/ble/ble_throughput_app/ble_throughput_app_ncp.slcp +++ b/examples/snippets/ble/ble_throughput_app/ble_throughput_app_ncp.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_throughput_app/ble_throughput_app_psram.slcp b/examples/snippets/ble/ble_throughput_app/ble_throughput_app_psram.slcp index cfc1e1ca4..ae68a6265 100644 --- a/examples/snippets/ble/ble_throughput_app/ble_throughput_app_psram.slcp +++ b/examples/snippets/ble/ble_throughput_app/ble_throughput_app_psram.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_throughput_app/ble_throughput_app_soc.slcp b/examples/snippets/ble/ble_throughput_app/ble_throughput_app_soc.slcp index 3b41efef4..3a5886eaf 100644 --- a/examples/snippets/ble/ble_throughput_app/ble_throughput_app_soc.slcp +++ b/examples/snippets/ble/ble_throughput_app/ble_throughput_app_soc.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_throughput_app/ble_throughput_app_uart_ncp.slcp b/examples/snippets/ble/ble_throughput_app/ble_throughput_app_uart_ncp.slcp index 42c4a28ad..40286dbe8 100644 --- a/examples/snippets/ble/ble_throughput_app/ble_throughput_app_uart_ncp.slcp +++ b/examples/snippets/ble/ble_throughput_app/ble_throughput_app_uart_ncp.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_unified_ae_coex_app/ble_unified_ae_coex_app_ncp.slcp b/examples/snippets/ble/ble_unified_ae_coex_app/ble_unified_ae_coex_app_ncp.slcp index 413d8b55c..d93c3b3f9 100644 --- a/examples/snippets/ble/ble_unified_ae_coex_app/ble_unified_ae_coex_app_ncp.slcp +++ b/examples/snippets/ble/ble_unified_ae_coex_app/ble_unified_ae_coex_app_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_unified_ae_coex_app/ble_unified_ae_coex_app_psram.slcp b/examples/snippets/ble/ble_unified_ae_coex_app/ble_unified_ae_coex_app_psram.slcp index 5fee02089..c94dfd556 100644 --- a/examples/snippets/ble/ble_unified_ae_coex_app/ble_unified_ae_coex_app_psram.slcp +++ b/examples/snippets/ble/ble_unified_ae_coex_app/ble_unified_ae_coex_app_psram.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_unified_ae_coex_app/ble_unified_ae_coex_app_soc.slcp b/examples/snippets/ble/ble_unified_ae_coex_app/ble_unified_ae_coex_app_soc.slcp index 5df0ac50b..1af7ce415 100644 --- a/examples/snippets/ble/ble_unified_ae_coex_app/ble_unified_ae_coex_app_soc.slcp +++ b/examples/snippets/ble/ble_unified_ae_coex_app/ble_unified_ae_coex_app_soc.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_update_gain_table/ble_update_gain_table_ncp.slcp b/examples/snippets/ble/ble_update_gain_table/ble_update_gain_table_ncp.slcp index b3b6cb5cd..097ea3afa 100644 --- a/examples/snippets/ble/ble_update_gain_table/ble_update_gain_table_ncp.slcp +++ b/examples/snippets/ble/ble_update_gain_table/ble_update_gain_table_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_update_gain_table/ble_update_gain_table_psram.slcp b/examples/snippets/ble/ble_update_gain_table/ble_update_gain_table_psram.slcp index 315e0dce6..fa91708d0 100644 --- a/examples/snippets/ble/ble_update_gain_table/ble_update_gain_table_psram.slcp +++ b/examples/snippets/ble/ble_update_gain_table/ble_update_gain_table_psram.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/ble_update_gain_table/ble_update_gain_table_soc.slcp b/examples/snippets/ble/ble_update_gain_table/ble_update_gain_table_soc.slcp index 3ec5120c3..801e3c044 100644 --- a/examples/snippets/ble/ble_update_gain_table/ble_update_gain_table_soc.slcp +++ b/examples/snippets/ble/ble_update_gain_table/ble_update_gain_table_soc.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/bt_stack_bypass/bt_stack_bypass.slcp b/examples/snippets/ble/bt_stack_bypass/bt_stack_bypass.slcp index 9998f9aa1..566ca3909 100644 --- a/examples/snippets/ble/bt_stack_bypass/bt_stack_bypass.slcp +++ b/examples/snippets/ble/bt_stack_bypass/bt_stack_bypass.slcp @@ -12,7 +12,7 @@ filter: value: ["Beginner"] sdk: {id: simplicity_sdk, version: 2024.6.2} sdk_extension: -- {id: wiseconnect3_sdk, version: 3.3.3} +- {id: wiseconnect3_sdk, version: 3.3.4} source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/gatt_long_read/gatt_long_read_ncp.slcp b/examples/snippets/ble/gatt_long_read/gatt_long_read_ncp.slcp index 75429e892..679973250 100644 --- a/examples/snippets/ble/gatt_long_read/gatt_long_read_ncp.slcp +++ b/examples/snippets/ble/gatt_long_read/gatt_long_read_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/gatt_long_read/gatt_long_read_psram.slcp b/examples/snippets/ble/gatt_long_read/gatt_long_read_psram.slcp index 2c865e4fd..af8537685 100644 --- a/examples/snippets/ble/gatt_long_read/gatt_long_read_psram.slcp +++ b/examples/snippets/ble/gatt_long_read/gatt_long_read_psram.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/ble/gatt_long_read/gatt_long_read_soc.slcp b/examples/snippets/ble/gatt_long_read/gatt_long_read_soc.slcp index d749939b5..4a4469d91 100644 --- a/examples/snippets/ble/gatt_long_read/gatt_long_read_soc.slcp +++ b/examples/snippets/ble/gatt_long_read/gatt_long_read_soc.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/cli_demo/cli_demo_ncp.slcp b/examples/snippets/cli_demo/cli_demo_ncp.slcp index 721fe7e06..b9909d030 100644 --- a/examples/snippets/cli_demo/cli_demo_ncp.slcp +++ b/examples/snippets/cli_demo/cli_demo_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: demo.c - path: main.c diff --git a/examples/snippets/cli_demo/cli_demo_soc.slcp b/examples/snippets/cli_demo/cli_demo_soc.slcp index 792681e93..2dd295254 100644 --- a/examples/snippets/cli_demo/cli_demo_soc.slcp +++ b/examples/snippets/cli_demo/cli_demo_soc.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: demo.c - path: main.c diff --git a/examples/snippets/cli_demo/cli_demo_uart_ncp.slcp b/examples/snippets/cli_demo/cli_demo_uart_ncp.slcp index 1b1cd9e68..cf6ab5a55 100644 --- a/examples/snippets/cli_demo/cli_demo_uart_ncp.slcp +++ b/examples/snippets/cli_demo/cli_demo_uart_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: demo.c - path: main.c diff --git a/examples/snippets/crypto/aes/aes.slcp b/examples/snippets/crypto/aes/aes.slcp index 7b83306ab..04db217ef 100644 --- a/examples/snippets/crypto/aes/aes.slcp +++ b/examples/snippets/crypto/aes/aes.slcp @@ -12,7 +12,7 @@ filter: value: ["Beginner"] sdk: {id: simplicity_sdk, version: 2024.6.2} sdk_extension: -- {id: wiseconnect3_sdk, version: 3.3.3} +- {id: wiseconnect3_sdk, version: 3.3.4} source: - path: app.c - path: main.c diff --git a/examples/snippets/crypto/attestation/attestation.slcp b/examples/snippets/crypto/attestation/attestation.slcp index 950d6bd4c..d345834d6 100644 --- a/examples/snippets/crypto/attestation/attestation.slcp +++ b/examples/snippets/crypto/attestation/attestation.slcp @@ -9,7 +9,7 @@ quality: production sdk: {id: simplicity_sdk, version: 2024.6.2} sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/crypto/ecdh/ecdh.slcp b/examples/snippets/crypto/ecdh/ecdh.slcp index 26f43abe0..095e29232 100644 --- a/examples/snippets/crypto/ecdh/ecdh.slcp +++ b/examples/snippets/crypto/ecdh/ecdh.slcp @@ -11,7 +11,7 @@ filter: value: ["Beginner"] sdk: {id: simplicity_sdk, version: 2024.6.2} sdk_extension: -- {id: wiseconnect3_sdk, version: 3.3.3} +- {id: wiseconnect3_sdk, version: 3.3.4} source: - path: app.c - path: main.c diff --git a/examples/snippets/crypto/ecdsa/ecdsa.slcp b/examples/snippets/crypto/ecdsa/ecdsa.slcp index 70d36841b..742b95cc2 100644 --- a/examples/snippets/crypto/ecdsa/ecdsa.slcp +++ b/examples/snippets/crypto/ecdsa/ecdsa.slcp @@ -11,7 +11,7 @@ filter: value: ["Beginner"] sdk: {id: simplicity_sdk, version: 2024.6.2} sdk_extension: -- {id: wiseconnect3_sdk, version: 3.3.3} +- {id: wiseconnect3_sdk, version: 3.3.4} source: - path: app.c - path: main.c diff --git a/examples/snippets/crypto/gcm_cmac/gcm_cmac.slcp b/examples/snippets/crypto/gcm_cmac/gcm_cmac.slcp index 129803edd..95615f41d 100644 --- a/examples/snippets/crypto/gcm_cmac/gcm_cmac.slcp +++ b/examples/snippets/crypto/gcm_cmac/gcm_cmac.slcp @@ -12,7 +12,7 @@ filter: value: ["Beginner"] sdk: {id: simplicity_sdk, version: 2024.6.2} sdk_extension: -- {id: wiseconnect3_sdk, version: 3.3.3} +- {id: wiseconnect3_sdk, version: 3.3.4} source: - path: app.c - path: main.c diff --git a/examples/snippets/crypto/hmac/hmac.slcp b/examples/snippets/crypto/hmac/hmac.slcp index 5e1b6e369..984513cab 100644 --- a/examples/snippets/crypto/hmac/hmac.slcp +++ b/examples/snippets/crypto/hmac/hmac.slcp @@ -12,7 +12,7 @@ filter: value: ["Beginner"] sdk: {id: simplicity_sdk, version: 2024.6.2} sdk_extension: -- {id: wiseconnect3_sdk, version: 3.3.3} +- {id: wiseconnect3_sdk, version: 3.3.4} source: - path: app.c - path: main.c diff --git a/examples/snippets/crypto/sha/sha.slcp b/examples/snippets/crypto/sha/sha.slcp index 77c9c358d..65066ce17 100644 --- a/examples/snippets/crypto/sha/sha.slcp +++ b/examples/snippets/crypto/sha/sha.slcp @@ -12,7 +12,7 @@ filter: value: ["Beginner"] sdk: {id: simplicity_sdk, version: 2024.6.2} sdk_extension: -- {id: wiseconnect3_sdk, version: 3.3.3} +- {id: wiseconnect3_sdk, version: 3.3.4} source: - path: app.c - path: main.c diff --git a/examples/snippets/flash_read_write/flash_read_write.slcp b/examples/snippets/flash_read_write/flash_read_write.slcp index 9af3b2b92..39d3b3f42 100644 --- a/examples/snippets/flash_read_write/flash_read_write.slcp +++ b/examples/snippets/flash_read_write/flash_read_write.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/sl_si91x_empty_c/sl_si91x_empty_c_ncp.slcp b/examples/snippets/sl_si91x_empty_c/sl_si91x_empty_c_ncp.slcp index 5e7f26777..e124efd90 100644 --- a/examples/snippets/sl_si91x_empty_c/sl_si91x_empty_c_ncp.slcp +++ b/examples/snippets/sl_si91x_empty_c/sl_si91x_empty_c_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/sl_si91x_empty_c/sl_si91x_empty_c_soc.slcp b/examples/snippets/sl_si91x_empty_c/sl_si91x_empty_c_soc.slcp index a777472fb..fee069380 100644 --- a/examples/snippets/sl_si91x_empty_c/sl_si91x_empty_c_soc.slcp +++ b/examples/snippets/sl_si91x_empty_c/sl_si91x_empty_c_soc.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/sl_si91x_empty_cpp/sl_si91x_empty_cpp_ncp.slcp b/examples/snippets/sl_si91x_empty_cpp/sl_si91x_empty_cpp_ncp.slcp index 9f0967a05..9cf5e2a28 100644 --- a/examples/snippets/sl_si91x_empty_cpp/sl_si91x_empty_cpp_ncp.slcp +++ b/examples/snippets/sl_si91x_empty_cpp/sl_si91x_empty_cpp_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.cpp - path: main.cpp diff --git a/examples/snippets/sl_si91x_empty_cpp/sl_si91x_empty_cpp_soc.slcp b/examples/snippets/sl_si91x_empty_cpp/sl_si91x_empty_cpp_soc.slcp index 943288263..6ab8e40d9 100644 --- a/examples/snippets/sl_si91x_empty_cpp/sl_si91x_empty_cpp_soc.slcp +++ b/examples/snippets/sl_si91x_empty_cpp/sl_si91x_empty_cpp_soc.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.cpp - path: main.cpp diff --git a/examples/snippets/wlan/access_point/access_point_ncp.slcp b/examples/snippets/wlan/access_point/access_point_ncp.slcp index f8e2b5417..a3a9bfd3f 100644 --- a/examples/snippets/wlan/access_point/access_point_ncp.slcp +++ b/examples/snippets/wlan/access_point/access_point_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/access_point/access_point_soc.slcp b/examples/snippets/wlan/access_point/access_point_soc.slcp index 9220da293..1e6feeab7 100644 --- a/examples/snippets/wlan/access_point/access_point_soc.slcp +++ b/examples/snippets/wlan/access_point/access_point_soc.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/access_point/access_point_uart_ncp.slcp b/examples/snippets/wlan/access_point/access_point_uart_ncp.slcp index 3626657f9..b5e3d859d 100644 --- a/examples/snippets/wlan/access_point/access_point_uart_ncp.slcp +++ b/examples/snippets/wlan/access_point/access_point_uart_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/ap_throughput/ap_throughput_ncp.slcp b/examples/snippets/wlan/ap_throughput/ap_throughput_ncp.slcp index 577057e74..bbd2c5d19 100644 --- a/examples/snippets/wlan/ap_throughput/ap_throughput_ncp.slcp +++ b/examples/snippets/wlan/ap_throughput/ap_throughput_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/ap_throughput/ap_throughput_soc.slcp b/examples/snippets/wlan/ap_throughput/ap_throughput_soc.slcp index 83e18ae12..f4867782d 100644 --- a/examples/snippets/wlan/ap_throughput/ap_throughput_soc.slcp +++ b/examples/snippets/wlan/ap_throughput/ap_throughput_soc.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/calibration_app/calibration_app_ncp.slcp b/examples/snippets/wlan/calibration_app/calibration_app_ncp.slcp index 4400c82b8..8489de56d 100644 --- a/examples/snippets/wlan/calibration_app/calibration_app_ncp.slcp +++ b/examples/snippets/wlan/calibration_app/calibration_app_ncp.slcp @@ -12,7 +12,7 @@ filter: value: ["Beginner"] sdk: {id: simplicity_sdk, version: 2024.6.2} sdk_extension: -- {id: wiseconnect3_sdk, version: 3.3.3} +- {id: wiseconnect3_sdk, version: 3.3.4} source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/calibration_app/calibration_app_soc.slcp b/examples/snippets/wlan/calibration_app/calibration_app_soc.slcp index 0b7b94666..61da4ad3a 100644 --- a/examples/snippets/wlan/calibration_app/calibration_app_soc.slcp +++ b/examples/snippets/wlan/calibration_app/calibration_app_soc.slcp @@ -12,7 +12,7 @@ filter: value: ["Beginner"] sdk: {id: simplicity_sdk, version: 2024.6.2} sdk_extension: -- {id: wiseconnect3_sdk, version: 3.3.3} +- {id: wiseconnect3_sdk, version: 3.3.4} source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/calibration_app/calibration_app_uart_ncp.slcp b/examples/snippets/wlan/calibration_app/calibration_app_uart_ncp.slcp index 6ef013bf0..1b4a3be6d 100644 --- a/examples/snippets/wlan/calibration_app/calibration_app_uart_ncp.slcp +++ b/examples/snippets/wlan/calibration_app/calibration_app_uart_ncp.slcp @@ -12,7 +12,7 @@ filter: value: ["Beginner"] sdk: {id: simplicity_sdk, version: 2024.6.2} sdk_extension: -- {id: wiseconnect3_sdk, version: 3.3.3} +- {id: wiseconnect3_sdk, version: 3.3.4} source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/cloud_apps/aws/mqtt/aws_mqtt_ncp.slcp b/examples/snippets/wlan/cloud_apps/aws/mqtt/aws_mqtt_ncp.slcp index 1e3464368..491b9029f 100644 --- a/examples/snippets/wlan/cloud_apps/aws/mqtt/aws_mqtt_ncp.slcp +++ b/examples/snippets/wlan/cloud_apps/aws/mqtt/aws_mqtt_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/cloud_apps/aws/mqtt/aws_mqtt_soc.slcp b/examples/snippets/wlan/cloud_apps/aws/mqtt/aws_mqtt_soc.slcp index fa7c6ab67..54f12a3dc 100644 --- a/examples/snippets/wlan/cloud_apps/aws/mqtt/aws_mqtt_soc.slcp +++ b/examples/snippets/wlan/cloud_apps/aws/mqtt/aws_mqtt_soc.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/cloud_apps/azure/azure_iot_ncp.slcp b/examples/snippets/wlan/cloud_apps/azure/azure_iot_ncp.slcp index b869dbbf8..cdb262d7a 100644 --- a/examples/snippets/wlan/cloud_apps/azure/azure_iot_ncp.slcp +++ b/examples/snippets/wlan/cloud_apps/azure/azure_iot_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/cloud_apps/azure/azure_iot_soc.slcp b/examples/snippets/wlan/cloud_apps/azure/azure_iot_soc.slcp index e6fd7f3fd..4cc6b0c97 100644 --- a/examples/snippets/wlan/cloud_apps/azure/azure_iot_soc.slcp +++ b/examples/snippets/wlan/cloud_apps/azure/azure_iot_soc.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/concurrent_firmware_update_from_host_uart/concurrent_firmware_update_from_host_uart_fg25_ncp.slcp b/examples/snippets/wlan/concurrent_firmware_update_from_host_uart/concurrent_firmware_update_from_host_uart_fg25_ncp.slcp index eb70a42ca..3312c5ede 100644 --- a/examples/snippets/wlan/concurrent_firmware_update_from_host_uart/concurrent_firmware_update_from_host_uart_fg25_ncp.slcp +++ b/examples/snippets/wlan/concurrent_firmware_update_from_host_uart/concurrent_firmware_update_from_host_uart_fg25_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/concurrent_http_server/concurrent_http_server_ncp.slcp b/examples/snippets/wlan/concurrent_http_server/concurrent_http_server_ncp.slcp index 006c52b0b..d7a38e342 100644 --- a/examples/snippets/wlan/concurrent_http_server/concurrent_http_server_ncp.slcp +++ b/examples/snippets/wlan/concurrent_http_server/concurrent_http_server_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/concurrent_http_server/concurrent_http_server_soc.slcp b/examples/snippets/wlan/concurrent_http_server/concurrent_http_server_soc.slcp index 38273575e..6a1756330 100644 --- a/examples/snippets/wlan/concurrent_http_server/concurrent_http_server_soc.slcp +++ b/examples/snippets/wlan/concurrent_http_server/concurrent_http_server_soc.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/concurrent_http_server_provisioning/concurrent_http_server_provisioning_fg25_ncp.slcp b/examples/snippets/wlan/concurrent_http_server_provisioning/concurrent_http_server_provisioning_fg25_ncp.slcp index 05988c74b..d8ed96be3 100644 --- a/examples/snippets/wlan/concurrent_http_server_provisioning/concurrent_http_server_provisioning_fg25_ncp.slcp +++ b/examples/snippets/wlan/concurrent_http_server_provisioning/concurrent_http_server_provisioning_fg25_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/concurrent_http_server_provisioning/concurrent_http_server_provisioning_ncp.slcp b/examples/snippets/wlan/concurrent_http_server_provisioning/concurrent_http_server_provisioning_ncp.slcp index cc95b4799..58a4109f0 100644 --- a/examples/snippets/wlan/concurrent_http_server_provisioning/concurrent_http_server_provisioning_ncp.slcp +++ b/examples/snippets/wlan/concurrent_http_server_provisioning/concurrent_http_server_provisioning_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/concurrent_http_server_provisioning/concurrent_http_server_provisioning_soc.slcp b/examples/snippets/wlan/concurrent_http_server_provisioning/concurrent_http_server_provisioning_soc.slcp index 5b3769884..65563ab4d 100644 --- a/examples/snippets/wlan/concurrent_http_server_provisioning/concurrent_http_server_provisioning_soc.slcp +++ b/examples/snippets/wlan/concurrent_http_server_provisioning/concurrent_http_server_provisioning_soc.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/concurrent_mode/concurrent_mode_fg25_ncp.slcp b/examples/snippets/wlan/concurrent_mode/concurrent_mode_fg25_ncp.slcp index 8ad14cdcf..bcd411c7b 100644 --- a/examples/snippets/wlan/concurrent_mode/concurrent_mode_fg25_ncp.slcp +++ b/examples/snippets/wlan/concurrent_mode/concurrent_mode_fg25_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/concurrent_mode/concurrent_mode_ncp.slcp b/examples/snippets/wlan/concurrent_mode/concurrent_mode_ncp.slcp index c9e05bcb6..34e726d0d 100644 --- a/examples/snippets/wlan/concurrent_mode/concurrent_mode_ncp.slcp +++ b/examples/snippets/wlan/concurrent_mode/concurrent_mode_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/concurrent_mode/concurrent_mode_soc.slcp b/examples/snippets/wlan/concurrent_mode/concurrent_mode_soc.slcp index 6ce1df0aa..a234c0b9c 100644 --- a/examples/snippets/wlan/concurrent_mode/concurrent_mode_soc.slcp +++ b/examples/snippets/wlan/concurrent_mode/concurrent_mode_soc.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/concurrent_mode/concurrent_mode_uart_ncp.slcp b/examples/snippets/wlan/concurrent_mode/concurrent_mode_uart_ncp.slcp index 86ede7e56..f55823635 100644 --- a/examples/snippets/wlan/concurrent_mode/concurrent_mode_uart_ncp.slcp +++ b/examples/snippets/wlan/concurrent_mode/concurrent_mode_uart_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/concurrent_mode_dual_ip/concurrent_mode_dual_ip_fg25_ncp.slcp b/examples/snippets/wlan/concurrent_mode_dual_ip/concurrent_mode_dual_ip_fg25_ncp.slcp index 17dd28c86..26e95bc7e 100644 --- a/examples/snippets/wlan/concurrent_mode_dual_ip/concurrent_mode_dual_ip_fg25_ncp.slcp +++ b/examples/snippets/wlan/concurrent_mode_dual_ip/concurrent_mode_dual_ip_fg25_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/concurrent_mode_dual_ip/concurrent_mode_dual_ip_ncp.slcp b/examples/snippets/wlan/concurrent_mode_dual_ip/concurrent_mode_dual_ip_ncp.slcp index 75e7d2b1c..94ffc107b 100644 --- a/examples/snippets/wlan/concurrent_mode_dual_ip/concurrent_mode_dual_ip_ncp.slcp +++ b/examples/snippets/wlan/concurrent_mode_dual_ip/concurrent_mode_dual_ip_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/concurrent_mode_dual_ip/concurrent_mode_dual_ip_soc.slcp b/examples/snippets/wlan/concurrent_mode_dual_ip/concurrent_mode_dual_ip_soc.slcp index 7cd0607d9..857e2b532 100644 --- a/examples/snippets/wlan/concurrent_mode_dual_ip/concurrent_mode_dual_ip_soc.slcp +++ b/examples/snippets/wlan/concurrent_mode_dual_ip/concurrent_mode_dual_ip_soc.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/data_transfer/data_transfer_ncp.slcp b/examples/snippets/wlan/data_transfer/data_transfer_ncp.slcp index 7aff149a9..a629f850b 100644 --- a/examples/snippets/wlan/data_transfer/data_transfer_ncp.slcp +++ b/examples/snippets/wlan/data_transfer/data_transfer_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/data_transfer/data_transfer_soc.slcp b/examples/snippets/wlan/data_transfer/data_transfer_soc.slcp index c252527da..144283bbf 100644 --- a/examples/snippets/wlan/data_transfer/data_transfer_soc.slcp +++ b/examples/snippets/wlan/data_transfer/data_transfer_soc.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/embedded_mqtt_client/embedded_mqtt_client_ncp.slcp b/examples/snippets/wlan/embedded_mqtt_client/embedded_mqtt_client_ncp.slcp index dca7681aa..63fc476cc 100644 --- a/examples/snippets/wlan/embedded_mqtt_client/embedded_mqtt_client_ncp.slcp +++ b/examples/snippets/wlan/embedded_mqtt_client/embedded_mqtt_client_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/embedded_mqtt_client/embedded_mqtt_client_soc.slcp b/examples/snippets/wlan/embedded_mqtt_client/embedded_mqtt_client_soc.slcp index 5cb7cc216..712898bd5 100644 --- a/examples/snippets/wlan/embedded_mqtt_client/embedded_mqtt_client_soc.slcp +++ b/examples/snippets/wlan/embedded_mqtt_client/embedded_mqtt_client_soc.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/embedded_mqtt_client_twt/embedded_mqtt_client_twt_ncp.slcp b/examples/snippets/wlan/embedded_mqtt_client_twt/embedded_mqtt_client_twt_ncp.slcp index a4b2ac7e7..aec472a58 100644 --- a/examples/snippets/wlan/embedded_mqtt_client_twt/embedded_mqtt_client_twt_ncp.slcp +++ b/examples/snippets/wlan/embedded_mqtt_client_twt/embedded_mqtt_client_twt_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/embedded_mqtt_client_twt/embedded_mqtt_client_twt_soc.slcp b/examples/snippets/wlan/embedded_mqtt_client_twt/embedded_mqtt_client_twt_soc.slcp index 10f320060..22d1a53a3 100644 --- a/examples/snippets/wlan/embedded_mqtt_client_twt/embedded_mqtt_client_twt_soc.slcp +++ b/examples/snippets/wlan/embedded_mqtt_client_twt/embedded_mqtt_client_twt_soc.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/embedded_mqtt_client_twt/embedded_mqtt_client_twt_uart_ncp.slcp b/examples/snippets/wlan/embedded_mqtt_client_twt/embedded_mqtt_client_twt_uart_ncp.slcp index 506c901a9..520aa6fa6 100644 --- a/examples/snippets/wlan/embedded_mqtt_client_twt/embedded_mqtt_client_twt_uart_ncp.slcp +++ b/examples/snippets/wlan/embedded_mqtt_client_twt/embedded_mqtt_client_twt_uart_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/enterprise_client/enterprise_client_ncp.slcp b/examples/snippets/wlan/enterprise_client/enterprise_client_ncp.slcp index 0d8c69d20..ceb613194 100644 --- a/examples/snippets/wlan/enterprise_client/enterprise_client_ncp.slcp +++ b/examples/snippets/wlan/enterprise_client/enterprise_client_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/enterprise_client/enterprise_client_soc.slcp b/examples/snippets/wlan/enterprise_client/enterprise_client_soc.slcp index 4315079dc..b6577023c 100644 --- a/examples/snippets/wlan/enterprise_client/enterprise_client_soc.slcp +++ b/examples/snippets/wlan/enterprise_client/enterprise_client_soc.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/firmware_flashing_from_host_uart_xmodem/firmware_flashing_ncp.slcp b/examples/snippets/wlan/firmware_flashing_from_host_uart_xmodem/firmware_flashing_ncp.slcp index d3a928456..7eb9a0f7d 100644 --- a/examples/snippets/wlan/firmware_flashing_from_host_uart_xmodem/firmware_flashing_ncp.slcp +++ b/examples/snippets/wlan/firmware_flashing_from_host_uart_xmodem/firmware_flashing_ncp.slcp @@ -15,7 +15,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/firmware_flashing_from_host_uart_xmodem/firmware_flashing_soc.slcp b/examples/snippets/wlan/firmware_flashing_from_host_uart_xmodem/firmware_flashing_soc.slcp index 278256fc2..879fb3514 100644 --- a/examples/snippets/wlan/firmware_flashing_from_host_uart_xmodem/firmware_flashing_soc.slcp +++ b/examples/snippets/wlan/firmware_flashing_from_host_uart_xmodem/firmware_flashing_soc.slcp @@ -15,7 +15,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/http_client/http_client_ncp.slcp b/examples/snippets/wlan/http_client/http_client_ncp.slcp index 5f315b282..8601f07d8 100644 --- a/examples/snippets/wlan/http_client/http_client_ncp.slcp +++ b/examples/snippets/wlan/http_client/http_client_ncp.slcp @@ -12,7 +12,7 @@ filter: value: ["Beginner"] sdk: {id: simplicity_sdk, version: 2024.6.2} sdk_extension: -- {id: wiseconnect3_sdk, version: 3.3.3} +- {id: wiseconnect3_sdk, version: 3.3.4} source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/http_client/http_client_soc.slcp b/examples/snippets/wlan/http_client/http_client_soc.slcp index d212b9f75..3d5e736fe 100644 --- a/examples/snippets/wlan/http_client/http_client_soc.slcp +++ b/examples/snippets/wlan/http_client/http_client_soc.slcp @@ -12,7 +12,7 @@ filter: value: ["Beginner"] sdk: {id: simplicity_sdk, version: 2024.6.2} sdk_extension: -- {id: wiseconnect3_sdk, version: 3.3.3} +- {id: wiseconnect3_sdk, version: 3.3.4} source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/http_otaf/http_otaf_ncp.slcp b/examples/snippets/wlan/http_otaf/http_otaf_ncp.slcp index 7de3e9625..3f8c0df1d 100644 --- a/examples/snippets/wlan/http_otaf/http_otaf_ncp.slcp +++ b/examples/snippets/wlan/http_otaf/http_otaf_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/http_otaf/http_otaf_soc.slcp b/examples/snippets/wlan/http_otaf/http_otaf_soc.slcp index 23c6d4ecf..62ef3b05d 100644 --- a/examples/snippets/wlan/http_otaf/http_otaf_soc.slcp +++ b/examples/snippets/wlan/http_otaf/http_otaf_soc.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/http_otaf/http_otaf_uart_ncp.slcp b/examples/snippets/wlan/http_otaf/http_otaf_uart_ncp.slcp index 15ba24856..ec7d0e54a 100644 --- a/examples/snippets/wlan/http_otaf/http_otaf_uart_ncp.slcp +++ b/examples/snippets/wlan/http_otaf/http_otaf_uart_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/http_otaf_twt/http_otaf_twt_ncp.slcp b/examples/snippets/wlan/http_otaf_twt/http_otaf_twt_ncp.slcp index a4c6d1a54..4f8bdb177 100644 --- a/examples/snippets/wlan/http_otaf_twt/http_otaf_twt_ncp.slcp +++ b/examples/snippets/wlan/http_otaf_twt/http_otaf_twt_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/http_otaf_twt/http_otaf_twt_soc.slcp b/examples/snippets/wlan/http_otaf_twt/http_otaf_twt_soc.slcp index 0cc835479..0ae50a14c 100644 --- a/examples/snippets/wlan/http_otaf_twt/http_otaf_twt_soc.slcp +++ b/examples/snippets/wlan/http_otaf_twt/http_otaf_twt_soc.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/http_server/http_server_soc.slcp b/examples/snippets/wlan/http_server/http_server_soc.slcp index bf19a4a13..7bb8c79e8 100644 --- a/examples/snippets/wlan/http_server/http_server_soc.slcp +++ b/examples/snippets/wlan/http_server/http_server_soc.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/lwip_tcp_client/lwip_tcp_client_ncp.slcp b/examples/snippets/wlan/lwip_tcp_client/lwip_tcp_client_ncp.slcp index 3f941a355..4d46f8ae6 100644 --- a/examples/snippets/wlan/lwip_tcp_client/lwip_tcp_client_ncp.slcp +++ b/examples/snippets/wlan/lwip_tcp_client/lwip_tcp_client_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/lwip_tcp_client/lwip_tcp_client_soc.slcp b/examples/snippets/wlan/lwip_tcp_client/lwip_tcp_client_soc.slcp index 234308004..686aaa089 100644 --- a/examples/snippets/wlan/lwip_tcp_client/lwip_tcp_client_soc.slcp +++ b/examples/snippets/wlan/lwip_tcp_client/lwip_tcp_client_soc.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/lwip_tcp_client/lwip_tcp_client_uart_ncp.slcp b/examples/snippets/wlan/lwip_tcp_client/lwip_tcp_client_uart_ncp.slcp index 812066e46..896c61e0e 100644 --- a/examples/snippets/wlan/lwip_tcp_client/lwip_tcp_client_uart_ncp.slcp +++ b/examples/snippets/wlan/lwip_tcp_client/lwip_tcp_client_uart_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/m4_firmware_update/m4_firmware_update.slcp b/examples/snippets/wlan/m4_firmware_update/m4_firmware_update.slcp index 4d6bd8620..13936d1a1 100644 --- a/examples/snippets/wlan/m4_firmware_update/m4_firmware_update.slcp +++ b/examples/snippets/wlan/m4_firmware_update/m4_firmware_update.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/multithreading_application/multithreading_application_ncp.slcp b/examples/snippets/wlan/multithreading_application/multithreading_application_ncp.slcp index 4ce3f39e1..23e156364 100644 --- a/examples/snippets/wlan/multithreading_application/multithreading_application_ncp.slcp +++ b/examples/snippets/wlan/multithreading_application/multithreading_application_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/multithreading_application/multithreading_application_soc.slcp b/examples/snippets/wlan/multithreading_application/multithreading_application_soc.slcp index 7ec06663f..7b67e69ec 100644 --- a/examples/snippets/wlan/multithreading_application/multithreading_application_soc.slcp +++ b/examples/snippets/wlan/multithreading_application/multithreading_application_soc.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/select_app/select_app_ncp.slcp b/examples/snippets/wlan/select_app/select_app_ncp.slcp index 4ac9a7e9d..a37b46e71 100644 --- a/examples/snippets/wlan/select_app/select_app_ncp.slcp +++ b/examples/snippets/wlan/select_app/select_app_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/select_app/select_app_soc.slcp b/examples/snippets/wlan/select_app/select_app_soc.slcp index 0f1b6337e..e17321b58 100644 --- a/examples/snippets/wlan/select_app/select_app_soc.slcp +++ b/examples/snippets/wlan/select_app/select_app_soc.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/sntp_client/sntp_client_ncp.slcp b/examples/snippets/wlan/sntp_client/sntp_client_ncp.slcp index d522c8cf7..4d5eb5595 100644 --- a/examples/snippets/wlan/sntp_client/sntp_client_ncp.slcp +++ b/examples/snippets/wlan/sntp_client/sntp_client_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/sntp_client/sntp_client_soc.slcp b/examples/snippets/wlan/sntp_client/sntp_client_soc.slcp index e66247869..af807d2ec 100644 --- a/examples/snippets/wlan/sntp_client/sntp_client_soc.slcp +++ b/examples/snippets/wlan/sntp_client/sntp_client_soc.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/sntp_client/sntp_client_uart_ncp.slcp b/examples/snippets/wlan/sntp_client/sntp_client_uart_ncp.slcp index 3c0abbefc..d76c1c698 100644 --- a/examples/snippets/wlan/sntp_client/sntp_client_uart_ncp.slcp +++ b/examples/snippets/wlan/sntp_client/sntp_client_uart_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/station_ping/station_ping_ncp.slcp b/examples/snippets/wlan/station_ping/station_ping_ncp.slcp index 6f8495b17..f7d4a751a 100644 --- a/examples/snippets/wlan/station_ping/station_ping_ncp.slcp +++ b/examples/snippets/wlan/station_ping/station_ping_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/station_ping/station_ping_soc.slcp b/examples/snippets/wlan/station_ping/station_ping_soc.slcp index fbebde538..055c6d3c5 100644 --- a/examples/snippets/wlan/station_ping/station_ping_soc.slcp +++ b/examples/snippets/wlan/station_ping/station_ping_soc.slcp @@ -16,7 +16,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/station_ping/station_ping_uart_ncp.slcp b/examples/snippets/wlan/station_ping/station_ping_uart_ncp.slcp index bfb49f174..786684676 100644 --- a/examples/snippets/wlan/station_ping/station_ping_uart_ncp.slcp +++ b/examples/snippets/wlan/station_ping/station_ping_uart_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/station_ping_v6/station_ping_v6.slcp b/examples/snippets/wlan/station_ping_v6/station_ping_v6.slcp index 375d0cf15..15026e961 100644 --- a/examples/snippets/wlan/station_ping_v6/station_ping_v6.slcp +++ b/examples/snippets/wlan/station_ping_v6/station_ping_v6.slcp @@ -16,7 +16,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/tcp_tx_on_periodic_wakeup/tcp_tx_on_periodic_wakeup_ncp.slcp b/examples/snippets/wlan/tcp_tx_on_periodic_wakeup/tcp_tx_on_periodic_wakeup_ncp.slcp index 291b374e5..0910b2ecb 100644 --- a/examples/snippets/wlan/tcp_tx_on_periodic_wakeup/tcp_tx_on_periodic_wakeup_ncp.slcp +++ b/examples/snippets/wlan/tcp_tx_on_periodic_wakeup/tcp_tx_on_periodic_wakeup_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/tcp_tx_on_periodic_wakeup/tcp_tx_on_periodic_wakeup_soc.slcp b/examples/snippets/wlan/tcp_tx_on_periodic_wakeup/tcp_tx_on_periodic_wakeup_soc.slcp index 9636a39b6..52d8d67cc 100644 --- a/examples/snippets/wlan/tcp_tx_on_periodic_wakeup/tcp_tx_on_periodic_wakeup_soc.slcp +++ b/examples/snippets/wlan/tcp_tx_on_periodic_wakeup/tcp_tx_on_periodic_wakeup_soc.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/three_ssl_concurrent_client_sockets/three_ssl_client_sockets_ncp.slcp b/examples/snippets/wlan/three_ssl_concurrent_client_sockets/three_ssl_client_sockets_ncp.slcp index c6930663b..e9e309069 100644 --- a/examples/snippets/wlan/three_ssl_concurrent_client_sockets/three_ssl_client_sockets_ncp.slcp +++ b/examples/snippets/wlan/three_ssl_concurrent_client_sockets/three_ssl_client_sockets_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/three_ssl_concurrent_client_sockets/three_ssl_client_sockets_soc.slcp b/examples/snippets/wlan/three_ssl_concurrent_client_sockets/three_ssl_client_sockets_soc.slcp index a146986a3..4b99fe3c9 100644 --- a/examples/snippets/wlan/three_ssl_concurrent_client_sockets/three_ssl_client_sockets_soc.slcp +++ b/examples/snippets/wlan/three_ssl_concurrent_client_sockets/three_ssl_client_sockets_soc.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/tls_client/tls_client_ncp.slcp b/examples/snippets/wlan/tls_client/tls_client_ncp.slcp index 366f9e84c..b03cced06 100644 --- a/examples/snippets/wlan/tls_client/tls_client_ncp.slcp +++ b/examples/snippets/wlan/tls_client/tls_client_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/tls_client/tls_client_soc.slcp b/examples/snippets/wlan/tls_client/tls_client_soc.slcp index 9def3934c..4f0f0017c 100644 --- a/examples/snippets/wlan/tls_client/tls_client_soc.slcp +++ b/examples/snippets/wlan/tls_client/tls_client_soc.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/twt_use_case_remote_app/twt_use_case_remote_app_ncp.slcp b/examples/snippets/wlan/twt_use_case_remote_app/twt_use_case_remote_app_ncp.slcp index f3a073948..ad158d6d0 100644 --- a/examples/snippets/wlan/twt_use_case_remote_app/twt_use_case_remote_app_ncp.slcp +++ b/examples/snippets/wlan/twt_use_case_remote_app/twt_use_case_remote_app_ncp.slcp @@ -16,7 +16,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/twt_use_case_remote_app/twt_use_case_remote_app_soc.slcp b/examples/snippets/wlan/twt_use_case_remote_app/twt_use_case_remote_app_soc.slcp index 51347597d..01b12cbe9 100644 --- a/examples/snippets/wlan/twt_use_case_remote_app/twt_use_case_remote_app_soc.slcp +++ b/examples/snippets/wlan/twt_use_case_remote_app/twt_use_case_remote_app_soc.slcp @@ -16,7 +16,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/user_gain_table/user_gain_table_ncp.slcp b/examples/snippets/wlan/user_gain_table/user_gain_table_ncp.slcp index 74101a086..7ebefb2e9 100644 --- a/examples/snippets/wlan/user_gain_table/user_gain_table_ncp.slcp +++ b/examples/snippets/wlan/user_gain_table/user_gain_table_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/user_gain_table/user_gain_table_soc.slcp b/examples/snippets/wlan/user_gain_table/user_gain_table_soc.slcp index e8d32229e..32be22977 100644 --- a/examples/snippets/wlan/user_gain_table/user_gain_table_soc.slcp +++ b/examples/snippets/wlan/user_gain_table/user_gain_table_soc.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/user_gain_table/user_gain_table_uart_ncp.slcp b/examples/snippets/wlan/user_gain_table/user_gain_table_uart_ncp.slcp index 73cbd061c..02e167e62 100644 --- a/examples/snippets/wlan/user_gain_table/user_gain_table_uart_ncp.slcp +++ b/examples/snippets/wlan/user_gain_table/user_gain_table_uart_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/wifi6_twt_use_case_demo/wifi6_twt_use_case_demo_ncp.slcp b/examples/snippets/wlan/wifi6_twt_use_case_demo/wifi6_twt_use_case_demo_ncp.slcp index 40e797451..fe99f7966 100644 --- a/examples/snippets/wlan/wifi6_twt_use_case_demo/wifi6_twt_use_case_demo_ncp.slcp +++ b/examples/snippets/wlan/wifi6_twt_use_case_demo/wifi6_twt_use_case_demo_ncp.slcp @@ -16,7 +16,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/wifi6_twt_use_case_demo/wifi6_twt_use_case_demo_soc.slcp b/examples/snippets/wlan/wifi6_twt_use_case_demo/wifi6_twt_use_case_demo_soc.slcp index a41e00199..06f571b4b 100644 --- a/examples/snippets/wlan/wifi6_twt_use_case_demo/wifi6_twt_use_case_demo_soc.slcp +++ b/examples/snippets/wlan/wifi6_twt_use_case_demo/wifi6_twt_use_case_demo_soc.slcp @@ -16,7 +16,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/wifi6_twt_use_case_demo/wifi6_twt_use_case_demo_uart_ncp.slcp b/examples/snippets/wlan/wifi6_twt_use_case_demo/wifi6_twt_use_case_demo_uart_ncp.slcp index 45cd21d0a..e70150cf6 100644 --- a/examples/snippets/wlan/wifi6_twt_use_case_demo/wifi6_twt_use_case_demo_uart_ncp.slcp +++ b/examples/snippets/wlan/wifi6_twt_use_case_demo/wifi6_twt_use_case_demo_uart_ncp.slcp @@ -16,7 +16,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/wlan_rf_test/wlan_rf_test_ncp.slcp b/examples/snippets/wlan/wlan_rf_test/wlan_rf_test_ncp.slcp index 92539a234..e7efb1483 100644 --- a/examples/snippets/wlan/wlan_rf_test/wlan_rf_test_ncp.slcp +++ b/examples/snippets/wlan/wlan_rf_test/wlan_rf_test_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/wlan_rf_test/wlan_rf_test_soc.slcp b/examples/snippets/wlan/wlan_rf_test/wlan_rf_test_soc.slcp index 05c129683..2c5422626 100644 --- a/examples/snippets/wlan/wlan_rf_test/wlan_rf_test_soc.slcp +++ b/examples/snippets/wlan/wlan_rf_test/wlan_rf_test_soc.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/wlan_rf_test/wlan_rf_test_uart_ncp.slcp b/examples/snippets/wlan/wlan_rf_test/wlan_rf_test_uart_ncp.slcp index 8972b17bb..4049e1572 100644 --- a/examples/snippets/wlan/wlan_rf_test/wlan_rf_test_uart_ncp.slcp +++ b/examples/snippets/wlan/wlan_rf_test/wlan_rf_test_uart_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/wlan_throughput_v6/wlan_throughput_v6_ncp.slcp b/examples/snippets/wlan/wlan_throughput_v6/wlan_throughput_v6_ncp.slcp index 2014c705d..79beceb76 100644 --- a/examples/snippets/wlan/wlan_throughput_v6/wlan_throughput_v6_ncp.slcp +++ b/examples/snippets/wlan/wlan_throughput_v6/wlan_throughput_v6_ncp.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan/wlan_throughput_v6/wlan_throughput_v6_soc.slcp b/examples/snippets/wlan/wlan_throughput_v6/wlan_throughput_v6_soc.slcp index 0efb4469e..30ac5a7ab 100644 --- a/examples/snippets/wlan/wlan_throughput_v6/wlan_throughput_v6_soc.slcp +++ b/examples/snippets/wlan/wlan_throughput_v6/wlan_throughput_v6_soc.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan_ble/out_of_box_demo/out_of_box_demo.slcp b/examples/snippets/wlan_ble/out_of_box_demo/out_of_box_demo.slcp index e622aa9ae..e15ec1679 100644 --- a/examples/snippets/wlan_ble/out_of_box_demo/out_of_box_demo.slcp +++ b/examples/snippets/wlan_ble/out_of_box_demo/out_of_box_demo.slcp @@ -12,7 +12,7 @@ filter: value: ["Intermediate"] sdk: {id: simplicity_sdk, version: 2024.6.2} sdk_extension: -- {id: wiseconnect3_sdk, version: 3.3.3} +- {id: wiseconnect3_sdk, version: 3.3.4} source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan_ble/wifi_https_ble_dual_role/wifi_https_ble_dual_role_ncp.slcp b/examples/snippets/wlan_ble/wifi_https_ble_dual_role/wifi_https_ble_dual_role_ncp.slcp index 6a74e4e72..32337c478 100644 --- a/examples/snippets/wlan_ble/wifi_https_ble_dual_role/wifi_https_ble_dual_role_ncp.slcp +++ b/examples/snippets/wlan_ble/wifi_https_ble_dual_role/wifi_https_ble_dual_role_ncp.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan_ble/wifi_https_ble_dual_role/wifi_https_ble_dual_role_soc.slcp b/examples/snippets/wlan_ble/wifi_https_ble_dual_role/wifi_https_ble_dual_role_soc.slcp index de8a09d72..4a95e373e 100644 --- a/examples/snippets/wlan_ble/wifi_https_ble_dual_role/wifi_https_ble_dual_role_soc.slcp +++ b/examples/snippets/wlan_ble/wifi_https_ble_dual_role/wifi_https_ble_dual_role_soc.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan_ble/wifi_station_ble_provisioning/wifi_station_ble_provisioning_ncp.slcp b/examples/snippets/wlan_ble/wifi_station_ble_provisioning/wifi_station_ble_provisioning_ncp.slcp index d5d2d35e2..7f8644db7 100644 --- a/examples/snippets/wlan_ble/wifi_station_ble_provisioning/wifi_station_ble_provisioning_ncp.slcp +++ b/examples/snippets/wlan_ble/wifi_station_ble_provisioning/wifi_station_ble_provisioning_ncp.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan_ble/wifi_station_ble_provisioning/wifi_station_ble_provisioning_soc.slcp b/examples/snippets/wlan_ble/wifi_station_ble_provisioning/wifi_station_ble_provisioning_soc.slcp index 4e443c19f..7f266eb67 100644 --- a/examples/snippets/wlan_ble/wifi_station_ble_provisioning/wifi_station_ble_provisioning_soc.slcp +++ b/examples/snippets/wlan_ble/wifi_station_ble_provisioning/wifi_station_ble_provisioning_soc.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan_ble/wifi_station_ble_provisioning_aws/wifi_station_ble_provisioning_aws_ncp.slcp b/examples/snippets/wlan_ble/wifi_station_ble_provisioning_aws/wifi_station_ble_provisioning_aws_ncp.slcp index 743b89537..06b729801 100644 --- a/examples/snippets/wlan_ble/wifi_station_ble_provisioning_aws/wifi_station_ble_provisioning_aws_ncp.slcp +++ b/examples/snippets/wlan_ble/wifi_station_ble_provisioning_aws/wifi_station_ble_provisioning_aws_ncp.slcp @@ -20,7 +20,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan_ble/wifi_station_ble_provisioning_aws/wifi_station_ble_provisioning_aws_soc.slcp b/examples/snippets/wlan_ble/wifi_station_ble_provisioning_aws/wifi_station_ble_provisioning_aws_soc.slcp index c86bd30a0..2c6338665 100644 --- a/examples/snippets/wlan_ble/wifi_station_ble_provisioning_aws/wifi_station_ble_provisioning_aws_soc.slcp +++ b/examples/snippets/wlan_ble/wifi_station_ble_provisioning_aws/wifi_station_ble_provisioning_aws_soc.slcp @@ -20,7 +20,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan_ble/wifi_station_ble_provisioning_aws/wifi_station_ble_provisioning_aws_uart_ncp.slcp b/examples/snippets/wlan_ble/wifi_station_ble_provisioning_aws/wifi_station_ble_provisioning_aws_uart_ncp.slcp index 9341f7324..d590a05cd 100644 --- a/examples/snippets/wlan_ble/wifi_station_ble_provisioning_aws/wifi_station_ble_provisioning_aws_uart_ncp.slcp +++ b/examples/snippets/wlan_ble/wifi_station_ble_provisioning_aws/wifi_station_ble_provisioning_aws_uart_ncp.slcp @@ -20,7 +20,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan_ble/wifi_station_ble_throughput_app/wifi_station_ble_throughput_app_ncp.slcp b/examples/snippets/wlan_ble/wifi_station_ble_throughput_app/wifi_station_ble_throughput_app_ncp.slcp index 1e7a52ee6..0f6103847 100644 --- a/examples/snippets/wlan_ble/wifi_station_ble_throughput_app/wifi_station_ble_throughput_app_ncp.slcp +++ b/examples/snippets/wlan_ble/wifi_station_ble_throughput_app/wifi_station_ble_throughput_app_ncp.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan_ble/wifi_station_ble_throughput_app/wifi_station_ble_throughput_app_soc.slcp b/examples/snippets/wlan_ble/wifi_station_ble_throughput_app/wifi_station_ble_throughput_app_soc.slcp index d0a6e7152..5c05463a4 100644 --- a/examples/snippets/wlan_ble/wifi_station_ble_throughput_app/wifi_station_ble_throughput_app_soc.slcp +++ b/examples/snippets/wlan_ble/wifi_station_ble_throughput_app/wifi_station_ble_throughput_app_soc.slcp @@ -17,7 +17,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan_ble/wifi_throughput_ble_dual_role/wifi_throughput_ble_dual_role_ncp.slcp b/examples/snippets/wlan_ble/wifi_throughput_ble_dual_role/wifi_throughput_ble_dual_role_ncp.slcp index 7b795deef..d2bd0548a 100644 --- a/examples/snippets/wlan_ble/wifi_throughput_ble_dual_role/wifi_throughput_ble_dual_role_ncp.slcp +++ b/examples/snippets/wlan_ble/wifi_throughput_ble_dual_role/wifi_throughput_ble_dual_role_ncp.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/examples/snippets/wlan_ble/wifi_throughput_ble_dual_role/wifi_throughput_ble_dual_role_soc.slcp b/examples/snippets/wlan_ble/wifi_throughput_ble_dual_role/wifi_throughput_ble_dual_role_soc.slcp index b4e3b947b..13f56e9bb 100644 --- a/examples/snippets/wlan_ble/wifi_throughput_ble_dual_role/wifi_throughput_ble_dual_role_soc.slcp +++ b/examples/snippets/wlan_ble/wifi_throughput_ble_dual_role/wifi_throughput_ble_dual_role_soc.slcp @@ -18,7 +18,7 @@ sdk: version: 2024.6.2 sdk_extension: - id: wiseconnect3_sdk - version: 3.3.3 + version: 3.3.4 source: - path: app.c - path: main.c diff --git a/wiseconnect3.slce b/wiseconnect3.slce index 04c23b84c..2336bbe9f 100644 --- a/wiseconnect3.slce +++ b/wiseconnect3.slce @@ -2,13 +2,13 @@ id: wiseconnect3_sdk label: WiSeConnect 3 SDK description: > WiSeConnect 3 extension for the Simplicity SDK (formerly Gecko SDK) -version: "3.3.3" +version: "3.3.4" sdk: id: simplicity_sdk version: "2024.6.2" documentation: - docset: wiseconnect - version: "3.3.3" + version: "3.3.4" component_path: - path: resources - path: components/board diff --git a/wiseconnect3.slsdk b/wiseconnect3.slsdk index dc5460f98..0e5fa6f92 100644 --- a/wiseconnect3.slsdk +++ b/wiseconnect3.slsdk @@ -1,12 +1,12 @@ # Properties file for Simplicity Studio metadata id=uc.extension.wiseconnect3_sdk -version=3.3.3 +version=3.3.4 label=WiSeConnect 3 description=WiSeConnect 3 SDK -prop.subLabel=Wi-Fi\\ SDK\\ 3.3.3 +prop.subLabel=Wi-Fi\\ SDK\\ 3.3.4 prop.file.templatesFile=wifi_templates.xml wifi_internal_templates.xml diff --git a/wiseconnect3_demos.xml b/wiseconnect3_demos.xml index 2a1714898..efeeba8c4 100644 --- a/wiseconnect3_demos.xml +++ b/wiseconnect3_demos.xml @@ -5,8 +5,8 @@ - - + + @@ -17,8 +17,8 @@ - - + + @@ -29,8 +29,8 @@ - - + + @@ -41,8 +41,8 @@ - - + + @@ -53,8 +53,8 @@ - - + + @@ -65,8 +65,8 @@ - - + + diff --git a/wiseconnect3_docs.xml b/wiseconnect3_docs.xml index 08383627e..1263a5763 100644 --- a/wiseconnect3_docs.xml +++ b/wiseconnect3_docs.xml @@ -1,7 +1,7 @@ - + @@ -9,7 +9,7 @@ Get started with developing an application for the SiWx91x™ chipset family using the WiSeConnect™ SDK v3.x with an EFR32™ host in Network Co-Processor (NCP) mode, where the application runs on the EFR32 host and the connectivity stack runs on the SiWx91x chipset. - + @@ -17,7 +17,7 @@ Release Notes for the WiSeConnect 3 SDK for NCP mode development. These release notes provide information on the release including part compatibility, changes, and supported features. - + @@ -35,7 +35,7 @@ Glossary of commonly used terms in the SiWx91x™ documentation. - + @@ -86,7 +86,7 @@ - Guide for updating an existing application using the WiSeConnect™ SDK v3.2.0 to a v3.3.0 application. This guide describes the naming and interface changes in v3.2.0, mostly in order to standardize the names and improve the overall usage experience of the application programming interface (API). Migration requires the names everywhere to be updated in the existing code of an application. + Guide for updating an existing application using the WiSeConnect™ SDK v3.2.0 to a v3.3.0 application. This guide describes the naming and interface changes in v3.3.0, mostly in order to standardize the names and improve the overall usage experience of the application programming interface (API). Migration requires the names everywhere to be updated in the existing code of an application. @@ -95,7 +95,7 @@ - Guide for updating an existing application using the WiSeConnect™ SDK v3.3.0 to a v3.3.1 application. This guide describes the naming and interface changes in v3.3.0, mostly in order to standardize the names and improve the overall usage experience of the application programming interface (API). Migration requires the names everywhere to be updated in the existing code of an application. + Guide for updating an existing application using the WiSeConnect™ SDK v3.3.0 to a v3.3.1 application. This guide describes the naming and interface changes in v3.3.1, mostly in order to standardize the names and improve the overall usage experience of the application programming interface (API). Migration requires the names everywhere to be updated in the existing code of an application. @@ -107,7 +107,7 @@ Guide for updating an existing application using the WiSeConnect™ SDK v3.3.2 to a v3.3.3 application. This guide describes the naming and interface changes in v3.3.3, mostly in order to standardize the names and improve the overall usage experience of the application programming interface (API). Migration requires the names everywhere to be updated in the existing code of an application. - + @@ -116,7 +116,7 @@ This reference manual provides information about the software on the SiWx917™, the first chip in the SiWx91x™ chipset family. It is intended to provide all the details required for a smooth developer experience. - + @@ -125,7 +125,7 @@ Guide to the application programming interface (API) of the WiSeConnect™ SDK v3.x, providing details of the functions, data types, constants, and callback frameworks within the various categories of APIs provided by the WiSeConnect™ SDK v3.x. - +