diff --git a/README.md b/README.md index ca56081ee..44e155a0b 100644 --- a/README.md +++ b/README.md @@ -28,7 +28,7 @@ The online WiSeConnect 3 SDK documentation is available [here](https://docs.sila - See the [Getting Started](https://docs.silabs.com/wiseconnect/latest/wiseconnect-getting-started) section to run your first example. - See the [Examples](https://docs.silabs.com/wiseconnect/latest/wiseconnect-examples) section to explore all the available examples. - - See our [Migration Guide](docs/software-reference/developer-guides/migrating-from-v3-2-0.md) for information on porting your WiSeConnect v3.2.0 application to WiSeConnect v3.3.0 + - See our [Migration Guide](docs/software-reference/developer-guides/migrating-from-v3-3-0.md) for information on porting your WiSeConnect v3.3.0 application to WiSeConnect v3.3.1 - [API Reference Guide](https://docs.silabs.com/wiseconnect/latest/wiseconnect-api-reference-guide-summary) - [SiWx917 Software Reference Manual](docs/software-reference/manuals/siwx91x-software-reference-manual.md) - [SiWG917 – TA Flash Memory Map Change Guide](https://www.silabs.com/Wi-Fi_H&L_Apps/Wi-Fi_H&L_Apps_SoC/SiWG917%E2%80%93TA_Flash_Memory_Map_Change_Guide_v1.3.pdf) diff --git a/components/board/silabs/component/brd2605a_config.slcc b/components/board/silabs/component/brd2605a_config.slcc index 5bd3aeafd..43eed5b08 100644 --- a/components/board/silabs/component/brd2605a_config.slcc +++ b/components/board/silabs/component/brd2605a_config.slcc @@ -166,4 +166,8 @@ - override: component: "%extension-wiseconnect3_sdk%board_configuration_headers" file_id: sl_board_control - path: brd2605a/sl_board_control.h \ No newline at end of file + path: brd2605a/sl_board_control.h + - override: + component: "%extension-wiseconnect3_sdk%board_configuration_headers" + file_id: pin_config + path: brd2605a/pin_config.h \ No newline at end of file diff --git a/components/board/silabs/component/brd4325f.slcc b/components/board/silabs/component/brd4325f.slcc index c66541783..610170dc0 100644 --- a/components/board/silabs/component/brd4325f.slcc +++ b/components/board/silabs/component/brd4325f.slcc @@ -37,34 +37,34 @@ - template_contribution: # Default Memory configuration - name: device_flash_addr - value: 136060928 # 0x081C 2000 + value: 136323072 # 0x0820 2000 priority: -1 condition: - si917_mem_config_1 - name: device_flash_size - value: 450560 # 0x0006 E000 + value: 2088960 # 0x001F E000 priority: -1 condition: - si917_mem_config_1 # Medium Memory configuration - name: device_flash_addr - value: 136060928 # 0x081C 2000 + value: 136323072 # 0x0820 2000 priority: -1 condition: - si917_mem_config_2 - name: device_flash_size - value: 450560 # 0x0006 E000 + value: 2088960 # 0x001F E000 priority: -1 condition: - si917_mem_config_2 # Advanced Memory configuration - name: device_flash_addr - value: 136060928 # 0x081C 2000 + value: 136323072 # 0x0820 2000 priority: -1 condition: - si917_mem_config_3 - name: device_flash_size - value: 450560 # 0x0006 E000 + value: 2088960 # 0x001F E000 priority: -1 condition: - si917_mem_config_3 diff --git a/components/board/silabs/component/brd4338a_config.slcc b/components/board/silabs/component/brd4338a_config.slcc index 60f68f689..5afc9136e 100644 --- a/components/board/silabs/component/brd4338a_config.slcc +++ b/components/board/silabs/component/brd4338a_config.slcc @@ -99,7 +99,7 @@ component: "%extension-wiseconnect3_sdk%pwm_instance" file_id: pwm_config instance: led0 - path: brd4338a/sl_si91x_pwm_init_led0_config.h + path: common_config/sl_si91x_pwm_init_led0_config.h - override: component: "%extension-wiseconnect3_sdk%pwm_instance" file_id: pwm_config diff --git a/components/board/silabs/component/brd4339a_config.slcc b/components/board/silabs/component/brd4339a_config.slcc index 9b8725d82..c7c64a313 100644 --- a/components/board/silabs/component/brd4339a_config.slcc +++ b/components/board/silabs/component/brd4339a_config.slcc @@ -166,4 +166,8 @@ - override: component: "%extension-wiseconnect3_sdk%board_configuration_headers" file_id: RTE_Device_917 - path: brd4339a/RTE_Device_917.h \ No newline at end of file + path: brd4339a/RTE_Device_917.h + - override: + component: "%extension-wiseconnect3_sdk%board_configuration_headers" + file_id: pin_config + path: brd4339a/pin_config.h \ No newline at end of file diff --git a/components/board/silabs/component/brd4340b.slcc b/components/board/silabs/component/brd4340b.slcc index 06a512e28..816300724 100644 --- a/components/board/silabs/component/brd4340b.slcc +++ b/components/board/silabs/component/brd4340b.slcc @@ -31,8 +31,6 @@ value: '"A01"' - name: SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER value: '1' - - name: SLI_SI91X_MCU_ENABLE_FLASH_BASED_EXECUTION - value: '1' - name: SLI_SI91X_MCU_CONFIG_RADIO_BOARD_VER2 value: '1' - name: SLI_SI91X_MCU_COMMON_FLASH_MODE @@ -41,34 +39,34 @@ - template_contribution: # Default Memory configuration - name: device_flash_addr - value: 136060928 # 0x081C 2000 + value: 136323072 # 0x0820 2000 priority: -1 condition: - si917_mem_config_1 - name: device_flash_size - value: 450560 # 0x0006 E000 + value: 2088960 # 0x001F E000 priority: -1 condition: - si917_mem_config_1 # Medium Memory configuration - name: device_flash_addr - value: 136060928 # 0x081C 2000 + value: 136323072 # 0x0820 2000 priority: -1 condition: - si917_mem_config_2 - name: device_flash_size - value: 450560 # 0x0006 E000 + value: 2088960 # 0x001F E000 priority: -1 condition: - si917_mem_config_2 # Advanced Memory configuration - name: device_flash_addr - value: 136060928 # 0x081C 2000 + value: 136323072 # 0x0820 2000 priority: -1 condition: - si917_mem_config_3 - name: device_flash_size - value: 450560 # 0x0006 E000 + value: 2088960 # 0x001F E000 priority: -1 condition: - si917_mem_config_3 diff --git a/components/board/silabs/component/brd4340b_config.slcc b/components/board/silabs/component/brd4340b_config.slcc index 299c91c48..6d48eba44 100644 --- a/components/board/silabs/component/brd4340b_config.slcc +++ b/components/board/silabs/component/brd4340b_config.slcc @@ -162,4 +162,8 @@ - override: component: "%extension-wiseconnect3_sdk%board_configuration_headers" file_id: sl_board_control - path: brd4340b/sl_board_control.h \ No newline at end of file + path: brd4340b/sl_board_control.h + - override: + component: "%extension-wiseconnect3_sdk%board_configuration_headers" + file_id: pin_config + path: brd4340b/pin_config.h \ No newline at end of file diff --git a/components/board/silabs/component/brd4341a.slcc b/components/board/silabs/component/brd4341a.slcc index 5aa839df7..6bfe6699c 100644 --- a/components/board/silabs/component/brd4341a.slcc +++ b/components/board/silabs/component/brd4341a.slcc @@ -39,34 +39,34 @@ - template_contribution: # Default Memory configuration - name: device_flash_addr - value: 136060928 # 0x081C 2000 + value: 136323072 # 0x0820 2000 priority: -1 condition: - si917_mem_config_1 - name: device_flash_size - value: 450560 # 0x0006 E000 + value: 2088960 # 0x001F E000 priority: -1 condition: - si917_mem_config_1 # Medium Memory configuration - name: device_flash_addr - value: 136060928 # 0x081C 2000 + value: 136323072 # 0x0820 2000 priority: -1 condition: - si917_mem_config_2 - name: device_flash_size - value: 450560 # 0x0006 E000 + value: 2088960 # 0x001F E000 priority: -1 condition: - si917_mem_config_2 # Advanced Memory configuration - name: device_flash_addr - value: 136060928 # 0x081C 2000 + value: 136323072 # 0x0820 2000 priority: -1 condition: - si917_mem_config_3 - name: device_flash_size - value: 450560 # 0x0006 E000 + value: 2088960 # 0x001F E000 priority: -1 condition: - si917_mem_config_3 diff --git a/components/board/silabs/component/brd4343a.slcc b/components/board/silabs/component/brd4343a.slcc index 408c548fa..f9cc2a67b 100644 --- a/components/board/silabs/component/brd4343a.slcc +++ b/components/board/silabs/component/brd4343a.slcc @@ -9,7 +9,7 @@ - ui_hints: visibility: never - requires: - - name: siwg917y111mgnb + - name: siwg917y111mgnba - name: brd4343a_config - name: hardware_board_mainboard - name: external_flash_none @@ -29,6 +29,8 @@ value: '"BRD4343A"' - name: SL_BOARD_REV value: '"A02"' + - name: SL_SI91X_MODULE_BOARD + value: '1' - name: SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER value: '1' - name: SLI_SI91X_MCU_CONFIG_RADIO_BOARD_VER2 @@ -74,7 +76,7 @@ - board:pn:BRD4343 - board:variant:A - board:revision:A02 - - board:device:siwg917y111mgnb + - board:device:siwg917y111mgnba - hardware:has:vcom # - hardware:has:pti # - hardware:has:led:2 diff --git a/components/board/silabs/component/brd4343a_config.slcc b/components/board/silabs/component/brd4343a_config.slcc index b73e36a98..1d5287b8f 100644 --- a/components/board/silabs/component/brd4343a_config.slcc +++ b/components/board/silabs/component/brd4343a_config.slcc @@ -162,4 +162,8 @@ - override: component: "%extension-wiseconnect3_sdk%board_configuration_headers" file_id: sl_board_control - path: brd4343a/sl_board_control.h \ No newline at end of file + path: brd4343a/sl_board_control.h + - override: + component: "%extension-wiseconnect3_sdk%board_configuration_headers" + file_id: pin_config + path: brd4343a/pin_config.h \ No newline at end of file diff --git a/components/board/silabs/component/brd4343b.slcc b/components/board/silabs/component/brd4343b.slcc index 023bdf83c..82ae674ba 100644 --- a/components/board/silabs/component/brd4343b.slcc +++ b/components/board/silabs/component/brd4343b.slcc @@ -29,6 +29,8 @@ value: '"BRD4343B"' - name: SL_BOARD_REV value: '"A02"' + - name: SL_SI91X_MODULE_BOARD + value: '1' - name: SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER value: '1' - name: SLI_SI91X_MCU_CONFIG_RADIO_BOARD_VER2 diff --git a/components/board/silabs/component/brd4343b_config.slcc b/components/board/silabs/component/brd4343b_config.slcc index 6d7304888..199d42521 100644 --- a/components/board/silabs/component/brd4343b_config.slcc +++ b/components/board/silabs/component/brd4343b_config.slcc @@ -162,4 +162,8 @@ - override: component: "%extension-wiseconnect3_sdk%board_configuration_headers" file_id: sl_board_control - path: brd4343b/sl_board_control.h \ No newline at end of file + path: brd4343b/sl_board_control.h + - override: + component: "%extension-wiseconnect3_sdk%board_configuration_headers" + file_id: pin_config + path: brd4343b/pin_config.h \ No newline at end of file diff --git a/components/board/silabs/component/brd4343q.slcc b/components/board/silabs/component/brd4343q.slcc new file mode 100644 index 000000000..dd2d84df9 --- /dev/null +++ b/components/board/silabs/component/brd4343q.slcc @@ -0,0 +1,87 @@ +!!omap +- id: brd4343q +- label: BRD4343Q +- package: platform +- description: Board support for BRD4343Q. +- category: Board|Radio Board +- quality: production +- root_path: components/board/silabs/config/brd4343q +- ui_hints: + visibility: never +- requires: + - name: siwg917y121mgnb + - name: brd4343q_config + - name: hardware_board_mainboard + - name: external_flash_none + - name: external_psram_none + - name: rsilib_board + - name: si91x_common_flash +- provides: + - name: brd4343q + - name: hardware_board + - name: hardware_board_rb + - name: hardware_board_supports_multi_slave + - name: si91x_b0_board +- recommends: + - id: brd4002a +- define: + - name: SL_BOARD_NAME + value: '"BRD4343Q"' + - name: SL_BOARD_REV + value: '"A02"' + - name: SL_SI91X_MODULE_BOARD + value: '1' + - name: SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER + value: '1' + - name: SLI_SI91X_MCU_CONFIG_RADIO_BOARD_VER2 + value: '1' + - name: SLI_SI91X_MCU_INTERNAL_LDO_FOR_PSRAM + value: '1' + - name: SLI_SI91X_MCU_COMMON_FLASH_MODE + value: '1' + +- template_contribution: + # Default Memory configuration + - name: device_flash_addr + value: 136323072 # 0x0820 2000 + priority: -1 + condition: + - si917_mem_config_1 + - name: device_flash_size + value: 2088960 # 0x001F E000 + priority: -1 + condition: + - si917_mem_config_1 + # Medium Memory configuration + - name: device_flash_addr + value: 136323072 # 0x0820 2000 + priority: -1 + condition: + - si917_mem_config_2 + - name: device_flash_size + value: 2088960 # 0x001F E000 + priority: -1 + condition: + - si917_mem_config_2 + # Advanced Memory configuration + - name: device_flash_addr + value: 136323072 # 0x0820 2000 + priority: -1 + condition: + - si917_mem_config_3 + - name: device_flash_size + value: 2088960 # 0x001F E000 + priority: -1 + condition: + - si917_mem_config_3 +- tag: + - board:pn:BRD4343 + - board:variant:Q + - board:revision:A00 + - board:device:siwg917y121mgnb + - hardware:has:vcom +# - hardware:has:pti +# - hardware:has:led:2 +# - hardware:has:button:2 +# - hardware:has:exp_header:uart +# - hardware:shares:button:led diff --git a/components/board/silabs/component/brd4343q_config.slcc b/components/board/silabs/component/brd4343q_config.slcc new file mode 100644 index 000000000..daf5edac0 --- /dev/null +++ b/components/board/silabs/component/brd4343q_config.slcc @@ -0,0 +1,179 @@ +!!omap +- id: brd4343q_config +- label: brd4343q config +- description: Configuration files for BRD4343Q +- package: platform +- category: Board|Configuration +- quality: production +- ui_hints: + visibility: never +- root_path: "components/board/silabs/config" +- provides: + - name: brd4343q_config +- config_file: + - override: + component: "%extension-wiseconnect3_sdk%board_configuration_headers" + file_id: RTE_Device_917 + path: brd4343q/RTE_Device_917.h + - override: + component: "%extension-wiseconnect3_sdk%adc_instance" + file_id: adc_config + instance: channel_1 + path: common_config/sl_si91x_adc_init_channel_1_config.h + - override: + component: "%extension-wiseconnect3_sdk%adc_instance" + file_id: adc_config + instance: channel_2 + path: common_config/sl_si91x_adc_init_channel_2_config.h + - override: + component: "%extension-wiseconnect3_sdk%adc_instance" + file_id: adc_config + instance: channel_3 + path: common_config/sl_si91x_adc_init_channel_3_config.h + - override: + component: "%extension-wiseconnect3_sdk%adc_instance" + file_id: adc_config + instance: channel_4 + path: common_config/sl_si91x_adc_init_channel_4_config.h + - override: + component: "%extension-wiseconnect3_sdk%adc_instance" + file_id: adc_config + instance: channel_5 + path: common_config/sl_si91x_adc_init_channel_5_config.h + - override: + component: "%extension-wiseconnect3_sdk%adc_instance" + file_id: adc_config + instance: channel_6 + path: common_config/sl_si91x_adc_init_channel_6_config.h + - override: + component: "%extension-wiseconnect3_sdk%adc_instance" + file_id: adc_config + instance: channel_7 + path: common_config/sl_si91x_adc_init_channel_7_config.h + - override: + component: "%extension-wiseconnect3_sdk%adc_instance" + file_id: adc_config + instance: channel_8 + path: common_config/sl_si91x_adc_init_channel_8_config.h + - override: + component: "%extension-wiseconnect3_sdk%adc_instance" + file_id: adc_config + instance: channel_9 + path: common_config/sl_si91x_adc_init_channel_9_config.h + - override: + component: "%extension-wiseconnect3_sdk%adc_instance" + file_id: adc_config + instance: channel_10 + path: common_config/sl_si91x_adc_init_channel_10_config.h + - override: + component: "%extension-wiseconnect3_sdk%adc_instance" + file_id: adc_config + instance: channel_11 + path: common_config/sl_si91x_adc_init_channel_11_config.h + - override: + component: "%extension-wiseconnect3_sdk%adc_instance" + file_id: adc_config + instance: channel_12 + path: common_config/sl_si91x_adc_init_channel_12_config.h + - override: + component: "%extension-wiseconnect3_sdk%adc_instance" + file_id: adc_config + instance: channel_13 + path: common_config/sl_si91x_adc_init_channel_13_config.h + - override: + component: "%extension-wiseconnect3_sdk%adc_instance" + file_id: adc_config + instance: channel_14 + path: common_config/sl_si91x_adc_init_channel_14_config.h + - override: + component: "%extension-wiseconnect3_sdk%adc_instance" + file_id: adc_config + instance: channel_15 + path: common_config/sl_si91x_adc_init_channel_15_config.h + - override: + component: "%extension-wiseconnect3_sdk%adc_instance" + file_id: adc_config + instance: channel_16 + path: common_config/sl_si91x_adc_init_channel_16_config.h + - override: + component: "%extension-wiseconnect3_sdk%pwm_instance" + file_id: pwm_config + instance: led0 + path: common_config/sl_si91x_pwm_init_led0_config.h + - override: + component: "%extension-wiseconnect3_sdk%pwm_instance" + file_id: pwm_config + instance: channel_0 + path: common_config/sl_si91x_pwm_init_channel_0_config.h + - override: + component: "%extension-wiseconnect3_sdk%pwm_instance" + file_id: pwm_config + instance: channel_1 + path: common_config/sl_si91x_pwm_init_channel_1_config.h + - override: + component: "%extension-wiseconnect3_sdk%pwm_instance" + file_id: pwm_config + instance: channel_2 + path: common_config/sl_si91x_pwm_init_channel_2_config.h + - override: + component: "%extension-wiseconnect3_sdk%pwm_instance" + file_id: pwm_config + instance: channel_3 + path: common_config/sl_si91x_pwm_init_channel_3_config.h + - override: + component: "%extension-wiseconnect3_sdk%i2c_instance" + file_id: i2c_config + instance: i2c0 + path: common_config/sl_si91x_i2c_init_i2c0_config.h + - override: + component: "%extension-wiseconnect3_sdk%i2c_instance" + file_id: i2c_config + instance: i2c1 + path: common_config/sl_si91x_i2c_init_i2c1_config.h + - override: + component: "%extension-wiseconnect3_sdk%i2c_instance" + file_id: i2c_config + instance: i2c2 + path: common_config/sl_si91x_i2c_init_i2c2_config.h + - override: + component: "%extension-wiseconnect3_sdk%ulp_timers_instance" + file_id: ulp_timer_config + instance: timer0 + path: common_config/sl_si91x_ulp_timer_init_timer0_config.h + - override: + component: "%extension-wiseconnect3_sdk%ulp_timers_instance" + file_id: ulp_timer_config + instance: timer1 + path: common_config/sl_si91x_ulp_timer_init_timer1_config.h + - override: + component: "%extension-wiseconnect3_sdk%ulp_timers_instance" + file_id: ulp_timer_config + instance: timer2 + path: common_config/sl_si91x_ulp_timer_init_timer2_config.h + - override: + component: "%extension-wiseconnect3_sdk%ulp_timers_instance" + file_id: ulp_timer_config + instance: timer3 + path: common_config/sl_si91x_ulp_timer_init_timer3_config.h + - override: + component: "%extension-wiseconnect3_sdk%board_configuration_headers" + file_id: sl_board_configuration + path: brd4343q/sl_board_configuration.h + - override: + component: "%extension-wiseconnect3_sdk%board_configuration_headers" + file_id: sl_board_control + path: brd4343q/sl_board_control.h + - override: + component: "%extension-wiseconnect3_sdk%board_configuration_headers" + file_id: pin_config + path: brd4343q/pin_config.h + - override: + component: "%extension-wiseconnect3_sdk%analog_comparator_instance" + file_id: analog_comparator_config + instance: comparator1 + path: common_config/sl_si91x_analog_comparator_comparator1_config.h + - override: + component: "%extension-wiseconnect3_sdk%analog_comparator_instance" + file_id: analog_comparator_config + instance: comparator2 + path: common_config/sl_si91x_analog_comparator_comparator2_config.h \ No newline at end of file diff --git a/components/board/silabs/config/brd2605a/RTE_Device_917.h b/components/board/silabs/config/brd2605a/RTE_Device_917.h index ae31db973..61ade5b1d 100644 --- a/components/board/silabs/config/brd2605a/RTE_Device_917.h +++ b/components/board/silabs/config/brd2605a/RTE_Device_917.h @@ -17,7 +17,7 @@ * * 3. This notice may not be removed or altered from any source distribution. * - * $Date: 4 January 2024 + * $Date: 1. June 2024 * $Revision: V2.4.4 * * Project: RTE Device Configuration for Si91x 2.0 B0 BRD2605A @@ -28,6 +28,7 @@ #ifndef __RTE_DEVICE_H #define __RTE_DEVICE_H #include "rsi_ccp_user_config.h" +#include "pin_config.h" #define GPIO_PORT_0 0 // GPIO port 0 #define ULP_GPIO_MODE_6 6 // ULP GPIO mode 6 @@ -37,29 +38,34 @@ #define BUTTON_0_GPIO_PIN 2 +#define SI917_DEVKIT + #define RTE_BUTTON0_PORT 0 #define RTE_BUTTON0_NUMBER 0 #define RTE_BUTTON0_PIN (2U) -#define RTE_BUTTON1_PORT 0 +#define RTE_BUTTON1_PORT 3 #define RTE_BUTTON1_NUMBER 1 -#define RTE_BUTTON1_PIN (11U) -#define RTE_BUTTON1_PAD 6 - -#define RTE_LED0_PORT 3 -#define RTE_LED0_NUMBER 0 -#define RTE_LED0_PIN 2 -#define RTE_LED0_PAD 14 - -#define RTE_LED1_PORT 3 -#define RTE_LED1_NUMBER 1 -#define RTE_LED1_PIN 3 -#define RTE_LED1_PAD 15 - -#define RTE_LED2_PORT 0 -#define RTE_LED2_NUMBER 2 -#define RTE_LED2_PIN 15 -#define RTE_LED2_PAD 8 +#define RTE_BUTTON1_PIN (1U) +#define RTE_BUTTON1_PAD 13 + +// RED LED +#define RTE_LEDR_PORT 3 +#define RTE_LEDR_NUMBER 0 +#define RTE_LEDR_PIN 2 +#define RTE_LEDR_PAD 14 + +// GREEN LED +#define RTE_LEDG_PORT 3 +#define RTE_LEDG_NUMBER 1 +#define RTE_LEDG_PIN 3 +#define RTE_LEDG_PAD 15 + +//BLUE LED +#define RTE_LEDB_PORT 0 +#define RTE_LEDB_NUMBER 2 +#define RTE_LEDB_PIN 15 +#define RTE_LEDB_PAD 8 // USART0 [Driver_USART0] // Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART @@ -67,7 +73,7 @@ #define RTE_USART0 1 -#define RTE_USART0_CLK_SRC USART_INTFPLLCLK +#define RTE_USART0_CLK_SRC USART_ULPREFCLK #define RTE_USART0_CLK_DIV_FACT 1 #define RTE_USART0_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER @@ -91,6 +97,7 @@ // USART0_CLK <0=>P0_8 <1=>P0_25 <2=>P0_52 <3=>P0_64 // CLK of USART0 +#ifndef USART0_CLK_LOC #define RTE_USART0_CLK_PORT_ID 0 #if (RTE_USART0_CLK_PORT_ID == 0) @@ -111,10 +118,35 @@ #else #error "Invalid USART0 RTE_USART0_CLK_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_CLK_PORT USART0_CLK_PORT +#if (USART0_CLK_LOC == 0) +#define RTE_USART0_CLK_PIN USART0_CLK_PIN +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 3 +#endif +#if (USART0_CLK_LOC == 1) +#define RTE_USART0_CLK_PIN USART0_CLK_PIN +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 0 //NO PAD +#endif +#if (USART0_CLK_LOC == 2) +#define RTE_USART0_CLK_PIN USART0_CLK_PIN +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 16 +#endif +#if (USART0_CLK_LOC == 3) +#define RTE_USART0_CLK_PIN (USART0_CLK_PIN + GPIO_MAX_PIN) +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 22 +#endif +//Pintool data +#endif // USART0_TX <0=>P0_15 <1=>P0_30 <2=>P0_54 <3=>P0_68 <4=>P0_71 // TX for USART0 - +#ifndef USART0_TX_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_USART0_TX_PORT_ID 1 #else @@ -144,10 +176,40 @@ #else #error "Invalid USART0 RTE_USART0_TX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_TX_PORT USART0_TX_PORT +#if (USART0_TX_LOC == 4) +#define RTE_USART0_TX_PIN USART0_TX_PIN +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 8 +#endif +#if (USART0_TX_LOC == 5) +#define RTE_USART0_TX_PIN USART0_TX_PIN +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 0 //NO PAD +#endif +#if (USART0_TX_LOC == 6) +#define RTE_USART0_TX_PIN USART0_TX_PIN +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 18 +#endif +#if (USART0_TX_LOC == 7) +#define RTE_USART0_TX_PIN (USART0_TX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 26 +#endif +#if (USART0_TX_LOC == 8) +#define RTE_USART0_TX_PIN (USART0_TX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_TX_MUX 4 +#define RTE_USART0_TX_PAD 29 +#endif +//Pintool data +#endif // USART0_RX <0=>P0_10 <1=>P0_29 <2=>P0_55 <3=>P0_65 <4=>P0_70 // RX for USART0 - +#ifndef USART0_RX_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_USART0_RX_PORT_ID 1 #else @@ -173,7 +235,7 @@ #define RTE_USART0_RX_PORT 0 #define RTE_USART0_RX_PIN 65 #define RTE_USART0_RX_MUX 2 -#define RTE_USART0_RX_PAD 24 +#define RTE_USART0_RX_PAD 23 #elif (RTE_USART0_RX_PORT_ID == 4) #define RTE_USART0_RX_PORT 0 #define RTE_USART0_RX_PIN 70 @@ -182,9 +244,40 @@ #else #error "Invalid USART0 RTE_USART0_RX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_RX_PORT USART0_RX_PORT +#if (USART0_RX_LOC == 9) +#define RTE_USART0_RX_PIN USART0_RX_PIN +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 5 +#endif +#if (USART0_RX_LOC == 10) +#define RTE_USART0_RX_PIN USART0_RX_PIN +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 0 //no pad +#endif +#if (USART0_RX_LOC == 11) +#define RTE_USART0_RX_PIN USART0_RX_PIN +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 19 +#endif +#if (USART0_RX_LOC == 12) +#define RTE_USART0_RX_PIN (USART0_RX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 23 +#endif +#if (USART0_RX_LOC == 13) +#define RTE_USART0_RX_PIN (USART0_RX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_RX_MUX 4 +#define RTE_USART0_RX_PAD 28 +#endif +//Pintool data +#endif // USART0_CTS <0=>P0_6 <1=>P0_26 <2=>P0_56 <3=>P0_70 // CTS for USART0 +#ifndef USART0_CTS_LOC #define RTE_USART0_CTS_PORT_ID 0 #if (RTE_USART0_CTS_PORT_ID == 0) @@ -210,9 +303,35 @@ #else #error "Invalid USART0 RTE_USART0_CTS_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_CTS_PORT USART0_CTS_PORT +#if (USART0_CTS_LOC == 14) +#define RTE_USART0_CTS_PIN USART0_CTS_PIN +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 1 +#endif +#if (USART0_CTS_LOC == 15) +#define RTE_USART0_CTS_PIN USART0_CTS_PIN +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 0 //NO PAD +#endif +#if (USART0_CTS_LOC == 16) +#define RTE_USART0_CTS_PIN USART0_CTS_PIN +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 20 +#endif +#if (USART0_CTS_LOC == 17) +#define RTE_USART0_CTS_PIN (USART0_CTS_PIN + GPIO_MAX_PIN) +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 28 +#endif +//Pintool data +#endif // USART0_RTS <0=>P0_9 <1=>P0_28 <2=>P0_53 <3=>P0_69 // RTS for USART0 +#ifndef USART0_RTS_LOC #define RTE_USART0_RTS_PORT_ID 0 #if (RTE_USART0_RTS_PORT_ID == 0) @@ -233,10 +352,35 @@ #else #error "Invalid USART0 RTE_USART0_RTS_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_RTS_PORT USART0_RTS_PORT +#if (USART0_RTS_LOC == 18) +#define RTE_USART0_RTS_PIN USART0_RTS_PIN +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 4 +#endif +#if (USART0_RTS_LOC == 19) +#define RTE_USART0_RTS_PIN USART0_RTS_PIN +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 0 //NO PAD +#endif +#if (USART0_RTS_LOC == 20) +#define RTE_USART0_RTS_PIN USART0_RTS_PIN +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 17 +#endif +#if (USART0_RTS_LOC == 21) +#define RTE_USART0_RTS_PIN (USART0_RTS_PIN + GPIO_MAX_PIN) +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 27 +#endif +//Pintool data +#endif // USART0_IR_TX <0=>P0_48 <1=>P0_72 // IR TX for USART0 - +#ifndef USART0_IRTX_LOC #define RTE_IR_TX_PORT_ID 0 #if ((RTE_IR_TX_PORT_ID == 2)) #error "Invalid USART0 RTE_USART0_IR_TX_PIN Pin Configuration!" @@ -260,10 +404,35 @@ #else #error "Invalid USART0 RTE_USART0_IR_TX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_IR_TX_PORT USART0_IRTX_PORT +#if (USART0_IRTX_LOC == 22) +#define RTE_USART0_IR_TX_PIN USART0_IRTX_PIN +#define RTE_USART0_IR_TX_MUX 13 +#define RTE_USART0_IR_TX_PAD 0 //No pad +#endif +#if (USART0_IRTX_LOC == 23) +#define RTE_USART0_IR_TX_PIN USART0_IRTX_PIN +#define RTE_USART0_IR_TX_MUX 2 +#define RTE_USART0_IR_TX_PAD 12 +#endif +#if (USART0_IRTX_LOC == 24) +#define RTE_USART0_IR_TX_PIN (USART0_IRTX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_IR_TX_MUX 11 +#define RTE_USART0_IR_TX_PAD 23 +#endif +#if (USART0_IRTX_LOC == 25) +#define RTE_USART0_IR_TX_PIN (USART0_IRTX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_IR_TX_MUX 2 +#define RTE_USART0_IR_TX_PAD 30 +#endif +//Pintool data +#endif // USART0_IR_RX <0=>P0_47 <1=>P0_71 <2=>P0_64 <3=>P0_25 // IR RX for USART0 - +#ifndef USART0_IRRX_LOC #define RTE_IR_RX_PORT_ID 0 #if ((RTE_IR_RX_PORT_ID == 2)) #error "Invalid USART0 RTE_USART0_IR_RX_PIN Pin Configuration!" @@ -287,9 +456,35 @@ #else #error "Invalid USART0 RTE_USART0_IR_RX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_IR_RX_PORT USART0_IRRX_PORT +#if (USART0_IRRX_LOC == 26) +#define RTE_USART0_IR_RX_PIN USART0_IRRX_PIN +#define RTE_USART0_IR_RX_MUX 13 +#define RTE_USART0_IR_RX_PAD 0 //no pad +#endif +#if (USART0_IRRX_LOC == 27) +#define RTE_USART0_IR_RX_PIN USART0_IRRX_PIN +#define RTE_USART0_IR_RX_MUX 2 +#define RTE_USART0_IR_RX_PAD 11 +#endif +#if (USART0_IRRX_LOC == 28) +#define RTE_USART0_IR_RX_PIN (USART0_IRRX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_IR_RX_MUX 11 +#define RTE_USART0_IR_RX_PAD 22 +#endif +#if (USART0_IRRX_LOC == 29) +#define RTE_USART0_IR_RX_PIN (USART0_IRRX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_IR_RX_MUX 2 +#define RTE_USART0_IR_RX_PAD 29 +#endif +//Pintool data +#endif // USART0_RI <0=>P0_27 <1=>P0_46 <2=>P0_68 // RI for USART0 +#ifndef USART0_RI_LOC #define RTE_RI_PORT_ID 0 #if (RTE_RI_PORT_ID == 0) @@ -305,9 +500,30 @@ #else #error "Invalid USART0 RTE_USART0_RI_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_RI_PORT USART0_RI_PORT +#if (USART0_RI_LOC == 30) +#define RTE_USART0_RI_PIN USART0_RI_PIN +#define RTE_USART0_RI_MUX 2 +#define RTE_USART0_RI_PAD 0 //no pad +#endif +#if (USART0_RI_LOC == 31) +#define RTE_USART0_RI_PIN USART0_RI_PIN +#define RTE_USART0_RI_MUX 2 +#define RTE_USART0_RI_PAD 10 +#endif +#if (USART0_RI_LOC == 32) +#define RTE_USART0_RI_PIN (USART0_RI_PIN + GPIO_MAX_PIN) +#define RTE_USART0_RI_MUX 11 +#define RTE_USART0_RI_PAD 26 +#endif +//Pintool data +#endif // USART0_DSR <0=>P0_11 <1=>P0_57 // DSR for USART0 +#ifndef USART0_DSR_LOC #define RTE_DSR_PORT_ID 0 #if (RTE_DSR_PORT_ID == 0) @@ -323,27 +539,56 @@ #else #error "Invalid USART0 RTE_USART0_RI_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_DSR_PORT USART0_DSR_PORT +#define RTE_USART0_DSR_PIN USART0_DSR_PIN +#if (USART0_DSR_LOC == 33) +#define RTE_USART0_DSR_MUX 2 +#define RTE_USART0_DSR_PAD 6 +#endif +#if (USART0_DSR_LOC == 34) +#define RTE_USART0_DSR_MUX 2 +#define RTE_USART0_DSR_PAD 21 +#endif +//Pintool data +#endif + // USART0_DCD <0=>P0_12 <1=>P0_29 // DCD for USART0 - +#ifndef USART0_DCD_LOC #define RTE_USART0_DCD_PORT 0 #define RTE_USART0_DCD_PIN 12 -#define RTE_USART0_DCD_MUX 2 -#define RTE_USART0_DCD_PAD 7 +#else +#define RTE_USART0_DCD_PORT USART0_DCD_PORT +#define RTE_USART0_DCD_PIN USART0_DCD_PIN +#if (USART0_DCD_LOC == 35) +#define RTE_USART0_DCD_MUX 2 +#define RTE_USART0_DCD_PAD 7 +#elif (USART0_DCD_LOC == 36) +#define RTE_USART0_DCD_MUX 12 +#define RTE_USART0_DCD_PAD 0 +#endif +#endif // USART0_DTR <0=>P0_7 // DTR for USART0 +#ifndef USART0_DTR_LOC #define RTE_USART0_DTR_PORT 0 #define RTE_USART0_DTR_PIN 7 -#define RTE_USART0_DTR_MUX 2 -#define RTE_USART0_DTR_PAD 2 +#else +#define RTE_USART0_DTR_PORT USART0_DTR_PORT +#define RTE_USART0_DTR_PIN USART0_DTR_PIN +#endif +#define RTE_USART0_DTR_MUX 2 +#define RTE_USART0_DTR_PAD 2 // // UART1 [Driver_UART1] // Configuration settings for Driver_UART1 in component ::CMSIS Driver:USART #define RTE_UART1 1 -#define RTE_UART1_CLK_SRC USART_INTFPLLCLK +#define RTE_UART1_CLK_SRC USART_ULPREFCLK #define RTE_UART1_CLK_DIV_FACT 1 #define RTE_UART1_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER @@ -363,7 +608,7 @@ /*UART1 PINS*/ // UART1_TX <0=>P0_7 <1=>P0_30 <2=>P0_67 <3=>P0_69 <4=>P0_73 <5=>P0_75 <6=>P0_34 // TX of UART1 - +#ifndef UART1_TX_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_UART1_TX_PORT_ID 0 #else @@ -402,10 +647,40 @@ #else #error "Invalid UART1 RTE_UART1_TX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_UART1_TX_PORT UART1_TX_PORT +#if (UART1_TX_LOC == 0) +#define RTE_UART1_TX_PIN UART1_TX_PIN +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 2 +#endif +#if (UART1_TX_LOC == 1) +#define RTE_UART1_TX_PIN UART1_TX_PIN +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 0 //no pad +#endif +#if (UART1_TX_LOC == 2) +#define RTE_UART1_TX_PIN (UART1_TX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 27 +#endif +#if (UART1_TX_LOC == 3) +#define RTE_UART1_TX_PIN (UART1_TX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 31 +#endif +#if (UART1_TX_LOC == 4) +#define RTE_UART1_TX_PIN (UART1_TX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_TX_MUX 9 +#define RTE_UART1_TX_PAD 33 +#endif +//Pintool data +#endif // UART1_RX <0=>P0_6 <1=>P0_29 <2=>P0_66 <3=>P0_68 <4=>P0_72 <5=>P0_74 <6=>P0_33 // RX of UART1 - +#ifndef UART1_RX_LOC #define RTE_UART1_RX_PORT_ID 0 #if (RTE_UART1_RX_PORT_ID == 0) @@ -436,9 +711,40 @@ #else #error "Invalid UART1 RTE_UART1_RX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_UART1_RX_PORT UART1_RX_PORT +#if (UART1_RX_LOC == 5) +#define RTE_UART1_RX_PIN UART1_RX_PIN +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 1 +#endif +#if (UART1_RX_LOC == 6) +#define RTE_UART1_RX_PIN UART1_RX_PIN +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 0 //no pad +#endif +#if (UART1_RX_LOC == 7) +#define RTE_UART1_RX_PIN (UART1_RX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 26 +#endif +#if (UART1_RX_LOC == 8) +#define RTE_UART1_RX_PIN (UART1_RX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 30 +#endif +#if (UART1_RX_LOC == 9) +#define RTE_UART1_RX_PIN (UART1_RX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RX_MUX 9 +#define RTE_UART1_RX_PAD 32 +#endif +//Pintool data +#endif // UART1_CTS <0=>P0_11 <1=>P0_28 <2=>P0_51 <3=>P0_65 <4=>P0_71 <5=>P0_73 <6=>P0_32 // CTS of UART1 +#ifndef UART1_CTS_LOC #define RTE_UART1_CTS_PORT_ID 0 #if (RTE_UART1_CTS_PORT_ID == 0) @@ -469,10 +775,45 @@ #else #error "Invalid UART1 RTE_UART1_CTS_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_UART1_CTS_PORT UART1_CTS_PORT +#if (UART1_CTS_LOC == 10) +#define RTE_UART1_CTS_PIN UART1_CTS_PIN +#define RTE_UART1_CTS_MUX 6 +#define RTE_UART1_CTS_PAD 6 +#endif +#if (UART1_CTS_LOC == 11) +#define RTE_UART1_CTS_PIN UART1_CTS_PIN +#define RTE_UART1_CTS_MUX 6 +#define RTE_UART1_CTS_PAD 0 //no pad +#endif +#if (UART1_CTS_LOC == 12) +#define RTE_UART1_CTS_PIN UART1_CTS_PIN +#define RTE_UART1_CTS_MUX 9 +#define RTE_UART1_CTS_PAD 15 +#endif +#if (UART1_CTS_LOC == 13) +#define RTE_UART1_CTS_PIN (UART1_CTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_CTS_MUX 9 +#define RTE_UART1_CTS_PAD 23 +#endif +#if (UART1_CTS_LOC == 14) +#define RTE_UART1_CTS_PIN (UART1_CTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_CTS_MUX 6 +#define RTE_UART1_CTS_PAD 29 +#endif +#if (UART1_CTS_LOC == 15) +#define RTE_UART1_CTS_PIN (UART1_CTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_CTS_MUX 9 +#define RTE_UART1_CTS_PAD 31 +#endif +//Pintool data +#endif // UART1_RTS <0=>P0_10 <1=>P0_27 <2=>P0_50 <3=>P0_64 <4=>P0_70 <5=>P0_72 <6=>P0_31 // RTS of UART1 - +#ifndef UART1_RTS_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_UART1_RTS_PORT_ID 0 #else @@ -507,6 +848,42 @@ #else #error "Invalid UART1 RTE_UART1_RTS_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_UART1_RTS_PORT UART1_RTS_PORT +#if (UART1_RTS_LOC == 16) +#define RTE_UART1_RTS_PIN UART1_RTS_PIN +#define RTE_UART1_RTS_MUX 6 +#define RTE_UART1_RTS_PAD 5 +#endif +#if (UART1_RTS_LOC == 17) +#define RTE_UART1_RTS_PIN UART1_RTS_PIN +#define RTE_UART1_RTS_MUX 6 +#define RTE_UART1_RTS_PAD 0 //no pad +#endif +#if (UART1_RTS_LOC == 18) +#define RTE_UART1_RTS_PIN UART1_RTS_PIN +#define RTE_UART1_RTS_MUX 9 +#define RTE_UART1_RTS_PAD 14 +#endif +#if (UART1_RTS_LOC == 19) +#define RTE_UART1_RTS_PIN (UART1_RTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RTS_MUX 9 +#define RTE_UART1_RTS_PAD 22 +#endif +#if (UART1_RTS_LOC == 20) +#define RTE_UART1_RTS_PIN (UART1_RTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RTS_MUX 6 +#define RTE_UART1_RTS_PAD 28 +#endif +#if (UART1_RTS_LOC == 21) +#define RTE_UART1_RTS_PIN (UART1_RTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RTS_MUX 9 +#define RTE_UART1_RTS_PAD 30 +#endif +//Pintool data +#endif + // // ULP_UART [Driver_ULP_UART] @@ -533,6 +910,7 @@ /*ULPSS UART PINS*/ // UART1_TX <0=>P0_3 <1=>P0_7 <2=>P0_11 // TX of ULPSS UART +#ifndef ULP_UART_TX_LOC #define RTE_ULP_UART_TX_PORT_ID 1 #if (RTE_ULP_UART_TX_PORT_ID == 0) #define RTE_ULP_UART_TX_PORT 0 @@ -545,9 +923,17 @@ #else #error "Invalid ULPSS UART RTE_ULP_UART_TX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_ULP_UART_TX_PORT ULP_UART_TX_PORT +#define RTE_ULP_UART_TX_PIN ULP_UART_TX_PIN +#define RTE_ULP_UART_TX_MUX 3 +//Pintool data +#endif // UART1_RX <0=>P0_2 <1=>P0_6 <2=>P0_9 // RX of ULPSS UART +#ifndef ULP_UART_RX_LOC #define RTE_ULP_UART_RX_PORT_ID 2 #if (RTE_ULP_UART_RX_PORT_ID == 0) #define RTE_ULP_UART_RX_PORT 0 @@ -564,9 +950,17 @@ #else #error "Invalid ULPSS UART RTE_ULP_UART_RX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_ULP_UART_RX_PORT ULP_UART_RX_PORT +#define RTE_ULP_UART_RX_PIN ULP_UART_RX_PIN +#define RTE_ULP_UART_RX_MUX 3 +//Pintool data +#endif // UART1_CTS <0=>P0_1 <1=>P0_5 <2=>P0_8 // CTS of ULPSS UART +#ifndef ULP_UART_CTS_LOC #define RTE_ULP_UART_CTS_PORT_ID 0 #if (RTE_ULP_UART_CTS_PORT_ID == 0) #define RTE_ULP_UART_CTS_PORT 0 @@ -579,17 +973,30 @@ #else #error "Invalid ULPSS UART RTE_ULP_UART_CTS_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_ULP_UART_CTS_PORT ULP_UART_CTS_PORT +#define RTE_ULP_UART_CTS_PIN ULP_UART_CTS_PIN +#define RTE_ULP_UART_CTS_MUX 3 +//Pintool data +#endif // UART1_RTS <0=>P0_0 <1=>P0_4 <2=>P0_10 // RTS of ULPSS UART +#ifndef ULP_UART_RTS_LOC #define RTE_ULP_UART_RTS_PORT_ID 0 #if (RTE_ULP_UART_RTS_PORT_ID == 0) #define RTE_ULP_UART_RTS_PORT 0 #define RTE_ULP_UART_RTS_PIN 10 -#define RTE_ULP_UART_RTS_MUX 8 #else #error "Invalid ULPSS UART RTE_ULP_UART_RTS_PIN Pin Configuration!" #endif +#else +#define RTE_ULP_UART_RTS_PORT ULP_UART_RTS_PORT +#define RTE_ULP_UART_RTS_PIN ULP_UART_RTS_PIN +#endif +#define RTE_ULP_UART_RTS_MUX 8 + // // SSI_MASTER (Serial Peripheral Interface 1) [Driver_SSI_MASTER] @@ -597,7 +1004,7 @@ #define RTE_SSI_MASTER 1 // SSI_MASTER_MISO Pin <0=>GPIO_12 <1=>GPIO_27 <2=>GPIO_57 - +#ifndef SSI_MASTER_DATA1_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SSI_MASTER_MISO_PORT_ID 1 #else @@ -625,8 +1032,26 @@ #else #error "Invalid SSI_MASTER_MISO Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_MASTER_MISO 1 +#define RTE_SSI_MASTER_MISO_PORT SSI_MASTER_MISO_DATA1_PORT +#define RTE_SSI_MASTER_MISO_PIN SSI_MASTER_MISO_DATA1_PIN +#define RTE_SSI_MASTER_MISO_MODE EGPIO_PIN_MUX_MODE3 +#if (SSI_MASTER_DATA1_LOC == 3) +#define RTE_SSI_MASTER_MISO_PADSEL 7 +#endif +#if (SSI_MASTER_DATA1_LOC == 4) +#define RTE_SSI_MASTER_MISO_PADSEL 0 //NO PAD +#endif +#if (SSI_MASTER_DATA1_LOC == 5) +#define RTE_SSI_MASTER_MISO_PADSEL 21 +#endif +//Pintool data +#endif // SSI_MASTER_MOSI Pin <0=>GPIO_11 <1=>GPIO_26 <2=>GPIO_56 +#ifndef SSI_MASTER_DATA0_LOC #define RTE_SSI_MASTER_MOSI_PORT_ID 1 #if (RTE_SSI_MASTER_MOSI_PORT_ID == 0) @@ -650,8 +1075,26 @@ #else #error "Invalid SSI_MASTER_MOSI Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_MASTER_MOSI 1 +#define RTE_SSI_MASTER_MOSI_PORT SSI_MASTER_MOSI_DATA0_PORT +#define RTE_SSI_MASTER_MOSI_PIN SSI_MASTER_MOSI_DATA0_PIN +#define RTE_SSI_MASTER_MOSI_MODE EGPIO_PIN_MUX_MODE3 +#if (SSI_MASTER_DATA0_LOC == 0) +#define RTE_SSI_MASTER_MOSI_PADSEL 6 +#endif +#if (SSI_MASTER_DATA0_LOC == 1) +#define RTE_SSI_MASTER_MOSI_PADSEL 0 //NO PAD +#endif +#if (SSI_MASTER_DATA0_LOC == 2) +#define RTE_SSI_MASTER_MOSI_PADSEL 20 +#endif +//Pintool data +#endif // SSI_MASTER_SCK Pin <0=>GPIO_8 <1=>GPIO_25 <2=>GPIO_52 +#ifndef SSI_MASTER_SCK_LOC #define RTE_SSI_MASTER_SCK_PORT_ID 1 #if (RTE_SSI_MASTER_SCK_PORT_ID == 0) @@ -675,6 +1118,23 @@ #else #error "Invalid SSI_MASTER_SCK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_MASTER_SCK 1 +#define RTE_SSI_MASTER_SCK_PORT SSI_MASTER_SCK__PORT +#define RTE_SSI_MASTER_SCK_PIN SSI_MASTER_SCK__PIN +#define RTE_SSI_MASTER_SCK_MODE EGPIO_PIN_MUX_MODE3 +#if (SSI_MASTER_SCK_LOC == 6) +#define RTE_SSI_MASTER_SCK_PADSEL 3 +#endif +#if (SSI_MASTER_SCK_LOC == 7) +#define RTE_SSI_MASTER_SCK_PADSEL 0 //NO PAD +#endif +#if (SSI_MASTER_SCK_LOC == 8) +#define RTE_SSI_MASTER_SCK_PADSEL 16 +#endif +//Pintool data +#endif #define M4_SSI_CS0 1 #define M4_SSI_CS1 0 @@ -682,6 +1142,7 @@ #define M4_SSI_CS3 0 // SSI_MASTER_CS Pin <0=>GPIO_9 <1=>GPIO_28 <2=>GPIO_53 <3=>GPIO_10 <4=>GPIO_15 <5=>GPIO_50 <6=>GPIO_51 +#ifndef SSI_MASTER_CS0_LOC #define RTE_SSI_MASTER_CS0_PORT_ID 1 #if (RTE_SSI_MASTER_CS0_PORT_ID == 0) @@ -705,20 +1166,43 @@ #else #error "Invalid SSI_MASTER_CS0 Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_MASTER_CS0 M4_SSI_CS0 +#define RTE_SSI_MASTER_CS0_PORT SSI_MASTER_CS0__PORT +#define RTE_SSI_MASTER_CS0_PIN SSI_MASTER_CS0__PIN +#define RTE_SSI_MASTER_CS0_MODE EGPIO_PIN_MUX_MODE3 +#if (SSI_MASTER_CS0_LOC == 9) +#define RTE_SSI_MASTER_CS0_PADSEL 4 +#endif +#if (SSI_MASTER_CS0_LOC == 10) +#define RTE_SSI_MASTER_CS0_PADSEL 0 //NO PAD +#endif +#if (SSI_MASTER_CS0_LOC == 11) +#define RTE_SSI_MASTER_CS0_PADSEL 17 +#endif +//Pintool data +#endif //CS1 +#ifndef SSI_MASTER_CS1_LOC #define RTE_SSI_MASTER_CS1_PORT_ID 0 #if (RTE_SSI_MASTER_CS1_PORT_ID == 0) -#define RTE_SSI_MASTER_CS1 M4_SSI_CS1 -#define RTE_SSI_MASTER_CS1_PORT 0 -#define RTE_SSI_MASTER_CS1_PIN 10 -#define RTE_SSI_MASTER_CS1_MODE EGPIO_PIN_MUX_MODE3 -#define RTE_SSI_MASTER_CS1_PADSEL 5 +#define RTE_SSI_MASTER_CS1_PORT 0 +#define RTE_SSI_MASTER_CS1_PIN 10 #else #error "Invalid SSI_MASTER_CS1 Pin Configuration!" #endif +#else +#define RTE_SSI_MASTER_CS1_PORT SSI_MASTER_CS1__PORT +#define RTE_SSI_MASTER_CS1_PIN SSI_MASTER_CS1__PIN +#endif +#define RTE_SSI_MASTER_CS1 M4_SSI_CS1 +#define RTE_SSI_MASTER_CS1_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS1_PADSEL 5 //CS2 +#ifndef SSI_MASTER_CS2_LOC #define RTE_SSI_MASTER_CS2_PORT_ID 1 #if (RTE_SSI_MASTER_CS2_PORT_ID == 0) #define RTE_SSI_MASTER_CS2 M4_SSI_CS2 @@ -735,18 +1219,37 @@ #else #error "Invalid SSI_MASTER_CS2 Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_MASTER_CS2 M4_SSI_CS2 +#define RTE_SSI_MASTER_CS2_PORT SSI_MASTER_CS2__PORT +#define RTE_SSI_MASTER_CS2_PIN SSI_MASTER_CS2__PIN +#define RTE_SSI_MASTER_CS2_MODE EGPIO_PIN_MUX_MODE3 +#if (SSI_MASTER_CS2_LOC == 13) +#define RTE_SSI_MASTER_CS2_PADSEL 8 +#endif +#if (SSI_MASTER_CS2_LOC == 14) +#define RTE_SSI_MASTER_CS2_PADSEL 14 +#endif +//Pintool data +#endif //CS3 +#ifndef SSI_MASTER_CS3_LOC #define RTE_SSI_MASTER_CS3_PORT_ID 0 #if (RTE_SSI_MASTER_CS3_PORT_ID == 0) -#define RTE_SSI_MASTER_CS3 M4_SSI_CS3 -#define RTE_SSI_MASTER_CS3_PORT 0 -#define RTE_SSI_MASTER_CS3_PIN 51 -#define RTE_SSI_MASTER_CS3_MODE EGPIO_PIN_MUX_MODE3 -#define RTE_SSI_MASTER_CS3_PADSEL 15 +#define RTE_SSI_MASTER_CS3_PORT 0 +#define RTE_SSI_MASTER_CS3_PIN 51 #else #error "Invalid SSI_MASTER_CS3 Pin Configuration!" #endif +#else +#define RTE_SSI_MASTER_CS3_PORT SSI_MASTER_CS3__PORT +#define RTE_SSI_MASTER_CS3_PIN SSI_MASTER_CS3__PIN +#endif +#define RTE_SSI_MASTER_CS3 M4_SSI_CS3 +#define RTE_SSI_MASTER_CS3_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS3_PADSEL 15 // DMA Rx // Channel <28=>28 @@ -768,6 +1271,7 @@ #define RTE_SSI_SLAVE_INPUT_CLOCK SSISLAVE_CLK // SSI_SLAVE_MISO Pin <0=>Not Used <1=>GPIO_11 <2=>GPIO_28 <3=>GPIO_49 <4=>GPIO_57 +#ifndef SSI_SLAVE_MISO_LOC #define RTE_SSI_SLAVE_MISO_PORT_ID 2 #if (RTE_SSI_SLAVE_MISO_PORT_ID == 0) @@ -799,9 +1303,29 @@ #else #error "Invalid SSI_SLAVE_MISO Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_SLAVE_MISO 1 +#define RTE_SSI_SLAVE_MISO_PORT SSI_SLAVE_MISO__PORT +#define RTE_SSI_SLAVE_MISO_PIN SSI_SLAVE_MISO__PIN +#define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8 +#if (SSI_SLAVE_MISO_LOC == 5) +#define RTE_SSI_SLAVE_MISO_PADSEL 6 +#endif +#if (SSI_SLAVE_MISO_LOC == 6) +#define RTE_SSI_SLAVE_MISO_PADSEL 0 //no pad +#endif +#if (SSI_SLAVE_MISO_LOC == 7) +#define RTE_SSI_SLAVE_MISO_PADSEL 13 +#endif +#if (SSI_SLAVE_MISO_LOC == 8) +#define RTE_SSI_SLAVE_MISO_PADSEL 21 +#endif +//Pintool data +#endif // SSI_SLAVE_MOSI Pin <0=>Not Used <1=>GPIO_10 <2=>GPIO_27 <3=>GPIO_48 <4=>GPIO_56 - +#ifndef SSI_SLAVE_MOSI_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SSI_SLAVE_MOSI_PORT_ID 2 #else @@ -837,8 +1361,29 @@ #else #error "Invalid SSI_SLAVE_MOSI Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_SLAVE_MOSI 1 +#define RTE_SSI_SLAVE_MOSI_PORT SSI_SLAVE_MOSI__PORT +#define RTE_SSI_SLAVE_MOSI_PIN SSI_SLAVE_MOSI__PIN +#define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8 +#if (SSI_SLAVE_MOSI_LOC == 1) +#define RTE_SSI_SLAVE_MOSI_PADSEL 5 +#endif +#if (SSI_SLAVE_MOSI_LOC == 2) +#define RTE_SSI_SLAVE_MOSI_PADSEL 0 //no pad +#endif +#if (SSI_SLAVE_MOSI_LOC == 3) +#define RTE_SSI_SLAVE_MOSI_PADSEL 12 +#endif +#if (SSI_SLAVE_MOSI_LOC == 4) +#define RTE_SSI_SLAVE_MOSI_PADSEL 20 +#endif +//Pintool data +#endif // SSI_SLAVE_SCK Pin <0=>Not Used <1=>GPIO_8 <2=>GPIO_26 <3=>GPIO_47 <4=>GPIO_52 +#ifndef SSI_SLAVE_SCK_LOC #define RTE_SSI_SLAVE_SCK_PORT_ID 2 #if (RTE_SSI_SLAVE_SCK_PORT_ID == 0) @@ -870,8 +1415,29 @@ #else #error "Invalid SSI_SLAVE_SCK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_SLAVE_SCK 1 +#define RTE_SSI_SLAVE_SCK_PORT SSI_SLAVE_SCK__PORT +#define RTE_SSI_SLAVE_SCK_PIN SSI_SLAVE_SCK__PIN +#define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8 +#if (SSI_SLAVE_SCK_LOC == 9) +#define RTE_SSI_SLAVE_SCK_PADSEL 3 +#endif +#if (SSI_SLAVE_SCK_LOC == 10) +#define RTE_SSI_SLAVE_SCK_PADSEL 0 //no pad +#endif +#if (SSI_SLAVE_SCK_LOC == 11) +#define RTE_SSI_SLAVE_SCK_PADSEL 11 +#endif +#if (SSI_SLAVE_SCK_LOC == 12) +#define RTE_SSI_SLAVE_SCK_PADSEL 16 +#endif +//Pintool data +#endif // SSI_SLAVE_CS Pin <0=>Not Used <1=>GPIO_9 <2=>GPIO_25 <3=>GPIO_46 <4=>GPIO_53 +#ifndef SSI_SLAVE_CS0_LOC #define RTE_SSI_SLAVE_CS_PORT_ID 1 #if (RTE_SSI_SLAVE_CS_PORT_ID == 0) @@ -903,6 +1469,26 @@ #else #error "Invalid SSI_SLAVE_CS Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_SLAVE_CS 1 +#define RTE_SSI_SLAVE_CS_PORT SSI_SLAVE_CS0__PORT +#define RTE_SSI_SLAVE_CS_PIN SSI_SLAVE_CS0__PIN +#define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8 +#if (SSI_SLAVE_CS0_LOC == 13) +#define RTE_SSI_SLAVE_CS_PADSEL 4 +#endif +#if (SSI_SLAVE_CS0_LOC == 14) +#define RTE_SSI_SLAVE_CS_PADSEL 0 //no pad +#endif +#if (SSI_SLAVE_CS0_LOC == 15) +#define RTE_SSI_SLAVE_CS_PADSEL 10 +#endif +#if (SSI_SLAVE_CS0_LOC == 16) +#define RTE_SSI_SLAVE_CS_PADSEL 17 +#endif +//Pintool data +#endif // DMA Rx // Channel <22=>22 @@ -920,7 +1506,7 @@ // -// SSI_ULP_MASTER (Serial Peripheral Interface 3) [Driver_SSI_ULP_MASTER] +// ULP SPI Peripheral (Serial Peripheral Interface 3) [Driver_SSI_ULP_MASTER] // Configuration settings for Driver_SSI_ULP_MASTER in component ::CMSIS Driver:SPI #define RTE_SSI_ULP_MASTER 1 @@ -930,6 +1516,7 @@ #define ULP_SSI_CS2 0 // SSI_ULP_MASTER_MISO Pin <0=>Not Used <1=>ULP_GPIO_2 <2=>ULP_GPIO_9 +#ifndef ULP_SPI_MISO_LOC #define RTE_SSI_ULP_MASTER_MISO_PORT_ID 0 #if (RTE_SSI_ULP_MASTER_MISO_PORT_ID == 0) #define RTE_SSI_ULP_MASTER_MISO 1 @@ -944,8 +1531,17 @@ #else #error "Invalid SSI_ULP_MISO Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_ULP_MASTER_MISO 1 +#define RTE_SSI_ULP_MASTER_MISO_PORT ULP_SPI_MISO__PORT +#define RTE_SSI_ULP_MASTER_MISO_PIN ULP_SPI_MISO__PIN +#define RTE_SSI_ULP_MASTER_MISO_MODE 1 +//Pintool data +#endif // SSI_ULP_MASTER_MOSI Pin <0=>Not Used <1=>ULP_GPIO_1 <2=>ULP_GPIO_11 +#ifndef ULP_SPI_MOSI_LOC #define RTE_SSI_ULP_MASTER_MOSI_PORT_ID 0 #if (RTE_SSI_ULP_MASTER_MOSI_PORT_ID == 0) #define RTE_SSI_ULP_MASTER_MOSI 1 @@ -960,8 +1556,17 @@ #else #error "Invalid SSI_ULP_MOSI Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_ULP_MASTER_MOSI 1 +#define RTE_SSI_ULP_MASTER_MOSI_PORT ULP_SPI_MOSI__PORT +#define RTE_SSI_ULP_MASTER_MOSI_PIN ULP_SPI_MOSI__PIN +#define RTE_SSI_ULP_MASTER_MOSI_MODE 1 +//Pintool data +#endif // SSI_ULP_MASTER_SCK Pin <0=>Not Used <1=>ULP_GPIO_0 <2=>ULP_GPIO_8 +#ifndef ULP_SPI_SCK_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SSI_ULP_MASTER_SCK_PORT_ID 2 #else @@ -982,8 +1587,17 @@ #else #error "Invalid SSI_ULP_SCK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_ULP_MASTER_SCK 1 +#define RTE_SSI_ULP_MASTER_SCK_PORT ULP_SPI_SCK__PORT +#define RTE_SSI_ULP_MASTER_SCK_PIN ULP_SPI_SCK__PIN +#define RTE_SSI_ULP_MASTER_SCK_MODE 1 +//Pintool data +#endif // CS0 +#ifndef ULP_SPI_CS0_LOC #define RTE_SSI_ULP_MASTER_CS0_PORT_ID 1 #if (RTE_SSI_ULP_MASTER_CS0_PORT_ID == 0) #define RTE_SSI_ULP_MASTER_CS0 ULP_SSI_CS0 @@ -998,17 +1612,35 @@ #else #error "Change RTE_SSI_ULP_MASTER_CS_PORT_ID other than '1' or'3' as per PACKAGE_TYPE" #endif +#else +//Pintool data +#define RTE_SSI_ULP_MASTER_CS0 ULP_SSI_CS0 +#define RTE_SSI_ULP_MASTER_CS0_PORT ULP_SPI_CS0__PORT +#define RTE_SSI_ULP_MASTER_CS0_PIN ULP_SPI_CS0__PIN +#define RTE_SSI_ULP_MASTER_CS0_MODE 1 +//Pintool data +#endif // CS1 -#define RTE_SSI_ULP_MASTER_CS1 ULP_SSI_CS1 +#ifndef ULP_SPI_CS1_LOC #define RTE_SSI_ULP_MASTER_CS1_PORT 0 #define RTE_SSI_ULP_MASTER_CS1_PIN 4 +#else +#define RTE_SSI_ULP_MASTER_CS1_PORT ULP_SPI_CS1__PORT +#define RTE_SSI_ULP_MASTER_CS1_PIN ULP_SPI_CS1__PIN +#endif +#define RTE_SSI_ULP_MASTER_CS1 ULP_SSI_CS1 #define RTE_SSI_ULP_MASTER_CS1_MODE 1 // CS2 -#define RTE_SSI_ULP_MASTER_CS2 ULP_SSI_CS2 +#ifndef ULP_SPI_CS2_LOC #define RTE_SSI_ULP_MASTER_CS2_PORT 0 #define RTE_SSI_ULP_MASTER_CS2_PIN 6 +#else +#define RTE_SSI_ULP_MASTER_CS2_PORT ULP_SPI_CS2__PORT +#define RTE_SSI_ULP_MASTER_CS2_PIN ULP_SPI_CS2__PIN +#endif +#define RTE_SSI_ULP_MASTER_CS2 ULP_SSI_CS2 #define RTE_SSI_ULP_MASTER_CS2_MODE 1 // DMA Rx @@ -1069,6 +1701,7 @@ // I2S0_SCLK <0=>P0_8 <1=>P0_25 <2=>P0_46 <3=>P0_52 // SCLK of I2S0 +#ifndef I2S0_SCLK_LOC #define RTE_I2S0_SCLK_PORT_ID 1 #if (RTE_I2S0_SCLK_PORT_ID == 0) @@ -1094,9 +1727,29 @@ #else #error "Invalid I2S0 RTE_I2S0_SCLK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S0_SCLK_PORT I2S0_SCLK_PORT +#define RTE_I2S0_SCLK_PIN I2S0_SCLK_PIN +#define RTE_I2S0_SCLK_MUX 7 +#if (I2S0_SCLK_LOC == 0) +#define RTE_I2S0_SCLK_PAD 3 +#endif +#if (I2S0_SCLK_LOC == 1) +#define RTE_I2S0_SCLK_PAD 0 //no pad +#endif +#if (I2S0_SCLK_LOC == 2) +#define RTE_I2S0_SCLK_PAD 10 +#endif +#if (I2S0_SCLK_LOC == 3) +#define RTE_I2S0_SCLK_PAD 16 +#endif +//Pintool data +#endif // I2S0_WSCLK <0=>P0_9 <1=>P0_26 <2=>P0_47 <3=>P0_53 // WSCLK for I2S0 +#ifndef I2S0_WSCLK_LOC #define RTE_I2S0_WSCLK_PORT_ID 1 #if (RTE_I2S0_WSCLK_PORT_ID == 0) @@ -1122,9 +1775,29 @@ #else #error "Invalid I2S0 RTE_I2S0_WSCLK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S0_WSCLK_PORT I2S0_WSCLK_PORT +#define RTE_I2S0_WSCLK_PIN I2S0_WSCLK_PIN +#define RTE_I2S0_WSCLK_MUX 7 +#if (I2S0_WSCLK_LOC == 4) +#define RTE_I2S0_WSCLK_PAD 4 +#endif +#if (I2S0_WSCLK_LOC == 5) +#define RTE_I2S0_WSCLK_PAD 0 +#endif +#if (I2S0_WSCLK_LOC == 6) +#define RTE_I2S0_WSCLK_PAD 11 +#endif +#if (I2S0_WSCLK_LOC == 7) +#define RTE_I2S0_WSCLK_PAD 17 +#endif +//Pintool data +#endif // I2S0_DOUT0 <0=>P0_11 <1=>P0_28 <2=>P0_49 <3=>P0_57 // DOUT0 for I2S0 +#ifndef I2S0_DOUT0_LOC #define RTE_I2S0_DOUT0_PORT_ID 1 #if (RTE_I2S0_DOUT0_PORT_ID == 0) @@ -1150,9 +1823,29 @@ #else #error "Invalid I2S0 RTE_I2S0_DOUT0 Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S0_DOUT0_PORT I2S0_DOUT0_PORT +#define RTE_I2S0_DOUT0_PIN I2S0_DOUT0_PIN +#define RTE_I2S0_DOUT0_MUX 7 +#if (I2S0_DOUT0_LOC == 8) +#define RTE_I2S0_DOUT0_PAD 6 +#endif +#if (I2S0_DOUT0_LOC == 9) +#define RTE_I2S0_DOUT0_PAD 0 +#endif +#if (I2S0_DOUT0_LOC == 10) +#define RTE_I2S0_DOUT0_PAD 13 +#endif +#if (I2S0_DOUT0_LOC == 11) +#define RTE_I2S0_DOUT0_PAD 21 +#endif +//Pintool data +#endif // I2S0_DIN0 <0=>P0_10 <1=>P0_27 <2=>P0_48 <3=>P0_56 // DIN0 for I2S0 +#ifndef I2S0_DIN0_LOC #define RTE_I2S0_DIN0_PORT_ID 1 #if (RTE_I2S0_DIN0_PORT_ID == 0) @@ -1178,10 +1871,29 @@ #else #error "Invalid I2S0 RTE_I2S0_DIN0 Pin Configuration!" #endif - +#else +//Pintool data +#define RTE_I2S0_DIN0_PORT I2S0_DIN0_PORT +#define RTE_I2S0_DIN0_PIN I2S0_DIN0_PIN +#define RTE_I2S0_DIN0_MUX 7 +#if (I2S0_DIN0_LOC == 12) +#define RTE_I2S0_DIN0_PAD 5 +#endif +#if (I2S0_DIN0_LOC == 13) +#define RTE_I2S0_DIN0_PAD 0 +#endif +#if (I2S0_DIN0_LOC == 14) +#define RTE_I2S0_DIN0_PAD 12 +#endif +#if (I2S0_DIN0_LOC == 15) +#define RTE_I2S0_DIN0_PAD 20 +#endif +//Pintool data +#endif + // I2S0_DOUT1 <0=>P0_7 <1=>P0_30 <2=>P0_51 <3=>P0_55 // DOUT1 for I2S0 - +#ifndef I2S0_DOUT1_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_I2S0_DOUT1_PORT_ID 1 #else @@ -1211,9 +1923,29 @@ #else #error "Invalid I2S0 RTE_I2S0_DOUT1 Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S0_DOUT1_PORT I2S0_DOUT1_PORT +#define RTE_I2S0_DOUT1_PIN I2S0_DOUT1_PIN +#define RTE_I2S0_DOUT1_MUX 7 +#if (I2S0_DOUT1_LOC == 16) +#define RTE_I2S0_DOUT1_PAD 2 +#endif +#if (I2S0_DOUT1_LOC == 17) +#define RTE_I2S0_DOUT1_PAD 0 +#endif +#if (I2S0_DOUT1_LOC == 18) +#define RTE_I2S0_DOUT1_PAD 15 +#endif +#if (I2S0_DOUT1_LOC == 19) +#define RTE_I2S0_DOUT1_PAD 19 +#endif +//Pintool data +#endif // I2S0_DIN1 <0=>P0_6 <1=>P0_29 <2=>P0_50 <3=>P0_54 // DIN1 for I2S0 +#ifndef I2S0_DIN1_LOC #define RTE_I2S0_DIN1_PORT_ID 0 #if (RTE_I2S0_DIN1_PORT_ID == 0) @@ -1239,8 +1971,27 @@ #else #error "Invalid I2S0 RTE_I2S0_DIN1 Pin Configuration!" #endif -// FIFO level can have value 1 to 7 -#define I2S0_TX_FIFO_LEVEL (2U) +#else +//Pintool data +#define RTE_I2S0_DIN1_PORT I2S0_DIN1_PORT +#define RTE_I2S0_DIN1_PIN I2S0_DIN1_PIN +#define RTE_I2S0_DIN1_MUX 7 +#if (I2S0_DIN1_LOC == 20) +#define RTE_I2S0_DIN1_PAD 1 +#endif +#if (I2S0_DIN1_LOC == 21) +#define RTE_I2S0_DIN1_PAD 0 +#endif +#if (I2S0_DIN1_LOC == 22) +#define RTE_I2S0_DIN1_PAD 14 +#endif +#if (I2S0_DIN1_LOC == 23) +#define RTE_I2S0_DIN1_PAD 18 +#endif +//Pintool data +#endif +// FIFO level can have value 0 to 7 +#define I2S0_TX_FIFO_LEVEL (0U) #define I2S0_RX_FIFO_LEVEL (2U) // I2S0_TX_RES <0=>12 @@ -1288,13 +2039,14 @@ // -// I2S1 [Driver_I2S1] +// ULP I2S [Driver_I2S1] // Configuration settings for Driver_I2S1 in component ::Drivers:I2S #define RTE_I2S1 1 #define I2S1_IRQHandler IRQ014_Handler // I2S1_SCLK Pin <0=>P0_3 <1=>P0_7 <2=>P0_8 /*I2S1 PINS*/ +#ifndef ULP_I2S_SCLK_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_I2S1_SCLK_PORT_ID 0 #else @@ -1315,8 +2067,16 @@ #else #error "Invalid I2S1 RTE_I2S1_SCLK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S1_SCLK_PORT ULP_I2S_SCLK_PORT +#define RTE_I2S1_SCLK_PIN ULP_I2S_SCLK_PIN +#define RTE_I2S1_SCLK_MUX 2 +//Pintool data +#endif // I2S1_WSCLK Pin <0=>P0_2 <1=>P0_4 <2=>P0_10 +#ifndef ULP_I2S_WSCLK_LOC #define RTE_I2S1_WSCLK_PORT_ID 0 #if (RTE_I2S1_WSCLK_PORT_ID == 0) #define RTE_I2S1_WSCLK_PORT 0 @@ -1329,8 +2089,16 @@ #else #error "Invalid I2S1 RTE_I2S1_WSCLK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S1_WSCLK_PORT ULP_I2S_WSCLK_PORT +#define RTE_I2S1_WSCLK_PIN ULP_I2S_WSCLK_PIN +#define RTE_I2S1_WSCLK_MUX 2 +//Pintool data +#endif // I2S1_DOUT0 Pin <0=>P0_1 <1=>P0_5 <2=>P0_11 +#ifndef ULP_I2S_DOUT0_LOC #define RTE_I2S1_DOUT0_PORT_ID 0 #if (RTE_I2S1_DOUT0_PORT_ID == 0) #define RTE_I2S1_DOUT0_PORT 0 @@ -1343,8 +2111,16 @@ #else #error "Invalid I2S1 RTE_I2S1_DOUT0 Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S1_DOUT0_PORT ULP_I2S_DOUT0_PORT +#define RTE_I2S1_DOUT0_PIN ULP_I2S_DOUT0_PIN +#define RTE_I2S1_DOUT0_MUX 2 +//Pintool data +#endif // I2S1_DIN0 Pin <0=>P0_0 <1=>P0_6 <2=>P0_9 <3=>P0_13 +#ifndef ULP_I2S_DIN0_LOC #define RTE_I2S1_DIN0_PORT_ID 1 #if (RTE_I2S1_DIN0_PORT_ID == 0) #define RTE_I2S1_DIN0_PORT 0 @@ -1361,9 +2137,16 @@ #else #error "Invalid I2S1 RTE_I2S1_DIN0 Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S1_DIN0_PORT ULP_I2S_DIN0_PORT +#define RTE_I2S1_DIN0_PIN ULP_I2S_DIN0_PIN +#define RTE_I2S1_DIN0_MUX 2 +//Pintool data +#endif -// FIFO level can have value 1 to 7 -#define I2S1_TX_FIFO_LEVEL (2U) +// FIFO level can have value 0 to 7 +#define I2S1_TX_FIFO_LEVEL (0U) #define I2S1_RX_FIFO_LEVEL (2U) // I2S1_TX_RES <0=>12 @@ -1406,39 +2189,6 @@ #define RTE_I2S1_CHNL_UDMA_RX_EN 1 #define RTE_I2S1_CHNL_UDMA_RX_CH 6 -#define I2S1_CLK_DIV_FACT 0 -// I2S1_CLK_SRC <0=>ULP_I2S_REF_CLK -// <1=>ULP_I2S_ULP_32KHZ_RO_CLK -// <2=>ULP_I2S_ULP_32KHZ_RC_CLK -// <3=>ULP_I2S_ULP_32KHZ_XTAL_CLK -// <4=>ULP_I2S_ULP_32MHZ_RC_CLK -// <5=>ULP_I2S_ULP_20MHZ_RO_CLK -// <6=>ULP_I2S_SOC_CLK -// <7=>ULP_I2S_ULP_DOUBLER_CLK -// <8=>ULP_I2S_PLL_CLK - -#define RTE_I2S1_CLK_SEL_ID 5 -#if (RTE_I2S1_CLK_SEL_ID == 0) -#define RTE_I2S1_CLK_SRC ULP_I2S_REF_CLK -#elif (RTE_I2S1_CLK_SEL_ID == 1) -#define RTE_I2S1_CLK_SRC ULP_I2S_ULP_32KHZ_RO_CLK -#elif (RTE_I2S1_CLK_SEL_ID == 2) -#define RTE_I2S1_CLK_SRC ULP_I2S_ULP_32KHZ_RC_CLK -#elif (RTE_I2S1_CLK_SEL_ID == 3) -#define RTE_I2S1_CLK_SRC ULP_I2S_ULP_32KHZ_XTAL_CLK -#elif (RTE_I2S1_CLK_SEL_ID == 4) -#define RTE_I2S1_CLK_SRC ULP_I2S_ULP_32MHZ_RC_CLK -#elif (RTE_I2S1_CLK_SEL_ID == 5) -#define RTE_I2S1_CLK_SRC ULP_I2S_ULP_20MHZ_RO_CLK -#elif (RTE_I2S1_CLK_SEL_ID == 6) -#define RTE_I2S1_CLK_SRC ULP_I2S_SOC_CLK -#elif (RTE_I2S1_CLK_SEL_ID == 7) -#define RTE_I2S1_CLK_SRC ULP_I2S_ULP_DOUBLER_CLK -#elif (RTE_I2S1_CLK_SEL_ID == 8) -#define RTE_I2S1_CLK_SRC ULP_I2S_PLL_CLK -#else -#error "Invalid I2S1 Clock source selection!" -#endif #define RTE_I2S1_DMA_TX_LEN_PER_DES 1024 #define RTE_I2S1_DMA_RX_LEN_PER_DES 1024 @@ -1451,7 +2201,7 @@ #define I2C0_IRQHandler IRQ042_Handler // I2C0_SCL Pin <0=>P0_7 <1=>P0_65 <2=>P0_66 <3=>P0_75 <4=>P0_32 - +#ifndef I2C0_SCL_LOC #define RTE_I2C0_SCL_PORT_ID 1 #if (RTE_I2C0_SCL_PORT_ID == 0) @@ -1481,9 +2231,32 @@ #else #error "Invalid I2C0 RTE_I2C0_SCL Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2C0_SCL_PORT I2C0_SCL_PORT +#if (I2C0_SCL_LOC == 0) +#define RTE_I2C0_SCL_PIN I2C0_SCL_PIN +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 2 +#define RTE_I2C0_SCL_I2C_REN 7 +#endif +#if (I2C0_SCL_LOC == 1) +#define RTE_I2C0_SCL_PIN (I2C0_SCL_PIN + GPIO_MAX_PIN) +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 23 +#define RTE_I2C0_SCL_I2C_REN 1 +#endif +#if (I2C0_SCL_LOC == 2) +#define RTE_I2C0_SCL_PIN (I2C0_SCL_PIN + GPIO_MAX_PIN) +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 33 +#define RTE_I2C0_SCL_I2C_REN 11 +#endif +//Pintool data +#endif // I2C0_SCL Pin <0=>P0_6 <1=>P0_64 <2=>P0_67 <3=>P0_74 <4=>P0_31 - +#ifndef I2C0_SDA_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_I2C0_SDA_PORT_ID 2 #else @@ -1511,6 +2284,29 @@ #else #error "Invalid I2C0 RTE_I2C0_SDA Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2C0_SDA_PORT I2C0_SDA_PORT +#if (I2C0_SDA_LOC == 3) +#define RTE_I2C0_SDA_PIN I2C0_SDA_PIN +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 1 +#define RTE_I2C0_SDA_I2C_REN 6 +#endif +#if (I2C0_SDA_LOC == 4) +#define RTE_I2C0_SDA_PIN (I2C0_SDA_PIN + GPIO_MAX_PIN) +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 22 +#define RTE_I2C0_SDA_I2C_REN 3 +#endif +#if (I2C0_SDA_LOC == 5) +#define RTE_I2C0_SDA_PIN (I2C0_SDA_PIN + GPIO_MAX_PIN) +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 32 +#define RTE_I2C0_SDA_I2C_REN 10 +#endif +//Pintool data +#endif #define IC_SCL_STUCK_TIMEOUT 20 #define IC_SDA_STUCK_TIMEOUT 20 @@ -1520,7 +2316,7 @@ #define DMA_TX_TL 1 #define DMA_RX_TL 1 #endif -// I2C0 [Driver_I2C0] +// I2C1 [Driver_I2C0] // I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1] // Configuration settings for Driver_I2C1 in component ::Drivers:I2C @@ -1528,6 +2324,7 @@ #define RTE_I2C1 1 #define I2C1_IRQHandler IRQ061_Handler // I2C1_SCL Pin <0=>P0_6 <1=>P0_29 <2=>P0_50 <3=>P0_54 <4=>P0_64 <4=>P0_66 <4=>P0_70 <7=>P0_33 +#ifndef I2C1_SCL_LOC #define RTE_I2C1_SCL_PORT_ID 2 #if (RTE_I2C1_SCL_PORT_ID == 0) @@ -1569,9 +2366,50 @@ #else #error "Invalid I2C1_SCL Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2C1_SCL_PORT I2C1_SCL_PORT +#if (I2C1_SCL_LOC == 0) +#define RTE_I2C1_SCL_PIN I2C1_SCL_PIN +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 1 +#define RTE_I2C1_SCL_REN 6 +#endif +#if (I2C1_SCL_LOC == 1) +#define RTE_I2C1_SCL_PIN I2C1_SCL_PIN +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 0 //no pad +#define RTE_I2C1_SCL_REN 29 +#endif +#if (I2C1_SCL_LOC == 2) +#define RTE_I2C1_SCL_PIN I2C1_SCL_PIN +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 14 +#define RTE_I2C1_SCL_REN 50 +#endif +#if (I2C1_SCL_LOC == 3) +#define RTE_I2C1_SCL_PIN I2C1_SCL_PIN +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 18 +#define RTE_I2C1_SCL_REN 54 +#endif +#if (I2C1_SCL_LOC == 4) +#define RTE_I2C1_SCL_PIN (I2C1_SCL_PIN + GPIO_MAX_PIN) +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 22 +#define RTE_I2C1_SCL_REN 2 +#endif +#if (I2C1_SCL_LOC == 5) +#define RTE_I2C1_SCL_PIN (I2C1_SCL_PIN + GPIO_MAX_PIN) +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 29 +#define RTE_I2C1_SCL_REN 6 +#endif +//Pintool data +#endif // I2C1_SCL Pin <0=>P0_7 <1=>P0_30 <2=>P0_51 <3=>P0_55 <4=>P0_65 <4=>P0_67 <4=>P0_71 <7=>P0_34 - +#ifndef I2C1_SDA_LOC #define RTE_I2C1_SDA_PORT_ID 2 #if (RTE_I2C1_SDA_PORT_ID == 0) @@ -1619,6 +2457,47 @@ #else #error "Invalid I2C1_SDA Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2C1_SDA_PORT I2C1_SDA_PORT +#if (I2C1_SDA_LOC == 6) +#define RTE_I2C1_SDA_PIN I2C1_SDA_PIN +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 2 +#define RTE_I2C1_SDA_REN 7 +#endif +#if (I2C1_SDA_LOC == 7) +#define RTE_I2C1_SDA_PIN I2C1_SDA_PIN +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 0 //no pad +#define RTE_I2C1_SDA_REN 30 +#endif +#if (I2C1_SDA_LOC == 8) +#define RTE_I2C1_SDA_PIN I2C1_SDA_PIN +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 15 +#define RTE_I2C1_SDA_REN 51 +#endif +#if (I2C1_SDA_LOC == 9) +#define RTE_I2C1_SDA_PIN I2C1_SDA_PIN +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 19 +#define RTE_I2C1_SDA_REN 55 +#endif +#if (I2C1_SDA_LOC == 10) +#define RTE_I2C1_SDA_PIN (I2C1_SDA_PIN + GPIO_MAX_PIN) +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 23 +#define RTE_I2C1_SDA_REN 1 +#endif +#if (I2C1_SDA_LOC == 11) +#define RTE_I2C1_SDA_PIN (I2C1_SDA_PIN + GPIO_MAX_PIN) +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 29 +#define RTE_I2C1_SDA_REN 7 +#endif +//Pintool data +#endif #define IC_SCL_STUCK_TIMEOUT 20 #define IC_SDA_STUCK_TIMEOUT 20 @@ -1631,12 +2510,13 @@ // I2C1 [Driver_I2C1] -// I2C2 (Inter-integrated Circuit Interface 2) [Driver_I2C2] +// ULP I2C (Inter-integrated Circuit Interface 2) [Driver_I2C2] // Configuration settings for Driver_I2C2 in component ::Drivers:I2C #define RTE_I2C2 1 #define I2C2_IRQHandler IRQ013_Handler // I2C2_SCL Pin <0=>P0_1 <1=>P0_5 <2=>P0_7 <3=>P0_8 <4=>P0_13 +#ifndef ULP_I2C_SCL_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_I2C2_SCL_PORT_ID 0 #else @@ -1655,8 +2535,25 @@ #else #error "Invalid I2C2_SCL Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2C2_SCL_PORT ULP_I2C_SCL_PORT +#define RTE_I2C2_SCL_PIN ULP_I2C_SCL_PIN +#define RTE_I2C2_SCL_MUX 4 +#if (ULP_I2C_SCL_LOC == 0) +#define RTE_I2C2_SCL_REN 0 +#elif (ULP_I2C_SCL_LOC == 1) +#define RTE_I2C2_SCL_REN 0 +#elif (ULP_I2C_SCL_LOC == 2) +#define RTE_I2C2_SCL_REN 7 +#elif (ULP_I2C_SCL_LOC == 3) +#define RTE_I2C2_SCL_REN 8 +#endif +//Pintool data +#endif // I2C2_SDA Pin <0=>P0_0 <1=>P0_4 <2=>P0_6 <3=>P0_9 <4=>P0_11 <5=>P0_12 +#ifndef ULP_I2C_SDA_LOC #define RTE_I2C2_SDA_PORT_ID 0 #if (RTE_I2C2_SDA_PORT_ID == 0) #define RTE_I2C2_SDA_PORT 0 @@ -1664,10 +2561,10 @@ #define RTE_I2C2_SDA_MUX 4 #define RTE_I2C2_SDA_REN 6 #elif (RTE_I2C2_SDA_PORT_ID == 1) -#define RTE_I2C2_SDA_PORT 0 -#define RTE_I2C2_SDA_PIN 9 -#define RTE_I2C2_SDA_MUX 4 -#define RTE_I2C2_SDA_I2C_REN 9 +#define RTE_I2C2_SDA_PORT 0 +#define RTE_I2C2_SDA_PIN 9 +#define RTE_I2C2_SDA_MUX 4 +#define RTE_I2C2_SDA_REN 9 #elif (RTE_I2C2_SDA_PORT_ID == 2) #define RTE_I2C2_SDA_PORT 0 #define RTE_I2C2_SDA_PIN 11 @@ -1676,6 +2573,24 @@ #else #error "Invalid I2C2_SDA Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2C2_SDA_PORT I2C2_SDA_PORT +#define RTE_I2C2_SDA_PIN I2C2_SDA_PIN +#define RTE_I2C2_SDA_MUX 4 +#if (ULP_I2C_SDA_LOC == 4) +#define RTE_I2C2_SDA_REN 0 +#elif (ULP_I2C_SDA_LOC == 5) +#define RTE_I2C2_SDA_REN 0 +#elif (ULP_I2C_SDA_LOC == 6) +#define RTE_I2C2_SDA_REN 6 +#elif (ULP_I2C_SDA_LOC == 7) +#define RTE_I2C2_SDA_REN 9 +#elif (ULP_I2C_SDA_LOC == 8) +#define RTE_I2C2_SDA_REN 11 +#endif +//Pintool data +#endif #define IC_SCL_STUCK_TIMEOUT 20 #define IC_SDA_STUCK_TIMEOUT 20 @@ -1694,6 +2609,7 @@ // GSPI_MASTER_CLK <0=>P0_8 <1=>P0_25 <2=>P0_46 <3=>P0_52 // CLK of GSPI0 +#ifndef GSPI_MASTER_SCK_LOC #define RTE_GSPI_MASTER_CLK_PORT_ID 1 #if (RTE_GSPI_MASTER_CLK_PORT_ID == 0) @@ -1719,13 +2635,32 @@ #else #error "Invalid GSPI0 RTE_GSPI_MASTER_CLK_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_GSPI_MASTER_CLK_PORT GSPI_MASTER_SCK__PORT +#define RTE_GSPI_MASTER_CLK_PIN GSPI_MASTER_SCK__PIN +#define RTE_GSPI_MASTER_CLK_MUX 4 +#if (GSPI_MASTER_SCK_LOC == 0) +#define RTE_GSPI_MASTER_CLK_PAD 3 +#endif +#if (GSPI_MASTER_SCK_LOC == 1) +#define RTE_GSPI_MASTER_CLK_PAD 0 +#endif +#if (GSPI_MASTER_SCK_LOC == 2) +#define RTE_GSPI_MASTER_CLK_PAD 10 +#endif +#if (GSPI_MASTER_SCK_LOC == 3) +#define RTE_GSPI_MASTER_CLK_PAD 16 +#endif +//Pintool data +#endif // GSPI_MASTER_CS0 // <0=>P0_9 <1=>P0_28 <2=>P0_49 <3=>P0_53 // CS0 of GSPI0 // - -#define RTE_GSPI_MASTER_CS0_PORT_ID 2 +#ifndef GSPI_MASTER_CS0_LOC +#define RTE_GSPI_MASTER_CS0_PORT_ID 1 #if (RTE_GSPI_MASTER_CS0_PORT_ID == 0) #define RTE_GSPI_MASTER_CS0 1 @@ -1754,12 +2689,33 @@ #else #error "Invalid GSPI0 RTE_GSPI_MASTER_CS0_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_GSPI_MASTER_CS0 1 +#define RTE_GSPI_MASTER_CS0_PORT GSPI_MASTER_CS0__PORT +#define RTE_GSPI_MASTER_CS0_PIN GSPI_MASTER_CS0__PIN +#define RTE_GSPI_MASTER_CS0_MUX 4 +#if (GSPI_MASTER_CS0_LOC == 4) +#define RTE_GSPI_MASTER_CS0_PAD 4 +#endif +#if (GSPI_MASTER_CS0_LOC == 5) +#define RTE_GSPI_MASTER_CS0_PAD 0 +#endif +#if (GSPI_MASTER_CS0_LOC == 6) +#define RTE_GSPI_MASTER_CS0_PAD 13 +#endif +#if (GSPI_MASTER_CS0_LOC == 7) +#define RTE_GSPI_MASTER_CS0_PAD 17 +#endif +//Pintool data +#endif // GSPI_MASTER_CS1 // <0=>P0_10 <1=>P0_29 <2=>P0_50 <3=>P0_54 // CS1 of GSPI0 // -#define RTE_GSPI_MASTER_CS1_PORT_ID 2 +#ifndef GSPI_MASTER_CS1_LOC +#define RTE_GSPI_MASTER_CS1_PORT_ID 1 #if (RTE_GSPI_MASTER_CS1_PORT_ID == 0) #define RTE_GSPI_MASTER_CS1 1 #define RTE_GSPI_MASTER_CS1_PORT 0 @@ -1787,11 +2743,32 @@ #else #error "Invalid GSPI0 RTE_GSPI_MASTER_CS1_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_GSPI_MASTER_CS1 1 +#define RTE_GSPI_MASTER_CS1_PORT GSPI_MASTER_CS1__PORT +#define RTE_GSPI_MASTER_CS1_PIN GSPI_MASTER_CS1__PIN +#define RTE_GSPI_MASTER_CS1_MUX 4 +#if (GSPI_MASTER_CS1_LOC == 8) +#define RTE_GSPI_MASTER_CS1_PAD 5 +#endif +#if (GSPI_MASTER_CS1_LOC == 9) +#define RTE_GSPI_MASTER_CS1_PAD 0 +#endif +#if (GSPI_MASTER_CS1_LOC == 10) +#define RTE_GSPI_MASTER_CS1_PAD 14 +#endif +#if (GSPI_MASTER_CS1_LOC == 11) +#define RTE_GSPI_MASTER_CS1_PAD 18 +#endif +//Pintool data +#endif // GSPI_MASTER_CS2 // <0=>P0_15 <1=>P0_30 <2=>P0_51 <3=>P0_55 // CS2 of GSPI0 // +#ifndef GSPI_MASTER_CS2_LOC #define RTE_GSPI_MASTER_CS2_PORT_ID 1 #if (RTE_GSPI_MASTER_CS2_PORT_ID == 0) #define RTE_GSPI_MASTER_CS2 1 @@ -1820,10 +2797,30 @@ #else #error "Invalid GSPI0 RTE_GSPI_MASTER_CS2_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_GSPI_MASTER_CS2 1 +#define RTE_GSPI_MASTER_CS2_PORT GSPI_MASTER_CS2__PORT +#define RTE_GSPI_MASTER_CS2_PIN GSPI_MASTER_CS2__PIN +#define RTE_GSPI_MASTER_CS2_MUX 4 +#if (GSPI_MASTER_CS2_LOC == 12) +#define RTE_GSPI_MASTER_CS2_PAD 8 +#endif +#if (GSPI_MASTER_CS2_LOC == 13) +#define RTE_GSPI_MASTER_CS2_PAD 0 +#endif +#if (GSPI_MASTER_CS2_LOC == 14) +#define RTE_GSPI_MASTER_CS2_PAD 15 +#endif +#if (GSPI_MASTER_CS2_LOC == 15) +#define RTE_GSPI_MASTER_CS2_PAD 19 +#endif +//Pintool data +#endif // GSPI_MASTER_MOSI <0=>P0_12 <1=>P0_27 <2=>P0_48 <3=>P0_57 <4=>P0_6 // MOSI of GSPI0 - +#ifndef GSPI_MASTER_MOSI_LOC #define RTE_GSPI_MASTER_MOSI_PORT_ID 1 #if (RTE_GSPI_MASTER_MOSI_PORT_ID == 0) @@ -1854,10 +2851,36 @@ #else #error "Invalid GSPI0 RTE_GSPI_MASTER_MOSI_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_GSPI_MASTER_MOSI_PORT GSPI_MASTER_MOSI__PORT +#define RTE_GSPI_MASTER_MOSI_PIN GSPI_MASTER_MOSI__PIN +#if (GSPI_MASTER_MOSI_LOC == 16) +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 1 +#endif +#if (GSPI_MASTER_MOSI_LOC == 17) +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 0 +#endif +#if (GSPI_MASTER_MOSI_LOC == 18) +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 12 +#endif +#if (GSPI_MASTER_MOSI_LOC == 19) +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 21 +#endif +#if (GSPI_MASTER_MOSI_LOC == 20) +#define RTE_GSPI_MASTER_MOSI_MUX 12 +#define RTE_GSPI_MASTER_MOSI_PAD 1 +#endif +//Pintool data +#endif // GSPI_MASTER_MISO <0=>P0_11 <1=>P0_26 <2=>P0_47 <3=>P0_56 // MISO of GSPI0 - +#ifndef GSPI_MASTER_MISO_LOC #define RTE_GSPI_MASTER_MISO_PORT_ID 1 #if (RTE_GSPI_MASTER_MISO_PORT_ID == 0) @@ -1883,16 +2906,33 @@ #else #error "Invalid GSPI0 RTE_GSPI_MASTER_MISO_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_GSPI_MASTER_MISO_PORT GSPI_MASTER_MISO__PORT +#define RTE_GSPI_MASTER_MISO_PIN GSPI_MASTER_MISO__PIN +#define RTE_GSPI_MASTER_MISO_MUX 4 +#if (GSPI_MASTER_MISO_LOC == 21) +#define RTE_GSPI_MASTER_MISO_PAD 6 +#endif +#if (GSPI_MASTER_MISO_LOC == 22) +#define RTE_GSPI_MASTER_MISO_PAD 0 +#endif +#if (GSPI_MASTER_MISO_LOC == 23) +#define RTE_GSPI_MASTER_MISO_PAD 11 +#endif +#if (GSPI_MASTER_MISO_LOC == 24) +#define RTE_GSPI_MASTER_MISO_PAD 20 +#endif +//Pintool data +#endif -#if HIGH_THROUGHPUT_EN +#if defined(HIGH_THROUGHPUT_EN) && (HIGH_THROUGHPUT_EN == ENABLE) #define RTE_GSPI_MASTER_CHNL_UDMA_TX_EN 1 #define RTE_GSPI_MASTER_CHNL_UDMA_TX_CH 11 #define RTE_GSPI_MASTER_CHNL_UDMA_RX_EN 1 #define RTE_GSPI_MASTER_CHNL_UDMA_RX_CH 10 -#define RTE_GSPI_CLOCK_SOURCE GSPI_SOC_PLL_CLK - #define RTE_FIFO_AFULL_THRLD 3 #define RTE_FIFO_AEMPTY_THRLD 7 @@ -1905,8 +2945,6 @@ #define RTE_GSPI_MASTER_CHNL_UDMA_RX_EN 0 #define RTE_GSPI_MASTER_CHNL_UDMA_RX_CH 10 -#define RTE_GSPI_CLOCK_SOURCE GSPI_SOC_PLL_CLK - #define RTE_FIFO_AFULL_THRLD 0 #define RTE_FIFO_AEMPTY_THRLD 0 @@ -1922,6 +2960,7 @@ //SCT_IN_0 <0=>GPIO_25 <1=>GPIO_64 <2=>GPIO_68 +#ifndef SCT_IN0_LOC #define RTE_SCT_IN_0_PORT_ID 0 #if (RTE_SCT_IN_0_PORT_ID == 0) @@ -1932,9 +2971,27 @@ #else #error "Invalid RTE_SCT_IN_0_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SCT_IN_0_PORT SCT_IN0_PORT +#if (SCT_IN0_LOC == 0) +#define RTE_SCT_IN_0_PIN SCT_IN0_PIN +#define RTE_SCT_IN_0_MUX 9 +#define RTE_SCT_IN_0_PAD 0 //no pad +#elif (SCT_IN0_LOC == 1) +#define RTE_SCT_IN_0_PIN (SCT_IN0_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_0_MUX 7 +#define RTE_SCT_IN_0_PAD 22 +#elif (SCT_IN0_LOC == 2) +#define RTE_SCT_IN_0_PIN (SCT_IN0_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_0_MUX 9 +#define RTE_SCT_IN_0_PAD 26 +#endif +//Pintool data +#endif //SCT_IN_1 <0=>GPIO_26 <1=>GPIO_65 <2=>GPIO_69 - +#ifndef SCT_IN1_LOC #define RTE_SCT_IN_1_PORT_ID 1 #if (RTE_SCT_IN_1_PORT_ID == 0) @@ -1950,9 +3007,29 @@ #else #error "Invalid RTE_SCT_IN_1_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SCT_IN_1_PORT SCT_IN1_PORT +#if (SCT_IN1_LOC == 3) +#define RTE_SCT_IN_1_PIN SCT_IN1_PIN +#define RTE_SCT_IN_1_MUX 9 +#define RTE_SCT_IN_1_PAD 0 //no pad +#endif +#if (SCT_IN1_LOC == 4) +#define RTE_SCT_IN_1_PIN (SCT_IN1_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_1_MUX 7 +#define RTE_SCT_IN_1_PAD 23 +#endif +#if (SCT_IN1_LOC == 5) +#define RTE_SCT_IN_1_PIN (SCT_IN1_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_1_MUX 9 +#define RTE_SCT_IN_1_PAD 27 +#endif +//Pintool data +#endif //SCT_IN_2 <0=>GPIO_27 <1=>GPIO_66 <2=>GPIO_70 - +#ifndef SCT_IN2_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SCT_IN_2_PORT_ID 0 #else @@ -1977,9 +3054,24 @@ #else #error "Invalid RTE_SCT_IN_0_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SCT_IN_2_PORT SCT_IN2_PORT +#if (SCT_IN2_LOC == 6) +#define RTE_SCT_IN_2_PIN SCT_IN2_PIN +#define RTE_SCT_IN_2_MUX 9 +#define RTE_SCT_IN_2_PAD 0 //no pad +#endif +#if (SCT_IN2_LOC == 7) +#define RTE_SCT_IN_2_PIN (SCT_IN2_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_2_MUX 9 +#define RTE_SCT_IN_2_PAD 28 +#endif +//Pintool data +#endif //SCT_IN_3 <0=>GPIO_28 <1=>GPIO_67 <2=>GPIO_71 - +#ifndef SCT_IN3_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SCT_IN_3_PORT_ID 0 #else @@ -2004,8 +3096,24 @@ #else #error "Invalid RTE_SCT_IN_0_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SCT_IN_3_PORT SCT_IN3_PORT +#if (SCT_IN3_LOC == 8) +#define RTE_SCT_IN_3_PIN SCT_IN3_PIN +#define RTE_SCT_IN_3_MUX 9 +#define RTE_SCT_IN_3_PAD 0 //no pad +#endif +#if (SCT_IN3_LOC == 9) +#define RTE_SCT_IN_3_PIN (SCT_IN3_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_3_MUX 9 +#define RTE_SCT_IN_3_PAD 29 +#endif +//Pintool data +#endif // SCT_OUT_0 <0=>GPIO_29 <1=>GPIO_68 +#ifndef SCT_OUT0_LOC #define RTE_SCT_OUT_0_PORT_ID 0 #if (RTE_SCT_OUT_0_PORT_ID == 0) #define RTE_SCT_OUT_0_PORT 0 @@ -2015,8 +3123,23 @@ #else #error "Invalid RTE_SCT_OUT_0_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SCT_OUT_0_PORT SCT_OUT0_PORT +#if (SCT_OUT0_LOC == 10) +#define RTE_SCT_OUT_0_PIN SCT_OUT0_PIN +#define RTE_SCT_OUT_0_MUX 9 +#define RTE_SCT_OUT_0_PAD 0 //no pad +#elif (SCT_OUT0_LOC == 11) +#define RTE_SCT_OUT_0_PIN (SCT_OUT0_PIN + GPIO_MAX_PIN) +#define RTE_SCT_OUT_0_MUX 7 +#define RTE_SCT_OUT_0_PAD 26 +#endif +//Pintool data +#endif // SCT_OUT_1 <0=>GPIO_30 <1=>GPIO_69 +#ifndef SCT_OUT1_LOC #define RTE_SCT_OUT_1_PORT_ID 0 #if (RTE_SCT_OUT_1_PORT_ID == 0) #define RTE_SCT_OUT_1_PORT 0 @@ -2026,117 +3149,67 @@ #else #error "Invalid RTE_SCT_OUT_1_PIN Pin Configuration!" #endif - -/// SCT_OUT_2 <0=>GPIO_70 <1=>GPIO_8 -#define RTE_SCT_OUT_2_PORT_ID 0 -#if ((RTE_SCT_OUT_2_PORT_ID == 1)) -#error "Invalid RTE_SCT_OUT_2_PIN pin Configuration!" +#else +//Pintool data +#define RTE_SCT_OUT_1_PORT SCT_OUT1_PORT +#if (SCT_OUT1_LOC == 12) +#define RTE_SCT_OUT_1_PIN SCT_OUT1_PIN +#define RTE_SCT_OUT_1_MUX 9 +#define RTE_SCT_OUT_1_PAD 0 //no pad +#elif (SCT_OUT1_LOC == 13) +#define RTE_SCT_OUT_1_PIN (SCT_OUT1_PIN + GPIO_MAX_PIN) +#define RTE_SCT_OUT_1_MUX 7 +#define RTE_SCT_OUT_1_PAD 27 +#endif +//Pintool data #endif -#if (RTE_SCT_OUT_2_PORT_ID == 0) -#define RTE_SCT_OUT_2_PORT 0 -#define RTE_SCT_OUT_2_PIN 70 +//Pintool data +#define RTE_SCT_OUT_2_PORT SCT_OUT2_PORT +#define RTE_SCT_OUT_2_PIN SCT_OUT2_PIN #define RTE_SCT_OUT_2_MUX 7 #define RTE_SCT_OUT_2_PAD 28 -#elif (RTE_SCT_OUT_2_PORT_ID == 1) -#define RTE_SCT_OUT_2_PORT 0 -#define RTE_SCT_OUT_2_PIN 8 -#define RTE_SCT_OUT_2_MUX 12 -#define RTE_SCT_OUT_2_PAD 3 -#else -#error "Invalid RTE_SCT_OUT_2_PIN Pin Configuration!" -#endif -/**/ -//SCT_OUT_3 <0=>GPIO_71 <1=>GPIO_9 -#define RTE_SCT_OUT_3_PORT_ID 0 -#if ((RTE_SCT_OUT_3_PORT_ID == 1)) -#error "Invalid RTE_SCT_OUT_3_PIN pin Configuration!" -#endif +//Pintool data -#if (RTE_SCT_OUT_3_PORT_ID == 0) -#define RTE_SCT_OUT_3_PORT 0 -#define RTE_SCT_OUT_3_PIN 71 +//Pintool data +#define RTE_SCT_OUT_3_PORT SCT_OUT3_PORT +#define RTE_SCT_OUT_3_PIN SCT_OUT3_PIN #define RTE_SCT_OUT_3_MUX 7 #define RTE_SCT_OUT_3_PAD 29 -#elif (RTE_SCT_OUT_3_PORT_ID == 1) -#define RTE_SCT_OUT_3_PORT 0 -#define RTE_SCT_OUT_3_PIN 9 -#define RTE_SCT_OUT_3_MUX 12 -#define RTE_SCT_OUT_3_PAD 4 -#else -#error "Invalid RTE_SCT_OUT_3_PIN Pin Configuration!" -#endif +//Pintool data -//SCT_OUT_4 <0=>GPIO_72 <1=>GPIO_68 - -#define RTE_SCT_OUT_4_PORT_ID 0 -#if ((RTE_SCT_OUT_4_PORT_ID == 1)) -#error "Invalid RTE_SCT_OUT_4_PIN pin Configuration!" -#endif - -#if (RTE_SCT_OUT_4_PORT_ID == 0) -/**/ -#define RTE_SCT_OUT_4_PORT 0 -#define RTE_SCT_OUT_4_PIN 72 +//Pintool data +#define RTE_SCT_OUT_4_PORT SCT_OUT4_PORT +#define RTE_SCT_OUT_4_PIN SCT_OUT4_PIN #define RTE_SCT_OUT_4_MUX 7 #define RTE_SCT_OUT_4_PAD 30 -#else -#error "Invalid RTE_SCT_OUT_4_PIN Pin Configuration!" -#endif -//SCT_OUT_5 <0=>GPIO_73 <1=>GPIO_69 - -#define RTE_SCT_OUT_5_PORT_ID 0 -#if ((RTE_SCT_OUT_5_PORT_ID == 1)) -#error "Invalid RTE_SCT_OUT_5_PIN pin Configuration!" -#endif +//Pintool data -#if (RTE_SCT_OUT_5_PORT_ID == 0) -#define RTE_SCT_OUT_5_PORT 2 -#define RTE_SCT_OUT_5_PIN 73 +//Pintool data +#define RTE_SCT_OUT_5_PORT SCT_OUT5_PORT +#define RTE_SCT_OUT_5_PIN SCT_OUT5_PIN #define RTE_SCT_OUT_5_MUX 7 #define RTE_SCT_OUT_5_PAD 31 -#else -#error "Invalid RTE_SCT_OUT_5_PIN Pin Configuration!" -#endif - -//SCT_OUT_6 <0=>GPIO_74 <1=>GPIO_70 +//Pintool data -#define RTE_SCT_OUT_6_PORT_ID 0 -#if ((RTE_SCT_OUT_6_PORT_ID == 1)) -#error "Invalid RTE_SCT_OUT_6_PIN pin Configuration!" -#endif - -#if (RTE_SCT_OUT_6_PORT_ID == 0) -#define RTE_SCT_OUT_6_PORT 0 -#define RTE_SCT_OUT_6_PIN 74 +//Pintool data +#define RTE_SCT_OUT_6_PORT SCT_OUT6_PORT +#define RTE_SCT_OUT_6_PIN SCT_OUT6_PIN #define RTE_SCT_OUT_6_MUX 7 #define RTE_SCT_OUT_6_PAD 32 -#elif (RTE_SCT_OUT_6_PORT_ID == 1) -#define RTE_SCT_OUT_6_PORT 0 -#define RTE_SCT_OUT_6_PIN 70 -#define RTE_SCT_OUT_6_MUX 13 -#define RTE_SCT_OUT_6_PAD 28 -#else -#error "Invalid RTE_SCT_OUT_6_PIN Pin Configuration!" -#endif - -// SCT_OUT_7 <0=>GPIO_75 <1=>GPIO_71 +//Pintool data -#define RTE_SCT_OUT_7_PORT_ID 0 - -#if (RTE_SCT_OUT_7_PORT_ID == 0) -#define RTE_SCT_OUT_7_PORT 0 -#define RTE_SCT_OUT_7_PIN 75 +//Pintool data +#define RTE_SCT_OUT_7_PORT SCT_OUT7_PORT +#define RTE_SCT_OUT_7_PIN SCT_OUT7_PIN #define RTE_SCT_OUT_7_MUX 7 #define RTE_SCT_OUT_7_PAD 33 -#else -#error "Invalid RTE_SCT_OUT_7_PIN Pin Configuration!" -#endif +//Pintool data // SIO // //<> Serial Input Output //SIO_0 <0=>GPIO_6 <1=>GPIO_25 <2=>GPIO_64 <3=>GPIO_72 - +#ifndef SIO_0_LOC #define RTE_SIO_0_PORT_ID 0 #if (RTE_SIO_0_PORT_ID == 0) @@ -2157,9 +3230,31 @@ #else #error "Invalid RTE_SIO_0_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_0_PORT SIO_SIO0_PORT +#define RTE_SIO_0_MUX 1 +#if (SIO_0_LOC == 0) +#define RTE_SIO_0_PIN SIO_SIO0_PIN +#define RTE_SIO_0_PAD 1 +#endif +#if (SIO_0_LOC == 1) +#define RTE_SIO_0_PIN SIO_SIO0_PIN +#define RTE_SIO_0_PAD 0 +#endif +#if (SIO_0_LOC == 2) +#define RTE_SIO_0_PIN (SIO_SIO0_PIN + GPIO_MAX_PIN) +#define RTE_SIO_0_PAD 22 +#endif +#if (SIO_0_LOC == 3) +#define RTE_SIO_0_PIN (SIO_SIO0_PIN + GPIO_MAX_PIN) +#define RTE_SIO_0_PAD 30 +#endif +//Pintool data +#endif //SIO_1 <0=>GPIO_7 <1=>GPIO_26 <2=>GPIO_65 <3=>GPIO_73 - +#ifndef SIO_1_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SIO_1_PORT_ID 1 #else @@ -2189,9 +3284,31 @@ #else #error "Invalid RTE_SIO_1_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_1_PORT SIO_SIO1_PORT +#define RTE_SIO_1_MUX 1 +#if (SIO_1_LOC == 4) +#define RTE_SIO_1_PIN SIO_SIO1_PIN +#define RTE_SIO_1_PAD 2 +#endif +#if (SIO_1_LOC == 5) +#define RTE_SIO_1_PIN SIO_SIO1_PIN +#define RTE_SIO_1_PAD 0 +#endif +#if (SIO_1_LOC == 6) +#define RTE_SIO_1_PIN (SIO_SIO1_PIN + GPIO_MAX_PIN) +#define RTE_SIO_1_PAD 23 +#endif +#if (SIO_1_LOC == 7) +#define RTE_SIO_1_PIN (SIO_SIO1_PIN + GPIO_MAX_PIN) +#define RTE_SIO_1_PAD 31 +#endif +//Pintool data +#endif // SIO_2 <0=>GPIO_8 <1=>GPIO_27 <2=>GPIO_66 <3=>GPIO_74 - +#ifndef SIO_2_LOC #define RTE_SIO_2_PORT_ID 1 #if (RTE_SIO_2_PORT_ID == 0) @@ -2217,9 +3334,27 @@ #else #error "Invalid RTE_SIO_2_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_2_PORT SIO_SIO2_PORT +#define RTE_SIO_2_MUX 1 +#if (SIO_2_LOC == 8) +#define RTE_SIO_2_PIN SIO_SIO2_PIN +#define RTE_SIO_2_PAD 3 +#endif +#if (SIO_2_LOC == 9) +#define RTE_SIO_2_PIN SIO_SIO2_PIN +#define RTE_SIO_2_PAD 0 +#endif +#if (SIO_2_LOC == 10) +#define RTE_SIO_2_PIN (SIO_SIO2_PIN + GPIO_MAX_PIN) +#define RTE_SIO_2_PAD 32 +#endif +//Pintool data +#endif //SIO_3 <0=>GPIO_9 <1=>GPIO_28 <2=>GPIO_67 <3=>GPIO_75 - +#ifndef SIO_3_LOC #define RTE_SIO_3_PORT_ID 1 #if (RTE_SIO_3_PORT_ID == 0) @@ -2245,8 +3380,27 @@ #else #error "Invalid RTE_SIO_3_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_3_PORT SIO_SIO3_PORT +#define RTE_SIO_3_MUX 1 +#if (SIO_3_LOC == 11) +#define RTE_SIO_3_PIN SIO_SIO3_PIN +#define RTE_SIO_3_PAD 4 +#endif +#if (SIO_3_LOC == 12) +#define RTE_SIO_3_PIN SIO_SIO3_PIN +#define RTE_SIO_3_PAD 0 +#endif +#if (SIO_3_LOC == 13) +#define RTE_SIO_3_PIN (SIO_SIO3_PIN + GPIO_MAX_PIN) +#define RTE_SIO_3_PAD 33 +#endif +//Pintool data +#endif //SIO_4 <0=>GPIO_10 <1=>GPIO_29 <2=>GPIO_68 +#ifndef SIO_4_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SIO_4_PORT_ID 1 #else @@ -2265,8 +3419,27 @@ #else #error "Invalid RTE_SIO_3_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_4_PORT SIO_SIO4_PORT +#define RTE_SIO_4_MUX 1 +#if (SIO_4_LOC == 14) +#define RTE_SIO_4_PAD 5 +#define RTE_SIO_4_PIN SIO_SIO4_PIN +#endif +#if (SIO_4_LOC == 15) +#define RTE_SIO_4_PAD 0 +#define RTE_SIO_4_PIN SIO_SIO4_PIN +#endif +#if (SIO_4_LOC == 16) +#define RTE_SIO_4_PAD 26 +#define RTE_SIO_4_PIN (SIO_SIO4_PIN + GPIO_MAX_PIN) +#endif +//Pintool data +#endif // SIO_5 <0=>GPIO_11 <1=>GPIO_30 <2=>GPIO_69 +#ifndef SIO_5_LOC #define RTE_SIO_5_PORT_ID 0 #if (RTE_SIO_5_PORT_ID == 0) #define RTE_SIO_5_PORT 0 @@ -2281,15 +3454,38 @@ #else #error "Invalid RTE_SIO_5_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_5_PORT SIO_SIO5_PORT +#define RTE_SIO_5_MUX 1 +#if (SIO_5_LOC == 17) +#define RTE_SIO_5_PAD 6 +#define RTE_SIO_5_PIN SIO_SIO5_PIN +#endif +#if (SIO_5_LOC == 18) +#define RTE_SIO_5_PAD 0 +#define RTE_SIO_5_PIN SIO_SIO5_PIN +#endif +#if (SIO_5_LOC == 19) +#define RTE_SIO_5_PAD 0 +#define RTE_SIO_5_PIN (SIO_SIO5_PIN + GPIO_MAX_PIN) +#endif +//Pintool data +#endif // SIO_6 GPIO_70 +#ifndef SIO_6_LOC #define RTE_SIO_6_PORT 0 #define RTE_SIO_6_PIN 70 -#define RTE_SIO_6_MUX 1 -#define RTE_SIO_6_PAD 28 +#else +#define RTE_SIO_6_PORT SIO_SIO6_PORT +#define RTE_SIO_6_PIN (SIO_SIO6_PIN + GPIO_MAX_PIN) +#endif +#define RTE_SIO_6_MUX 1 +#define RTE_SIO_6_PAD 28 // SIO_7 <0=>GPIO_15 <1=>GPIO_71 - +#ifndef SIO_7_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SIO_7_PORT_ID 1 #else @@ -2309,10 +3505,24 @@ #else #error "Invalid RTE_SIO_7_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_7_PORT SIO_SIO7_PORT +#define RTE_SIO_7_MUX 1 +#if (SIO_7_LOC == 21) +#define RTE_SIO_7_PIN SIO_SIO7_PIN +#define RTE_SIO_7_PAD 8 +#endif +#if (SIO_7_LOC == 22) +#define RTE_SIO_7_PIN (SIO_SIO7_PIN + GPIO_MAX_PIN) +#define RTE_SIO_7_PAD 29 +#endif +//Pintool data +#endif //<> Pulse Width Modulation //PWM_1H <0=>GPIO_7 <1=>GPIO_64 <2=>GPIO_65 - +#ifndef PWM_1H_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_PWM_1H_PORT_ID 0 #else @@ -2332,9 +3542,24 @@ #else #error "Invalid RTE_PWM_1H_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_1H_PORT PWM_1H_PORT +#if (PWM_1H_LOC == 0) +#define RTE_PWM_1H_PIN PWM_1H_PIN +#define RTE_PWM_1H_MUX 10 +#define RTE_PWM_1H_PAD 2 +#endif +#if (PWM_1H_LOC == 1) +#define RTE_PWM_1H_PIN (PWM_1H_PIN + GPIO_MAX_PIN) +#define RTE_PWM_1H_MUX 8 +#define RTE_PWM_1H_PAD 22 +#endif +//Pintool data +#endif // PWM_1L <0=>GPIO_6 <1=>GPIO_64 <2=>GPIO_64 - +#ifndef PWM_1L_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_PWM_1L_PORT_ID 0 #else @@ -2349,9 +3574,23 @@ #else #error "Invalid RTE_PWM_1L_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_1L_PORT PWM_1L_PORT +#if (PWM_1L_LOC == 2) +#define RTE_PWM_1L_PIN PWM_1L_PIN +#define RTE_PWM_1L_MUX 10 +#define RTE_PWM_1L_PAD 1 +#elif (PWM_1L_LOC == 3) +#define RTE_PWM_1L_PIN (PWM_1L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_1L_MUX 8 +#define RTE_PWM_1L_PAD 22 +#endif +//Pintool data +#endif //PWM_2H <0=>GPIO_9 <1=>GPIO_67 <2=>GPIO_69 - +#ifndef PWM_2H_LOC #define RTE_PWM_2H_PORT_ID 0 #if ((RTE_PWM_2H_PORT_ID == 2)) #error "Invalid RTE_PWM_2H_PIN pin Configuration!" @@ -2370,9 +3609,24 @@ #else #error "Invalid RTE_PWM_2H_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_2H_PORT PWM_2H_PORT +#if (PWM_2H_LOC == 4) +#define RTE_PWM_2H_PIN PWM_2H_PIN +#define RTE_PWM_2H_MUX 10 +#define RTE_PWM_2H_PAD 4 +#endif +#if (PWM_2H_LOC == 5) +#define RTE_PWM_2H_PIN (PWM_2H_PIN + GPIO_MAX_PIN) +#define RTE_PWM_2H_MUX 12 +#define RTE_PWM_2H_PAD 27 +#endif +//Pintool data +#endif // PWM_2L <0=>GPIO_8 <1=>GPIO_66 <2=>GPIO_68 - +#ifndef PWM_2L_LOC #define RTE_PWM_2L_PORT_ID 0 #if ((RTE_PWM_2L_PORT_ID == 2)) #error "Invalid RTE_PWM_2L_PIN pin Configuration!" @@ -2391,8 +3645,29 @@ #else #error "Invalid RTE_PWM_2L_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_2L_PORT PWM_2L_PORT +#if (PWM_2L_LOC == 6) +#define RTE_PWM_2L_PIN PWM_2L_PIN +#define RTE_PWM_2L_MUX 10 +#define RTE_PWM_2L_PAD 3 +#endif +#if (PWM_2L_LOC == 7) +#define RTE_PWM_2L_PIN (PWM_2L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_2L_MUX 8 +#define RTE_PWM_2L_PAD 24 +#endif +#if (PWM_2L_LOC == 8) +#define RTE_PWM_2L_PIN (PWM_2L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_2L_MUX 12 +#define RTE_PWM_2L_PAD 26 +#endif +//Pintool data +#endif // PWM_3H <0=>GPIO_11 <1=>GPIO_69 +#ifndef PWM_3H_LOC #define RTE_PWM_3H_PORT_ID 0 #if (RTE_PWM_3H_PORT_ID == 0) #define RTE_PWM_3H_PORT 0 @@ -2402,8 +3677,23 @@ #else #error "Invalid RTE_PWM_3H_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_3H_PORT PWM_3H_PORT +#if (PWM_3H_LOC == 9) +#define RTE_PWM_3H_PIN PWM_3H_PIN +#define RTE_PWM_3H_MUX 10 +#define RTE_PWM_3H_PAD 6 +#elif (PWM_3H_LOC == 10) +#define RTE_PWM_3H_PIN (PWM_3H_PIN + GPIO_MAX_PIN) +#define RTE_PWM_3H_MUX 8 +#define RTE_PWM_3H_PAD 27 +#endif +//Pintool data +#endif // PWM_3L <0=>GPIO_10 <1=>GPIO_68 +#ifndef PWM_3L_LOC #define RTE_PWM_3L_PORT_ID 0 #if (RTE_PWM_3L_PORT_ID == 0) @@ -2414,9 +3704,23 @@ #else #error "Invalid RTE_PWM_3L_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_3L_PORT PWM_3L_PORT +#if (PWM_3L_LOC == 11) +#define RTE_PWM_3L_PIN PWM_3L_PIN +#define RTE_PWM_3L_MUX 10 +#define RTE_PWM_3L_PAD 5 +#elif (PWM_3L_LOC == 12) +#define RTE_PWM_3L_PIN (PWM_3L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_3L_MUX 8 +#define RTE_PWM_3L_PAD 26 +#endif +//Pintool data +#endif // PWM_4H <0=>GPIO_15 <1=>GPIO_71 - +#ifndef PWM_4H_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_PWM_4H_PORT_ID 1 #else @@ -2436,9 +3740,17 @@ #else #error "Invalid RTE_PWM_4H_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_4H_PORT PWM_4H_PORT +#define RTE_PWM_4H_PIN (PWM_4H_PIN + GPIO_MAX_PIN) +#define RTE_PWM_4H_MUX 8 +#define RTE_PWM_4H_PAD 29 +//Pintool data +#endif // PWM_4H <0=>GPIO_12 <1=>GPIO_70 - +#ifndef PWM_4L_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_PWM_4L_PORT_ID 1 #else @@ -2458,8 +3770,24 @@ #else #error "Invalid RTE_PWM_4L_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_4L_PORT PWM_4L_PORT +#if (PWM_4L_LOC == 14) +#define RTE_PWM_4L_PIN PWM_4L_PIN +#define RTE_PWM_4L_MUX 10 +#define RTE_PWM_4L_PAD 7 +#endif +#if (PWM_4L_LOC == 15) +#define RTE_PWM_4L_PIN (PWM_4L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_4L_MUX 8 +#define RTE_PWM_4L_PAD 28 +#endif +//Pintool data +#endif // PWM_FAULTA <0=>GPIO_25 <1=>GPIO_68 <1=>GPIO_73 +#ifndef PWM_FAULTA_LOC #define RTE_PWM_FAULTA_PORT_ID 0 #if (RTE_PWM_FAULTA_PORT_ID == 0) @@ -2475,8 +3803,29 @@ #else #error "Invalid RTE_PWM_FAULTA_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_FAULTA_PORT PWM_FAULTA_PORT +#if (PWM_FAULTA_LOC == 16) +#define RTE_PWM_FAULTA_PIN PWM_FAULTA_PIN +#define RTE_PWM_FAULTA_MUX 10 +#define RTE_PWM_FAULTA_PAD 0 //no pad +#endif +#if (PWM_FAULTA_LOC == 17) +#define RTE_PWM_FAULTA_PIN (PWM_FAULTA_PIN + GPIO_MAX_PIN) +#define RTE_PWM_FAULTA_MUX 10 +#define RTE_PWM_FAULTA_PAD 26 +#endif +#if (PWM_FAULTA_LOC == 18) +#define RTE_PWM_FAULTA_PIN (PWM_FAULTA_PIN + GPIO_MAX_PIN) +#define RTE_PWM_FAULTA_MUX 8 +#define RTE_PWM_FAULTA_PAD 31 +#endif +//Pintool data +#endif // PWM_FAULTB <0=>GPIO_26 <1=>GPIO_69 <1=>GPIO_74 +#ifndef PWM_FAULTB_LOC #define RTE_PWM_FAULTB_PORT_ID 0 #if (RTE_PWM_FAULTB_PORT_ID == 0) @@ -2492,13 +3841,42 @@ #else #error "Invalid RTE_PWM_FAULTB_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_FAULTB_PORT PWM_FAULTB_PORT +#if (PWM_FAULTB_LOC == 19) +#define RTE_PWM_FAULTB_PIN PWM_FAULTB_PIN +#define RTE_PWM_FAULTB_MUX 10 +#define RTE_PWM_FAULTB_PAD 0 //no pad +#endif +#if (PWM_FAULTB_LOC == 20) +#define RTE_PWM_FAULTB_PIN (PWM_FAULTB_PIN + GPIO_MAX_PIN) +#define RTE_PWM_FAULTB_MUX 10 +#define RTE_PWM_FAULTB_PAD 27 +#endif +#if (PWM_FAULTB_LOC == 21) +#define RTE_PWM_FAULTB_PIN (PWM_FAULTB_PIN + GPIO_MAX_PIN) +#define RTE_PWM_FAULTB_MUX 8 +#define RTE_PWM_FAULTB_PAD 32 +#endif +//Pintool data +#endif + //PWM_SLP_EVENT_TRIG GPIO_72 +#ifndef PWM_EVTTRIG_LOC #define RTE_PWM_SLP_EVENT_TRIG_PORT 0 #define RTE_PWM_SLP_EVENT_TRIG_PIN 72 -#define RTE_PWM_SLP_EVENT_TRIG_MUX 8 -#define RTE_PWM_SLP_EVENT_TRIG_PAD 30 +#else +//Pintool data +#define RTE_PWM_SLP_EVENT_TRIG_PORT PWM_SLEEP_EVT_TRIG_PORT +#define RTE_PWM_SLP_EVENT_TRIG_PIN (PWM_SLEEP_EVT_TRIG_PIN + GPIO_MAX_PIN) +//Pintool data +#endif +#define RTE_PWM_SLP_EVENT_TRIG_MUX 8 +#define RTE_PWM_SLP_EVENT_TRIG_PAD 30 //PWM_TMR_EXT_TRIG_1 <0=>GPIO_27 <1=>GPIO_51 <2=>GPIO_70 <3=>GPIO_75 +#ifndef PWM_EXTTRIG1_LOC #define RTE_PWM_TMR_EXT_TRIG_1_PORT_ID 0 #if (RTE_PWM_TMR_EXT_TRIG_1_PORT_ID == 0) @@ -2524,8 +3902,34 @@ #else #error "Invalid RTE_PWM_TMR_EXT_TRIG_1_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_TMR_EXT_TRIG_1_PORT PWM_TMR_EXT_TRIG_1_PORT +#if (PWM_EXTTRIG1_LOC == 22) +#define RTE_PWM_TMR_EXT_TRIG_1_PIN PWM_TMR_EXT_TRIG_1_PIN +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 0 //no pad +#endif +#if (PWM_EXTTRIG1_LOC == 23) +#define RTE_PWM_TMR_EXT_TRIG_1_PIN PWM_TMR_EXT_TRIG_1_PIN +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 15 +#endif +#if (PWM_EXTTRIG1_LOC == 24) +#define RTE_PWM_TMR_EXT_TRIG_1_PIN (PWM_TMR_EXT_TRIG_1_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 28 +#endif +#if (PWM_EXTTRIG1_LOC == 25) +#define RTE_PWM_TMR_EXT_TRIG_1_PIN (PWM_TMR_EXT_TRIG_1_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 33 +#endif +//Pintool data +#endif //PWM_TMR_EXT_TRIG_2 <0=>GPIO_28 <1=>GPIO_54 <2=>GPIO_71 +#ifndef PWM_EXTTRIG2_LOC #define RTE_PWM_TMR_EXT_TRIG_2_PORT_ID 0 #if (RTE_PWM_TMR_EXT_TRIG_2_PORT_ID == 0) @@ -2546,6 +3950,71 @@ #else #error "Invalid RTE_PWM_TMR_EXT_TRIG_2_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_TMR_EXT_TRIG_2_PORT PWM_TMR_EXT_TRIG_2_PORT +#if (PWM_EXTTRIG2_LOC == 26) +#define RTE_PWM_TMR_EXT_TRIG_2_PIN PWM_TMR_EXT_TRIG_2_PIN +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 0 //no pad +#endif +#if (PWM_EXTTRIG2_LOC == 27) +#define RTE_PWM_TMR_EXT_TRIG_2_PIN PWM_TMR_EXT_TRIG_2_PIN +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 18 +#endif +#if (PWM_EXTTRIG2_LOC == 28) //Combination not available in pin mux +#define RTE_PWM_TMR_EXT_TRIG_2_PIN (PWM_TMR_EXT_TRIG_2_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 29 +#endif +#if (PWM_EXTTRIG2_LOC == 29) +#define RTE_PWM_TMR_EXT_TRIG_2_PIN (PWM_TMR_EXT_TRIG_2_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 29 +#endif +//Pintool data +#endif + +//PWM_TMR_EXT_TRIG_3 +//Pintool data +#define RTE_PWM_TMR_EXT_TRIG_3_PORT PWM_TMR_EXT_TRIG_3_PORT +#if (PWM_EXTTRIG3_LOC == 30) +#define RTE_PWM_TMR_EXT_TRIG_3_PIN PWM_TMR_EXT_TRIG_3_PIN +#define RTE_PWM_TMR_EXT_TRIG_3_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_3_PAD 0 //no pad +#endif +#if (PWM_EXTTRIG3_LOC == 31) +#define RTE_PWM_TMR_EXT_TRIG_3_PIN PWM_TMR_EXT_TRIG_3_PIN +#define RTE_PWM_TMR_EXT_TRIG_3_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_3_PAD 19 +#endif +#if (PWM_EXTTRIG3_LOC == 32) +#define RTE_PWM_TMR_EXT_TRIG_3_PIN (PWM_TMR_EXT_TRIG_3_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_3_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_3_PAD 30 +#endif +//Pintool data + +//PWM_TMR_EXT_TRIG_4 +//Pintool data +#define RTE_PWM_TMR_EXT_TRIG_4_PORT PWM_TMR_EXT_TRIG_4_PORT +#if (PWM_EXTTRIG4_LOC == 33) +#define RTE_PWM_TMR_EXT_TRIG_4_PIN PWM_TMR_EXT_TRIG_4_PIN +#define RTE_PWM_TMR_EXT_TRIG_4_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_4_PAD 0 //no pad +#endif +#if (PWM_EXTTRIG4_LOC == 34) +#define RTE_PWM_TMR_EXT_TRIG_4_PIN PWM_TMR_EXT_TRIG_4_PIN +#define RTE_PWM_TMR_EXT_TRIG_4_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_4_PAD 14 +#endif +#if (PWM_EXTTRIG4_LOC == 35) +#define RTE_PWM_TMR_EXT_TRIG_4_PIN (PWM_TMR_EXT_TRIG_4_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_4_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_4_PAD 31 +#endif +//Pintool data //<> QEI (Quadrature Encode Interface) @@ -2696,6 +4165,339 @@ #endif +//ADC START + +#ifndef ADC_P0_LOC +#define RTE_ADC_P0_PORT 0 +#define RTE_ADC_P0_PIN 0 +#else +#define RTE_ADC_P0_PORT ADC_P0_PORT +#define RTE_ADC_P0_PIN ADC_P0_PIN +#endif +#define RTE_ADC_P0_MUX 1 + +#ifndef ADC_N0_LOC +#define RTE_ADC_N0_PORT 0 +#define RTE_ADC_N0_PIN 1 +#else +#define RTE_ADC_N0_PORT ADC_N0_PORT +#define RTE_ADC_N0_PIN ADC_N0_PIN +#endif +#define RTE_ADC_N0_MUX 1 + +#ifndef ADC_P1_LOC +#define RTE_ADC_P1_PORT 0 +#define RTE_ADC_P1_PIN 2 +#else +#define RTE_ADC_P1_PORT ADC_P1_PORT +#define RTE_ADC_P1_PIN ADC_P1_PIN +#endif +#define RTE_ADC_P1_MUX 1 + +#ifndef ADC_N1_LOC +#define RTE_ADC_N1_PORT 0 +#define RTE_ADC_N1_PIN 3 +#else +#define RTE_ADC_N1_PORT ADC_N1_PORT +#define RTE_ADC_N1_PIN ADC_N1_PIN +#endif +#define RTE_ADC_N1_MUX 1 + +#ifndef ADC_P2_LOC +#define RTE_ADC_P2_PORT 0 +#define RTE_ADC_P2_PIN 4 +#else +#define RTE_ADC_P2_PORT ADC_P2_PORT +#define RTE_ADC_P2_PIN ADC_P2_PIN +#endif +#define RTE_ADC_P2_MUX 1 + +#ifndef ADC_N2_LOC +#define RTE_ADC_N2_PORT 0 +#define RTE_ADC_N2_PIN 5 +#else +#define RTE_ADC_N2_PORT ADC_N2_PORT +#define RTE_ADC_N2_PIN ADC_N2_PIN +#endif +#define RTE_ADC_N2_MUX 1 + +#ifndef ADC_P3_LOC +#define RTE_ADC_P3_PORT 0 +#define RTE_ADC_P3_PIN 6 +#else +#define RTE_ADC_P3_PORT ADC_P3_PORT +#define RTE_ADC_P3_PIN ADC_P3_PIN +#endif +#define RTE_ADC_P3_MUX 1 + +#ifndef ADC_N3_LOC +#define RTE_ADC_N3_PORT 0 +#define RTE_ADC_N3_PIN 11 +#else +#define RTE_ADC_N3_PORT ADC_N3_PORT +#define RTE_ADC_N3_PIN ADC_N3_PIN +#endif +#define RTE_ADC_N3_MUX 1 + +#ifndef ADC_P4_LOC +#define RTE_ADC_P4_PORT 0 +#define RTE_ADC_P4_PIN 8 +#else +#define RTE_ADC_P4_PORT ADC_P4_PORT +#define RTE_ADC_P4_PIN ADC_P4_PIN +#endif +#define RTE_ADC_P4_MUX 1 + +#ifndef ADC_N4_LOC +#define RTE_ADC_N4_PORT 0 +#define RTE_ADC_N4_PIN 9 +#else +#define RTE_ADC_N4_PORT ADC_N4_PORT +#define RTE_ADC_N4_PIN ADC_N4_PIN +#endif +#define RTE_ADC_N4_MUX 1 + +#ifndef ADC_P5_LOC +#define RTE_ADC_P5_PORT 0 +#define RTE_ADC_P5_PIN 10 +#else +#define RTE_ADC_P5_PORT ADC_P5_PORT +#define RTE_ADC_P5_PIN ADC_P5_PIN +#endif +#define RTE_ADC_P5_MUX 1 + +#ifndef ADC_N5_LOC +#define RTE_ADC_N5_PORT 0 +#define RTE_ADC_N5_PIN 7 +#else +#define RTE_ADC_N5_PORT ADC_N5_PORT +#define RTE_ADC_N5_PIN ADC_N5_PIN +#endif +#define RTE_ADC_N5_MUX 1 + +#ifndef ADC_P6_LOC +#define RTE_ADC_P6_PORT 0 +#define RTE_ADC_P6_PIN 25 +#else +#define RTE_ADC_P6_PORT ADC_P6_PORT +#define RTE_ADC_P6_PIN ADC_P6_PIN +#endif +#define RTE_ADC_P6_MUX 1 +#define RTE_ADC_P6_PAD 0 + +#ifndef ADC_N6_LOC +#define RTE_ADC_N6_PORT 0 +#define RTE_ADC_N6_PIN 26 +#else +#define RTE_ADC_N6_PORT ADC_N6_PORT +#define RTE_ADC_N6_PIN ADC_N6_PIN +#endif +#define RTE_ADC_N6_MUX 1 +#define RTE_ADC_N6_PAD 0 + +#ifndef ADC_P7_LOC +#define RTE_ADC_P7_PORT 0 +#define RTE_ADC_P7_PIN 27 +#else +#define RTE_ADC_P7_PORT ADC_P7_PORT +#define RTE_ADC_P7_PIN ADC_P7_PIN +#endif +#define RTE_ADC_P7_MUX 1 +#define RTE_ADC_P7_PAD 0 + +#ifndef ADC_N7_LOC +#define RTE_ADC_N7_PORT 0 +#define RTE_ADC_N7_PIN 28 +#else +#define RTE_ADC_N7_PORT ADC_N7_PORT +#define RTE_ADC_N7_PIN ADC_N7_PIN +#endif +#define RTE_ADC_N7_MUX 1 +#define RTE_ADC_N7_PAD 0 + +#ifndef ADC_P8_LOC +#define RTE_ADC_P8_PORT 0 +#define RTE_ADC_P8_PIN 29 +#else +#define RTE_ADC_P8_PORT ADC_P8_PORT +#define RTE_ADC_P8_PIN ADC_P8_PIN +#endif +#define RTE_ADC_P8_MUX 1 +#define RTE_ADC_P8_PAD 0 + +#ifndef ADC_N8_LOC +#define RTE_ADC_N8_PORT 0 +#define RTE_ADC_N8_PIN 30 +#else +#define RTE_ADC_N8_PORT ADC_N8_PORT +#define RTE_ADC_N8_PIN ADC_N8_PIN +#endif +#define RTE_ADC_N8_MUX 1 +#define RTE_ADC_N8_PAD 0 + +#ifndef ADC_P10_LOC +#define RTE_ADC_P10_PORT 0 +#define RTE_ADC_P10_PIN 1 +#else +#define RTE_ADC_P10_PORT ADC_P10_PORT +#define RTE_ADC_P10_PIN ADC_P10_PIN +#endif +#define RTE_ADC_P10_MUX 1 + +#ifndef ADC_P11_LOC +#define RTE_ADC_P11_PORT 0 +#define RTE_ADC_P11_PIN 3 +#else +#define RTE_ADC_P11_PORT ADC_P11_PORT +#define RTE_ADC_P11_PIN ADC_P11_PIN +#endif +#define RTE_ADC_P11_MUX 1 + +#ifndef ADC_P12_LOC +#define RTE_ADC_P12_PORT 0 +#define RTE_ADC_P12_PIN 5 +#else +#define RTE_ADC_P12_PORT ADC_P12_PORT +#define RTE_ADC_P12_PIN ADC_P12_PIN +#endif +#define RTE_ADC_P12_MUX 1 + +#ifndef ADC_P13_LOC +#define RTE_ADC_P13_PORT 0 +#define RTE_ADC_P13_PIN 11 +#else +#define RTE_ADC_P13_PORT ADC_P13_PORT +#define RTE_ADC_P13_PIN ADC_P13_PIN +#endif +#define RTE_ADC_P13_MUX 1 + +#ifndef ADC_P14_LOC +#define RTE_ADC_P14_PORT 0 +#define RTE_ADC_P14_PIN 9 +#else +#define RTE_ADC_P14_PORT ADC_P14_PORT +#define RTE_ADC_P14_PIN ADC_P14_PIN +#endif +#define RTE_ADC_P14_MUX 1 + +#ifndef ADC_P15_LOC +#define RTE_ADC_P15_PORT 0 +#define RTE_ADC_P15_PIN 7 +#else +#define RTE_ADC_P15_PORT ADC_P15_PORT +#define RTE_ADC_P15_PIN ADC_P15_PIN +#endif +#define RTE_ADC_P15_MUX 1 + +#ifndef ADC_P16_LOC +#define RTE_ADC_P16_PORT 0 +#define RTE_ADC_P16_PIN 26 +#else +#define RTE_ADC_P16_PORT ADC_P16_PORT +#define RTE_ADC_P16_PIN ADC_P16_PIN +#endif +#define RTE_ADC_P16_MUX 1 +#define RTE_ADC_P16_PAD 0 + +#ifndef ADC_P17_LOC +#define RTE_ADC_P17_PORT 0 +#define RTE_ADC_P17_PIN 28 +#else +#define RTE_ADC_P17_PORT ADC_P17_PORT +#define RTE_ADC_P17_PIN ADC_P17_PIN +#endif +#define RTE_ADC_P17_MUX 1 +#define RTE_ADC_P17_PAD 0 + +#ifndef ADC_P18_LOC +#define RTE_ADC_P18_PORT 0 +#define RTE_ADC_P18_PIN 30 +#else +#define RTE_ADC_P18_PORT ADC_P18_PORT +#define RTE_ADC_P18_PIN ADC_P18_PIN +#endif +#define RTE_ADC_P18_MUX 1 +#define RTE_ADC_P18_PAD 0 + +//ADC END + +//COMPARATOR START + +#ifndef COMP1_P0_LOC +#define RTE_COMP1_P0_PORT 0 +#define RTE_COMP1_P0_PIN 0 +#else +#define RTE_COMP1_P0_PORT COMP1_P0_PORT +#define RTE_COMP1_P0_PIN COMP1_P0_PIN +#endif +#define RTE_COMP1_P0_MUX 0 + +#ifndef COMP1_N0_LOC +#define RTE_COMP1_N0_PORT 0 +#define RTE_COMP1_N0_PIN 1 +#else +#define RTE_COMP1_N0_PORT COMP1_N0_PORT +#define RTE_COMP1_N0_PIN COMP1_N0_PIN +#endif +#define RTE_COMP1_N0_MUX 0 + +#ifndef COMP1_P1_LOC +#define RTE_COMP1_P1_PORT 0 +#define RTE_COMP1_P1_PIN 5 +#else +#define RTE_COMP1_P1_PORT COMP1_P1_PORT +#define RTE_COMP1_P1_PIN COMP1_P1_PIN +#endif +#define RTE_COMP1_P1_MUX 0 + +#ifndef COMP1_N1_LOC +#define RTE_COMP1_N1_PORT 0 +#define RTE_COMP1_N1_PIN 4 +#else +#define RTE_COMP1_N1_PORT COMP1_N1_PORT +#define RTE_COMP1_N1_PIN COMP1_N1_PIN +#endif +#define RTE_COMP1_N1_MUX 0 + +#ifndef COMP2_P0_LOC +#define RTE_COMP2_P0_PORT 0 +#define RTE_COMP2_P0_PIN 2 +#else +#define RTE_COMP2_P0_PORT COMP2_P0_PORT +#define RTE_COMP2_P0_PIN COMP2_P0_PIN +#endif +#define RTE_COMP2_P0_MUX 0 + +#ifndef COMP2_N0_LOC +#define RTE_COMP2_N0_PORT 0 +#define RTE_COMP2_N0_PIN 3 +#else +#define RTE_COMP2_N0_PORT COMP2_N0_PORT +#define RTE_COMP2_N0_PIN COMP2_N0_PIN +#endif +#define RTE_COMP2_N0_MUX 0 + +#ifndef COMP2_P1_LOC +#define RTE_COMP2_P1_PORT 0 +#define RTE_COMP2_P1_PIN 27 +#else +#define RTE_COMP2_P1_PORT COMP2_P1_PORT +#define RTE_COMP2_P1_PIN COMP2_P1_PIN +#endif +#define RTE_COMP2_P1_MUX 0 +#define RTE_COMP2_P1_PAD 0 + +#ifndef COMP2_N1_LOC +#define RTE_COMP2_N1_PORT 0 +#define RTE_COMP2_N1_PIN 28 +#else +#define RTE_COMP2_N1_PORT COMP2_N1_PORT +#define RTE_COMP2_N1_PIN COMP2_N1_PIN +#endif +#define RTE_COMP2_N1_MUX 0 + +//COMPARATOR END + #define RTE_GPIO_6_PORT 0 #define RTE_GPIO_6_PAD 1 #define RTE_GPIO_6_PIN 6 @@ -3095,3 +4897,13 @@ // UULP GPIO as enable pin for sensors #define SENSOR_ENABLE_GPIO_MAPPED_TO_UULP #define SENSOR_ENABLE_GPIO_PIN RTE_UULP_GPIO_1_PIN + +// Memlcd GPIOs +#define RTE_MEMLCD_CS_PIN 10 // Memlcd SPI CS pin +#define RTE_MEMLCD_CS_PORT 0 // Memlcd SPI CS port + +#define RTE_MEMLCD_EXTCOMIN_PIN 3 // Memlcd external communication pin +#define RTE_MEMLCD_EXTCOMIN_PORT 0 // Memlcd external communication port + +#define RTE_MEMLCD_ENABLE_DISPLAY_PIN 0 // Memlcd display enable pin +#define RTE_MEMLCD_ENABLE_DISPLAY_PORT 0 // Memlcd display enable port diff --git a/components/board/silabs/config/brd2605a/pin_config.h b/components/board/silabs/config/brd2605a/pin_config.h new file mode 100644 index 000000000..2bbc8c59c --- /dev/null +++ b/components/board/silabs/config/brd2605a/pin_config.h @@ -0,0 +1,140 @@ +#ifndef PIN_CONFIG_H +#define PIN_CONFIG_H + +// $[USART0] +// [USART0]$ + +// $[UART1] +// [UART1]$ + +// $[ULP_UART] +// [ULP_UART]$ + +// $[I2C0] +// [I2C0]$ + +// $[I2C1] +// [I2C1]$ + +// $[ULP_I2C] +// [ULP_I2C]$ + +// $[SSI_MASTER] +// [SSI_MASTER]$ + +// $[SSI_SLAVE] +// [SSI_SLAVE]$ + +// $[ULP_SPI] +// [ULP_SPI]$ + +// $[GSPI_MASTER] +// [GSPI_MASTER]$ + +// $[I2S0] +// [I2S0]$ + +// $[ULP_I2S] +// [ULP_I2S]$ + +// $[SCT] +// [SCT]$ + +// $[SIO] +// [SIO]$ + +// $[PWM] +// [PWM]$ + +// $[PWM_CH0] +// [PWM_CH0]$ + +// $[PWM_CH1] +// [PWM_CH1]$ + +// $[PWM_CH2] +// [PWM_CH2]$ + +// $[PWM_CH3] +// [PWM_CH3]$ + +// $[ADC_CH1] +// [ADC_CH1]$ + +// $[ADC_CH2] +// [ADC_CH2]$ + +// $[ADC_CH3] +// [ADC_CH3]$ + +// $[ADC_CH4] +// [ADC_CH4]$ + +// $[ADC_CH5] +// [ADC_CH5]$ + +// $[ADC_CH6] +// [ADC_CH6]$ + +// $[ADC_CH7] +// [ADC_CH7]$ + +// $[ADC_CH8] +// [ADC_CH8]$ + +// $[ADC_CH9] +// [ADC_CH9]$ + +// $[ADC_CH10] +// [ADC_CH10]$ + +// $[ADC_CH11] +// [ADC_CH11]$ + +// $[ADC_CH12] +// [ADC_CH12]$ + +// $[ADC_CH13] +// [ADC_CH13]$ + +// $[ADC_CH14] +// [ADC_CH14]$ + +// $[ADC_CH15] +// [ADC_CH15]$ + +// $[ADC_CH16] +// [ADC_CH16]$ + +// $[ADC_CH17] +// [ADC_CH17]$ + +// $[ADC_CH18] +// [ADC_CH18]$ + +// $[ADC_CH19] +// [ADC_CH19]$ + +// $[COMP1] +// [COMP1]$ + +// $[COMP2] +// [COMP2]$ + +// $[DAC0] +// [DAC0]$ + +// $[DAC1] +// [DAC1]$ + +// $[CUSTOM_PIN_NAME] +#ifndef _PORT +#define _PORT 0 +#endif +#ifndef _PIN +#define _PIN 6 +#endif + +// [CUSTOM_PIN_NAME]$ + +#endif // PIN_CONFIG_H diff --git a/components/board/silabs/config/brd4325a/RTE_Device_917.h b/components/board/silabs/config/brd4325a/RTE_Device_917.h index ca4ddce09..7a5fd1bb6 100644 --- a/components/board/silabs/config/brd4325a/RTE_Device_917.h +++ b/components/board/silabs/config/brd4325a/RTE_Device_917.h @@ -60,7 +60,7 @@ #define RTE_USART0 1 -#define RTE_USART0_CLK_SRC USART_INTFPLLCLK +#define RTE_USART0_CLK_SRC USART_ULPREFCLK #define RTE_USART0_CLK_DIV_FACT 1 #define RTE_USART0_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER @@ -174,7 +174,7 @@ #define RTE_USART0_RX_PORT 0 #define RTE_USART0_RX_PIN 65 #define RTE_USART0_RX_MUX 2 -#define RTE_USART0_RX_PAD 24 +#define RTE_USART0_RX_PAD 23 #elif (RTE_USART0_RX_PORT_ID == 4) #define RTE_USART0_RX_PORT 0 #define RTE_USART0_RX_PIN 70 @@ -354,7 +354,7 @@ // Configuration settings for Driver_UART1 in component ::CMSIS Driver:USART #define RTE_UART1 1 -#define RTE_UART1_CLK_SRC USART_INTFPLLCLK +#define RTE_UART1_CLK_SRC USART_ULPREFCLK #define RTE_UART1_CLK_DIV_FACT 1 #define RTE_UART1_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER @@ -3335,3 +3335,13 @@ // GPIO as enable pin for sensors #define SENSOR_ENABLE_GPIO_PORT RTE_GPIO_7_PORT #define SENSOR_ENABLE_GPIO_PIN RTE_GPIO_7_PIN + +// Memlcd GPIOs +#define RTE_MEMLCD_CS_PIN 10 // Memlcd SPI CS pin +#define RTE_MEMLCD_CS_PORT 0 // Memlcd SPI CS port + +#define RTE_MEMLCD_EXTCOMIN_PIN 3 // Memlcd external communication pin +#define RTE_MEMLCD_EXTCOMIN_PORT 0 // Memlcd external communication port + +#define RTE_MEMLCD_ENABLE_DISPLAY_PIN 0 // Memlcd display enable pin +#define RTE_MEMLCD_ENABLE_DISPLAY_PORT 0 // Memlcd display enable port diff --git a/components/board/silabs/config/brd4325b/RTE_Device_917.h b/components/board/silabs/config/brd4325b/RTE_Device_917.h index 3c439ff11..ae139aef4 100644 --- a/components/board/silabs/config/brd4325b/RTE_Device_917.h +++ b/components/board/silabs/config/brd4325b/RTE_Device_917.h @@ -60,7 +60,7 @@ #define RTE_USART0 1 -#define RTE_USART0_CLK_SRC USART_INTFPLLCLK +#define RTE_USART0_CLK_SRC USART_ULPREFCLK #define RTE_USART0_CLK_DIV_FACT 1 #define RTE_USART0_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER @@ -166,7 +166,7 @@ #define RTE_USART0_RX_PORT 0 #define RTE_USART0_RX_PIN 65 #define RTE_USART0_RX_MUX 2 -#define RTE_USART0_RX_PAD 24 +#define RTE_USART0_RX_PAD 23 #elif (RTE_USART0_RX_PORT_ID == 4) #define RTE_USART0_RX_PORT 0 #define RTE_USART0_RX_PIN 70 @@ -336,7 +336,7 @@ // Configuration settings for Driver_UART1 in component ::CMSIS Driver:USART #define RTE_UART1 1 -#define RTE_UART1_CLK_SRC USART_INTFPLLCLK +#define RTE_UART1_CLK_SRC USART_ULPREFCLK #define RTE_UART1_CLK_DIV_FACT 1 #define RTE_UART1_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER @@ -3067,3 +3067,13 @@ // GPIO as enable pin for sensors #define SENSOR_ENABLE_GPIO_PORT RTE_GPIO_7_PORT #define SENSOR_ENABLE_GPIO_PIN RTE_GPIO_7_PIN + +// Memlcd GPIOs +#define RTE_MEMLCD_CS_PIN 10 // Memlcd SPI CS pin +#define RTE_MEMLCD_CS_PORT 0 // Memlcd SPI CS port + +#define RTE_MEMLCD_EXTCOMIN_PIN 3 // Memlcd external communication pin +#define RTE_MEMLCD_EXTCOMIN_PORT 0 // Memlcd external communication port + +#define RTE_MEMLCD_ENABLE_DISPLAY_PIN 0 // Memlcd display enable pin +#define RTE_MEMLCD_ENABLE_DISPLAY_PORT 0 // Memlcd display enable port diff --git a/components/board/silabs/config/brd4325c/RTE_Device_917.h b/components/board/silabs/config/brd4325c/RTE_Device_917.h index 24c4df989..5cb21224a 100644 --- a/components/board/silabs/config/brd4325c/RTE_Device_917.h +++ b/components/board/silabs/config/brd4325c/RTE_Device_917.h @@ -60,7 +60,7 @@ #define RTE_USART0 1 -#define RTE_USART0_CLK_SRC USART_INTFPLLCLK +#define RTE_USART0_CLK_SRC USART_ULPREFCLK #define RTE_USART0_CLK_DIV_FACT 1 #define RTE_USART0_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER @@ -166,7 +166,7 @@ #define RTE_USART0_RX_PORT 0 #define RTE_USART0_RX_PIN 65 #define RTE_USART0_RX_MUX 2 -#define RTE_USART0_RX_PAD 24 +#define RTE_USART0_RX_PAD 23 #elif (RTE_USART0_RX_PORT_ID == 4) #define RTE_USART0_RX_PORT 0 #define RTE_USART0_RX_PIN 70 @@ -336,7 +336,7 @@ // Configuration settings for Driver_UART1 in component ::CMSIS Driver:USART #define RTE_UART1 1 -#define RTE_UART1_CLK_SRC USART_INTFPLLCLK +#define RTE_UART1_CLK_SRC USART_ULPREFCLK #define RTE_UART1_CLK_DIV_FACT 1 #define RTE_UART1_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER @@ -3067,3 +3067,13 @@ // GPIO as enable pin for sensors #define SENSOR_ENABLE_GPIO_PORT RTE_GPIO_7_PORT #define SENSOR_ENABLE_GPIO_PIN RTE_GPIO_7_PIN + +// Memlcd GPIOs +#define RTE_MEMLCD_CS_PIN 10 // Memlcd SPI CS pin +#define RTE_MEMLCD_CS_PORT 0 // Memlcd SPI CS port + +#define RTE_MEMLCD_EXTCOMIN_PIN 3 // Memlcd external communication pin +#define RTE_MEMLCD_EXTCOMIN_PORT 0 // Memlcd external communication port + +#define RTE_MEMLCD_ENABLE_DISPLAY_PIN 0 // Memlcd display enable pin +#define RTE_MEMLCD_ENABLE_DISPLAY_PORT 0 // Memlcd display enable port diff --git a/components/board/silabs/config/brd4325e/RTE_Device_917.h b/components/board/silabs/config/brd4325e/RTE_Device_917.h index b9aabdc42..3b0d88a52 100644 --- a/components/board/silabs/config/brd4325e/RTE_Device_917.h +++ b/components/board/silabs/config/brd4325e/RTE_Device_917.h @@ -36,7 +36,7 @@ #define RTE_USART0 1 -#define RTE_USART0_CLK_SRC USART_INTFPLLCLK +#define RTE_USART0_CLK_SRC USART_ULPREFCLK #define RTE_USART0_CLK_DIV_FACT 1 #define RTE_USART0_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER @@ -144,7 +144,7 @@ #define RTE_USART0_RX_PORT 0 #define RTE_USART0_RX_PIN 65 #define RTE_USART0_RX_MUX 2 -#define RTE_USART0_RX_PAD 24 +#define RTE_USART0_RX_PAD 23 #elif (RTE_USART0_RX_PORT_ID == 4) #define RTE_USART0_RX_PORT 0 #define RTE_USART0_RX_PIN 70 @@ -314,7 +314,7 @@ // Configuration settings for Driver_UART1 in component ::CMSIS Driver:USART #define RTE_UART1 1 -#define RTE_UART1_CLK_SRC USART_INTFPLLCLK +#define RTE_UART1_CLK_SRC USART_ULPREFCLK #define RTE_UART1_CLK_DIV_FACT 1 #define RTE_UART1_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER @@ -3039,3 +3039,13 @@ // GPIO as enable pin for sensors #define SENSOR_ENABLE_GPIO_PORT RTE_GPIO_7_PORT #define SENSOR_ENABLE_GPIO_PIN RTE_GPIO_7_PIN + +// Memlcd GPIOs +#define RTE_MEMLCD_CS_PIN 10 // Memlcd SPI CS pin +#define RTE_MEMLCD_CS_PORT 0 // Memlcd SPI CS port + +#define RTE_MEMLCD_EXTCOMIN_PIN 3 // Memlcd external communication pin +#define RTE_MEMLCD_EXTCOMIN_PORT 0 // Memlcd external communication port + +#define RTE_MEMLCD_ENABLE_DISPLAY_PIN 0 // Memlcd display enable pin +#define RTE_MEMLCD_ENABLE_DISPLAY_PORT 0 // Memlcd display enable port diff --git a/components/board/silabs/config/brd4325f/RTE_Device_917.h b/components/board/silabs/config/brd4325f/RTE_Device_917.h index 5cef54625..0a7d78985 100644 --- a/components/board/silabs/config/brd4325f/RTE_Device_917.h +++ b/components/board/silabs/config/brd4325f/RTE_Device_917.h @@ -62,7 +62,7 @@ #define RTE_USART0 1 -#define RTE_USART0_CLK_SRC USART_INTFPLLCLK +#define RTE_USART0_CLK_SRC USART_ULPREFCLK #define RTE_USART0_CLK_DIV_FACT 1 #define RTE_USART0_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER @@ -168,7 +168,7 @@ #define RTE_USART0_RX_PORT 0 #define RTE_USART0_RX_PIN 65 #define RTE_USART0_RX_MUX 2 -#define RTE_USART0_RX_PAD 24 +#define RTE_USART0_RX_PAD 23 #elif (RTE_USART0_RX_PORT_ID == 4) #define RTE_USART0_RX_PORT 0 #define RTE_USART0_RX_PIN 70 @@ -338,7 +338,7 @@ // Configuration settings for Driver_UART1 in component ::CMSIS Driver:USART #define RTE_UART1 1 -#define RTE_UART1_CLK_SRC USART_INTFPLLCLK +#define RTE_UART1_CLK_SRC USART_ULPREFCLK #define RTE_UART1_CLK_DIV_FACT 1 #define RTE_UART1_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER @@ -3053,3 +3053,13 @@ // GPIO as enable pin for sensors #define SENSOR_ENABLE_GPIO_PORT RTE_GPIO_7_PORT #define SENSOR_ENABLE_GPIO_PIN RTE_GPIO_7_PIN + +// Memlcd GPIOs +#define RTE_MEMLCD_CS_PIN 10 // Memlcd SPI CS pin +#define RTE_MEMLCD_CS_PORT 0 // Memlcd SPI CS port + +#define RTE_MEMLCD_EXTCOMIN_PIN 3 // Memlcd external communication pin +#define RTE_MEMLCD_EXTCOMIN_PORT 0 // Memlcd external communication port + +#define RTE_MEMLCD_ENABLE_DISPLAY_PIN 0 // Memlcd display enable pin +#define RTE_MEMLCD_ENABLE_DISPLAY_PORT 0 // Memlcd display enable port diff --git a/components/board/silabs/config/brd4325g/RTE_Device_917.h b/components/board/silabs/config/brd4325g/RTE_Device_917.h index 1309ac538..393335bb2 100644 --- a/components/board/silabs/config/brd4325g/RTE_Device_917.h +++ b/components/board/silabs/config/brd4325g/RTE_Device_917.h @@ -60,7 +60,7 @@ #define RTE_USART0 1 -#define RTE_USART0_CLK_SRC USART_INTFPLLCLK +#define RTE_USART0_CLK_SRC USART_ULPREFCLK #define RTE_USART0_CLK_DIV_FACT 1 #define RTE_USART0_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER @@ -166,7 +166,7 @@ #define RTE_USART0_RX_PORT 0 #define RTE_USART0_RX_PIN 65 #define RTE_USART0_RX_MUX 2 -#define RTE_USART0_RX_PAD 24 +#define RTE_USART0_RX_PAD 23 #elif (RTE_USART0_RX_PORT_ID == 4) #define RTE_USART0_RX_PORT 0 #define RTE_USART0_RX_PIN 70 @@ -336,7 +336,7 @@ // Configuration settings for Driver_UART1 in component ::CMSIS Driver:USART #define RTE_UART1 1 -#define RTE_UART1_CLK_SRC USART_INTFPLLCLK +#define RTE_UART1_CLK_SRC USART_ULPREFCLK #define RTE_UART1_CLK_DIV_FACT 1 #define RTE_UART1_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER @@ -3067,3 +3067,13 @@ // GPIO as enable pin for sensors #define SENSOR_ENABLE_GPIO_PORT RTE_GPIO_7_PORT #define SENSOR_ENABLE_GPIO_PIN RTE_GPIO_7_PIN + +// Memlcd GPIOs +#define RTE_MEMLCD_CS_PIN 10 // Memlcd SPI CS pin +#define RTE_MEMLCD_CS_PORT 0 // Memlcd SPI CS port + +#define RTE_MEMLCD_EXTCOMIN_PIN 3 // Memlcd external communication pin +#define RTE_MEMLCD_EXTCOMIN_PORT 0 // Memlcd external communication port + +#define RTE_MEMLCD_ENABLE_DISPLAY_PIN 0 // Memlcd display enable pin +#define RTE_MEMLCD_ENABLE_DISPLAY_PORT 0 // Memlcd display enable port diff --git a/components/board/silabs/config/brd4338a/RTE_Device_917.h b/components/board/silabs/config/brd4338a/RTE_Device_917.h index add7bf77a..64cb5a563 100644 --- a/components/board/silabs/config/brd4338a/RTE_Device_917.h +++ b/components/board/silabs/config/brd4338a/RTE_Device_917.h @@ -17,7 +17,7 @@ * * 3. This notice may not be removed or altered from any source distribution. * - * $Date: 1. December 2016 + * $Date: 1. June 2024 * $Revision: V2.4.4 * * Project: RTE Device Configuration for Si91x 2.0 B0 BRD4338A @@ -47,7 +47,7 @@ #define RTE_BUTTON1_PIN (11U) #define RTE_BUTTON1_PAD 6 -#define RTE_LED0_PORT 0 +#define RTE_LED0_PORT 4 #define RTE_LED0_NUMBER 0 #define RTE_LED0_PIN (2U) @@ -63,7 +63,7 @@ #define RTE_USART0 1 -#define RTE_USART0_CLK_SRC USART_INTFPLLCLK +#define RTE_USART0_CLK_SRC USART_ULPREFCLK #define RTE_USART0_CLK_DIV_FACT 1 #define RTE_USART0_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER @@ -225,7 +225,7 @@ #define RTE_USART0_RX_PORT 0 #define RTE_USART0_RX_PIN 65 #define RTE_USART0_RX_MUX 2 -#define RTE_USART0_RX_PAD 24 +#define RTE_USART0_RX_PAD 23 #elif (RTE_USART0_RX_PORT_ID == 4) #define RTE_USART0_RX_PORT 0 #define RTE_USART0_RX_PIN 70 @@ -255,7 +255,7 @@ #if (USART0_RX_LOC == 12) #define RTE_USART0_RX_PIN (USART0_RX_PIN + GPIO_MAX_PIN) #define RTE_USART0_RX_MUX 2 -#define RTE_USART0_RX_PAD 24 +#define RTE_USART0_RX_PAD 23 #endif #if (USART0_RX_LOC == 13) #define RTE_USART0_RX_PIN (USART0_RX_PIN + GPIO_MAX_PIN) @@ -578,7 +578,7 @@ // Configuration settings for Driver_UART1 in component ::CMSIS Driver:USART #define RTE_UART1 1 -#define RTE_UART1_CLK_SRC USART_INTFPLLCLK +#define RTE_UART1_CLK_SRC USART_ULPREFCLK #define RTE_UART1_CLK_DIV_FACT 1 #define RTE_UART1_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER @@ -4887,3 +4887,13 @@ // UULP GPIO as enable pin for sensors #define SENSOR_ENABLE_GPIO_MAPPED_TO_UULP #define SENSOR_ENABLE_GPIO_PIN RTE_UULP_GPIO_1_PIN + +// Memlcd GPIOs +#define RTE_MEMLCD_CS_PIN 10 // Memlcd SPI CS pin +#define RTE_MEMLCD_CS_PORT 0 // Memlcd SPI CS port + +#define RTE_MEMLCD_EXTCOMIN_PIN 3 // Memlcd external communication pin +#define RTE_MEMLCD_EXTCOMIN_PORT 0 // Memlcd external communication port + +#define RTE_MEMLCD_ENABLE_DISPLAY_PIN 0 // Memlcd display enable pin +#define RTE_MEMLCD_ENABLE_DISPLAY_PORT 0 // Memlcd display enable port diff --git a/components/board/silabs/config/brd4338a/pin_config.h b/components/board/silabs/config/brd4338a/pin_config.h index ab6a56743..2bbc8c59c 100644 --- a/components/board/silabs/config/brd4338a/pin_config.h +++ b/components/board/silabs/config/brd4338a/pin_config.h @@ -46,8 +46,74 @@ // $[PWM] // [PWM]$ -// $[ADC] -// [ADC]$ +// $[PWM_CH0] +// [PWM_CH0]$ + +// $[PWM_CH1] +// [PWM_CH1]$ + +// $[PWM_CH2] +// [PWM_CH2]$ + +// $[PWM_CH3] +// [PWM_CH3]$ + +// $[ADC_CH1] +// [ADC_CH1]$ + +// $[ADC_CH2] +// [ADC_CH2]$ + +// $[ADC_CH3] +// [ADC_CH3]$ + +// $[ADC_CH4] +// [ADC_CH4]$ + +// $[ADC_CH5] +// [ADC_CH5]$ + +// $[ADC_CH6] +// [ADC_CH6]$ + +// $[ADC_CH7] +// [ADC_CH7]$ + +// $[ADC_CH8] +// [ADC_CH8]$ + +// $[ADC_CH9] +// [ADC_CH9]$ + +// $[ADC_CH10] +// [ADC_CH10]$ + +// $[ADC_CH11] +// [ADC_CH11]$ + +// $[ADC_CH12] +// [ADC_CH12]$ + +// $[ADC_CH13] +// [ADC_CH13]$ + +// $[ADC_CH14] +// [ADC_CH14]$ + +// $[ADC_CH15] +// [ADC_CH15]$ + +// $[ADC_CH16] +// [ADC_CH16]$ + +// $[ADC_CH17] +// [ADC_CH17]$ + +// $[ADC_CH18] +// [ADC_CH18]$ + +// $[ADC_CH19] +// [ADC_CH19]$ // $[COMP1] // [COMP1]$ diff --git a/components/board/silabs/config/brd4339a/RTE_Device_917.h b/components/board/silabs/config/brd4339a/RTE_Device_917.h index 9314213cd..c061ec27f 100644 --- a/components/board/silabs/config/brd4339a/RTE_Device_917.h +++ b/components/board/silabs/config/brd4339a/RTE_Device_917.h @@ -46,7 +46,7 @@ #define RTE_BUTTON1_PIN (11U) #define RTE_BUTTON1_PAD 6 -#define RTE_LED0_PORT 0 +#define RTE_LED0_PORT 4 #define RTE_LED0_NUMBER 0 #define RTE_LED0_PIN (2U) @@ -62,7 +62,7 @@ #define RTE_USART0 1 -#define RTE_USART0_CLK_SRC USART_INTFPLLCLK +#define RTE_USART0_CLK_SRC USART_ULPREFCLK #define RTE_USART0_CLK_DIV_FACT 1 #define RTE_USART0_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER @@ -86,6 +86,7 @@ // USART0_CLK <0=>P0_8 <1=>P0_25 <2=>P0_52 <3=>P0_64 // CLK of USART0 +#ifndef USART0_CLK_LOC #define RTE_USART0_CLK_PORT_ID 0 #if (RTE_USART0_CLK_PORT_ID == 0) @@ -106,10 +107,35 @@ #else #error "Invalid USART0 RTE_USART0_CLK_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_CLK_PORT USART0_CLK_PORT +#if (USART0_CLK_LOC == 0) +#define RTE_USART0_CLK_PIN USART0_CLK_PIN +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 3 +#endif +#if (USART0_CLK_LOC == 1) +#define RTE_USART0_CLK_PIN USART0_CLK_PIN +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 0 //NO PAD +#endif +#if (USART0_CLK_LOC == 2) +#define RTE_USART0_CLK_PIN USART0_CLK_PIN +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 16 +#endif +#if (USART0_CLK_LOC == 3) +#define RTE_USART0_CLK_PIN (USART0_CLK_PIN + GPIO_MAX_PIN) +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 22 +#endif +//Pintool data +#endif // USART0_TX <0=>P0_15 <1=>P0_30 <2=>P0_54 <3=>P0_68 <4=>P0_71 // TX for USART0 - +#ifndef USART0_TX_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_USART0_TX_PORT_ID 1 #else @@ -139,10 +165,40 @@ #else #error "Invalid USART0 RTE_USART0_TX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_TX_PORT USART0_TX_PORT +#if (USART0_TX_LOC == 4) +#define RTE_USART0_TX_PIN USART0_TX_PIN +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 8 +#endif +#if (USART0_TX_LOC == 5) +#define RTE_USART0_TX_PIN USART0_TX_PIN +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 0 //NO PAD +#endif +#if (USART0_TX_LOC == 6) +#define RTE_USART0_TX_PIN USART0_TX_PIN +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 18 +#endif +#if (USART0_TX_LOC == 7) +#define RTE_USART0_TX_PIN (USART0_TX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 26 +#endif +#if (USART0_TX_LOC == 8) +#define RTE_USART0_TX_PIN (USART0_TX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_TX_MUX 4 +#define RTE_USART0_TX_PAD 29 +#endif +//Pintool data +#endif // USART0_RX <0=>P0_10 <1=>P0_29 <2=>P0_55 <3=>P0_65 <4=>P0_70 // RX for USART0 - +#ifndef USART0_RX_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_USART0_RX_PORT_ID 1 #else @@ -168,7 +224,7 @@ #define RTE_USART0_RX_PORT 0 #define RTE_USART0_RX_PIN 65 #define RTE_USART0_RX_MUX 2 -#define RTE_USART0_RX_PAD 24 +#define RTE_USART0_RX_PAD 23 #elif (RTE_USART0_RX_PORT_ID == 4) #define RTE_USART0_RX_PORT 0 #define RTE_USART0_RX_PIN 70 @@ -177,9 +233,40 @@ #else #error "Invalid USART0 RTE_USART0_RX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_RX_PORT USART0_RX_PORT +#if (USART0_RX_LOC == 9) +#define RTE_USART0_RX_PIN USART0_RX_PIN +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 5 +#endif +#if (USART0_RX_LOC == 10) +#define RTE_USART0_RX_PIN USART0_RX_PIN +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 0 //no pad +#endif +#if (USART0_RX_LOC == 11) +#define RTE_USART0_RX_PIN USART0_RX_PIN +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 19 +#endif +#if (USART0_RX_LOC == 12) +#define RTE_USART0_RX_PIN (USART0_RX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 23 +#endif +#if (USART0_RX_LOC == 13) +#define RTE_USART0_RX_PIN (USART0_RX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_RX_MUX 4 +#define RTE_USART0_RX_PAD 28 +#endif +//Pintool data +#endif // USART0_CTS <0=>P0_6 <1=>P0_26 <2=>P0_56 <3=>P0_70 // CTS for USART0 +#ifndef USART0_CTS_LOC #define RTE_USART0_CTS_PORT_ID 0 #if (RTE_USART0_CTS_PORT_ID == 0) @@ -205,9 +292,35 @@ #else #error "Invalid USART0 RTE_USART0_CTS_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_CTS_PORT USART0_CTS_PORT +#if (USART0_CTS_LOC == 14) +#define RTE_USART0_CTS_PIN USART0_CTS_PIN +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 1 +#endif +#if (USART0_CTS_LOC == 15) +#define RTE_USART0_CTS_PIN USART0_CTS_PIN +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 0 //NO PAD +#endif +#if (USART0_CTS_LOC == 16) +#define RTE_USART0_CTS_PIN USART0_CTS_PIN +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 20 +#endif +#if (USART0_CTS_LOC == 17) +#define RTE_USART0_CTS_PIN (USART0_CTS_PIN + GPIO_MAX_PIN) +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 28 +#endif +//Pintool data +#endif // USART0_RTS <0=>P0_9 <1=>P0_28 <2=>P0_53 <3=>P0_69 // RTS for USART0 +#ifndef USART0_RTS_LOC #define RTE_USART0_RTS_PORT_ID 0 #if (RTE_USART0_RTS_PORT_ID == 0) @@ -228,10 +341,35 @@ #else #error "Invalid USART0 RTE_USART0_RTS_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_RTS_PORT USART0_RTS_PORT +#if (USART0_RTS_LOC == 18) +#define RTE_USART0_RTS_PIN USART0_RTS_PIN +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 4 +#endif +#if (USART0_RTS_LOC == 19) +#define RTE_USART0_RTS_PIN USART0_RTS_PIN +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 0 //NO PAD +#endif +#if (USART0_RTS_LOC == 20) +#define RTE_USART0_RTS_PIN USART0_RTS_PIN +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 17 +#endif +#if (USART0_RTS_LOC == 21) +#define RTE_USART0_RTS_PIN (USART0_RTS_PIN + GPIO_MAX_PIN) +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 27 +#endif +//Pintool data +#endif // USART0_IR_TX <0=>P0_48 <1=>P0_72 // IR TX for USART0 - +#ifndef USART0_IRTX_LOC #define RTE_IR_TX_PORT_ID 0 #if ((RTE_IR_TX_PORT_ID == 2)) #error "Invalid USART0 RTE_USART0_IR_TX_PIN Pin Configuration!" @@ -255,10 +393,35 @@ #else #error "Invalid USART0 RTE_USART0_IR_TX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_IR_TX_PORT USART0_IRTX_PORT +#if (USART0_IRTX_LOC == 22) +#define RTE_USART0_IR_TX_PIN USART0_IRTX_PIN +#define RTE_USART0_IR_TX_MUX 13 +#define RTE_USART0_IR_TX_PAD 0 //No pad +#endif +#if (USART0_IRTX_LOC == 23) +#define RTE_USART0_IR_TX_PIN USART0_IRTX_PIN +#define RTE_USART0_IR_TX_MUX 2 +#define RTE_USART0_IR_TX_PAD 12 +#endif +#if (USART0_IRTX_LOC == 24) +#define RTE_USART0_IR_TX_PIN (USART0_IRTX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_IR_TX_MUX 11 +#define RTE_USART0_IR_TX_PAD 23 +#endif +#if (USART0_IRTX_LOC == 25) +#define RTE_USART0_IR_TX_PIN (USART0_IRTX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_IR_TX_MUX 2 +#define RTE_USART0_IR_TX_PAD 30 +#endif +//Pintool data +#endif // USART0_IR_RX <0=>P0_47 <1=>P0_71 <2=>P0_64 <3=>P0_25 // IR RX for USART0 - +#ifndef USART0_IRRX_LOC #define RTE_IR_RX_PORT_ID 0 #if ((RTE_IR_RX_PORT_ID == 2)) #error "Invalid USART0 RTE_USART0_IR_RX_PIN Pin Configuration!" @@ -282,9 +445,35 @@ #else #error "Invalid USART0 RTE_USART0_IR_RX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_IR_RX_PORT USART0_IRRX_PORT +#if (USART0_IRRX_LOC == 26) +#define RTE_USART0_IR_RX_PIN USART0_IRRX_PIN +#define RTE_USART0_IR_RX_MUX 13 +#define RTE_USART0_IR_RX_PAD 0 //no pad +#endif +#if (USART0_IRRX_LOC == 27) +#define RTE_USART0_IR_RX_PIN USART0_IRRX_PIN +#define RTE_USART0_IR_RX_MUX 2 +#define RTE_USART0_IR_RX_PAD 11 +#endif +#if (USART0_IRRX_LOC == 28) +#define RTE_USART0_IR_RX_PIN (USART0_IRRX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_IR_RX_MUX 11 +#define RTE_USART0_IR_RX_PAD 22 +#endif +#if (USART0_IRRX_LOC == 29) +#define RTE_USART0_IR_RX_PIN (USART0_IRRX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_IR_RX_MUX 2 +#define RTE_USART0_IR_RX_PAD 29 +#endif +//Pintool data +#endif // USART0_RI <0=>P0_27 <1=>P0_46 <2=>P0_68 // RI for USART0 +#ifndef USART0_RI_LOC #define RTE_RI_PORT_ID 0 #if (RTE_RI_PORT_ID == 0) @@ -300,9 +489,30 @@ #else #error "Invalid USART0 RTE_USART0_RI_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_RI_PORT USART0_RI_PORT +#if (USART0_RI_LOC == 30) +#define RTE_USART0_RI_PIN USART0_RI_PIN +#define RTE_USART0_RI_MUX 2 +#define RTE_USART0_RI_PAD 0 //no pad +#endif +#if (USART0_RI_LOC == 31) +#define RTE_USART0_RI_PIN USART0_RI_PIN +#define RTE_USART0_RI_MUX 2 +#define RTE_USART0_RI_PAD 10 +#endif +#if (USART0_RI_LOC == 32) +#define RTE_USART0_RI_PIN (USART0_RI_PIN + GPIO_MAX_PIN) +#define RTE_USART0_RI_MUX 11 +#define RTE_USART0_RI_PAD 26 +#endif +//Pintool data +#endif // USART0_DSR <0=>P0_11 <1=>P0_57 // DSR for USART0 +#ifndef USART0_DSR_LOC #define RTE_DSR_PORT_ID 0 #if (RTE_DSR_PORT_ID == 0) @@ -318,27 +528,56 @@ #else #error "Invalid USART0 RTE_USART0_RI_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_DSR_PORT USART0_DSR_PORT +#define RTE_USART0_DSR_PIN USART0_DSR_PIN +#if (USART0_DSR_LOC == 33) +#define RTE_USART0_DSR_MUX 2 +#define RTE_USART0_DSR_PAD 6 +#endif +#if (USART0_DSR_LOC == 34) +#define RTE_USART0_DSR_MUX 2 +#define RTE_USART0_DSR_PAD 21 +#endif +//Pintool data +#endif + // USART0_DCD <0=>P0_12 <1=>P0_29 // DCD for USART0 - +#ifndef USART0_DCD_LOC #define RTE_USART0_DCD_PORT 0 #define RTE_USART0_DCD_PIN 12 -#define RTE_USART0_DCD_MUX 2 -#define RTE_USART0_DCD_PAD 7 +#else +#define RTE_USART0_DCD_PORT USART0_DCD_PORT +#define RTE_USART0_DCD_PIN USART0_DCD_PIN +#if (USART0_DCD_LOC == 35) +#define RTE_USART0_DCD_MUX 2 +#define RTE_USART0_DCD_PAD 7 +#elif (USART0_DCD_LOC == 36) +#define RTE_USART0_DCD_MUX 12 +#define RTE_USART0_DCD_PAD 0 +#endif +#endif // USART0_DTR <0=>P0_7 // DTR for USART0 +#ifndef USART0_DTR_LOC #define RTE_USART0_DTR_PORT 0 #define RTE_USART0_DTR_PIN 7 -#define RTE_USART0_DTR_MUX 2 -#define RTE_USART0_DTR_PAD 2 +#else +#define RTE_USART0_DTR_PORT USART0_DTR_PORT +#define RTE_USART0_DTR_PIN USART0_DTR_PIN +#endif +#define RTE_USART0_DTR_MUX 2 +#define RTE_USART0_DTR_PAD 2 // // UART1 [Driver_UART1] // Configuration settings for Driver_UART1 in component ::CMSIS Driver:USART #define RTE_UART1 1 -#define RTE_UART1_CLK_SRC USART_INTFPLLCLK +#define RTE_UART1_CLK_SRC USART_ULPREFCLK #define RTE_UART1_CLK_DIV_FACT 1 #define RTE_UART1_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER @@ -358,7 +597,7 @@ /*UART1 PINS*/ // UART1_TX <0=>P0_7 <1=>P0_30 <2=>P0_67 <3=>P0_69 <4=>P0_73 <5=>P0_75 <6=>P0_34 // TX of UART1 - +#ifndef UART1_TX_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_UART1_TX_PORT_ID 0 #else @@ -397,10 +636,40 @@ #else #error "Invalid UART1 RTE_UART1_TX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_UART1_TX_PORT UART1_TX_PORT +#if (UART1_TX_LOC == 0) +#define RTE_UART1_TX_PIN UART1_TX_PIN +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 2 +#endif +#if (UART1_TX_LOC == 1) +#define RTE_UART1_TX_PIN UART1_TX_PIN +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 0 //no pad +#endif +#if (UART1_TX_LOC == 2) +#define RTE_UART1_TX_PIN (UART1_TX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 27 +#endif +#if (UART1_TX_LOC == 3) +#define RTE_UART1_TX_PIN (UART1_TX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 31 +#endif +#if (UART1_TX_LOC == 4) +#define RTE_UART1_TX_PIN (UART1_TX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_TX_MUX 9 +#define RTE_UART1_TX_PAD 33 +#endif +//Pintool data +#endif // UART1_RX <0=>P0_6 <1=>P0_29 <2=>P0_66 <3=>P0_68 <4=>P0_72 <5=>P0_74 <6=>P0_33 // RX of UART1 - +#ifndef UART1_RX_LOC #define RTE_UART1_RX_PORT_ID 0 #if (RTE_UART1_RX_PORT_ID == 0) @@ -431,9 +700,40 @@ #else #error "Invalid UART1 RTE_UART1_RX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_UART1_RX_PORT UART1_RX_PORT +#if (UART1_RX_LOC == 5) +#define RTE_UART1_RX_PIN UART1_RX_PIN +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 1 +#endif +#if (UART1_RX_LOC == 6) +#define RTE_UART1_RX_PIN UART1_RX_PIN +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 0 //no pad +#endif +#if (UART1_RX_LOC == 7) +#define RTE_UART1_RX_PIN (UART1_RX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 26 +#endif +#if (UART1_RX_LOC == 8) +#define RTE_UART1_RX_PIN (UART1_RX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 30 +#endif +#if (UART1_RX_LOC == 9) +#define RTE_UART1_RX_PIN (UART1_RX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RX_MUX 9 +#define RTE_UART1_RX_PAD 32 +#endif +//Pintool data +#endif // UART1_CTS <0=>P0_11 <1=>P0_28 <2=>P0_51 <3=>P0_65 <4=>P0_71 <5=>P0_73 <6=>P0_32 // CTS of UART1 +#ifndef UART1_CTS_LOC #define RTE_UART1_CTS_PORT_ID 0 #if (RTE_UART1_CTS_PORT_ID == 0) @@ -464,10 +764,45 @@ #else #error "Invalid UART1 RTE_UART1_CTS_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_UART1_CTS_PORT UART1_CTS_PORT +#if (UART1_CTS_LOC == 10) +#define RTE_UART1_CTS_PIN UART1_CTS_PIN +#define RTE_UART1_CTS_MUX 6 +#define RTE_UART1_CTS_PAD 6 +#endif +#if (UART1_CTS_LOC == 11) +#define RTE_UART1_CTS_PIN UART1_CTS_PIN +#define RTE_UART1_CTS_MUX 6 +#define RTE_UART1_CTS_PAD 0 //no pad +#endif +#if (UART1_CTS_LOC == 12) +#define RTE_UART1_CTS_PIN UART1_CTS_PIN +#define RTE_UART1_CTS_MUX 9 +#define RTE_UART1_CTS_PAD 15 +#endif +#if (UART1_CTS_LOC == 13) +#define RTE_UART1_CTS_PIN (UART1_CTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_CTS_MUX 9 +#define RTE_UART1_CTS_PAD 23 +#endif +#if (UART1_CTS_LOC == 14) +#define RTE_UART1_CTS_PIN (UART1_CTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_CTS_MUX 6 +#define RTE_UART1_CTS_PAD 29 +#endif +#if (UART1_CTS_LOC == 15) +#define RTE_UART1_CTS_PIN (UART1_CTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_CTS_MUX 9 +#define RTE_UART1_CTS_PAD 31 +#endif +//Pintool data +#endif // UART1_RTS <0=>P0_10 <1=>P0_27 <2=>P0_50 <3=>P0_64 <4=>P0_70 <5=>P0_72 <6=>P0_31 // RTS of UART1 - +#ifndef UART1_RTS_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_UART1_RTS_PORT_ID 0 #else @@ -502,6 +837,42 @@ #else #error "Invalid UART1 RTE_UART1_RTS_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_UART1_RTS_PORT UART1_RTS_PORT +#if (UART1_RTS_LOC == 16) +#define RTE_UART1_RTS_PIN UART1_RTS_PIN +#define RTE_UART1_RTS_MUX 6 +#define RTE_UART1_RTS_PAD 5 +#endif +#if (UART1_RTS_LOC == 17) +#define RTE_UART1_RTS_PIN UART1_RTS_PIN +#define RTE_UART1_RTS_MUX 6 +#define RTE_UART1_RTS_PAD 0 //no pad +#endif +#if (UART1_RTS_LOC == 18) +#define RTE_UART1_RTS_PIN UART1_RTS_PIN +#define RTE_UART1_RTS_MUX 9 +#define RTE_UART1_RTS_PAD 14 +#endif +#if (UART1_RTS_LOC == 19) +#define RTE_UART1_RTS_PIN (UART1_RTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RTS_MUX 9 +#define RTE_UART1_RTS_PAD 22 +#endif +#if (UART1_RTS_LOC == 20) +#define RTE_UART1_RTS_PIN (UART1_RTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RTS_MUX 6 +#define RTE_UART1_RTS_PAD 28 +#endif +#if (UART1_RTS_LOC == 21) +#define RTE_UART1_RTS_PIN (UART1_RTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RTS_MUX 9 +#define RTE_UART1_RTS_PAD 30 +#endif +//Pintool data +#endif + // // ULP_UART [Driver_ULP_UART] @@ -528,6 +899,7 @@ /*ULPSS UART PINS*/ // UART1_TX <0=>P0_3 <1=>P0_7 <2=>P0_11 // TX of ULPSS UART +#ifndef ULP_UART_TX_LOC #define RTE_ULP_UART_TX_PORT_ID 1 #if (RTE_ULP_UART_TX_PORT_ID == 0) #define RTE_ULP_UART_TX_PORT 0 @@ -540,9 +912,17 @@ #else #error "Invalid ULPSS UART RTE_ULP_UART_TX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_ULP_UART_TX_PORT ULP_UART_TX_PORT +#define RTE_ULP_UART_TX_PIN ULP_UART_TX_PIN +#define RTE_ULP_UART_TX_MUX 3 +//Pintool data +#endif // UART1_RX <0=>P0_2 <1=>P0_6 <2=>P0_9 // RX of ULPSS UART +#ifndef ULP_UART_RX_LOC #define RTE_ULP_UART_RX_PORT_ID 2 #if (RTE_ULP_UART_RX_PORT_ID == 0) #define RTE_ULP_UART_RX_PORT 0 @@ -559,9 +939,17 @@ #else #error "Invalid ULPSS UART RTE_ULP_UART_RX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_ULP_UART_RX_PORT ULP_UART_RX_PORT +#define RTE_ULP_UART_RX_PIN ULP_UART_RX_PIN +#define RTE_ULP_UART_RX_MUX 3 +//Pintool data +#endif // UART1_CTS <0=>P0_1 <1=>P0_5 <2=>P0_8 // CTS of ULPSS UART +#ifndef ULP_UART_CTS_LOC #define RTE_ULP_UART_CTS_PORT_ID 0 #if (RTE_ULP_UART_CTS_PORT_ID == 0) #define RTE_ULP_UART_CTS_PORT 0 @@ -574,17 +962,30 @@ #else #error "Invalid ULPSS UART RTE_ULP_UART_CTS_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_ULP_UART_CTS_PORT ULP_UART_CTS_PORT +#define RTE_ULP_UART_CTS_PIN ULP_UART_CTS_PIN +#define RTE_ULP_UART_CTS_MUX 3 +//Pintool data +#endif // UART1_RTS <0=>P0_0 <1=>P0_4 <2=>P0_10 // RTS of ULPSS UART +#ifndef ULP_UART_RTS_LOC #define RTE_ULP_UART_RTS_PORT_ID 0 #if (RTE_ULP_UART_RTS_PORT_ID == 0) #define RTE_ULP_UART_RTS_PORT 0 #define RTE_ULP_UART_RTS_PIN 10 -#define RTE_ULP_UART_RTS_MUX 8 #else #error "Invalid ULPSS UART RTE_ULP_UART_RTS_PIN Pin Configuration!" #endif +#else +#define RTE_ULP_UART_RTS_PORT ULP_UART_RTS_PORT +#define RTE_ULP_UART_RTS_PIN ULP_UART_RTS_PIN +#endif +#define RTE_ULP_UART_RTS_MUX 8 + // // SSI_MASTER (Serial Peripheral Interface 1) [Driver_SSI_MASTER] @@ -592,7 +993,7 @@ #define RTE_SSI_MASTER 1 // SSI_MASTER_MISO Pin <0=>GPIO_12 <1=>GPIO_27 <2=>GPIO_57 - +#ifndef SSI_MASTER_DATA1_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SSI_MASTER_MISO_PORT_ID 1 #else @@ -620,8 +1021,26 @@ #else #error "Invalid SSI_MASTER_MISO Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_MASTER_MISO 1 +#define RTE_SSI_MASTER_MISO_PORT SSI_MASTER_MISO_DATA1_PORT +#define RTE_SSI_MASTER_MISO_PIN SSI_MASTER_MISO_DATA1_PIN +#define RTE_SSI_MASTER_MISO_MODE EGPIO_PIN_MUX_MODE3 +#if (SSI_MASTER_DATA1_LOC == 3) +#define RTE_SSI_MASTER_MISO_PADSEL 7 +#endif +#if (SSI_MASTER_DATA1_LOC == 4) +#define RTE_SSI_MASTER_MISO_PADSEL 0 //NO PAD +#endif +#if (SSI_MASTER_DATA1_LOC == 5) +#define RTE_SSI_MASTER_MISO_PADSEL 21 +#endif +//Pintool data +#endif // SSI_MASTER_MOSI Pin <0=>GPIO_11 <1=>GPIO_26 <2=>GPIO_56 +#ifndef SSI_MASTER_DATA0_LOC #define RTE_SSI_MASTER_MOSI_PORT_ID 1 #if (RTE_SSI_MASTER_MOSI_PORT_ID == 0) @@ -645,8 +1064,26 @@ #else #error "Invalid SSI_MASTER_MOSI Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_MASTER_MOSI 1 +#define RTE_SSI_MASTER_MOSI_PORT SSI_MASTER_MOSI_DATA0_PORT +#define RTE_SSI_MASTER_MOSI_PIN SSI_MASTER_MOSI_DATA0_PIN +#define RTE_SSI_MASTER_MOSI_MODE EGPIO_PIN_MUX_MODE3 +#if (SSI_MASTER_DATA0_LOC == 0) +#define RTE_SSI_MASTER_MOSI_PADSEL 6 +#endif +#if (SSI_MASTER_DATA0_LOC == 1) +#define RTE_SSI_MASTER_MOSI_PADSEL 0 //NO PAD +#endif +#if (SSI_MASTER_DATA0_LOC == 2) +#define RTE_SSI_MASTER_MOSI_PADSEL 20 +#endif +//Pintool data +#endif // SSI_MASTER_SCK Pin <0=>GPIO_8 <1=>GPIO_25 <2=>GPIO_52 +#ifndef SSI_MASTER_SCK_LOC #define RTE_SSI_MASTER_SCK_PORT_ID 1 #if (RTE_SSI_MASTER_SCK_PORT_ID == 0) @@ -670,6 +1107,23 @@ #else #error "Invalid SSI_MASTER_SCK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_MASTER_SCK 1 +#define RTE_SSI_MASTER_SCK_PORT SSI_MASTER_SCK__PORT +#define RTE_SSI_MASTER_SCK_PIN SSI_MASTER_SCK__PIN +#define RTE_SSI_MASTER_SCK_MODE EGPIO_PIN_MUX_MODE3 +#if (SSI_MASTER_SCK_LOC == 6) +#define RTE_SSI_MASTER_SCK_PADSEL 3 +#endif +#if (SSI_MASTER_SCK_LOC == 7) +#define RTE_SSI_MASTER_SCK_PADSEL 0 //NO PAD +#endif +#if (SSI_MASTER_SCK_LOC == 8) +#define RTE_SSI_MASTER_SCK_PADSEL 16 +#endif +//Pintool data +#endif #define M4_SSI_CS0 1 #define M4_SSI_CS1 0 @@ -677,6 +1131,7 @@ #define M4_SSI_CS3 0 // SSI_MASTER_CS Pin <0=>GPIO_9 <1=>GPIO_28 <2=>GPIO_53 <3=>GPIO_10 <4=>GPIO_15 <5=>GPIO_50 <6=>GPIO_51 +#ifndef SSI_MASTER_CS0_LOC #define RTE_SSI_MASTER_CS0_PORT_ID 1 #if (RTE_SSI_MASTER_CS0_PORT_ID == 0) @@ -700,20 +1155,43 @@ #else #error "Invalid SSI_MASTER_CS0 Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_MASTER_CS0 M4_SSI_CS0 +#define RTE_SSI_MASTER_CS0_PORT SSI_MASTER_CS0__PORT +#define RTE_SSI_MASTER_CS0_PIN SSI_MASTER_CS0__PIN +#define RTE_SSI_MASTER_CS0_MODE EGPIO_PIN_MUX_MODE3 +#if (SSI_MASTER_CS0_LOC == 9) +#define RTE_SSI_MASTER_CS0_PADSEL 4 +#endif +#if (SSI_MASTER_CS0_LOC == 10) +#define RTE_SSI_MASTER_CS0_PADSEL 0 //NO PAD +#endif +#if (SSI_MASTER_CS0_LOC == 11) +#define RTE_SSI_MASTER_CS0_PADSEL 17 +#endif +//Pintool data +#endif //CS1 +#ifndef SSI_MASTER_CS1_LOC #define RTE_SSI_MASTER_CS1_PORT_ID 0 #if (RTE_SSI_MASTER_CS1_PORT_ID == 0) -#define RTE_SSI_MASTER_CS1 M4_SSI_CS1 -#define RTE_SSI_MASTER_CS1_PORT 0 -#define RTE_SSI_MASTER_CS1_PIN 10 -#define RTE_SSI_MASTER_CS1_MODE EGPIO_PIN_MUX_MODE3 -#define RTE_SSI_MASTER_CS1_PADSEL 5 +#define RTE_SSI_MASTER_CS1_PORT 0 +#define RTE_SSI_MASTER_CS1_PIN 10 #else #error "Invalid SSI_MASTER_CS1 Pin Configuration!" #endif +#else +#define RTE_SSI_MASTER_CS1_PORT SSI_MASTER_CS1__PORT +#define RTE_SSI_MASTER_CS1_PIN SSI_MASTER_CS1__PIN +#endif +#define RTE_SSI_MASTER_CS1 M4_SSI_CS1 +#define RTE_SSI_MASTER_CS1_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS1_PADSEL 5 //CS2 +#ifndef SSI_MASTER_CS2_LOC #define RTE_SSI_MASTER_CS2_PORT_ID 1 #if (RTE_SSI_MASTER_CS2_PORT_ID == 0) #define RTE_SSI_MASTER_CS2 M4_SSI_CS2 @@ -730,18 +1208,37 @@ #else #error "Invalid SSI_MASTER_CS2 Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_MASTER_CS2 M4_SSI_CS2 +#define RTE_SSI_MASTER_CS2_PORT SSI_MASTER_CS2__PORT +#define RTE_SSI_MASTER_CS2_PIN SSI_MASTER_CS2__PIN +#define RTE_SSI_MASTER_CS2_MODE EGPIO_PIN_MUX_MODE3 +#if (SSI_MASTER_CS2_LOC == 13) +#define RTE_SSI_MASTER_CS2_PADSEL 8 +#endif +#if (SSI_MASTER_CS2_LOC == 14) +#define RTE_SSI_MASTER_CS2_PADSEL 14 +#endif +//Pintool data +#endif //CS3 +#ifndef SSI_MASTER_CS3_LOC #define RTE_SSI_MASTER_CS3_PORT_ID 0 #if (RTE_SSI_MASTER_CS3_PORT_ID == 0) -#define RTE_SSI_MASTER_CS3 M4_SSI_CS3 -#define RTE_SSI_MASTER_CS3_PORT 0 -#define RTE_SSI_MASTER_CS3_PIN 51 -#define RTE_SSI_MASTER_CS3_MODE EGPIO_PIN_MUX_MODE3 -#define RTE_SSI_MASTER_CS3_PADSEL 15 +#define RTE_SSI_MASTER_CS3_PORT 0 +#define RTE_SSI_MASTER_CS3_PIN 51 #else #error "Invalid SSI_MASTER_CS3 Pin Configuration!" #endif +#else +#define RTE_SSI_MASTER_CS3_PORT SSI_MASTER_CS3__PORT +#define RTE_SSI_MASTER_CS3_PIN SSI_MASTER_CS3__PIN +#endif +#define RTE_SSI_MASTER_CS3 M4_SSI_CS3 +#define RTE_SSI_MASTER_CS3_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS3_PADSEL 15 // DMA Rx // Channel <28=>28 @@ -763,6 +1260,7 @@ #define RTE_SSI_SLAVE_INPUT_CLOCK SSISLAVE_CLK // SSI_SLAVE_MISO Pin <0=>Not Used <1=>GPIO_11 <2=>GPIO_28 <3=>GPIO_49 <4=>GPIO_57 +#ifndef SSI_SLAVE_MISO_LOC #define RTE_SSI_SLAVE_MISO_PORT_ID 2 #if (RTE_SSI_SLAVE_MISO_PORT_ID == 0) @@ -794,9 +1292,29 @@ #else #error "Invalid SSI_SLAVE_MISO Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_SLAVE_MISO 1 +#define RTE_SSI_SLAVE_MISO_PORT SSI_SLAVE_MISO__PORT +#define RTE_SSI_SLAVE_MISO_PIN SSI_SLAVE_MISO__PIN +#define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8 +#if (SSI_SLAVE_MISO_LOC == 5) +#define RTE_SSI_SLAVE_MISO_PADSEL 6 +#endif +#if (SSI_SLAVE_MISO_LOC == 6) +#define RTE_SSI_SLAVE_MISO_PADSEL 0 //no pad +#endif +#if (SSI_SLAVE_MISO_LOC == 7) +#define RTE_SSI_SLAVE_MISO_PADSEL 13 +#endif +#if (SSI_SLAVE_MISO_LOC == 8) +#define RTE_SSI_SLAVE_MISO_PADSEL 21 +#endif +//Pintool data +#endif // SSI_SLAVE_MOSI Pin <0=>Not Used <1=>GPIO_10 <2=>GPIO_27 <3=>GPIO_48 <4=>GPIO_56 - +#ifndef SSI_SLAVE_MOSI_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SSI_SLAVE_MOSI_PORT_ID 2 #else @@ -832,8 +1350,29 @@ #else #error "Invalid SSI_SLAVE_MOSI Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_SLAVE_MOSI 1 +#define RTE_SSI_SLAVE_MOSI_PORT SSI_SLAVE_MOSI__PORT +#define RTE_SSI_SLAVE_MOSI_PIN SSI_SLAVE_MOSI__PIN +#define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8 +#if (SSI_SLAVE_MOSI_LOC == 1) +#define RTE_SSI_SLAVE_MOSI_PADSEL 5 +#endif +#if (SSI_SLAVE_MOSI_LOC == 2) +#define RTE_SSI_SLAVE_MOSI_PADSEL 0 //no pad +#endif +#if (SSI_SLAVE_MOSI_LOC == 3) +#define RTE_SSI_SLAVE_MOSI_PADSEL 12 +#endif +#if (SSI_SLAVE_MOSI_LOC == 4) +#define RTE_SSI_SLAVE_MOSI_PADSEL 20 +#endif +//Pintool data +#endif // SSI_SLAVE_SCK Pin <0=>Not Used <1=>GPIO_8 <2=>GPIO_26 <3=>GPIO_47 <4=>GPIO_52 +#ifndef SSI_SLAVE_SCK_LOC #define RTE_SSI_SLAVE_SCK_PORT_ID 2 #if (RTE_SSI_SLAVE_SCK_PORT_ID == 0) @@ -865,8 +1404,29 @@ #else #error "Invalid SSI_SLAVE_SCK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_SLAVE_SCK 1 +#define RTE_SSI_SLAVE_SCK_PORT SSI_SLAVE_SCK__PORT +#define RTE_SSI_SLAVE_SCK_PIN SSI_SLAVE_SCK__PIN +#define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8 +#if (SSI_SLAVE_SCK_LOC == 9) +#define RTE_SSI_SLAVE_SCK_PADSEL 3 +#endif +#if (SSI_SLAVE_SCK_LOC == 10) +#define RTE_SSI_SLAVE_SCK_PADSEL 0 //no pad +#endif +#if (SSI_SLAVE_SCK_LOC == 11) +#define RTE_SSI_SLAVE_SCK_PADSEL 11 +#endif +#if (SSI_SLAVE_SCK_LOC == 12) +#define RTE_SSI_SLAVE_SCK_PADSEL 16 +#endif +//Pintool data +#endif // SSI_SLAVE_CS Pin <0=>Not Used <1=>GPIO_9 <2=>GPIO_25 <3=>GPIO_46 <4=>GPIO_53 +#ifndef SSI_SLAVE_CS0_LOC #define RTE_SSI_SLAVE_CS_PORT_ID 1 #if (RTE_SSI_SLAVE_CS_PORT_ID == 0) @@ -898,6 +1458,26 @@ #else #error "Invalid SSI_SLAVE_CS Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_SLAVE_CS 1 +#define RTE_SSI_SLAVE_CS_PORT SSI_SLAVE_CS0__PORT +#define RTE_SSI_SLAVE_CS_PIN SSI_SLAVE_CS0__PIN +#define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8 +#if (SSI_SLAVE_CS0_LOC == 13) +#define RTE_SSI_SLAVE_CS_PADSEL 4 +#endif +#if (SSI_SLAVE_CS0_LOC == 14) +#define RTE_SSI_SLAVE_CS_PADSEL 0 //no pad +#endif +#if (SSI_SLAVE_CS0_LOC == 15) +#define RTE_SSI_SLAVE_CS_PADSEL 10 +#endif +#if (SSI_SLAVE_CS0_LOC == 16) +#define RTE_SSI_SLAVE_CS_PADSEL 17 +#endif +//Pintool data +#endif // DMA Rx // Channel <22=>22 @@ -915,7 +1495,7 @@ // -// SSI_ULP_MASTER (Serial Peripheral Interface 3) [Driver_SSI_ULP_MASTER] +// ULP SPI Peripheral (Serial Peripheral Interface 3) [Driver_SSI_ULP_MASTER] // Configuration settings for Driver_SSI_ULP_MASTER in component ::CMSIS Driver:SPI #define RTE_SSI_ULP_MASTER 1 @@ -925,6 +1505,7 @@ #define ULP_SSI_CS2 0 // SSI_ULP_MASTER_MISO Pin <0=>Not Used <1=>ULP_GPIO_2 <2=>ULP_GPIO_9 +#ifndef ULP_SPI_MISO_LOC #define RTE_SSI_ULP_MASTER_MISO_PORT_ID 0 #if (RTE_SSI_ULP_MASTER_MISO_PORT_ID == 0) #define RTE_SSI_ULP_MASTER_MISO 1 @@ -939,8 +1520,17 @@ #else #error "Invalid SSI_ULP_MISO Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_ULP_MASTER_MISO 1 +#define RTE_SSI_ULP_MASTER_MISO_PORT ULP_SPI_MISO__PORT +#define RTE_SSI_ULP_MASTER_MISO_PIN ULP_SPI_MISO__PIN +#define RTE_SSI_ULP_MASTER_MISO_MODE 1 +//Pintool data +#endif // SSI_ULP_MASTER_MOSI Pin <0=>Not Used <1=>ULP_GPIO_1 <2=>ULP_GPIO_11 +#ifndef ULP_SPI_MOSI_LOC #define RTE_SSI_ULP_MASTER_MOSI_PORT_ID 0 #if (RTE_SSI_ULP_MASTER_MOSI_PORT_ID == 0) #define RTE_SSI_ULP_MASTER_MOSI 1 @@ -955,8 +1545,17 @@ #else #error "Invalid SSI_ULP_MOSI Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_ULP_MASTER_MOSI 1 +#define RTE_SSI_ULP_MASTER_MOSI_PORT ULP_SPI_MOSI__PORT +#define RTE_SSI_ULP_MASTER_MOSI_PIN ULP_SPI_MOSI__PIN +#define RTE_SSI_ULP_MASTER_MOSI_MODE 1 +//Pintool data +#endif // SSI_ULP_MASTER_SCK Pin <0=>Not Used <1=>ULP_GPIO_0 <2=>ULP_GPIO_8 +#ifndef ULP_SPI_SCK_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SSI_ULP_MASTER_SCK_PORT_ID 2 #else @@ -977,8 +1576,17 @@ #else #error "Invalid SSI_ULP_SCK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_ULP_MASTER_SCK 1 +#define RTE_SSI_ULP_MASTER_SCK_PORT ULP_SPI_SCK__PORT +#define RTE_SSI_ULP_MASTER_SCK_PIN ULP_SPI_SCK__PIN +#define RTE_SSI_ULP_MASTER_SCK_MODE 1 +//Pintool data +#endif // CS0 +#ifndef ULP_SPI_CS0_LOC #define RTE_SSI_ULP_MASTER_CS0_PORT_ID 1 #if (RTE_SSI_ULP_MASTER_CS0_PORT_ID == 0) #define RTE_SSI_ULP_MASTER_CS0 ULP_SSI_CS0 @@ -993,17 +1601,35 @@ #else #error "Change RTE_SSI_ULP_MASTER_CS_PORT_ID other than '1' or'3' as per PACKAGE_TYPE" #endif +#else +//Pintool data +#define RTE_SSI_ULP_MASTER_CS0 ULP_SSI_CS0 +#define RTE_SSI_ULP_MASTER_CS0_PORT ULP_SPI_CS0__PORT +#define RTE_SSI_ULP_MASTER_CS0_PIN ULP_SPI_CS0__PIN +#define RTE_SSI_ULP_MASTER_CS0_MODE 1 +//Pintool data +#endif // CS1 -#define RTE_SSI_ULP_MASTER_CS1 ULP_SSI_CS1 +#ifndef ULP_SPI_CS1_LOC #define RTE_SSI_ULP_MASTER_CS1_PORT 0 #define RTE_SSI_ULP_MASTER_CS1_PIN 4 +#else +#define RTE_SSI_ULP_MASTER_CS1_PORT ULP_SPI_CS1__PORT +#define RTE_SSI_ULP_MASTER_CS1_PIN ULP_SPI_CS1__PIN +#endif +#define RTE_SSI_ULP_MASTER_CS1 ULP_SSI_CS1 #define RTE_SSI_ULP_MASTER_CS1_MODE 1 // CS2 -#define RTE_SSI_ULP_MASTER_CS2 ULP_SSI_CS2 +#ifndef ULP_SPI_CS2_LOC #define RTE_SSI_ULP_MASTER_CS2_PORT 0 #define RTE_SSI_ULP_MASTER_CS2_PIN 6 +#else +#define RTE_SSI_ULP_MASTER_CS2_PORT ULP_SPI_CS2__PORT +#define RTE_SSI_ULP_MASTER_CS2_PIN ULP_SPI_CS2__PIN +#endif +#define RTE_SSI_ULP_MASTER_CS2 ULP_SSI_CS2 #define RTE_SSI_ULP_MASTER_CS2_MODE 1 // DMA Rx @@ -1064,6 +1690,7 @@ // I2S0_SCLK <0=>P0_8 <1=>P0_25 <2=>P0_46 <3=>P0_52 // SCLK of I2S0 +#ifndef I2S0_SCLK_LOC #define RTE_I2S0_SCLK_PORT_ID 1 #if (RTE_I2S0_SCLK_PORT_ID == 0) @@ -1089,9 +1716,29 @@ #else #error "Invalid I2S0 RTE_I2S0_SCLK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S0_SCLK_PORT I2S0_SCLK_PORT +#define RTE_I2S0_SCLK_PIN I2S0_SCLK_PIN +#define RTE_I2S0_SCLK_MUX 7 +#if (I2S0_SCLK_LOC == 0) +#define RTE_I2S0_SCLK_PAD 3 +#endif +#if (I2S0_SCLK_LOC == 1) +#define RTE_I2S0_SCLK_PAD 0 //no pad +#endif +#if (I2S0_SCLK_LOC == 2) +#define RTE_I2S0_SCLK_PAD 10 +#endif +#if (I2S0_SCLK_LOC == 3) +#define RTE_I2S0_SCLK_PAD 16 +#endif +//Pintool data +#endif // I2S0_WSCLK <0=>P0_9 <1=>P0_26 <2=>P0_47 <3=>P0_53 // WSCLK for I2S0 +#ifndef I2S0_WSCLK_LOC #define RTE_I2S0_WSCLK_PORT_ID 1 #if (RTE_I2S0_WSCLK_PORT_ID == 0) @@ -1117,9 +1764,29 @@ #else #error "Invalid I2S0 RTE_I2S0_WSCLK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S0_WSCLK_PORT I2S0_WSCLK_PORT +#define RTE_I2S0_WSCLK_PIN I2S0_WSCLK_PIN +#define RTE_I2S0_WSCLK_MUX 7 +#if (I2S0_WSCLK_LOC == 4) +#define RTE_I2S0_WSCLK_PAD 4 +#endif +#if (I2S0_WSCLK_LOC == 5) +#define RTE_I2S0_WSCLK_PAD 0 +#endif +#if (I2S0_WSCLK_LOC == 6) +#define RTE_I2S0_WSCLK_PAD 11 +#endif +#if (I2S0_WSCLK_LOC == 7) +#define RTE_I2S0_WSCLK_PAD 17 +#endif +//Pintool data +#endif // I2S0_DOUT0 <0=>P0_11 <1=>P0_28 <2=>P0_49 <3=>P0_57 // DOUT0 for I2S0 +#ifndef I2S0_DOUT0_LOC #define RTE_I2S0_DOUT0_PORT_ID 1 #if (RTE_I2S0_DOUT0_PORT_ID == 0) @@ -1145,9 +1812,29 @@ #else #error "Invalid I2S0 RTE_I2S0_DOUT0 Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S0_DOUT0_PORT I2S0_DOUT0_PORT +#define RTE_I2S0_DOUT0_PIN I2S0_DOUT0_PIN +#define RTE_I2S0_DOUT0_MUX 7 +#if (I2S0_DOUT0_LOC == 8) +#define RTE_I2S0_DOUT0_PAD 6 +#endif +#if (I2S0_DOUT0_LOC == 9) +#define RTE_I2S0_DOUT0_PAD 0 +#endif +#if (I2S0_DOUT0_LOC == 10) +#define RTE_I2S0_DOUT0_PAD 13 +#endif +#if (I2S0_DOUT0_LOC == 11) +#define RTE_I2S0_DOUT0_PAD 21 +#endif +//Pintool data +#endif // I2S0_DIN0 <0=>P0_10 <1=>P0_27 <2=>P0_48 <3=>P0_56 // DIN0 for I2S0 +#ifndef I2S0_DIN0_LOC #define RTE_I2S0_DIN0_PORT_ID 1 #if (RTE_I2S0_DIN0_PORT_ID == 0) @@ -1173,11 +1860,30 @@ #else #error "Invalid I2S0 RTE_I2S0_DIN0 Pin Configuration!" #endif - -// I2S0_DOUT1 <0=>P0_7 <1=>P0_30 <2=>P0_51 <3=>P0_55 -// DOUT1 for I2S0 - -#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#else +//Pintool data +#define RTE_I2S0_DIN0_PORT I2S0_DIN0_PORT +#define RTE_I2S0_DIN0_PIN I2S0_DIN0_PIN +#define RTE_I2S0_DIN0_MUX 7 +#if (I2S0_DIN0_LOC == 12) +#define RTE_I2S0_DIN0_PAD 5 +#endif +#if (I2S0_DIN0_LOC == 13) +#define RTE_I2S0_DIN0_PAD 0 +#endif +#if (I2S0_DIN0_LOC == 14) +#define RTE_I2S0_DIN0_PAD 12 +#endif +#if (I2S0_DIN0_LOC == 15) +#define RTE_I2S0_DIN0_PAD 20 +#endif +//Pintool data +#endif + +// I2S0_DOUT1 <0=>P0_7 <1=>P0_30 <2=>P0_51 <3=>P0_55 +// DOUT1 for I2S0 +#ifndef I2S0_DOUT1_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_I2S0_DOUT1_PORT_ID 1 #else #define RTE_I2S0_DOUT1_PORT_ID 0 @@ -1206,9 +1912,29 @@ #else #error "Invalid I2S0 RTE_I2S0_DOUT1 Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S0_DOUT1_PORT I2S0_DOUT1_PORT +#define RTE_I2S0_DOUT1_PIN I2S0_DOUT1_PIN +#define RTE_I2S0_DOUT1_MUX 7 +#if (I2S0_DOUT1_LOC == 16) +#define RTE_I2S0_DOUT1_PAD 2 +#endif +#if (I2S0_DOUT1_LOC == 17) +#define RTE_I2S0_DOUT1_PAD 0 +#endif +#if (I2S0_DOUT1_LOC == 18) +#define RTE_I2S0_DOUT1_PAD 15 +#endif +#if (I2S0_DOUT1_LOC == 19) +#define RTE_I2S0_DOUT1_PAD 19 +#endif +//Pintool data +#endif // I2S0_DIN1 <0=>P0_6 <1=>P0_29 <2=>P0_50 <3=>P0_54 // DIN1 for I2S0 +#ifndef I2S0_DIN1_LOC #define RTE_I2S0_DIN1_PORT_ID 0 #if (RTE_I2S0_DIN1_PORT_ID == 0) @@ -1234,8 +1960,27 @@ #else #error "Invalid I2S0 RTE_I2S0_DIN1 Pin Configuration!" #endif -// FIFO level can have value 1 to 7 -#define I2S0_TX_FIFO_LEVEL (2U) +#else +//Pintool data +#define RTE_I2S0_DIN1_PORT I2S0_DIN1_PORT +#define RTE_I2S0_DIN1_PIN I2S0_DIN1_PIN +#define RTE_I2S0_DIN1_MUX 7 +#if (I2S0_DIN1_LOC == 20) +#define RTE_I2S0_DIN1_PAD 1 +#endif +#if (I2S0_DIN1_LOC == 21) +#define RTE_I2S0_DIN1_PAD 0 +#endif +#if (I2S0_DIN1_LOC == 22) +#define RTE_I2S0_DIN1_PAD 14 +#endif +#if (I2S0_DIN1_LOC == 23) +#define RTE_I2S0_DIN1_PAD 18 +#endif +//Pintool data +#endif +// FIFO level can have value 0 to 7 +#define I2S0_TX_FIFO_LEVEL (0U) #define I2S0_RX_FIFO_LEVEL (2U) // I2S0_TX_RES <0=>12 @@ -1283,13 +2028,14 @@ // -// I2S1 [Driver_I2S1] +// ULP I2S [Driver_I2S1] // Configuration settings for Driver_I2S1 in component ::Drivers:I2S #define RTE_I2S1 1 #define I2S1_IRQHandler IRQ014_Handler // I2S1_SCLK Pin <0=>P0_3 <1=>P0_7 <2=>P0_8 /*I2S1 PINS*/ +#ifndef ULP_I2S_SCLK_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_I2S1_SCLK_PORT_ID 0 #else @@ -1310,8 +2056,16 @@ #else #error "Invalid I2S1 RTE_I2S1_SCLK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S1_SCLK_PORT ULP_I2S_SCLK_PORT +#define RTE_I2S1_SCLK_PIN ULP_I2S_SCLK_PIN +#define RTE_I2S1_SCLK_MUX 2 +//Pintool data +#endif // I2S1_WSCLK Pin <0=>P0_2 <1=>P0_4 <2=>P0_10 +#ifndef ULP_I2S_WSCLK_LOC #define RTE_I2S1_WSCLK_PORT_ID 0 #if (RTE_I2S1_WSCLK_PORT_ID == 0) #define RTE_I2S1_WSCLK_PORT 0 @@ -1324,8 +2078,16 @@ #else #error "Invalid I2S1 RTE_I2S1_WSCLK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S1_WSCLK_PORT ULP_I2S_WSCLK_PORT +#define RTE_I2S1_WSCLK_PIN ULP_I2S_WSCLK_PIN +#define RTE_I2S1_WSCLK_MUX 2 +//Pintool data +#endif // I2S1_DOUT0 Pin <0=>P0_1 <1=>P0_5 <2=>P0_11 +#ifndef ULP_I2S_DOUT0_LOC #define RTE_I2S1_DOUT0_PORT_ID 0 #if (RTE_I2S1_DOUT0_PORT_ID == 0) #define RTE_I2S1_DOUT0_PORT 0 @@ -1338,8 +2100,16 @@ #else #error "Invalid I2S1 RTE_I2S1_DOUT0 Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S1_DOUT0_PORT ULP_I2S_DOUT0_PORT +#define RTE_I2S1_DOUT0_PIN ULP_I2S_DOUT0_PIN +#define RTE_I2S1_DOUT0_MUX 2 +//Pintool data +#endif // I2S1_DIN0 Pin <0=>P0_0 <1=>P0_6 <2=>P0_9 <3=>P0_13 +#ifndef ULP_I2S_DIN0_LOC #define RTE_I2S1_DIN0_PORT_ID 1 #if (RTE_I2S1_DIN0_PORT_ID == 0) #define RTE_I2S1_DIN0_PORT 0 @@ -1356,9 +2126,16 @@ #else #error "Invalid I2S1 RTE_I2S1_DIN0 Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S1_DIN0_PORT ULP_I2S_DIN0_PORT +#define RTE_I2S1_DIN0_PIN ULP_I2S_DIN0_PIN +#define RTE_I2S1_DIN0_MUX 2 +//Pintool data +#endif -// FIFO level can have value 1 to 7 -#define I2S1_TX_FIFO_LEVEL (2U) +// FIFO level can have value 0 to 7 +#define I2S1_TX_FIFO_LEVEL (0U) #define I2S1_RX_FIFO_LEVEL (2U) // I2S1_TX_RES <0=>12 @@ -1413,7 +2190,7 @@ #define I2C0_IRQHandler IRQ042_Handler // I2C0_SCL Pin <0=>P0_7 <1=>P0_65 <2=>P0_66 <3=>P0_75 <4=>P0_32 - +#ifndef I2C0_SCL_LOC #define RTE_I2C0_SCL_PORT_ID 1 #if (RTE_I2C0_SCL_PORT_ID == 0) @@ -1443,9 +2220,32 @@ #else #error "Invalid I2C0 RTE_I2C0_SCL Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2C0_SCL_PORT I2C0_SCL_PORT +#if (I2C0_SCL_LOC == 0) +#define RTE_I2C0_SCL_PIN I2C0_SCL_PIN +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 2 +#define RTE_I2C0_SCL_I2C_REN 7 +#endif +#if (I2C0_SCL_LOC == 1) +#define RTE_I2C0_SCL_PIN (I2C0_SCL_PIN + GPIO_MAX_PIN) +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 23 +#define RTE_I2C0_SCL_I2C_REN 1 +#endif +#if (I2C0_SCL_LOC == 2) +#define RTE_I2C0_SCL_PIN (I2C0_SCL_PIN + GPIO_MAX_PIN) +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 33 +#define RTE_I2C0_SCL_I2C_REN 11 +#endif +//Pintool data +#endif // I2C0_SCL Pin <0=>P0_6 <1=>P0_64 <2=>P0_67 <3=>P0_74 <4=>P0_31 - +#ifndef I2C0_SDA_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_I2C0_SDA_PORT_ID 2 #else @@ -1473,6 +2273,29 @@ #else #error "Invalid I2C0 RTE_I2C0_SDA Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2C0_SDA_PORT I2C0_SDA_PORT +#if (I2C0_SDA_LOC == 3) +#define RTE_I2C0_SDA_PIN I2C0_SDA_PIN +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 1 +#define RTE_I2C0_SDA_I2C_REN 6 +#endif +#if (I2C0_SDA_LOC == 4) +#define RTE_I2C0_SDA_PIN (I2C0_SDA_PIN + GPIO_MAX_PIN) +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 22 +#define RTE_I2C0_SDA_I2C_REN 3 +#endif +#if (I2C0_SDA_LOC == 5) +#define RTE_I2C0_SDA_PIN (I2C0_SDA_PIN + GPIO_MAX_PIN) +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 32 +#define RTE_I2C0_SDA_I2C_REN 10 +#endif +//Pintool data +#endif #define IC_SCL_STUCK_TIMEOUT 20 #define IC_SDA_STUCK_TIMEOUT 20 @@ -1482,7 +2305,7 @@ #define DMA_TX_TL 1 #define DMA_RX_TL 1 #endif -// I2C0 [Driver_I2C0] +// I2C1 [Driver_I2C0] // I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1] // Configuration settings for Driver_I2C1 in component ::Drivers:I2C @@ -1490,6 +2313,7 @@ #define RTE_I2C1 1 #define I2C1_IRQHandler IRQ061_Handler // I2C1_SCL Pin <0=>P0_6 <1=>P0_29 <2=>P0_50 <3=>P0_54 <4=>P0_64 <4=>P0_66 <4=>P0_70 <7=>P0_33 +#ifndef I2C1_SCL_LOC #define RTE_I2C1_SCL_PORT_ID 2 #if (RTE_I2C1_SCL_PORT_ID == 0) @@ -1531,9 +2355,50 @@ #else #error "Invalid I2C1_SCL Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2C1_SCL_PORT I2C1_SCL_PORT +#if (I2C1_SCL_LOC == 0) +#define RTE_I2C1_SCL_PIN I2C1_SCL_PIN +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 1 +#define RTE_I2C1_SCL_REN 6 +#endif +#if (I2C1_SCL_LOC == 1) +#define RTE_I2C1_SCL_PIN I2C1_SCL_PIN +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 0 //no pad +#define RTE_I2C1_SCL_REN 29 +#endif +#if (I2C1_SCL_LOC == 2) +#define RTE_I2C1_SCL_PIN I2C1_SCL_PIN +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 14 +#define RTE_I2C1_SCL_REN 50 +#endif +#if (I2C1_SCL_LOC == 3) +#define RTE_I2C1_SCL_PIN I2C1_SCL_PIN +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 18 +#define RTE_I2C1_SCL_REN 54 +#endif +#if (I2C1_SCL_LOC == 4) +#define RTE_I2C1_SCL_PIN (I2C1_SCL_PIN + GPIO_MAX_PIN) +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 22 +#define RTE_I2C1_SCL_REN 2 +#endif +#if (I2C1_SCL_LOC == 5) +#define RTE_I2C1_SCL_PIN (I2C1_SCL_PIN + GPIO_MAX_PIN) +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 29 +#define RTE_I2C1_SCL_REN 6 +#endif +//Pintool data +#endif // I2C1_SCL Pin <0=>P0_7 <1=>P0_30 <2=>P0_51 <3=>P0_55 <4=>P0_65 <4=>P0_67 <4=>P0_71 <7=>P0_34 - +#ifndef I2C1_SDA_LOC #define RTE_I2C1_SDA_PORT_ID 2 #if (RTE_I2C1_SDA_PORT_ID == 0) @@ -1581,6 +2446,47 @@ #else #error "Invalid I2C1_SDA Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2C1_SDA_PORT I2C1_SDA_PORT +#if (I2C1_SDA_LOC == 6) +#define RTE_I2C1_SDA_PIN I2C1_SDA_PIN +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 2 +#define RTE_I2C1_SDA_REN 7 +#endif +#if (I2C1_SDA_LOC == 7) +#define RTE_I2C1_SDA_PIN I2C1_SDA_PIN +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 0 //no pad +#define RTE_I2C1_SDA_REN 30 +#endif +#if (I2C1_SDA_LOC == 8) +#define RTE_I2C1_SDA_PIN I2C1_SDA_PIN +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 15 +#define RTE_I2C1_SDA_REN 51 +#endif +#if (I2C1_SDA_LOC == 9) +#define RTE_I2C1_SDA_PIN I2C1_SDA_PIN +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 19 +#define RTE_I2C1_SDA_REN 55 +#endif +#if (I2C1_SDA_LOC == 10) +#define RTE_I2C1_SDA_PIN (I2C1_SDA_PIN + GPIO_MAX_PIN) +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 23 +#define RTE_I2C1_SDA_REN 1 +#endif +#if (I2C1_SDA_LOC == 11) +#define RTE_I2C1_SDA_PIN (I2C1_SDA_PIN + GPIO_MAX_PIN) +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 29 +#define RTE_I2C1_SDA_REN 7 +#endif +//Pintool data +#endif #define IC_SCL_STUCK_TIMEOUT 20 #define IC_SDA_STUCK_TIMEOUT 20 @@ -1593,12 +2499,13 @@ // I2C1 [Driver_I2C1] -// I2C2 (Inter-integrated Circuit Interface 2) [Driver_I2C2] +// ULP I2C (Inter-integrated Circuit Interface 2) [Driver_I2C2] // Configuration settings for Driver_I2C2 in component ::Drivers:I2C #define RTE_I2C2 1 #define I2C2_IRQHandler IRQ013_Handler // I2C2_SCL Pin <0=>P0_1 <1=>P0_5 <2=>P0_7 <3=>P0_8 <4=>P0_13 +#ifndef ULP_I2C_SCL_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_I2C2_SCL_PORT_ID 0 #else @@ -1617,8 +2524,25 @@ #else #error "Invalid I2C2_SCL Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2C2_SCL_PORT ULP_I2C_SCL_PORT +#define RTE_I2C2_SCL_PIN ULP_I2C_SCL_PIN +#define RTE_I2C2_SCL_MUX 4 +#if (ULP_I2C_SCL_LOC == 0) +#define RTE_I2C2_SCL_REN 0 +#elif (ULP_I2C_SCL_LOC == 1) +#define RTE_I2C2_SCL_REN 0 +#elif (ULP_I2C_SCL_LOC == 2) +#define RTE_I2C2_SCL_REN 7 +#elif (ULP_I2C_SCL_LOC == 3) +#define RTE_I2C2_SCL_REN 8 +#endif +//Pintool data +#endif // I2C2_SDA Pin <0=>P0_0 <1=>P0_4 <2=>P0_6 <3=>P0_9 <4=>P0_11 <5=>P0_12 +#ifndef ULP_I2C_SDA_LOC #define RTE_I2C2_SDA_PORT_ID 0 #if (RTE_I2C2_SDA_PORT_ID == 0) #define RTE_I2C2_SDA_PORT 0 @@ -1626,10 +2550,10 @@ #define RTE_I2C2_SDA_MUX 4 #define RTE_I2C2_SDA_REN 6 #elif (RTE_I2C2_SDA_PORT_ID == 1) -#define RTE_I2C2_SDA_PORT 0 -#define RTE_I2C2_SDA_PIN 9 -#define RTE_I2C2_SDA_MUX 4 -#define RTE_I2C2_SDA_I2C_REN 9 +#define RTE_I2C2_SDA_PORT 0 +#define RTE_I2C2_SDA_PIN 9 +#define RTE_I2C2_SDA_MUX 4 +#define RTE_I2C2_SDA_REN 9 #elif (RTE_I2C2_SDA_PORT_ID == 2) #define RTE_I2C2_SDA_PORT 0 #define RTE_I2C2_SDA_PIN 11 @@ -1638,6 +2562,24 @@ #else #error "Invalid I2C2_SDA Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2C2_SDA_PORT I2C2_SDA_PORT +#define RTE_I2C2_SDA_PIN I2C2_SDA_PIN +#define RTE_I2C2_SDA_MUX 4 +#if (ULP_I2C_SDA_LOC == 4) +#define RTE_I2C2_SDA_REN 0 +#elif (ULP_I2C_SDA_LOC == 5) +#define RTE_I2C2_SDA_REN 0 +#elif (ULP_I2C_SDA_LOC == 6) +#define RTE_I2C2_SDA_REN 6 +#elif (ULP_I2C_SDA_LOC == 7) +#define RTE_I2C2_SDA_REN 9 +#elif (ULP_I2C_SDA_LOC == 8) +#define RTE_I2C2_SDA_REN 11 +#endif +//Pintool data +#endif #define IC_SCL_STUCK_TIMEOUT 20 #define IC_SDA_STUCK_TIMEOUT 20 @@ -1656,6 +2598,7 @@ // GSPI_MASTER_CLK <0=>P0_8 <1=>P0_25 <2=>P0_46 <3=>P0_52 // CLK of GSPI0 +#ifndef GSPI_MASTER_SCK_LOC #define RTE_GSPI_MASTER_CLK_PORT_ID 1 #if (RTE_GSPI_MASTER_CLK_PORT_ID == 0) @@ -1681,12 +2624,31 @@ #else #error "Invalid GSPI0 RTE_GSPI_MASTER_CLK_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_GSPI_MASTER_CLK_PORT GSPI_MASTER_SCK__PORT +#define RTE_GSPI_MASTER_CLK_PIN GSPI_MASTER_SCK__PIN +#define RTE_GSPI_MASTER_CLK_MUX 4 +#if (GSPI_MASTER_SCK_LOC == 0) +#define RTE_GSPI_MASTER_CLK_PAD 3 +#endif +#if (GSPI_MASTER_SCK_LOC == 1) +#define RTE_GSPI_MASTER_CLK_PAD 0 +#endif +#if (GSPI_MASTER_SCK_LOC == 2) +#define RTE_GSPI_MASTER_CLK_PAD 10 +#endif +#if (GSPI_MASTER_SCK_LOC == 3) +#define RTE_GSPI_MASTER_CLK_PAD 16 +#endif +//Pintool data +#endif // GSPI_MASTER_CS0 // <0=>P0_9 <1=>P0_28 <2=>P0_49 <3=>P0_53 // CS0 of GSPI0 // - +#ifndef GSPI_MASTER_CS0_LOC #define RTE_GSPI_MASTER_CS0_PORT_ID 1 #if (RTE_GSPI_MASTER_CS0_PORT_ID == 0) @@ -1716,11 +2678,32 @@ #else #error "Invalid GSPI0 RTE_GSPI_MASTER_CS0_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_GSPI_MASTER_CS0 1 +#define RTE_GSPI_MASTER_CS0_PORT GSPI_MASTER_CS0__PORT +#define RTE_GSPI_MASTER_CS0_PIN GSPI_MASTER_CS0__PIN +#define RTE_GSPI_MASTER_CS0_MUX 4 +#if (GSPI_MASTER_CS0_LOC == 4) +#define RTE_GSPI_MASTER_CS0_PAD 4 +#endif +#if (GSPI_MASTER_CS0_LOC == 5) +#define RTE_GSPI_MASTER_CS0_PAD 0 +#endif +#if (GSPI_MASTER_CS0_LOC == 6) +#define RTE_GSPI_MASTER_CS0_PAD 13 +#endif +#if (GSPI_MASTER_CS0_LOC == 7) +#define RTE_GSPI_MASTER_CS0_PAD 17 +#endif +//Pintool data +#endif // GSPI_MASTER_CS1 // <0=>P0_10 <1=>P0_29 <2=>P0_50 <3=>P0_54 // CS1 of GSPI0 // +#ifndef GSPI_MASTER_CS1_LOC #define RTE_GSPI_MASTER_CS1_PORT_ID 1 #if (RTE_GSPI_MASTER_CS1_PORT_ID == 0) #define RTE_GSPI_MASTER_CS1 1 @@ -1749,11 +2732,32 @@ #else #error "Invalid GSPI0 RTE_GSPI_MASTER_CS1_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_GSPI_MASTER_CS1 1 +#define RTE_GSPI_MASTER_CS1_PORT GSPI_MASTER_CS1__PORT +#define RTE_GSPI_MASTER_CS1_PIN GSPI_MASTER_CS1__PIN +#define RTE_GSPI_MASTER_CS1_MUX 4 +#if (GSPI_MASTER_CS1_LOC == 8) +#define RTE_GSPI_MASTER_CS1_PAD 5 +#endif +#if (GSPI_MASTER_CS1_LOC == 9) +#define RTE_GSPI_MASTER_CS1_PAD 0 +#endif +#if (GSPI_MASTER_CS1_LOC == 10) +#define RTE_GSPI_MASTER_CS1_PAD 14 +#endif +#if (GSPI_MASTER_CS1_LOC == 11) +#define RTE_GSPI_MASTER_CS1_PAD 18 +#endif +//Pintool data +#endif // GSPI_MASTER_CS2 // <0=>P0_15 <1=>P0_30 <2=>P0_51 <3=>P0_55 // CS2 of GSPI0 // +#ifndef GSPI_MASTER_CS2_LOC #define RTE_GSPI_MASTER_CS2_PORT_ID 1 #if (RTE_GSPI_MASTER_CS2_PORT_ID == 0) #define RTE_GSPI_MASTER_CS2 1 @@ -1782,10 +2786,30 @@ #else #error "Invalid GSPI0 RTE_GSPI_MASTER_CS2_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_GSPI_MASTER_CS2 1 +#define RTE_GSPI_MASTER_CS2_PORT GSPI_MASTER_CS2__PORT +#define RTE_GSPI_MASTER_CS2_PIN GSPI_MASTER_CS2__PIN +#define RTE_GSPI_MASTER_CS2_MUX 4 +#if (GSPI_MASTER_CS2_LOC == 12) +#define RTE_GSPI_MASTER_CS2_PAD 8 +#endif +#if (GSPI_MASTER_CS2_LOC == 13) +#define RTE_GSPI_MASTER_CS2_PAD 0 +#endif +#if (GSPI_MASTER_CS2_LOC == 14) +#define RTE_GSPI_MASTER_CS2_PAD 15 +#endif +#if (GSPI_MASTER_CS2_LOC == 15) +#define RTE_GSPI_MASTER_CS2_PAD 19 +#endif +//Pintool data +#endif // GSPI_MASTER_MOSI <0=>P0_12 <1=>P0_27 <2=>P0_48 <3=>P0_57 <4=>P0_6 // MOSI of GSPI0 - +#ifndef GSPI_MASTER_MOSI_LOC #define RTE_GSPI_MASTER_MOSI_PORT_ID 1 #if (RTE_GSPI_MASTER_MOSI_PORT_ID == 0) @@ -1816,10 +2840,36 @@ #else #error "Invalid GSPI0 RTE_GSPI_MASTER_MOSI_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_GSPI_MASTER_MOSI_PORT GSPI_MASTER_MOSI__PORT +#define RTE_GSPI_MASTER_MOSI_PIN GSPI_MASTER_MOSI__PIN +#if (GSPI_MASTER_MOSI_LOC == 16) +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 1 +#endif +#if (GSPI_MASTER_MOSI_LOC == 17) +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 0 +#endif +#if (GSPI_MASTER_MOSI_LOC == 18) +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 12 +#endif +#if (GSPI_MASTER_MOSI_LOC == 19) +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 21 +#endif +#if (GSPI_MASTER_MOSI_LOC == 20) +#define RTE_GSPI_MASTER_MOSI_MUX 12 +#define RTE_GSPI_MASTER_MOSI_PAD 1 +#endif +//Pintool data +#endif // GSPI_MASTER_MISO <0=>P0_11 <1=>P0_26 <2=>P0_47 <3=>P0_56 // MISO of GSPI0 - +#ifndef GSPI_MASTER_MISO_LOC #define RTE_GSPI_MASTER_MISO_PORT_ID 1 #if (RTE_GSPI_MASTER_MISO_PORT_ID == 0) @@ -1845,6 +2895,25 @@ #else #error "Invalid GSPI0 RTE_GSPI_MASTER_MISO_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_GSPI_MASTER_MISO_PORT GSPI_MASTER_MISO__PORT +#define RTE_GSPI_MASTER_MISO_PIN GSPI_MASTER_MISO__PIN +#define RTE_GSPI_MASTER_MISO_MUX 4 +#if (GSPI_MASTER_MISO_LOC == 21) +#define RTE_GSPI_MASTER_MISO_PAD 6 +#endif +#if (GSPI_MASTER_MISO_LOC == 22) +#define RTE_GSPI_MASTER_MISO_PAD 0 +#endif +#if (GSPI_MASTER_MISO_LOC == 23) +#define RTE_GSPI_MASTER_MISO_PAD 11 +#endif +#if (GSPI_MASTER_MISO_LOC == 24) +#define RTE_GSPI_MASTER_MISO_PAD 20 +#endif +//Pintool data +#endif #if defined(HIGH_THROUGHPUT_EN) && (HIGH_THROUGHPUT_EN == ENABLE) #define RTE_GSPI_MASTER_CHNL_UDMA_TX_EN 1 @@ -1880,6 +2949,7 @@ //SCT_IN_0 <0=>GPIO_25 <1=>GPIO_64 <2=>GPIO_68 +#ifndef SCT_IN0_LOC #define RTE_SCT_IN_0_PORT_ID 0 #if (RTE_SCT_IN_0_PORT_ID == 0) @@ -1890,9 +2960,27 @@ #else #error "Invalid RTE_SCT_IN_0_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SCT_IN_0_PORT SCT_IN0_PORT +#if (SCT_IN0_LOC == 0) +#define RTE_SCT_IN_0_PIN SCT_IN0_PIN +#define RTE_SCT_IN_0_MUX 9 +#define RTE_SCT_IN_0_PAD 0 //no pad +#elif (SCT_IN0_LOC == 1) +#define RTE_SCT_IN_0_PIN (SCT_IN0_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_0_MUX 7 +#define RTE_SCT_IN_0_PAD 22 +#elif (SCT_IN0_LOC == 2) +#define RTE_SCT_IN_0_PIN (SCT_IN0_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_0_MUX 9 +#define RTE_SCT_IN_0_PAD 26 +#endif +//Pintool data +#endif //SCT_IN_1 <0=>GPIO_26 <1=>GPIO_65 <2=>GPIO_69 - +#ifndef SCT_IN1_LOC #define RTE_SCT_IN_1_PORT_ID 1 #if (RTE_SCT_IN_1_PORT_ID == 0) @@ -1908,9 +2996,29 @@ #else #error "Invalid RTE_SCT_IN_1_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SCT_IN_1_PORT SCT_IN1_PORT +#if (SCT_IN1_LOC == 3) +#define RTE_SCT_IN_1_PIN SCT_IN1_PIN +#define RTE_SCT_IN_1_MUX 9 +#define RTE_SCT_IN_1_PAD 0 //no pad +#endif +#if (SCT_IN1_LOC == 4) +#define RTE_SCT_IN_1_PIN (SCT_IN1_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_1_MUX 7 +#define RTE_SCT_IN_1_PAD 23 +#endif +#if (SCT_IN1_LOC == 5) +#define RTE_SCT_IN_1_PIN (SCT_IN1_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_1_MUX 9 +#define RTE_SCT_IN_1_PAD 27 +#endif +//Pintool data +#endif //SCT_IN_2 <0=>GPIO_27 <1=>GPIO_66 <2=>GPIO_70 - +#ifndef SCT_IN2_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SCT_IN_2_PORT_ID 0 #else @@ -1935,9 +3043,24 @@ #else #error "Invalid RTE_SCT_IN_0_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SCT_IN_2_PORT SCT_IN2_PORT +#if (SCT_IN2_LOC == 6) +#define RTE_SCT_IN_2_PIN SCT_IN2_PIN +#define RTE_SCT_IN_2_MUX 9 +#define RTE_SCT_IN_2_PAD 0 //no pad +#endif +#if (SCT_IN2_LOC == 7) +#define RTE_SCT_IN_2_PIN (SCT_IN2_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_2_MUX 9 +#define RTE_SCT_IN_2_PAD 28 +#endif +//Pintool data +#endif //SCT_IN_3 <0=>GPIO_28 <1=>GPIO_67 <2=>GPIO_71 - +#ifndef SCT_IN3_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SCT_IN_3_PORT_ID 0 #else @@ -1962,8 +3085,24 @@ #else #error "Invalid RTE_SCT_IN_0_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SCT_IN_3_PORT SCT_IN3_PORT +#if (SCT_IN3_LOC == 8) +#define RTE_SCT_IN_3_PIN SCT_IN3_PIN +#define RTE_SCT_IN_3_MUX 9 +#define RTE_SCT_IN_3_PAD 0 //no pad +#endif +#if (SCT_IN3_LOC == 9) +#define RTE_SCT_IN_3_PIN (SCT_IN3_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_3_MUX 9 +#define RTE_SCT_IN_3_PAD 29 +#endif +//Pintool data +#endif // SCT_OUT_0 <0=>GPIO_29 <1=>GPIO_68 +#ifndef SCT_OUT0_LOC #define RTE_SCT_OUT_0_PORT_ID 0 #if (RTE_SCT_OUT_0_PORT_ID == 0) #define RTE_SCT_OUT_0_PORT 0 @@ -1973,8 +3112,23 @@ #else #error "Invalid RTE_SCT_OUT_0_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SCT_OUT_0_PORT SCT_OUT0_PORT +#if (SCT_OUT0_LOC == 10) +#define RTE_SCT_OUT_0_PIN SCT_OUT0_PIN +#define RTE_SCT_OUT_0_MUX 9 +#define RTE_SCT_OUT_0_PAD 0 //no pad +#elif (SCT_OUT0_LOC == 11) +#define RTE_SCT_OUT_0_PIN (SCT_OUT0_PIN + GPIO_MAX_PIN) +#define RTE_SCT_OUT_0_MUX 7 +#define RTE_SCT_OUT_0_PAD 26 +#endif +//Pintool data +#endif // SCT_OUT_1 <0=>GPIO_30 <1=>GPIO_69 +#ifndef SCT_OUT1_LOC #define RTE_SCT_OUT_1_PORT_ID 0 #if (RTE_SCT_OUT_1_PORT_ID == 0) #define RTE_SCT_OUT_1_PORT 0 @@ -1984,117 +3138,67 @@ #else #error "Invalid RTE_SCT_OUT_1_PIN Pin Configuration!" #endif - -/// SCT_OUT_2 <0=>GPIO_70 <1=>GPIO_8 -#define RTE_SCT_OUT_2_PORT_ID 0 -#if ((RTE_SCT_OUT_2_PORT_ID == 1)) -#error "Invalid RTE_SCT_OUT_2_PIN pin Configuration!" +#else +//Pintool data +#define RTE_SCT_OUT_1_PORT SCT_OUT1_PORT +#if (SCT_OUT1_LOC == 12) +#define RTE_SCT_OUT_1_PIN SCT_OUT1_PIN +#define RTE_SCT_OUT_1_MUX 9 +#define RTE_SCT_OUT_1_PAD 0 //no pad +#elif (SCT_OUT1_LOC == 13) +#define RTE_SCT_OUT_1_PIN (SCT_OUT1_PIN + GPIO_MAX_PIN) +#define RTE_SCT_OUT_1_MUX 7 +#define RTE_SCT_OUT_1_PAD 27 +#endif +//Pintool data #endif -#if (RTE_SCT_OUT_2_PORT_ID == 0) -#define RTE_SCT_OUT_2_PORT 0 -#define RTE_SCT_OUT_2_PIN 70 +//Pintool data +#define RTE_SCT_OUT_2_PORT SCT_OUT2_PORT +#define RTE_SCT_OUT_2_PIN SCT_OUT2_PIN #define RTE_SCT_OUT_2_MUX 7 #define RTE_SCT_OUT_2_PAD 28 -#elif (RTE_SCT_OUT_2_PORT_ID == 1) -#define RTE_SCT_OUT_2_PORT 0 -#define RTE_SCT_OUT_2_PIN 8 -#define RTE_SCT_OUT_2_MUX 12 -#define RTE_SCT_OUT_2_PAD 3 -#else -#error "Invalid RTE_SCT_OUT_2_PIN Pin Configuration!" -#endif -/**/ -//SCT_OUT_3 <0=>GPIO_71 <1=>GPIO_9 -#define RTE_SCT_OUT_3_PORT_ID 0 -#if ((RTE_SCT_OUT_3_PORT_ID == 1)) -#error "Invalid RTE_SCT_OUT_3_PIN pin Configuration!" -#endif +//Pintool data -#if (RTE_SCT_OUT_3_PORT_ID == 0) -#define RTE_SCT_OUT_3_PORT 0 -#define RTE_SCT_OUT_3_PIN 71 +//Pintool data +#define RTE_SCT_OUT_3_PORT SCT_OUT3_PORT +#define RTE_SCT_OUT_3_PIN SCT_OUT3_PIN #define RTE_SCT_OUT_3_MUX 7 #define RTE_SCT_OUT_3_PAD 29 -#elif (RTE_SCT_OUT_3_PORT_ID == 1) -#define RTE_SCT_OUT_3_PORT 0 -#define RTE_SCT_OUT_3_PIN 9 -#define RTE_SCT_OUT_3_MUX 12 -#define RTE_SCT_OUT_3_PAD 4 -#else -#error "Invalid RTE_SCT_OUT_3_PIN Pin Configuration!" -#endif - -//SCT_OUT_4 <0=>GPIO_72 <1=>GPIO_68 +//Pintool data -#define RTE_SCT_OUT_4_PORT_ID 0 -#if ((RTE_SCT_OUT_4_PORT_ID == 1)) -#error "Invalid RTE_SCT_OUT_4_PIN pin Configuration!" -#endif - -#if (RTE_SCT_OUT_4_PORT_ID == 0) -/**/ -#define RTE_SCT_OUT_4_PORT 0 -#define RTE_SCT_OUT_4_PIN 72 +//Pintool data +#define RTE_SCT_OUT_4_PORT SCT_OUT4_PORT +#define RTE_SCT_OUT_4_PIN SCT_OUT4_PIN #define RTE_SCT_OUT_4_MUX 7 #define RTE_SCT_OUT_4_PAD 30 -#else -#error "Invalid RTE_SCT_OUT_4_PIN Pin Configuration!" -#endif -//SCT_OUT_5 <0=>GPIO_73 <1=>GPIO_69 +//Pintool data -#define RTE_SCT_OUT_5_PORT_ID 0 -#if ((RTE_SCT_OUT_5_PORT_ID == 1)) -#error "Invalid RTE_SCT_OUT_5_PIN pin Configuration!" -#endif - -#if (RTE_SCT_OUT_5_PORT_ID == 0) -#define RTE_SCT_OUT_5_PORT 2 -#define RTE_SCT_OUT_5_PIN 73 +//Pintool data +#define RTE_SCT_OUT_5_PORT SCT_OUT5_PORT +#define RTE_SCT_OUT_5_PIN SCT_OUT5_PIN #define RTE_SCT_OUT_5_MUX 7 #define RTE_SCT_OUT_5_PAD 31 -#else -#error "Invalid RTE_SCT_OUT_5_PIN Pin Configuration!" -#endif - -//SCT_OUT_6 <0=>GPIO_74 <1=>GPIO_70 - -#define RTE_SCT_OUT_6_PORT_ID 0 -#if ((RTE_SCT_OUT_6_PORT_ID == 1)) -#error "Invalid RTE_SCT_OUT_6_PIN pin Configuration!" -#endif +//Pintool data -#if (RTE_SCT_OUT_6_PORT_ID == 0) -#define RTE_SCT_OUT_6_PORT 0 -#define RTE_SCT_OUT_6_PIN 74 +//Pintool data +#define RTE_SCT_OUT_6_PORT SCT_OUT6_PORT +#define RTE_SCT_OUT_6_PIN SCT_OUT6_PIN #define RTE_SCT_OUT_6_MUX 7 #define RTE_SCT_OUT_6_PAD 32 -#elif (RTE_SCT_OUT_6_PORT_ID == 1) -#define RTE_SCT_OUT_6_PORT 0 -#define RTE_SCT_OUT_6_PIN 70 -#define RTE_SCT_OUT_6_MUX 13 -#define RTE_SCT_OUT_6_PAD 28 -#else -#error "Invalid RTE_SCT_OUT_6_PIN Pin Configuration!" -#endif +//Pintool data -// SCT_OUT_7 <0=>GPIO_75 <1=>GPIO_71 - -#define RTE_SCT_OUT_7_PORT_ID 0 - -#if (RTE_SCT_OUT_7_PORT_ID == 0) -#define RTE_SCT_OUT_7_PORT 0 -#define RTE_SCT_OUT_7_PIN 75 +//Pintool data +#define RTE_SCT_OUT_7_PORT SCT_OUT7_PORT +#define RTE_SCT_OUT_7_PIN SCT_OUT7_PIN #define RTE_SCT_OUT_7_MUX 7 #define RTE_SCT_OUT_7_PAD 33 -#else -#error "Invalid RTE_SCT_OUT_7_PIN Pin Configuration!" -#endif +//Pintool data // SIO // //<> Serial Input Output //SIO_0 <0=>GPIO_6 <1=>GPIO_25 <2=>GPIO_64 <3=>GPIO_72 - +#ifndef SIO_0_LOC #define RTE_SIO_0_PORT_ID 0 #if (RTE_SIO_0_PORT_ID == 0) @@ -2115,9 +3219,31 @@ #else #error "Invalid RTE_SIO_0_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_0_PORT SIO_SIO0_PORT +#define RTE_SIO_0_MUX 1 +#if (SIO_0_LOC == 0) +#define RTE_SIO_0_PIN SIO_SIO0_PIN +#define RTE_SIO_0_PAD 1 +#endif +#if (SIO_0_LOC == 1) +#define RTE_SIO_0_PIN SIO_SIO0_PIN +#define RTE_SIO_0_PAD 0 +#endif +#if (SIO_0_LOC == 2) +#define RTE_SIO_0_PIN (SIO_SIO0_PIN + GPIO_MAX_PIN) +#define RTE_SIO_0_PAD 22 +#endif +#if (SIO_0_LOC == 3) +#define RTE_SIO_0_PIN (SIO_SIO0_PIN + GPIO_MAX_PIN) +#define RTE_SIO_0_PAD 30 +#endif +//Pintool data +#endif //SIO_1 <0=>GPIO_7 <1=>GPIO_26 <2=>GPIO_65 <3=>GPIO_73 - +#ifndef SIO_1_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SIO_1_PORT_ID 1 #else @@ -2147,9 +3273,31 @@ #else #error "Invalid RTE_SIO_1_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_1_PORT SIO_SIO1_PORT +#define RTE_SIO_1_MUX 1 +#if (SIO_1_LOC == 4) +#define RTE_SIO_1_PIN SIO_SIO1_PIN +#define RTE_SIO_1_PAD 2 +#endif +#if (SIO_1_LOC == 5) +#define RTE_SIO_1_PIN SIO_SIO1_PIN +#define RTE_SIO_1_PAD 0 +#endif +#if (SIO_1_LOC == 6) +#define RTE_SIO_1_PIN (SIO_SIO1_PIN + GPIO_MAX_PIN) +#define RTE_SIO_1_PAD 23 +#endif +#if (SIO_1_LOC == 7) +#define RTE_SIO_1_PIN (SIO_SIO1_PIN + GPIO_MAX_PIN) +#define RTE_SIO_1_PAD 31 +#endif +//Pintool data +#endif // SIO_2 <0=>GPIO_8 <1=>GPIO_27 <2=>GPIO_66 <3=>GPIO_74 - +#ifndef SIO_2_LOC #define RTE_SIO_2_PORT_ID 1 #if (RTE_SIO_2_PORT_ID == 0) @@ -2175,9 +3323,27 @@ #else #error "Invalid RTE_SIO_2_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_2_PORT SIO_SIO2_PORT +#define RTE_SIO_2_MUX 1 +#if (SIO_2_LOC == 8) +#define RTE_SIO_2_PIN SIO_SIO2_PIN +#define RTE_SIO_2_PAD 3 +#endif +#if (SIO_2_LOC == 9) +#define RTE_SIO_2_PIN SIO_SIO2_PIN +#define RTE_SIO_2_PAD 0 +#endif +#if (SIO_2_LOC == 10) +#define RTE_SIO_2_PIN (SIO_SIO2_PIN + GPIO_MAX_PIN) +#define RTE_SIO_2_PAD 32 +#endif +//Pintool data +#endif //SIO_3 <0=>GPIO_9 <1=>GPIO_28 <2=>GPIO_67 <3=>GPIO_75 - +#ifndef SIO_3_LOC #define RTE_SIO_3_PORT_ID 1 #if (RTE_SIO_3_PORT_ID == 0) @@ -2203,8 +3369,27 @@ #else #error "Invalid RTE_SIO_3_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_3_PORT SIO_SIO3_PORT +#define RTE_SIO_3_MUX 1 +#if (SIO_3_LOC == 11) +#define RTE_SIO_3_PIN SIO_SIO3_PIN +#define RTE_SIO_3_PAD 4 +#endif +#if (SIO_3_LOC == 12) +#define RTE_SIO_3_PIN SIO_SIO3_PIN +#define RTE_SIO_3_PAD 0 +#endif +#if (SIO_3_LOC == 13) +#define RTE_SIO_3_PIN (SIO_SIO3_PIN + GPIO_MAX_PIN) +#define RTE_SIO_3_PAD 33 +#endif +//Pintool data +#endif //SIO_4 <0=>GPIO_10 <1=>GPIO_29 <2=>GPIO_68 +#ifndef SIO_4_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SIO_4_PORT_ID 1 #else @@ -2223,8 +3408,27 @@ #else #error "Invalid RTE_SIO_3_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_4_PORT SIO_SIO4_PORT +#define RTE_SIO_4_MUX 1 +#if (SIO_4_LOC == 14) +#define RTE_SIO_4_PAD 5 +#define RTE_SIO_4_PIN SIO_SIO4_PIN +#endif +#if (SIO_4_LOC == 15) +#define RTE_SIO_4_PAD 0 +#define RTE_SIO_4_PIN SIO_SIO4_PIN +#endif +#if (SIO_4_LOC == 16) +#define RTE_SIO_4_PAD 26 +#define RTE_SIO_4_PIN (SIO_SIO4_PIN + GPIO_MAX_PIN) +#endif +//Pintool data +#endif // SIO_5 <0=>GPIO_11 <1=>GPIO_30 <2=>GPIO_69 +#ifndef SIO_5_LOC #define RTE_SIO_5_PORT_ID 0 #if (RTE_SIO_5_PORT_ID == 0) #define RTE_SIO_5_PORT 0 @@ -2239,15 +3443,38 @@ #else #error "Invalid RTE_SIO_5_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_5_PORT SIO_SIO5_PORT +#define RTE_SIO_5_MUX 1 +#if (SIO_5_LOC == 17) +#define RTE_SIO_5_PAD 6 +#define RTE_SIO_5_PIN SIO_SIO5_PIN +#endif +#if (SIO_5_LOC == 18) +#define RTE_SIO_5_PAD 0 +#define RTE_SIO_5_PIN SIO_SIO5_PIN +#endif +#if (SIO_5_LOC == 19) +#define RTE_SIO_5_PAD 0 +#define RTE_SIO_5_PIN (SIO_SIO5_PIN + GPIO_MAX_PIN) +#endif +//Pintool data +#endif // SIO_6 GPIO_70 +#ifndef SIO_6_LOC #define RTE_SIO_6_PORT 0 #define RTE_SIO_6_PIN 70 -#define RTE_SIO_6_MUX 1 -#define RTE_SIO_6_PAD 28 +#else +#define RTE_SIO_6_PORT SIO_SIO6_PORT +#define RTE_SIO_6_PIN (SIO_SIO6_PIN + GPIO_MAX_PIN) +#endif +#define RTE_SIO_6_MUX 1 +#define RTE_SIO_6_PAD 28 // SIO_7 <0=>GPIO_15 <1=>GPIO_71 - +#ifndef SIO_7_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SIO_7_PORT_ID 1 #else @@ -2267,10 +3494,24 @@ #else #error "Invalid RTE_SIO_7_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_7_PORT SIO_SIO7_PORT +#define RTE_SIO_7_MUX 1 +#if (SIO_7_LOC == 21) +#define RTE_SIO_7_PIN SIO_SIO7_PIN +#define RTE_SIO_7_PAD 8 +#endif +#if (SIO_7_LOC == 22) +#define RTE_SIO_7_PIN (SIO_SIO7_PIN + GPIO_MAX_PIN) +#define RTE_SIO_7_PAD 29 +#endif +//Pintool data +#endif //<> Pulse Width Modulation //PWM_1H <0=>GPIO_7 <1=>GPIO_64 <2=>GPIO_65 - +#ifndef PWM_1H_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_PWM_1H_PORT_ID 0 #else @@ -2290,9 +3531,24 @@ #else #error "Invalid RTE_PWM_1H_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_1H_PORT PWM_1H_PORT +#if (PWM_1H_LOC == 0) +#define RTE_PWM_1H_PIN PWM_1H_PIN +#define RTE_PWM_1H_MUX 10 +#define RTE_PWM_1H_PAD 2 +#endif +#if (PWM_1H_LOC == 1) +#define RTE_PWM_1H_PIN (PWM_1H_PIN + GPIO_MAX_PIN) +#define RTE_PWM_1H_MUX 8 +#define RTE_PWM_1H_PAD 22 +#endif +//Pintool data +#endif // PWM_1L <0=>GPIO_6 <1=>GPIO_64 <2=>GPIO_64 - +#ifndef PWM_1L_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_PWM_1L_PORT_ID 0 #else @@ -2307,9 +3563,23 @@ #else #error "Invalid RTE_PWM_1L_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_1L_PORT PWM_1L_PORT +#if (PWM_1L_LOC == 2) +#define RTE_PWM_1L_PIN PWM_1L_PIN +#define RTE_PWM_1L_MUX 10 +#define RTE_PWM_1L_PAD 1 +#elif (PWM_1L_LOC == 3) +#define RTE_PWM_1L_PIN (PWM_1L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_1L_MUX 8 +#define RTE_PWM_1L_PAD 22 +#endif +//Pintool data +#endif //PWM_2H <0=>GPIO_9 <1=>GPIO_67 <2=>GPIO_69 - +#ifndef PWM_2H_LOC #define RTE_PWM_2H_PORT_ID 0 #if ((RTE_PWM_2H_PORT_ID == 2)) #error "Invalid RTE_PWM_2H_PIN pin Configuration!" @@ -2328,9 +3598,24 @@ #else #error "Invalid RTE_PWM_2H_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_2H_PORT PWM_2H_PORT +#if (PWM_2H_LOC == 4) +#define RTE_PWM_2H_PIN PWM_2H_PIN +#define RTE_PWM_2H_MUX 10 +#define RTE_PWM_2H_PAD 4 +#endif +#if (PWM_2H_LOC == 5) +#define RTE_PWM_2H_PIN (PWM_2H_PIN + GPIO_MAX_PIN) +#define RTE_PWM_2H_MUX 12 +#define RTE_PWM_2H_PAD 27 +#endif +//Pintool data +#endif // PWM_2L <0=>GPIO_8 <1=>GPIO_66 <2=>GPIO_68 - +#ifndef PWM_2L_LOC #define RTE_PWM_2L_PORT_ID 0 #if ((RTE_PWM_2L_PORT_ID == 2)) #error "Invalid RTE_PWM_2L_PIN pin Configuration!" @@ -2349,8 +3634,29 @@ #else #error "Invalid RTE_PWM_2L_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_2L_PORT PWM_2L_PORT +#if (PWM_2L_LOC == 6) +#define RTE_PWM_2L_PIN PWM_2L_PIN +#define RTE_PWM_2L_MUX 10 +#define RTE_PWM_2L_PAD 3 +#endif +#if (PWM_2L_LOC == 7) +#define RTE_PWM_2L_PIN (PWM_2L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_2L_MUX 8 +#define RTE_PWM_2L_PAD 24 +#endif +#if (PWM_2L_LOC == 8) +#define RTE_PWM_2L_PIN (PWM_2L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_2L_MUX 12 +#define RTE_PWM_2L_PAD 26 +#endif +//Pintool data +#endif // PWM_3H <0=>GPIO_11 <1=>GPIO_69 +#ifndef PWM_3H_LOC #define RTE_PWM_3H_PORT_ID 0 #if (RTE_PWM_3H_PORT_ID == 0) #define RTE_PWM_3H_PORT 0 @@ -2360,8 +3666,23 @@ #else #error "Invalid RTE_PWM_3H_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_3H_PORT PWM_3H_PORT +#if (PWM_3H_LOC == 9) +#define RTE_PWM_3H_PIN PWM_3H_PIN +#define RTE_PWM_3H_MUX 10 +#define RTE_PWM_3H_PAD 6 +#elif (PWM_3H_LOC == 10) +#define RTE_PWM_3H_PIN (PWM_3H_PIN + GPIO_MAX_PIN) +#define RTE_PWM_3H_MUX 8 +#define RTE_PWM_3H_PAD 27 +#endif +//Pintool data +#endif // PWM_3L <0=>GPIO_10 <1=>GPIO_68 +#ifndef PWM_3L_LOC #define RTE_PWM_3L_PORT_ID 0 #if (RTE_PWM_3L_PORT_ID == 0) @@ -2372,9 +3693,23 @@ #else #error "Invalid RTE_PWM_3L_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_3L_PORT PWM_3L_PORT +#if (PWM_3L_LOC == 11) +#define RTE_PWM_3L_PIN PWM_3L_PIN +#define RTE_PWM_3L_MUX 10 +#define RTE_PWM_3L_PAD 5 +#elif (PWM_3L_LOC == 12) +#define RTE_PWM_3L_PIN (PWM_3L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_3L_MUX 8 +#define RTE_PWM_3L_PAD 26 +#endif +//Pintool data +#endif // PWM_4H <0=>GPIO_15 <1=>GPIO_71 - +#ifndef PWM_4H_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_PWM_4H_PORT_ID 1 #else @@ -2394,9 +3729,17 @@ #else #error "Invalid RTE_PWM_4H_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_4H_PORT PWM_4H_PORT +#define RTE_PWM_4H_PIN (PWM_4H_PIN + GPIO_MAX_PIN) +#define RTE_PWM_4H_MUX 8 +#define RTE_PWM_4H_PAD 29 +//Pintool data +#endif // PWM_4H <0=>GPIO_12 <1=>GPIO_70 - +#ifndef PWM_4L_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_PWM_4L_PORT_ID 1 #else @@ -2416,8 +3759,24 @@ #else #error "Invalid RTE_PWM_4L_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_4L_PORT PWM_4L_PORT +#if (PWM_4L_LOC == 14) +#define RTE_PWM_4L_PIN PWM_4L_PIN +#define RTE_PWM_4L_MUX 10 +#define RTE_PWM_4L_PAD 7 +#endif +#if (PWM_4L_LOC == 15) +#define RTE_PWM_4L_PIN (PWM_4L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_4L_MUX 8 +#define RTE_PWM_4L_PAD 28 +#endif +//Pintool data +#endif // PWM_FAULTA <0=>GPIO_25 <1=>GPIO_68 <1=>GPIO_73 +#ifndef PWM_FAULTA_LOC #define RTE_PWM_FAULTA_PORT_ID 0 #if (RTE_PWM_FAULTA_PORT_ID == 0) @@ -2433,8 +3792,29 @@ #else #error "Invalid RTE_PWM_FAULTA_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_FAULTA_PORT PWM_FAULTA_PORT +#if (PWM_FAULTA_LOC == 16) +#define RTE_PWM_FAULTA_PIN PWM_FAULTA_PIN +#define RTE_PWM_FAULTA_MUX 10 +#define RTE_PWM_FAULTA_PAD 0 //no pad +#endif +#if (PWM_FAULTA_LOC == 17) +#define RTE_PWM_FAULTA_PIN (PWM_FAULTA_PIN + GPIO_MAX_PIN) +#define RTE_PWM_FAULTA_MUX 10 +#define RTE_PWM_FAULTA_PAD 26 +#endif +#if (PWM_FAULTA_LOC == 18) +#define RTE_PWM_FAULTA_PIN (PWM_FAULTA_PIN + GPIO_MAX_PIN) +#define RTE_PWM_FAULTA_MUX 8 +#define RTE_PWM_FAULTA_PAD 31 +#endif +//Pintool data +#endif // PWM_FAULTB <0=>GPIO_26 <1=>GPIO_69 <1=>GPIO_74 +#ifndef PWM_FAULTB_LOC #define RTE_PWM_FAULTB_PORT_ID 0 #if (RTE_PWM_FAULTB_PORT_ID == 0) @@ -2450,13 +3830,42 @@ #else #error "Invalid RTE_PWM_FAULTB_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_FAULTB_PORT PWM_FAULTB_PORT +#if (PWM_FAULTB_LOC == 19) +#define RTE_PWM_FAULTB_PIN PWM_FAULTB_PIN +#define RTE_PWM_FAULTB_MUX 10 +#define RTE_PWM_FAULTB_PAD 0 //no pad +#endif +#if (PWM_FAULTB_LOC == 20) +#define RTE_PWM_FAULTB_PIN (PWM_FAULTB_PIN + GPIO_MAX_PIN) +#define RTE_PWM_FAULTB_MUX 10 +#define RTE_PWM_FAULTB_PAD 27 +#endif +#if (PWM_FAULTB_LOC == 21) +#define RTE_PWM_FAULTB_PIN (PWM_FAULTB_PIN + GPIO_MAX_PIN) +#define RTE_PWM_FAULTB_MUX 8 +#define RTE_PWM_FAULTB_PAD 32 +#endif +//Pintool data +#endif + //PWM_SLP_EVENT_TRIG GPIO_72 +#ifndef PWM_EVTTRIG_LOC #define RTE_PWM_SLP_EVENT_TRIG_PORT 0 #define RTE_PWM_SLP_EVENT_TRIG_PIN 72 -#define RTE_PWM_SLP_EVENT_TRIG_MUX 8 -#define RTE_PWM_SLP_EVENT_TRIG_PAD 30 +#else +//Pintool data +#define RTE_PWM_SLP_EVENT_TRIG_PORT PWM_SLEEP_EVT_TRIG_PORT +#define RTE_PWM_SLP_EVENT_TRIG_PIN (PWM_SLEEP_EVT_TRIG_PIN + GPIO_MAX_PIN) +//Pintool data +#endif +#define RTE_PWM_SLP_EVENT_TRIG_MUX 8 +#define RTE_PWM_SLP_EVENT_TRIG_PAD 30 //PWM_TMR_EXT_TRIG_1 <0=>GPIO_27 <1=>GPIO_51 <2=>GPIO_70 <3=>GPIO_75 +#ifndef PWM_EXTTRIG1_LOC #define RTE_PWM_TMR_EXT_TRIG_1_PORT_ID 0 #if (RTE_PWM_TMR_EXT_TRIG_1_PORT_ID == 0) @@ -2482,8 +3891,34 @@ #else #error "Invalid RTE_PWM_TMR_EXT_TRIG_1_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_TMR_EXT_TRIG_1_PORT PWM_TMR_EXT_TRIG_1_PORT +#if (PWM_EXTTRIG1_LOC == 22) +#define RTE_PWM_TMR_EXT_TRIG_1_PIN PWM_TMR_EXT_TRIG_1_PIN +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 0 //no pad +#endif +#if (PWM_EXTTRIG1_LOC == 23) +#define RTE_PWM_TMR_EXT_TRIG_1_PIN PWM_TMR_EXT_TRIG_1_PIN +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 15 +#endif +#if (PWM_EXTTRIG1_LOC == 24) +#define RTE_PWM_TMR_EXT_TRIG_1_PIN (PWM_TMR_EXT_TRIG_1_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 28 +#endif +#if (PWM_EXTTRIG1_LOC == 25) +#define RTE_PWM_TMR_EXT_TRIG_1_PIN (PWM_TMR_EXT_TRIG_1_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 33 +#endif +//Pintool data +#endif //PWM_TMR_EXT_TRIG_2 <0=>GPIO_28 <1=>GPIO_54 <2=>GPIO_71 +#ifndef PWM_EXTTRIG2_LOC #define RTE_PWM_TMR_EXT_TRIG_2_PORT_ID 0 #if (RTE_PWM_TMR_EXT_TRIG_2_PORT_ID == 0) @@ -2504,6 +3939,71 @@ #else #error "Invalid RTE_PWM_TMR_EXT_TRIG_2_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_TMR_EXT_TRIG_2_PORT PWM_TMR_EXT_TRIG_2_PORT +#if (PWM_EXTTRIG2_LOC == 26) +#define RTE_PWM_TMR_EXT_TRIG_2_PIN PWM_TMR_EXT_TRIG_2_PIN +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 0 //no pad +#endif +#if (PWM_EXTTRIG2_LOC == 27) +#define RTE_PWM_TMR_EXT_TRIG_2_PIN PWM_TMR_EXT_TRIG_2_PIN +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 18 +#endif +#if (PWM_EXTTRIG2_LOC == 28) //Combination not available in pin mux +#define RTE_PWM_TMR_EXT_TRIG_2_PIN (PWM_TMR_EXT_TRIG_2_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 29 +#endif +#if (PWM_EXTTRIG2_LOC == 29) +#define RTE_PWM_TMR_EXT_TRIG_2_PIN (PWM_TMR_EXT_TRIG_2_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 29 +#endif +//Pintool data +#endif + +//PWM_TMR_EXT_TRIG_3 +//Pintool data +#define RTE_PWM_TMR_EXT_TRIG_3_PORT PWM_TMR_EXT_TRIG_3_PORT +#if (PWM_EXTTRIG3_LOC == 30) +#define RTE_PWM_TMR_EXT_TRIG_3_PIN PWM_TMR_EXT_TRIG_3_PIN +#define RTE_PWM_TMR_EXT_TRIG_3_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_3_PAD 0 //no pad +#endif +#if (PWM_EXTTRIG3_LOC == 31) +#define RTE_PWM_TMR_EXT_TRIG_3_PIN PWM_TMR_EXT_TRIG_3_PIN +#define RTE_PWM_TMR_EXT_TRIG_3_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_3_PAD 19 +#endif +#if (PWM_EXTTRIG3_LOC == 32) +#define RTE_PWM_TMR_EXT_TRIG_3_PIN (PWM_TMR_EXT_TRIG_3_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_3_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_3_PAD 30 +#endif +//Pintool data + +//PWM_TMR_EXT_TRIG_4 +//Pintool data +#define RTE_PWM_TMR_EXT_TRIG_4_PORT PWM_TMR_EXT_TRIG_4_PORT +#if (PWM_EXTTRIG4_LOC == 33) +#define RTE_PWM_TMR_EXT_TRIG_4_PIN PWM_TMR_EXT_TRIG_4_PIN +#define RTE_PWM_TMR_EXT_TRIG_4_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_4_PAD 0 //no pad +#endif +#if (PWM_EXTTRIG4_LOC == 34) +#define RTE_PWM_TMR_EXT_TRIG_4_PIN PWM_TMR_EXT_TRIG_4_PIN +#define RTE_PWM_TMR_EXT_TRIG_4_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_4_PAD 14 +#endif +#if (PWM_EXTTRIG4_LOC == 35) +#define RTE_PWM_TMR_EXT_TRIG_4_PIN (PWM_TMR_EXT_TRIG_4_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_4_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_4_PAD 31 +#endif +//Pintool data //<> QEI (Quadrature Encode Interface) @@ -2654,6 +4154,339 @@ #endif +//ADC START + +#ifndef ADC_P0_LOC +#define RTE_ADC_P0_PORT 0 +#define RTE_ADC_P0_PIN 0 +#else +#define RTE_ADC_P0_PORT ADC_P0_PORT +#define RTE_ADC_P0_PIN ADC_P0_PIN +#endif +#define RTE_ADC_P0_MUX 1 + +#ifndef ADC_N0_LOC +#define RTE_ADC_N0_PORT 0 +#define RTE_ADC_N0_PIN 1 +#else +#define RTE_ADC_N0_PORT ADC_N0_PORT +#define RTE_ADC_N0_PIN ADC_N0_PIN +#endif +#define RTE_ADC_N0_MUX 1 + +#ifndef ADC_P1_LOC +#define RTE_ADC_P1_PORT 0 +#define RTE_ADC_P1_PIN 2 +#else +#define RTE_ADC_P1_PORT ADC_P1_PORT +#define RTE_ADC_P1_PIN ADC_P1_PIN +#endif +#define RTE_ADC_P1_MUX 1 + +#ifndef ADC_N1_LOC +#define RTE_ADC_N1_PORT 0 +#define RTE_ADC_N1_PIN 3 +#else +#define RTE_ADC_N1_PORT ADC_N1_PORT +#define RTE_ADC_N1_PIN ADC_N1_PIN +#endif +#define RTE_ADC_N1_MUX 1 + +#ifndef ADC_P2_LOC +#define RTE_ADC_P2_PORT 0 +#define RTE_ADC_P2_PIN 4 +#else +#define RTE_ADC_P2_PORT ADC_P2_PORT +#define RTE_ADC_P2_PIN ADC_P2_PIN +#endif +#define RTE_ADC_P2_MUX 1 + +#ifndef ADC_N2_LOC +#define RTE_ADC_N2_PORT 0 +#define RTE_ADC_N2_PIN 5 +#else +#define RTE_ADC_N2_PORT ADC_N2_PORT +#define RTE_ADC_N2_PIN ADC_N2_PIN +#endif +#define RTE_ADC_N2_MUX 1 + +#ifndef ADC_P3_LOC +#define RTE_ADC_P3_PORT 0 +#define RTE_ADC_P3_PIN 6 +#else +#define RTE_ADC_P3_PORT ADC_P3_PORT +#define RTE_ADC_P3_PIN ADC_P3_PIN +#endif +#define RTE_ADC_P3_MUX 1 + +#ifndef ADC_N3_LOC +#define RTE_ADC_N3_PORT 0 +#define RTE_ADC_N3_PIN 11 +#else +#define RTE_ADC_N3_PORT ADC_N3_PORT +#define RTE_ADC_N3_PIN ADC_N3_PIN +#endif +#define RTE_ADC_N3_MUX 1 + +#ifndef ADC_P4_LOC +#define RTE_ADC_P4_PORT 0 +#define RTE_ADC_P4_PIN 8 +#else +#define RTE_ADC_P4_PORT ADC_P4_PORT +#define RTE_ADC_P4_PIN ADC_P4_PIN +#endif +#define RTE_ADC_P4_MUX 1 + +#ifndef ADC_N4_LOC +#define RTE_ADC_N4_PORT 0 +#define RTE_ADC_N4_PIN 9 +#else +#define RTE_ADC_N4_PORT ADC_N4_PORT +#define RTE_ADC_N4_PIN ADC_N4_PIN +#endif +#define RTE_ADC_N4_MUX 1 + +#ifndef ADC_P5_LOC +#define RTE_ADC_P5_PORT 0 +#define RTE_ADC_P5_PIN 10 +#else +#define RTE_ADC_P5_PORT ADC_P5_PORT +#define RTE_ADC_P5_PIN ADC_P5_PIN +#endif +#define RTE_ADC_P5_MUX 1 + +#ifndef ADC_N5_LOC +#define RTE_ADC_N5_PORT 0 +#define RTE_ADC_N5_PIN 7 +#else +#define RTE_ADC_N5_PORT ADC_N5_PORT +#define RTE_ADC_N5_PIN ADC_N5_PIN +#endif +#define RTE_ADC_N5_MUX 1 + +#ifndef ADC_P6_LOC +#define RTE_ADC_P6_PORT 0 +#define RTE_ADC_P6_PIN 25 +#else +#define RTE_ADC_P6_PORT ADC_P6_PORT +#define RTE_ADC_P6_PIN ADC_P6_PIN +#endif +#define RTE_ADC_P6_MUX 1 +#define RTE_ADC_P6_PAD 0 + +#ifndef ADC_N6_LOC +#define RTE_ADC_N6_PORT 0 +#define RTE_ADC_N6_PIN 26 +#else +#define RTE_ADC_N6_PORT ADC_N6_PORT +#define RTE_ADC_N6_PIN ADC_N6_PIN +#endif +#define RTE_ADC_N6_MUX 1 +#define RTE_ADC_N6_PAD 0 + +#ifndef ADC_P7_LOC +#define RTE_ADC_P7_PORT 0 +#define RTE_ADC_P7_PIN 27 +#else +#define RTE_ADC_P7_PORT ADC_P7_PORT +#define RTE_ADC_P7_PIN ADC_P7_PIN +#endif +#define RTE_ADC_P7_MUX 1 +#define RTE_ADC_P7_PAD 0 + +#ifndef ADC_N7_LOC +#define RTE_ADC_N7_PORT 0 +#define RTE_ADC_N7_PIN 28 +#else +#define RTE_ADC_N7_PORT ADC_N7_PORT +#define RTE_ADC_N7_PIN ADC_N7_PIN +#endif +#define RTE_ADC_N7_MUX 1 +#define RTE_ADC_N7_PAD 0 + +#ifndef ADC_P8_LOC +#define RTE_ADC_P8_PORT 0 +#define RTE_ADC_P8_PIN 29 +#else +#define RTE_ADC_P8_PORT ADC_P8_PORT +#define RTE_ADC_P8_PIN ADC_P8_PIN +#endif +#define RTE_ADC_P8_MUX 1 +#define RTE_ADC_P8_PAD 0 + +#ifndef ADC_N8_LOC +#define RTE_ADC_N8_PORT 0 +#define RTE_ADC_N8_PIN 30 +#else +#define RTE_ADC_N8_PORT ADC_N8_PORT +#define RTE_ADC_N8_PIN ADC_N8_PIN +#endif +#define RTE_ADC_N8_MUX 1 +#define RTE_ADC_N8_PAD 0 + +#ifndef ADC_P10_LOC +#define RTE_ADC_P10_PORT 0 +#define RTE_ADC_P10_PIN 1 +#else +#define RTE_ADC_P10_PORT ADC_P10_PORT +#define RTE_ADC_P10_PIN ADC_P10_PIN +#endif +#define RTE_ADC_P10_MUX 1 + +#ifndef ADC_P11_LOC +#define RTE_ADC_P11_PORT 0 +#define RTE_ADC_P11_PIN 3 +#else +#define RTE_ADC_P11_PORT ADC_P11_PORT +#define RTE_ADC_P11_PIN ADC_P11_PIN +#endif +#define RTE_ADC_P11_MUX 1 + +#ifndef ADC_P12_LOC +#define RTE_ADC_P12_PORT 0 +#define RTE_ADC_P12_PIN 5 +#else +#define RTE_ADC_P12_PORT ADC_P12_PORT +#define RTE_ADC_P12_PIN ADC_P12_PIN +#endif +#define RTE_ADC_P12_MUX 1 + +#ifndef ADC_P13_LOC +#define RTE_ADC_P13_PORT 0 +#define RTE_ADC_P13_PIN 11 +#else +#define RTE_ADC_P13_PORT ADC_P13_PORT +#define RTE_ADC_P13_PIN ADC_P13_PIN +#endif +#define RTE_ADC_P13_MUX 1 + +#ifndef ADC_P14_LOC +#define RTE_ADC_P14_PORT 0 +#define RTE_ADC_P14_PIN 9 +#else +#define RTE_ADC_P14_PORT ADC_P14_PORT +#define RTE_ADC_P14_PIN ADC_P14_PIN +#endif +#define RTE_ADC_P14_MUX 1 + +#ifndef ADC_P15_LOC +#define RTE_ADC_P15_PORT 0 +#define RTE_ADC_P15_PIN 7 +#else +#define RTE_ADC_P15_PORT ADC_P15_PORT +#define RTE_ADC_P15_PIN ADC_P15_PIN +#endif +#define RTE_ADC_P15_MUX 1 + +#ifndef ADC_P16_LOC +#define RTE_ADC_P16_PORT 0 +#define RTE_ADC_P16_PIN 26 +#else +#define RTE_ADC_P16_PORT ADC_P16_PORT +#define RTE_ADC_P16_PIN ADC_P16_PIN +#endif +#define RTE_ADC_P16_MUX 1 +#define RTE_ADC_P16_PAD 0 + +#ifndef ADC_P17_LOC +#define RTE_ADC_P17_PORT 0 +#define RTE_ADC_P17_PIN 28 +#else +#define RTE_ADC_P17_PORT ADC_P17_PORT +#define RTE_ADC_P17_PIN ADC_P17_PIN +#endif +#define RTE_ADC_P17_MUX 1 +#define RTE_ADC_P17_PAD 0 + +#ifndef ADC_P18_LOC +#define RTE_ADC_P18_PORT 0 +#define RTE_ADC_P18_PIN 30 +#else +#define RTE_ADC_P18_PORT ADC_P18_PORT +#define RTE_ADC_P18_PIN ADC_P18_PIN +#endif +#define RTE_ADC_P18_MUX 1 +#define RTE_ADC_P18_PAD 0 + +//ADC END + +//COMPARATOR START + +#ifndef COMP1_P0_LOC +#define RTE_COMP1_P0_PORT 0 +#define RTE_COMP1_P0_PIN 0 +#else +#define RTE_COMP1_P0_PORT COMP1_P0_PORT +#define RTE_COMP1_P0_PIN COMP1_P0_PIN +#endif +#define RTE_COMP1_P0_MUX 0 + +#ifndef COMP1_N0_LOC +#define RTE_COMP1_N0_PORT 0 +#define RTE_COMP1_N0_PIN 1 +#else +#define RTE_COMP1_N0_PORT COMP1_N0_PORT +#define RTE_COMP1_N0_PIN COMP1_N0_PIN +#endif +#define RTE_COMP1_N0_MUX 0 + +#ifndef COMP1_P1_LOC +#define RTE_COMP1_P1_PORT 0 +#define RTE_COMP1_P1_PIN 5 +#else +#define RTE_COMP1_P1_PORT COMP1_P1_PORT +#define RTE_COMP1_P1_PIN COMP1_P1_PIN +#endif +#define RTE_COMP1_P1_MUX 0 + +#ifndef COMP1_N1_LOC +#define RTE_COMP1_N1_PORT 0 +#define RTE_COMP1_N1_PIN 4 +#else +#define RTE_COMP1_N1_PORT COMP1_N1_PORT +#define RTE_COMP1_N1_PIN COMP1_N1_PIN +#endif +#define RTE_COMP1_N1_MUX 0 + +#ifndef COMP2_P0_LOC +#define RTE_COMP2_P0_PORT 0 +#define RTE_COMP2_P0_PIN 2 +#else +#define RTE_COMP2_P0_PORT COMP2_P0_PORT +#define RTE_COMP2_P0_PIN COMP2_P0_PIN +#endif +#define RTE_COMP2_P0_MUX 0 + +#ifndef COMP2_N0_LOC +#define RTE_COMP2_N0_PORT 0 +#define RTE_COMP2_N0_PIN 3 +#else +#define RTE_COMP2_N0_PORT COMP2_N0_PORT +#define RTE_COMP2_N0_PIN COMP2_N0_PIN +#endif +#define RTE_COMP2_N0_MUX 0 + +#ifndef COMP2_P1_LOC +#define RTE_COMP2_P1_PORT 0 +#define RTE_COMP2_P1_PIN 27 +#else +#define RTE_COMP2_P1_PORT COMP2_P1_PORT +#define RTE_COMP2_P1_PIN COMP2_P1_PIN +#endif +#define RTE_COMP2_P1_MUX 0 +#define RTE_COMP2_P1_PAD 0 + +#ifndef COMP2_N1_LOC +#define RTE_COMP2_N1_PORT 0 +#define RTE_COMP2_N1_PIN 28 +#else +#define RTE_COMP2_N1_PORT COMP2_N1_PORT +#define RTE_COMP2_N1_PIN COMP2_N1_PIN +#endif +#define RTE_COMP2_N1_MUX 0 + +//COMPARATOR END + #define RTE_GPIO_6_PORT 0 #define RTE_GPIO_6_PAD 1 #define RTE_GPIO_6_PIN 6 @@ -3045,4 +4878,21 @@ #define RTE_UULP_GPIO_4_PORT 5 #define RTE_UULP_GPIO_4_PIN 4 -#define RTE_UULP_GPIO_4_MODE 0 \ No newline at end of file +#define RTE_UULP_GPIO_4_MODE 0 + +#define RTE_UULP_GPIO_5_PIN 5 +#define RTE_UULP_GPIO_5_MODE 0 + +// UULP GPIO as enable pin for sensors +#define SENSOR_ENABLE_GPIO_MAPPED_TO_UULP +#define SENSOR_ENABLE_GPIO_PIN RTE_UULP_GPIO_1_PIN + +// Memlcd GPIOs +#define RTE_MEMLCD_CS_PIN 10 // Memlcd SPI CS pin +#define RTE_MEMLCD_CS_PORT 0 // Memlcd SPI CS port + +#define RTE_MEMLCD_EXTCOMIN_PIN 3 // Memlcd external communication pin +#define RTE_MEMLCD_EXTCOMIN_PORT 0 // Memlcd external communication port + +#define RTE_MEMLCD_ENABLE_DISPLAY_PIN 0 // Memlcd display enable pin +#define RTE_MEMLCD_ENABLE_DISPLAY_PORT 0 // Memlcd display enable port diff --git a/components/board/silabs/config/brd4339a/pin_config.h b/components/board/silabs/config/brd4339a/pin_config.h new file mode 100644 index 000000000..2bbc8c59c --- /dev/null +++ b/components/board/silabs/config/brd4339a/pin_config.h @@ -0,0 +1,140 @@ +#ifndef PIN_CONFIG_H +#define PIN_CONFIG_H + +// $[USART0] +// [USART0]$ + +// $[UART1] +// [UART1]$ + +// $[ULP_UART] +// [ULP_UART]$ + +// $[I2C0] +// [I2C0]$ + +// $[I2C1] +// [I2C1]$ + +// $[ULP_I2C] +// [ULP_I2C]$ + +// $[SSI_MASTER] +// [SSI_MASTER]$ + +// $[SSI_SLAVE] +// [SSI_SLAVE]$ + +// $[ULP_SPI] +// [ULP_SPI]$ + +// $[GSPI_MASTER] +// [GSPI_MASTER]$ + +// $[I2S0] +// [I2S0]$ + +// $[ULP_I2S] +// [ULP_I2S]$ + +// $[SCT] +// [SCT]$ + +// $[SIO] +// [SIO]$ + +// $[PWM] +// [PWM]$ + +// $[PWM_CH0] +// [PWM_CH0]$ + +// $[PWM_CH1] +// [PWM_CH1]$ + +// $[PWM_CH2] +// [PWM_CH2]$ + +// $[PWM_CH3] +// [PWM_CH3]$ + +// $[ADC_CH1] +// [ADC_CH1]$ + +// $[ADC_CH2] +// [ADC_CH2]$ + +// $[ADC_CH3] +// [ADC_CH3]$ + +// $[ADC_CH4] +// [ADC_CH4]$ + +// $[ADC_CH5] +// [ADC_CH5]$ + +// $[ADC_CH6] +// [ADC_CH6]$ + +// $[ADC_CH7] +// [ADC_CH7]$ + +// $[ADC_CH8] +// [ADC_CH8]$ + +// $[ADC_CH9] +// [ADC_CH9]$ + +// $[ADC_CH10] +// [ADC_CH10]$ + +// $[ADC_CH11] +// [ADC_CH11]$ + +// $[ADC_CH12] +// [ADC_CH12]$ + +// $[ADC_CH13] +// [ADC_CH13]$ + +// $[ADC_CH14] +// [ADC_CH14]$ + +// $[ADC_CH15] +// [ADC_CH15]$ + +// $[ADC_CH16] +// [ADC_CH16]$ + +// $[ADC_CH17] +// [ADC_CH17]$ + +// $[ADC_CH18] +// [ADC_CH18]$ + +// $[ADC_CH19] +// [ADC_CH19]$ + +// $[COMP1] +// [COMP1]$ + +// $[COMP2] +// [COMP2]$ + +// $[DAC0] +// [DAC0]$ + +// $[DAC1] +// [DAC1]$ + +// $[CUSTOM_PIN_NAME] +#ifndef _PORT +#define _PORT 0 +#endif +#ifndef _PIN +#define _PIN 6 +#endif + +// [CUSTOM_PIN_NAME]$ + +#endif // PIN_CONFIG_H diff --git a/components/board/silabs/config/brd4339b/RTE_Device_917.h b/components/board/silabs/config/brd4339b/RTE_Device_917.h index bd66908f8..da52615dc 100644 --- a/components/board/silabs/config/brd4339b/RTE_Device_917.h +++ b/components/board/silabs/config/brd4339b/RTE_Device_917.h @@ -17,7 +17,7 @@ * * 3. This notice may not be removed or altered from any source distribution. * - * $Date: 1. December 2016 + * $Date: 1. June 2024 * $Revision: V2.4.4 * * Project: RTE Device Configuration for Si91x 2.0 B0 BRD4339B @@ -47,7 +47,7 @@ #define RTE_BUTTON1_PIN (11U) #define RTE_BUTTON1_PAD 6 -#define RTE_LED0_PORT 0 +#define RTE_LED0_PORT 4 #define RTE_LED0_NUMBER 0 #define RTE_LED0_PIN (2U) @@ -63,7 +63,7 @@ #define RTE_USART0 1 -#define RTE_USART0_CLK_SRC USART_INTFPLLCLK +#define RTE_USART0_CLK_SRC USART_ULPREFCLK #define RTE_USART0_CLK_DIV_FACT 1 #define RTE_USART0_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER @@ -225,7 +225,7 @@ #define RTE_USART0_RX_PORT 0 #define RTE_USART0_RX_PIN 65 #define RTE_USART0_RX_MUX 2 -#define RTE_USART0_RX_PAD 24 +#define RTE_USART0_RX_PAD 23 #elif (RTE_USART0_RX_PORT_ID == 4) #define RTE_USART0_RX_PORT 0 #define RTE_USART0_RX_PIN 70 @@ -255,7 +255,7 @@ #if (USART0_RX_LOC == 12) #define RTE_USART0_RX_PIN (USART0_RX_PIN + GPIO_MAX_PIN) #define RTE_USART0_RX_MUX 2 -#define RTE_USART0_RX_PAD 24 +#define RTE_USART0_RX_PAD 23 #endif #if (USART0_RX_LOC == 13) #define RTE_USART0_RX_PIN (USART0_RX_PIN + GPIO_MAX_PIN) @@ -578,7 +578,7 @@ // Configuration settings for Driver_UART1 in component ::CMSIS Driver:USART #define RTE_UART1 1 -#define RTE_UART1_CLK_SRC USART_INTFPLLCLK +#define RTE_UART1_CLK_SRC USART_ULPREFCLK #define RTE_UART1_CLK_DIV_FACT 1 #define RTE_UART1_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER @@ -4887,3 +4887,13 @@ // UULP GPIO as enable pin for sensors #define SENSOR_ENABLE_GPIO_MAPPED_TO_UULP #define SENSOR_ENABLE_GPIO_PIN RTE_UULP_GPIO_1_PIN + +// Memlcd GPIOs +#define RTE_MEMLCD_CS_PIN 10 // Memlcd SPI CS pin +#define RTE_MEMLCD_CS_PORT 0 // Memlcd SPI CS port + +#define RTE_MEMLCD_EXTCOMIN_PIN 3 // Memlcd external communication pin +#define RTE_MEMLCD_EXTCOMIN_PORT 0 // Memlcd external communication port + +#define RTE_MEMLCD_ENABLE_DISPLAY_PIN 0 // Memlcd display enable pin +#define RTE_MEMLCD_ENABLE_DISPLAY_PORT 0 // Memlcd display enable port diff --git a/components/board/silabs/config/brd4339b/pin_config.h b/components/board/silabs/config/brd4339b/pin_config.h index ab6a56743..2bbc8c59c 100644 --- a/components/board/silabs/config/brd4339b/pin_config.h +++ b/components/board/silabs/config/brd4339b/pin_config.h @@ -46,8 +46,74 @@ // $[PWM] // [PWM]$ -// $[ADC] -// [ADC]$ +// $[PWM_CH0] +// [PWM_CH0]$ + +// $[PWM_CH1] +// [PWM_CH1]$ + +// $[PWM_CH2] +// [PWM_CH2]$ + +// $[PWM_CH3] +// [PWM_CH3]$ + +// $[ADC_CH1] +// [ADC_CH1]$ + +// $[ADC_CH2] +// [ADC_CH2]$ + +// $[ADC_CH3] +// [ADC_CH3]$ + +// $[ADC_CH4] +// [ADC_CH4]$ + +// $[ADC_CH5] +// [ADC_CH5]$ + +// $[ADC_CH6] +// [ADC_CH6]$ + +// $[ADC_CH7] +// [ADC_CH7]$ + +// $[ADC_CH8] +// [ADC_CH8]$ + +// $[ADC_CH9] +// [ADC_CH9]$ + +// $[ADC_CH10] +// [ADC_CH10]$ + +// $[ADC_CH11] +// [ADC_CH11]$ + +// $[ADC_CH12] +// [ADC_CH12]$ + +// $[ADC_CH13] +// [ADC_CH13]$ + +// $[ADC_CH14] +// [ADC_CH14]$ + +// $[ADC_CH15] +// [ADC_CH15]$ + +// $[ADC_CH16] +// [ADC_CH16]$ + +// $[ADC_CH17] +// [ADC_CH17]$ + +// $[ADC_CH18] +// [ADC_CH18]$ + +// $[ADC_CH19] +// [ADC_CH19]$ // $[COMP1] // [COMP1]$ diff --git a/components/board/silabs/config/brd4340a/RTE_Device_917.h b/components/board/silabs/config/brd4340a/RTE_Device_917.h index 71d84eba1..120a801bb 100644 --- a/components/board/silabs/config/brd4340a/RTE_Device_917.h +++ b/components/board/silabs/config/brd4340a/RTE_Device_917.h @@ -17,7 +17,7 @@ * * 3. This notice may not be removed or altered from any source distribution. * - * $Date: 1. December 2016 + * $Date: 1. June 2024 * $Revision: V2.4.4 * * Project: RTE Device Configuration for Si91x 2.0 B0 BRD4340A @@ -47,7 +47,7 @@ #define RTE_BUTTON1_PIN (11U) #define RTE_BUTTON1_PAD 6 -#define RTE_LED0_PORT 0 +#define RTE_LED0_PORT 4 #define RTE_LED0_NUMBER 0 #define RTE_LED0_PIN (2U) @@ -63,7 +63,7 @@ #define RTE_USART0 1 -#define RTE_USART0_CLK_SRC USART_INTFPLLCLK +#define RTE_USART0_CLK_SRC USART_ULPREFCLK #define RTE_USART0_CLK_DIV_FACT 1 #define RTE_USART0_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER @@ -111,19 +111,26 @@ #else //Pintool data #define RTE_USART0_CLK_PORT USART0_CLK_PORT -#define RTE_USART0_CLK_PIN USART0_CLK_PIN #if (USART0_CLK_LOC == 0) +#define RTE_USART0_CLK_PIN USART0_CLK_PIN #define RTE_USART0_CLK_MUX 2 #define RTE_USART0_CLK_PAD 3 #endif #if (USART0_CLK_LOC == 1) +#define RTE_USART0_CLK_PIN USART0_CLK_PIN #define RTE_USART0_CLK_MUX 2 #define RTE_USART0_CLK_PAD 0 //NO PAD #endif #if (USART0_CLK_LOC == 2) +#define RTE_USART0_CLK_PIN USART0_CLK_PIN #define RTE_USART0_CLK_MUX 2 #define RTE_USART0_CLK_PAD 16 #endif +#if (USART0_CLK_LOC == 3) +#define RTE_USART0_CLK_PIN (USART0_CLK_PIN + GPIO_MAX_PIN) +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 22 +#endif //Pintool data #endif @@ -162,22 +169,27 @@ #else //Pintool data #define RTE_USART0_TX_PORT USART0_TX_PORT -#if (USART0_TX_LOC == 0) +#if (USART0_TX_LOC == 4) #define RTE_USART0_TX_PIN USART0_TX_PIN #define RTE_USART0_TX_MUX 2 #define RTE_USART0_TX_PAD 8 #endif -#if (USART0_TX_LOC == 1) +#if (USART0_TX_LOC == 5) #define RTE_USART0_TX_PIN USART0_TX_PIN #define RTE_USART0_TX_MUX 2 #define RTE_USART0_TX_PAD 0 //NO PAD #endif -#if (USART0_TX_LOC == 2) +#if (USART0_TX_LOC == 6) #define RTE_USART0_TX_PIN USART0_TX_PIN #define RTE_USART0_TX_MUX 2 #define RTE_USART0_TX_PAD 18 #endif -#if (USART0_TX_LOC == 3) +#if (USART0_TX_LOC == 7) +#define RTE_USART0_TX_PIN (USART0_TX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 26 +#endif +#if (USART0_TX_LOC == 8) #define RTE_USART0_TX_PIN (USART0_TX_PIN + GPIO_MAX_PIN) #define RTE_USART0_TX_MUX 4 #define RTE_USART0_TX_PAD 29 @@ -213,7 +225,7 @@ #define RTE_USART0_RX_PORT 0 #define RTE_USART0_RX_PIN 65 #define RTE_USART0_RX_MUX 2 -#define RTE_USART0_RX_PAD 24 +#define RTE_USART0_RX_PAD 23 #elif (RTE_USART0_RX_PORT_ID == 4) #define RTE_USART0_RX_PORT 0 #define RTE_USART0_RX_PIN 70 @@ -225,27 +237,27 @@ #else //Pintool data #define RTE_USART0_RX_PORT USART0_RX_PORT -#if (USART0_RX_LOC == 0) +#if (USART0_RX_LOC == 9) #define RTE_USART0_RX_PIN USART0_RX_PIN #define RTE_USART0_RX_MUX 2 #define RTE_USART0_RX_PAD 5 #endif -#if (USART0_RX_LOC == 1) +#if (USART0_RX_LOC == 10) #define RTE_USART0_RX_PIN USART0_RX_PIN #define RTE_USART0_RX_MUX 2 #define RTE_USART0_RX_PAD 0 //no pad #endif -#if (USART0_RX_LOC == 2) +#if (USART0_RX_LOC == 11) #define RTE_USART0_RX_PIN USART0_RX_PIN #define RTE_USART0_RX_MUX 2 #define RTE_USART0_RX_PAD 19 #endif -#if (USART0_RX_LOC == 3) +#if (USART0_RX_LOC == 12) #define RTE_USART0_RX_PIN (USART0_RX_PIN + GPIO_MAX_PIN) #define RTE_USART0_RX_MUX 2 -#define RTE_USART0_RX_PAD 24 +#define RTE_USART0_RX_PAD 23 #endif -#if (USART0_RX_LOC == 4) +#if (USART0_RX_LOC == 13) #define RTE_USART0_RX_PIN (USART0_RX_PIN + GPIO_MAX_PIN) #define RTE_USART0_RX_MUX 4 #define RTE_USART0_RX_PAD 28 @@ -284,22 +296,22 @@ #else //Pintool data #define RTE_USART0_CTS_PORT USART0_CTS_PORT -#if (USART0_CTS_LOC == 0) +#if (USART0_CTS_LOC == 14) #define RTE_USART0_CTS_PIN USART0_CTS_PIN #define RTE_USART0_CTS_MUX 2 #define RTE_USART0_CTS_PAD 1 #endif -#if (USART0_CTS_LOC == 1) +#if (USART0_CTS_LOC == 15) #define RTE_USART0_CTS_PIN USART0_CTS_PIN #define RTE_USART0_CTS_MUX 2 #define RTE_USART0_CTS_PAD 0 //NO PAD #endif -#if (USART0_CTS_LOC == 2) +#if (USART0_CTS_LOC == 16) #define RTE_USART0_CTS_PIN USART0_CTS_PIN #define RTE_USART0_CTS_MUX 2 #define RTE_USART0_CTS_PAD 20 #endif -#if (USART0_CTS_LOC == 3) +#if (USART0_CTS_LOC == 17) #define RTE_USART0_CTS_PIN (USART0_CTS_PIN + GPIO_MAX_PIN) #define RTE_USART0_CTS_MUX 2 #define RTE_USART0_CTS_PAD 28 @@ -333,19 +345,26 @@ #else //Pintool data #define RTE_USART0_RTS_PORT USART0_RTS_PORT -#define RTE_USART0_RTS_PIN USART0_RTS_PIN -#if (USART0_RTS_LOC == 0) +#if (USART0_RTS_LOC == 18) +#define RTE_USART0_RTS_PIN USART0_RTS_PIN #define RTE_USART0_RTS_MUX 2 #define RTE_USART0_RTS_PAD 4 #endif -#if (USART0_RTS_LOC == 1) +#if (USART0_RTS_LOC == 19) +#define RTE_USART0_RTS_PIN USART0_RTS_PIN #define RTE_USART0_RTS_MUX 2 #define RTE_USART0_RTS_PAD 0 //NO PAD #endif -#if (USART0_RTS_LOC == 2) +#if (USART0_RTS_LOC == 20) +#define RTE_USART0_RTS_PIN USART0_RTS_PIN #define RTE_USART0_RTS_MUX 2 #define RTE_USART0_RTS_PAD 17 #endif +#if (USART0_RTS_LOC == 21) +#define RTE_USART0_RTS_PIN (USART0_RTS_PIN + GPIO_MAX_PIN) +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 27 +#endif //Pintool data #endif @@ -378,12 +397,22 @@ #else //Pintool data #define RTE_USART0_IR_TX_PORT USART0_IRTX_PORT -#if (USART0_IRTX_LOC == 0) +#if (USART0_IRTX_LOC == 22) +#define RTE_USART0_IR_TX_PIN USART0_IRTX_PIN +#define RTE_USART0_IR_TX_MUX 13 +#define RTE_USART0_IR_TX_PAD 0 //No pad +#endif +#if (USART0_IRTX_LOC == 23) #define RTE_USART0_IR_TX_PIN USART0_IRTX_PIN #define RTE_USART0_IR_TX_MUX 2 #define RTE_USART0_IR_TX_PAD 12 #endif -#if (USART0_IRTX_LOC == 1) +#if (USART0_IRTX_LOC == 24) +#define RTE_USART0_IR_TX_PIN (USART0_IRTX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_IR_TX_MUX 11 +#define RTE_USART0_IR_TX_PAD 23 +#endif +#if (USART0_IRTX_LOC == 25) #define RTE_USART0_IR_TX_PIN (USART0_IRTX_PIN + GPIO_MAX_PIN) #define RTE_USART0_IR_TX_MUX 2 #define RTE_USART0_IR_TX_PAD 30 @@ -420,12 +449,22 @@ #else //Pintool data #define RTE_USART0_IR_RX_PORT USART0_IRRX_PORT -#if (USART0_IRRX_LOC == 0) +#if (USART0_IRRX_LOC == 26) +#define RTE_USART0_IR_RX_PIN USART0_IRRX_PIN +#define RTE_USART0_IR_RX_MUX 13 +#define RTE_USART0_IR_RX_PAD 0 //no pad +#endif +#if (USART0_IRRX_LOC == 27) #define RTE_USART0_IR_RX_PIN USART0_IRRX_PIN #define RTE_USART0_IR_RX_MUX 2 #define RTE_USART0_IR_RX_PAD 11 #endif -#if (USART0_IRRX_LOC == 1) +#if (USART0_IRRX_LOC == 28) +#define RTE_USART0_IR_RX_PIN (USART0_IRRX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_IR_RX_MUX 11 +#define RTE_USART0_IR_RX_PAD 22 +#endif +#if (USART0_IRRX_LOC == 29) #define RTE_USART0_IR_RX_PIN (USART0_IRRX_PIN + GPIO_MAX_PIN) #define RTE_USART0_IR_RX_MUX 2 #define RTE_USART0_IR_RX_PAD 29 @@ -454,15 +493,21 @@ #else //Pintool data #define RTE_USART0_RI_PORT USART0_RI_PORT -#define RTE_USART0_RI_PIN USART0_RI_PIN -#if (USART0_RI_LOC == 0) +#if (USART0_RI_LOC == 30) +#define RTE_USART0_RI_PIN USART0_RI_PIN #define RTE_USART0_RI_MUX 2 #define RTE_USART0_RI_PAD 0 //no pad #endif -#if (USART0_RI_LOC == 1) +#if (USART0_RI_LOC == 31) +#define RTE_USART0_RI_PIN USART0_RI_PIN #define RTE_USART0_RI_MUX 2 #define RTE_USART0_RI_PAD 10 #endif +#if (USART0_RI_LOC == 32) +#define RTE_USART0_RI_PIN (USART0_RI_PIN + GPIO_MAX_PIN) +#define RTE_USART0_RI_MUX 11 +#define RTE_USART0_RI_PAD 26 +#endif //Pintool data #endif @@ -488,11 +533,11 @@ //Pintool data #define RTE_USART0_DSR_PORT USART0_DSR_PORT #define RTE_USART0_DSR_PIN USART0_DSR_PIN -#if (USART0_DSR_LOC == 0) +#if (USART0_DSR_LOC == 33) #define RTE_USART0_DSR_MUX 2 #define RTE_USART0_DSR_PAD 6 #endif -#if (USART0_DSR_LOC == 1) +#if (USART0_DSR_LOC == 34) #define RTE_USART0_DSR_MUX 2 #define RTE_USART0_DSR_PAD 21 #endif @@ -507,9 +552,14 @@ #else #define RTE_USART0_DCD_PORT USART0_DCD_PORT #define RTE_USART0_DCD_PIN USART0_DCD_PIN -#endif +#if (USART0_DCD_LOC == 35) #define RTE_USART0_DCD_MUX 2 #define RTE_USART0_DCD_PAD 7 +#elif (USART0_DCD_LOC == 36) +#define RTE_USART0_DCD_MUX 12 +#define RTE_USART0_DCD_PAD 0 +#endif +#endif // USART0_DTR <0=>P0_7 // DTR for USART0 @@ -528,7 +578,7 @@ // Configuration settings for Driver_UART1 in component ::CMSIS Driver:USART #define RTE_UART1 1 -#define RTE_UART1_CLK_SRC USART_INTFPLLCLK +#define RTE_UART1_CLK_SRC USART_ULPREFCLK #define RTE_UART1_CLK_DIV_FACT 1 #define RTE_UART1_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER @@ -602,8 +652,8 @@ #endif #if (UART1_TX_LOC == 2) #define RTE_UART1_TX_PIN (UART1_TX_PIN + GPIO_MAX_PIN) -#define RTE_UART1_TX_MUX 9 -#define RTE_UART1_TX_PAD 25 +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 27 #endif #if (UART1_TX_LOC == 3) #define RTE_UART1_TX_PIN (UART1_TX_PIN + GPIO_MAX_PIN) @@ -654,27 +704,27 @@ #else //Pintool data #define RTE_UART1_RX_PORT UART1_RX_PORT -#if (UART1_RX_LOC == 0) +#if (UART1_RX_LOC == 5) #define RTE_UART1_RX_PIN UART1_RX_PIN #define RTE_UART1_RX_MUX 6 #define RTE_UART1_RX_PAD 1 #endif -#if (UART1_RX_LOC == 1) +#if (UART1_RX_LOC == 6) #define RTE_UART1_RX_PIN UART1_RX_PIN #define RTE_UART1_RX_MUX 6 #define RTE_UART1_RX_PAD 0 //no pad #endif -#if (UART1_RX_LOC == 2) +#if (UART1_RX_LOC == 7) #define RTE_UART1_RX_PIN (UART1_RX_PIN + GPIO_MAX_PIN) -#define RTE_UART1_RX_MUX 9 -#define RTE_UART1_RX_PAD 24 +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 26 #endif -#if (UART1_RX_LOC == 3) +#if (UART1_RX_LOC == 8) #define RTE_UART1_RX_PIN (UART1_RX_PIN + GPIO_MAX_PIN) #define RTE_UART1_RX_MUX 6 #define RTE_UART1_RX_PAD 30 #endif -#if (UART1_RX_LOC == 4) +#if (UART1_RX_LOC == 9) #define RTE_UART1_RX_PIN (UART1_RX_PIN + GPIO_MAX_PIN) #define RTE_UART1_RX_MUX 9 #define RTE_UART1_RX_PAD 32 @@ -718,31 +768,36 @@ #else //Pintool data #define RTE_UART1_CTS_PORT UART1_CTS_PORT -#if (UART1_CTS_LOC == 0) +#if (UART1_CTS_LOC == 10) #define RTE_UART1_CTS_PIN UART1_CTS_PIN #define RTE_UART1_CTS_MUX 6 #define RTE_UART1_CTS_PAD 6 #endif -#if (UART1_CTS_LOC == 1) +#if (UART1_CTS_LOC == 11) #define RTE_UART1_CTS_PIN UART1_CTS_PIN #define RTE_UART1_CTS_MUX 6 #define RTE_UART1_CTS_PAD 0 //no pad #endif -#if (UART1_CTS_LOC == 2) +#if (UART1_CTS_LOC == 12) #define RTE_UART1_CTS_PIN UART1_CTS_PIN #define RTE_UART1_CTS_MUX 9 #define RTE_UART1_CTS_PAD 15 #endif -#if (UART1_CTS_LOC == 3) +#if (UART1_CTS_LOC == 13) #define RTE_UART1_CTS_PIN (UART1_CTS_PIN + GPIO_MAX_PIN) #define RTE_UART1_CTS_MUX 9 #define RTE_UART1_CTS_PAD 23 #endif -#if (UART1_CTS_LOC == 4) +#if (UART1_CTS_LOC == 14) #define RTE_UART1_CTS_PIN (UART1_CTS_PIN + GPIO_MAX_PIN) #define RTE_UART1_CTS_MUX 6 #define RTE_UART1_CTS_PAD 29 #endif +#if (UART1_CTS_LOC == 15) +#define RTE_UART1_CTS_PIN (UART1_CTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_CTS_MUX 9 +#define RTE_UART1_CTS_PAD 31 +#endif //Pintool data #endif @@ -786,27 +841,32 @@ #else //Pintool data #define RTE_UART1_RTS_PORT UART1_RTS_PORT -#if (UART1_RTS_LOC == 0) +#if (UART1_RTS_LOC == 16) #define RTE_UART1_RTS_PIN UART1_RTS_PIN #define RTE_UART1_RTS_MUX 6 #define RTE_UART1_RTS_PAD 5 #endif -#if (UART1_RTS_LOC == 1) +#if (UART1_RTS_LOC == 17) #define RTE_UART1_RTS_PIN UART1_RTS_PIN #define RTE_UART1_RTS_MUX 6 #define RTE_UART1_RTS_PAD 0 //no pad #endif -#if (UART1_RTS_LOC == 2) +#if (UART1_RTS_LOC == 18) #define RTE_UART1_RTS_PIN UART1_RTS_PIN #define RTE_UART1_RTS_MUX 9 #define RTE_UART1_RTS_PAD 14 #endif -#if (UART1_RTS_LOC == 3) +#if (UART1_RTS_LOC == 19) +#define RTE_UART1_RTS_PIN (UART1_RTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RTS_MUX 9 +#define RTE_UART1_RTS_PAD 22 +#endif +#if (UART1_RTS_LOC == 20) #define RTE_UART1_RTS_PIN (UART1_RTS_PIN + GPIO_MAX_PIN) #define RTE_UART1_RTS_MUX 6 #define RTE_UART1_RTS_PAD 28 #endif -#if (UART1_RTS_LOC == 4) +#if (UART1_RTS_LOC == 21) #define RTE_UART1_RTS_PIN (UART1_RTS_PIN + GPIO_MAX_PIN) #define RTE_UART1_RTS_MUX 9 #define RTE_UART1_RTS_PAD 30 @@ -918,7 +978,6 @@ #if (RTE_ULP_UART_RTS_PORT_ID == 0) #define RTE_ULP_UART_RTS_PORT 0 #define RTE_ULP_UART_RTS_PIN 10 -#define RTE_ULP_UART_RTS_MUX 8 #else #error "Invalid ULPSS UART RTE_ULP_UART_RTS_PIN Pin Configuration!" #endif @@ -935,7 +994,7 @@ #define RTE_SSI_MASTER 1 // SSI_MASTER_MISO Pin <0=>GPIO_12 <1=>GPIO_27 <2=>GPIO_57 -#ifndef SSI_MASTER_MISO_LOC +#ifndef SSI_MASTER_DATA1_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SSI_MASTER_MISO_PORT_ID 1 #else @@ -966,23 +1025,23 @@ #else //Pintool data #define RTE_SSI_MASTER_MISO 1 -#define RTE_SSI_MASTER_MISO_PORT SSI_MASTER_MISO__PORT -#define RTE_SSI_MASTER_MISO_PIN SSI_MASTER_MISO__PIN +#define RTE_SSI_MASTER_MISO_PORT SSI_MASTER_MISO_DATA1_PORT +#define RTE_SSI_MASTER_MISO_PIN SSI_MASTER_MISO_DATA1_PIN #define RTE_SSI_MASTER_MISO_MODE EGPIO_PIN_MUX_MODE3 -#if (SSI_MASTER_MISO_LOC == 0) +#if (SSI_MASTER_DATA1_LOC == 3) #define RTE_SSI_MASTER_MISO_PADSEL 7 #endif -#if (SSI_MASTER_MISO_LOC == 1) +#if (SSI_MASTER_DATA1_LOC == 4) #define RTE_SSI_MASTER_MISO_PADSEL 0 //NO PAD #endif -#if (SSI_MASTER_MISO_LOC == 2) +#if (SSI_MASTER_DATA1_LOC == 5) #define RTE_SSI_MASTER_MISO_PADSEL 21 #endif //Pintool data #endif // SSI_MASTER_MOSI Pin <0=>GPIO_11 <1=>GPIO_26 <2=>GPIO_56 -#ifndef SSI_MASTER_MOSI_LOC +#ifndef SSI_MASTER_DATA0_LOC #define RTE_SSI_MASTER_MOSI_PORT_ID 1 #if (RTE_SSI_MASTER_MOSI_PORT_ID == 0) @@ -1009,16 +1068,16 @@ #else //Pintool data #define RTE_SSI_MASTER_MOSI 1 -#define RTE_SSI_MASTER_MOSI_PORT SSI_MASTER_MOSI__PORT -#define RTE_SSI_MASTER_MOSI_PIN SSI_MASTER_MOSI__PIN +#define RTE_SSI_MASTER_MOSI_PORT SSI_MASTER_MOSI_DATA0_PORT +#define RTE_SSI_MASTER_MOSI_PIN SSI_MASTER_MOSI_DATA0_PIN #define RTE_SSI_MASTER_MOSI_MODE EGPIO_PIN_MUX_MODE3 -#if (SSI_MASTER_MOSI_LOC == 0) +#if (SSI_MASTER_DATA0_LOC == 0) #define RTE_SSI_MASTER_MOSI_PADSEL 6 #endif -#if (SSI_MASTER_MOSI_LOC == 1) +#if (SSI_MASTER_DATA0_LOC == 1) #define RTE_SSI_MASTER_MOSI_PADSEL 0 //NO PAD #endif -#if (SSI_MASTER_MOSI_LOC == 2) +#if (SSI_MASTER_DATA0_LOC == 2) #define RTE_SSI_MASTER_MOSI_PADSEL 20 #endif //Pintool data @@ -1055,13 +1114,13 @@ #define RTE_SSI_MASTER_SCK_PORT SSI_MASTER_SCK__PORT #define RTE_SSI_MASTER_SCK_PIN SSI_MASTER_SCK__PIN #define RTE_SSI_MASTER_SCK_MODE EGPIO_PIN_MUX_MODE3 -#if (SSI_MASTER_SCK_LOC == 0) +#if (SSI_MASTER_SCK_LOC == 6) #define RTE_SSI_MASTER_SCK_PADSEL 3 #endif -#if (SSI_MASTER_SCK_LOC == 1) +#if (SSI_MASTER_SCK_LOC == 7) #define RTE_SSI_MASTER_SCK_PADSEL 0 //NO PAD #endif -#if (SSI_MASTER_SCK_LOC == 2) +#if (SSI_MASTER_SCK_LOC == 8) #define RTE_SSI_MASTER_SCK_PADSEL 16 #endif //Pintool data @@ -1103,13 +1162,13 @@ #define RTE_SSI_MASTER_CS0_PORT SSI_MASTER_CS0__PORT #define RTE_SSI_MASTER_CS0_PIN SSI_MASTER_CS0__PIN #define RTE_SSI_MASTER_CS0_MODE EGPIO_PIN_MUX_MODE3 -#if (SSI_MASTER_CS0_LOC == 0) +#if (SSI_MASTER_CS0_LOC == 9) #define RTE_SSI_MASTER_CS0_PADSEL 4 #endif -#if (SSI_MASTER_CS0_LOC == 1) +#if (SSI_MASTER_CS0_LOC == 10) #define RTE_SSI_MASTER_CS0_PADSEL 0 //NO PAD #endif -#if (SSI_MASTER_CS0_LOC == 2) +#if (SSI_MASTER_CS0_LOC == 11) #define RTE_SSI_MASTER_CS0_PADSEL 17 #endif //Pintool data @@ -1156,10 +1215,10 @@ #define RTE_SSI_MASTER_CS2_PORT SSI_MASTER_CS2__PORT #define RTE_SSI_MASTER_CS2_PIN SSI_MASTER_CS2__PIN #define RTE_SSI_MASTER_CS2_MODE EGPIO_PIN_MUX_MODE3 -#if (SSI_MASTER_CS2_LOC == 0) +#if (SSI_MASTER_CS2_LOC == 13) #define RTE_SSI_MASTER_CS2_PADSEL 8 #endif -#if (SSI_MASTER_CS2_LOC == 1) +#if (SSI_MASTER_CS2_LOC == 14) #define RTE_SSI_MASTER_CS2_PADSEL 14 #endif //Pintool data @@ -1240,16 +1299,16 @@ #define RTE_SSI_SLAVE_MISO_PORT SSI_SLAVE_MISO__PORT #define RTE_SSI_SLAVE_MISO_PIN SSI_SLAVE_MISO__PIN #define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8 -#if (SSI_SLAVE_MISO_LOC == 1) +#if (SSI_SLAVE_MISO_LOC == 5) #define RTE_SSI_SLAVE_MISO_PADSEL 6 #endif -#if (SSI_SLAVE_MISO_LOC == 2) +#if (SSI_SLAVE_MISO_LOC == 6) #define RTE_SSI_SLAVE_MISO_PADSEL 0 //no pad #endif -#if (SSI_SLAVE_MISO_LOC == 3) +#if (SSI_SLAVE_MISO_LOC == 7) #define RTE_SSI_SLAVE_MISO_PADSEL 13 #endif -#if (SSI_SLAVE_MISO_LOC == 4) +#if (SSI_SLAVE_MISO_LOC == 8) #define RTE_SSI_SLAVE_MISO_PADSEL 21 #endif //Pintool data @@ -1352,16 +1411,16 @@ #define RTE_SSI_SLAVE_SCK_PORT SSI_SLAVE_SCK__PORT #define RTE_SSI_SLAVE_SCK_PIN SSI_SLAVE_SCK__PIN #define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8 -#if (SSI_SLAVE_SCK_LOC == 1) +#if (SSI_SLAVE_SCK_LOC == 9) #define RTE_SSI_SLAVE_SCK_PADSEL 3 #endif -#if (SSI_SLAVE_SCK_LOC == 2) +#if (SSI_SLAVE_SCK_LOC == 10) #define RTE_SSI_SLAVE_SCK_PADSEL 0 //no pad #endif -#if (SSI_SLAVE_SCK_LOC == 3) +#if (SSI_SLAVE_SCK_LOC == 11) #define RTE_SSI_SLAVE_SCK_PADSEL 11 #endif -#if (SSI_SLAVE_SCK_LOC == 4) +#if (SSI_SLAVE_SCK_LOC == 12) #define RTE_SSI_SLAVE_SCK_PADSEL 16 #endif //Pintool data @@ -1406,16 +1465,16 @@ #define RTE_SSI_SLAVE_CS_PORT SSI_SLAVE_CS0__PORT #define RTE_SSI_SLAVE_CS_PIN SSI_SLAVE_CS0__PIN #define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8 -#if (SSI_SLAVE_CS0_LOC == 1) +#if (SSI_SLAVE_CS0_LOC == 13) #define RTE_SSI_SLAVE_CS_PADSEL 4 #endif -#if (SSI_SLAVE_CS0_LOC == 2) +#if (SSI_SLAVE_CS0_LOC == 14) #define RTE_SSI_SLAVE_CS_PADSEL 0 //no pad #endif -#if (SSI_SLAVE_CS0_LOC == 3) +#if (SSI_SLAVE_CS0_LOC == 15) #define RTE_SSI_SLAVE_CS_PADSEL 10 #endif -#if (SSI_SLAVE_CS0_LOC == 4) +#if (SSI_SLAVE_CS0_LOC == 16) #define RTE_SSI_SLAVE_CS_PADSEL 17 #endif //Pintool data @@ -1437,7 +1496,7 @@ // -// SSI_ULP_MASTER (Serial Peripheral Interface 3) [Driver_SSI_ULP_MASTER] +// ULP SPI Peripheral (Serial Peripheral Interface 3) [Driver_SSI_ULP_MASTER] // Configuration settings for Driver_SSI_ULP_MASTER in component ::CMSIS Driver:SPI #define RTE_SSI_ULP_MASTER 1 @@ -1447,7 +1506,7 @@ #define ULP_SSI_CS2 0 // SSI_ULP_MASTER_MISO Pin <0=>Not Used <1=>ULP_GPIO_2 <2=>ULP_GPIO_9 -#ifndef SSI_ULP_MASTER_MISO_LOC +#ifndef ULP_SPI_MISO_LOC #define RTE_SSI_ULP_MASTER_MISO_PORT_ID 0 #if (RTE_SSI_ULP_MASTER_MISO_PORT_ID == 0) #define RTE_SSI_ULP_MASTER_MISO 1 @@ -1465,14 +1524,14 @@ #else //Pintool data #define RTE_SSI_ULP_MASTER_MISO 1 -#define RTE_SSI_ULP_MASTER_MISO_PORT SSI_ULP_MASTER_MISO__PORT -#define RTE_SSI_ULP_MASTER_MISO_PIN SSI_ULP_MASTER_MISO__PIN +#define RTE_SSI_ULP_MASTER_MISO_PORT ULP_SPI_MISO__PORT +#define RTE_SSI_ULP_MASTER_MISO_PIN ULP_SPI_MISO__PIN #define RTE_SSI_ULP_MASTER_MISO_MODE 1 //Pintool data #endif // SSI_ULP_MASTER_MOSI Pin <0=>Not Used <1=>ULP_GPIO_1 <2=>ULP_GPIO_11 -#ifndef SSI_ULP_MASTER_MOSI_LOC +#ifndef ULP_SPI_MOSI_LOC #define RTE_SSI_ULP_MASTER_MOSI_PORT_ID 0 #if (RTE_SSI_ULP_MASTER_MOSI_PORT_ID == 0) #define RTE_SSI_ULP_MASTER_MOSI 1 @@ -1490,14 +1549,14 @@ #else //Pintool data #define RTE_SSI_ULP_MASTER_MOSI 1 -#define RTE_SSI_ULP_MASTER_MOSI_PORT SSI_ULP_MASTER_MOSI__PORT -#define RTE_SSI_ULP_MASTER_MOSI_PIN SSI_ULP_MASTER_MOSI__PIN +#define RTE_SSI_ULP_MASTER_MOSI_PORT ULP_SPI_MOSI__PORT +#define RTE_SSI_ULP_MASTER_MOSI_PIN ULP_SPI_MOSI__PIN #define RTE_SSI_ULP_MASTER_MOSI_MODE 1 //Pintool data #endif // SSI_ULP_MASTER_SCK Pin <0=>Not Used <1=>ULP_GPIO_0 <2=>ULP_GPIO_8 -#ifndef SSI_ULP_MASTER_SCK_LOC +#ifndef ULP_SPI_SCK_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SSI_ULP_MASTER_SCK_PORT_ID 2 #else @@ -1521,14 +1580,14 @@ #else //Pintool data #define RTE_SSI_ULP_MASTER_SCK 1 -#define RTE_SSI_ULP_MASTER_SCK_PORT SSI_ULP_MASTER_SCK__PORT -#define RTE_SSI_ULP_MASTER_SCK_PIN SSI_ULP_MASTER_SCK__PIN +#define RTE_SSI_ULP_MASTER_SCK_PORT ULP_SPI_SCK__PORT +#define RTE_SSI_ULP_MASTER_SCK_PIN ULP_SPI_SCK__PIN #define RTE_SSI_ULP_MASTER_SCK_MODE 1 //Pintool data #endif // CS0 -#ifndef SSI_ULP_MASTER_CS0_LOC +#ifndef ULP_SPI_CS0_LOC #define RTE_SSI_ULP_MASTER_CS0_PORT_ID 1 #if (RTE_SSI_ULP_MASTER_CS0_PORT_ID == 0) #define RTE_SSI_ULP_MASTER_CS0 ULP_SSI_CS0 @@ -1546,30 +1605,30 @@ #else //Pintool data #define RTE_SSI_ULP_MASTER_CS0 ULP_SSI_CS0 -#define RTE_SSI_ULP_MASTER_CS0_PORT SSI_ULP_MASTER_CS0__PORT -#define RTE_SSI_ULP_MASTER_CS0_PIN SSI_ULP_MASTER_CS0__PIN +#define RTE_SSI_ULP_MASTER_CS0_PORT ULP_SPI_CS0__PORT +#define RTE_SSI_ULP_MASTER_CS0_PIN ULP_SPI_CS0__PIN #define RTE_SSI_ULP_MASTER_CS0_MODE 1 //Pintool data #endif // CS1 -#ifndef SSI_ULP_MASTER_CS1_LOC +#ifndef ULP_SPI_CS1_LOC #define RTE_SSI_ULP_MASTER_CS1_PORT 0 #define RTE_SSI_ULP_MASTER_CS1_PIN 4 #else -#define RTE_SSI_ULP_MASTER_CS1_PORT SSI_ULP_MASTER_CS1__PORT -#define RTE_SSI_ULP_MASTER_CS1_PIN SSI_ULP_MASTER_CS1__PIN +#define RTE_SSI_ULP_MASTER_CS1_PORT ULP_SPI_CS1__PORT +#define RTE_SSI_ULP_MASTER_CS1_PIN ULP_SPI_CS1__PIN #endif #define RTE_SSI_ULP_MASTER_CS1 ULP_SSI_CS1 #define RTE_SSI_ULP_MASTER_CS1_MODE 1 // CS2 -#ifndef SSI_ULP_MASTER_CS2_LOC +#ifndef ULP_SPI_CS2_LOC #define RTE_SSI_ULP_MASTER_CS2_PORT 0 #define RTE_SSI_ULP_MASTER_CS2_PIN 6 #else -#define RTE_SSI_ULP_MASTER_CS2_PORT SSI_ULP_MASTER_CS2__PORT -#define RTE_SSI_ULP_MASTER_CS2_PIN SSI_ULP_MASTER_CS2__PIN +#define RTE_SSI_ULP_MASTER_CS2_PORT ULP_SPI_CS2__PORT +#define RTE_SSI_ULP_MASTER_CS2_PIN ULP_SPI_CS2__PIN #endif #define RTE_SSI_ULP_MASTER_CS2 ULP_SSI_CS2 #define RTE_SSI_ULP_MASTER_CS2_MODE 1 @@ -1711,16 +1770,16 @@ #define RTE_I2S0_WSCLK_PORT I2S0_WSCLK_PORT #define RTE_I2S0_WSCLK_PIN I2S0_WSCLK_PIN #define RTE_I2S0_WSCLK_MUX 7 -#if (I2S0_WSCLK_LOC == 0) +#if (I2S0_WSCLK_LOC == 4) #define RTE_I2S0_WSCLK_PAD 4 #endif -#if (I2S0_WSCLK_LOC == 1) +#if (I2S0_WSCLK_LOC == 5) #define RTE_I2S0_WSCLK_PAD 0 #endif -#if (I2S0_WSCLK_LOC == 2) +#if (I2S0_WSCLK_LOC == 6) #define RTE_I2S0_WSCLK_PAD 11 #endif -#if (I2S0_WSCLK_LOC == 3) +#if (I2S0_WSCLK_LOC == 7) #define RTE_I2S0_WSCLK_PAD 17 #endif //Pintool data @@ -1759,16 +1818,16 @@ #define RTE_I2S0_DOUT0_PORT I2S0_DOUT0_PORT #define RTE_I2S0_DOUT0_PIN I2S0_DOUT0_PIN #define RTE_I2S0_DOUT0_MUX 7 -#if (I2S0_DOUT0_LOC == 0) +#if (I2S0_DOUT0_LOC == 8) #define RTE_I2S0_DOUT0_PAD 6 #endif -#if (I2S0_DOUT0_LOC == 1) +#if (I2S0_DOUT0_LOC == 9) #define RTE_I2S0_DOUT0_PAD 0 #endif -#if (I2S0_DOUT0_LOC == 2) +#if (I2S0_DOUT0_LOC == 10) #define RTE_I2S0_DOUT0_PAD 13 #endif -#if (I2S0_DOUT0_LOC == 3) +#if (I2S0_DOUT0_LOC == 11) #define RTE_I2S0_DOUT0_PAD 21 #endif //Pintool data @@ -1807,16 +1866,16 @@ #define RTE_I2S0_DIN0_PORT I2S0_DIN0_PORT #define RTE_I2S0_DIN0_PIN I2S0_DIN0_PIN #define RTE_I2S0_DIN0_MUX 7 -#if (I2S0_DIN0_LOC == 0) +#if (I2S0_DIN0_LOC == 12) #define RTE_I2S0_DIN0_PAD 5 #endif -#if (I2S0_DIN0_LOC == 1) +#if (I2S0_DIN0_LOC == 13) #define RTE_I2S0_DIN0_PAD 0 #endif -#if (I2S0_DIN0_LOC == 2) +#if (I2S0_DIN0_LOC == 14) #define RTE_I2S0_DIN0_PAD 12 #endif -#if (I2S0_DIN0_LOC == 3) +#if (I2S0_DIN0_LOC == 15) #define RTE_I2S0_DIN0_PAD 20 #endif //Pintool data @@ -1859,16 +1918,16 @@ #define RTE_I2S0_DOUT1_PORT I2S0_DOUT1_PORT #define RTE_I2S0_DOUT1_PIN I2S0_DOUT1_PIN #define RTE_I2S0_DOUT1_MUX 7 -#if (I2S0_DOUT1_LOC == 0) +#if (I2S0_DOUT1_LOC == 16) #define RTE_I2S0_DOUT1_PAD 2 #endif -#if (I2S0_DOUT1_LOC == 1) +#if (I2S0_DOUT1_LOC == 17) #define RTE_I2S0_DOUT1_PAD 0 #endif -#if (I2S0_DOUT1_LOC == 2) +#if (I2S0_DOUT1_LOC == 18) #define RTE_I2S0_DOUT1_PAD 15 #endif -#if (I2S0_DOUT1_LOC == 3) +#if (I2S0_DOUT1_LOC == 19) #define RTE_I2S0_DOUT1_PAD 19 #endif //Pintool data @@ -1907,22 +1966,22 @@ #define RTE_I2S0_DIN1_PORT I2S0_DIN1_PORT #define RTE_I2S0_DIN1_PIN I2S0_DIN1_PIN #define RTE_I2S0_DIN1_MUX 7 -#if (I2S0_DIN1_LOC == 0) +#if (I2S0_DIN1_LOC == 20) #define RTE_I2S0_DIN1_PAD 1 #endif -#if (I2S0_DIN1_LOC == 1) +#if (I2S0_DIN1_LOC == 21) #define RTE_I2S0_DIN1_PAD 0 #endif -#if (I2S0_DIN1_LOC == 2) +#if (I2S0_DIN1_LOC == 22) #define RTE_I2S0_DIN1_PAD 14 #endif -#if (I2S0_DIN1_LOC == 3) +#if (I2S0_DIN1_LOC == 23) #define RTE_I2S0_DIN1_PAD 18 #endif //Pintool data #endif -// FIFO level can have value 1 to 7 -#define I2S0_TX_FIFO_LEVEL (2U) +// FIFO level can have value 0 to 7 +#define I2S0_TX_FIFO_LEVEL (0U) #define I2S0_RX_FIFO_LEVEL (2U) // I2S0_TX_RES <0=>12 @@ -1970,14 +2029,14 @@ // -// I2S1 [Driver_I2S1] +// ULP I2S [Driver_I2S1] // Configuration settings for Driver_I2S1 in component ::Drivers:I2S #define RTE_I2S1 1 #define I2S1_IRQHandler IRQ014_Handler // I2S1_SCLK Pin <0=>P0_3 <1=>P0_7 <2=>P0_8 /*I2S1 PINS*/ -#ifndef I2S1_SCLK_LOC +#ifndef ULP_I2S_SCLK_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_I2S1_SCLK_PORT_ID 0 #else @@ -2000,14 +2059,14 @@ #endif #else //Pintool data -#define RTE_I2S1_SCLK_PORT I2S1_SCLK_PORT -#define RTE_I2S1_SCLK_PIN I2S1_SCLK_PIN +#define RTE_I2S1_SCLK_PORT ULP_I2S_SCLK_PORT +#define RTE_I2S1_SCLK_PIN ULP_I2S_SCLK_PIN #define RTE_I2S1_SCLK_MUX 2 //Pintool data #endif // I2S1_WSCLK Pin <0=>P0_2 <1=>P0_4 <2=>P0_10 -#ifndef I2S1_WSCLK_LOC +#ifndef ULP_I2S_WSCLK_LOC #define RTE_I2S1_WSCLK_PORT_ID 0 #if (RTE_I2S1_WSCLK_PORT_ID == 0) #define RTE_I2S1_WSCLK_PORT 0 @@ -2022,14 +2081,14 @@ #endif #else //Pintool data -#define RTE_I2S1_WSCLK_PORT I2S1_WSCLK_PORT -#define RTE_I2S1_WSCLK_PIN I2S1_WSCLK_PIN +#define RTE_I2S1_WSCLK_PORT ULP_I2S_WSCLK_PORT +#define RTE_I2S1_WSCLK_PIN ULP_I2S_WSCLK_PIN #define RTE_I2S1_WSCLK_MUX 2 //Pintool data #endif // I2S1_DOUT0 Pin <0=>P0_1 <1=>P0_5 <2=>P0_11 -#ifndef I2S1_DOUT0_LOC +#ifndef ULP_I2S_DOUT0_LOC #define RTE_I2S1_DOUT0_PORT_ID 0 #if (RTE_I2S1_DOUT0_PORT_ID == 0) #define RTE_I2S1_DOUT0_PORT 0 @@ -2044,14 +2103,14 @@ #endif #else //Pintool data -#define RTE_I2S1_DOUT0_PORT I2S1_DOUT0_PORT -#define RTE_I2S1_DOUT0_PIN I2S1_DOUT0_PIN +#define RTE_I2S1_DOUT0_PORT ULP_I2S_DOUT0_PORT +#define RTE_I2S1_DOUT0_PIN ULP_I2S_DOUT0_PIN #define RTE_I2S1_DOUT0_MUX 2 //Pintool data #endif // I2S1_DIN0 Pin <0=>P0_0 <1=>P0_6 <2=>P0_9 <3=>P0_13 -#ifndef I2S1_DIN0_LOC +#ifndef ULP_I2S_DIN0_LOC #define RTE_I2S1_DIN0_PORT_ID 1 #if (RTE_I2S1_DIN0_PORT_ID == 0) #define RTE_I2S1_DIN0_PORT 0 @@ -2070,14 +2129,14 @@ #endif #else //Pintool data -#define RTE_I2S1_DIN0_PORT I2S1_DIN0_PORT -#define RTE_I2S1_DIN0_PIN I2S1_DIN0_PIN +#define RTE_I2S1_DIN0_PORT ULP_I2S_DIN0_PORT +#define RTE_I2S1_DIN0_PIN ULP_I2S_DIN0_PIN #define RTE_I2S1_DIN0_MUX 2 //Pintool data #endif -// FIFO level can have value 1 to 7 -#define I2S1_TX_FIFO_LEVEL (2U) +// FIFO level can have value 0 to 7 +#define I2S1_TX_FIFO_LEVEL (0U) #define I2S1_RX_FIFO_LEVEL (2U) // I2S1_TX_RES <0=>12 @@ -2180,12 +2239,6 @@ #if (I2C0_SCL_LOC == 2) #define RTE_I2C0_SCL_PIN (I2C0_SCL_PIN + GPIO_MAX_PIN) #define RTE_I2C0_SCL_MUX 4 -#define RTE_I2C0_SCL_PAD 24 -#define RTE_I2C0_SCL_I2C_REN 2 -#endif -#if (I2C0_SCL_LOC == 3) -#define RTE_I2C0_SCL_PIN (I2C0_SCL_PIN + GPIO_MAX_PIN) -#define RTE_I2C0_SCL_MUX 4 #define RTE_I2C0_SCL_PAD 33 #define RTE_I2C0_SCL_I2C_REN 11 #endif @@ -2224,19 +2277,19 @@ #else //Pintool data #define RTE_I2C0_SDA_PORT I2C0_SDA_PORT -#if (I2C0_SDA_LOC == 0) +#if (I2C0_SDA_LOC == 3) #define RTE_I2C0_SDA_PIN I2C0_SDA_PIN #define RTE_I2C0_SDA_MUX 4 #define RTE_I2C0_SDA_PAD 1 #define RTE_I2C0_SDA_I2C_REN 6 #endif -#if (I2C0_SDA_LOC == 1) +#if (I2C0_SDA_LOC == 4) #define RTE_I2C0_SDA_PIN (I2C0_SDA_PIN + GPIO_MAX_PIN) #define RTE_I2C0_SDA_MUX 4 -#define RTE_I2C0_SDA_PAD 25 +#define RTE_I2C0_SDA_PAD 22 #define RTE_I2C0_SDA_I2C_REN 3 #endif -#if (I2C0_SDA_LOC == 2) +#if (I2C0_SDA_LOC == 5) #define RTE_I2C0_SDA_PIN (I2C0_SDA_PIN + GPIO_MAX_PIN) #define RTE_I2C0_SDA_MUX 4 #define RTE_I2C0_SDA_PAD 32 @@ -2253,7 +2306,7 @@ #define DMA_TX_TL 1 #define DMA_RX_TL 1 #endif -// I2C0 [Driver_I2C0] +// I2C1 [Driver_I2C0] // I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1] // Configuration settings for Driver_I2C1 in component ::Drivers:I2C @@ -2330,13 +2383,13 @@ #define RTE_I2C1_SCL_PAD 18 #define RTE_I2C1_SCL_REN 54 #endif -#if (I2C1_SCL_LOC == 5) +#if (I2C1_SCL_LOC == 4) #define RTE_I2C1_SCL_PIN (I2C1_SCL_PIN + GPIO_MAX_PIN) #define RTE_I2C1_SCL_MUX 5 -#define RTE_I2C1_SCL_PAD 24 +#define RTE_I2C1_SCL_PAD 22 #define RTE_I2C1_SCL_REN 2 #endif -#if (I2C1_SCL_LOC == 6) +#if (I2C1_SCL_LOC == 5) #define RTE_I2C1_SCL_PIN (I2C1_SCL_PIN + GPIO_MAX_PIN) #define RTE_I2C1_SCL_MUX 5 #define RTE_I2C1_SCL_PAD 29 @@ -2397,43 +2450,37 @@ #else //Pintool data #define RTE_I2C1_SDA_PORT I2C1_SDA_PORT -#if (I2C1_SDA_LOC == 0) +#if (I2C1_SDA_LOC == 6) #define RTE_I2C1_SDA_PIN I2C1_SDA_PIN #define RTE_I2C1_SDA_MUX 5 #define RTE_I2C1_SDA_PAD 2 #define RTE_I2C1_SDA_REN 7 #endif -#if (I2C1_SDA_LOC == 1) +#if (I2C1_SDA_LOC == 7) #define RTE_I2C1_SDA_PIN I2C1_SDA_PIN #define RTE_I2C1_SDA_MUX 5 #define RTE_I2C1_SDA_PAD 0 //no pad #define RTE_I2C1_SDA_REN 30 #endif -#if (I2C1_SDA_LOC == 2) +#if (I2C1_SDA_LOC == 8) #define RTE_I2C1_SDA_PIN I2C1_SDA_PIN #define RTE_I2C1_SDA_MUX 5 #define RTE_I2C1_SDA_PAD 15 #define RTE_I2C1_SDA_REN 51 #endif -#if (I2C1_SDA_LOC == 3) +#if (I2C1_SDA_LOC == 9) #define RTE_I2C1_SDA_PIN I2C1_SDA_PIN #define RTE_I2C1_SDA_MUX 5 #define RTE_I2C1_SDA_PAD 19 #define RTE_I2C1_SDA_REN 55 #endif -#if (I2C1_SDA_LOC == 4) +#if (I2C1_SDA_LOC == 10) #define RTE_I2C1_SDA_PIN (I2C1_SDA_PIN + GPIO_MAX_PIN) #define RTE_I2C1_SDA_MUX 5 #define RTE_I2C1_SDA_PAD 23 #define RTE_I2C1_SDA_REN 1 #endif -#if (I2C1_SDA_LOC == 5) -#define RTE_I2C1_SDA_PIN (I2C1_SDA_PIN + GPIO_MAX_PIN) -#define RTE_I2C1_SDA_MUX 5 -#define RTE_I2C1_SDA_PAD 25 -#define RTE_I2C1_SDA_REN 3 -#endif -#if (I2C1_SDA_LOC == 6) +#if (I2C1_SDA_LOC == 11) #define RTE_I2C1_SDA_PIN (I2C1_SDA_PIN + GPIO_MAX_PIN) #define RTE_I2C1_SDA_MUX 5 #define RTE_I2C1_SDA_PAD 29 @@ -2453,13 +2500,13 @@ // I2C1 [Driver_I2C1] -// I2C2 (Inter-integrated Circuit Interface 2) [Driver_I2C2] +// ULP I2C (Inter-integrated Circuit Interface 2) [Driver_I2C2] // Configuration settings for Driver_I2C2 in component ::Drivers:I2C #define RTE_I2C2 1 #define I2C2_IRQHandler IRQ013_Handler // I2C2_SCL Pin <0=>P0_1 <1=>P0_5 <2=>P0_7 <3=>P0_8 <4=>P0_13 -#ifndef I2C2_SCL_LOC +#ifndef ULP_I2C_SCL_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_I2C2_SCL_PORT_ID 0 #else @@ -2480,20 +2527,23 @@ #endif #else //Pintool data -#define RTE_I2C2_SCL_PORT I2C2_SCL_PORT -#define RTE_I2C2_SCL_PIN I2C2_SCL_PIN +#define RTE_I2C2_SCL_PORT ULP_I2C_SCL_PORT +#define RTE_I2C2_SCL_PIN ULP_I2C_SCL_PIN #define RTE_I2C2_SCL_MUX 4 -#if (I2C2_SCL_LOC == 0) +#if (ULP_I2C_SCL_LOC == 0) +#define RTE_I2C2_SCL_REN 0 +#elif (ULP_I2C_SCL_LOC == 1) +#define RTE_I2C2_SCL_REN 0 +#elif (ULP_I2C_SCL_LOC == 2) #define RTE_I2C2_SCL_REN 7 -#endif -#if (I2C2_SCL_LOC == 1) +#elif (ULP_I2C_SCL_LOC == 3) #define RTE_I2C2_SCL_REN 8 #endif //Pintool data #endif // I2C2_SDA Pin <0=>P0_0 <1=>P0_4 <2=>P0_6 <3=>P0_9 <4=>P0_11 <5=>P0_12 -#ifndef I2C2_SDA_LOC +#ifndef ULP_I2C_SDA_LOC #define RTE_I2C2_SDA_PORT_ID 0 #if (RTE_I2C2_SDA_PORT_ID == 0) #define RTE_I2C2_SDA_PORT 0 @@ -2501,10 +2551,10 @@ #define RTE_I2C2_SDA_MUX 4 #define RTE_I2C2_SDA_REN 6 #elif (RTE_I2C2_SDA_PORT_ID == 1) -#define RTE_I2C2_SDA_PORT 0 -#define RTE_I2C2_SDA_PIN 9 -#define RTE_I2C2_SDA_MUX 4 -#define RTE_I2C2_SDA_I2C_REN 9 +#define RTE_I2C2_SDA_PORT 0 +#define RTE_I2C2_SDA_PIN 9 +#define RTE_I2C2_SDA_MUX 4 +#define RTE_I2C2_SDA_REN 9 #elif (RTE_I2C2_SDA_PORT_ID == 2) #define RTE_I2C2_SDA_PORT 0 #define RTE_I2C2_SDA_PIN 11 @@ -2518,14 +2568,16 @@ #define RTE_I2C2_SDA_PORT I2C2_SDA_PORT #define RTE_I2C2_SDA_PIN I2C2_SDA_PIN #define RTE_I2C2_SDA_MUX 4 -#if (I2C2_SDA_LOC == 0) +#if (ULP_I2C_SDA_LOC == 4) +#define RTE_I2C2_SDA_REN 0 +#elif (ULP_I2C_SDA_LOC == 5) +#define RTE_I2C2_SDA_REN 0 +#elif (ULP_I2C_SDA_LOC == 6) #define RTE_I2C2_SDA_REN 6 -#endif -#if (I2C2_SDA_LOC == 1) -#define RTE_I2C2_SDA_MUX 4 -#endif -#if (I2C2_SDA_LOC == 2) -#define RTE_I2C2_SDA_MUX 4 +#elif (ULP_I2C_SDA_LOC == 7) +#define RTE_I2C2_SDA_REN 9 +#elif (ULP_I2C_SDA_LOC == 8) +#define RTE_I2C2_SDA_REN 11 #endif //Pintool data #endif @@ -2633,16 +2685,16 @@ #define RTE_GSPI_MASTER_CS0_PORT GSPI_MASTER_CS0__PORT #define RTE_GSPI_MASTER_CS0_PIN GSPI_MASTER_CS0__PIN #define RTE_GSPI_MASTER_CS0_MUX 4 -#if (GSPI_MASTER_CS0_LOC == 0) +#if (GSPI_MASTER_CS0_LOC == 4) #define RTE_GSPI_MASTER_CS0_PAD 4 #endif -#if (GSPI_MASTER_CS0_LOC == 1) +#if (GSPI_MASTER_CS0_LOC == 5) #define RTE_GSPI_MASTER_CS0_PAD 0 #endif -#if (GSPI_MASTER_CS0_LOC == 2) +#if (GSPI_MASTER_CS0_LOC == 6) #define RTE_GSPI_MASTER_CS0_PAD 13 #endif -#if (GSPI_MASTER_CS0_LOC == 3) +#if (GSPI_MASTER_CS0_LOC == 7) #define RTE_GSPI_MASTER_CS0_PAD 17 #endif //Pintool data @@ -2687,16 +2739,16 @@ #define RTE_GSPI_MASTER_CS1_PORT GSPI_MASTER_CS1__PORT #define RTE_GSPI_MASTER_CS1_PIN GSPI_MASTER_CS1__PIN #define RTE_GSPI_MASTER_CS1_MUX 4 -#if (GSPI_MASTER_CS1_LOC == 0) +#if (GSPI_MASTER_CS1_LOC == 8) #define RTE_GSPI_MASTER_CS1_PAD 5 #endif -#if (GSPI_MASTER_CS1_LOC == 1) +#if (GSPI_MASTER_CS1_LOC == 9) #define RTE_GSPI_MASTER_CS1_PAD 0 #endif -#if (GSPI_MASTER_CS1_LOC == 2) +#if (GSPI_MASTER_CS1_LOC == 10) #define RTE_GSPI_MASTER_CS1_PAD 14 #endif -#if (GSPI_MASTER_CS1_LOC == 3) +#if (GSPI_MASTER_CS1_LOC == 11) #define RTE_GSPI_MASTER_CS1_PAD 18 #endif //Pintool data @@ -2741,16 +2793,16 @@ #define RTE_GSPI_MASTER_CS2_PORT GSPI_MASTER_CS2__PORT #define RTE_GSPI_MASTER_CS2_PIN GSPI_MASTER_CS2__PIN #define RTE_GSPI_MASTER_CS2_MUX 4 -#if (GSPI_MASTER_CS2_LOC == 0) +#if (GSPI_MASTER_CS2_LOC == 12) #define RTE_GSPI_MASTER_CS2_PAD 8 #endif -#if (GSPI_MASTER_CS2_LOC == 1) +#if (GSPI_MASTER_CS2_LOC == 13) #define RTE_GSPI_MASTER_CS2_PAD 0 #endif -#if (GSPI_MASTER_CS2_LOC == 2) +#if (GSPI_MASTER_CS2_LOC == 14) #define RTE_GSPI_MASTER_CS2_PAD 15 #endif -#if (GSPI_MASTER_CS2_LOC == 3) +#if (GSPI_MASTER_CS2_LOC == 15) #define RTE_GSPI_MASTER_CS2_PAD 19 #endif //Pintool data @@ -2793,19 +2845,26 @@ //Pintool data #define RTE_GSPI_MASTER_MOSI_PORT GSPI_MASTER_MOSI__PORT #define RTE_GSPI_MASTER_MOSI_PIN GSPI_MASTER_MOSI__PIN -#define RTE_GSPI_MASTER_MOSI_MUX 4 -#if (GSPI_MASTER_MOSI_LOC == 0) +#if (GSPI_MASTER_MOSI_LOC == 16) +#define RTE_GSPI_MASTER_MOSI_MUX 4 #define RTE_GSPI_MASTER_MOSI_PAD 1 #endif -#if (GSPI_MASTER_MOSI_LOC == 1) +#if (GSPI_MASTER_MOSI_LOC == 17) +#define RTE_GSPI_MASTER_MOSI_MUX 4 #define RTE_GSPI_MASTER_MOSI_PAD 0 #endif -#if (GSPI_MASTER_MOSI_LOC == 2) +#if (GSPI_MASTER_MOSI_LOC == 18) +#define RTE_GSPI_MASTER_MOSI_MUX 4 #define RTE_GSPI_MASTER_MOSI_PAD 12 #endif -#if (GSPI_MASTER_MOSI_LOC == 3) +#if (GSPI_MASTER_MOSI_LOC == 19) +#define RTE_GSPI_MASTER_MOSI_MUX 4 #define RTE_GSPI_MASTER_MOSI_PAD 21 #endif +#if (GSPI_MASTER_MOSI_LOC == 20) +#define RTE_GSPI_MASTER_MOSI_MUX 12 +#define RTE_GSPI_MASTER_MOSI_PAD 1 +#endif //Pintool data #endif @@ -2842,16 +2901,16 @@ #define RTE_GSPI_MASTER_MISO_PORT GSPI_MASTER_MISO__PORT #define RTE_GSPI_MASTER_MISO_PIN GSPI_MASTER_MISO__PIN #define RTE_GSPI_MASTER_MISO_MUX 4 -#if (GSPI_MASTER_MISO_LOC == 0) +#if (GSPI_MASTER_MISO_LOC == 21) #define RTE_GSPI_MASTER_MISO_PAD 6 #endif -#if (GSPI_MASTER_MISO_LOC == 1) +#if (GSPI_MASTER_MISO_LOC == 22) #define RTE_GSPI_MASTER_MISO_PAD 0 #endif -#if (GSPI_MASTER_MISO_LOC == 2) +#if (GSPI_MASTER_MISO_LOC == 23) #define RTE_GSPI_MASTER_MISO_PAD 11 #endif -#if (GSPI_MASTER_MISO_LOC == 3) +#if (GSPI_MASTER_MISO_LOC == 24) #define RTE_GSPI_MASTER_MISO_PAD 20 #endif //Pintool data @@ -2897,17 +2956,29 @@ #if (RTE_SCT_IN_0_PORT_ID == 0) #define RTE_SCT_IN_0_PORT 0 #define RTE_SCT_IN_0_PIN 25 +#define RTE_SCT_IN_0_MUX 9 +#define RTE_SCT_IN_0_PAD 0 //no pad #else #error "Invalid RTE_SCT_IN_0_PIN Pin Configuration!" #endif #else //Pintool data #define RTE_SCT_IN_0_PORT SCT_IN0_PORT -#define RTE_SCT_IN_0_PIN SCT_IN0_PIN -//Pintool data -#endif +#if (SCT_IN0_LOC == 0) +#define RTE_SCT_IN_0_PIN SCT_IN0_PIN #define RTE_SCT_IN_0_MUX 9 #define RTE_SCT_IN_0_PAD 0 //no pad +#elif (SCT_IN0_LOC == 1) +#define RTE_SCT_IN_0_PIN (SCT_IN0_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_0_MUX 7 +#define RTE_SCT_IN_0_PAD 22 +#elif (SCT_IN0_LOC == 2) +#define RTE_SCT_IN_0_PIN (SCT_IN0_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_0_MUX 9 +#define RTE_SCT_IN_0_PAD 26 +#endif +//Pintool data +#endif //SCT_IN_1 <0=>GPIO_26 <1=>GPIO_65 <2=>GPIO_69 #ifndef SCT_IN1_LOC @@ -2929,16 +3000,21 @@ #else //Pintool data #define RTE_SCT_IN_1_PORT SCT_IN1_PORT -#if (SCT_IN1_LOC == 0) +#if (SCT_IN1_LOC == 3) #define RTE_SCT_IN_1_PIN SCT_IN1_PIN #define RTE_SCT_IN_1_MUX 9 #define RTE_SCT_IN_1_PAD 0 //no pad #endif -#if (SCT_IN1_LOC == 1) +#if (SCT_IN1_LOC == 4) #define RTE_SCT_IN_1_PIN (SCT_IN1_PIN + GPIO_MAX_PIN) #define RTE_SCT_IN_1_MUX 7 #define RTE_SCT_IN_1_PAD 23 #endif +#if (SCT_IN1_LOC == 5) +#define RTE_SCT_IN_1_PIN (SCT_IN1_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_1_MUX 9 +#define RTE_SCT_IN_1_PAD 27 +#endif //Pintool data #endif @@ -2971,17 +3047,12 @@ #else //Pintool data #define RTE_SCT_IN_2_PORT SCT_IN2_PORT -#if (SCT_IN2_LOC == 0) +#if (SCT_IN2_LOC == 6) #define RTE_SCT_IN_2_PIN SCT_IN2_PIN #define RTE_SCT_IN_2_MUX 9 #define RTE_SCT_IN_2_PAD 0 //no pad #endif -#if (SCT_IN2_LOC == 1) -#define RTE_SCT_IN_2_PIN (SCT_IN2_PIN + GPIO_MAX_PIN) -#define RTE_SCT_IN_2_MUX 7 -#define RTE_SCT_IN_2_PAD 24 -#endif -#if (SCT_IN2_LOC == 2) +#if (SCT_IN2_LOC == 7) #define RTE_SCT_IN_2_PIN (SCT_IN2_PIN + GPIO_MAX_PIN) #define RTE_SCT_IN_2_MUX 9 #define RTE_SCT_IN_2_PAD 28 @@ -3018,17 +3089,12 @@ #else //Pintool data #define RTE_SCT_IN_3_PORT SCT_IN3_PORT -#if (SCT_IN3_LOC == 0) +#if (SCT_IN3_LOC == 8) #define RTE_SCT_IN_3_PIN SCT_IN3_PIN #define RTE_SCT_IN_3_MUX 9 #define RTE_SCT_IN_3_PAD 0 //no pad #endif -#if (SCT_IN3_LOC == 1) -#define RTE_SCT_IN_3_PIN (SCT_IN3_PIN + GPIO_MAX_PIN) -#define RTE_SCT_IN_3_MUX 7 -#define RTE_SCT_IN_3_PAD 25 -#endif -#if (SCT_IN3_LOC == 2) +#if (SCT_IN3_LOC == 9) #define RTE_SCT_IN_3_PIN (SCT_IN3_PIN + GPIO_MAX_PIN) #define RTE_SCT_IN_3_MUX 9 #define RTE_SCT_IN_3_PAD 29 @@ -3042,17 +3108,25 @@ #if (RTE_SCT_OUT_0_PORT_ID == 0) #define RTE_SCT_OUT_0_PORT 0 #define RTE_SCT_OUT_0_PIN 29 +#define RTE_SCT_OUT_0_MUX 9 +#define RTE_SCT_OUT_0_PAD 0 //no pad #else #error "Invalid RTE_SCT_OUT_0_PIN Pin Configuration!" #endif #else //Pintool data #define RTE_SCT_OUT_0_PORT SCT_OUT0_PORT -#define RTE_SCT_OUT_0_PIN SCT_OUT0_PIN -//Pintool data -#endif +#if (SCT_OUT0_LOC == 10) +#define RTE_SCT_OUT_0_PIN SCT_OUT0_PIN #define RTE_SCT_OUT_0_MUX 9 #define RTE_SCT_OUT_0_PAD 0 //no pad +#elif (SCT_OUT0_LOC == 11) +#define RTE_SCT_OUT_0_PIN (SCT_OUT0_PIN + GPIO_MAX_PIN) +#define RTE_SCT_OUT_0_MUX 7 +#define RTE_SCT_OUT_0_PAD 26 +#endif +//Pintool data +#endif // SCT_OUT_1 <0=>GPIO_30 <1=>GPIO_69 #ifndef SCT_OUT1_LOC @@ -3060,17 +3134,67 @@ #if (RTE_SCT_OUT_1_PORT_ID == 0) #define RTE_SCT_OUT_1_PORT 0 #define RTE_SCT_OUT_1_PIN 30 +#define RTE_SCT_OUT_1_MUX 9 +#define RTE_SCT_OUT_1_PAD 0 //no pad #else #error "Invalid RTE_SCT_OUT_1_PIN Pin Configuration!" #endif #else //Pintool data #define RTE_SCT_OUT_1_PORT SCT_OUT1_PORT -#define RTE_SCT_OUT_1_PIN SCT_OUT1_PIN -//Pintool data -#endif +#if (SCT_OUT1_LOC == 12) +#define RTE_SCT_OUT_1_PIN SCT_OUT1_PIN #define RTE_SCT_OUT_1_MUX 9 #define RTE_SCT_OUT_1_PAD 0 //no pad +#elif (SCT_OUT1_LOC == 13) +#define RTE_SCT_OUT_1_PIN (SCT_OUT1_PIN + GPIO_MAX_PIN) +#define RTE_SCT_OUT_1_MUX 7 +#define RTE_SCT_OUT_1_PAD 27 +#endif +//Pintool data +#endif + +//Pintool data +#define RTE_SCT_OUT_2_PORT SCT_OUT2_PORT +#define RTE_SCT_OUT_2_PIN SCT_OUT2_PIN +#define RTE_SCT_OUT_2_MUX 7 +#define RTE_SCT_OUT_2_PAD 28 +//Pintool data + +//Pintool data +#define RTE_SCT_OUT_3_PORT SCT_OUT3_PORT +#define RTE_SCT_OUT_3_PIN SCT_OUT3_PIN +#define RTE_SCT_OUT_3_MUX 7 +#define RTE_SCT_OUT_3_PAD 29 +//Pintool data + +//Pintool data +#define RTE_SCT_OUT_4_PORT SCT_OUT4_PORT +#define RTE_SCT_OUT_4_PIN SCT_OUT4_PIN +#define RTE_SCT_OUT_4_MUX 7 +#define RTE_SCT_OUT_4_PAD 30 +//Pintool data + +//Pintool data +#define RTE_SCT_OUT_5_PORT SCT_OUT5_PORT +#define RTE_SCT_OUT_5_PIN SCT_OUT5_PIN +#define RTE_SCT_OUT_5_MUX 7 +#define RTE_SCT_OUT_5_PAD 31 +//Pintool data + +//Pintool data +#define RTE_SCT_OUT_6_PORT SCT_OUT6_PORT +#define RTE_SCT_OUT_6_PIN SCT_OUT6_PIN +#define RTE_SCT_OUT_6_MUX 7 +#define RTE_SCT_OUT_6_PAD 32 +//Pintool data + +//Pintool data +#define RTE_SCT_OUT_7_PORT SCT_OUT7_PORT +#define RTE_SCT_OUT_7_PIN SCT_OUT7_PIN +#define RTE_SCT_OUT_7_MUX 7 +#define RTE_SCT_OUT_7_PAD 33 +//Pintool data // SIO // //<> Serial Input Output @@ -3110,6 +3234,10 @@ #endif #if (SIO_0_LOC == 2) #define RTE_SIO_0_PIN (SIO_SIO0_PIN + GPIO_MAX_PIN) +#define RTE_SIO_0_PAD 22 +#endif +#if (SIO_0_LOC == 3) +#define RTE_SIO_0_PIN (SIO_SIO0_PIN + GPIO_MAX_PIN) #define RTE_SIO_0_PAD 30 #endif //Pintool data @@ -3150,19 +3278,19 @@ //Pintool data #define RTE_SIO_1_PORT SIO_SIO1_PORT #define RTE_SIO_1_MUX 1 -#if (SIO_1_LOC == 0) +#if (SIO_1_LOC == 4) #define RTE_SIO_1_PIN SIO_SIO1_PIN #define RTE_SIO_1_PAD 2 #endif -#if (SIO_1_LOC == 1) +#if (SIO_1_LOC == 5) #define RTE_SIO_1_PIN SIO_SIO1_PIN #define RTE_SIO_1_PAD 0 #endif -#if (SIO_1_LOC == 2) +#if (SIO_1_LOC == 6) #define RTE_SIO_1_PIN (SIO_SIO1_PIN + GPIO_MAX_PIN) #define RTE_SIO_1_PAD 23 #endif -#if (SIO_1_LOC == 3) +#if (SIO_1_LOC == 7) #define RTE_SIO_1_PIN (SIO_SIO1_PIN + GPIO_MAX_PIN) #define RTE_SIO_1_PAD 31 #endif @@ -3200,19 +3328,15 @@ //Pintool data #define RTE_SIO_2_PORT SIO_SIO2_PORT #define RTE_SIO_2_MUX 1 -#if (SIO_2_LOC == 0) +#if (SIO_2_LOC == 8) #define RTE_SIO_2_PIN SIO_SIO2_PIN #define RTE_SIO_2_PAD 3 #endif -#if (SIO_2_LOC == 1) +#if (SIO_2_LOC == 9) #define RTE_SIO_2_PIN SIO_SIO2_PIN #define RTE_SIO_2_PAD 0 #endif -#if (SIO_2_LOC == 2) -#define RTE_SIO_2_PIN (SIO_SIO2_PIN + GPIO_MAX_PIN) -#define RTE_SIO_2_PAD 24 -#endif -#if (SIO_2_LOC == 3) +#if (SIO_2_LOC == 10) #define RTE_SIO_2_PIN (SIO_SIO2_PIN + GPIO_MAX_PIN) #define RTE_SIO_2_PAD 32 #endif @@ -3250,19 +3374,15 @@ //Pintool data #define RTE_SIO_3_PORT SIO_SIO3_PORT #define RTE_SIO_3_MUX 1 -#if (SIO_3_LOC == 0) +#if (SIO_3_LOC == 11) #define RTE_SIO_3_PIN SIO_SIO3_PIN #define RTE_SIO_3_PAD 4 #endif -#if (SIO_3_LOC == 1) +#if (SIO_3_LOC == 12) #define RTE_SIO_3_PIN SIO_SIO3_PIN #define RTE_SIO_3_PAD 0 #endif -#if (SIO_3_LOC == 2) -#define RTE_SIO_3_PIN (SIO_SIO3_PIN + GPIO_MAX_PIN) -#define RTE_SIO_3_PAD 25 -#endif -#if (SIO_3_LOC == 3) +#if (SIO_3_LOC == 13) #define RTE_SIO_3_PIN (SIO_SIO3_PIN + GPIO_MAX_PIN) #define RTE_SIO_3_PAD 33 #endif @@ -3292,13 +3412,18 @@ #else //Pintool data #define RTE_SIO_4_PORT SIO_SIO4_PORT -#define RTE_SIO_4_PIN SIO_SIO4_PIN #define RTE_SIO_4_MUX 1 -#if (SIO_4_LOC == 0) +#if (SIO_4_LOC == 14) #define RTE_SIO_4_PAD 5 +#define RTE_SIO_4_PIN SIO_SIO4_PIN #endif -#if (SIO_4_LOC == 1) +#if (SIO_4_LOC == 15) #define RTE_SIO_4_PAD 0 +#define RTE_SIO_4_PIN SIO_SIO4_PIN +#endif +#if (SIO_4_LOC == 16) +#define RTE_SIO_4_PAD 26 +#define RTE_SIO_4_PIN (SIO_SIO4_PIN + GPIO_MAX_PIN) #endif //Pintool data #endif @@ -3322,13 +3447,18 @@ #else //Pintool data #define RTE_SIO_5_PORT SIO_SIO5_PORT -#define RTE_SIO_5_PIN SIO_SIO5_PIN #define RTE_SIO_5_MUX 1 -#if (SIO_5_LOC == 0) +#if (SIO_5_LOC == 17) #define RTE_SIO_5_PAD 6 +#define RTE_SIO_5_PIN SIO_SIO5_PIN #endif -#if (SIO_5_LOC == 1) +#if (SIO_5_LOC == 18) #define RTE_SIO_5_PAD 0 +#define RTE_SIO_5_PIN SIO_SIO5_PIN +#endif +#if (SIO_5_LOC == 19) +#define RTE_SIO_5_PAD 0 +#define RTE_SIO_5_PIN (SIO_SIO5_PIN + GPIO_MAX_PIN) #endif //Pintool data #endif @@ -3369,11 +3499,11 @@ //Pintool data #define RTE_SIO_7_PORT SIO_SIO7_PORT #define RTE_SIO_7_MUX 1 -#if (SIO_7_LOC == 0) +#if (SIO_7_LOC == 21) #define RTE_SIO_7_PIN SIO_SIO7_PIN #define RTE_SIO_7_PAD 8 #endif -#if (SIO_7_LOC == 1) +#if (SIO_7_LOC == 22) #define RTE_SIO_7_PIN (SIO_SIO7_PIN + GPIO_MAX_PIN) #define RTE_SIO_7_PAD 29 #endif @@ -3382,7 +3512,7 @@ //<> Pulse Width Modulation //PWM_1H <0=>GPIO_7 <1=>GPIO_64 <2=>GPIO_65 -#ifndef PWM_H1_LOC +#ifndef PWM_1H_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_PWM_1H_PORT_ID 0 #else @@ -3404,14 +3534,14 @@ #endif #else //Pintool data -#define RTE_PWM_1H_PORT PWM_H1_PORT -#if (PWM_H1_LOC == 0) -#define RTE_PWM_1H_PIN PWM_H1_PIN +#define RTE_PWM_1H_PORT PWM_1H_PORT +#if (PWM_1H_LOC == 0) +#define RTE_PWM_1H_PIN PWM_1H_PIN #define RTE_PWM_1H_MUX 10 #define RTE_PWM_1H_PAD 2 #endif -#if (PWM_H1_LOC == 1) -#define RTE_PWM_1H_PIN (PWM_H1_PIN + GPIO_MAX_PIN) +#if (PWM_1H_LOC == 1) +#define RTE_PWM_1H_PIN (PWM_1H_PIN + GPIO_MAX_PIN) #define RTE_PWM_1H_MUX 8 #define RTE_PWM_1H_PAD 22 #endif @@ -3419,7 +3549,7 @@ #endif // PWM_1L <0=>GPIO_6 <1=>GPIO_64 <2=>GPIO_64 -#ifndef PWM_L1_LOC +#ifndef PWM_1L_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_PWM_1L_PORT_ID 0 #else @@ -3429,20 +3559,28 @@ #if (RTE_PWM_1L_PORT_ID == 0) #define RTE_PWM_1L_PORT 0 #define RTE_PWM_1L_PIN 6 +#define RTE_PWM_1L_MUX 10 +#define RTE_PWM_1L_PAD 1 #else #error "Invalid RTE_PWM_1L_PIN Pin Configuration!" #endif #else //Pintool data -#define RTE_PWM_1L_PORT PWM_L1_PORT -#define RTE_PWM_1L_PIN PWM_L1_PIN -//Pintool data -#endif +#define RTE_PWM_1L_PORT PWM_1L_PORT +#if (PWM_1L_LOC == 2) +#define RTE_PWM_1L_PIN PWM_1L_PIN #define RTE_PWM_1L_MUX 10 #define RTE_PWM_1L_PAD 1 +#elif (PWM_1L_LOC == 3) +#define RTE_PWM_1L_PIN (PWM_1L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_1L_MUX 8 +#define RTE_PWM_1L_PAD 22 +#endif +//Pintool data +#endif //PWM_2H <0=>GPIO_9 <1=>GPIO_67 <2=>GPIO_69 -#ifndef PWM_H2_LOC +#ifndef PWM_2H_LOC #define RTE_PWM_2H_PORT_ID 0 #if ((RTE_PWM_2H_PORT_ID == 2)) #error "Invalid RTE_PWM_2H_PIN pin Configuration!" @@ -3463,22 +3601,22 @@ #endif #else //Pintool data -#define RTE_PWM_2H_PORT PWM_H2_PORT -#if (PWM_H2_LOC == 0) -#define RTE_PWM_2H_PIN PWM_H2_PIN +#define RTE_PWM_2H_PORT PWM_2H_PORT +#if (PWM_2H_LOC == 4) +#define RTE_PWM_2H_PIN PWM_2H_PIN #define RTE_PWM_2H_MUX 10 #define RTE_PWM_2H_PAD 4 #endif -#if (PWM_H2_LOC == 1) -#define RTE_PWM_2H_PIN (PWM_H2_PIN + GPIO_MAX_PIN) -#define RTE_PWM_2H_MUX 8 -#define RTE_PWM_2H_PAD 25 +#if (PWM_2H_LOC == 5) +#define RTE_PWM_2H_PIN (PWM_2H_PIN + GPIO_MAX_PIN) +#define RTE_PWM_2H_MUX 12 +#define RTE_PWM_2H_PAD 27 #endif //Pintool data #endif // PWM_2L <0=>GPIO_8 <1=>GPIO_66 <2=>GPIO_68 -#ifndef PWM_L2_LOC +#ifndef PWM_2L_LOC #define RTE_PWM_2L_PORT_ID 0 #if ((RTE_PWM_2L_PORT_ID == 2)) #error "Invalid RTE_PWM_2L_PIN pin Configuration!" @@ -3499,59 +3637,80 @@ #endif #else //Pintool data -#define RTE_PWM_2L_PORT PWM_L2_PORT -#if (PWM_L2_LOC == 0) -#define RTE_PWM_2L_PIN PWM_L2_PIN +#define RTE_PWM_2L_PORT PWM_2L_PORT +#if (PWM_2L_LOC == 6) +#define RTE_PWM_2L_PIN PWM_2L_PIN #define RTE_PWM_2L_MUX 10 #define RTE_PWM_2L_PAD 3 #endif -#if (PWM_L2_LOC == 1) -#define RTE_PWM_2L_PIN (PWM_L2_PIN + GPIO_MAX_PIN) +#if (PWM_2L_LOC == 7) +#define RTE_PWM_2L_PIN (PWM_2L_PIN + GPIO_MAX_PIN) #define RTE_PWM_2L_MUX 8 #define RTE_PWM_2L_PAD 24 #endif +#if (PWM_2L_LOC == 8) +#define RTE_PWM_2L_PIN (PWM_2L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_2L_MUX 12 +#define RTE_PWM_2L_PAD 26 +#endif //Pintool data #endif // PWM_3H <0=>GPIO_11 <1=>GPIO_69 -#ifndef PWM_H3_LOC +#ifndef PWM_3H_LOC #define RTE_PWM_3H_PORT_ID 0 #if (RTE_PWM_3H_PORT_ID == 0) #define RTE_PWM_3H_PORT 0 #define RTE_PWM_3H_PIN 11 +#define RTE_PWM_3H_MUX 10 +#define RTE_PWM_3H_PAD 6 #else #error "Invalid RTE_PWM_3H_PIN Pin Configuration!" #endif #else //Pintool data -#define RTE_PWM_3H_PORT PWM_H3_PORT -#define RTE_PWM_3H_PIN PWM_H3_PIN -//Pintool data -#endif +#define RTE_PWM_3H_PORT PWM_3H_PORT +#if (PWM_3H_LOC == 9) +#define RTE_PWM_3H_PIN PWM_3H_PIN #define RTE_PWM_3H_MUX 10 #define RTE_PWM_3H_PAD 6 +#elif (PWM_3H_LOC == 10) +#define RTE_PWM_3H_PIN (PWM_3H_PIN + GPIO_MAX_PIN) +#define RTE_PWM_3H_MUX 8 +#define RTE_PWM_3H_PAD 27 +#endif +//Pintool data +#endif // PWM_3L <0=>GPIO_10 <1=>GPIO_68 -#ifndef PWM_L3_LOC +#ifndef PWM_3L_LOC #define RTE_PWM_3L_PORT_ID 0 #if (RTE_PWM_3L_PORT_ID == 0) #define RTE_PWM_3L_PORT 0 #define RTE_PWM_3L_PIN 10 +#define RTE_PWM_3L_MUX 10 +#define RTE_PWM_3L_PAD 5 #else #error "Invalid RTE_PWM_3L_PIN Pin Configuration!" #endif #else //Pintool data -#define RTE_PWM_3L_PORT PWM_L3_PORT -#define RTE_PWM_3L_PIN PWM_L3_PIN -//Pintool data -#endif +#define RTE_PWM_3L_PORT PWM_3L_PORT +#if (PWM_3L_LOC == 11) +#define RTE_PWM_3L_PIN PWM_3L_PIN #define RTE_PWM_3L_MUX 10 #define RTE_PWM_3L_PAD 5 +#elif (PWM_3L_LOC == 12) +#define RTE_PWM_3L_PIN (PWM_3L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_3L_MUX 8 +#define RTE_PWM_3L_PAD 26 +#endif +//Pintool data +#endif // PWM_4H <0=>GPIO_15 <1=>GPIO_71 -#ifndef PWM_H4_LOC +#ifndef PWM_4H_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_PWM_4H_PORT_ID 1 #else @@ -3573,22 +3732,15 @@ #endif #else //Pintool data -#define RTE_PWM_4H_PORT PWM_H4_PORT -#if (PWM_H4_LOC == 0) -#define RTE_PWM_4H_PIN PWM_H4_PIN -#define RTE_PWM_4H_MUX 10 -#define RTE_PWM_4H_PAD 8 -#endif -#if (PWM_H4_LOC == 1) -#define RTE_PWM_4H_PIN (PWM_H4_PIN + GPIO_MAX_PIN) -#define RTE_PWM_4H_MUX 8 -#define RTE_PWM_4H_PAD 29 -#endif +#define RTE_PWM_4H_PORT PWM_4H_PORT +#define RTE_PWM_4H_PIN (PWM_4H_PIN + GPIO_MAX_PIN) +#define RTE_PWM_4H_MUX 8 +#define RTE_PWM_4H_PAD 29 //Pintool data #endif // PWM_4H <0=>GPIO_12 <1=>GPIO_70 -#ifndef PWM_L4_LOC +#ifndef PWM_4L_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_PWM_4L_PORT_ID 1 #else @@ -3610,14 +3762,14 @@ #endif #else //Pintool data -#define RTE_PWM_4L_PORT PWM_L4_PORT -#if (PWM_L4_LOC == 0) -#define RTE_PWM_4L_PIN PWM_L4_PIN +#define RTE_PWM_4L_PORT PWM_4L_PORT +#if (PWM_4L_LOC == 14) +#define RTE_PWM_4L_PIN PWM_4L_PIN #define RTE_PWM_4L_MUX 10 #define RTE_PWM_4L_PAD 7 #endif -#if (PWM_L4_LOC == 1) -#define RTE_PWM_4L_PIN (PWM_L4_PIN + GPIO_MAX_PIN) +#if (PWM_4L_LOC == 15) +#define RTE_PWM_4L_PIN (PWM_4L_PIN + GPIO_MAX_PIN) #define RTE_PWM_4L_MUX 8 #define RTE_PWM_4L_PAD 28 #endif @@ -3644,12 +3796,17 @@ #else //Pintool data #define RTE_PWM_FAULTA_PORT PWM_FAULTA_PORT -#if (PWM_FAULTA_LOC == 0) +#if (PWM_FAULTA_LOC == 16) #define RTE_PWM_FAULTA_PIN PWM_FAULTA_PIN #define RTE_PWM_FAULTA_MUX 10 #define RTE_PWM_FAULTA_PAD 0 //no pad #endif -#if (PWM_FAULTA_LOC == 2) +#if (PWM_FAULTA_LOC == 17) +#define RTE_PWM_FAULTA_PIN (PWM_FAULTA_PIN + GPIO_MAX_PIN) +#define RTE_PWM_FAULTA_MUX 10 +#define RTE_PWM_FAULTA_PAD 26 +#endif +#if (PWM_FAULTA_LOC == 18) #define RTE_PWM_FAULTA_PIN (PWM_FAULTA_PIN + GPIO_MAX_PIN) #define RTE_PWM_FAULTA_MUX 8 #define RTE_PWM_FAULTA_PAD 31 @@ -3677,12 +3834,17 @@ #else //Pintool data #define RTE_PWM_FAULTB_PORT PWM_FAULTB_PORT -#if (PWM_FAULTB_LOC == 0) +#if (PWM_FAULTB_LOC == 19) #define RTE_PWM_FAULTB_PIN PWM_FAULTB_PIN #define RTE_PWM_FAULTB_MUX 10 #define RTE_PWM_FAULTB_PAD 0 //no pad #endif -#if (PWM_FAULTB_LOC == 2) +#if (PWM_FAULTB_LOC == 20) +#define RTE_PWM_FAULTB_PIN (PWM_FAULTB_PIN + GPIO_MAX_PIN) +#define RTE_PWM_FAULTB_MUX 10 +#define RTE_PWM_FAULTB_PAD 27 +#endif +#if (PWM_FAULTB_LOC == 21) #define RTE_PWM_FAULTB_PIN (PWM_FAULTB_PIN + GPIO_MAX_PIN) #define RTE_PWM_FAULTB_MUX 8 #define RTE_PWM_FAULTB_PAD 32 @@ -3691,13 +3853,13 @@ #endif //PWM_SLP_EVENT_TRIG GPIO_72 -#ifndef PWM_SLEEPTRIG_LOC +#ifndef PWM_EVTTRIG_LOC #define RTE_PWM_SLP_EVENT_TRIG_PORT 0 #define RTE_PWM_SLP_EVENT_TRIG_PIN 72 #else //Pintool data -#define RTE_PWM_SLP_EVENT_TRIG_PORT PWM_SLEEP_EVENT_TRIG_PORT -#define RTE_PWM_SLP_EVENT_TRIG_PIN (PWM_SLEEP_EVENT_TRIG_PIN + GPIO_MAX_PIN) +#define RTE_PWM_SLP_EVENT_TRIG_PORT PWM_SLEEP_EVT_TRIG_PORT +#define RTE_PWM_SLP_EVENT_TRIG_PIN (PWM_SLEEP_EVT_TRIG_PIN + GPIO_MAX_PIN) //Pintool data #endif #define RTE_PWM_SLP_EVENT_TRIG_MUX 8 @@ -3733,22 +3895,22 @@ #else //Pintool data #define RTE_PWM_TMR_EXT_TRIG_1_PORT PWM_TMR_EXT_TRIG_1_PORT -#if (PWM_EXTTRIG1_LOC == 0) +#if (PWM_EXTTRIG1_LOC == 22) #define RTE_PWM_TMR_EXT_TRIG_1_PIN PWM_TMR_EXT_TRIG_1_PIN #define RTE_PWM_TMR_EXT_TRIG_1_MUX 10 #define RTE_PWM_TMR_EXT_TRIG_1_PAD 0 //no pad #endif -#if (PWM_EXTTRIG1_LOC == 1) +#if (PWM_EXTTRIG1_LOC == 23) #define RTE_PWM_TMR_EXT_TRIG_1_PIN PWM_TMR_EXT_TRIG_1_PIN #define RTE_PWM_TMR_EXT_TRIG_1_MUX 8 #define RTE_PWM_TMR_EXT_TRIG_1_PAD 15 #endif -#if (PWM_EXTTRIG1_LOC == 2) +#if (PWM_EXTTRIG1_LOC == 24) #define RTE_PWM_TMR_EXT_TRIG_1_PIN (PWM_TMR_EXT_TRIG_1_PIN + GPIO_MAX_PIN) #define RTE_PWM_TMR_EXT_TRIG_1_MUX 10 #define RTE_PWM_TMR_EXT_TRIG_1_PAD 28 #endif -#if (PWM_EXTTRIG1_LOC == 3) +#if (PWM_EXTTRIG1_LOC == 25) #define RTE_PWM_TMR_EXT_TRIG_1_PIN (PWM_TMR_EXT_TRIG_1_PIN + GPIO_MAX_PIN) #define RTE_PWM_TMR_EXT_TRIG_1_MUX 8 #define RTE_PWM_TMR_EXT_TRIG_1_PAD 33 @@ -3781,17 +3943,22 @@ #else //Pintool data #define RTE_PWM_TMR_EXT_TRIG_2_PORT PWM_TMR_EXT_TRIG_2_PORT -#if (PWM_EXTTRIG2_LOC == 0) +#if (PWM_EXTTRIG2_LOC == 26) #define RTE_PWM_TMR_EXT_TRIG_2_PIN PWM_TMR_EXT_TRIG_2_PIN #define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 #define RTE_PWM_TMR_EXT_TRIG_2_PAD 0 //no pad #endif -#if (PWM_EXTTRIG2_LOC == 1) +#if (PWM_EXTTRIG2_LOC == 27) #define RTE_PWM_TMR_EXT_TRIG_2_PIN PWM_TMR_EXT_TRIG_2_PIN #define RTE_PWM_TMR_EXT_TRIG_2_MUX 8 #define RTE_PWM_TMR_EXT_TRIG_2_PAD 18 #endif -#if (PWM_EXTTRIG2_LOC == 2) +#if (PWM_EXTTRIG2_LOC == 28) //Combination not available in pin mux +#define RTE_PWM_TMR_EXT_TRIG_2_PIN (PWM_TMR_EXT_TRIG_2_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 29 +#endif +#if (PWM_EXTTRIG2_LOC == 29) #define RTE_PWM_TMR_EXT_TRIG_2_PIN (PWM_TMR_EXT_TRIG_2_PIN + GPIO_MAX_PIN) #define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 #define RTE_PWM_TMR_EXT_TRIG_2_PAD 29 @@ -3799,6 +3966,46 @@ //Pintool data #endif +//PWM_TMR_EXT_TRIG_3 +//Pintool data +#define RTE_PWM_TMR_EXT_TRIG_3_PORT PWM_TMR_EXT_TRIG_3_PORT +#if (PWM_EXTTRIG3_LOC == 30) +#define RTE_PWM_TMR_EXT_TRIG_3_PIN PWM_TMR_EXT_TRIG_3_PIN +#define RTE_PWM_TMR_EXT_TRIG_3_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_3_PAD 0 //no pad +#endif +#if (PWM_EXTTRIG3_LOC == 31) +#define RTE_PWM_TMR_EXT_TRIG_3_PIN PWM_TMR_EXT_TRIG_3_PIN +#define RTE_PWM_TMR_EXT_TRIG_3_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_3_PAD 19 +#endif +#if (PWM_EXTTRIG3_LOC == 32) +#define RTE_PWM_TMR_EXT_TRIG_3_PIN (PWM_TMR_EXT_TRIG_3_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_3_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_3_PAD 30 +#endif +//Pintool data + +//PWM_TMR_EXT_TRIG_4 +//Pintool data +#define RTE_PWM_TMR_EXT_TRIG_4_PORT PWM_TMR_EXT_TRIG_4_PORT +#if (PWM_EXTTRIG4_LOC == 33) +#define RTE_PWM_TMR_EXT_TRIG_4_PIN PWM_TMR_EXT_TRIG_4_PIN +#define RTE_PWM_TMR_EXT_TRIG_4_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_4_PAD 0 //no pad +#endif +#if (PWM_EXTTRIG4_LOC == 34) +#define RTE_PWM_TMR_EXT_TRIG_4_PIN PWM_TMR_EXT_TRIG_4_PIN +#define RTE_PWM_TMR_EXT_TRIG_4_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_4_PAD 14 +#endif +#if (PWM_EXTTRIG4_LOC == 35) +#define RTE_PWM_TMR_EXT_TRIG_4_PIN (PWM_TMR_EXT_TRIG_4_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_4_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_4_PAD 31 +#endif +//Pintool data + //<> QEI (Quadrature Encode Interface) //QEI_DIR <0=>GPIO_28 <1=>GPIO_49 <2=>GPIO_57 <3=>GPIO_67 <4=>GPIO_71 <5=>GPIO_73 <6=>GPIO_11 <7=>GPIO_34 @@ -4672,9 +4879,21 @@ #define RTE_UULP_GPIO_4_PORT 5 #define RTE_UULP_GPIO_4_PIN 4 - #define RTE_UULP_GPIO_4_MODE 0 +#define RTE_UULP_GPIO_5_PIN 5 +#define RTE_UULP_GPIO_5_MODE 0 + // UULP GPIO as enable pin for sensors #define SENSOR_ENABLE_GPIO_MAPPED_TO_UULP -#define SENSOR_ENABLE_GPIO_PIN RTE_UULP_GPIO_1_PIN \ No newline at end of file +#define SENSOR_ENABLE_GPIO_PIN RTE_UULP_GPIO_1_PIN + +// Memlcd GPIOs +#define RTE_MEMLCD_CS_PIN 10 // Memlcd SPI CS pin +#define RTE_MEMLCD_CS_PORT 0 // Memlcd SPI CS port + +#define RTE_MEMLCD_EXTCOMIN_PIN 3 // Memlcd external communication pin +#define RTE_MEMLCD_EXTCOMIN_PORT 0 // Memlcd external communication port + +#define RTE_MEMLCD_ENABLE_DISPLAY_PIN 0 // Memlcd display enable pin +#define RTE_MEMLCD_ENABLE_DISPLAY_PORT 0 // Memlcd display enable port diff --git a/components/board/silabs/config/brd4340a/pin_config.h b/components/board/silabs/config/brd4340a/pin_config.h index fcbb183c6..2bbc8c59c 100644 --- a/components/board/silabs/config/brd4340a/pin_config.h +++ b/components/board/silabs/config/brd4340a/pin_config.h @@ -16,8 +16,8 @@ // $[I2C1] // [I2C1]$ -// $[I2C2] -// [I2C2]$ +// $[ULP_I2C] +// [ULP_I2C]$ // $[SSI_MASTER] // [SSI_MASTER]$ @@ -25,8 +25,8 @@ // $[SSI_SLAVE] // [SSI_SLAVE]$ -// $[SSI_ULP_MASTER] -// [SSI_ULP_MASTER]$ +// $[ULP_SPI] +// [ULP_SPI]$ // $[GSPI_MASTER] // [GSPI_MASTER]$ @@ -34,8 +34,8 @@ // $[I2S0] // [I2S0]$ -// $[I2S1] -// [I2S1]$ +// $[ULP_I2S] +// [ULP_I2S]$ // $[SCT] // [SCT]$ @@ -46,8 +46,74 @@ // $[PWM] // [PWM]$ -// $[ADC] -// [ADC]$ +// $[PWM_CH0] +// [PWM_CH0]$ + +// $[PWM_CH1] +// [PWM_CH1]$ + +// $[PWM_CH2] +// [PWM_CH2]$ + +// $[PWM_CH3] +// [PWM_CH3]$ + +// $[ADC_CH1] +// [ADC_CH1]$ + +// $[ADC_CH2] +// [ADC_CH2]$ + +// $[ADC_CH3] +// [ADC_CH3]$ + +// $[ADC_CH4] +// [ADC_CH4]$ + +// $[ADC_CH5] +// [ADC_CH5]$ + +// $[ADC_CH6] +// [ADC_CH6]$ + +// $[ADC_CH7] +// [ADC_CH7]$ + +// $[ADC_CH8] +// [ADC_CH8]$ + +// $[ADC_CH9] +// [ADC_CH9]$ + +// $[ADC_CH10] +// [ADC_CH10]$ + +// $[ADC_CH11] +// [ADC_CH11]$ + +// $[ADC_CH12] +// [ADC_CH12]$ + +// $[ADC_CH13] +// [ADC_CH13]$ + +// $[ADC_CH14] +// [ADC_CH14]$ + +// $[ADC_CH15] +// [ADC_CH15]$ + +// $[ADC_CH16] +// [ADC_CH16]$ + +// $[ADC_CH17] +// [ADC_CH17]$ + +// $[ADC_CH18] +// [ADC_CH18]$ + +// $[ADC_CH19] +// [ADC_CH19]$ // $[COMP1] // [COMP1]$ diff --git a/components/board/silabs/config/brd4340b/RTE_Device_917.h b/components/board/silabs/config/brd4340b/RTE_Device_917.h index 5f36558ad..b3602f10f 100644 --- a/components/board/silabs/config/brd4340b/RTE_Device_917.h +++ b/components/board/silabs/config/brd4340b/RTE_Device_917.h @@ -17,7 +17,7 @@ * * 3. This notice may not be removed or altered from any source distribution. * - * $Date: 1. December 2016 + * $Date: 1. June 2024 * $Revision: V2.4.4 * * Project: RTE Device Configuration for Si91x 2.0 B0 BRD4340B @@ -28,6 +28,7 @@ #ifndef __RTE_DEVICE_H #define __RTE_DEVICE_H #include "rsi_ccp_user_config.h" +#include "pin_config.h" #define GPIO_PORT_0 0 // GPIO port 0 #define ULP_GPIO_MODE_6 6 // ULP GPIO mode 6 @@ -46,7 +47,7 @@ #define RTE_BUTTON1_PIN (11U) #define RTE_BUTTON1_PAD 6 -#define RTE_LED0_PORT 0 +#define RTE_LED0_PORT 4 #define RTE_LED0_NUMBER 0 #define RTE_LED0_PIN (2U) @@ -62,7 +63,7 @@ #define RTE_USART0 1 -#define RTE_USART0_CLK_SRC USART_INTFPLLCLK +#define RTE_USART0_CLK_SRC USART_ULPREFCLK #define RTE_USART0_CLK_DIV_FACT 1 #define RTE_USART0_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER @@ -86,6 +87,7 @@ // USART0_CLK <0=>P0_8 <1=>P0_25 <2=>P0_52 <3=>P0_64 // CLK of USART0 +#ifndef USART0_CLK_LOC #define RTE_USART0_CLK_PORT_ID 0 #if (RTE_USART0_CLK_PORT_ID == 0) @@ -106,10 +108,35 @@ #else #error "Invalid USART0 RTE_USART0_CLK_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_CLK_PORT USART0_CLK_PORT +#if (USART0_CLK_LOC == 0) +#define RTE_USART0_CLK_PIN USART0_CLK_PIN +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 3 +#endif +#if (USART0_CLK_LOC == 1) +#define RTE_USART0_CLK_PIN USART0_CLK_PIN +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 0 //NO PAD +#endif +#if (USART0_CLK_LOC == 2) +#define RTE_USART0_CLK_PIN USART0_CLK_PIN +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 16 +#endif +#if (USART0_CLK_LOC == 3) +#define RTE_USART0_CLK_PIN (USART0_CLK_PIN + GPIO_MAX_PIN) +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 22 +#endif +//Pintool data +#endif // USART0_TX <0=>P0_15 <1=>P0_30 <2=>P0_54 <3=>P0_68 <4=>P0_71 // TX for USART0 - +#ifndef USART0_TX_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_USART0_TX_PORT_ID 1 #else @@ -139,10 +166,40 @@ #else #error "Invalid USART0 RTE_USART0_TX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_TX_PORT USART0_TX_PORT +#if (USART0_TX_LOC == 4) +#define RTE_USART0_TX_PIN USART0_TX_PIN +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 8 +#endif +#if (USART0_TX_LOC == 5) +#define RTE_USART0_TX_PIN USART0_TX_PIN +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 0 //NO PAD +#endif +#if (USART0_TX_LOC == 6) +#define RTE_USART0_TX_PIN USART0_TX_PIN +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 18 +#endif +#if (USART0_TX_LOC == 7) +#define RTE_USART0_TX_PIN (USART0_TX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 26 +#endif +#if (USART0_TX_LOC == 8) +#define RTE_USART0_TX_PIN (USART0_TX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_TX_MUX 4 +#define RTE_USART0_TX_PAD 29 +#endif +//Pintool data +#endif // USART0_RX <0=>P0_10 <1=>P0_29 <2=>P0_55 <3=>P0_65 <4=>P0_70 // RX for USART0 - +#ifndef USART0_RX_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_USART0_RX_PORT_ID 1 #else @@ -168,7 +225,7 @@ #define RTE_USART0_RX_PORT 0 #define RTE_USART0_RX_PIN 65 #define RTE_USART0_RX_MUX 2 -#define RTE_USART0_RX_PAD 24 +#define RTE_USART0_RX_PAD 23 #elif (RTE_USART0_RX_PORT_ID == 4) #define RTE_USART0_RX_PORT 0 #define RTE_USART0_RX_PIN 70 @@ -177,9 +234,40 @@ #else #error "Invalid USART0 RTE_USART0_RX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_RX_PORT USART0_RX_PORT +#if (USART0_RX_LOC == 9) +#define RTE_USART0_RX_PIN USART0_RX_PIN +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 5 +#endif +#if (USART0_RX_LOC == 10) +#define RTE_USART0_RX_PIN USART0_RX_PIN +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 0 //no pad +#endif +#if (USART0_RX_LOC == 11) +#define RTE_USART0_RX_PIN USART0_RX_PIN +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 19 +#endif +#if (USART0_RX_LOC == 12) +#define RTE_USART0_RX_PIN (USART0_RX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 23 +#endif +#if (USART0_RX_LOC == 13) +#define RTE_USART0_RX_PIN (USART0_RX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_RX_MUX 4 +#define RTE_USART0_RX_PAD 28 +#endif +//Pintool data +#endif // USART0_CTS <0=>P0_6 <1=>P0_26 <2=>P0_56 <3=>P0_70 // CTS for USART0 +#ifndef USART0_CTS_LOC #define RTE_USART0_CTS_PORT_ID 0 #if (RTE_USART0_CTS_PORT_ID == 0) @@ -205,9 +293,35 @@ #else #error "Invalid USART0 RTE_USART0_CTS_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_CTS_PORT USART0_CTS_PORT +#if (USART0_CTS_LOC == 14) +#define RTE_USART0_CTS_PIN USART0_CTS_PIN +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 1 +#endif +#if (USART0_CTS_LOC == 15) +#define RTE_USART0_CTS_PIN USART0_CTS_PIN +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 0 //NO PAD +#endif +#if (USART0_CTS_LOC == 16) +#define RTE_USART0_CTS_PIN USART0_CTS_PIN +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 20 +#endif +#if (USART0_CTS_LOC == 17) +#define RTE_USART0_CTS_PIN (USART0_CTS_PIN + GPIO_MAX_PIN) +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 28 +#endif +//Pintool data +#endif // USART0_RTS <0=>P0_9 <1=>P0_28 <2=>P0_53 <3=>P0_69 // RTS for USART0 +#ifndef USART0_RTS_LOC #define RTE_USART0_RTS_PORT_ID 0 #if (RTE_USART0_RTS_PORT_ID == 0) @@ -228,10 +342,35 @@ #else #error "Invalid USART0 RTE_USART0_RTS_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_RTS_PORT USART0_RTS_PORT +#if (USART0_RTS_LOC == 18) +#define RTE_USART0_RTS_PIN USART0_RTS_PIN +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 4 +#endif +#if (USART0_RTS_LOC == 19) +#define RTE_USART0_RTS_PIN USART0_RTS_PIN +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 0 //NO PAD +#endif +#if (USART0_RTS_LOC == 20) +#define RTE_USART0_RTS_PIN USART0_RTS_PIN +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 17 +#endif +#if (USART0_RTS_LOC == 21) +#define RTE_USART0_RTS_PIN (USART0_RTS_PIN + GPIO_MAX_PIN) +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 27 +#endif +//Pintool data +#endif // USART0_IR_TX <0=>P0_48 <1=>P0_72 // IR TX for USART0 - +#ifndef USART0_IRTX_LOC #define RTE_IR_TX_PORT_ID 0 #if ((RTE_IR_TX_PORT_ID == 2)) #error "Invalid USART0 RTE_USART0_IR_TX_PIN Pin Configuration!" @@ -255,10 +394,35 @@ #else #error "Invalid USART0 RTE_USART0_IR_TX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_IR_TX_PORT USART0_IRTX_PORT +#if (USART0_IRTX_LOC == 22) +#define RTE_USART0_IR_TX_PIN USART0_IRTX_PIN +#define RTE_USART0_IR_TX_MUX 13 +#define RTE_USART0_IR_TX_PAD 0 //No pad +#endif +#if (USART0_IRTX_LOC == 23) +#define RTE_USART0_IR_TX_PIN USART0_IRTX_PIN +#define RTE_USART0_IR_TX_MUX 2 +#define RTE_USART0_IR_TX_PAD 12 +#endif +#if (USART0_IRTX_LOC == 24) +#define RTE_USART0_IR_TX_PIN (USART0_IRTX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_IR_TX_MUX 11 +#define RTE_USART0_IR_TX_PAD 23 +#endif +#if (USART0_IRTX_LOC == 25) +#define RTE_USART0_IR_TX_PIN (USART0_IRTX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_IR_TX_MUX 2 +#define RTE_USART0_IR_TX_PAD 30 +#endif +//Pintool data +#endif // USART0_IR_RX <0=>P0_47 <1=>P0_71 <2=>P0_64 <3=>P0_25 // IR RX for USART0 - +#ifndef USART0_IRRX_LOC #define RTE_IR_RX_PORT_ID 0 #if ((RTE_IR_RX_PORT_ID == 2)) #error "Invalid USART0 RTE_USART0_IR_RX_PIN Pin Configuration!" @@ -282,9 +446,35 @@ #else #error "Invalid USART0 RTE_USART0_IR_RX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_IR_RX_PORT USART0_IRRX_PORT +#if (USART0_IRRX_LOC == 26) +#define RTE_USART0_IR_RX_PIN USART0_IRRX_PIN +#define RTE_USART0_IR_RX_MUX 13 +#define RTE_USART0_IR_RX_PAD 0 //no pad +#endif +#if (USART0_IRRX_LOC == 27) +#define RTE_USART0_IR_RX_PIN USART0_IRRX_PIN +#define RTE_USART0_IR_RX_MUX 2 +#define RTE_USART0_IR_RX_PAD 11 +#endif +#if (USART0_IRRX_LOC == 28) +#define RTE_USART0_IR_RX_PIN (USART0_IRRX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_IR_RX_MUX 11 +#define RTE_USART0_IR_RX_PAD 22 +#endif +#if (USART0_IRRX_LOC == 29) +#define RTE_USART0_IR_RX_PIN (USART0_IRRX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_IR_RX_MUX 2 +#define RTE_USART0_IR_RX_PAD 29 +#endif +//Pintool data +#endif // USART0_RI <0=>P0_27 <1=>P0_46 <2=>P0_68 // RI for USART0 +#ifndef USART0_RI_LOC #define RTE_RI_PORT_ID 0 #if (RTE_RI_PORT_ID == 0) @@ -300,9 +490,30 @@ #else #error "Invalid USART0 RTE_USART0_RI_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_RI_PORT USART0_RI_PORT +#if (USART0_RI_LOC == 30) +#define RTE_USART0_RI_PIN USART0_RI_PIN +#define RTE_USART0_RI_MUX 2 +#define RTE_USART0_RI_PAD 0 //no pad +#endif +#if (USART0_RI_LOC == 31) +#define RTE_USART0_RI_PIN USART0_RI_PIN +#define RTE_USART0_RI_MUX 2 +#define RTE_USART0_RI_PAD 10 +#endif +#if (USART0_RI_LOC == 32) +#define RTE_USART0_RI_PIN (USART0_RI_PIN + GPIO_MAX_PIN) +#define RTE_USART0_RI_MUX 11 +#define RTE_USART0_RI_PAD 26 +#endif +//Pintool data +#endif // USART0_DSR <0=>P0_11 <1=>P0_57 // DSR for USART0 +#ifndef USART0_DSR_LOC #define RTE_DSR_PORT_ID 0 #if (RTE_DSR_PORT_ID == 0) @@ -318,27 +529,56 @@ #else #error "Invalid USART0 RTE_USART0_RI_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_DSR_PORT USART0_DSR_PORT +#define RTE_USART0_DSR_PIN USART0_DSR_PIN +#if (USART0_DSR_LOC == 33) +#define RTE_USART0_DSR_MUX 2 +#define RTE_USART0_DSR_PAD 6 +#endif +#if (USART0_DSR_LOC == 34) +#define RTE_USART0_DSR_MUX 2 +#define RTE_USART0_DSR_PAD 21 +#endif +//Pintool data +#endif + // USART0_DCD <0=>P0_12 <1=>P0_29 // DCD for USART0 - +#ifndef USART0_DCD_LOC #define RTE_USART0_DCD_PORT 0 #define RTE_USART0_DCD_PIN 12 -#define RTE_USART0_DCD_MUX 2 -#define RTE_USART0_DCD_PAD 7 +#else +#define RTE_USART0_DCD_PORT USART0_DCD_PORT +#define RTE_USART0_DCD_PIN USART0_DCD_PIN +#if (USART0_DCD_LOC == 35) +#define RTE_USART0_DCD_MUX 2 +#define RTE_USART0_DCD_PAD 7 +#elif (USART0_DCD_LOC == 36) +#define RTE_USART0_DCD_MUX 12 +#define RTE_USART0_DCD_PAD 0 +#endif +#endif // USART0_DTR <0=>P0_7 // DTR for USART0 +#ifndef USART0_DTR_LOC #define RTE_USART0_DTR_PORT 0 #define RTE_USART0_DTR_PIN 7 -#define RTE_USART0_DTR_MUX 2 -#define RTE_USART0_DTR_PAD 2 +#else +#define RTE_USART0_DTR_PORT USART0_DTR_PORT +#define RTE_USART0_DTR_PIN USART0_DTR_PIN +#endif +#define RTE_USART0_DTR_MUX 2 +#define RTE_USART0_DTR_PAD 2 // // UART1 [Driver_UART1] // Configuration settings for Driver_UART1 in component ::CMSIS Driver:USART #define RTE_UART1 1 -#define RTE_UART1_CLK_SRC USART_INTFPLLCLK +#define RTE_UART1_CLK_SRC USART_ULPREFCLK #define RTE_UART1_CLK_DIV_FACT 1 #define RTE_UART1_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER @@ -358,7 +598,7 @@ /*UART1 PINS*/ // UART1_TX <0=>P0_7 <1=>P0_30 <2=>P0_67 <3=>P0_69 <4=>P0_73 <5=>P0_75 <6=>P0_34 // TX of UART1 - +#ifndef UART1_TX_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_UART1_TX_PORT_ID 0 #else @@ -397,10 +637,40 @@ #else #error "Invalid UART1 RTE_UART1_TX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_UART1_TX_PORT UART1_TX_PORT +#if (UART1_TX_LOC == 0) +#define RTE_UART1_TX_PIN UART1_TX_PIN +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 2 +#endif +#if (UART1_TX_LOC == 1) +#define RTE_UART1_TX_PIN UART1_TX_PIN +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 0 //no pad +#endif +#if (UART1_TX_LOC == 2) +#define RTE_UART1_TX_PIN (UART1_TX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 27 +#endif +#if (UART1_TX_LOC == 3) +#define RTE_UART1_TX_PIN (UART1_TX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 31 +#endif +#if (UART1_TX_LOC == 4) +#define RTE_UART1_TX_PIN (UART1_TX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_TX_MUX 9 +#define RTE_UART1_TX_PAD 33 +#endif +//Pintool data +#endif // UART1_RX <0=>P0_6 <1=>P0_29 <2=>P0_66 <3=>P0_68 <4=>P0_72 <5=>P0_74 <6=>P0_33 // RX of UART1 - +#ifndef UART1_RX_LOC #define RTE_UART1_RX_PORT_ID 0 #if (RTE_UART1_RX_PORT_ID == 0) @@ -431,9 +701,40 @@ #else #error "Invalid UART1 RTE_UART1_RX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_UART1_RX_PORT UART1_RX_PORT +#if (UART1_RX_LOC == 5) +#define RTE_UART1_RX_PIN UART1_RX_PIN +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 1 +#endif +#if (UART1_RX_LOC == 6) +#define RTE_UART1_RX_PIN UART1_RX_PIN +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 0 //no pad +#endif +#if (UART1_RX_LOC == 7) +#define RTE_UART1_RX_PIN (UART1_RX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 26 +#endif +#if (UART1_RX_LOC == 8) +#define RTE_UART1_RX_PIN (UART1_RX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 30 +#endif +#if (UART1_RX_LOC == 9) +#define RTE_UART1_RX_PIN (UART1_RX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RX_MUX 9 +#define RTE_UART1_RX_PAD 32 +#endif +//Pintool data +#endif // UART1_CTS <0=>P0_11 <1=>P0_28 <2=>P0_51 <3=>P0_65 <4=>P0_71 <5=>P0_73 <6=>P0_32 // CTS of UART1 +#ifndef UART1_CTS_LOC #define RTE_UART1_CTS_PORT_ID 0 #if (RTE_UART1_CTS_PORT_ID == 0) @@ -464,10 +765,45 @@ #else #error "Invalid UART1 RTE_UART1_CTS_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_UART1_CTS_PORT UART1_CTS_PORT +#if (UART1_CTS_LOC == 10) +#define RTE_UART1_CTS_PIN UART1_CTS_PIN +#define RTE_UART1_CTS_MUX 6 +#define RTE_UART1_CTS_PAD 6 +#endif +#if (UART1_CTS_LOC == 11) +#define RTE_UART1_CTS_PIN UART1_CTS_PIN +#define RTE_UART1_CTS_MUX 6 +#define RTE_UART1_CTS_PAD 0 //no pad +#endif +#if (UART1_CTS_LOC == 12) +#define RTE_UART1_CTS_PIN UART1_CTS_PIN +#define RTE_UART1_CTS_MUX 9 +#define RTE_UART1_CTS_PAD 15 +#endif +#if (UART1_CTS_LOC == 13) +#define RTE_UART1_CTS_PIN (UART1_CTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_CTS_MUX 9 +#define RTE_UART1_CTS_PAD 23 +#endif +#if (UART1_CTS_LOC == 14) +#define RTE_UART1_CTS_PIN (UART1_CTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_CTS_MUX 6 +#define RTE_UART1_CTS_PAD 29 +#endif +#if (UART1_CTS_LOC == 15) +#define RTE_UART1_CTS_PIN (UART1_CTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_CTS_MUX 9 +#define RTE_UART1_CTS_PAD 31 +#endif +//Pintool data +#endif // UART1_RTS <0=>P0_10 <1=>P0_27 <2=>P0_50 <3=>P0_64 <4=>P0_70 <5=>P0_72 <6=>P0_31 // RTS of UART1 - +#ifndef UART1_RTS_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_UART1_RTS_PORT_ID 0 #else @@ -502,6 +838,42 @@ #else #error "Invalid UART1 RTE_UART1_RTS_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_UART1_RTS_PORT UART1_RTS_PORT +#if (UART1_RTS_LOC == 16) +#define RTE_UART1_RTS_PIN UART1_RTS_PIN +#define RTE_UART1_RTS_MUX 6 +#define RTE_UART1_RTS_PAD 5 +#endif +#if (UART1_RTS_LOC == 17) +#define RTE_UART1_RTS_PIN UART1_RTS_PIN +#define RTE_UART1_RTS_MUX 6 +#define RTE_UART1_RTS_PAD 0 //no pad +#endif +#if (UART1_RTS_LOC == 18) +#define RTE_UART1_RTS_PIN UART1_RTS_PIN +#define RTE_UART1_RTS_MUX 9 +#define RTE_UART1_RTS_PAD 14 +#endif +#if (UART1_RTS_LOC == 19) +#define RTE_UART1_RTS_PIN (UART1_RTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RTS_MUX 9 +#define RTE_UART1_RTS_PAD 22 +#endif +#if (UART1_RTS_LOC == 20) +#define RTE_UART1_RTS_PIN (UART1_RTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RTS_MUX 6 +#define RTE_UART1_RTS_PAD 28 +#endif +#if (UART1_RTS_LOC == 21) +#define RTE_UART1_RTS_PIN (UART1_RTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RTS_MUX 9 +#define RTE_UART1_RTS_PAD 30 +#endif +//Pintool data +#endif + // // ULP_UART [Driver_ULP_UART] @@ -528,6 +900,7 @@ /*ULPSS UART PINS*/ // UART1_TX <0=>P0_3 <1=>P0_7 <2=>P0_11 // TX of ULPSS UART +#ifndef ULP_UART_TX_LOC #define RTE_ULP_UART_TX_PORT_ID 1 #if (RTE_ULP_UART_TX_PORT_ID == 0) #define RTE_ULP_UART_TX_PORT 0 @@ -540,9 +913,17 @@ #else #error "Invalid ULPSS UART RTE_ULP_UART_TX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_ULP_UART_TX_PORT ULP_UART_TX_PORT +#define RTE_ULP_UART_TX_PIN ULP_UART_TX_PIN +#define RTE_ULP_UART_TX_MUX 3 +//Pintool data +#endif // UART1_RX <0=>P0_2 <1=>P0_6 <2=>P0_9 // RX of ULPSS UART +#ifndef ULP_UART_RX_LOC #define RTE_ULP_UART_RX_PORT_ID 2 #if (RTE_ULP_UART_RX_PORT_ID == 0) #define RTE_ULP_UART_RX_PORT 0 @@ -559,9 +940,17 @@ #else #error "Invalid ULPSS UART RTE_ULP_UART_RX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_ULP_UART_RX_PORT ULP_UART_RX_PORT +#define RTE_ULP_UART_RX_PIN ULP_UART_RX_PIN +#define RTE_ULP_UART_RX_MUX 3 +//Pintool data +#endif // UART1_CTS <0=>P0_1 <1=>P0_5 <2=>P0_8 // CTS of ULPSS UART +#ifndef ULP_UART_CTS_LOC #define RTE_ULP_UART_CTS_PORT_ID 0 #if (RTE_ULP_UART_CTS_PORT_ID == 0) #define RTE_ULP_UART_CTS_PORT 0 @@ -574,17 +963,30 @@ #else #error "Invalid ULPSS UART RTE_ULP_UART_CTS_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_ULP_UART_CTS_PORT ULP_UART_CTS_PORT +#define RTE_ULP_UART_CTS_PIN ULP_UART_CTS_PIN +#define RTE_ULP_UART_CTS_MUX 3 +//Pintool data +#endif // UART1_RTS <0=>P0_0 <1=>P0_4 <2=>P0_10 // RTS of ULPSS UART +#ifndef ULP_UART_RTS_LOC #define RTE_ULP_UART_RTS_PORT_ID 0 #if (RTE_ULP_UART_RTS_PORT_ID == 0) #define RTE_ULP_UART_RTS_PORT 0 #define RTE_ULP_UART_RTS_PIN 10 -#define RTE_ULP_UART_RTS_MUX 8 #else #error "Invalid ULPSS UART RTE_ULP_UART_RTS_PIN Pin Configuration!" #endif +#else +#define RTE_ULP_UART_RTS_PORT ULP_UART_RTS_PORT +#define RTE_ULP_UART_RTS_PIN ULP_UART_RTS_PIN +#endif +#define RTE_ULP_UART_RTS_MUX 8 + // // SSI_MASTER (Serial Peripheral Interface 1) [Driver_SSI_MASTER] @@ -592,7 +994,7 @@ #define RTE_SSI_MASTER 1 // SSI_MASTER_MISO Pin <0=>GPIO_12 <1=>GPIO_27 <2=>GPIO_57 - +#ifndef SSI_MASTER_DATA1_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SSI_MASTER_MISO_PORT_ID 1 #else @@ -620,8 +1022,26 @@ #else #error "Invalid SSI_MASTER_MISO Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_MASTER_MISO 1 +#define RTE_SSI_MASTER_MISO_PORT SSI_MASTER_MISO_DATA1_PORT +#define RTE_SSI_MASTER_MISO_PIN SSI_MASTER_MISO_DATA1_PIN +#define RTE_SSI_MASTER_MISO_MODE EGPIO_PIN_MUX_MODE3 +#if (SSI_MASTER_DATA1_LOC == 3) +#define RTE_SSI_MASTER_MISO_PADSEL 7 +#endif +#if (SSI_MASTER_DATA1_LOC == 4) +#define RTE_SSI_MASTER_MISO_PADSEL 0 //NO PAD +#endif +#if (SSI_MASTER_DATA1_LOC == 5) +#define RTE_SSI_MASTER_MISO_PADSEL 21 +#endif +//Pintool data +#endif // SSI_MASTER_MOSI Pin <0=>GPIO_11 <1=>GPIO_26 <2=>GPIO_56 +#ifndef SSI_MASTER_DATA0_LOC #define RTE_SSI_MASTER_MOSI_PORT_ID 1 #if (RTE_SSI_MASTER_MOSI_PORT_ID == 0) @@ -645,8 +1065,26 @@ #else #error "Invalid SSI_MASTER_MOSI Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_MASTER_MOSI 1 +#define RTE_SSI_MASTER_MOSI_PORT SSI_MASTER_MOSI_DATA0_PORT +#define RTE_SSI_MASTER_MOSI_PIN SSI_MASTER_MOSI_DATA0_PIN +#define RTE_SSI_MASTER_MOSI_MODE EGPIO_PIN_MUX_MODE3 +#if (SSI_MASTER_DATA0_LOC == 0) +#define RTE_SSI_MASTER_MOSI_PADSEL 6 +#endif +#if (SSI_MASTER_DATA0_LOC == 1) +#define RTE_SSI_MASTER_MOSI_PADSEL 0 //NO PAD +#endif +#if (SSI_MASTER_DATA0_LOC == 2) +#define RTE_SSI_MASTER_MOSI_PADSEL 20 +#endif +//Pintool data +#endif // SSI_MASTER_SCK Pin <0=>GPIO_8 <1=>GPIO_25 <2=>GPIO_52 +#ifndef SSI_MASTER_SCK_LOC #define RTE_SSI_MASTER_SCK_PORT_ID 1 #if (RTE_SSI_MASTER_SCK_PORT_ID == 0) @@ -670,6 +1108,23 @@ #else #error "Invalid SSI_MASTER_SCK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_MASTER_SCK 1 +#define RTE_SSI_MASTER_SCK_PORT SSI_MASTER_SCK__PORT +#define RTE_SSI_MASTER_SCK_PIN SSI_MASTER_SCK__PIN +#define RTE_SSI_MASTER_SCK_MODE EGPIO_PIN_MUX_MODE3 +#if (SSI_MASTER_SCK_LOC == 6) +#define RTE_SSI_MASTER_SCK_PADSEL 3 +#endif +#if (SSI_MASTER_SCK_LOC == 7) +#define RTE_SSI_MASTER_SCK_PADSEL 0 //NO PAD +#endif +#if (SSI_MASTER_SCK_LOC == 8) +#define RTE_SSI_MASTER_SCK_PADSEL 16 +#endif +//Pintool data +#endif #define M4_SSI_CS0 1 #define M4_SSI_CS1 0 @@ -677,6 +1132,7 @@ #define M4_SSI_CS3 0 // SSI_MASTER_CS Pin <0=>GPIO_9 <1=>GPIO_28 <2=>GPIO_53 <3=>GPIO_10 <4=>GPIO_15 <5=>GPIO_50 <6=>GPIO_51 +#ifndef SSI_MASTER_CS0_LOC #define RTE_SSI_MASTER_CS0_PORT_ID 1 #if (RTE_SSI_MASTER_CS0_PORT_ID == 0) @@ -700,20 +1156,43 @@ #else #error "Invalid SSI_MASTER_CS0 Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_MASTER_CS0 M4_SSI_CS0 +#define RTE_SSI_MASTER_CS0_PORT SSI_MASTER_CS0__PORT +#define RTE_SSI_MASTER_CS0_PIN SSI_MASTER_CS0__PIN +#define RTE_SSI_MASTER_CS0_MODE EGPIO_PIN_MUX_MODE3 +#if (SSI_MASTER_CS0_LOC == 9) +#define RTE_SSI_MASTER_CS0_PADSEL 4 +#endif +#if (SSI_MASTER_CS0_LOC == 10) +#define RTE_SSI_MASTER_CS0_PADSEL 0 //NO PAD +#endif +#if (SSI_MASTER_CS0_LOC == 11) +#define RTE_SSI_MASTER_CS0_PADSEL 17 +#endif +//Pintool data +#endif //CS1 +#ifndef SSI_MASTER_CS1_LOC #define RTE_SSI_MASTER_CS1_PORT_ID 0 #if (RTE_SSI_MASTER_CS1_PORT_ID == 0) -#define RTE_SSI_MASTER_CS1 M4_SSI_CS1 -#define RTE_SSI_MASTER_CS1_PORT 0 -#define RTE_SSI_MASTER_CS1_PIN 10 -#define RTE_SSI_MASTER_CS1_MODE EGPIO_PIN_MUX_MODE3 -#define RTE_SSI_MASTER_CS1_PADSEL 5 +#define RTE_SSI_MASTER_CS1_PORT 0 +#define RTE_SSI_MASTER_CS1_PIN 10 #else #error "Invalid SSI_MASTER_CS1 Pin Configuration!" #endif +#else +#define RTE_SSI_MASTER_CS1_PORT SSI_MASTER_CS1__PORT +#define RTE_SSI_MASTER_CS1_PIN SSI_MASTER_CS1__PIN +#endif +#define RTE_SSI_MASTER_CS1 M4_SSI_CS1 +#define RTE_SSI_MASTER_CS1_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS1_PADSEL 5 //CS2 +#ifndef SSI_MASTER_CS2_LOC #define RTE_SSI_MASTER_CS2_PORT_ID 1 #if (RTE_SSI_MASTER_CS2_PORT_ID == 0) #define RTE_SSI_MASTER_CS2 M4_SSI_CS2 @@ -730,18 +1209,37 @@ #else #error "Invalid SSI_MASTER_CS2 Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_MASTER_CS2 M4_SSI_CS2 +#define RTE_SSI_MASTER_CS2_PORT SSI_MASTER_CS2__PORT +#define RTE_SSI_MASTER_CS2_PIN SSI_MASTER_CS2__PIN +#define RTE_SSI_MASTER_CS2_MODE EGPIO_PIN_MUX_MODE3 +#if (SSI_MASTER_CS2_LOC == 13) +#define RTE_SSI_MASTER_CS2_PADSEL 8 +#endif +#if (SSI_MASTER_CS2_LOC == 14) +#define RTE_SSI_MASTER_CS2_PADSEL 14 +#endif +//Pintool data +#endif //CS3 +#ifndef SSI_MASTER_CS3_LOC #define RTE_SSI_MASTER_CS3_PORT_ID 0 #if (RTE_SSI_MASTER_CS3_PORT_ID == 0) -#define RTE_SSI_MASTER_CS3 M4_SSI_CS3 -#define RTE_SSI_MASTER_CS3_PORT 0 -#define RTE_SSI_MASTER_CS3_PIN 51 -#define RTE_SSI_MASTER_CS3_MODE EGPIO_PIN_MUX_MODE3 -#define RTE_SSI_MASTER_CS3_PADSEL 15 +#define RTE_SSI_MASTER_CS3_PORT 0 +#define RTE_SSI_MASTER_CS3_PIN 51 #else #error "Invalid SSI_MASTER_CS3 Pin Configuration!" #endif +#else +#define RTE_SSI_MASTER_CS3_PORT SSI_MASTER_CS3__PORT +#define RTE_SSI_MASTER_CS3_PIN SSI_MASTER_CS3__PIN +#endif +#define RTE_SSI_MASTER_CS3 M4_SSI_CS3 +#define RTE_SSI_MASTER_CS3_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS3_PADSEL 15 // DMA Rx // Channel <28=>28 @@ -763,6 +1261,7 @@ #define RTE_SSI_SLAVE_INPUT_CLOCK SSISLAVE_CLK // SSI_SLAVE_MISO Pin <0=>Not Used <1=>GPIO_11 <2=>GPIO_28 <3=>GPIO_49 <4=>GPIO_57 +#ifndef SSI_SLAVE_MISO_LOC #define RTE_SSI_SLAVE_MISO_PORT_ID 2 #if (RTE_SSI_SLAVE_MISO_PORT_ID == 0) @@ -794,9 +1293,29 @@ #else #error "Invalid SSI_SLAVE_MISO Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_SLAVE_MISO 1 +#define RTE_SSI_SLAVE_MISO_PORT SSI_SLAVE_MISO__PORT +#define RTE_SSI_SLAVE_MISO_PIN SSI_SLAVE_MISO__PIN +#define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8 +#if (SSI_SLAVE_MISO_LOC == 5) +#define RTE_SSI_SLAVE_MISO_PADSEL 6 +#endif +#if (SSI_SLAVE_MISO_LOC == 6) +#define RTE_SSI_SLAVE_MISO_PADSEL 0 //no pad +#endif +#if (SSI_SLAVE_MISO_LOC == 7) +#define RTE_SSI_SLAVE_MISO_PADSEL 13 +#endif +#if (SSI_SLAVE_MISO_LOC == 8) +#define RTE_SSI_SLAVE_MISO_PADSEL 21 +#endif +//Pintool data +#endif // SSI_SLAVE_MOSI Pin <0=>Not Used <1=>GPIO_10 <2=>GPIO_27 <3=>GPIO_48 <4=>GPIO_56 - +#ifndef SSI_SLAVE_MOSI_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SSI_SLAVE_MOSI_PORT_ID 2 #else @@ -832,8 +1351,29 @@ #else #error "Invalid SSI_SLAVE_MOSI Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_SLAVE_MOSI 1 +#define RTE_SSI_SLAVE_MOSI_PORT SSI_SLAVE_MOSI__PORT +#define RTE_SSI_SLAVE_MOSI_PIN SSI_SLAVE_MOSI__PIN +#define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8 +#if (SSI_SLAVE_MOSI_LOC == 1) +#define RTE_SSI_SLAVE_MOSI_PADSEL 5 +#endif +#if (SSI_SLAVE_MOSI_LOC == 2) +#define RTE_SSI_SLAVE_MOSI_PADSEL 0 //no pad +#endif +#if (SSI_SLAVE_MOSI_LOC == 3) +#define RTE_SSI_SLAVE_MOSI_PADSEL 12 +#endif +#if (SSI_SLAVE_MOSI_LOC == 4) +#define RTE_SSI_SLAVE_MOSI_PADSEL 20 +#endif +//Pintool data +#endif // SSI_SLAVE_SCK Pin <0=>Not Used <1=>GPIO_8 <2=>GPIO_26 <3=>GPIO_47 <4=>GPIO_52 +#ifndef SSI_SLAVE_SCK_LOC #define RTE_SSI_SLAVE_SCK_PORT_ID 2 #if (RTE_SSI_SLAVE_SCK_PORT_ID == 0) @@ -865,8 +1405,29 @@ #else #error "Invalid SSI_SLAVE_SCK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_SLAVE_SCK 1 +#define RTE_SSI_SLAVE_SCK_PORT SSI_SLAVE_SCK__PORT +#define RTE_SSI_SLAVE_SCK_PIN SSI_SLAVE_SCK__PIN +#define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8 +#if (SSI_SLAVE_SCK_LOC == 9) +#define RTE_SSI_SLAVE_SCK_PADSEL 3 +#endif +#if (SSI_SLAVE_SCK_LOC == 10) +#define RTE_SSI_SLAVE_SCK_PADSEL 0 //no pad +#endif +#if (SSI_SLAVE_SCK_LOC == 11) +#define RTE_SSI_SLAVE_SCK_PADSEL 11 +#endif +#if (SSI_SLAVE_SCK_LOC == 12) +#define RTE_SSI_SLAVE_SCK_PADSEL 16 +#endif +//Pintool data +#endif // SSI_SLAVE_CS Pin <0=>Not Used <1=>GPIO_9 <2=>GPIO_25 <3=>GPIO_46 <4=>GPIO_53 +#ifndef SSI_SLAVE_CS0_LOC #define RTE_SSI_SLAVE_CS_PORT_ID 1 #if (RTE_SSI_SLAVE_CS_PORT_ID == 0) @@ -898,6 +1459,26 @@ #else #error "Invalid SSI_SLAVE_CS Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_SLAVE_CS 1 +#define RTE_SSI_SLAVE_CS_PORT SSI_SLAVE_CS0__PORT +#define RTE_SSI_SLAVE_CS_PIN SSI_SLAVE_CS0__PIN +#define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8 +#if (SSI_SLAVE_CS0_LOC == 13) +#define RTE_SSI_SLAVE_CS_PADSEL 4 +#endif +#if (SSI_SLAVE_CS0_LOC == 14) +#define RTE_SSI_SLAVE_CS_PADSEL 0 //no pad +#endif +#if (SSI_SLAVE_CS0_LOC == 15) +#define RTE_SSI_SLAVE_CS_PADSEL 10 +#endif +#if (SSI_SLAVE_CS0_LOC == 16) +#define RTE_SSI_SLAVE_CS_PADSEL 17 +#endif +//Pintool data +#endif // DMA Rx // Channel <22=>22 @@ -915,7 +1496,7 @@ // -// SSI_ULP_MASTER (Serial Peripheral Interface 3) [Driver_SSI_ULP_MASTER] +// ULP SPI Peripheral (Serial Peripheral Interface 3) [Driver_SSI_ULP_MASTER] // Configuration settings for Driver_SSI_ULP_MASTER in component ::CMSIS Driver:SPI #define RTE_SSI_ULP_MASTER 1 @@ -925,6 +1506,7 @@ #define ULP_SSI_CS2 0 // SSI_ULP_MASTER_MISO Pin <0=>Not Used <1=>ULP_GPIO_2 <2=>ULP_GPIO_9 +#ifndef ULP_SPI_MISO_LOC #define RTE_SSI_ULP_MASTER_MISO_PORT_ID 0 #if (RTE_SSI_ULP_MASTER_MISO_PORT_ID == 0) #define RTE_SSI_ULP_MASTER_MISO 1 @@ -939,8 +1521,17 @@ #else #error "Invalid SSI_ULP_MISO Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_ULP_MASTER_MISO 1 +#define RTE_SSI_ULP_MASTER_MISO_PORT ULP_SPI_MISO__PORT +#define RTE_SSI_ULP_MASTER_MISO_PIN ULP_SPI_MISO__PIN +#define RTE_SSI_ULP_MASTER_MISO_MODE 1 +//Pintool data +#endif // SSI_ULP_MASTER_MOSI Pin <0=>Not Used <1=>ULP_GPIO_1 <2=>ULP_GPIO_11 +#ifndef ULP_SPI_MOSI_LOC #define RTE_SSI_ULP_MASTER_MOSI_PORT_ID 0 #if (RTE_SSI_ULP_MASTER_MOSI_PORT_ID == 0) #define RTE_SSI_ULP_MASTER_MOSI 1 @@ -955,8 +1546,17 @@ #else #error "Invalid SSI_ULP_MOSI Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_ULP_MASTER_MOSI 1 +#define RTE_SSI_ULP_MASTER_MOSI_PORT ULP_SPI_MOSI__PORT +#define RTE_SSI_ULP_MASTER_MOSI_PIN ULP_SPI_MOSI__PIN +#define RTE_SSI_ULP_MASTER_MOSI_MODE 1 +//Pintool data +#endif // SSI_ULP_MASTER_SCK Pin <0=>Not Used <1=>ULP_GPIO_0 <2=>ULP_GPIO_8 +#ifndef ULP_SPI_SCK_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SSI_ULP_MASTER_SCK_PORT_ID 2 #else @@ -977,8 +1577,17 @@ #else #error "Invalid SSI_ULP_SCK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_ULP_MASTER_SCK 1 +#define RTE_SSI_ULP_MASTER_SCK_PORT ULP_SPI_SCK__PORT +#define RTE_SSI_ULP_MASTER_SCK_PIN ULP_SPI_SCK__PIN +#define RTE_SSI_ULP_MASTER_SCK_MODE 1 +//Pintool data +#endif // CS0 +#ifndef ULP_SPI_CS0_LOC #define RTE_SSI_ULP_MASTER_CS0_PORT_ID 1 #if (RTE_SSI_ULP_MASTER_CS0_PORT_ID == 0) #define RTE_SSI_ULP_MASTER_CS0 ULP_SSI_CS0 @@ -993,17 +1602,35 @@ #else #error "Change RTE_SSI_ULP_MASTER_CS_PORT_ID other than '1' or'3' as per PACKAGE_TYPE" #endif +#else +//Pintool data +#define RTE_SSI_ULP_MASTER_CS0 ULP_SSI_CS0 +#define RTE_SSI_ULP_MASTER_CS0_PORT ULP_SPI_CS0__PORT +#define RTE_SSI_ULP_MASTER_CS0_PIN ULP_SPI_CS0__PIN +#define RTE_SSI_ULP_MASTER_CS0_MODE 1 +//Pintool data +#endif // CS1 -#define RTE_SSI_ULP_MASTER_CS1 ULP_SSI_CS1 +#ifndef ULP_SPI_CS1_LOC #define RTE_SSI_ULP_MASTER_CS1_PORT 0 #define RTE_SSI_ULP_MASTER_CS1_PIN 4 +#else +#define RTE_SSI_ULP_MASTER_CS1_PORT ULP_SPI_CS1__PORT +#define RTE_SSI_ULP_MASTER_CS1_PIN ULP_SPI_CS1__PIN +#endif +#define RTE_SSI_ULP_MASTER_CS1 ULP_SSI_CS1 #define RTE_SSI_ULP_MASTER_CS1_MODE 1 // CS2 -#define RTE_SSI_ULP_MASTER_CS2 ULP_SSI_CS2 +#ifndef ULP_SPI_CS2_LOC #define RTE_SSI_ULP_MASTER_CS2_PORT 0 #define RTE_SSI_ULP_MASTER_CS2_PIN 6 +#else +#define RTE_SSI_ULP_MASTER_CS2_PORT ULP_SPI_CS2__PORT +#define RTE_SSI_ULP_MASTER_CS2_PIN ULP_SPI_CS2__PIN +#endif +#define RTE_SSI_ULP_MASTER_CS2 ULP_SSI_CS2 #define RTE_SSI_ULP_MASTER_CS2_MODE 1 // DMA Rx @@ -1064,6 +1691,7 @@ // I2S0_SCLK <0=>P0_8 <1=>P0_25 <2=>P0_46 <3=>P0_52 // SCLK of I2S0 +#ifndef I2S0_SCLK_LOC #define RTE_I2S0_SCLK_PORT_ID 1 #if (RTE_I2S0_SCLK_PORT_ID == 0) @@ -1089,9 +1717,29 @@ #else #error "Invalid I2S0 RTE_I2S0_SCLK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S0_SCLK_PORT I2S0_SCLK_PORT +#define RTE_I2S0_SCLK_PIN I2S0_SCLK_PIN +#define RTE_I2S0_SCLK_MUX 7 +#if (I2S0_SCLK_LOC == 0) +#define RTE_I2S0_SCLK_PAD 3 +#endif +#if (I2S0_SCLK_LOC == 1) +#define RTE_I2S0_SCLK_PAD 0 //no pad +#endif +#if (I2S0_SCLK_LOC == 2) +#define RTE_I2S0_SCLK_PAD 10 +#endif +#if (I2S0_SCLK_LOC == 3) +#define RTE_I2S0_SCLK_PAD 16 +#endif +//Pintool data +#endif // I2S0_WSCLK <0=>P0_9 <1=>P0_26 <2=>P0_47 <3=>P0_53 // WSCLK for I2S0 +#ifndef I2S0_WSCLK_LOC #define RTE_I2S0_WSCLK_PORT_ID 1 #if (RTE_I2S0_WSCLK_PORT_ID == 0) @@ -1117,9 +1765,29 @@ #else #error "Invalid I2S0 RTE_I2S0_WSCLK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S0_WSCLK_PORT I2S0_WSCLK_PORT +#define RTE_I2S0_WSCLK_PIN I2S0_WSCLK_PIN +#define RTE_I2S0_WSCLK_MUX 7 +#if (I2S0_WSCLK_LOC == 4) +#define RTE_I2S0_WSCLK_PAD 4 +#endif +#if (I2S0_WSCLK_LOC == 5) +#define RTE_I2S0_WSCLK_PAD 0 +#endif +#if (I2S0_WSCLK_LOC == 6) +#define RTE_I2S0_WSCLK_PAD 11 +#endif +#if (I2S0_WSCLK_LOC == 7) +#define RTE_I2S0_WSCLK_PAD 17 +#endif +//Pintool data +#endif // I2S0_DOUT0 <0=>P0_11 <1=>P0_28 <2=>P0_49 <3=>P0_57 // DOUT0 for I2S0 +#ifndef I2S0_DOUT0_LOC #define RTE_I2S0_DOUT0_PORT_ID 1 #if (RTE_I2S0_DOUT0_PORT_ID == 0) @@ -1145,9 +1813,29 @@ #else #error "Invalid I2S0 RTE_I2S0_DOUT0 Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S0_DOUT0_PORT I2S0_DOUT0_PORT +#define RTE_I2S0_DOUT0_PIN I2S0_DOUT0_PIN +#define RTE_I2S0_DOUT0_MUX 7 +#if (I2S0_DOUT0_LOC == 8) +#define RTE_I2S0_DOUT0_PAD 6 +#endif +#if (I2S0_DOUT0_LOC == 9) +#define RTE_I2S0_DOUT0_PAD 0 +#endif +#if (I2S0_DOUT0_LOC == 10) +#define RTE_I2S0_DOUT0_PAD 13 +#endif +#if (I2S0_DOUT0_LOC == 11) +#define RTE_I2S0_DOUT0_PAD 21 +#endif +//Pintool data +#endif // I2S0_DIN0 <0=>P0_10 <1=>P0_27 <2=>P0_48 <3=>P0_56 // DIN0 for I2S0 +#ifndef I2S0_DIN0_LOC #define RTE_I2S0_DIN0_PORT_ID 1 #if (RTE_I2S0_DIN0_PORT_ID == 0) @@ -1173,11 +1861,30 @@ #else #error "Invalid I2S0 RTE_I2S0_DIN0 Pin Configuration!" #endif - -// I2S0_DOUT1 <0=>P0_7 <1=>P0_30 <2=>P0_51 <3=>P0_55 -// DOUT1 for I2S0 - -#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#else +//Pintool data +#define RTE_I2S0_DIN0_PORT I2S0_DIN0_PORT +#define RTE_I2S0_DIN0_PIN I2S0_DIN0_PIN +#define RTE_I2S0_DIN0_MUX 7 +#if (I2S0_DIN0_LOC == 12) +#define RTE_I2S0_DIN0_PAD 5 +#endif +#if (I2S0_DIN0_LOC == 13) +#define RTE_I2S0_DIN0_PAD 0 +#endif +#if (I2S0_DIN0_LOC == 14) +#define RTE_I2S0_DIN0_PAD 12 +#endif +#if (I2S0_DIN0_LOC == 15) +#define RTE_I2S0_DIN0_PAD 20 +#endif +//Pintool data +#endif + +// I2S0_DOUT1 <0=>P0_7 <1=>P0_30 <2=>P0_51 <3=>P0_55 +// DOUT1 for I2S0 +#ifndef I2S0_DOUT1_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_I2S0_DOUT1_PORT_ID 1 #else #define RTE_I2S0_DOUT1_PORT_ID 0 @@ -1206,9 +1913,29 @@ #else #error "Invalid I2S0 RTE_I2S0_DOUT1 Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S0_DOUT1_PORT I2S0_DOUT1_PORT +#define RTE_I2S0_DOUT1_PIN I2S0_DOUT1_PIN +#define RTE_I2S0_DOUT1_MUX 7 +#if (I2S0_DOUT1_LOC == 16) +#define RTE_I2S0_DOUT1_PAD 2 +#endif +#if (I2S0_DOUT1_LOC == 17) +#define RTE_I2S0_DOUT1_PAD 0 +#endif +#if (I2S0_DOUT1_LOC == 18) +#define RTE_I2S0_DOUT1_PAD 15 +#endif +#if (I2S0_DOUT1_LOC == 19) +#define RTE_I2S0_DOUT1_PAD 19 +#endif +//Pintool data +#endif // I2S0_DIN1 <0=>P0_6 <1=>P0_29 <2=>P0_50 <3=>P0_54 // DIN1 for I2S0 +#ifndef I2S0_DIN1_LOC #define RTE_I2S0_DIN1_PORT_ID 0 #if (RTE_I2S0_DIN1_PORT_ID == 0) @@ -1234,8 +1961,27 @@ #else #error "Invalid I2S0 RTE_I2S0_DIN1 Pin Configuration!" #endif -// FIFO level can have value 1 to 7 -#define I2S0_TX_FIFO_LEVEL (2U) +#else +//Pintool data +#define RTE_I2S0_DIN1_PORT I2S0_DIN1_PORT +#define RTE_I2S0_DIN1_PIN I2S0_DIN1_PIN +#define RTE_I2S0_DIN1_MUX 7 +#if (I2S0_DIN1_LOC == 20) +#define RTE_I2S0_DIN1_PAD 1 +#endif +#if (I2S0_DIN1_LOC == 21) +#define RTE_I2S0_DIN1_PAD 0 +#endif +#if (I2S0_DIN1_LOC == 22) +#define RTE_I2S0_DIN1_PAD 14 +#endif +#if (I2S0_DIN1_LOC == 23) +#define RTE_I2S0_DIN1_PAD 18 +#endif +//Pintool data +#endif +// FIFO level can have value 0 to 7 +#define I2S0_TX_FIFO_LEVEL (0U) #define I2S0_RX_FIFO_LEVEL (2U) // I2S0_TX_RES <0=>12 @@ -1283,13 +2029,14 @@ // -// I2S1 [Driver_I2S1] +// ULP I2S [Driver_I2S1] // Configuration settings for Driver_I2S1 in component ::Drivers:I2S #define RTE_I2S1 1 #define I2S1_IRQHandler IRQ014_Handler // I2S1_SCLK Pin <0=>P0_3 <1=>P0_7 <2=>P0_8 /*I2S1 PINS*/ +#ifndef ULP_I2S_SCLK_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_I2S1_SCLK_PORT_ID 0 #else @@ -1310,8 +2057,16 @@ #else #error "Invalid I2S1 RTE_I2S1_SCLK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S1_SCLK_PORT ULP_I2S_SCLK_PORT +#define RTE_I2S1_SCLK_PIN ULP_I2S_SCLK_PIN +#define RTE_I2S1_SCLK_MUX 2 +//Pintool data +#endif // I2S1_WSCLK Pin <0=>P0_2 <1=>P0_4 <2=>P0_10 +#ifndef ULP_I2S_WSCLK_LOC #define RTE_I2S1_WSCLK_PORT_ID 0 #if (RTE_I2S1_WSCLK_PORT_ID == 0) #define RTE_I2S1_WSCLK_PORT 0 @@ -1324,8 +2079,16 @@ #else #error "Invalid I2S1 RTE_I2S1_WSCLK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S1_WSCLK_PORT ULP_I2S_WSCLK_PORT +#define RTE_I2S1_WSCLK_PIN ULP_I2S_WSCLK_PIN +#define RTE_I2S1_WSCLK_MUX 2 +//Pintool data +#endif // I2S1_DOUT0 Pin <0=>P0_1 <1=>P0_5 <2=>P0_11 +#ifndef ULP_I2S_DOUT0_LOC #define RTE_I2S1_DOUT0_PORT_ID 0 #if (RTE_I2S1_DOUT0_PORT_ID == 0) #define RTE_I2S1_DOUT0_PORT 0 @@ -1338,8 +2101,16 @@ #else #error "Invalid I2S1 RTE_I2S1_DOUT0 Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S1_DOUT0_PORT ULP_I2S_DOUT0_PORT +#define RTE_I2S1_DOUT0_PIN ULP_I2S_DOUT0_PIN +#define RTE_I2S1_DOUT0_MUX 2 +//Pintool data +#endif // I2S1_DIN0 Pin <0=>P0_0 <1=>P0_6 <2=>P0_9 <3=>P0_13 +#ifndef ULP_I2S_DIN0_LOC #define RTE_I2S1_DIN0_PORT_ID 1 #if (RTE_I2S1_DIN0_PORT_ID == 0) #define RTE_I2S1_DIN0_PORT 0 @@ -1356,9 +2127,16 @@ #else #error "Invalid I2S1 RTE_I2S1_DIN0 Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S1_DIN0_PORT ULP_I2S_DIN0_PORT +#define RTE_I2S1_DIN0_PIN ULP_I2S_DIN0_PIN +#define RTE_I2S1_DIN0_MUX 2 +//Pintool data +#endif -// FIFO level can have value 1 to 7 -#define I2S1_TX_FIFO_LEVEL (2U) +// FIFO level can have value 0 to 7 +#define I2S1_TX_FIFO_LEVEL (0U) #define I2S1_RX_FIFO_LEVEL (2U) // I2S1_TX_RES <0=>12 @@ -1413,7 +2191,7 @@ #define I2C0_IRQHandler IRQ042_Handler // I2C0_SCL Pin <0=>P0_7 <1=>P0_65 <2=>P0_66 <3=>P0_75 <4=>P0_32 - +#ifndef I2C0_SCL_LOC #define RTE_I2C0_SCL_PORT_ID 1 #if (RTE_I2C0_SCL_PORT_ID == 0) @@ -1443,9 +2221,32 @@ #else #error "Invalid I2C0 RTE_I2C0_SCL Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2C0_SCL_PORT I2C0_SCL_PORT +#if (I2C0_SCL_LOC == 0) +#define RTE_I2C0_SCL_PIN I2C0_SCL_PIN +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 2 +#define RTE_I2C0_SCL_I2C_REN 7 +#endif +#if (I2C0_SCL_LOC == 1) +#define RTE_I2C0_SCL_PIN (I2C0_SCL_PIN + GPIO_MAX_PIN) +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 23 +#define RTE_I2C0_SCL_I2C_REN 1 +#endif +#if (I2C0_SCL_LOC == 2) +#define RTE_I2C0_SCL_PIN (I2C0_SCL_PIN + GPIO_MAX_PIN) +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 33 +#define RTE_I2C0_SCL_I2C_REN 11 +#endif +//Pintool data +#endif // I2C0_SCL Pin <0=>P0_6 <1=>P0_64 <2=>P0_67 <3=>P0_74 <4=>P0_31 - +#ifndef I2C0_SDA_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_I2C0_SDA_PORT_ID 2 #else @@ -1473,6 +2274,29 @@ #else #error "Invalid I2C0 RTE_I2C0_SDA Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2C0_SDA_PORT I2C0_SDA_PORT +#if (I2C0_SDA_LOC == 3) +#define RTE_I2C0_SDA_PIN I2C0_SDA_PIN +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 1 +#define RTE_I2C0_SDA_I2C_REN 6 +#endif +#if (I2C0_SDA_LOC == 4) +#define RTE_I2C0_SDA_PIN (I2C0_SDA_PIN + GPIO_MAX_PIN) +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 22 +#define RTE_I2C0_SDA_I2C_REN 3 +#endif +#if (I2C0_SDA_LOC == 5) +#define RTE_I2C0_SDA_PIN (I2C0_SDA_PIN + GPIO_MAX_PIN) +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 32 +#define RTE_I2C0_SDA_I2C_REN 10 +#endif +//Pintool data +#endif #define IC_SCL_STUCK_TIMEOUT 20 #define IC_SDA_STUCK_TIMEOUT 20 @@ -1482,7 +2306,7 @@ #define DMA_TX_TL 1 #define DMA_RX_TL 1 #endif -// I2C0 [Driver_I2C0] +// I2C1 [Driver_I2C0] // I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1] // Configuration settings for Driver_I2C1 in component ::Drivers:I2C @@ -1490,6 +2314,7 @@ #define RTE_I2C1 1 #define I2C1_IRQHandler IRQ061_Handler // I2C1_SCL Pin <0=>P0_6 <1=>P0_29 <2=>P0_50 <3=>P0_54 <4=>P0_64 <4=>P0_66 <4=>P0_70 <7=>P0_33 +#ifndef I2C1_SCL_LOC #define RTE_I2C1_SCL_PORT_ID 2 #if (RTE_I2C1_SCL_PORT_ID == 0) @@ -1531,9 +2356,50 @@ #else #error "Invalid I2C1_SCL Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2C1_SCL_PORT I2C1_SCL_PORT +#if (I2C1_SCL_LOC == 0) +#define RTE_I2C1_SCL_PIN I2C1_SCL_PIN +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 1 +#define RTE_I2C1_SCL_REN 6 +#endif +#if (I2C1_SCL_LOC == 1) +#define RTE_I2C1_SCL_PIN I2C1_SCL_PIN +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 0 //no pad +#define RTE_I2C1_SCL_REN 29 +#endif +#if (I2C1_SCL_LOC == 2) +#define RTE_I2C1_SCL_PIN I2C1_SCL_PIN +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 14 +#define RTE_I2C1_SCL_REN 50 +#endif +#if (I2C1_SCL_LOC == 3) +#define RTE_I2C1_SCL_PIN I2C1_SCL_PIN +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 18 +#define RTE_I2C1_SCL_REN 54 +#endif +#if (I2C1_SCL_LOC == 4) +#define RTE_I2C1_SCL_PIN (I2C1_SCL_PIN + GPIO_MAX_PIN) +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 22 +#define RTE_I2C1_SCL_REN 2 +#endif +#if (I2C1_SCL_LOC == 5) +#define RTE_I2C1_SCL_PIN (I2C1_SCL_PIN + GPIO_MAX_PIN) +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 29 +#define RTE_I2C1_SCL_REN 6 +#endif +//Pintool data +#endif // I2C1_SCL Pin <0=>P0_7 <1=>P0_30 <2=>P0_51 <3=>P0_55 <4=>P0_65 <4=>P0_67 <4=>P0_71 <7=>P0_34 - +#ifndef I2C1_SDA_LOC #define RTE_I2C1_SDA_PORT_ID 2 #if (RTE_I2C1_SDA_PORT_ID == 0) @@ -1581,6 +2447,47 @@ #else #error "Invalid I2C1_SDA Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2C1_SDA_PORT I2C1_SDA_PORT +#if (I2C1_SDA_LOC == 6) +#define RTE_I2C1_SDA_PIN I2C1_SDA_PIN +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 2 +#define RTE_I2C1_SDA_REN 7 +#endif +#if (I2C1_SDA_LOC == 7) +#define RTE_I2C1_SDA_PIN I2C1_SDA_PIN +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 0 //no pad +#define RTE_I2C1_SDA_REN 30 +#endif +#if (I2C1_SDA_LOC == 8) +#define RTE_I2C1_SDA_PIN I2C1_SDA_PIN +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 15 +#define RTE_I2C1_SDA_REN 51 +#endif +#if (I2C1_SDA_LOC == 9) +#define RTE_I2C1_SDA_PIN I2C1_SDA_PIN +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 19 +#define RTE_I2C1_SDA_REN 55 +#endif +#if (I2C1_SDA_LOC == 10) +#define RTE_I2C1_SDA_PIN (I2C1_SDA_PIN + GPIO_MAX_PIN) +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 23 +#define RTE_I2C1_SDA_REN 1 +#endif +#if (I2C1_SDA_LOC == 11) +#define RTE_I2C1_SDA_PIN (I2C1_SDA_PIN + GPIO_MAX_PIN) +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 29 +#define RTE_I2C1_SDA_REN 7 +#endif +//Pintool data +#endif #define IC_SCL_STUCK_TIMEOUT 20 #define IC_SDA_STUCK_TIMEOUT 20 @@ -1593,12 +2500,13 @@ // I2C1 [Driver_I2C1] -// I2C2 (Inter-integrated Circuit Interface 2) [Driver_I2C2] +// ULP I2C (Inter-integrated Circuit Interface 2) [Driver_I2C2] // Configuration settings for Driver_I2C2 in component ::Drivers:I2C #define RTE_I2C2 1 #define I2C2_IRQHandler IRQ013_Handler // I2C2_SCL Pin <0=>P0_1 <1=>P0_5 <2=>P0_7 <3=>P0_8 <4=>P0_13 +#ifndef ULP_I2C_SCL_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_I2C2_SCL_PORT_ID 0 #else @@ -1617,8 +2525,25 @@ #else #error "Invalid I2C2_SCL Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2C2_SCL_PORT ULP_I2C_SCL_PORT +#define RTE_I2C2_SCL_PIN ULP_I2C_SCL_PIN +#define RTE_I2C2_SCL_MUX 4 +#if (ULP_I2C_SCL_LOC == 0) +#define RTE_I2C2_SCL_REN 0 +#elif (ULP_I2C_SCL_LOC == 1) +#define RTE_I2C2_SCL_REN 0 +#elif (ULP_I2C_SCL_LOC == 2) +#define RTE_I2C2_SCL_REN 7 +#elif (ULP_I2C_SCL_LOC == 3) +#define RTE_I2C2_SCL_REN 8 +#endif +//Pintool data +#endif // I2C2_SDA Pin <0=>P0_0 <1=>P0_4 <2=>P0_6 <3=>P0_9 <4=>P0_11 <5=>P0_12 +#ifndef ULP_I2C_SDA_LOC #define RTE_I2C2_SDA_PORT_ID 0 #if (RTE_I2C2_SDA_PORT_ID == 0) #define RTE_I2C2_SDA_PORT 0 @@ -1626,10 +2551,10 @@ #define RTE_I2C2_SDA_MUX 4 #define RTE_I2C2_SDA_REN 6 #elif (RTE_I2C2_SDA_PORT_ID == 1) -#define RTE_I2C2_SDA_PORT 0 -#define RTE_I2C2_SDA_PIN 9 -#define RTE_I2C2_SDA_MUX 4 -#define RTE_I2C2_SDA_I2C_REN 9 +#define RTE_I2C2_SDA_PORT 0 +#define RTE_I2C2_SDA_PIN 9 +#define RTE_I2C2_SDA_MUX 4 +#define RTE_I2C2_SDA_REN 9 #elif (RTE_I2C2_SDA_PORT_ID == 2) #define RTE_I2C2_SDA_PORT 0 #define RTE_I2C2_SDA_PIN 11 @@ -1638,6 +2563,24 @@ #else #error "Invalid I2C2_SDA Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2C2_SDA_PORT I2C2_SDA_PORT +#define RTE_I2C2_SDA_PIN I2C2_SDA_PIN +#define RTE_I2C2_SDA_MUX 4 +#if (ULP_I2C_SDA_LOC == 4) +#define RTE_I2C2_SDA_REN 0 +#elif (ULP_I2C_SDA_LOC == 5) +#define RTE_I2C2_SDA_REN 0 +#elif (ULP_I2C_SDA_LOC == 6) +#define RTE_I2C2_SDA_REN 6 +#elif (ULP_I2C_SDA_LOC == 7) +#define RTE_I2C2_SDA_REN 9 +#elif (ULP_I2C_SDA_LOC == 8) +#define RTE_I2C2_SDA_REN 11 +#endif +//Pintool data +#endif #define IC_SCL_STUCK_TIMEOUT 20 #define IC_SDA_STUCK_TIMEOUT 20 @@ -1656,6 +2599,7 @@ // GSPI_MASTER_CLK <0=>P0_8 <1=>P0_25 <2=>P0_46 <3=>P0_52 // CLK of GSPI0 +#ifndef GSPI_MASTER_SCK_LOC #define RTE_GSPI_MASTER_CLK_PORT_ID 1 #if (RTE_GSPI_MASTER_CLK_PORT_ID == 0) @@ -1681,12 +2625,31 @@ #else #error "Invalid GSPI0 RTE_GSPI_MASTER_CLK_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_GSPI_MASTER_CLK_PORT GSPI_MASTER_SCK__PORT +#define RTE_GSPI_MASTER_CLK_PIN GSPI_MASTER_SCK__PIN +#define RTE_GSPI_MASTER_CLK_MUX 4 +#if (GSPI_MASTER_SCK_LOC == 0) +#define RTE_GSPI_MASTER_CLK_PAD 3 +#endif +#if (GSPI_MASTER_SCK_LOC == 1) +#define RTE_GSPI_MASTER_CLK_PAD 0 +#endif +#if (GSPI_MASTER_SCK_LOC == 2) +#define RTE_GSPI_MASTER_CLK_PAD 10 +#endif +#if (GSPI_MASTER_SCK_LOC == 3) +#define RTE_GSPI_MASTER_CLK_PAD 16 +#endif +//Pintool data +#endif // GSPI_MASTER_CS0 // <0=>P0_9 <1=>P0_28 <2=>P0_49 <3=>P0_53 // CS0 of GSPI0 // - +#ifndef GSPI_MASTER_CS0_LOC #define RTE_GSPI_MASTER_CS0_PORT_ID 1 #if (RTE_GSPI_MASTER_CS0_PORT_ID == 0) @@ -1716,11 +2679,32 @@ #else #error "Invalid GSPI0 RTE_GSPI_MASTER_CS0_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_GSPI_MASTER_CS0 1 +#define RTE_GSPI_MASTER_CS0_PORT GSPI_MASTER_CS0__PORT +#define RTE_GSPI_MASTER_CS0_PIN GSPI_MASTER_CS0__PIN +#define RTE_GSPI_MASTER_CS0_MUX 4 +#if (GSPI_MASTER_CS0_LOC == 4) +#define RTE_GSPI_MASTER_CS0_PAD 4 +#endif +#if (GSPI_MASTER_CS0_LOC == 5) +#define RTE_GSPI_MASTER_CS0_PAD 0 +#endif +#if (GSPI_MASTER_CS0_LOC == 6) +#define RTE_GSPI_MASTER_CS0_PAD 13 +#endif +#if (GSPI_MASTER_CS0_LOC == 7) +#define RTE_GSPI_MASTER_CS0_PAD 17 +#endif +//Pintool data +#endif // GSPI_MASTER_CS1 // <0=>P0_10 <1=>P0_29 <2=>P0_50 <3=>P0_54 // CS1 of GSPI0 // +#ifndef GSPI_MASTER_CS1_LOC #define RTE_GSPI_MASTER_CS1_PORT_ID 1 #if (RTE_GSPI_MASTER_CS1_PORT_ID == 0) #define RTE_GSPI_MASTER_CS1 1 @@ -1749,11 +2733,32 @@ #else #error "Invalid GSPI0 RTE_GSPI_MASTER_CS1_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_GSPI_MASTER_CS1 1 +#define RTE_GSPI_MASTER_CS1_PORT GSPI_MASTER_CS1__PORT +#define RTE_GSPI_MASTER_CS1_PIN GSPI_MASTER_CS1__PIN +#define RTE_GSPI_MASTER_CS1_MUX 4 +#if (GSPI_MASTER_CS1_LOC == 8) +#define RTE_GSPI_MASTER_CS1_PAD 5 +#endif +#if (GSPI_MASTER_CS1_LOC == 9) +#define RTE_GSPI_MASTER_CS1_PAD 0 +#endif +#if (GSPI_MASTER_CS1_LOC == 10) +#define RTE_GSPI_MASTER_CS1_PAD 14 +#endif +#if (GSPI_MASTER_CS1_LOC == 11) +#define RTE_GSPI_MASTER_CS1_PAD 18 +#endif +//Pintool data +#endif // GSPI_MASTER_CS2 // <0=>P0_15 <1=>P0_30 <2=>P0_51 <3=>P0_55 // CS2 of GSPI0 // +#ifndef GSPI_MASTER_CS2_LOC #define RTE_GSPI_MASTER_CS2_PORT_ID 1 #if (RTE_GSPI_MASTER_CS2_PORT_ID == 0) #define RTE_GSPI_MASTER_CS2 1 @@ -1782,10 +2787,30 @@ #else #error "Invalid GSPI0 RTE_GSPI_MASTER_CS2_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_GSPI_MASTER_CS2 1 +#define RTE_GSPI_MASTER_CS2_PORT GSPI_MASTER_CS2__PORT +#define RTE_GSPI_MASTER_CS2_PIN GSPI_MASTER_CS2__PIN +#define RTE_GSPI_MASTER_CS2_MUX 4 +#if (GSPI_MASTER_CS2_LOC == 12) +#define RTE_GSPI_MASTER_CS2_PAD 8 +#endif +#if (GSPI_MASTER_CS2_LOC == 13) +#define RTE_GSPI_MASTER_CS2_PAD 0 +#endif +#if (GSPI_MASTER_CS2_LOC == 14) +#define RTE_GSPI_MASTER_CS2_PAD 15 +#endif +#if (GSPI_MASTER_CS2_LOC == 15) +#define RTE_GSPI_MASTER_CS2_PAD 19 +#endif +//Pintool data +#endif // GSPI_MASTER_MOSI <0=>P0_12 <1=>P0_27 <2=>P0_48 <3=>P0_57 <4=>P0_6 // MOSI of GSPI0 - +#ifndef GSPI_MASTER_MOSI_LOC #define RTE_GSPI_MASTER_MOSI_PORT_ID 1 #if (RTE_GSPI_MASTER_MOSI_PORT_ID == 0) @@ -1816,10 +2841,36 @@ #else #error "Invalid GSPI0 RTE_GSPI_MASTER_MOSI_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_GSPI_MASTER_MOSI_PORT GSPI_MASTER_MOSI__PORT +#define RTE_GSPI_MASTER_MOSI_PIN GSPI_MASTER_MOSI__PIN +#if (GSPI_MASTER_MOSI_LOC == 16) +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 1 +#endif +#if (GSPI_MASTER_MOSI_LOC == 17) +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 0 +#endif +#if (GSPI_MASTER_MOSI_LOC == 18) +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 12 +#endif +#if (GSPI_MASTER_MOSI_LOC == 19) +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 21 +#endif +#if (GSPI_MASTER_MOSI_LOC == 20) +#define RTE_GSPI_MASTER_MOSI_MUX 12 +#define RTE_GSPI_MASTER_MOSI_PAD 1 +#endif +//Pintool data +#endif // GSPI_MASTER_MISO <0=>P0_11 <1=>P0_26 <2=>P0_47 <3=>P0_56 // MISO of GSPI0 - +#ifndef GSPI_MASTER_MISO_LOC #define RTE_GSPI_MASTER_MISO_PORT_ID 1 #if (RTE_GSPI_MASTER_MISO_PORT_ID == 0) @@ -1845,6 +2896,25 @@ #else #error "Invalid GSPI0 RTE_GSPI_MASTER_MISO_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_GSPI_MASTER_MISO_PORT GSPI_MASTER_MISO__PORT +#define RTE_GSPI_MASTER_MISO_PIN GSPI_MASTER_MISO__PIN +#define RTE_GSPI_MASTER_MISO_MUX 4 +#if (GSPI_MASTER_MISO_LOC == 21) +#define RTE_GSPI_MASTER_MISO_PAD 6 +#endif +#if (GSPI_MASTER_MISO_LOC == 22) +#define RTE_GSPI_MASTER_MISO_PAD 0 +#endif +#if (GSPI_MASTER_MISO_LOC == 23) +#define RTE_GSPI_MASTER_MISO_PAD 11 +#endif +#if (GSPI_MASTER_MISO_LOC == 24) +#define RTE_GSPI_MASTER_MISO_PAD 20 +#endif +//Pintool data +#endif #if defined(HIGH_THROUGHPUT_EN) && (HIGH_THROUGHPUT_EN == ENABLE) #define RTE_GSPI_MASTER_CHNL_UDMA_TX_EN 1 @@ -1880,6 +2950,7 @@ //SCT_IN_0 <0=>GPIO_25 <1=>GPIO_64 <2=>GPIO_68 +#ifndef SCT_IN0_LOC #define RTE_SCT_IN_0_PORT_ID 0 #if (RTE_SCT_IN_0_PORT_ID == 0) @@ -1890,9 +2961,27 @@ #else #error "Invalid RTE_SCT_IN_0_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SCT_IN_0_PORT SCT_IN0_PORT +#if (SCT_IN0_LOC == 0) +#define RTE_SCT_IN_0_PIN SCT_IN0_PIN +#define RTE_SCT_IN_0_MUX 9 +#define RTE_SCT_IN_0_PAD 0 //no pad +#elif (SCT_IN0_LOC == 1) +#define RTE_SCT_IN_0_PIN (SCT_IN0_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_0_MUX 7 +#define RTE_SCT_IN_0_PAD 22 +#elif (SCT_IN0_LOC == 2) +#define RTE_SCT_IN_0_PIN (SCT_IN0_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_0_MUX 9 +#define RTE_SCT_IN_0_PAD 26 +#endif +//Pintool data +#endif //SCT_IN_1 <0=>GPIO_26 <1=>GPIO_65 <2=>GPIO_69 - +#ifndef SCT_IN1_LOC #define RTE_SCT_IN_1_PORT_ID 1 #if (RTE_SCT_IN_1_PORT_ID == 0) @@ -1908,9 +2997,29 @@ #else #error "Invalid RTE_SCT_IN_1_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SCT_IN_1_PORT SCT_IN1_PORT +#if (SCT_IN1_LOC == 3) +#define RTE_SCT_IN_1_PIN SCT_IN1_PIN +#define RTE_SCT_IN_1_MUX 9 +#define RTE_SCT_IN_1_PAD 0 //no pad +#endif +#if (SCT_IN1_LOC == 4) +#define RTE_SCT_IN_1_PIN (SCT_IN1_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_1_MUX 7 +#define RTE_SCT_IN_1_PAD 23 +#endif +#if (SCT_IN1_LOC == 5) +#define RTE_SCT_IN_1_PIN (SCT_IN1_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_1_MUX 9 +#define RTE_SCT_IN_1_PAD 27 +#endif +//Pintool data +#endif //SCT_IN_2 <0=>GPIO_27 <1=>GPIO_66 <2=>GPIO_70 - +#ifndef SCT_IN2_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SCT_IN_2_PORT_ID 0 #else @@ -1935,9 +3044,24 @@ #else #error "Invalid RTE_SCT_IN_0_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SCT_IN_2_PORT SCT_IN2_PORT +#if (SCT_IN2_LOC == 6) +#define RTE_SCT_IN_2_PIN SCT_IN2_PIN +#define RTE_SCT_IN_2_MUX 9 +#define RTE_SCT_IN_2_PAD 0 //no pad +#endif +#if (SCT_IN2_LOC == 7) +#define RTE_SCT_IN_2_PIN (SCT_IN2_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_2_MUX 9 +#define RTE_SCT_IN_2_PAD 28 +#endif +//Pintool data +#endif //SCT_IN_3 <0=>GPIO_28 <1=>GPIO_67 <2=>GPIO_71 - +#ifndef SCT_IN3_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SCT_IN_3_PORT_ID 0 #else @@ -1962,8 +3086,24 @@ #else #error "Invalid RTE_SCT_IN_0_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SCT_IN_3_PORT SCT_IN3_PORT +#if (SCT_IN3_LOC == 8) +#define RTE_SCT_IN_3_PIN SCT_IN3_PIN +#define RTE_SCT_IN_3_MUX 9 +#define RTE_SCT_IN_3_PAD 0 //no pad +#endif +#if (SCT_IN3_LOC == 9) +#define RTE_SCT_IN_3_PIN (SCT_IN3_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_3_MUX 9 +#define RTE_SCT_IN_3_PAD 29 +#endif +//Pintool data +#endif // SCT_OUT_0 <0=>GPIO_29 <1=>GPIO_68 +#ifndef SCT_OUT0_LOC #define RTE_SCT_OUT_0_PORT_ID 0 #if (RTE_SCT_OUT_0_PORT_ID == 0) #define RTE_SCT_OUT_0_PORT 0 @@ -1973,8 +3113,23 @@ #else #error "Invalid RTE_SCT_OUT_0_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SCT_OUT_0_PORT SCT_OUT0_PORT +#if (SCT_OUT0_LOC == 10) +#define RTE_SCT_OUT_0_PIN SCT_OUT0_PIN +#define RTE_SCT_OUT_0_MUX 9 +#define RTE_SCT_OUT_0_PAD 0 //no pad +#elif (SCT_OUT0_LOC == 11) +#define RTE_SCT_OUT_0_PIN (SCT_OUT0_PIN + GPIO_MAX_PIN) +#define RTE_SCT_OUT_0_MUX 7 +#define RTE_SCT_OUT_0_PAD 26 +#endif +//Pintool data +#endif // SCT_OUT_1 <0=>GPIO_30 <1=>GPIO_69 +#ifndef SCT_OUT1_LOC #define RTE_SCT_OUT_1_PORT_ID 0 #if (RTE_SCT_OUT_1_PORT_ID == 0) #define RTE_SCT_OUT_1_PORT 0 @@ -1984,117 +3139,67 @@ #else #error "Invalid RTE_SCT_OUT_1_PIN Pin Configuration!" #endif - -/// SCT_OUT_2 <0=>GPIO_70 <1=>GPIO_8 -#define RTE_SCT_OUT_2_PORT_ID 0 -#if ((RTE_SCT_OUT_2_PORT_ID == 1)) -#error "Invalid RTE_SCT_OUT_2_PIN pin Configuration!" +#else +//Pintool data +#define RTE_SCT_OUT_1_PORT SCT_OUT1_PORT +#if (SCT_OUT1_LOC == 12) +#define RTE_SCT_OUT_1_PIN SCT_OUT1_PIN +#define RTE_SCT_OUT_1_MUX 9 +#define RTE_SCT_OUT_1_PAD 0 //no pad +#elif (SCT_OUT1_LOC == 13) +#define RTE_SCT_OUT_1_PIN (SCT_OUT1_PIN + GPIO_MAX_PIN) +#define RTE_SCT_OUT_1_MUX 7 +#define RTE_SCT_OUT_1_PAD 27 +#endif +//Pintool data #endif -#if (RTE_SCT_OUT_2_PORT_ID == 0) -#define RTE_SCT_OUT_2_PORT 0 -#define RTE_SCT_OUT_2_PIN 70 +//Pintool data +#define RTE_SCT_OUT_2_PORT SCT_OUT2_PORT +#define RTE_SCT_OUT_2_PIN SCT_OUT2_PIN #define RTE_SCT_OUT_2_MUX 7 #define RTE_SCT_OUT_2_PAD 28 -#elif (RTE_SCT_OUT_2_PORT_ID == 1) -#define RTE_SCT_OUT_2_PORT 0 -#define RTE_SCT_OUT_2_PIN 8 -#define RTE_SCT_OUT_2_MUX 12 -#define RTE_SCT_OUT_2_PAD 3 -#else -#error "Invalid RTE_SCT_OUT_2_PIN Pin Configuration!" -#endif -/**/ -//SCT_OUT_3 <0=>GPIO_71 <1=>GPIO_9 -#define RTE_SCT_OUT_3_PORT_ID 0 -#if ((RTE_SCT_OUT_3_PORT_ID == 1)) -#error "Invalid RTE_SCT_OUT_3_PIN pin Configuration!" -#endif +//Pintool data -#if (RTE_SCT_OUT_3_PORT_ID == 0) -#define RTE_SCT_OUT_3_PORT 0 -#define RTE_SCT_OUT_3_PIN 71 +//Pintool data +#define RTE_SCT_OUT_3_PORT SCT_OUT3_PORT +#define RTE_SCT_OUT_3_PIN SCT_OUT3_PIN #define RTE_SCT_OUT_3_MUX 7 #define RTE_SCT_OUT_3_PAD 29 -#elif (RTE_SCT_OUT_3_PORT_ID == 1) -#define RTE_SCT_OUT_3_PORT 0 -#define RTE_SCT_OUT_3_PIN 9 -#define RTE_SCT_OUT_3_MUX 12 -#define RTE_SCT_OUT_3_PAD 4 -#else -#error "Invalid RTE_SCT_OUT_3_PIN Pin Configuration!" -#endif +//Pintool data -//SCT_OUT_4 <0=>GPIO_72 <1=>GPIO_68 - -#define RTE_SCT_OUT_4_PORT_ID 0 -#if ((RTE_SCT_OUT_4_PORT_ID == 1)) -#error "Invalid RTE_SCT_OUT_4_PIN pin Configuration!" -#endif - -#if (RTE_SCT_OUT_4_PORT_ID == 0) -/**/ -#define RTE_SCT_OUT_4_PORT 0 -#define RTE_SCT_OUT_4_PIN 72 +//Pintool data +#define RTE_SCT_OUT_4_PORT SCT_OUT4_PORT +#define RTE_SCT_OUT_4_PIN SCT_OUT4_PIN #define RTE_SCT_OUT_4_MUX 7 #define RTE_SCT_OUT_4_PAD 30 -#else -#error "Invalid RTE_SCT_OUT_4_PIN Pin Configuration!" -#endif -//SCT_OUT_5 <0=>GPIO_73 <1=>GPIO_69 - -#define RTE_SCT_OUT_5_PORT_ID 0 -#if ((RTE_SCT_OUT_5_PORT_ID == 1)) -#error "Invalid RTE_SCT_OUT_5_PIN pin Configuration!" -#endif +//Pintool data -#if (RTE_SCT_OUT_5_PORT_ID == 0) -#define RTE_SCT_OUT_5_PORT 2 -#define RTE_SCT_OUT_5_PIN 73 +//Pintool data +#define RTE_SCT_OUT_5_PORT SCT_OUT5_PORT +#define RTE_SCT_OUT_5_PIN SCT_OUT5_PIN #define RTE_SCT_OUT_5_MUX 7 #define RTE_SCT_OUT_5_PAD 31 -#else -#error "Invalid RTE_SCT_OUT_5_PIN Pin Configuration!" -#endif - -//SCT_OUT_6 <0=>GPIO_74 <1=>GPIO_70 +//Pintool data -#define RTE_SCT_OUT_6_PORT_ID 0 -#if ((RTE_SCT_OUT_6_PORT_ID == 1)) -#error "Invalid RTE_SCT_OUT_6_PIN pin Configuration!" -#endif - -#if (RTE_SCT_OUT_6_PORT_ID == 0) -#define RTE_SCT_OUT_6_PORT 0 -#define RTE_SCT_OUT_6_PIN 74 +//Pintool data +#define RTE_SCT_OUT_6_PORT SCT_OUT6_PORT +#define RTE_SCT_OUT_6_PIN SCT_OUT6_PIN #define RTE_SCT_OUT_6_MUX 7 #define RTE_SCT_OUT_6_PAD 32 -#elif (RTE_SCT_OUT_6_PORT_ID == 1) -#define RTE_SCT_OUT_6_PORT 0 -#define RTE_SCT_OUT_6_PIN 70 -#define RTE_SCT_OUT_6_MUX 13 -#define RTE_SCT_OUT_6_PAD 28 -#else -#error "Invalid RTE_SCT_OUT_6_PIN Pin Configuration!" -#endif - -// SCT_OUT_7 <0=>GPIO_75 <1=>GPIO_71 +//Pintool data -#define RTE_SCT_OUT_7_PORT_ID 0 - -#if (RTE_SCT_OUT_7_PORT_ID == 0) -#define RTE_SCT_OUT_7_PORT 0 -#define RTE_SCT_OUT_7_PIN 75 +//Pintool data +#define RTE_SCT_OUT_7_PORT SCT_OUT7_PORT +#define RTE_SCT_OUT_7_PIN SCT_OUT7_PIN #define RTE_SCT_OUT_7_MUX 7 #define RTE_SCT_OUT_7_PAD 33 -#else -#error "Invalid RTE_SCT_OUT_7_PIN Pin Configuration!" -#endif +//Pintool data // SIO // //<> Serial Input Output //SIO_0 <0=>GPIO_6 <1=>GPIO_25 <2=>GPIO_64 <3=>GPIO_72 - +#ifndef SIO_0_LOC #define RTE_SIO_0_PORT_ID 0 #if (RTE_SIO_0_PORT_ID == 0) @@ -2115,9 +3220,31 @@ #else #error "Invalid RTE_SIO_0_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_0_PORT SIO_SIO0_PORT +#define RTE_SIO_0_MUX 1 +#if (SIO_0_LOC == 0) +#define RTE_SIO_0_PIN SIO_SIO0_PIN +#define RTE_SIO_0_PAD 1 +#endif +#if (SIO_0_LOC == 1) +#define RTE_SIO_0_PIN SIO_SIO0_PIN +#define RTE_SIO_0_PAD 0 +#endif +#if (SIO_0_LOC == 2) +#define RTE_SIO_0_PIN (SIO_SIO0_PIN + GPIO_MAX_PIN) +#define RTE_SIO_0_PAD 22 +#endif +#if (SIO_0_LOC == 3) +#define RTE_SIO_0_PIN (SIO_SIO0_PIN + GPIO_MAX_PIN) +#define RTE_SIO_0_PAD 30 +#endif +//Pintool data +#endif //SIO_1 <0=>GPIO_7 <1=>GPIO_26 <2=>GPIO_65 <3=>GPIO_73 - +#ifndef SIO_1_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SIO_1_PORT_ID 1 #else @@ -2147,9 +3274,31 @@ #else #error "Invalid RTE_SIO_1_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_1_PORT SIO_SIO1_PORT +#define RTE_SIO_1_MUX 1 +#if (SIO_1_LOC == 4) +#define RTE_SIO_1_PIN SIO_SIO1_PIN +#define RTE_SIO_1_PAD 2 +#endif +#if (SIO_1_LOC == 5) +#define RTE_SIO_1_PIN SIO_SIO1_PIN +#define RTE_SIO_1_PAD 0 +#endif +#if (SIO_1_LOC == 6) +#define RTE_SIO_1_PIN (SIO_SIO1_PIN + GPIO_MAX_PIN) +#define RTE_SIO_1_PAD 23 +#endif +#if (SIO_1_LOC == 7) +#define RTE_SIO_1_PIN (SIO_SIO1_PIN + GPIO_MAX_PIN) +#define RTE_SIO_1_PAD 31 +#endif +//Pintool data +#endif // SIO_2 <0=>GPIO_8 <1=>GPIO_27 <2=>GPIO_66 <3=>GPIO_74 - +#ifndef SIO_2_LOC #define RTE_SIO_2_PORT_ID 1 #if (RTE_SIO_2_PORT_ID == 0) @@ -2175,9 +3324,27 @@ #else #error "Invalid RTE_SIO_2_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_2_PORT SIO_SIO2_PORT +#define RTE_SIO_2_MUX 1 +#if (SIO_2_LOC == 8) +#define RTE_SIO_2_PIN SIO_SIO2_PIN +#define RTE_SIO_2_PAD 3 +#endif +#if (SIO_2_LOC == 9) +#define RTE_SIO_2_PIN SIO_SIO2_PIN +#define RTE_SIO_2_PAD 0 +#endif +#if (SIO_2_LOC == 10) +#define RTE_SIO_2_PIN (SIO_SIO2_PIN + GPIO_MAX_PIN) +#define RTE_SIO_2_PAD 32 +#endif +//Pintool data +#endif //SIO_3 <0=>GPIO_9 <1=>GPIO_28 <2=>GPIO_67 <3=>GPIO_75 - +#ifndef SIO_3_LOC #define RTE_SIO_3_PORT_ID 1 #if (RTE_SIO_3_PORT_ID == 0) @@ -2203,8 +3370,27 @@ #else #error "Invalid RTE_SIO_3_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_3_PORT SIO_SIO3_PORT +#define RTE_SIO_3_MUX 1 +#if (SIO_3_LOC == 11) +#define RTE_SIO_3_PIN SIO_SIO3_PIN +#define RTE_SIO_3_PAD 4 +#endif +#if (SIO_3_LOC == 12) +#define RTE_SIO_3_PIN SIO_SIO3_PIN +#define RTE_SIO_3_PAD 0 +#endif +#if (SIO_3_LOC == 13) +#define RTE_SIO_3_PIN (SIO_SIO3_PIN + GPIO_MAX_PIN) +#define RTE_SIO_3_PAD 33 +#endif +//Pintool data +#endif //SIO_4 <0=>GPIO_10 <1=>GPIO_29 <2=>GPIO_68 +#ifndef SIO_4_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SIO_4_PORT_ID 1 #else @@ -2223,8 +3409,27 @@ #else #error "Invalid RTE_SIO_3_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_4_PORT SIO_SIO4_PORT +#define RTE_SIO_4_MUX 1 +#if (SIO_4_LOC == 14) +#define RTE_SIO_4_PAD 5 +#define RTE_SIO_4_PIN SIO_SIO4_PIN +#endif +#if (SIO_4_LOC == 15) +#define RTE_SIO_4_PAD 0 +#define RTE_SIO_4_PIN SIO_SIO4_PIN +#endif +#if (SIO_4_LOC == 16) +#define RTE_SIO_4_PAD 26 +#define RTE_SIO_4_PIN (SIO_SIO4_PIN + GPIO_MAX_PIN) +#endif +//Pintool data +#endif // SIO_5 <0=>GPIO_11 <1=>GPIO_30 <2=>GPIO_69 +#ifndef SIO_5_LOC #define RTE_SIO_5_PORT_ID 0 #if (RTE_SIO_5_PORT_ID == 0) #define RTE_SIO_5_PORT 0 @@ -2239,15 +3444,38 @@ #else #error "Invalid RTE_SIO_5_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_5_PORT SIO_SIO5_PORT +#define RTE_SIO_5_MUX 1 +#if (SIO_5_LOC == 17) +#define RTE_SIO_5_PAD 6 +#define RTE_SIO_5_PIN SIO_SIO5_PIN +#endif +#if (SIO_5_LOC == 18) +#define RTE_SIO_5_PAD 0 +#define RTE_SIO_5_PIN SIO_SIO5_PIN +#endif +#if (SIO_5_LOC == 19) +#define RTE_SIO_5_PAD 0 +#define RTE_SIO_5_PIN (SIO_SIO5_PIN + GPIO_MAX_PIN) +#endif +//Pintool data +#endif // SIO_6 GPIO_70 +#ifndef SIO_6_LOC #define RTE_SIO_6_PORT 0 #define RTE_SIO_6_PIN 70 -#define RTE_SIO_6_MUX 1 -#define RTE_SIO_6_PAD 28 +#else +#define RTE_SIO_6_PORT SIO_SIO6_PORT +#define RTE_SIO_6_PIN (SIO_SIO6_PIN + GPIO_MAX_PIN) +#endif +#define RTE_SIO_6_MUX 1 +#define RTE_SIO_6_PAD 28 // SIO_7 <0=>GPIO_15 <1=>GPIO_71 - +#ifndef SIO_7_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SIO_7_PORT_ID 1 #else @@ -2267,10 +3495,24 @@ #else #error "Invalid RTE_SIO_7_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_7_PORT SIO_SIO7_PORT +#define RTE_SIO_7_MUX 1 +#if (SIO_7_LOC == 21) +#define RTE_SIO_7_PIN SIO_SIO7_PIN +#define RTE_SIO_7_PAD 8 +#endif +#if (SIO_7_LOC == 22) +#define RTE_SIO_7_PIN (SIO_SIO7_PIN + GPIO_MAX_PIN) +#define RTE_SIO_7_PAD 29 +#endif +//Pintool data +#endif //<> Pulse Width Modulation //PWM_1H <0=>GPIO_7 <1=>GPIO_64 <2=>GPIO_65 - +#ifndef PWM_1H_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_PWM_1H_PORT_ID 0 #else @@ -2290,9 +3532,24 @@ #else #error "Invalid RTE_PWM_1H_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_1H_PORT PWM_1H_PORT +#if (PWM_1H_LOC == 0) +#define RTE_PWM_1H_PIN PWM_1H_PIN +#define RTE_PWM_1H_MUX 10 +#define RTE_PWM_1H_PAD 2 +#endif +#if (PWM_1H_LOC == 1) +#define RTE_PWM_1H_PIN (PWM_1H_PIN + GPIO_MAX_PIN) +#define RTE_PWM_1H_MUX 8 +#define RTE_PWM_1H_PAD 22 +#endif +//Pintool data +#endif // PWM_1L <0=>GPIO_6 <1=>GPIO_64 <2=>GPIO_64 - +#ifndef PWM_1L_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_PWM_1L_PORT_ID 0 #else @@ -2307,9 +3564,23 @@ #else #error "Invalid RTE_PWM_1L_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_1L_PORT PWM_1L_PORT +#if (PWM_1L_LOC == 2) +#define RTE_PWM_1L_PIN PWM_1L_PIN +#define RTE_PWM_1L_MUX 10 +#define RTE_PWM_1L_PAD 1 +#elif (PWM_1L_LOC == 3) +#define RTE_PWM_1L_PIN (PWM_1L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_1L_MUX 8 +#define RTE_PWM_1L_PAD 22 +#endif +//Pintool data +#endif //PWM_2H <0=>GPIO_9 <1=>GPIO_67 <2=>GPIO_69 - +#ifndef PWM_2H_LOC #define RTE_PWM_2H_PORT_ID 0 #if ((RTE_PWM_2H_PORT_ID == 2)) #error "Invalid RTE_PWM_2H_PIN pin Configuration!" @@ -2328,9 +3599,24 @@ #else #error "Invalid RTE_PWM_2H_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_2H_PORT PWM_2H_PORT +#if (PWM_2H_LOC == 4) +#define RTE_PWM_2H_PIN PWM_2H_PIN +#define RTE_PWM_2H_MUX 10 +#define RTE_PWM_2H_PAD 4 +#endif +#if (PWM_2H_LOC == 5) +#define RTE_PWM_2H_PIN (PWM_2H_PIN + GPIO_MAX_PIN) +#define RTE_PWM_2H_MUX 12 +#define RTE_PWM_2H_PAD 27 +#endif +//Pintool data +#endif // PWM_2L <0=>GPIO_8 <1=>GPIO_66 <2=>GPIO_68 - +#ifndef PWM_2L_LOC #define RTE_PWM_2L_PORT_ID 0 #if ((RTE_PWM_2L_PORT_ID == 2)) #error "Invalid RTE_PWM_2L_PIN pin Configuration!" @@ -2349,8 +3635,29 @@ #else #error "Invalid RTE_PWM_2L_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_2L_PORT PWM_2L_PORT +#if (PWM_2L_LOC == 6) +#define RTE_PWM_2L_PIN PWM_2L_PIN +#define RTE_PWM_2L_MUX 10 +#define RTE_PWM_2L_PAD 3 +#endif +#if (PWM_2L_LOC == 7) +#define RTE_PWM_2L_PIN (PWM_2L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_2L_MUX 8 +#define RTE_PWM_2L_PAD 24 +#endif +#if (PWM_2L_LOC == 8) +#define RTE_PWM_2L_PIN (PWM_2L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_2L_MUX 12 +#define RTE_PWM_2L_PAD 26 +#endif +//Pintool data +#endif // PWM_3H <0=>GPIO_11 <1=>GPIO_69 +#ifndef PWM_3H_LOC #define RTE_PWM_3H_PORT_ID 0 #if (RTE_PWM_3H_PORT_ID == 0) #define RTE_PWM_3H_PORT 0 @@ -2360,8 +3667,23 @@ #else #error "Invalid RTE_PWM_3H_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_3H_PORT PWM_3H_PORT +#if (PWM_3H_LOC == 9) +#define RTE_PWM_3H_PIN PWM_3H_PIN +#define RTE_PWM_3H_MUX 10 +#define RTE_PWM_3H_PAD 6 +#elif (PWM_3H_LOC == 10) +#define RTE_PWM_3H_PIN (PWM_3H_PIN + GPIO_MAX_PIN) +#define RTE_PWM_3H_MUX 8 +#define RTE_PWM_3H_PAD 27 +#endif +//Pintool data +#endif // PWM_3L <0=>GPIO_10 <1=>GPIO_68 +#ifndef PWM_3L_LOC #define RTE_PWM_3L_PORT_ID 0 #if (RTE_PWM_3L_PORT_ID == 0) @@ -2372,9 +3694,23 @@ #else #error "Invalid RTE_PWM_3L_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_3L_PORT PWM_3L_PORT +#if (PWM_3L_LOC == 11) +#define RTE_PWM_3L_PIN PWM_3L_PIN +#define RTE_PWM_3L_MUX 10 +#define RTE_PWM_3L_PAD 5 +#elif (PWM_3L_LOC == 12) +#define RTE_PWM_3L_PIN (PWM_3L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_3L_MUX 8 +#define RTE_PWM_3L_PAD 26 +#endif +//Pintool data +#endif // PWM_4H <0=>GPIO_15 <1=>GPIO_71 - +#ifndef PWM_4H_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_PWM_4H_PORT_ID 1 #else @@ -2394,9 +3730,17 @@ #else #error "Invalid RTE_PWM_4H_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_4H_PORT PWM_4H_PORT +#define RTE_PWM_4H_PIN (PWM_4H_PIN + GPIO_MAX_PIN) +#define RTE_PWM_4H_MUX 8 +#define RTE_PWM_4H_PAD 29 +//Pintool data +#endif // PWM_4H <0=>GPIO_12 <1=>GPIO_70 - +#ifndef PWM_4L_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_PWM_4L_PORT_ID 1 #else @@ -2416,8 +3760,24 @@ #else #error "Invalid RTE_PWM_4L_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_4L_PORT PWM_4L_PORT +#if (PWM_4L_LOC == 14) +#define RTE_PWM_4L_PIN PWM_4L_PIN +#define RTE_PWM_4L_MUX 10 +#define RTE_PWM_4L_PAD 7 +#endif +#if (PWM_4L_LOC == 15) +#define RTE_PWM_4L_PIN (PWM_4L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_4L_MUX 8 +#define RTE_PWM_4L_PAD 28 +#endif +//Pintool data +#endif // PWM_FAULTA <0=>GPIO_25 <1=>GPIO_68 <1=>GPIO_73 +#ifndef PWM_FAULTA_LOC #define RTE_PWM_FAULTA_PORT_ID 0 #if (RTE_PWM_FAULTA_PORT_ID == 0) @@ -2433,8 +3793,29 @@ #else #error "Invalid RTE_PWM_FAULTA_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_FAULTA_PORT PWM_FAULTA_PORT +#if (PWM_FAULTA_LOC == 16) +#define RTE_PWM_FAULTA_PIN PWM_FAULTA_PIN +#define RTE_PWM_FAULTA_MUX 10 +#define RTE_PWM_FAULTA_PAD 0 //no pad +#endif +#if (PWM_FAULTA_LOC == 17) +#define RTE_PWM_FAULTA_PIN (PWM_FAULTA_PIN + GPIO_MAX_PIN) +#define RTE_PWM_FAULTA_MUX 10 +#define RTE_PWM_FAULTA_PAD 26 +#endif +#if (PWM_FAULTA_LOC == 18) +#define RTE_PWM_FAULTA_PIN (PWM_FAULTA_PIN + GPIO_MAX_PIN) +#define RTE_PWM_FAULTA_MUX 8 +#define RTE_PWM_FAULTA_PAD 31 +#endif +//Pintool data +#endif // PWM_FAULTB <0=>GPIO_26 <1=>GPIO_69 <1=>GPIO_74 +#ifndef PWM_FAULTB_LOC #define RTE_PWM_FAULTB_PORT_ID 0 #if (RTE_PWM_FAULTB_PORT_ID == 0) @@ -2450,13 +3831,42 @@ #else #error "Invalid RTE_PWM_FAULTB_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_FAULTB_PORT PWM_FAULTB_PORT +#if (PWM_FAULTB_LOC == 19) +#define RTE_PWM_FAULTB_PIN PWM_FAULTB_PIN +#define RTE_PWM_FAULTB_MUX 10 +#define RTE_PWM_FAULTB_PAD 0 //no pad +#endif +#if (PWM_FAULTB_LOC == 20) +#define RTE_PWM_FAULTB_PIN (PWM_FAULTB_PIN + GPIO_MAX_PIN) +#define RTE_PWM_FAULTB_MUX 10 +#define RTE_PWM_FAULTB_PAD 27 +#endif +#if (PWM_FAULTB_LOC == 21) +#define RTE_PWM_FAULTB_PIN (PWM_FAULTB_PIN + GPIO_MAX_PIN) +#define RTE_PWM_FAULTB_MUX 8 +#define RTE_PWM_FAULTB_PAD 32 +#endif +//Pintool data +#endif + //PWM_SLP_EVENT_TRIG GPIO_72 +#ifndef PWM_EVTTRIG_LOC #define RTE_PWM_SLP_EVENT_TRIG_PORT 0 #define RTE_PWM_SLP_EVENT_TRIG_PIN 72 -#define RTE_PWM_SLP_EVENT_TRIG_MUX 8 -#define RTE_PWM_SLP_EVENT_TRIG_PAD 30 +#else +//Pintool data +#define RTE_PWM_SLP_EVENT_TRIG_PORT PWM_SLEEP_EVT_TRIG_PORT +#define RTE_PWM_SLP_EVENT_TRIG_PIN (PWM_SLEEP_EVT_TRIG_PIN + GPIO_MAX_PIN) +//Pintool data +#endif +#define RTE_PWM_SLP_EVENT_TRIG_MUX 8 +#define RTE_PWM_SLP_EVENT_TRIG_PAD 30 //PWM_TMR_EXT_TRIG_1 <0=>GPIO_27 <1=>GPIO_51 <2=>GPIO_70 <3=>GPIO_75 +#ifndef PWM_EXTTRIG1_LOC #define RTE_PWM_TMR_EXT_TRIG_1_PORT_ID 0 #if (RTE_PWM_TMR_EXT_TRIG_1_PORT_ID == 0) @@ -2482,8 +3892,34 @@ #else #error "Invalid RTE_PWM_TMR_EXT_TRIG_1_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_TMR_EXT_TRIG_1_PORT PWM_TMR_EXT_TRIG_1_PORT +#if (PWM_EXTTRIG1_LOC == 22) +#define RTE_PWM_TMR_EXT_TRIG_1_PIN PWM_TMR_EXT_TRIG_1_PIN +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 0 //no pad +#endif +#if (PWM_EXTTRIG1_LOC == 23) +#define RTE_PWM_TMR_EXT_TRIG_1_PIN PWM_TMR_EXT_TRIG_1_PIN +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 15 +#endif +#if (PWM_EXTTRIG1_LOC == 24) +#define RTE_PWM_TMR_EXT_TRIG_1_PIN (PWM_TMR_EXT_TRIG_1_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 28 +#endif +#if (PWM_EXTTRIG1_LOC == 25) +#define RTE_PWM_TMR_EXT_TRIG_1_PIN (PWM_TMR_EXT_TRIG_1_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 33 +#endif +//Pintool data +#endif //PWM_TMR_EXT_TRIG_2 <0=>GPIO_28 <1=>GPIO_54 <2=>GPIO_71 +#ifndef PWM_EXTTRIG2_LOC #define RTE_PWM_TMR_EXT_TRIG_2_PORT_ID 0 #if (RTE_PWM_TMR_EXT_TRIG_2_PORT_ID == 0) @@ -2504,6 +3940,71 @@ #else #error "Invalid RTE_PWM_TMR_EXT_TRIG_2_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_TMR_EXT_TRIG_2_PORT PWM_TMR_EXT_TRIG_2_PORT +#if (PWM_EXTTRIG2_LOC == 26) +#define RTE_PWM_TMR_EXT_TRIG_2_PIN PWM_TMR_EXT_TRIG_2_PIN +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 0 //no pad +#endif +#if (PWM_EXTTRIG2_LOC == 27) +#define RTE_PWM_TMR_EXT_TRIG_2_PIN PWM_TMR_EXT_TRIG_2_PIN +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 18 +#endif +#if (PWM_EXTTRIG2_LOC == 28) //Combination not available in pin mux +#define RTE_PWM_TMR_EXT_TRIG_2_PIN (PWM_TMR_EXT_TRIG_2_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 29 +#endif +#if (PWM_EXTTRIG2_LOC == 29) +#define RTE_PWM_TMR_EXT_TRIG_2_PIN (PWM_TMR_EXT_TRIG_2_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 29 +#endif +//Pintool data +#endif + +//PWM_TMR_EXT_TRIG_3 +//Pintool data +#define RTE_PWM_TMR_EXT_TRIG_3_PORT PWM_TMR_EXT_TRIG_3_PORT +#if (PWM_EXTTRIG3_LOC == 30) +#define RTE_PWM_TMR_EXT_TRIG_3_PIN PWM_TMR_EXT_TRIG_3_PIN +#define RTE_PWM_TMR_EXT_TRIG_3_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_3_PAD 0 //no pad +#endif +#if (PWM_EXTTRIG3_LOC == 31) +#define RTE_PWM_TMR_EXT_TRIG_3_PIN PWM_TMR_EXT_TRIG_3_PIN +#define RTE_PWM_TMR_EXT_TRIG_3_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_3_PAD 19 +#endif +#if (PWM_EXTTRIG3_LOC == 32) +#define RTE_PWM_TMR_EXT_TRIG_3_PIN (PWM_TMR_EXT_TRIG_3_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_3_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_3_PAD 30 +#endif +//Pintool data + +//PWM_TMR_EXT_TRIG_4 +//Pintool data +#define RTE_PWM_TMR_EXT_TRIG_4_PORT PWM_TMR_EXT_TRIG_4_PORT +#if (PWM_EXTTRIG4_LOC == 33) +#define RTE_PWM_TMR_EXT_TRIG_4_PIN PWM_TMR_EXT_TRIG_4_PIN +#define RTE_PWM_TMR_EXT_TRIG_4_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_4_PAD 0 //no pad +#endif +#if (PWM_EXTTRIG4_LOC == 34) +#define RTE_PWM_TMR_EXT_TRIG_4_PIN PWM_TMR_EXT_TRIG_4_PIN +#define RTE_PWM_TMR_EXT_TRIG_4_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_4_PAD 14 +#endif +#if (PWM_EXTTRIG4_LOC == 35) +#define RTE_PWM_TMR_EXT_TRIG_4_PIN (PWM_TMR_EXT_TRIG_4_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_4_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_4_PAD 31 +#endif +//Pintool data //<> QEI (Quadrature Encode Interface) @@ -2654,6 +4155,339 @@ #endif +//ADC START + +#ifndef ADC_P0_LOC +#define RTE_ADC_P0_PORT 0 +#define RTE_ADC_P0_PIN 0 +#else +#define RTE_ADC_P0_PORT ADC_P0_PORT +#define RTE_ADC_P0_PIN ADC_P0_PIN +#endif +#define RTE_ADC_P0_MUX 1 + +#ifndef ADC_N0_LOC +#define RTE_ADC_N0_PORT 0 +#define RTE_ADC_N0_PIN 1 +#else +#define RTE_ADC_N0_PORT ADC_N0_PORT +#define RTE_ADC_N0_PIN ADC_N0_PIN +#endif +#define RTE_ADC_N0_MUX 1 + +#ifndef ADC_P1_LOC +#define RTE_ADC_P1_PORT 0 +#define RTE_ADC_P1_PIN 2 +#else +#define RTE_ADC_P1_PORT ADC_P1_PORT +#define RTE_ADC_P1_PIN ADC_P1_PIN +#endif +#define RTE_ADC_P1_MUX 1 + +#ifndef ADC_N1_LOC +#define RTE_ADC_N1_PORT 0 +#define RTE_ADC_N1_PIN 3 +#else +#define RTE_ADC_N1_PORT ADC_N1_PORT +#define RTE_ADC_N1_PIN ADC_N1_PIN +#endif +#define RTE_ADC_N1_MUX 1 + +#ifndef ADC_P2_LOC +#define RTE_ADC_P2_PORT 0 +#define RTE_ADC_P2_PIN 4 +#else +#define RTE_ADC_P2_PORT ADC_P2_PORT +#define RTE_ADC_P2_PIN ADC_P2_PIN +#endif +#define RTE_ADC_P2_MUX 1 + +#ifndef ADC_N2_LOC +#define RTE_ADC_N2_PORT 0 +#define RTE_ADC_N2_PIN 5 +#else +#define RTE_ADC_N2_PORT ADC_N2_PORT +#define RTE_ADC_N2_PIN ADC_N2_PIN +#endif +#define RTE_ADC_N2_MUX 1 + +#ifndef ADC_P3_LOC +#define RTE_ADC_P3_PORT 0 +#define RTE_ADC_P3_PIN 6 +#else +#define RTE_ADC_P3_PORT ADC_P3_PORT +#define RTE_ADC_P3_PIN ADC_P3_PIN +#endif +#define RTE_ADC_P3_MUX 1 + +#ifndef ADC_N3_LOC +#define RTE_ADC_N3_PORT 0 +#define RTE_ADC_N3_PIN 11 +#else +#define RTE_ADC_N3_PORT ADC_N3_PORT +#define RTE_ADC_N3_PIN ADC_N3_PIN +#endif +#define RTE_ADC_N3_MUX 1 + +#ifndef ADC_P4_LOC +#define RTE_ADC_P4_PORT 0 +#define RTE_ADC_P4_PIN 8 +#else +#define RTE_ADC_P4_PORT ADC_P4_PORT +#define RTE_ADC_P4_PIN ADC_P4_PIN +#endif +#define RTE_ADC_P4_MUX 1 + +#ifndef ADC_N4_LOC +#define RTE_ADC_N4_PORT 0 +#define RTE_ADC_N4_PIN 9 +#else +#define RTE_ADC_N4_PORT ADC_N4_PORT +#define RTE_ADC_N4_PIN ADC_N4_PIN +#endif +#define RTE_ADC_N4_MUX 1 + +#ifndef ADC_P5_LOC +#define RTE_ADC_P5_PORT 0 +#define RTE_ADC_P5_PIN 10 +#else +#define RTE_ADC_P5_PORT ADC_P5_PORT +#define RTE_ADC_P5_PIN ADC_P5_PIN +#endif +#define RTE_ADC_P5_MUX 1 + +#ifndef ADC_N5_LOC +#define RTE_ADC_N5_PORT 0 +#define RTE_ADC_N5_PIN 7 +#else +#define RTE_ADC_N5_PORT ADC_N5_PORT +#define RTE_ADC_N5_PIN ADC_N5_PIN +#endif +#define RTE_ADC_N5_MUX 1 + +#ifndef ADC_P6_LOC +#define RTE_ADC_P6_PORT 0 +#define RTE_ADC_P6_PIN 25 +#else +#define RTE_ADC_P6_PORT ADC_P6_PORT +#define RTE_ADC_P6_PIN ADC_P6_PIN +#endif +#define RTE_ADC_P6_MUX 1 +#define RTE_ADC_P6_PAD 0 + +#ifndef ADC_N6_LOC +#define RTE_ADC_N6_PORT 0 +#define RTE_ADC_N6_PIN 26 +#else +#define RTE_ADC_N6_PORT ADC_N6_PORT +#define RTE_ADC_N6_PIN ADC_N6_PIN +#endif +#define RTE_ADC_N6_MUX 1 +#define RTE_ADC_N6_PAD 0 + +#ifndef ADC_P7_LOC +#define RTE_ADC_P7_PORT 0 +#define RTE_ADC_P7_PIN 27 +#else +#define RTE_ADC_P7_PORT ADC_P7_PORT +#define RTE_ADC_P7_PIN ADC_P7_PIN +#endif +#define RTE_ADC_P7_MUX 1 +#define RTE_ADC_P7_PAD 0 + +#ifndef ADC_N7_LOC +#define RTE_ADC_N7_PORT 0 +#define RTE_ADC_N7_PIN 28 +#else +#define RTE_ADC_N7_PORT ADC_N7_PORT +#define RTE_ADC_N7_PIN ADC_N7_PIN +#endif +#define RTE_ADC_N7_MUX 1 +#define RTE_ADC_N7_PAD 0 + +#ifndef ADC_P8_LOC +#define RTE_ADC_P8_PORT 0 +#define RTE_ADC_P8_PIN 29 +#else +#define RTE_ADC_P8_PORT ADC_P8_PORT +#define RTE_ADC_P8_PIN ADC_P8_PIN +#endif +#define RTE_ADC_P8_MUX 1 +#define RTE_ADC_P8_PAD 0 + +#ifndef ADC_N8_LOC +#define RTE_ADC_N8_PORT 0 +#define RTE_ADC_N8_PIN 30 +#else +#define RTE_ADC_N8_PORT ADC_N8_PORT +#define RTE_ADC_N8_PIN ADC_N8_PIN +#endif +#define RTE_ADC_N8_MUX 1 +#define RTE_ADC_N8_PAD 0 + +#ifndef ADC_P10_LOC +#define RTE_ADC_P10_PORT 0 +#define RTE_ADC_P10_PIN 1 +#else +#define RTE_ADC_P10_PORT ADC_P10_PORT +#define RTE_ADC_P10_PIN ADC_P10_PIN +#endif +#define RTE_ADC_P10_MUX 1 + +#ifndef ADC_P11_LOC +#define RTE_ADC_P11_PORT 0 +#define RTE_ADC_P11_PIN 3 +#else +#define RTE_ADC_P11_PORT ADC_P11_PORT +#define RTE_ADC_P11_PIN ADC_P11_PIN +#endif +#define RTE_ADC_P11_MUX 1 + +#ifndef ADC_P12_LOC +#define RTE_ADC_P12_PORT 0 +#define RTE_ADC_P12_PIN 5 +#else +#define RTE_ADC_P12_PORT ADC_P12_PORT +#define RTE_ADC_P12_PIN ADC_P12_PIN +#endif +#define RTE_ADC_P12_MUX 1 + +#ifndef ADC_P13_LOC +#define RTE_ADC_P13_PORT 0 +#define RTE_ADC_P13_PIN 11 +#else +#define RTE_ADC_P13_PORT ADC_P13_PORT +#define RTE_ADC_P13_PIN ADC_P13_PIN +#endif +#define RTE_ADC_P13_MUX 1 + +#ifndef ADC_P14_LOC +#define RTE_ADC_P14_PORT 0 +#define RTE_ADC_P14_PIN 9 +#else +#define RTE_ADC_P14_PORT ADC_P14_PORT +#define RTE_ADC_P14_PIN ADC_P14_PIN +#endif +#define RTE_ADC_P14_MUX 1 + +#ifndef ADC_P15_LOC +#define RTE_ADC_P15_PORT 0 +#define RTE_ADC_P15_PIN 7 +#else +#define RTE_ADC_P15_PORT ADC_P15_PORT +#define RTE_ADC_P15_PIN ADC_P15_PIN +#endif +#define RTE_ADC_P15_MUX 1 + +#ifndef ADC_P16_LOC +#define RTE_ADC_P16_PORT 0 +#define RTE_ADC_P16_PIN 26 +#else +#define RTE_ADC_P16_PORT ADC_P16_PORT +#define RTE_ADC_P16_PIN ADC_P16_PIN +#endif +#define RTE_ADC_P16_MUX 1 +#define RTE_ADC_P16_PAD 0 + +#ifndef ADC_P17_LOC +#define RTE_ADC_P17_PORT 0 +#define RTE_ADC_P17_PIN 28 +#else +#define RTE_ADC_P17_PORT ADC_P17_PORT +#define RTE_ADC_P17_PIN ADC_P17_PIN +#endif +#define RTE_ADC_P17_MUX 1 +#define RTE_ADC_P17_PAD 0 + +#ifndef ADC_P18_LOC +#define RTE_ADC_P18_PORT 0 +#define RTE_ADC_P18_PIN 30 +#else +#define RTE_ADC_P18_PORT ADC_P18_PORT +#define RTE_ADC_P18_PIN ADC_P18_PIN +#endif +#define RTE_ADC_P18_MUX 1 +#define RTE_ADC_P18_PAD 0 + +//ADC END + +//COMPARATOR START + +#ifndef COMP1_P0_LOC +#define RTE_COMP1_P0_PORT 0 +#define RTE_COMP1_P0_PIN 0 +#else +#define RTE_COMP1_P0_PORT COMP1_P0_PORT +#define RTE_COMP1_P0_PIN COMP1_P0_PIN +#endif +#define RTE_COMP1_P0_MUX 0 + +#ifndef COMP1_N0_LOC +#define RTE_COMP1_N0_PORT 0 +#define RTE_COMP1_N0_PIN 1 +#else +#define RTE_COMP1_N0_PORT COMP1_N0_PORT +#define RTE_COMP1_N0_PIN COMP1_N0_PIN +#endif +#define RTE_COMP1_N0_MUX 0 + +#ifndef COMP1_P1_LOC +#define RTE_COMP1_P1_PORT 0 +#define RTE_COMP1_P1_PIN 5 +#else +#define RTE_COMP1_P1_PORT COMP1_P1_PORT +#define RTE_COMP1_P1_PIN COMP1_P1_PIN +#endif +#define RTE_COMP1_P1_MUX 0 + +#ifndef COMP1_N1_LOC +#define RTE_COMP1_N1_PORT 0 +#define RTE_COMP1_N1_PIN 4 +#else +#define RTE_COMP1_N1_PORT COMP1_N1_PORT +#define RTE_COMP1_N1_PIN COMP1_N1_PIN +#endif +#define RTE_COMP1_N1_MUX 0 + +#ifndef COMP2_P0_LOC +#define RTE_COMP2_P0_PORT 0 +#define RTE_COMP2_P0_PIN 2 +#else +#define RTE_COMP2_P0_PORT COMP2_P0_PORT +#define RTE_COMP2_P0_PIN COMP2_P0_PIN +#endif +#define RTE_COMP2_P0_MUX 0 + +#ifndef COMP2_N0_LOC +#define RTE_COMP2_N0_PORT 0 +#define RTE_COMP2_N0_PIN 3 +#else +#define RTE_COMP2_N0_PORT COMP2_N0_PORT +#define RTE_COMP2_N0_PIN COMP2_N0_PIN +#endif +#define RTE_COMP2_N0_MUX 0 + +#ifndef COMP2_P1_LOC +#define RTE_COMP2_P1_PORT 0 +#define RTE_COMP2_P1_PIN 27 +#else +#define RTE_COMP2_P1_PORT COMP2_P1_PORT +#define RTE_COMP2_P1_PIN COMP2_P1_PIN +#endif +#define RTE_COMP2_P1_MUX 0 +#define RTE_COMP2_P1_PAD 0 + +#ifndef COMP2_N1_LOC +#define RTE_COMP2_N1_PORT 0 +#define RTE_COMP2_N1_PIN 28 +#else +#define RTE_COMP2_N1_PORT COMP2_N1_PORT +#define RTE_COMP2_N1_PIN COMP2_N1_PIN +#endif +#define RTE_COMP2_N1_MUX 0 + +//COMPARATOR END + #define RTE_GPIO_6_PORT 0 #define RTE_GPIO_6_PAD 1 #define RTE_GPIO_6_PIN 6 @@ -3053,3 +4887,13 @@ // UULP GPIO as enable pin for sensors #define SENSOR_ENABLE_GPIO_MAPPED_TO_UULP #define SENSOR_ENABLE_GPIO_PIN RTE_UULP_GPIO_1_PIN + +// Memlcd GPIOs +#define RTE_MEMLCD_CS_PIN 10 // Memlcd SPI CS pin +#define RTE_MEMLCD_CS_PORT 0 // Memlcd SPI CS port + +#define RTE_MEMLCD_EXTCOMIN_PIN 3 // Memlcd external communication pin +#define RTE_MEMLCD_EXTCOMIN_PORT 0 // Memlcd external communication port + +#define RTE_MEMLCD_ENABLE_DISPLAY_PIN 0 // Memlcd display enable pin +#define RTE_MEMLCD_ENABLE_DISPLAY_PORT 0 // Memlcd display enable port diff --git a/components/board/silabs/config/brd4340b/pin_config.h b/components/board/silabs/config/brd4340b/pin_config.h new file mode 100644 index 000000000..2bbc8c59c --- /dev/null +++ b/components/board/silabs/config/brd4340b/pin_config.h @@ -0,0 +1,140 @@ +#ifndef PIN_CONFIG_H +#define PIN_CONFIG_H + +// $[USART0] +// [USART0]$ + +// $[UART1] +// [UART1]$ + +// $[ULP_UART] +// [ULP_UART]$ + +// $[I2C0] +// [I2C0]$ + +// $[I2C1] +// [I2C1]$ + +// $[ULP_I2C] +// [ULP_I2C]$ + +// $[SSI_MASTER] +// [SSI_MASTER]$ + +// $[SSI_SLAVE] +// [SSI_SLAVE]$ + +// $[ULP_SPI] +// [ULP_SPI]$ + +// $[GSPI_MASTER] +// [GSPI_MASTER]$ + +// $[I2S0] +// [I2S0]$ + +// $[ULP_I2S] +// [ULP_I2S]$ + +// $[SCT] +// [SCT]$ + +// $[SIO] +// [SIO]$ + +// $[PWM] +// [PWM]$ + +// $[PWM_CH0] +// [PWM_CH0]$ + +// $[PWM_CH1] +// [PWM_CH1]$ + +// $[PWM_CH2] +// [PWM_CH2]$ + +// $[PWM_CH3] +// [PWM_CH3]$ + +// $[ADC_CH1] +// [ADC_CH1]$ + +// $[ADC_CH2] +// [ADC_CH2]$ + +// $[ADC_CH3] +// [ADC_CH3]$ + +// $[ADC_CH4] +// [ADC_CH4]$ + +// $[ADC_CH5] +// [ADC_CH5]$ + +// $[ADC_CH6] +// [ADC_CH6]$ + +// $[ADC_CH7] +// [ADC_CH7]$ + +// $[ADC_CH8] +// [ADC_CH8]$ + +// $[ADC_CH9] +// [ADC_CH9]$ + +// $[ADC_CH10] +// [ADC_CH10]$ + +// $[ADC_CH11] +// [ADC_CH11]$ + +// $[ADC_CH12] +// [ADC_CH12]$ + +// $[ADC_CH13] +// [ADC_CH13]$ + +// $[ADC_CH14] +// [ADC_CH14]$ + +// $[ADC_CH15] +// [ADC_CH15]$ + +// $[ADC_CH16] +// [ADC_CH16]$ + +// $[ADC_CH17] +// [ADC_CH17]$ + +// $[ADC_CH18] +// [ADC_CH18]$ + +// $[ADC_CH19] +// [ADC_CH19]$ + +// $[COMP1] +// [COMP1]$ + +// $[COMP2] +// [COMP2]$ + +// $[DAC0] +// [DAC0]$ + +// $[DAC1] +// [DAC1]$ + +// $[CUSTOM_PIN_NAME] +#ifndef _PORT +#define _PORT 0 +#endif +#ifndef _PIN +#define _PIN 6 +#endif + +// [CUSTOM_PIN_NAME]$ + +#endif // PIN_CONFIG_H diff --git a/components/board/silabs/config/brd4341a/RTE_Device_917.h b/components/board/silabs/config/brd4341a/RTE_Device_917.h index 7ffed5f92..e06201447 100644 --- a/components/board/silabs/config/brd4341a/RTE_Device_917.h +++ b/components/board/silabs/config/brd4341a/RTE_Device_917.h @@ -30,13 +30,33 @@ #include "rsi_ccp_user_config.h" #define BUTTON_0_GPIO_PIN 2 + +#define RTE_BUTTON0_PORT 0 +#define RTE_BUTTON0_NUMBER 0 +#define RTE_BUTTON0_PIN (2U) + +#define RTE_BUTTON1_PORT 0 +#define RTE_BUTTON1_NUMBER 1 +#define RTE_BUTTON1_PIN (11U) +#define RTE_BUTTON1_PAD 6 + +#define RTE_LED0_PORT 0 +#define RTE_LED0_NUMBER 0 +#define RTE_LED0_PIN (2U) + +#define RTE_LED1_PORT 0 +#define RTE_LED1_NUMBER 1 +#define RTE_LED1_PIN (10U) +#define BOARD_ACTIVITY_LED (2U) // LED0 +#define RTE_LED1_PAD 5 + // USART0 [Driver_USART0] // Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART #define RTE_ENABLE_FIFO 1 #define RTE_USART0 1 -#define RTE_USART0_CLK_SRC USART_INTFPLLCLK +#define RTE_USART0_CLK_SRC USART_ULPREFCLK #define RTE_USART0_CLK_DIV_FACT 1 #define RTE_USART0_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER @@ -54,14 +74,13 @@ #define RTE_USART0_DMA_TX_LEN_PER_DES 1024 #define RTE_USART0_DMA_RX_LEN_PER_DES 1024 -#define RTE_USART0_CHNL_UDMA_TX_EN 0 #define RTE_USART0_CHNL_UDMA_TX_CH 25 -#define RTE_USART0_CHNL_UDMA_RX_EN 0 #define RTE_USART0_CHNL_UDMA_RX_CH 24 // USART0_CLK <0=>P0_8 <1=>P0_25 <2=>P0_52 <3=>P0_64 // CLK of USART0 +#ifndef USART0_CLK_LOC #define RTE_USART0_CLK_PORT_ID 0 #if (RTE_USART0_CLK_PORT_ID == 0) @@ -82,10 +101,35 @@ #else #error "Invalid USART0 RTE_USART0_CLK_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_CLK_PORT USART0_CLK_PORT +#if (USART0_CLK_LOC == 0) +#define RTE_USART0_CLK_PIN USART0_CLK_PIN +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 3 +#endif +#if (USART0_CLK_LOC == 1) +#define RTE_USART0_CLK_PIN USART0_CLK_PIN +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 0 //NO PAD +#endif +#if (USART0_CLK_LOC == 2) +#define RTE_USART0_CLK_PIN USART0_CLK_PIN +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 16 +#endif +#if (USART0_CLK_LOC == 3) +#define RTE_USART0_CLK_PIN (USART0_CLK_PIN + GPIO_MAX_PIN) +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 22 +#endif +//Pintool data +#endif // USART0_TX <0=>P0_15 <1=>P0_30 <2=>P0_54 <3=>P0_68 <4=>P0_71 // TX for USART0 - +#ifndef USART0_TX_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_USART0_TX_PORT_ID 1 #else @@ -115,10 +159,40 @@ #else #error "Invalid USART0 RTE_USART0_TX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_TX_PORT USART0_TX_PORT +#if (USART0_TX_LOC == 4) +#define RTE_USART0_TX_PIN USART0_TX_PIN +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 8 +#endif +#if (USART0_TX_LOC == 5) +#define RTE_USART0_TX_PIN USART0_TX_PIN +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 0 //NO PAD +#endif +#if (USART0_TX_LOC == 6) +#define RTE_USART0_TX_PIN USART0_TX_PIN +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 18 +#endif +#if (USART0_TX_LOC == 7) +#define RTE_USART0_TX_PIN (USART0_TX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 26 +#endif +#if (USART0_TX_LOC == 8) +#define RTE_USART0_TX_PIN (USART0_TX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_TX_MUX 4 +#define RTE_USART0_TX_PAD 29 +#endif +//Pintool data +#endif // USART0_RX <0=>P0_10 <1=>P0_29 <2=>P0_55 <3=>P0_65 <4=>P0_70 // RX for USART0 - +#ifndef USART0_RX_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_USART0_RX_PORT_ID 1 #else @@ -144,7 +218,7 @@ #define RTE_USART0_RX_PORT 0 #define RTE_USART0_RX_PIN 65 #define RTE_USART0_RX_MUX 2 -#define RTE_USART0_RX_PAD 24 +#define RTE_USART0_RX_PAD 23 #elif (RTE_USART0_RX_PORT_ID == 4) #define RTE_USART0_RX_PORT 0 #define RTE_USART0_RX_PIN 70 @@ -153,9 +227,40 @@ #else #error "Invalid USART0 RTE_USART0_RX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_RX_PORT USART0_RX_PORT +#if (USART0_RX_LOC == 9) +#define RTE_USART0_RX_PIN USART0_RX_PIN +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 5 +#endif +#if (USART0_RX_LOC == 10) +#define RTE_USART0_RX_PIN USART0_RX_PIN +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 0 //no pad +#endif +#if (USART0_RX_LOC == 11) +#define RTE_USART0_RX_PIN USART0_RX_PIN +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 19 +#endif +#if (USART0_RX_LOC == 12) +#define RTE_USART0_RX_PIN (USART0_RX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 23 +#endif +#if (USART0_RX_LOC == 13) +#define RTE_USART0_RX_PIN (USART0_RX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_RX_MUX 4 +#define RTE_USART0_RX_PAD 28 +#endif +//Pintool data +#endif // USART0_CTS <0=>P0_6 <1=>P0_26 <2=>P0_56 <3=>P0_70 // CTS for USART0 +#ifndef USART0_CTS_LOC #define RTE_USART0_CTS_PORT_ID 0 #if (RTE_USART0_CTS_PORT_ID == 0) @@ -181,9 +286,35 @@ #else #error "Invalid USART0 RTE_USART0_CTS_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_CTS_PORT USART0_CTS_PORT +#if (USART0_CTS_LOC == 14) +#define RTE_USART0_CTS_PIN USART0_CTS_PIN +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 1 +#endif +#if (USART0_CTS_LOC == 15) +#define RTE_USART0_CTS_PIN USART0_CTS_PIN +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 0 //NO PAD +#endif +#if (USART0_CTS_LOC == 16) +#define RTE_USART0_CTS_PIN USART0_CTS_PIN +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 20 +#endif +#if (USART0_CTS_LOC == 17) +#define RTE_USART0_CTS_PIN (USART0_CTS_PIN + GPIO_MAX_PIN) +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 28 +#endif +//Pintool data +#endif // USART0_RTS <0=>P0_9 <1=>P0_28 <2=>P0_53 <3=>P0_69 // RTS for USART0 +#ifndef USART0_RTS_LOC #define RTE_USART0_RTS_PORT_ID 0 #if (RTE_USART0_RTS_PORT_ID == 0) @@ -204,10 +335,35 @@ #else #error "Invalid USART0 RTE_USART0_RTS_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_RTS_PORT USART0_RTS_PORT +#if (USART0_RTS_LOC == 18) +#define RTE_USART0_RTS_PIN USART0_RTS_PIN +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 4 +#endif +#if (USART0_RTS_LOC == 19) +#define RTE_USART0_RTS_PIN USART0_RTS_PIN +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 0 //NO PAD +#endif +#if (USART0_RTS_LOC == 20) +#define RTE_USART0_RTS_PIN USART0_RTS_PIN +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 17 +#endif +#if (USART0_RTS_LOC == 21) +#define RTE_USART0_RTS_PIN (USART0_RTS_PIN + GPIO_MAX_PIN) +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 27 +#endif +//Pintool data +#endif // USART0_IR_TX <0=>P0_48 <1=>P0_72 // IR TX for USART0 - +#ifndef USART0_IRTX_LOC #define RTE_IR_TX_PORT_ID 0 #if ((RTE_IR_TX_PORT_ID == 2)) #error "Invalid USART0 RTE_USART0_IR_TX_PIN Pin Configuration!" @@ -231,10 +387,35 @@ #else #error "Invalid USART0 RTE_USART0_IR_TX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_IR_TX_PORT USART0_IRTX_PORT +#if (USART0_IRTX_LOC == 22) +#define RTE_USART0_IR_TX_PIN USART0_IRTX_PIN +#define RTE_USART0_IR_TX_MUX 13 +#define RTE_USART0_IR_TX_PAD 0 //No pad +#endif +#if (USART0_IRTX_LOC == 23) +#define RTE_USART0_IR_TX_PIN USART0_IRTX_PIN +#define RTE_USART0_IR_TX_MUX 2 +#define RTE_USART0_IR_TX_PAD 12 +#endif +#if (USART0_IRTX_LOC == 24) +#define RTE_USART0_IR_TX_PIN (USART0_IRTX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_IR_TX_MUX 11 +#define RTE_USART0_IR_TX_PAD 23 +#endif +#if (USART0_IRTX_LOC == 25) +#define RTE_USART0_IR_TX_PIN (USART0_IRTX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_IR_TX_MUX 2 +#define RTE_USART0_IR_TX_PAD 30 +#endif +//Pintool data +#endif // USART0_IR_RX <0=>P0_47 <1=>P0_71 <2=>P0_64 <3=>P0_25 // IR RX for USART0 - +#ifndef USART0_IRRX_LOC #define RTE_IR_RX_PORT_ID 0 #if ((RTE_IR_RX_PORT_ID == 2)) #error "Invalid USART0 RTE_USART0_IR_RX_PIN Pin Configuration!" @@ -258,9 +439,35 @@ #else #error "Invalid USART0 RTE_USART0_IR_RX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_IR_RX_PORT USART0_IRRX_PORT +#if (USART0_IRRX_LOC == 26) +#define RTE_USART0_IR_RX_PIN USART0_IRRX_PIN +#define RTE_USART0_IR_RX_MUX 13 +#define RTE_USART0_IR_RX_PAD 0 //no pad +#endif +#if (USART0_IRRX_LOC == 27) +#define RTE_USART0_IR_RX_PIN USART0_IRRX_PIN +#define RTE_USART0_IR_RX_MUX 2 +#define RTE_USART0_IR_RX_PAD 11 +#endif +#if (USART0_IRRX_LOC == 28) +#define RTE_USART0_IR_RX_PIN (USART0_IRRX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_IR_RX_MUX 11 +#define RTE_USART0_IR_RX_PAD 22 +#endif +#if (USART0_IRRX_LOC == 29) +#define RTE_USART0_IR_RX_PIN (USART0_IRRX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_IR_RX_MUX 2 +#define RTE_USART0_IR_RX_PAD 29 +#endif +//Pintool data +#endif // USART0_RI <0=>P0_27 <1=>P0_46 <2=>P0_68 // RI for USART0 +#ifndef USART0_RI_LOC #define RTE_RI_PORT_ID 0 #if (RTE_RI_PORT_ID == 0) @@ -276,9 +483,30 @@ #else #error "Invalid USART0 RTE_USART0_RI_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_RI_PORT USART0_RI_PORT +#if (USART0_RI_LOC == 30) +#define RTE_USART0_RI_PIN USART0_RI_PIN +#define RTE_USART0_RI_MUX 2 +#define RTE_USART0_RI_PAD 0 //no pad +#endif +#if (USART0_RI_LOC == 31) +#define RTE_USART0_RI_PIN USART0_RI_PIN +#define RTE_USART0_RI_MUX 2 +#define RTE_USART0_RI_PAD 10 +#endif +#if (USART0_RI_LOC == 32) +#define RTE_USART0_RI_PIN (USART0_RI_PIN + GPIO_MAX_PIN) +#define RTE_USART0_RI_MUX 11 +#define RTE_USART0_RI_PAD 26 +#endif +//Pintool data +#endif // USART0_DSR <0=>P0_11 <1=>P0_57 // DSR for USART0 +#ifndef USART0_DSR_LOC #define RTE_DSR_PORT_ID 0 #if (RTE_DSR_PORT_ID == 0) @@ -294,27 +522,56 @@ #else #error "Invalid USART0 RTE_USART0_RI_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_DSR_PORT USART0_DSR_PORT +#define RTE_USART0_DSR_PIN USART0_DSR_PIN +#if (USART0_DSR_LOC == 33) +#define RTE_USART0_DSR_MUX 2 +#define RTE_USART0_DSR_PAD 6 +#endif +#if (USART0_DSR_LOC == 34) +#define RTE_USART0_DSR_MUX 2 +#define RTE_USART0_DSR_PAD 21 +#endif +//Pintool data +#endif + // USART0_DCD <0=>P0_12 <1=>P0_29 // DCD for USART0 - +#ifndef USART0_DCD_LOC #define RTE_USART0_DCD_PORT 0 #define RTE_USART0_DCD_PIN 12 -#define RTE_USART0_DCD_MUX 2 -#define RTE_USART0_DCD_PAD 7 +#else +#define RTE_USART0_DCD_PORT USART0_DCD_PORT +#define RTE_USART0_DCD_PIN USART0_DCD_PIN +#if (USART0_DCD_LOC == 35) +#define RTE_USART0_DCD_MUX 2 +#define RTE_USART0_DCD_PAD 7 +#elif (USART0_DCD_LOC == 36) +#define RTE_USART0_DCD_MUX 12 +#define RTE_USART0_DCD_PAD 0 +#endif +#endif // USART0_DTR <0=>P0_7 // DTR for USART0 +#ifndef USART0_DTR_LOC #define RTE_USART0_DTR_PORT 0 #define RTE_USART0_DTR_PIN 7 -#define RTE_USART0_DTR_MUX 2 -#define RTE_USART0_DTR_PAD 2 +#else +#define RTE_USART0_DTR_PORT USART0_DTR_PORT +#define RTE_USART0_DTR_PIN USART0_DTR_PIN +#endif +#define RTE_USART0_DTR_MUX 2 +#define RTE_USART0_DTR_PAD 2 // // UART1 [Driver_UART1] // Configuration settings for Driver_UART1 in component ::CMSIS Driver:USART #define RTE_UART1 1 -#define RTE_UART1_CLK_SRC USART_INTFPLLCLK +#define RTE_UART1_CLK_SRC USART_ULPREFCLK #define RTE_UART1_CLK_DIV_FACT 1 #define RTE_UART1_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER @@ -327,16 +584,14 @@ #define RTE_UART1_DMA_TX_LEN_PER_DES 1024 #define RTE_UART1_DMA_RX_LEN_PER_DES 1024 -#define RTE_UART1_CHNL_UDMA_TX_EN 0 #define RTE_UART1_CHNL_UDMA_TX_CH 27 -#define RTE_UART1_CHNL_UDMA_RX_EN 0 #define RTE_UART1_CHNL_UDMA_RX_CH 26 /*UART1 PINS*/ // UART1_TX <0=>P0_7 <1=>P0_30 <2=>P0_67 <3=>P0_69 <4=>P0_73 <5=>P0_75 <6=>P0_34 // TX of UART1 - +#ifndef UART1_TX_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_UART1_TX_PORT_ID 0 #else @@ -375,10 +630,40 @@ #else #error "Invalid UART1 RTE_UART1_TX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_UART1_TX_PORT UART1_TX_PORT +#if (UART1_TX_LOC == 0) +#define RTE_UART1_TX_PIN UART1_TX_PIN +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 2 +#endif +#if (UART1_TX_LOC == 1) +#define RTE_UART1_TX_PIN UART1_TX_PIN +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 0 //no pad +#endif +#if (UART1_TX_LOC == 2) +#define RTE_UART1_TX_PIN (UART1_TX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 27 +#endif +#if (UART1_TX_LOC == 3) +#define RTE_UART1_TX_PIN (UART1_TX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 31 +#endif +#if (UART1_TX_LOC == 4) +#define RTE_UART1_TX_PIN (UART1_TX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_TX_MUX 9 +#define RTE_UART1_TX_PAD 33 +#endif +//Pintool data +#endif // UART1_RX <0=>P0_6 <1=>P0_29 <2=>P0_66 <3=>P0_68 <4=>P0_72 <5=>P0_74 <6=>P0_33 // RX of UART1 - +#ifndef UART1_RX_LOC #define RTE_UART1_RX_PORT_ID 0 #if (RTE_UART1_RX_PORT_ID == 0) @@ -409,9 +694,40 @@ #else #error "Invalid UART1 RTE_UART1_RX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_UART1_RX_PORT UART1_RX_PORT +#if (UART1_RX_LOC == 5) +#define RTE_UART1_RX_PIN UART1_RX_PIN +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 1 +#endif +#if (UART1_RX_LOC == 6) +#define RTE_UART1_RX_PIN UART1_RX_PIN +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 0 //no pad +#endif +#if (UART1_RX_LOC == 7) +#define RTE_UART1_RX_PIN (UART1_RX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 26 +#endif +#if (UART1_RX_LOC == 8) +#define RTE_UART1_RX_PIN (UART1_RX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 30 +#endif +#if (UART1_RX_LOC == 9) +#define RTE_UART1_RX_PIN (UART1_RX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RX_MUX 9 +#define RTE_UART1_RX_PAD 32 +#endif +//Pintool data +#endif // UART1_CTS <0=>P0_11 <1=>P0_28 <2=>P0_51 <3=>P0_65 <4=>P0_71 <5=>P0_73 <6=>P0_32 // CTS of UART1 +#ifndef UART1_CTS_LOC #define RTE_UART1_CTS_PORT_ID 0 #if (RTE_UART1_CTS_PORT_ID == 0) @@ -442,10 +758,45 @@ #else #error "Invalid UART1 RTE_UART1_CTS_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_UART1_CTS_PORT UART1_CTS_PORT +#if (UART1_CTS_LOC == 10) +#define RTE_UART1_CTS_PIN UART1_CTS_PIN +#define RTE_UART1_CTS_MUX 6 +#define RTE_UART1_CTS_PAD 6 +#endif +#if (UART1_CTS_LOC == 11) +#define RTE_UART1_CTS_PIN UART1_CTS_PIN +#define RTE_UART1_CTS_MUX 6 +#define RTE_UART1_CTS_PAD 0 //no pad +#endif +#if (UART1_CTS_LOC == 12) +#define RTE_UART1_CTS_PIN UART1_CTS_PIN +#define RTE_UART1_CTS_MUX 9 +#define RTE_UART1_CTS_PAD 15 +#endif +#if (UART1_CTS_LOC == 13) +#define RTE_UART1_CTS_PIN (UART1_CTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_CTS_MUX 9 +#define RTE_UART1_CTS_PAD 23 +#endif +#if (UART1_CTS_LOC == 14) +#define RTE_UART1_CTS_PIN (UART1_CTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_CTS_MUX 6 +#define RTE_UART1_CTS_PAD 29 +#endif +#if (UART1_CTS_LOC == 15) +#define RTE_UART1_CTS_PIN (UART1_CTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_CTS_MUX 9 +#define RTE_UART1_CTS_PAD 31 +#endif +//Pintool data +#endif // UART1_RTS <0=>P0_10 <1=>P0_27 <2=>P0_50 <3=>P0_64 <4=>P0_70 <5=>P0_72 <6=>P0_31 // RTS of UART1 - +#ifndef UART1_RTS_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_UART1_RTS_PORT_ID 0 #else @@ -480,6 +831,42 @@ #else #error "Invalid UART1 RTE_UART1_RTS_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_UART1_RTS_PORT UART1_RTS_PORT +#if (UART1_RTS_LOC == 16) +#define RTE_UART1_RTS_PIN UART1_RTS_PIN +#define RTE_UART1_RTS_MUX 6 +#define RTE_UART1_RTS_PAD 5 +#endif +#if (UART1_RTS_LOC == 17) +#define RTE_UART1_RTS_PIN UART1_RTS_PIN +#define RTE_UART1_RTS_MUX 6 +#define RTE_UART1_RTS_PAD 0 //no pad +#endif +#if (UART1_RTS_LOC == 18) +#define RTE_UART1_RTS_PIN UART1_RTS_PIN +#define RTE_UART1_RTS_MUX 9 +#define RTE_UART1_RTS_PAD 14 +#endif +#if (UART1_RTS_LOC == 19) +#define RTE_UART1_RTS_PIN (UART1_RTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RTS_MUX 9 +#define RTE_UART1_RTS_PAD 22 +#endif +#if (UART1_RTS_LOC == 20) +#define RTE_UART1_RTS_PIN (UART1_RTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RTS_MUX 6 +#define RTE_UART1_RTS_PAD 28 +#endif +#if (UART1_RTS_LOC == 21) +#define RTE_UART1_RTS_PIN (UART1_RTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RTS_MUX 9 +#define RTE_UART1_RTS_PAD 30 +#endif +//Pintool data +#endif + // // ULP_UART [Driver_ULP_UART] @@ -499,15 +886,14 @@ #define RTE_ULP_UART_DMA_TX_LEN_PER_DES 1024 #define RTE_ULP_UART_DMA_RX_LEN_PER_DES 1024 -#define RTE_ULPUART_CHNL_UDMA_TX_EN 0 #define RTE_ULPUART_CHNL_UDMA_TX_CH 1 -#define RTE_ULPUART_CHNL_UDMA_RX_EN 0 #define RTE_ULPUART_CHNL_UDMA_RX_CH 0 /*ULPSS UART PINS*/ // UART1_TX <0=>P0_3 <1=>P0_7 <2=>P0_11 // TX of ULPSS UART +#ifndef ULP_UART_TX_LOC #define RTE_ULP_UART_TX_PORT_ID 1 #if (RTE_ULP_UART_TX_PORT_ID == 0) #define RTE_ULP_UART_TX_PORT 0 @@ -520,10 +906,18 @@ #else #error "Invalid ULPSS UART RTE_ULP_UART_TX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_ULP_UART_TX_PORT ULP_UART_TX_PORT +#define RTE_ULP_UART_TX_PIN ULP_UART_TX_PIN +#define RTE_ULP_UART_TX_MUX 3 +//Pintool data +#endif // UART1_RX <0=>P0_2 <1=>P0_6 <2=>P0_9 // RX of ULPSS UART -#define RTE_ULP_UART_RX_PORT_ID 0 +#ifndef ULP_UART_RX_LOC +#define RTE_ULP_UART_RX_PORT_ID 2 #if (RTE_ULP_UART_RX_PORT_ID == 0) #define RTE_ULP_UART_RX_PORT 0 #define RTE_ULP_UART_RX_PIN 2 @@ -539,9 +933,17 @@ #else #error "Invalid ULPSS UART RTE_ULP_UART_RX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_ULP_UART_RX_PORT ULP_UART_RX_PORT +#define RTE_ULP_UART_RX_PIN ULP_UART_RX_PIN +#define RTE_ULP_UART_RX_MUX 3 +//Pintool data +#endif // UART1_CTS <0=>P0_1 <1=>P0_5 <2=>P0_8 // CTS of ULPSS UART +#ifndef ULP_UART_CTS_LOC #define RTE_ULP_UART_CTS_PORT_ID 0 #if (RTE_ULP_UART_CTS_PORT_ID == 0) #define RTE_ULP_UART_CTS_PORT 0 @@ -554,17 +956,30 @@ #else #error "Invalid ULPSS UART RTE_ULP_UART_CTS_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_ULP_UART_CTS_PORT ULP_UART_CTS_PORT +#define RTE_ULP_UART_CTS_PIN ULP_UART_CTS_PIN +#define RTE_ULP_UART_CTS_MUX 3 +//Pintool data +#endif // UART1_RTS <0=>P0_0 <1=>P0_4 <2=>P0_10 // RTS of ULPSS UART +#ifndef ULP_UART_RTS_LOC #define RTE_ULP_UART_RTS_PORT_ID 0 #if (RTE_ULP_UART_RTS_PORT_ID == 0) #define RTE_ULP_UART_RTS_PORT 0 #define RTE_ULP_UART_RTS_PIN 10 -#define RTE_ULP_UART_RTS_MUX 8 #else #error "Invalid ULPSS UART RTE_ULP_UART_RTS_PIN Pin Configuration!" #endif +#else +#define RTE_ULP_UART_RTS_PORT ULP_UART_RTS_PORT +#define RTE_ULP_UART_RTS_PIN ULP_UART_RTS_PIN +#endif +#define RTE_ULP_UART_RTS_MUX 8 + // // SSI_MASTER (Serial Peripheral Interface 1) [Driver_SSI_MASTER] @@ -572,7 +987,7 @@ #define RTE_SSI_MASTER 1 // SSI_MASTER_MISO Pin <0=>GPIO_12 <1=>GPIO_27 <2=>GPIO_57 - +#ifndef SSI_MASTER_DATA1_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SSI_MASTER_MISO_PORT_ID 1 #else @@ -600,8 +1015,26 @@ #else #error "Invalid SSI_MASTER_MISO Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_MASTER_MISO 1 +#define RTE_SSI_MASTER_MISO_PORT SSI_MASTER_MISO_DATA1_PORT +#define RTE_SSI_MASTER_MISO_PIN SSI_MASTER_MISO_DATA1_PIN +#define RTE_SSI_MASTER_MISO_MODE EGPIO_PIN_MUX_MODE3 +#if (SSI_MASTER_DATA1_LOC == 3) +#define RTE_SSI_MASTER_MISO_PADSEL 7 +#endif +#if (SSI_MASTER_DATA1_LOC == 4) +#define RTE_SSI_MASTER_MISO_PADSEL 0 //NO PAD +#endif +#if (SSI_MASTER_DATA1_LOC == 5) +#define RTE_SSI_MASTER_MISO_PADSEL 21 +#endif +//Pintool data +#endif // SSI_MASTER_MOSI Pin <0=>GPIO_11 <1=>GPIO_26 <2=>GPIO_56 +#ifndef SSI_MASTER_DATA0_LOC #define RTE_SSI_MASTER_MOSI_PORT_ID 1 #if (RTE_SSI_MASTER_MOSI_PORT_ID == 0) @@ -625,8 +1058,26 @@ #else #error "Invalid SSI_MASTER_MOSI Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_MASTER_MOSI 1 +#define RTE_SSI_MASTER_MOSI_PORT SSI_MASTER_MOSI_DATA0_PORT +#define RTE_SSI_MASTER_MOSI_PIN SSI_MASTER_MOSI_DATA0_PIN +#define RTE_SSI_MASTER_MOSI_MODE EGPIO_PIN_MUX_MODE3 +#if (SSI_MASTER_DATA0_LOC == 0) +#define RTE_SSI_MASTER_MOSI_PADSEL 6 +#endif +#if (SSI_MASTER_DATA0_LOC == 1) +#define RTE_SSI_MASTER_MOSI_PADSEL 0 //NO PAD +#endif +#if (SSI_MASTER_DATA0_LOC == 2) +#define RTE_SSI_MASTER_MOSI_PADSEL 20 +#endif +//Pintool data +#endif // SSI_MASTER_SCK Pin <0=>GPIO_8 <1=>GPIO_25 <2=>GPIO_52 +#ifndef SSI_MASTER_SCK_LOC #define RTE_SSI_MASTER_SCK_PORT_ID 1 #if (RTE_SSI_MASTER_SCK_PORT_ID == 0) @@ -650,6 +1101,23 @@ #else #error "Invalid SSI_MASTER_SCK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_MASTER_SCK 1 +#define RTE_SSI_MASTER_SCK_PORT SSI_MASTER_SCK__PORT +#define RTE_SSI_MASTER_SCK_PIN SSI_MASTER_SCK__PIN +#define RTE_SSI_MASTER_SCK_MODE EGPIO_PIN_MUX_MODE3 +#if (SSI_MASTER_SCK_LOC == 6) +#define RTE_SSI_MASTER_SCK_PADSEL 3 +#endif +#if (SSI_MASTER_SCK_LOC == 7) +#define RTE_SSI_MASTER_SCK_PADSEL 0 //NO PAD +#endif +#if (SSI_MASTER_SCK_LOC == 8) +#define RTE_SSI_MASTER_SCK_PADSEL 16 +#endif +//Pintool data +#endif #define M4_SSI_CS0 1 #define M4_SSI_CS1 0 @@ -657,6 +1125,7 @@ #define M4_SSI_CS3 0 // SSI_MASTER_CS Pin <0=>GPIO_9 <1=>GPIO_28 <2=>GPIO_53 <3=>GPIO_10 <4=>GPIO_15 <5=>GPIO_50 <6=>GPIO_51 +#ifndef SSI_MASTER_CS0_LOC #define RTE_SSI_MASTER_CS0_PORT_ID 1 #if (RTE_SSI_MASTER_CS0_PORT_ID == 0) @@ -680,20 +1149,43 @@ #else #error "Invalid SSI_MASTER_CS0 Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_MASTER_CS0 M4_SSI_CS0 +#define RTE_SSI_MASTER_CS0_PORT SSI_MASTER_CS0__PORT +#define RTE_SSI_MASTER_CS0_PIN SSI_MASTER_CS0__PIN +#define RTE_SSI_MASTER_CS0_MODE EGPIO_PIN_MUX_MODE3 +#if (SSI_MASTER_CS0_LOC == 9) +#define RTE_SSI_MASTER_CS0_PADSEL 4 +#endif +#if (SSI_MASTER_CS0_LOC == 10) +#define RTE_SSI_MASTER_CS0_PADSEL 0 //NO PAD +#endif +#if (SSI_MASTER_CS0_LOC == 11) +#define RTE_SSI_MASTER_CS0_PADSEL 17 +#endif +//Pintool data +#endif //CS1 +#ifndef SSI_MASTER_CS1_LOC #define RTE_SSI_MASTER_CS1_PORT_ID 0 #if (RTE_SSI_MASTER_CS1_PORT_ID == 0) -#define RTE_SSI_MASTER_CS1 M4_SSI_CS1 -#define RTE_SSI_MASTER_CS1_PORT 0 -#define RTE_SSI_MASTER_CS1_PIN 10 -#define RTE_SSI_MASTER_CS1_MODE EGPIO_PIN_MUX_MODE3 -#define RTE_SSI_MASTER_CS1_PADSEL 5 +#define RTE_SSI_MASTER_CS1_PORT 0 +#define RTE_SSI_MASTER_CS1_PIN 10 #else #error "Invalid SSI_MASTER_CS1 Pin Configuration!" #endif +#else +#define RTE_SSI_MASTER_CS1_PORT SSI_MASTER_CS1__PORT +#define RTE_SSI_MASTER_CS1_PIN SSI_MASTER_CS1__PIN +#endif +#define RTE_SSI_MASTER_CS1 M4_SSI_CS1 +#define RTE_SSI_MASTER_CS1_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS1_PADSEL 5 //CS2 +#ifndef SSI_MASTER_CS2_LOC #define RTE_SSI_MASTER_CS2_PORT_ID 1 #if (RTE_SSI_MASTER_CS2_PORT_ID == 0) #define RTE_SSI_MASTER_CS2 M4_SSI_CS2 @@ -710,31 +1202,48 @@ #else #error "Invalid SSI_MASTER_CS2 Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_MASTER_CS2 M4_SSI_CS2 +#define RTE_SSI_MASTER_CS2_PORT SSI_MASTER_CS2__PORT +#define RTE_SSI_MASTER_CS2_PIN SSI_MASTER_CS2__PIN +#define RTE_SSI_MASTER_CS2_MODE EGPIO_PIN_MUX_MODE3 +#if (SSI_MASTER_CS2_LOC == 13) +#define RTE_SSI_MASTER_CS2_PADSEL 8 +#endif +#if (SSI_MASTER_CS2_LOC == 14) +#define RTE_SSI_MASTER_CS2_PADSEL 14 +#endif +//Pintool data +#endif //CS3 +#ifndef SSI_MASTER_CS3_LOC #define RTE_SSI_MASTER_CS3_PORT_ID 0 #if (RTE_SSI_MASTER_CS3_PORT_ID == 0) -#define RTE_SSI_MASTER_CS3 M4_SSI_CS3 -#define RTE_SSI_MASTER_CS3_PORT 0 -#define RTE_SSI_MASTER_CS3_PIN 51 -#define RTE_SSI_MASTER_CS3_MODE EGPIO_PIN_MUX_MODE3 -#define RTE_SSI_MASTER_CS3_PADSEL 15 +#define RTE_SSI_MASTER_CS3_PORT 0 +#define RTE_SSI_MASTER_CS3_PIN 51 #else #error "Invalid SSI_MASTER_CS3 Pin Configuration!" #endif +#else +#define RTE_SSI_MASTER_CS3_PORT SSI_MASTER_CS3__PORT +#define RTE_SSI_MASTER_CS3_PIN SSI_MASTER_CS3__PIN +#endif +#define RTE_SSI_MASTER_CS3 M4_SSI_CS3 +#define RTE_SSI_MASTER_CS3_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS3_PADSEL 15 // DMA Rx // Channel <28=>28 // Selects DMA Channel (only Channel 28 can be used) // -#define RTE_SSI_MASTER_RX_DMA 0 #define RTE_SSI_MASTER_UDMA_RX_CH 28 // DMA Tx // Channel <29=>29 // Selects DMA Channel (only Channel 29 can be used) // -#define RTE_SSI_MASTER_TX_DMA 0 #define RTE_SSI_MASTER_UDMA_TX_CH 29 // @@ -745,6 +1254,7 @@ #define RTE_SSI_SLAVE_INPUT_CLOCK SSISLAVE_CLK // SSI_SLAVE_MISO Pin <0=>Not Used <1=>GPIO_11 <2=>GPIO_28 <3=>GPIO_49 <4=>GPIO_57 +#ifndef SSI_SLAVE_MISO_LOC #define RTE_SSI_SLAVE_MISO_PORT_ID 2 #if (RTE_SSI_SLAVE_MISO_PORT_ID == 0) @@ -776,9 +1286,29 @@ #else #error "Invalid SSI_SLAVE_MISO Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_SLAVE_MISO 1 +#define RTE_SSI_SLAVE_MISO_PORT SSI_SLAVE_MISO__PORT +#define RTE_SSI_SLAVE_MISO_PIN SSI_SLAVE_MISO__PIN +#define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8 +#if (SSI_SLAVE_MISO_LOC == 5) +#define RTE_SSI_SLAVE_MISO_PADSEL 6 +#endif +#if (SSI_SLAVE_MISO_LOC == 6) +#define RTE_SSI_SLAVE_MISO_PADSEL 0 //no pad +#endif +#if (SSI_SLAVE_MISO_LOC == 7) +#define RTE_SSI_SLAVE_MISO_PADSEL 13 +#endif +#if (SSI_SLAVE_MISO_LOC == 8) +#define RTE_SSI_SLAVE_MISO_PADSEL 21 +#endif +//Pintool data +#endif // SSI_SLAVE_MOSI Pin <0=>Not Used <1=>GPIO_10 <2=>GPIO_27 <3=>GPIO_48 <4=>GPIO_56 - +#ifndef SSI_SLAVE_MOSI_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SSI_SLAVE_MOSI_PORT_ID 2 #else @@ -814,8 +1344,29 @@ #else #error "Invalid SSI_SLAVE_MOSI Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_SLAVE_MOSI 1 +#define RTE_SSI_SLAVE_MOSI_PORT SSI_SLAVE_MOSI__PORT +#define RTE_SSI_SLAVE_MOSI_PIN SSI_SLAVE_MOSI__PIN +#define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8 +#if (SSI_SLAVE_MOSI_LOC == 1) +#define RTE_SSI_SLAVE_MOSI_PADSEL 5 +#endif +#if (SSI_SLAVE_MOSI_LOC == 2) +#define RTE_SSI_SLAVE_MOSI_PADSEL 0 //no pad +#endif +#if (SSI_SLAVE_MOSI_LOC == 3) +#define RTE_SSI_SLAVE_MOSI_PADSEL 12 +#endif +#if (SSI_SLAVE_MOSI_LOC == 4) +#define RTE_SSI_SLAVE_MOSI_PADSEL 20 +#endif +//Pintool data +#endif // SSI_SLAVE_SCK Pin <0=>Not Used <1=>GPIO_8 <2=>GPIO_26 <3=>GPIO_47 <4=>GPIO_52 +#ifndef SSI_SLAVE_SCK_LOC #define RTE_SSI_SLAVE_SCK_PORT_ID 2 #if (RTE_SSI_SLAVE_SCK_PORT_ID == 0) @@ -847,8 +1398,29 @@ #else #error "Invalid SSI_SLAVE_SCK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_SLAVE_SCK 1 +#define RTE_SSI_SLAVE_SCK_PORT SSI_SLAVE_SCK__PORT +#define RTE_SSI_SLAVE_SCK_PIN SSI_SLAVE_SCK__PIN +#define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8 +#if (SSI_SLAVE_SCK_LOC == 9) +#define RTE_SSI_SLAVE_SCK_PADSEL 3 +#endif +#if (SSI_SLAVE_SCK_LOC == 10) +#define RTE_SSI_SLAVE_SCK_PADSEL 0 //no pad +#endif +#if (SSI_SLAVE_SCK_LOC == 11) +#define RTE_SSI_SLAVE_SCK_PADSEL 11 +#endif +#if (SSI_SLAVE_SCK_LOC == 12) +#define RTE_SSI_SLAVE_SCK_PADSEL 16 +#endif +//Pintool data +#endif // SSI_SLAVE_CS Pin <0=>Not Used <1=>GPIO_9 <2=>GPIO_25 <3=>GPIO_46 <4=>GPIO_53 +#ifndef SSI_SLAVE_CS0_LOC #define RTE_SSI_SLAVE_CS_PORT_ID 1 #if (RTE_SSI_SLAVE_CS_PORT_ID == 0) @@ -880,12 +1452,31 @@ #else #error "Invalid SSI_SLAVE_CS Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_SLAVE_CS 1 +#define RTE_SSI_SLAVE_CS_PORT SSI_SLAVE_CS0__PORT +#define RTE_SSI_SLAVE_CS_PIN SSI_SLAVE_CS0__PIN +#define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8 +#if (SSI_SLAVE_CS0_LOC == 13) +#define RTE_SSI_SLAVE_CS_PADSEL 4 +#endif +#if (SSI_SLAVE_CS0_LOC == 14) +#define RTE_SSI_SLAVE_CS_PADSEL 0 //no pad +#endif +#if (SSI_SLAVE_CS0_LOC == 15) +#define RTE_SSI_SLAVE_CS_PADSEL 10 +#endif +#if (SSI_SLAVE_CS0_LOC == 16) +#define RTE_SSI_SLAVE_CS_PADSEL 17 +#endif +//Pintool data +#endif // DMA Rx // Channel <22=>22 // Selects DMA Channel (only Channel 22 can be used) // -#define RTE_SSI_SLAVE_RX_DMA 0 #define RTE_SSI_SLAVE_UDMA_RX_CH 22 #define RTE_SSI_SLAVE_DMA_RX_LEN_PER_DES 1024 @@ -893,13 +1484,12 @@ // Channel <23=>23 // Selects DMA Channel (only Channel 23 can be used) // -#define RTE_SSI_SLAVE_TX_DMA 0 #define RTE_SSI_SLAVE_UDMA_TX_CH 23 #define RTE_SSI_SLAVE_DMA_TX_LEN_PER_DES 1024 // -// SSI_ULP_MASTER (Serial Peripheral Interface 3) [Driver_SSI_ULP_MASTER] +// ULP SPI Peripheral (Serial Peripheral Interface 3) [Driver_SSI_ULP_MASTER] // Configuration settings for Driver_SSI_ULP_MASTER in component ::CMSIS Driver:SPI #define RTE_SSI_ULP_MASTER 1 @@ -909,6 +1499,7 @@ #define ULP_SSI_CS2 0 // SSI_ULP_MASTER_MISO Pin <0=>Not Used <1=>ULP_GPIO_2 <2=>ULP_GPIO_9 +#ifndef ULP_SPI_MISO_LOC #define RTE_SSI_ULP_MASTER_MISO_PORT_ID 0 #if (RTE_SSI_ULP_MASTER_MISO_PORT_ID == 0) #define RTE_SSI_ULP_MASTER_MISO 1 @@ -923,8 +1514,17 @@ #else #error "Invalid SSI_ULP_MISO Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_ULP_MASTER_MISO 1 +#define RTE_SSI_ULP_MASTER_MISO_PORT ULP_SPI_MISO__PORT +#define RTE_SSI_ULP_MASTER_MISO_PIN ULP_SPI_MISO__PIN +#define RTE_SSI_ULP_MASTER_MISO_MODE 1 +//Pintool data +#endif // SSI_ULP_MASTER_MOSI Pin <0=>Not Used <1=>ULP_GPIO_1 <2=>ULP_GPIO_11 +#ifndef ULP_SPI_MOSI_LOC #define RTE_SSI_ULP_MASTER_MOSI_PORT_ID 0 #if (RTE_SSI_ULP_MASTER_MOSI_PORT_ID == 0) #define RTE_SSI_ULP_MASTER_MOSI 1 @@ -939,8 +1539,17 @@ #else #error "Invalid SSI_ULP_MOSI Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_ULP_MASTER_MOSI 1 +#define RTE_SSI_ULP_MASTER_MOSI_PORT ULP_SPI_MOSI__PORT +#define RTE_SSI_ULP_MASTER_MOSI_PIN ULP_SPI_MOSI__PIN +#define RTE_SSI_ULP_MASTER_MOSI_MODE 1 +//Pintool data +#endif // SSI_ULP_MASTER_SCK Pin <0=>Not Used <1=>ULP_GPIO_0 <2=>ULP_GPIO_8 +#ifndef ULP_SPI_SCK_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SSI_ULP_MASTER_SCK_PORT_ID 2 #else @@ -961,8 +1570,17 @@ #else #error "Invalid SSI_ULP_SCK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_ULP_MASTER_SCK 1 +#define RTE_SSI_ULP_MASTER_SCK_PORT ULP_SPI_SCK__PORT +#define RTE_SSI_ULP_MASTER_SCK_PIN ULP_SPI_SCK__PIN +#define RTE_SSI_ULP_MASTER_SCK_MODE 1 +//Pintool data +#endif // CS0 +#ifndef ULP_SPI_CS0_LOC #define RTE_SSI_ULP_MASTER_CS0_PORT_ID 1 #if (RTE_SSI_ULP_MASTER_CS0_PORT_ID == 0) #define RTE_SSI_ULP_MASTER_CS0 ULP_SSI_CS0 @@ -977,24 +1595,41 @@ #else #error "Change RTE_SSI_ULP_MASTER_CS_PORT_ID other than '1' or'3' as per PACKAGE_TYPE" #endif +#else +//Pintool data +#define RTE_SSI_ULP_MASTER_CS0 ULP_SSI_CS0 +#define RTE_SSI_ULP_MASTER_CS0_PORT ULP_SPI_CS0__PORT +#define RTE_SSI_ULP_MASTER_CS0_PIN ULP_SPI_CS0__PIN +#define RTE_SSI_ULP_MASTER_CS0_MODE 1 +//Pintool data +#endif // CS1 -#define RTE_SSI_ULP_MASTER_CS1 ULP_SSI_CS1 +#ifndef ULP_SPI_CS1_LOC #define RTE_SSI_ULP_MASTER_CS1_PORT 0 #define RTE_SSI_ULP_MASTER_CS1_PIN 4 +#else +#define RTE_SSI_ULP_MASTER_CS1_PORT ULP_SPI_CS1__PORT +#define RTE_SSI_ULP_MASTER_CS1_PIN ULP_SPI_CS1__PIN +#endif +#define RTE_SSI_ULP_MASTER_CS1 ULP_SSI_CS1 #define RTE_SSI_ULP_MASTER_CS1_MODE 1 // CS2 -#define RTE_SSI_ULP_MASTER_CS2 ULP_SSI_CS2 +#ifndef ULP_SPI_CS2_LOC #define RTE_SSI_ULP_MASTER_CS2_PORT 0 #define RTE_SSI_ULP_MASTER_CS2_PIN 6 +#else +#define RTE_SSI_ULP_MASTER_CS2_PORT ULP_SPI_CS2__PORT +#define RTE_SSI_ULP_MASTER_CS2_PIN ULP_SPI_CS2__PIN +#endif +#define RTE_SSI_ULP_MASTER_CS2 ULP_SSI_CS2 #define RTE_SSI_ULP_MASTER_CS2_MODE 1 // DMA Rx // Channel <2=>2 // Selects DMA Channel (only Channel 2 can be used) // -#define RTE_SSI_ULP_MASTER_RX_DMA 1 #define RTE_SSI_ULP_MASTER_UDMA_RX_CH 2 #define RTE_SSI_ULP_MASTER_DMA_RX_LEN_PER_DES 96 @@ -1002,7 +1637,6 @@ // Channel <3=>3 // Selects DMA Channel (only Channel 3 can be used) // -#define RTE_SSI_ULP_MASTER_TX_DMA 1 #define RTE_SSI_ULP_MASTER_UDMA_TX_CH 3 #define RTE_SSI_ULP_MASTER_DMA_TX_LEN_PER_DES 96 @@ -1033,7 +1667,7 @@ // RTE_UDMA1_BASE_MEM <0=>PS2 <1=>PS4 #define RTE_UDMA1_BASE_MEM 0 #if (RTE_UDMA1_BASE_MEM == 0) -#define UDMA1_SRAM_BASE 0x24060000 +#define UDMA1_SRAM_BASE 0x24061C00 #elif (RTE_UDMA1_BASE_MEM == 1) #define UDMA1_SRAM_BASE 0x1CC00 #else @@ -1050,6 +1684,7 @@ // I2S0_SCLK <0=>P0_8 <1=>P0_25 <2=>P0_46 <3=>P0_52 // SCLK of I2S0 +#ifndef I2S0_SCLK_LOC #define RTE_I2S0_SCLK_PORT_ID 1 #if (RTE_I2S0_SCLK_PORT_ID == 0) @@ -1075,9 +1710,29 @@ #else #error "Invalid I2S0 RTE_I2S0_SCLK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S0_SCLK_PORT I2S0_SCLK_PORT +#define RTE_I2S0_SCLK_PIN I2S0_SCLK_PIN +#define RTE_I2S0_SCLK_MUX 7 +#if (I2S0_SCLK_LOC == 0) +#define RTE_I2S0_SCLK_PAD 3 +#endif +#if (I2S0_SCLK_LOC == 1) +#define RTE_I2S0_SCLK_PAD 0 //no pad +#endif +#if (I2S0_SCLK_LOC == 2) +#define RTE_I2S0_SCLK_PAD 10 +#endif +#if (I2S0_SCLK_LOC == 3) +#define RTE_I2S0_SCLK_PAD 16 +#endif +//Pintool data +#endif // I2S0_WSCLK <0=>P0_9 <1=>P0_26 <2=>P0_47 <3=>P0_53 // WSCLK for I2S0 +#ifndef I2S0_WSCLK_LOC #define RTE_I2S0_WSCLK_PORT_ID 1 #if (RTE_I2S0_WSCLK_PORT_ID == 0) @@ -1103,9 +1758,29 @@ #else #error "Invalid I2S0 RTE_I2S0_WSCLK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S0_WSCLK_PORT I2S0_WSCLK_PORT +#define RTE_I2S0_WSCLK_PIN I2S0_WSCLK_PIN +#define RTE_I2S0_WSCLK_MUX 7 +#if (I2S0_WSCLK_LOC == 4) +#define RTE_I2S0_WSCLK_PAD 4 +#endif +#if (I2S0_WSCLK_LOC == 5) +#define RTE_I2S0_WSCLK_PAD 0 +#endif +#if (I2S0_WSCLK_LOC == 6) +#define RTE_I2S0_WSCLK_PAD 11 +#endif +#if (I2S0_WSCLK_LOC == 7) +#define RTE_I2S0_WSCLK_PAD 17 +#endif +//Pintool data +#endif // I2S0_DOUT0 <0=>P0_11 <1=>P0_28 <2=>P0_49 <3=>P0_57 // DOUT0 for I2S0 +#ifndef I2S0_DOUT0_LOC #define RTE_I2S0_DOUT0_PORT_ID 1 #if (RTE_I2S0_DOUT0_PORT_ID == 0) @@ -1131,9 +1806,29 @@ #else #error "Invalid I2S0 RTE_I2S0_DOUT0 Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S0_DOUT0_PORT I2S0_DOUT0_PORT +#define RTE_I2S0_DOUT0_PIN I2S0_DOUT0_PIN +#define RTE_I2S0_DOUT0_MUX 7 +#if (I2S0_DOUT0_LOC == 8) +#define RTE_I2S0_DOUT0_PAD 6 +#endif +#if (I2S0_DOUT0_LOC == 9) +#define RTE_I2S0_DOUT0_PAD 0 +#endif +#if (I2S0_DOUT0_LOC == 10) +#define RTE_I2S0_DOUT0_PAD 13 +#endif +#if (I2S0_DOUT0_LOC == 11) +#define RTE_I2S0_DOUT0_PAD 21 +#endif +//Pintool data +#endif // I2S0_DIN0 <0=>P0_10 <1=>P0_27 <2=>P0_48 <3=>P0_56 // DIN0 for I2S0 +#ifndef I2S0_DIN0_LOC #define RTE_I2S0_DIN0_PORT_ID 1 #if (RTE_I2S0_DIN0_PORT_ID == 0) @@ -1159,10 +1854,29 @@ #else #error "Invalid I2S0 RTE_I2S0_DIN0 Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S0_DIN0_PORT I2S0_DIN0_PORT +#define RTE_I2S0_DIN0_PIN I2S0_DIN0_PIN +#define RTE_I2S0_DIN0_MUX 7 +#if (I2S0_DIN0_LOC == 12) +#define RTE_I2S0_DIN0_PAD 5 +#endif +#if (I2S0_DIN0_LOC == 13) +#define RTE_I2S0_DIN0_PAD 0 +#endif +#if (I2S0_DIN0_LOC == 14) +#define RTE_I2S0_DIN0_PAD 12 +#endif +#if (I2S0_DIN0_LOC == 15) +#define RTE_I2S0_DIN0_PAD 20 +#endif +//Pintool data +#endif // I2S0_DOUT1 <0=>P0_7 <1=>P0_30 <2=>P0_51 <3=>P0_55 // DOUT1 for I2S0 - +#ifndef I2S0_DOUT1_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_I2S0_DOUT1_PORT_ID 1 #else @@ -1192,9 +1906,29 @@ #else #error "Invalid I2S0 RTE_I2S0_DOUT1 Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S0_DOUT1_PORT I2S0_DOUT1_PORT +#define RTE_I2S0_DOUT1_PIN I2S0_DOUT1_PIN +#define RTE_I2S0_DOUT1_MUX 7 +#if (I2S0_DOUT1_LOC == 16) +#define RTE_I2S0_DOUT1_PAD 2 +#endif +#if (I2S0_DOUT1_LOC == 17) +#define RTE_I2S0_DOUT1_PAD 0 +#endif +#if (I2S0_DOUT1_LOC == 18) +#define RTE_I2S0_DOUT1_PAD 15 +#endif +#if (I2S0_DOUT1_LOC == 19) +#define RTE_I2S0_DOUT1_PAD 19 +#endif +//Pintool data +#endif // I2S0_DIN1 <0=>P0_6 <1=>P0_29 <2=>P0_50 <3=>P0_54 // DIN1 for I2S0 +#ifndef I2S0_DIN1_LOC #define RTE_I2S0_DIN1_PORT_ID 0 #if (RTE_I2S0_DIN1_PORT_ID == 0) @@ -1220,8 +1954,27 @@ #else #error "Invalid I2S0 RTE_I2S0_DIN1 Pin Configuration!" #endif -// FIFO level can have value 1 to 7 -#define I2S0_TX_FIFO_LEVEL (2U) +#else +//Pintool data +#define RTE_I2S0_DIN1_PORT I2S0_DIN1_PORT +#define RTE_I2S0_DIN1_PIN I2S0_DIN1_PIN +#define RTE_I2S0_DIN1_MUX 7 +#if (I2S0_DIN1_LOC == 20) +#define RTE_I2S0_DIN1_PAD 1 +#endif +#if (I2S0_DIN1_LOC == 21) +#define RTE_I2S0_DIN1_PAD 0 +#endif +#if (I2S0_DIN1_LOC == 22) +#define RTE_I2S0_DIN1_PAD 14 +#endif +#if (I2S0_DIN1_LOC == 23) +#define RTE_I2S0_DIN1_PAD 18 +#endif +//Pintool data +#endif +// FIFO level can have value 0 to 7 +#define I2S0_TX_FIFO_LEVEL (0U) #define I2S0_RX_FIFO_LEVEL (2U) // I2S0_TX_RES <0=>12 @@ -1269,13 +2022,14 @@ // -// I2S1 [Driver_I2S1] +// ULP I2S [Driver_I2S1] // Configuration settings for Driver_I2S1 in component ::Drivers:I2S #define RTE_I2S1 1 #define I2S1_IRQHandler IRQ014_Handler // I2S1_SCLK Pin <0=>P0_3 <1=>P0_7 <2=>P0_8 /*I2S1 PINS*/ +#ifndef ULP_I2S_SCLK_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_I2S1_SCLK_PORT_ID 0 #else @@ -1296,8 +2050,16 @@ #else #error "Invalid I2S1 RTE_I2S1_SCLK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S1_SCLK_PORT ULP_I2S_SCLK_PORT +#define RTE_I2S1_SCLK_PIN ULP_I2S_SCLK_PIN +#define RTE_I2S1_SCLK_MUX 2 +//Pintool data +#endif // I2S1_WSCLK Pin <0=>P0_2 <1=>P0_4 <2=>P0_10 +#ifndef ULP_I2S_WSCLK_LOC #define RTE_I2S1_WSCLK_PORT_ID 0 #if (RTE_I2S1_WSCLK_PORT_ID == 0) #define RTE_I2S1_WSCLK_PORT 0 @@ -1310,8 +2072,16 @@ #else #error "Invalid I2S1 RTE_I2S1_WSCLK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S1_WSCLK_PORT ULP_I2S_WSCLK_PORT +#define RTE_I2S1_WSCLK_PIN ULP_I2S_WSCLK_PIN +#define RTE_I2S1_WSCLK_MUX 2 +//Pintool data +#endif // I2S1_DOUT0 Pin <0=>P0_1 <1=>P0_5 <2=>P0_11 +#ifndef ULP_I2S_DOUT0_LOC #define RTE_I2S1_DOUT0_PORT_ID 0 #if (RTE_I2S1_DOUT0_PORT_ID == 0) #define RTE_I2S1_DOUT0_PORT 0 @@ -1324,8 +2094,16 @@ #else #error "Invalid I2S1 RTE_I2S1_DOUT0 Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S1_DOUT0_PORT ULP_I2S_DOUT0_PORT +#define RTE_I2S1_DOUT0_PIN ULP_I2S_DOUT0_PIN +#define RTE_I2S1_DOUT0_MUX 2 +//Pintool data +#endif // I2S1_DIN0 Pin <0=>P0_0 <1=>P0_6 <2=>P0_9 <3=>P0_13 +#ifndef ULP_I2S_DIN0_LOC #define RTE_I2S1_DIN0_PORT_ID 1 #if (RTE_I2S1_DIN0_PORT_ID == 0) #define RTE_I2S1_DIN0_PORT 0 @@ -1342,9 +2120,16 @@ #else #error "Invalid I2S1 RTE_I2S1_DIN0 Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S1_DIN0_PORT ULP_I2S_DIN0_PORT +#define RTE_I2S1_DIN0_PIN ULP_I2S_DIN0_PIN +#define RTE_I2S1_DIN0_MUX 2 +//Pintool data +#endif -// FIFO level can have value 1 to 7 -#define I2S1_TX_FIFO_LEVEL (2U) +// FIFO level can have value 0 to 7 +#define I2S1_TX_FIFO_LEVEL (0U) #define I2S1_RX_FIFO_LEVEL (2U) // I2S1_TX_RES <0=>12 @@ -1399,7 +2184,7 @@ #define I2C0_IRQHandler IRQ042_Handler // I2C0_SCL Pin <0=>P0_7 <1=>P0_65 <2=>P0_66 <3=>P0_75 <4=>P0_32 - +#ifndef I2C0_SCL_LOC #define RTE_I2C0_SCL_PORT_ID 1 #if (RTE_I2C0_SCL_PORT_ID == 0) @@ -1429,9 +2214,32 @@ #else #error "Invalid I2C0 RTE_I2C0_SCL Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2C0_SCL_PORT I2C0_SCL_PORT +#if (I2C0_SCL_LOC == 0) +#define RTE_I2C0_SCL_PIN I2C0_SCL_PIN +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 2 +#define RTE_I2C0_SCL_I2C_REN 7 +#endif +#if (I2C0_SCL_LOC == 1) +#define RTE_I2C0_SCL_PIN (I2C0_SCL_PIN + GPIO_MAX_PIN) +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 23 +#define RTE_I2C0_SCL_I2C_REN 1 +#endif +#if (I2C0_SCL_LOC == 2) +#define RTE_I2C0_SCL_PIN (I2C0_SCL_PIN + GPIO_MAX_PIN) +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 33 +#define RTE_I2C0_SCL_I2C_REN 11 +#endif +//Pintool data +#endif // I2C0_SCL Pin <0=>P0_6 <1=>P0_64 <2=>P0_67 <3=>P0_74 <4=>P0_31 - +#ifndef I2C0_SDA_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_I2C0_SDA_PORT_ID 2 #else @@ -1459,6 +2267,29 @@ #else #error "Invalid I2C0 RTE_I2C0_SDA Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2C0_SDA_PORT I2C0_SDA_PORT +#if (I2C0_SDA_LOC == 3) +#define RTE_I2C0_SDA_PIN I2C0_SDA_PIN +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 1 +#define RTE_I2C0_SDA_I2C_REN 6 +#endif +#if (I2C0_SDA_LOC == 4) +#define RTE_I2C0_SDA_PIN (I2C0_SDA_PIN + GPIO_MAX_PIN) +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 22 +#define RTE_I2C0_SDA_I2C_REN 3 +#endif +#if (I2C0_SDA_LOC == 5) +#define RTE_I2C0_SDA_PIN (I2C0_SDA_PIN + GPIO_MAX_PIN) +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 32 +#define RTE_I2C0_SDA_I2C_REN 10 +#endif +//Pintool data +#endif #define IC_SCL_STUCK_TIMEOUT 20 #define IC_SDA_STUCK_TIMEOUT 20 @@ -1468,7 +2299,7 @@ #define DMA_TX_TL 1 #define DMA_RX_TL 1 #endif -// I2C0 [Driver_I2C0] +// I2C1 [Driver_I2C0] // I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1] // Configuration settings for Driver_I2C1 in component ::Drivers:I2C @@ -1476,7 +2307,8 @@ #define RTE_I2C1 1 #define I2C1_IRQHandler IRQ061_Handler // I2C1_SCL Pin <0=>P0_6 <1=>P0_29 <2=>P0_50 <3=>P0_54 <4=>P0_64 <4=>P0_66 <4=>P0_70 <7=>P0_33 -#define RTE_I2C1_SCL_PORT_ID 0 +#ifndef I2C1_SCL_LOC +#define RTE_I2C1_SCL_PORT_ID 2 #if (RTE_I2C1_SCL_PORT_ID == 0) #define RTE_I2C1_SCL_PORT 0 @@ -1517,10 +2349,51 @@ #else #error "Invalid I2C1_SCL Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2C1_SCL_PORT I2C1_SCL_PORT +#if (I2C1_SCL_LOC == 0) +#define RTE_I2C1_SCL_PIN I2C1_SCL_PIN +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 1 +#define RTE_I2C1_SCL_REN 6 +#endif +#if (I2C1_SCL_LOC == 1) +#define RTE_I2C1_SCL_PIN I2C1_SCL_PIN +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 0 //no pad +#define RTE_I2C1_SCL_REN 29 +#endif +#if (I2C1_SCL_LOC == 2) +#define RTE_I2C1_SCL_PIN I2C1_SCL_PIN +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 14 +#define RTE_I2C1_SCL_REN 50 +#endif +#if (I2C1_SCL_LOC == 3) +#define RTE_I2C1_SCL_PIN I2C1_SCL_PIN +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 18 +#define RTE_I2C1_SCL_REN 54 +#endif +#if (I2C1_SCL_LOC == 4) +#define RTE_I2C1_SCL_PIN (I2C1_SCL_PIN + GPIO_MAX_PIN) +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 22 +#define RTE_I2C1_SCL_REN 2 +#endif +#if (I2C1_SCL_LOC == 5) +#define RTE_I2C1_SCL_PIN (I2C1_SCL_PIN + GPIO_MAX_PIN) +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 29 +#define RTE_I2C1_SCL_REN 6 +#endif +//Pintool data +#endif // I2C1_SCL Pin <0=>P0_7 <1=>P0_30 <2=>P0_51 <3=>P0_55 <4=>P0_65 <4=>P0_67 <4=>P0_71 <7=>P0_34 - -#define RTE_I2C1_SDA_PORT_ID 6 +#ifndef I2C1_SDA_LOC +#define RTE_I2C1_SDA_PORT_ID 2 #if (RTE_I2C1_SDA_PORT_ID == 0) #define RTE_I2C1_SDA_PORT 0 @@ -1567,6 +2440,47 @@ #else #error "Invalid I2C1_SDA Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2C1_SDA_PORT I2C1_SDA_PORT +#if (I2C1_SDA_LOC == 6) +#define RTE_I2C1_SDA_PIN I2C1_SDA_PIN +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 2 +#define RTE_I2C1_SDA_REN 7 +#endif +#if (I2C1_SDA_LOC == 7) +#define RTE_I2C1_SDA_PIN I2C1_SDA_PIN +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 0 //no pad +#define RTE_I2C1_SDA_REN 30 +#endif +#if (I2C1_SDA_LOC == 8) +#define RTE_I2C1_SDA_PIN I2C1_SDA_PIN +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 15 +#define RTE_I2C1_SDA_REN 51 +#endif +#if (I2C1_SDA_LOC == 9) +#define RTE_I2C1_SDA_PIN I2C1_SDA_PIN +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 19 +#define RTE_I2C1_SDA_REN 55 +#endif +#if (I2C1_SDA_LOC == 10) +#define RTE_I2C1_SDA_PIN (I2C1_SDA_PIN + GPIO_MAX_PIN) +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 23 +#define RTE_I2C1_SDA_REN 1 +#endif +#if (I2C1_SDA_LOC == 11) +#define RTE_I2C1_SDA_PIN (I2C1_SDA_PIN + GPIO_MAX_PIN) +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 29 +#define RTE_I2C1_SDA_REN 7 +#endif +//Pintool data +#endif #define IC_SCL_STUCK_TIMEOUT 20 #define IC_SDA_STUCK_TIMEOUT 20 @@ -1579,12 +2493,13 @@ // I2C1 [Driver_I2C1] -// I2C2 (Inter-integrated Circuit Interface 2) [Driver_I2C2] +// ULP I2C (Inter-integrated Circuit Interface 2) [Driver_I2C2] // Configuration settings for Driver_I2C2 in component ::Drivers:I2C #define RTE_I2C2 1 #define I2C2_IRQHandler IRQ013_Handler // I2C2_SCL Pin <0=>P0_1 <1=>P0_5 <2=>P0_7 <3=>P0_8 <4=>P0_13 +#ifndef ULP_I2C_SCL_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_I2C2_SCL_PORT_ID 0 #else @@ -1603,8 +2518,25 @@ #else #error "Invalid I2C2_SCL Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2C2_SCL_PORT ULP_I2C_SCL_PORT +#define RTE_I2C2_SCL_PIN ULP_I2C_SCL_PIN +#define RTE_I2C2_SCL_MUX 4 +#if (ULP_I2C_SCL_LOC == 0) +#define RTE_I2C2_SCL_REN 0 +#elif (ULP_I2C_SCL_LOC == 1) +#define RTE_I2C2_SCL_REN 0 +#elif (ULP_I2C_SCL_LOC == 2) +#define RTE_I2C2_SCL_REN 7 +#elif (ULP_I2C_SCL_LOC == 3) +#define RTE_I2C2_SCL_REN 8 +#endif +//Pintool data +#endif // I2C2_SDA Pin <0=>P0_0 <1=>P0_4 <2=>P0_6 <3=>P0_9 <4=>P0_11 <5=>P0_12 +#ifndef ULP_I2C_SDA_LOC #define RTE_I2C2_SDA_PORT_ID 0 #if (RTE_I2C2_SDA_PORT_ID == 0) #define RTE_I2C2_SDA_PORT 0 @@ -1612,10 +2544,10 @@ #define RTE_I2C2_SDA_MUX 4 #define RTE_I2C2_SDA_REN 6 #elif (RTE_I2C2_SDA_PORT_ID == 1) -#define RTE_I2C2_SDA_PORT 0 -#define RTE_I2C2_SDA_PIN 9 -#define RTE_I2C2_SDA_MUX 4 -#define RTE_I2C2_SDA_I2C_REN 9 +#define RTE_I2C2_SDA_PORT 0 +#define RTE_I2C2_SDA_PIN 9 +#define RTE_I2C2_SDA_MUX 4 +#define RTE_I2C2_SDA_REN 9 #elif (RTE_I2C2_SDA_PORT_ID == 2) #define RTE_I2C2_SDA_PORT 0 #define RTE_I2C2_SDA_PIN 11 @@ -1624,6 +2556,24 @@ #else #error "Invalid I2C2_SDA Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2C2_SDA_PORT I2C2_SDA_PORT +#define RTE_I2C2_SDA_PIN I2C2_SDA_PIN +#define RTE_I2C2_SDA_MUX 4 +#if (ULP_I2C_SDA_LOC == 4) +#define RTE_I2C2_SDA_REN 0 +#elif (ULP_I2C_SDA_LOC == 5) +#define RTE_I2C2_SDA_REN 0 +#elif (ULP_I2C_SDA_LOC == 6) +#define RTE_I2C2_SDA_REN 6 +#elif (ULP_I2C_SDA_LOC == 7) +#define RTE_I2C2_SDA_REN 9 +#elif (ULP_I2C_SDA_LOC == 8) +#define RTE_I2C2_SDA_REN 11 +#endif +//Pintool data +#endif #define IC_SCL_STUCK_TIMEOUT 20 #define IC_SDA_STUCK_TIMEOUT 20 @@ -1642,6 +2592,7 @@ // GSPI_MASTER_CLK <0=>P0_8 <1=>P0_25 <2=>P0_46 <3=>P0_52 // CLK of GSPI0 +#ifndef GSPI_MASTER_SCK_LOC #define RTE_GSPI_MASTER_CLK_PORT_ID 1 #if (RTE_GSPI_MASTER_CLK_PORT_ID == 0) @@ -1667,12 +2618,31 @@ #else #error "Invalid GSPI0 RTE_GSPI_MASTER_CLK_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_GSPI_MASTER_CLK_PORT GSPI_MASTER_SCK__PORT +#define RTE_GSPI_MASTER_CLK_PIN GSPI_MASTER_SCK__PIN +#define RTE_GSPI_MASTER_CLK_MUX 4 +#if (GSPI_MASTER_SCK_LOC == 0) +#define RTE_GSPI_MASTER_CLK_PAD 3 +#endif +#if (GSPI_MASTER_SCK_LOC == 1) +#define RTE_GSPI_MASTER_CLK_PAD 0 +#endif +#if (GSPI_MASTER_SCK_LOC == 2) +#define RTE_GSPI_MASTER_CLK_PAD 10 +#endif +#if (GSPI_MASTER_SCK_LOC == 3) +#define RTE_GSPI_MASTER_CLK_PAD 16 +#endif +//Pintool data +#endif // GSPI_MASTER_CS0 // <0=>P0_9 <1=>P0_28 <2=>P0_49 <3=>P0_53 // CS0 of GSPI0 // - +#ifndef GSPI_MASTER_CS0_LOC #define RTE_GSPI_MASTER_CS0_PORT_ID 1 #if (RTE_GSPI_MASTER_CS0_PORT_ID == 0) @@ -1702,11 +2672,32 @@ #else #error "Invalid GSPI0 RTE_GSPI_MASTER_CS0_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_GSPI_MASTER_CS0 1 +#define RTE_GSPI_MASTER_CS0_PORT GSPI_MASTER_CS0__PORT +#define RTE_GSPI_MASTER_CS0_PIN GSPI_MASTER_CS0__PIN +#define RTE_GSPI_MASTER_CS0_MUX 4 +#if (GSPI_MASTER_CS0_LOC == 4) +#define RTE_GSPI_MASTER_CS0_PAD 4 +#endif +#if (GSPI_MASTER_CS0_LOC == 5) +#define RTE_GSPI_MASTER_CS0_PAD 0 +#endif +#if (GSPI_MASTER_CS0_LOC == 6) +#define RTE_GSPI_MASTER_CS0_PAD 13 +#endif +#if (GSPI_MASTER_CS0_LOC == 7) +#define RTE_GSPI_MASTER_CS0_PAD 17 +#endif +//Pintool data +#endif // GSPI_MASTER_CS1 // <0=>P0_10 <1=>P0_29 <2=>P0_50 <3=>P0_54 // CS1 of GSPI0 // +#ifndef GSPI_MASTER_CS1_LOC #define RTE_GSPI_MASTER_CS1_PORT_ID 1 #if (RTE_GSPI_MASTER_CS1_PORT_ID == 0) #define RTE_GSPI_MASTER_CS1 1 @@ -1735,11 +2726,32 @@ #else #error "Invalid GSPI0 RTE_GSPI_MASTER_CS1_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_GSPI_MASTER_CS1 1 +#define RTE_GSPI_MASTER_CS1_PORT GSPI_MASTER_CS1__PORT +#define RTE_GSPI_MASTER_CS1_PIN GSPI_MASTER_CS1__PIN +#define RTE_GSPI_MASTER_CS1_MUX 4 +#if (GSPI_MASTER_CS1_LOC == 8) +#define RTE_GSPI_MASTER_CS1_PAD 5 +#endif +#if (GSPI_MASTER_CS1_LOC == 9) +#define RTE_GSPI_MASTER_CS1_PAD 0 +#endif +#if (GSPI_MASTER_CS1_LOC == 10) +#define RTE_GSPI_MASTER_CS1_PAD 14 +#endif +#if (GSPI_MASTER_CS1_LOC == 11) +#define RTE_GSPI_MASTER_CS1_PAD 18 +#endif +//Pintool data +#endif // GSPI_MASTER_CS2 // <0=>P0_15 <1=>P0_30 <2=>P0_51 <3=>P0_55 // CS2 of GSPI0 // +#ifndef GSPI_MASTER_CS2_LOC #define RTE_GSPI_MASTER_CS2_PORT_ID 1 #if (RTE_GSPI_MASTER_CS2_PORT_ID == 0) #define RTE_GSPI_MASTER_CS2 1 @@ -1768,10 +2780,30 @@ #else #error "Invalid GSPI0 RTE_GSPI_MASTER_CS2_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_GSPI_MASTER_CS2 1 +#define RTE_GSPI_MASTER_CS2_PORT GSPI_MASTER_CS2__PORT +#define RTE_GSPI_MASTER_CS2_PIN GSPI_MASTER_CS2__PIN +#define RTE_GSPI_MASTER_CS2_MUX 4 +#if (GSPI_MASTER_CS2_LOC == 12) +#define RTE_GSPI_MASTER_CS2_PAD 8 +#endif +#if (GSPI_MASTER_CS2_LOC == 13) +#define RTE_GSPI_MASTER_CS2_PAD 0 +#endif +#if (GSPI_MASTER_CS2_LOC == 14) +#define RTE_GSPI_MASTER_CS2_PAD 15 +#endif +#if (GSPI_MASTER_CS2_LOC == 15) +#define RTE_GSPI_MASTER_CS2_PAD 19 +#endif +//Pintool data +#endif // GSPI_MASTER_MOSI <0=>P0_12 <1=>P0_27 <2=>P0_48 <3=>P0_57 <4=>P0_6 // MOSI of GSPI0 - +#ifndef GSPI_MASTER_MOSI_LOC #define RTE_GSPI_MASTER_MOSI_PORT_ID 1 #if (RTE_GSPI_MASTER_MOSI_PORT_ID == 0) @@ -1802,10 +2834,36 @@ #else #error "Invalid GSPI0 RTE_GSPI_MASTER_MOSI_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_GSPI_MASTER_MOSI_PORT GSPI_MASTER_MOSI__PORT +#define RTE_GSPI_MASTER_MOSI_PIN GSPI_MASTER_MOSI__PIN +#if (GSPI_MASTER_MOSI_LOC == 16) +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 1 +#endif +#if (GSPI_MASTER_MOSI_LOC == 17) +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 0 +#endif +#if (GSPI_MASTER_MOSI_LOC == 18) +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 12 +#endif +#if (GSPI_MASTER_MOSI_LOC == 19) +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 21 +#endif +#if (GSPI_MASTER_MOSI_LOC == 20) +#define RTE_GSPI_MASTER_MOSI_MUX 12 +#define RTE_GSPI_MASTER_MOSI_PAD 1 +#endif +//Pintool data +#endif // GSPI_MASTER_MISO <0=>P0_11 <1=>P0_26 <2=>P0_47 <3=>P0_56 // MISO of GSPI0 - +#ifndef GSPI_MASTER_MISO_LOC #define RTE_GSPI_MASTER_MISO_PORT_ID 1 #if (RTE_GSPI_MASTER_MISO_PORT_ID == 0) @@ -1831,6 +2889,25 @@ #else #error "Invalid GSPI0 RTE_GSPI_MASTER_MISO_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_GSPI_MASTER_MISO_PORT GSPI_MASTER_MISO__PORT +#define RTE_GSPI_MASTER_MISO_PIN GSPI_MASTER_MISO__PIN +#define RTE_GSPI_MASTER_MISO_MUX 4 +#if (GSPI_MASTER_MISO_LOC == 21) +#define RTE_GSPI_MASTER_MISO_PAD 6 +#endif +#if (GSPI_MASTER_MISO_LOC == 22) +#define RTE_GSPI_MASTER_MISO_PAD 0 +#endif +#if (GSPI_MASTER_MISO_LOC == 23) +#define RTE_GSPI_MASTER_MISO_PAD 11 +#endif +#if (GSPI_MASTER_MISO_LOC == 24) +#define RTE_GSPI_MASTER_MISO_PAD 20 +#endif +//Pintool data +#endif #if defined(HIGH_THROUGHPUT_EN) && (HIGH_THROUGHPUT_EN == ENABLE) #define RTE_GSPI_MASTER_CHNL_UDMA_TX_EN 1 @@ -1866,6 +2943,7 @@ //SCT_IN_0 <0=>GPIO_25 <1=>GPIO_64 <2=>GPIO_68 +#ifndef SCT_IN0_LOC #define RTE_SCT_IN_0_PORT_ID 0 #if (RTE_SCT_IN_0_PORT_ID == 0) @@ -1876,9 +2954,27 @@ #else #error "Invalid RTE_SCT_IN_0_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SCT_IN_0_PORT SCT_IN0_PORT +#if (SCT_IN0_LOC == 0) +#define RTE_SCT_IN_0_PIN SCT_IN0_PIN +#define RTE_SCT_IN_0_MUX 9 +#define RTE_SCT_IN_0_PAD 0 //no pad +#elif (SCT_IN0_LOC == 1) +#define RTE_SCT_IN_0_PIN (SCT_IN0_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_0_MUX 7 +#define RTE_SCT_IN_0_PAD 22 +#elif (SCT_IN0_LOC == 2) +#define RTE_SCT_IN_0_PIN (SCT_IN0_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_0_MUX 9 +#define RTE_SCT_IN_0_PAD 26 +#endif +//Pintool data +#endif //SCT_IN_1 <0=>GPIO_26 <1=>GPIO_65 <2=>GPIO_69 - +#ifndef SCT_IN1_LOC #define RTE_SCT_IN_1_PORT_ID 1 #if (RTE_SCT_IN_1_PORT_ID == 0) @@ -1894,9 +2990,29 @@ #else #error "Invalid RTE_SCT_IN_1_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SCT_IN_1_PORT SCT_IN1_PORT +#if (SCT_IN1_LOC == 3) +#define RTE_SCT_IN_1_PIN SCT_IN1_PIN +#define RTE_SCT_IN_1_MUX 9 +#define RTE_SCT_IN_1_PAD 0 //no pad +#endif +#if (SCT_IN1_LOC == 4) +#define RTE_SCT_IN_1_PIN (SCT_IN1_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_1_MUX 7 +#define RTE_SCT_IN_1_PAD 23 +#endif +#if (SCT_IN1_LOC == 5) +#define RTE_SCT_IN_1_PIN (SCT_IN1_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_1_MUX 9 +#define RTE_SCT_IN_1_PAD 27 +#endif +//Pintool data +#endif //SCT_IN_2 <0=>GPIO_27 <1=>GPIO_66 <2=>GPIO_70 - +#ifndef SCT_IN2_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SCT_IN_2_PORT_ID 0 #else @@ -1921,9 +3037,24 @@ #else #error "Invalid RTE_SCT_IN_0_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SCT_IN_2_PORT SCT_IN2_PORT +#if (SCT_IN2_LOC == 6) +#define RTE_SCT_IN_2_PIN SCT_IN2_PIN +#define RTE_SCT_IN_2_MUX 9 +#define RTE_SCT_IN_2_PAD 0 //no pad +#endif +#if (SCT_IN2_LOC == 7) +#define RTE_SCT_IN_2_PIN (SCT_IN2_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_2_MUX 9 +#define RTE_SCT_IN_2_PAD 28 +#endif +//Pintool data +#endif //SCT_IN_3 <0=>GPIO_28 <1=>GPIO_67 <2=>GPIO_71 - +#ifndef SCT_IN3_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SCT_IN_3_PORT_ID 0 #else @@ -1948,8 +3079,24 @@ #else #error "Invalid RTE_SCT_IN_0_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SCT_IN_3_PORT SCT_IN3_PORT +#if (SCT_IN3_LOC == 8) +#define RTE_SCT_IN_3_PIN SCT_IN3_PIN +#define RTE_SCT_IN_3_MUX 9 +#define RTE_SCT_IN_3_PAD 0 //no pad +#endif +#if (SCT_IN3_LOC == 9) +#define RTE_SCT_IN_3_PIN (SCT_IN3_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_3_MUX 9 +#define RTE_SCT_IN_3_PAD 29 +#endif +//Pintool data +#endif // SCT_OUT_0 <0=>GPIO_29 <1=>GPIO_68 +#ifndef SCT_OUT0_LOC #define RTE_SCT_OUT_0_PORT_ID 0 #if (RTE_SCT_OUT_0_PORT_ID == 0) #define RTE_SCT_OUT_0_PORT 0 @@ -1959,8 +3106,23 @@ #else #error "Invalid RTE_SCT_OUT_0_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SCT_OUT_0_PORT SCT_OUT0_PORT +#if (SCT_OUT0_LOC == 10) +#define RTE_SCT_OUT_0_PIN SCT_OUT0_PIN +#define RTE_SCT_OUT_0_MUX 9 +#define RTE_SCT_OUT_0_PAD 0 //no pad +#elif (SCT_OUT0_LOC == 11) +#define RTE_SCT_OUT_0_PIN (SCT_OUT0_PIN + GPIO_MAX_PIN) +#define RTE_SCT_OUT_0_MUX 7 +#define RTE_SCT_OUT_0_PAD 26 +#endif +//Pintool data +#endif // SCT_OUT_1 <0=>GPIO_30 <1=>GPIO_69 +#ifndef SCT_OUT1_LOC #define RTE_SCT_OUT_1_PORT_ID 0 #if (RTE_SCT_OUT_1_PORT_ID == 0) #define RTE_SCT_OUT_1_PORT 0 @@ -1970,117 +3132,67 @@ #else #error "Invalid RTE_SCT_OUT_1_PIN Pin Configuration!" #endif - -/// SCT_OUT_2 <0=>GPIO_70 <1=>GPIO_8 -#define RTE_SCT_OUT_2_PORT_ID 0 -#if ((RTE_SCT_OUT_2_PORT_ID == 1)) -#error "Invalid RTE_SCT_OUT_2_PIN pin Configuration!" +#else +//Pintool data +#define RTE_SCT_OUT_1_PORT SCT_OUT1_PORT +#if (SCT_OUT1_LOC == 12) +#define RTE_SCT_OUT_1_PIN SCT_OUT1_PIN +#define RTE_SCT_OUT_1_MUX 9 +#define RTE_SCT_OUT_1_PAD 0 //no pad +#elif (SCT_OUT1_LOC == 13) +#define RTE_SCT_OUT_1_PIN (SCT_OUT1_PIN + GPIO_MAX_PIN) +#define RTE_SCT_OUT_1_MUX 7 +#define RTE_SCT_OUT_1_PAD 27 +#endif +//Pintool data #endif -#if (RTE_SCT_OUT_2_PORT_ID == 0) -#define RTE_SCT_OUT_2_PORT 0 -#define RTE_SCT_OUT_2_PIN 70 +//Pintool data +#define RTE_SCT_OUT_2_PORT SCT_OUT2_PORT +#define RTE_SCT_OUT_2_PIN SCT_OUT2_PIN #define RTE_SCT_OUT_2_MUX 7 #define RTE_SCT_OUT_2_PAD 28 -#elif (RTE_SCT_OUT_2_PORT_ID == 1) -#define RTE_SCT_OUT_2_PORT 0 -#define RTE_SCT_OUT_2_PIN 8 -#define RTE_SCT_OUT_2_MUX 12 -#define RTE_SCT_OUT_2_PAD 3 -#else -#error "Invalid RTE_SCT_OUT_2_PIN Pin Configuration!" -#endif -/**/ -//SCT_OUT_3 <0=>GPIO_71 <1=>GPIO_9 -#define RTE_SCT_OUT_3_PORT_ID 0 -#if ((RTE_SCT_OUT_3_PORT_ID == 1)) -#error "Invalid RTE_SCT_OUT_3_PIN pin Configuration!" -#endif +//Pintool data -#if (RTE_SCT_OUT_3_PORT_ID == 0) -#define RTE_SCT_OUT_3_PORT 0 -#define RTE_SCT_OUT_3_PIN 71 +//Pintool data +#define RTE_SCT_OUT_3_PORT SCT_OUT3_PORT +#define RTE_SCT_OUT_3_PIN SCT_OUT3_PIN #define RTE_SCT_OUT_3_MUX 7 #define RTE_SCT_OUT_3_PAD 29 -#elif (RTE_SCT_OUT_3_PORT_ID == 1) -#define RTE_SCT_OUT_3_PORT 0 -#define RTE_SCT_OUT_3_PIN 9 -#define RTE_SCT_OUT_3_MUX 12 -#define RTE_SCT_OUT_3_PAD 4 -#else -#error "Invalid RTE_SCT_OUT_3_PIN Pin Configuration!" -#endif - -//SCT_OUT_4 <0=>GPIO_72 <1=>GPIO_68 - -#define RTE_SCT_OUT_4_PORT_ID 0 -#if ((RTE_SCT_OUT_4_PORT_ID == 1)) -#error "Invalid RTE_SCT_OUT_4_PIN pin Configuration!" -#endif +//Pintool data -#if (RTE_SCT_OUT_4_PORT_ID == 0) -/**/ -#define RTE_SCT_OUT_4_PORT 0 -#define RTE_SCT_OUT_4_PIN 72 +//Pintool data +#define RTE_SCT_OUT_4_PORT SCT_OUT4_PORT +#define RTE_SCT_OUT_4_PIN SCT_OUT4_PIN #define RTE_SCT_OUT_4_MUX 7 #define RTE_SCT_OUT_4_PAD 30 -#else -#error "Invalid RTE_SCT_OUT_4_PIN Pin Configuration!" -#endif -//SCT_OUT_5 <0=>GPIO_73 <1=>GPIO_69 - -#define RTE_SCT_OUT_5_PORT_ID 0 -#if ((RTE_SCT_OUT_5_PORT_ID == 1)) -#error "Invalid RTE_SCT_OUT_5_PIN pin Configuration!" -#endif +//Pintool data -#if (RTE_SCT_OUT_5_PORT_ID == 0) -#define RTE_SCT_OUT_5_PORT 2 -#define RTE_SCT_OUT_5_PIN 73 +//Pintool data +#define RTE_SCT_OUT_5_PORT SCT_OUT5_PORT +#define RTE_SCT_OUT_5_PIN SCT_OUT5_PIN #define RTE_SCT_OUT_5_MUX 7 #define RTE_SCT_OUT_5_PAD 31 -#else -#error "Invalid RTE_SCT_OUT_5_PIN Pin Configuration!" -#endif - -//SCT_OUT_6 <0=>GPIO_74 <1=>GPIO_70 +//Pintool data -#define RTE_SCT_OUT_6_PORT_ID 0 -#if ((RTE_SCT_OUT_6_PORT_ID == 1)) -#error "Invalid RTE_SCT_OUT_6_PIN pin Configuration!" -#endif - -#if (RTE_SCT_OUT_6_PORT_ID == 0) -#define RTE_SCT_OUT_6_PORT 0 -#define RTE_SCT_OUT_6_PIN 74 +//Pintool data +#define RTE_SCT_OUT_6_PORT SCT_OUT6_PORT +#define RTE_SCT_OUT_6_PIN SCT_OUT6_PIN #define RTE_SCT_OUT_6_MUX 7 #define RTE_SCT_OUT_6_PAD 32 -#elif (RTE_SCT_OUT_6_PORT_ID == 1) -#define RTE_SCT_OUT_6_PORT 0 -#define RTE_SCT_OUT_6_PIN 70 -#define RTE_SCT_OUT_6_MUX 13 -#define RTE_SCT_OUT_6_PAD 28 -#else -#error "Invalid RTE_SCT_OUT_6_PIN Pin Configuration!" -#endif - -// SCT_OUT_7 <0=>GPIO_75 <1=>GPIO_71 - -#define RTE_SCT_OUT_7_PORT_ID 0 +//Pintool data -#if (RTE_SCT_OUT_7_PORT_ID == 0) -#define RTE_SCT_OUT_7_PORT 0 -#define RTE_SCT_OUT_7_PIN 75 +//Pintool data +#define RTE_SCT_OUT_7_PORT SCT_OUT7_PORT +#define RTE_SCT_OUT_7_PIN SCT_OUT7_PIN #define RTE_SCT_OUT_7_MUX 7 #define RTE_SCT_OUT_7_PAD 33 -#else -#error "Invalid RTE_SCT_OUT_7_PIN Pin Configuration!" -#endif +//Pintool data // SIO // //<> Serial Input Output //SIO_0 <0=>GPIO_6 <1=>GPIO_25 <2=>GPIO_64 <3=>GPIO_72 - +#ifndef SIO_0_LOC #define RTE_SIO_0_PORT_ID 0 #if (RTE_SIO_0_PORT_ID == 0) @@ -2101,9 +3213,31 @@ #else #error "Invalid RTE_SIO_0_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_0_PORT SIO_SIO0_PORT +#define RTE_SIO_0_MUX 1 +#if (SIO_0_LOC == 0) +#define RTE_SIO_0_PIN SIO_SIO0_PIN +#define RTE_SIO_0_PAD 1 +#endif +#if (SIO_0_LOC == 1) +#define RTE_SIO_0_PIN SIO_SIO0_PIN +#define RTE_SIO_0_PAD 0 +#endif +#if (SIO_0_LOC == 2) +#define RTE_SIO_0_PIN (SIO_SIO0_PIN + GPIO_MAX_PIN) +#define RTE_SIO_0_PAD 22 +#endif +#if (SIO_0_LOC == 3) +#define RTE_SIO_0_PIN (SIO_SIO0_PIN + GPIO_MAX_PIN) +#define RTE_SIO_0_PAD 30 +#endif +//Pintool data +#endif //SIO_1 <0=>GPIO_7 <1=>GPIO_26 <2=>GPIO_65 <3=>GPIO_73 - +#ifndef SIO_1_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SIO_1_PORT_ID 1 #else @@ -2133,9 +3267,31 @@ #else #error "Invalid RTE_SIO_1_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_1_PORT SIO_SIO1_PORT +#define RTE_SIO_1_MUX 1 +#if (SIO_1_LOC == 4) +#define RTE_SIO_1_PIN SIO_SIO1_PIN +#define RTE_SIO_1_PAD 2 +#endif +#if (SIO_1_LOC == 5) +#define RTE_SIO_1_PIN SIO_SIO1_PIN +#define RTE_SIO_1_PAD 0 +#endif +#if (SIO_1_LOC == 6) +#define RTE_SIO_1_PIN (SIO_SIO1_PIN + GPIO_MAX_PIN) +#define RTE_SIO_1_PAD 23 +#endif +#if (SIO_1_LOC == 7) +#define RTE_SIO_1_PIN (SIO_SIO1_PIN + GPIO_MAX_PIN) +#define RTE_SIO_1_PAD 31 +#endif +//Pintool data +#endif // SIO_2 <0=>GPIO_8 <1=>GPIO_27 <2=>GPIO_66 <3=>GPIO_74 - +#ifndef SIO_2_LOC #define RTE_SIO_2_PORT_ID 1 #if (RTE_SIO_2_PORT_ID == 0) @@ -2161,9 +3317,27 @@ #else #error "Invalid RTE_SIO_2_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_2_PORT SIO_SIO2_PORT +#define RTE_SIO_2_MUX 1 +#if (SIO_2_LOC == 8) +#define RTE_SIO_2_PIN SIO_SIO2_PIN +#define RTE_SIO_2_PAD 3 +#endif +#if (SIO_2_LOC == 9) +#define RTE_SIO_2_PIN SIO_SIO2_PIN +#define RTE_SIO_2_PAD 0 +#endif +#if (SIO_2_LOC == 10) +#define RTE_SIO_2_PIN (SIO_SIO2_PIN + GPIO_MAX_PIN) +#define RTE_SIO_2_PAD 32 +#endif +//Pintool data +#endif //SIO_3 <0=>GPIO_9 <1=>GPIO_28 <2=>GPIO_67 <3=>GPIO_75 - +#ifndef SIO_3_LOC #define RTE_SIO_3_PORT_ID 1 #if (RTE_SIO_3_PORT_ID == 0) @@ -2189,8 +3363,27 @@ #else #error "Invalid RTE_SIO_3_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_3_PORT SIO_SIO3_PORT +#define RTE_SIO_3_MUX 1 +#if (SIO_3_LOC == 11) +#define RTE_SIO_3_PIN SIO_SIO3_PIN +#define RTE_SIO_3_PAD 4 +#endif +#if (SIO_3_LOC == 12) +#define RTE_SIO_3_PIN SIO_SIO3_PIN +#define RTE_SIO_3_PAD 0 +#endif +#if (SIO_3_LOC == 13) +#define RTE_SIO_3_PIN (SIO_SIO3_PIN + GPIO_MAX_PIN) +#define RTE_SIO_3_PAD 33 +#endif +//Pintool data +#endif //SIO_4 <0=>GPIO_10 <1=>GPIO_29 <2=>GPIO_68 +#ifndef SIO_4_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SIO_4_PORT_ID 1 #else @@ -2209,8 +3402,27 @@ #else #error "Invalid RTE_SIO_3_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_4_PORT SIO_SIO4_PORT +#define RTE_SIO_4_MUX 1 +#if (SIO_4_LOC == 14) +#define RTE_SIO_4_PAD 5 +#define RTE_SIO_4_PIN SIO_SIO4_PIN +#endif +#if (SIO_4_LOC == 15) +#define RTE_SIO_4_PAD 0 +#define RTE_SIO_4_PIN SIO_SIO4_PIN +#endif +#if (SIO_4_LOC == 16) +#define RTE_SIO_4_PAD 26 +#define RTE_SIO_4_PIN (SIO_SIO4_PIN + GPIO_MAX_PIN) +#endif +//Pintool data +#endif // SIO_5 <0=>GPIO_11 <1=>GPIO_30 <2=>GPIO_69 +#ifndef SIO_5_LOC #define RTE_SIO_5_PORT_ID 0 #if (RTE_SIO_5_PORT_ID == 0) #define RTE_SIO_5_PORT 0 @@ -2225,15 +3437,38 @@ #else #error "Invalid RTE_SIO_5_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_5_PORT SIO_SIO5_PORT +#define RTE_SIO_5_MUX 1 +#if (SIO_5_LOC == 17) +#define RTE_SIO_5_PAD 6 +#define RTE_SIO_5_PIN SIO_SIO5_PIN +#endif +#if (SIO_5_LOC == 18) +#define RTE_SIO_5_PAD 0 +#define RTE_SIO_5_PIN SIO_SIO5_PIN +#endif +#if (SIO_5_LOC == 19) +#define RTE_SIO_5_PAD 0 +#define RTE_SIO_5_PIN (SIO_SIO5_PIN + GPIO_MAX_PIN) +#endif +//Pintool data +#endif // SIO_6 GPIO_70 +#ifndef SIO_6_LOC #define RTE_SIO_6_PORT 0 #define RTE_SIO_6_PIN 70 -#define RTE_SIO_6_MUX 1 -#define RTE_SIO_6_PAD 28 +#else +#define RTE_SIO_6_PORT SIO_SIO6_PORT +#define RTE_SIO_6_PIN (SIO_SIO6_PIN + GPIO_MAX_PIN) +#endif +#define RTE_SIO_6_MUX 1 +#define RTE_SIO_6_PAD 28 // SIO_7 <0=>GPIO_15 <1=>GPIO_71 - +#ifndef SIO_7_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SIO_7_PORT_ID 1 #else @@ -2253,12 +3488,26 @@ #else #error "Invalid RTE_SIO_7_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_7_PORT SIO_SIO7_PORT +#define RTE_SIO_7_MUX 1 +#if (SIO_7_LOC == 21) +#define RTE_SIO_7_PIN SIO_SIO7_PIN +#define RTE_SIO_7_PAD 8 +#endif +#if (SIO_7_LOC == 22) +#define RTE_SIO_7_PIN (SIO_SIO7_PIN + GPIO_MAX_PIN) +#define RTE_SIO_7_PAD 29 +#endif +//Pintool data +#endif //<> Pulse Width Modulation //PWM_1H <0=>GPIO_7 <1=>GPIO_64 <2=>GPIO_65 - +#ifndef PWM_1H_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER -#define RTE_PWM_1H_PORT_ID 1 +#define RTE_PWM_1H_PORT_ID 0 #else #define RTE_PWM_1H_PORT_ID 0 #endif @@ -2276,9 +3525,24 @@ #else #error "Invalid RTE_PWM_1H_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_1H_PORT PWM_1H_PORT +#if (PWM_1H_LOC == 0) +#define RTE_PWM_1H_PIN PWM_1H_PIN +#define RTE_PWM_1H_MUX 10 +#define RTE_PWM_1H_PAD 2 +#endif +#if (PWM_1H_LOC == 1) +#define RTE_PWM_1H_PIN (PWM_1H_PIN + GPIO_MAX_PIN) +#define RTE_PWM_1H_MUX 8 +#define RTE_PWM_1H_PAD 22 +#endif +//Pintool data +#endif // PWM_1L <0=>GPIO_6 <1=>GPIO_64 <2=>GPIO_64 - +#ifndef PWM_1L_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_PWM_1L_PORT_ID 0 #else @@ -2293,9 +3557,23 @@ #else #error "Invalid RTE_PWM_1L_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_1L_PORT PWM_1L_PORT +#if (PWM_1L_LOC == 2) +#define RTE_PWM_1L_PIN PWM_1L_PIN +#define RTE_PWM_1L_MUX 10 +#define RTE_PWM_1L_PAD 1 +#elif (PWM_1L_LOC == 3) +#define RTE_PWM_1L_PIN (PWM_1L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_1L_MUX 8 +#define RTE_PWM_1L_PAD 22 +#endif +//Pintool data +#endif //PWM_2H <0=>GPIO_9 <1=>GPIO_67 <2=>GPIO_69 - +#ifndef PWM_2H_LOC #define RTE_PWM_2H_PORT_ID 0 #if ((RTE_PWM_2H_PORT_ID == 2)) #error "Invalid RTE_PWM_2H_PIN pin Configuration!" @@ -2314,9 +3592,24 @@ #else #error "Invalid RTE_PWM_2H_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_2H_PORT PWM_2H_PORT +#if (PWM_2H_LOC == 4) +#define RTE_PWM_2H_PIN PWM_2H_PIN +#define RTE_PWM_2H_MUX 10 +#define RTE_PWM_2H_PAD 4 +#endif +#if (PWM_2H_LOC == 5) +#define RTE_PWM_2H_PIN (PWM_2H_PIN + GPIO_MAX_PIN) +#define RTE_PWM_2H_MUX 12 +#define RTE_PWM_2H_PAD 27 +#endif +//Pintool data +#endif // PWM_2L <0=>GPIO_8 <1=>GPIO_66 <2=>GPIO_68 - +#ifndef PWM_2L_LOC #define RTE_PWM_2L_PORT_ID 0 #if ((RTE_PWM_2L_PORT_ID == 2)) #error "Invalid RTE_PWM_2L_PIN pin Configuration!" @@ -2335,8 +3628,29 @@ #else #error "Invalid RTE_PWM_2L_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_2L_PORT PWM_2L_PORT +#if (PWM_2L_LOC == 6) +#define RTE_PWM_2L_PIN PWM_2L_PIN +#define RTE_PWM_2L_MUX 10 +#define RTE_PWM_2L_PAD 3 +#endif +#if (PWM_2L_LOC == 7) +#define RTE_PWM_2L_PIN (PWM_2L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_2L_MUX 8 +#define RTE_PWM_2L_PAD 24 +#endif +#if (PWM_2L_LOC == 8) +#define RTE_PWM_2L_PIN (PWM_2L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_2L_MUX 12 +#define RTE_PWM_2L_PAD 26 +#endif +//Pintool data +#endif // PWM_3H <0=>GPIO_11 <1=>GPIO_69 +#ifndef PWM_3H_LOC #define RTE_PWM_3H_PORT_ID 0 #if (RTE_PWM_3H_PORT_ID == 0) #define RTE_PWM_3H_PORT 0 @@ -2346,8 +3660,23 @@ #else #error "Invalid RTE_PWM_3H_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_3H_PORT PWM_3H_PORT +#if (PWM_3H_LOC == 9) +#define RTE_PWM_3H_PIN PWM_3H_PIN +#define RTE_PWM_3H_MUX 10 +#define RTE_PWM_3H_PAD 6 +#elif (PWM_3H_LOC == 10) +#define RTE_PWM_3H_PIN (PWM_3H_PIN + GPIO_MAX_PIN) +#define RTE_PWM_3H_MUX 8 +#define RTE_PWM_3H_PAD 27 +#endif +//Pintool data +#endif // PWM_3L <0=>GPIO_10 <1=>GPIO_68 +#ifndef PWM_3L_LOC #define RTE_PWM_3L_PORT_ID 0 #if (RTE_PWM_3L_PORT_ID == 0) @@ -2358,9 +3687,23 @@ #else #error "Invalid RTE_PWM_3L_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_3L_PORT PWM_3L_PORT +#if (PWM_3L_LOC == 11) +#define RTE_PWM_3L_PIN PWM_3L_PIN +#define RTE_PWM_3L_MUX 10 +#define RTE_PWM_3L_PAD 5 +#elif (PWM_3L_LOC == 12) +#define RTE_PWM_3L_PIN (PWM_3L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_3L_MUX 8 +#define RTE_PWM_3L_PAD 26 +#endif +//Pintool data +#endif // PWM_4H <0=>GPIO_15 <1=>GPIO_71 - +#ifndef PWM_4H_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_PWM_4H_PORT_ID 1 #else @@ -2380,9 +3723,17 @@ #else #error "Invalid RTE_PWM_4H_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_4H_PORT PWM_4H_PORT +#define RTE_PWM_4H_PIN (PWM_4H_PIN + GPIO_MAX_PIN) +#define RTE_PWM_4H_MUX 8 +#define RTE_PWM_4H_PAD 29 +//Pintool data +#endif // PWM_4H <0=>GPIO_12 <1=>GPIO_70 - +#ifndef PWM_4L_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_PWM_4L_PORT_ID 1 #else @@ -2402,8 +3753,24 @@ #else #error "Invalid RTE_PWM_4L_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_4L_PORT PWM_4L_PORT +#if (PWM_4L_LOC == 14) +#define RTE_PWM_4L_PIN PWM_4L_PIN +#define RTE_PWM_4L_MUX 10 +#define RTE_PWM_4L_PAD 7 +#endif +#if (PWM_4L_LOC == 15) +#define RTE_PWM_4L_PIN (PWM_4L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_4L_MUX 8 +#define RTE_PWM_4L_PAD 28 +#endif +//Pintool data +#endif // PWM_FAULTA <0=>GPIO_25 <1=>GPIO_68 <1=>GPIO_73 +#ifndef PWM_FAULTA_LOC #define RTE_PWM_FAULTA_PORT_ID 0 #if (RTE_PWM_FAULTA_PORT_ID == 0) @@ -2419,8 +3786,29 @@ #else #error "Invalid RTE_PWM_FAULTA_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_FAULTA_PORT PWM_FAULTA_PORT +#if (PWM_FAULTA_LOC == 16) +#define RTE_PWM_FAULTA_PIN PWM_FAULTA_PIN +#define RTE_PWM_FAULTA_MUX 10 +#define RTE_PWM_FAULTA_PAD 0 //no pad +#endif +#if (PWM_FAULTA_LOC == 17) +#define RTE_PWM_FAULTA_PIN (PWM_FAULTA_PIN + GPIO_MAX_PIN) +#define RTE_PWM_FAULTA_MUX 10 +#define RTE_PWM_FAULTA_PAD 26 +#endif +#if (PWM_FAULTA_LOC == 18) +#define RTE_PWM_FAULTA_PIN (PWM_FAULTA_PIN + GPIO_MAX_PIN) +#define RTE_PWM_FAULTA_MUX 8 +#define RTE_PWM_FAULTA_PAD 31 +#endif +//Pintool data +#endif // PWM_FAULTB <0=>GPIO_26 <1=>GPIO_69 <1=>GPIO_74 +#ifndef PWM_FAULTB_LOC #define RTE_PWM_FAULTB_PORT_ID 0 #if (RTE_PWM_FAULTB_PORT_ID == 0) @@ -2436,13 +3824,42 @@ #else #error "Invalid RTE_PWM_FAULTB_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_FAULTB_PORT PWM_FAULTB_PORT +#if (PWM_FAULTB_LOC == 19) +#define RTE_PWM_FAULTB_PIN PWM_FAULTB_PIN +#define RTE_PWM_FAULTB_MUX 10 +#define RTE_PWM_FAULTB_PAD 0 //no pad +#endif +#if (PWM_FAULTB_LOC == 20) +#define RTE_PWM_FAULTB_PIN (PWM_FAULTB_PIN + GPIO_MAX_PIN) +#define RTE_PWM_FAULTB_MUX 10 +#define RTE_PWM_FAULTB_PAD 27 +#endif +#if (PWM_FAULTB_LOC == 21) +#define RTE_PWM_FAULTB_PIN (PWM_FAULTB_PIN + GPIO_MAX_PIN) +#define RTE_PWM_FAULTB_MUX 8 +#define RTE_PWM_FAULTB_PAD 32 +#endif +//Pintool data +#endif + //PWM_SLP_EVENT_TRIG GPIO_72 +#ifndef PWM_EVTTRIG_LOC #define RTE_PWM_SLP_EVENT_TRIG_PORT 0 #define RTE_PWM_SLP_EVENT_TRIG_PIN 72 -#define RTE_PWM_SLP_EVENT_TRIG_MUX 8 -#define RTE_PWM_SLP_EVENT_TRIG_PAD 30 +#else +//Pintool data +#define RTE_PWM_SLP_EVENT_TRIG_PORT PWM_SLEEP_EVT_TRIG_PORT +#define RTE_PWM_SLP_EVENT_TRIG_PIN (PWM_SLEEP_EVT_TRIG_PIN + GPIO_MAX_PIN) +//Pintool data +#endif +#define RTE_PWM_SLP_EVENT_TRIG_MUX 8 +#define RTE_PWM_SLP_EVENT_TRIG_PAD 30 //PWM_TMR_EXT_TRIG_1 <0=>GPIO_27 <1=>GPIO_51 <2=>GPIO_70 <3=>GPIO_75 +#ifndef PWM_EXTTRIG1_LOC #define RTE_PWM_TMR_EXT_TRIG_1_PORT_ID 0 #if (RTE_PWM_TMR_EXT_TRIG_1_PORT_ID == 0) @@ -2468,8 +3885,34 @@ #else #error "Invalid RTE_PWM_TMR_EXT_TRIG_1_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_TMR_EXT_TRIG_1_PORT PWM_TMR_EXT_TRIG_1_PORT +#if (PWM_EXTTRIG1_LOC == 22) +#define RTE_PWM_TMR_EXT_TRIG_1_PIN PWM_TMR_EXT_TRIG_1_PIN +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 0 //no pad +#endif +#if (PWM_EXTTRIG1_LOC == 23) +#define RTE_PWM_TMR_EXT_TRIG_1_PIN PWM_TMR_EXT_TRIG_1_PIN +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 15 +#endif +#if (PWM_EXTTRIG1_LOC == 24) +#define RTE_PWM_TMR_EXT_TRIG_1_PIN (PWM_TMR_EXT_TRIG_1_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 28 +#endif +#if (PWM_EXTTRIG1_LOC == 25) +#define RTE_PWM_TMR_EXT_TRIG_1_PIN (PWM_TMR_EXT_TRIG_1_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 33 +#endif +//Pintool data +#endif //PWM_TMR_EXT_TRIG_2 <0=>GPIO_28 <1=>GPIO_54 <2=>GPIO_71 +#ifndef PWM_EXTTRIG2_LOC #define RTE_PWM_TMR_EXT_TRIG_2_PORT_ID 0 #if (RTE_PWM_TMR_EXT_TRIG_2_PORT_ID == 0) @@ -2490,6 +3933,71 @@ #else #error "Invalid RTE_PWM_TMR_EXT_TRIG_2_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_TMR_EXT_TRIG_2_PORT PWM_TMR_EXT_TRIG_2_PORT +#if (PWM_EXTTRIG2_LOC == 26) +#define RTE_PWM_TMR_EXT_TRIG_2_PIN PWM_TMR_EXT_TRIG_2_PIN +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 0 //no pad +#endif +#if (PWM_EXTTRIG2_LOC == 27) +#define RTE_PWM_TMR_EXT_TRIG_2_PIN PWM_TMR_EXT_TRIG_2_PIN +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 18 +#endif +#if (PWM_EXTTRIG2_LOC == 28) //Combination not available in pin mux +#define RTE_PWM_TMR_EXT_TRIG_2_PIN (PWM_TMR_EXT_TRIG_2_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 29 +#endif +#if (PWM_EXTTRIG2_LOC == 29) +#define RTE_PWM_TMR_EXT_TRIG_2_PIN (PWM_TMR_EXT_TRIG_2_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 29 +#endif +//Pintool data +#endif + +//PWM_TMR_EXT_TRIG_3 +//Pintool data +#define RTE_PWM_TMR_EXT_TRIG_3_PORT PWM_TMR_EXT_TRIG_3_PORT +#if (PWM_EXTTRIG3_LOC == 30) +#define RTE_PWM_TMR_EXT_TRIG_3_PIN PWM_TMR_EXT_TRIG_3_PIN +#define RTE_PWM_TMR_EXT_TRIG_3_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_3_PAD 0 //no pad +#endif +#if (PWM_EXTTRIG3_LOC == 31) +#define RTE_PWM_TMR_EXT_TRIG_3_PIN PWM_TMR_EXT_TRIG_3_PIN +#define RTE_PWM_TMR_EXT_TRIG_3_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_3_PAD 19 +#endif +#if (PWM_EXTTRIG3_LOC == 32) +#define RTE_PWM_TMR_EXT_TRIG_3_PIN (PWM_TMR_EXT_TRIG_3_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_3_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_3_PAD 30 +#endif +//Pintool data + +//PWM_TMR_EXT_TRIG_4 +//Pintool data +#define RTE_PWM_TMR_EXT_TRIG_4_PORT PWM_TMR_EXT_TRIG_4_PORT +#if (PWM_EXTTRIG4_LOC == 33) +#define RTE_PWM_TMR_EXT_TRIG_4_PIN PWM_TMR_EXT_TRIG_4_PIN +#define RTE_PWM_TMR_EXT_TRIG_4_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_4_PAD 0 //no pad +#endif +#if (PWM_EXTTRIG4_LOC == 34) +#define RTE_PWM_TMR_EXT_TRIG_4_PIN PWM_TMR_EXT_TRIG_4_PIN +#define RTE_PWM_TMR_EXT_TRIG_4_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_4_PAD 14 +#endif +#if (PWM_EXTTRIG4_LOC == 35) +#define RTE_PWM_TMR_EXT_TRIG_4_PIN (PWM_TMR_EXT_TRIG_4_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_4_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_4_PAD 31 +#endif +//Pintool data //<> QEI (Quadrature Encode Interface) @@ -2640,6 +4148,339 @@ #endif +//ADC START + +#ifndef ADC_P0_LOC +#define RTE_ADC_P0_PORT 0 +#define RTE_ADC_P0_PIN 0 +#else +#define RTE_ADC_P0_PORT ADC_P0_PORT +#define RTE_ADC_P0_PIN ADC_P0_PIN +#endif +#define RTE_ADC_P0_MUX 1 + +#ifndef ADC_N0_LOC +#define RTE_ADC_N0_PORT 0 +#define RTE_ADC_N0_PIN 1 +#else +#define RTE_ADC_N0_PORT ADC_N0_PORT +#define RTE_ADC_N0_PIN ADC_N0_PIN +#endif +#define RTE_ADC_N0_MUX 1 + +#ifndef ADC_P1_LOC +#define RTE_ADC_P1_PORT 0 +#define RTE_ADC_P1_PIN 2 +#else +#define RTE_ADC_P1_PORT ADC_P1_PORT +#define RTE_ADC_P1_PIN ADC_P1_PIN +#endif +#define RTE_ADC_P1_MUX 1 + +#ifndef ADC_N1_LOC +#define RTE_ADC_N1_PORT 0 +#define RTE_ADC_N1_PIN 3 +#else +#define RTE_ADC_N1_PORT ADC_N1_PORT +#define RTE_ADC_N1_PIN ADC_N1_PIN +#endif +#define RTE_ADC_N1_MUX 1 + +#ifndef ADC_P2_LOC +#define RTE_ADC_P2_PORT 0 +#define RTE_ADC_P2_PIN 4 +#else +#define RTE_ADC_P2_PORT ADC_P2_PORT +#define RTE_ADC_P2_PIN ADC_P2_PIN +#endif +#define RTE_ADC_P2_MUX 1 + +#ifndef ADC_N2_LOC +#define RTE_ADC_N2_PORT 0 +#define RTE_ADC_N2_PIN 5 +#else +#define RTE_ADC_N2_PORT ADC_N2_PORT +#define RTE_ADC_N2_PIN ADC_N2_PIN +#endif +#define RTE_ADC_N2_MUX 1 + +#ifndef ADC_P3_LOC +#define RTE_ADC_P3_PORT 0 +#define RTE_ADC_P3_PIN 6 +#else +#define RTE_ADC_P3_PORT ADC_P3_PORT +#define RTE_ADC_P3_PIN ADC_P3_PIN +#endif +#define RTE_ADC_P3_MUX 1 + +#ifndef ADC_N3_LOC +#define RTE_ADC_N3_PORT 0 +#define RTE_ADC_N3_PIN 11 +#else +#define RTE_ADC_N3_PORT ADC_N3_PORT +#define RTE_ADC_N3_PIN ADC_N3_PIN +#endif +#define RTE_ADC_N3_MUX 1 + +#ifndef ADC_P4_LOC +#define RTE_ADC_P4_PORT 0 +#define RTE_ADC_P4_PIN 8 +#else +#define RTE_ADC_P4_PORT ADC_P4_PORT +#define RTE_ADC_P4_PIN ADC_P4_PIN +#endif +#define RTE_ADC_P4_MUX 1 + +#ifndef ADC_N4_LOC +#define RTE_ADC_N4_PORT 0 +#define RTE_ADC_N4_PIN 9 +#else +#define RTE_ADC_N4_PORT ADC_N4_PORT +#define RTE_ADC_N4_PIN ADC_N4_PIN +#endif +#define RTE_ADC_N4_MUX 1 + +#ifndef ADC_P5_LOC +#define RTE_ADC_P5_PORT 0 +#define RTE_ADC_P5_PIN 10 +#else +#define RTE_ADC_P5_PORT ADC_P5_PORT +#define RTE_ADC_P5_PIN ADC_P5_PIN +#endif +#define RTE_ADC_P5_MUX 1 + +#ifndef ADC_N5_LOC +#define RTE_ADC_N5_PORT 0 +#define RTE_ADC_N5_PIN 7 +#else +#define RTE_ADC_N5_PORT ADC_N5_PORT +#define RTE_ADC_N5_PIN ADC_N5_PIN +#endif +#define RTE_ADC_N5_MUX 1 + +#ifndef ADC_P6_LOC +#define RTE_ADC_P6_PORT 0 +#define RTE_ADC_P6_PIN 25 +#else +#define RTE_ADC_P6_PORT ADC_P6_PORT +#define RTE_ADC_P6_PIN ADC_P6_PIN +#endif +#define RTE_ADC_P6_MUX 1 +#define RTE_ADC_P6_PAD 0 + +#ifndef ADC_N6_LOC +#define RTE_ADC_N6_PORT 0 +#define RTE_ADC_N6_PIN 26 +#else +#define RTE_ADC_N6_PORT ADC_N6_PORT +#define RTE_ADC_N6_PIN ADC_N6_PIN +#endif +#define RTE_ADC_N6_MUX 1 +#define RTE_ADC_N6_PAD 0 + +#ifndef ADC_P7_LOC +#define RTE_ADC_P7_PORT 0 +#define RTE_ADC_P7_PIN 27 +#else +#define RTE_ADC_P7_PORT ADC_P7_PORT +#define RTE_ADC_P7_PIN ADC_P7_PIN +#endif +#define RTE_ADC_P7_MUX 1 +#define RTE_ADC_P7_PAD 0 + +#ifndef ADC_N7_LOC +#define RTE_ADC_N7_PORT 0 +#define RTE_ADC_N7_PIN 28 +#else +#define RTE_ADC_N7_PORT ADC_N7_PORT +#define RTE_ADC_N7_PIN ADC_N7_PIN +#endif +#define RTE_ADC_N7_MUX 1 +#define RTE_ADC_N7_PAD 0 + +#ifndef ADC_P8_LOC +#define RTE_ADC_P8_PORT 0 +#define RTE_ADC_P8_PIN 29 +#else +#define RTE_ADC_P8_PORT ADC_P8_PORT +#define RTE_ADC_P8_PIN ADC_P8_PIN +#endif +#define RTE_ADC_P8_MUX 1 +#define RTE_ADC_P8_PAD 0 + +#ifndef ADC_N8_LOC +#define RTE_ADC_N8_PORT 0 +#define RTE_ADC_N8_PIN 30 +#else +#define RTE_ADC_N8_PORT ADC_N8_PORT +#define RTE_ADC_N8_PIN ADC_N8_PIN +#endif +#define RTE_ADC_N8_MUX 1 +#define RTE_ADC_N8_PAD 0 + +#ifndef ADC_P10_LOC +#define RTE_ADC_P10_PORT 0 +#define RTE_ADC_P10_PIN 1 +#else +#define RTE_ADC_P10_PORT ADC_P10_PORT +#define RTE_ADC_P10_PIN ADC_P10_PIN +#endif +#define RTE_ADC_P10_MUX 1 + +#ifndef ADC_P11_LOC +#define RTE_ADC_P11_PORT 0 +#define RTE_ADC_P11_PIN 3 +#else +#define RTE_ADC_P11_PORT ADC_P11_PORT +#define RTE_ADC_P11_PIN ADC_P11_PIN +#endif +#define RTE_ADC_P11_MUX 1 + +#ifndef ADC_P12_LOC +#define RTE_ADC_P12_PORT 0 +#define RTE_ADC_P12_PIN 5 +#else +#define RTE_ADC_P12_PORT ADC_P12_PORT +#define RTE_ADC_P12_PIN ADC_P12_PIN +#endif +#define RTE_ADC_P12_MUX 1 + +#ifndef ADC_P13_LOC +#define RTE_ADC_P13_PORT 0 +#define RTE_ADC_P13_PIN 11 +#else +#define RTE_ADC_P13_PORT ADC_P13_PORT +#define RTE_ADC_P13_PIN ADC_P13_PIN +#endif +#define RTE_ADC_P13_MUX 1 + +#ifndef ADC_P14_LOC +#define RTE_ADC_P14_PORT 0 +#define RTE_ADC_P14_PIN 9 +#else +#define RTE_ADC_P14_PORT ADC_P14_PORT +#define RTE_ADC_P14_PIN ADC_P14_PIN +#endif +#define RTE_ADC_P14_MUX 1 + +#ifndef ADC_P15_LOC +#define RTE_ADC_P15_PORT 0 +#define RTE_ADC_P15_PIN 7 +#else +#define RTE_ADC_P15_PORT ADC_P15_PORT +#define RTE_ADC_P15_PIN ADC_P15_PIN +#endif +#define RTE_ADC_P15_MUX 1 + +#ifndef ADC_P16_LOC +#define RTE_ADC_P16_PORT 0 +#define RTE_ADC_P16_PIN 26 +#else +#define RTE_ADC_P16_PORT ADC_P16_PORT +#define RTE_ADC_P16_PIN ADC_P16_PIN +#endif +#define RTE_ADC_P16_MUX 1 +#define RTE_ADC_P16_PAD 0 + +#ifndef ADC_P17_LOC +#define RTE_ADC_P17_PORT 0 +#define RTE_ADC_P17_PIN 28 +#else +#define RTE_ADC_P17_PORT ADC_P17_PORT +#define RTE_ADC_P17_PIN ADC_P17_PIN +#endif +#define RTE_ADC_P17_MUX 1 +#define RTE_ADC_P17_PAD 0 + +#ifndef ADC_P18_LOC +#define RTE_ADC_P18_PORT 0 +#define RTE_ADC_P18_PIN 30 +#else +#define RTE_ADC_P18_PORT ADC_P18_PORT +#define RTE_ADC_P18_PIN ADC_P18_PIN +#endif +#define RTE_ADC_P18_MUX 1 +#define RTE_ADC_P18_PAD 0 + +//ADC END + +//COMPARATOR START + +#ifndef COMP1_P0_LOC +#define RTE_COMP1_P0_PORT 0 +#define RTE_COMP1_P0_PIN 0 +#else +#define RTE_COMP1_P0_PORT COMP1_P0_PORT +#define RTE_COMP1_P0_PIN COMP1_P0_PIN +#endif +#define RTE_COMP1_P0_MUX 0 + +#ifndef COMP1_N0_LOC +#define RTE_COMP1_N0_PORT 0 +#define RTE_COMP1_N0_PIN 1 +#else +#define RTE_COMP1_N0_PORT COMP1_N0_PORT +#define RTE_COMP1_N0_PIN COMP1_N0_PIN +#endif +#define RTE_COMP1_N0_MUX 0 + +#ifndef COMP1_P1_LOC +#define RTE_COMP1_P1_PORT 0 +#define RTE_COMP1_P1_PIN 5 +#else +#define RTE_COMP1_P1_PORT COMP1_P1_PORT +#define RTE_COMP1_P1_PIN COMP1_P1_PIN +#endif +#define RTE_COMP1_P1_MUX 0 + +#ifndef COMP1_N1_LOC +#define RTE_COMP1_N1_PORT 0 +#define RTE_COMP1_N1_PIN 4 +#else +#define RTE_COMP1_N1_PORT COMP1_N1_PORT +#define RTE_COMP1_N1_PIN COMP1_N1_PIN +#endif +#define RTE_COMP1_N1_MUX 0 + +#ifndef COMP2_P0_LOC +#define RTE_COMP2_P0_PORT 0 +#define RTE_COMP2_P0_PIN 2 +#else +#define RTE_COMP2_P0_PORT COMP2_P0_PORT +#define RTE_COMP2_P0_PIN COMP2_P0_PIN +#endif +#define RTE_COMP2_P0_MUX 0 + +#ifndef COMP2_N0_LOC +#define RTE_COMP2_N0_PORT 0 +#define RTE_COMP2_N0_PIN 3 +#else +#define RTE_COMP2_N0_PORT COMP2_N0_PORT +#define RTE_COMP2_N0_PIN COMP2_N0_PIN +#endif +#define RTE_COMP2_N0_MUX 0 + +#ifndef COMP2_P1_LOC +#define RTE_COMP2_P1_PORT 0 +#define RTE_COMP2_P1_PIN 27 +#else +#define RTE_COMP2_P1_PORT COMP2_P1_PORT +#define RTE_COMP2_P1_PIN COMP2_P1_PIN +#endif +#define RTE_COMP2_P1_MUX 0 +#define RTE_COMP2_P1_PAD 0 + +#ifndef COMP2_N1_LOC +#define RTE_COMP2_N1_PORT 0 +#define RTE_COMP2_N1_PIN 28 +#else +#define RTE_COMP2_N1_PORT COMP2_N1_PORT +#define RTE_COMP2_N1_PIN COMP2_N1_PIN +#endif +#define RTE_COMP2_N1_MUX 0 + +//COMPARATOR END + #define RTE_GPIO_6_PORT 0 #define RTE_GPIO_6_PAD 1 #define RTE_GPIO_6_PIN 6 @@ -3031,4 +4872,21 @@ #define RTE_UULP_GPIO_4_PORT 5 #define RTE_UULP_GPIO_4_PIN 4 -#define RTE_UULP_GPIO_4_MODE 0 \ No newline at end of file +#define RTE_UULP_GPIO_4_MODE 0 + +#define RTE_UULP_GPIO_5_PIN 5 +#define RTE_UULP_GPIO_5_MODE 0 + +// UULP GPIO as enable pin for sensors +#define SENSOR_ENABLE_GPIO_MAPPED_TO_UULP +#define SENSOR_ENABLE_GPIO_PIN RTE_UULP_GPIO_1_PIN + +// Memlcd GPIOs +#define RTE_MEMLCD_CS_PIN 10 // Memlcd SPI CS pin +#define RTE_MEMLCD_CS_PORT 0 // Memlcd SPI CS port + +#define RTE_MEMLCD_EXTCOMIN_PIN 3 // Memlcd external communication pin +#define RTE_MEMLCD_EXTCOMIN_PORT 0 // Memlcd external communication port + +#define RTE_MEMLCD_ENABLE_DISPLAY_PIN 0 // Memlcd display enable pin +#define RTE_MEMLCD_ENABLE_DISPLAY_PORT 0 // Memlcd display enable port diff --git a/components/board/silabs/config/brd4342a/RTE_Device_917.h b/components/board/silabs/config/brd4342a/RTE_Device_917.h index f7c99111c..a0dfaad55 100644 --- a/components/board/silabs/config/brd4342a/RTE_Device_917.h +++ b/components/board/silabs/config/brd4342a/RTE_Device_917.h @@ -17,7 +17,7 @@ * * 3. This notice may not be removed or altered from any source distribution. * - * $Date: 1. December 2016 + * $Date: 1. June 2024 * $Revision: V2.4.4 * * Project: RTE Device Configuration for Si91x 2.0 B0 BRD4342A @@ -47,7 +47,7 @@ #define RTE_BUTTON1_PIN (11U) #define RTE_BUTTON1_PAD 6 -#define RTE_LED0_PORT 0 +#define RTE_LED0_PORT 4 #define RTE_LED0_NUMBER 0 #define RTE_LED0_PIN (2U) @@ -63,7 +63,7 @@ #define RTE_USART0 1 -#define RTE_USART0_CLK_SRC USART_INTFPLLCLK +#define RTE_USART0_CLK_SRC USART_ULPREFCLK #define RTE_USART0_CLK_DIV_FACT 1 #define RTE_USART0_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER @@ -111,19 +111,26 @@ #else //Pintool data #define RTE_USART0_CLK_PORT USART0_CLK_PORT -#define RTE_USART0_CLK_PIN USART0_CLK_PIN #if (USART0_CLK_LOC == 0) +#define RTE_USART0_CLK_PIN USART0_CLK_PIN #define RTE_USART0_CLK_MUX 2 #define RTE_USART0_CLK_PAD 3 #endif #if (USART0_CLK_LOC == 1) +#define RTE_USART0_CLK_PIN USART0_CLK_PIN #define RTE_USART0_CLK_MUX 2 #define RTE_USART0_CLK_PAD 0 //NO PAD #endif #if (USART0_CLK_LOC == 2) +#define RTE_USART0_CLK_PIN USART0_CLK_PIN #define RTE_USART0_CLK_MUX 2 #define RTE_USART0_CLK_PAD 16 #endif +#if (USART0_CLK_LOC == 3) +#define RTE_USART0_CLK_PIN (USART0_CLK_PIN + GPIO_MAX_PIN) +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 22 +#endif //Pintool data #endif @@ -162,22 +169,27 @@ #else //Pintool data #define RTE_USART0_TX_PORT USART0_TX_PORT -#if (USART0_TX_LOC == 0) +#if (USART0_TX_LOC == 4) #define RTE_USART0_TX_PIN USART0_TX_PIN #define RTE_USART0_TX_MUX 2 #define RTE_USART0_TX_PAD 8 #endif -#if (USART0_TX_LOC == 1) +#if (USART0_TX_LOC == 5) #define RTE_USART0_TX_PIN USART0_TX_PIN #define RTE_USART0_TX_MUX 2 #define RTE_USART0_TX_PAD 0 //NO PAD #endif -#if (USART0_TX_LOC == 2) +#if (USART0_TX_LOC == 6) #define RTE_USART0_TX_PIN USART0_TX_PIN #define RTE_USART0_TX_MUX 2 #define RTE_USART0_TX_PAD 18 #endif -#if (USART0_TX_LOC == 3) +#if (USART0_TX_LOC == 7) +#define RTE_USART0_TX_PIN (USART0_TX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 26 +#endif +#if (USART0_TX_LOC == 8) #define RTE_USART0_TX_PIN (USART0_TX_PIN + GPIO_MAX_PIN) #define RTE_USART0_TX_MUX 4 #define RTE_USART0_TX_PAD 29 @@ -213,7 +225,7 @@ #define RTE_USART0_RX_PORT 0 #define RTE_USART0_RX_PIN 65 #define RTE_USART0_RX_MUX 2 -#define RTE_USART0_RX_PAD 24 +#define RTE_USART0_RX_PAD 23 #elif (RTE_USART0_RX_PORT_ID == 4) #define RTE_USART0_RX_PORT 0 #define RTE_USART0_RX_PIN 70 @@ -225,27 +237,27 @@ #else //Pintool data #define RTE_USART0_RX_PORT USART0_RX_PORT -#if (USART0_RX_LOC == 0) +#if (USART0_RX_LOC == 9) #define RTE_USART0_RX_PIN USART0_RX_PIN #define RTE_USART0_RX_MUX 2 #define RTE_USART0_RX_PAD 5 #endif -#if (USART0_RX_LOC == 1) +#if (USART0_RX_LOC == 10) #define RTE_USART0_RX_PIN USART0_RX_PIN #define RTE_USART0_RX_MUX 2 #define RTE_USART0_RX_PAD 0 //no pad #endif -#if (USART0_RX_LOC == 2) +#if (USART0_RX_LOC == 11) #define RTE_USART0_RX_PIN USART0_RX_PIN #define RTE_USART0_RX_MUX 2 #define RTE_USART0_RX_PAD 19 #endif -#if (USART0_RX_LOC == 3) +#if (USART0_RX_LOC == 12) #define RTE_USART0_RX_PIN (USART0_RX_PIN + GPIO_MAX_PIN) #define RTE_USART0_RX_MUX 2 -#define RTE_USART0_RX_PAD 24 +#define RTE_USART0_RX_PAD 23 #endif -#if (USART0_RX_LOC == 4) +#if (USART0_RX_LOC == 13) #define RTE_USART0_RX_PIN (USART0_RX_PIN + GPIO_MAX_PIN) #define RTE_USART0_RX_MUX 4 #define RTE_USART0_RX_PAD 28 @@ -284,22 +296,22 @@ #else //Pintool data #define RTE_USART0_CTS_PORT USART0_CTS_PORT -#if (USART0_CTS_LOC == 0) +#if (USART0_CTS_LOC == 14) #define RTE_USART0_CTS_PIN USART0_CTS_PIN #define RTE_USART0_CTS_MUX 2 #define RTE_USART0_CTS_PAD 1 #endif -#if (USART0_CTS_LOC == 1) +#if (USART0_CTS_LOC == 15) #define RTE_USART0_CTS_PIN USART0_CTS_PIN #define RTE_USART0_CTS_MUX 2 #define RTE_USART0_CTS_PAD 0 //NO PAD #endif -#if (USART0_CTS_LOC == 2) +#if (USART0_CTS_LOC == 16) #define RTE_USART0_CTS_PIN USART0_CTS_PIN #define RTE_USART0_CTS_MUX 2 #define RTE_USART0_CTS_PAD 20 #endif -#if (USART0_CTS_LOC == 3) +#if (USART0_CTS_LOC == 17) #define RTE_USART0_CTS_PIN (USART0_CTS_PIN + GPIO_MAX_PIN) #define RTE_USART0_CTS_MUX 2 #define RTE_USART0_CTS_PAD 28 @@ -333,19 +345,26 @@ #else //Pintool data #define RTE_USART0_RTS_PORT USART0_RTS_PORT -#define RTE_USART0_RTS_PIN USART0_RTS_PIN -#if (USART0_RTS_LOC == 0) +#if (USART0_RTS_LOC == 18) +#define RTE_USART0_RTS_PIN USART0_RTS_PIN #define RTE_USART0_RTS_MUX 2 #define RTE_USART0_RTS_PAD 4 #endif -#if (USART0_RTS_LOC == 1) +#if (USART0_RTS_LOC == 19) +#define RTE_USART0_RTS_PIN USART0_RTS_PIN #define RTE_USART0_RTS_MUX 2 #define RTE_USART0_RTS_PAD 0 //NO PAD #endif -#if (USART0_RTS_LOC == 2) +#if (USART0_RTS_LOC == 20) +#define RTE_USART0_RTS_PIN USART0_RTS_PIN #define RTE_USART0_RTS_MUX 2 #define RTE_USART0_RTS_PAD 17 #endif +#if (USART0_RTS_LOC == 21) +#define RTE_USART0_RTS_PIN (USART0_RTS_PIN + GPIO_MAX_PIN) +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 27 +#endif //Pintool data #endif @@ -378,12 +397,22 @@ #else //Pintool data #define RTE_USART0_IR_TX_PORT USART0_IRTX_PORT -#if (USART0_IRTX_LOC == 0) +#if (USART0_IRTX_LOC == 22) +#define RTE_USART0_IR_TX_PIN USART0_IRTX_PIN +#define RTE_USART0_IR_TX_MUX 13 +#define RTE_USART0_IR_TX_PAD 0 //No pad +#endif +#if (USART0_IRTX_LOC == 23) #define RTE_USART0_IR_TX_PIN USART0_IRTX_PIN #define RTE_USART0_IR_TX_MUX 2 #define RTE_USART0_IR_TX_PAD 12 #endif -#if (USART0_IRTX_LOC == 1) +#if (USART0_IRTX_LOC == 24) +#define RTE_USART0_IR_TX_PIN (USART0_IRTX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_IR_TX_MUX 11 +#define RTE_USART0_IR_TX_PAD 23 +#endif +#if (USART0_IRTX_LOC == 25) #define RTE_USART0_IR_TX_PIN (USART0_IRTX_PIN + GPIO_MAX_PIN) #define RTE_USART0_IR_TX_MUX 2 #define RTE_USART0_IR_TX_PAD 30 @@ -420,12 +449,22 @@ #else //Pintool data #define RTE_USART0_IR_RX_PORT USART0_IRRX_PORT -#if (USART0_IRRX_LOC == 0) +#if (USART0_IRRX_LOC == 26) +#define RTE_USART0_IR_RX_PIN USART0_IRRX_PIN +#define RTE_USART0_IR_RX_MUX 13 +#define RTE_USART0_IR_RX_PAD 0 //no pad +#endif +#if (USART0_IRRX_LOC == 27) #define RTE_USART0_IR_RX_PIN USART0_IRRX_PIN #define RTE_USART0_IR_RX_MUX 2 #define RTE_USART0_IR_RX_PAD 11 #endif -#if (USART0_IRRX_LOC == 1) +#if (USART0_IRRX_LOC == 28) +#define RTE_USART0_IR_RX_PIN (USART0_IRRX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_IR_RX_MUX 11 +#define RTE_USART0_IR_RX_PAD 22 +#endif +#if (USART0_IRRX_LOC == 29) #define RTE_USART0_IR_RX_PIN (USART0_IRRX_PIN + GPIO_MAX_PIN) #define RTE_USART0_IR_RX_MUX 2 #define RTE_USART0_IR_RX_PAD 29 @@ -454,15 +493,21 @@ #else //Pintool data #define RTE_USART0_RI_PORT USART0_RI_PORT -#define RTE_USART0_RI_PIN USART0_RI_PIN -#if (USART0_RI_LOC == 0) +#if (USART0_RI_LOC == 30) +#define RTE_USART0_RI_PIN USART0_RI_PIN #define RTE_USART0_RI_MUX 2 #define RTE_USART0_RI_PAD 0 //no pad #endif -#if (USART0_RI_LOC == 1) +#if (USART0_RI_LOC == 31) +#define RTE_USART0_RI_PIN USART0_RI_PIN #define RTE_USART0_RI_MUX 2 #define RTE_USART0_RI_PAD 10 #endif +#if (USART0_RI_LOC == 32) +#define RTE_USART0_RI_PIN (USART0_RI_PIN + GPIO_MAX_PIN) +#define RTE_USART0_RI_MUX 11 +#define RTE_USART0_RI_PAD 26 +#endif //Pintool data #endif @@ -488,11 +533,11 @@ //Pintool data #define RTE_USART0_DSR_PORT USART0_DSR_PORT #define RTE_USART0_DSR_PIN USART0_DSR_PIN -#if (USART0_DSR_LOC == 0) +#if (USART0_DSR_LOC == 33) #define RTE_USART0_DSR_MUX 2 #define RTE_USART0_DSR_PAD 6 #endif -#if (USART0_DSR_LOC == 1) +#if (USART0_DSR_LOC == 34) #define RTE_USART0_DSR_MUX 2 #define RTE_USART0_DSR_PAD 21 #endif @@ -507,9 +552,14 @@ #else #define RTE_USART0_DCD_PORT USART0_DCD_PORT #define RTE_USART0_DCD_PIN USART0_DCD_PIN -#endif +#if (USART0_DCD_LOC == 35) #define RTE_USART0_DCD_MUX 2 #define RTE_USART0_DCD_PAD 7 +#elif (USART0_DCD_LOC == 36) +#define RTE_USART0_DCD_MUX 12 +#define RTE_USART0_DCD_PAD 0 +#endif +#endif // USART0_DTR <0=>P0_7 // DTR for USART0 @@ -528,7 +578,7 @@ // Configuration settings for Driver_UART1 in component ::CMSIS Driver:USART #define RTE_UART1 1 -#define RTE_UART1_CLK_SRC USART_INTFPLLCLK +#define RTE_UART1_CLK_SRC USART_ULPREFCLK #define RTE_UART1_CLK_DIV_FACT 1 #define RTE_UART1_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER @@ -602,8 +652,8 @@ #endif #if (UART1_TX_LOC == 2) #define RTE_UART1_TX_PIN (UART1_TX_PIN + GPIO_MAX_PIN) -#define RTE_UART1_TX_MUX 9 -#define RTE_UART1_TX_PAD 25 +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 27 #endif #if (UART1_TX_LOC == 3) #define RTE_UART1_TX_PIN (UART1_TX_PIN + GPIO_MAX_PIN) @@ -654,27 +704,27 @@ #else //Pintool data #define RTE_UART1_RX_PORT UART1_RX_PORT -#if (UART1_RX_LOC == 0) +#if (UART1_RX_LOC == 5) #define RTE_UART1_RX_PIN UART1_RX_PIN #define RTE_UART1_RX_MUX 6 #define RTE_UART1_RX_PAD 1 #endif -#if (UART1_RX_LOC == 1) +#if (UART1_RX_LOC == 6) #define RTE_UART1_RX_PIN UART1_RX_PIN #define RTE_UART1_RX_MUX 6 #define RTE_UART1_RX_PAD 0 //no pad #endif -#if (UART1_RX_LOC == 2) +#if (UART1_RX_LOC == 7) #define RTE_UART1_RX_PIN (UART1_RX_PIN + GPIO_MAX_PIN) -#define RTE_UART1_RX_MUX 9 -#define RTE_UART1_RX_PAD 24 +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 26 #endif -#if (UART1_RX_LOC == 3) +#if (UART1_RX_LOC == 8) #define RTE_UART1_RX_PIN (UART1_RX_PIN + GPIO_MAX_PIN) #define RTE_UART1_RX_MUX 6 #define RTE_UART1_RX_PAD 30 #endif -#if (UART1_RX_LOC == 4) +#if (UART1_RX_LOC == 9) #define RTE_UART1_RX_PIN (UART1_RX_PIN + GPIO_MAX_PIN) #define RTE_UART1_RX_MUX 9 #define RTE_UART1_RX_PAD 32 @@ -718,31 +768,36 @@ #else //Pintool data #define RTE_UART1_CTS_PORT UART1_CTS_PORT -#if (UART1_CTS_LOC == 0) +#if (UART1_CTS_LOC == 10) #define RTE_UART1_CTS_PIN UART1_CTS_PIN #define RTE_UART1_CTS_MUX 6 #define RTE_UART1_CTS_PAD 6 #endif -#if (UART1_CTS_LOC == 1) +#if (UART1_CTS_LOC == 11) #define RTE_UART1_CTS_PIN UART1_CTS_PIN #define RTE_UART1_CTS_MUX 6 #define RTE_UART1_CTS_PAD 0 //no pad #endif -#if (UART1_CTS_LOC == 2) +#if (UART1_CTS_LOC == 12) #define RTE_UART1_CTS_PIN UART1_CTS_PIN #define RTE_UART1_CTS_MUX 9 #define RTE_UART1_CTS_PAD 15 #endif -#if (UART1_CTS_LOC == 3) +#if (UART1_CTS_LOC == 13) #define RTE_UART1_CTS_PIN (UART1_CTS_PIN + GPIO_MAX_PIN) #define RTE_UART1_CTS_MUX 9 #define RTE_UART1_CTS_PAD 23 #endif -#if (UART1_CTS_LOC == 4) +#if (UART1_CTS_LOC == 14) #define RTE_UART1_CTS_PIN (UART1_CTS_PIN + GPIO_MAX_PIN) #define RTE_UART1_CTS_MUX 6 #define RTE_UART1_CTS_PAD 29 #endif +#if (UART1_CTS_LOC == 15) +#define RTE_UART1_CTS_PIN (UART1_CTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_CTS_MUX 9 +#define RTE_UART1_CTS_PAD 31 +#endif //Pintool data #endif @@ -786,27 +841,32 @@ #else //Pintool data #define RTE_UART1_RTS_PORT UART1_RTS_PORT -#if (UART1_RTS_LOC == 0) +#if (UART1_RTS_LOC == 16) #define RTE_UART1_RTS_PIN UART1_RTS_PIN #define RTE_UART1_RTS_MUX 6 #define RTE_UART1_RTS_PAD 5 #endif -#if (UART1_RTS_LOC == 1) +#if (UART1_RTS_LOC == 17) #define RTE_UART1_RTS_PIN UART1_RTS_PIN #define RTE_UART1_RTS_MUX 6 #define RTE_UART1_RTS_PAD 0 //no pad #endif -#if (UART1_RTS_LOC == 2) +#if (UART1_RTS_LOC == 18) #define RTE_UART1_RTS_PIN UART1_RTS_PIN #define RTE_UART1_RTS_MUX 9 #define RTE_UART1_RTS_PAD 14 #endif -#if (UART1_RTS_LOC == 3) +#if (UART1_RTS_LOC == 19) +#define RTE_UART1_RTS_PIN (UART1_RTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RTS_MUX 9 +#define RTE_UART1_RTS_PAD 22 +#endif +#if (UART1_RTS_LOC == 20) #define RTE_UART1_RTS_PIN (UART1_RTS_PIN + GPIO_MAX_PIN) #define RTE_UART1_RTS_MUX 6 #define RTE_UART1_RTS_PAD 28 #endif -#if (UART1_RTS_LOC == 4) +#if (UART1_RTS_LOC == 21) #define RTE_UART1_RTS_PIN (UART1_RTS_PIN + GPIO_MAX_PIN) #define RTE_UART1_RTS_MUX 9 #define RTE_UART1_RTS_PAD 30 @@ -918,7 +978,6 @@ #if (RTE_ULP_UART_RTS_PORT_ID == 0) #define RTE_ULP_UART_RTS_PORT 0 #define RTE_ULP_UART_RTS_PIN 10 -#define RTE_ULP_UART_RTS_MUX 8 #else #error "Invalid ULPSS UART RTE_ULP_UART_RTS_PIN Pin Configuration!" #endif @@ -935,7 +994,7 @@ #define RTE_SSI_MASTER 1 // SSI_MASTER_MISO Pin <0=>GPIO_12 <1=>GPIO_27 <2=>GPIO_57 -#ifndef SSI_MASTER_MISO_LOC +#ifndef SSI_MASTER_DATA1_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SSI_MASTER_MISO_PORT_ID 1 #else @@ -966,23 +1025,23 @@ #else //Pintool data #define RTE_SSI_MASTER_MISO 1 -#define RTE_SSI_MASTER_MISO_PORT SSI_MASTER_MISO__PORT -#define RTE_SSI_MASTER_MISO_PIN SSI_MASTER_MISO__PIN +#define RTE_SSI_MASTER_MISO_PORT SSI_MASTER_MISO_DATA1_PORT +#define RTE_SSI_MASTER_MISO_PIN SSI_MASTER_MISO_DATA1_PIN #define RTE_SSI_MASTER_MISO_MODE EGPIO_PIN_MUX_MODE3 -#if (SSI_MASTER_MISO_LOC == 0) +#if (SSI_MASTER_DATA1_LOC == 3) #define RTE_SSI_MASTER_MISO_PADSEL 7 #endif -#if (SSI_MASTER_MISO_LOC == 1) +#if (SSI_MASTER_DATA1_LOC == 4) #define RTE_SSI_MASTER_MISO_PADSEL 0 //NO PAD #endif -#if (SSI_MASTER_MISO_LOC == 2) +#if (SSI_MASTER_DATA1_LOC == 5) #define RTE_SSI_MASTER_MISO_PADSEL 21 #endif //Pintool data #endif // SSI_MASTER_MOSI Pin <0=>GPIO_11 <1=>GPIO_26 <2=>GPIO_56 -#ifndef SSI_MASTER_MOSI_LOC +#ifndef SSI_MASTER_DATA0_LOC #define RTE_SSI_MASTER_MOSI_PORT_ID 1 #if (RTE_SSI_MASTER_MOSI_PORT_ID == 0) @@ -1009,16 +1068,16 @@ #else //Pintool data #define RTE_SSI_MASTER_MOSI 1 -#define RTE_SSI_MASTER_MOSI_PORT SSI_MASTER_MOSI__PORT -#define RTE_SSI_MASTER_MOSI_PIN SSI_MASTER_MOSI__PIN +#define RTE_SSI_MASTER_MOSI_PORT SSI_MASTER_MOSI_DATA0_PORT +#define RTE_SSI_MASTER_MOSI_PIN SSI_MASTER_MOSI_DATA0_PIN #define RTE_SSI_MASTER_MOSI_MODE EGPIO_PIN_MUX_MODE3 -#if (SSI_MASTER_MOSI_LOC == 0) +#if (SSI_MASTER_DATA0_LOC == 0) #define RTE_SSI_MASTER_MOSI_PADSEL 6 #endif -#if (SSI_MASTER_MOSI_LOC == 1) +#if (SSI_MASTER_DATA0_LOC == 1) #define RTE_SSI_MASTER_MOSI_PADSEL 0 //NO PAD #endif -#if (SSI_MASTER_MOSI_LOC == 2) +#if (SSI_MASTER_DATA0_LOC == 2) #define RTE_SSI_MASTER_MOSI_PADSEL 20 #endif //Pintool data @@ -1055,13 +1114,13 @@ #define RTE_SSI_MASTER_SCK_PORT SSI_MASTER_SCK__PORT #define RTE_SSI_MASTER_SCK_PIN SSI_MASTER_SCK__PIN #define RTE_SSI_MASTER_SCK_MODE EGPIO_PIN_MUX_MODE3 -#if (SSI_MASTER_SCK_LOC == 0) +#if (SSI_MASTER_SCK_LOC == 6) #define RTE_SSI_MASTER_SCK_PADSEL 3 #endif -#if (SSI_MASTER_SCK_LOC == 1) +#if (SSI_MASTER_SCK_LOC == 7) #define RTE_SSI_MASTER_SCK_PADSEL 0 //NO PAD #endif -#if (SSI_MASTER_SCK_LOC == 2) +#if (SSI_MASTER_SCK_LOC == 8) #define RTE_SSI_MASTER_SCK_PADSEL 16 #endif //Pintool data @@ -1103,13 +1162,13 @@ #define RTE_SSI_MASTER_CS0_PORT SSI_MASTER_CS0__PORT #define RTE_SSI_MASTER_CS0_PIN SSI_MASTER_CS0__PIN #define RTE_SSI_MASTER_CS0_MODE EGPIO_PIN_MUX_MODE3 -#if (SSI_MASTER_CS0_LOC == 0) +#if (SSI_MASTER_CS0_LOC == 9) #define RTE_SSI_MASTER_CS0_PADSEL 4 #endif -#if (SSI_MASTER_CS0_LOC == 1) +#if (SSI_MASTER_CS0_LOC == 10) #define RTE_SSI_MASTER_CS0_PADSEL 0 //NO PAD #endif -#if (SSI_MASTER_CS0_LOC == 2) +#if (SSI_MASTER_CS0_LOC == 11) #define RTE_SSI_MASTER_CS0_PADSEL 17 #endif //Pintool data @@ -1156,10 +1215,10 @@ #define RTE_SSI_MASTER_CS2_PORT SSI_MASTER_CS2__PORT #define RTE_SSI_MASTER_CS2_PIN SSI_MASTER_CS2__PIN #define RTE_SSI_MASTER_CS2_MODE EGPIO_PIN_MUX_MODE3 -#if (SSI_MASTER_CS2_LOC == 0) +#if (SSI_MASTER_CS2_LOC == 13) #define RTE_SSI_MASTER_CS2_PADSEL 8 #endif -#if (SSI_MASTER_CS2_LOC == 1) +#if (SSI_MASTER_CS2_LOC == 14) #define RTE_SSI_MASTER_CS2_PADSEL 14 #endif //Pintool data @@ -1240,16 +1299,16 @@ #define RTE_SSI_SLAVE_MISO_PORT SSI_SLAVE_MISO__PORT #define RTE_SSI_SLAVE_MISO_PIN SSI_SLAVE_MISO__PIN #define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8 -#if (SSI_SLAVE_MISO_LOC == 1) +#if (SSI_SLAVE_MISO_LOC == 5) #define RTE_SSI_SLAVE_MISO_PADSEL 6 #endif -#if (SSI_SLAVE_MISO_LOC == 2) +#if (SSI_SLAVE_MISO_LOC == 6) #define RTE_SSI_SLAVE_MISO_PADSEL 0 //no pad #endif -#if (SSI_SLAVE_MISO_LOC == 3) +#if (SSI_SLAVE_MISO_LOC == 7) #define RTE_SSI_SLAVE_MISO_PADSEL 13 #endif -#if (SSI_SLAVE_MISO_LOC == 4) +#if (SSI_SLAVE_MISO_LOC == 8) #define RTE_SSI_SLAVE_MISO_PADSEL 21 #endif //Pintool data @@ -1352,16 +1411,16 @@ #define RTE_SSI_SLAVE_SCK_PORT SSI_SLAVE_SCK__PORT #define RTE_SSI_SLAVE_SCK_PIN SSI_SLAVE_SCK__PIN #define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8 -#if (SSI_SLAVE_SCK_LOC == 1) +#if (SSI_SLAVE_SCK_LOC == 9) #define RTE_SSI_SLAVE_SCK_PADSEL 3 #endif -#if (SSI_SLAVE_SCK_LOC == 2) +#if (SSI_SLAVE_SCK_LOC == 10) #define RTE_SSI_SLAVE_SCK_PADSEL 0 //no pad #endif -#if (SSI_SLAVE_SCK_LOC == 3) +#if (SSI_SLAVE_SCK_LOC == 11) #define RTE_SSI_SLAVE_SCK_PADSEL 11 #endif -#if (SSI_SLAVE_SCK_LOC == 4) +#if (SSI_SLAVE_SCK_LOC == 12) #define RTE_SSI_SLAVE_SCK_PADSEL 16 #endif //Pintool data @@ -1406,16 +1465,16 @@ #define RTE_SSI_SLAVE_CS_PORT SSI_SLAVE_CS0__PORT #define RTE_SSI_SLAVE_CS_PIN SSI_SLAVE_CS0__PIN #define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8 -#if (SSI_SLAVE_CS0_LOC == 1) +#if (SSI_SLAVE_CS0_LOC == 13) #define RTE_SSI_SLAVE_CS_PADSEL 4 #endif -#if (SSI_SLAVE_CS0_LOC == 2) +#if (SSI_SLAVE_CS0_LOC == 14) #define RTE_SSI_SLAVE_CS_PADSEL 0 //no pad #endif -#if (SSI_SLAVE_CS0_LOC == 3) +#if (SSI_SLAVE_CS0_LOC == 15) #define RTE_SSI_SLAVE_CS_PADSEL 10 #endif -#if (SSI_SLAVE_CS0_LOC == 4) +#if (SSI_SLAVE_CS0_LOC == 16) #define RTE_SSI_SLAVE_CS_PADSEL 17 #endif //Pintool data @@ -1437,7 +1496,7 @@ // -// SSI_ULP_MASTER (Serial Peripheral Interface 3) [Driver_SSI_ULP_MASTER] +// ULP SPI Peripheral (Serial Peripheral Interface 3) [Driver_SSI_ULP_MASTER] // Configuration settings for Driver_SSI_ULP_MASTER in component ::CMSIS Driver:SPI #define RTE_SSI_ULP_MASTER 1 @@ -1447,7 +1506,7 @@ #define ULP_SSI_CS2 0 // SSI_ULP_MASTER_MISO Pin <0=>Not Used <1=>ULP_GPIO_2 <2=>ULP_GPIO_9 -#ifndef SSI_ULP_MASTER_MISO_LOC +#ifndef ULP_SPI_MISO_LOC #define RTE_SSI_ULP_MASTER_MISO_PORT_ID 0 #if (RTE_SSI_ULP_MASTER_MISO_PORT_ID == 0) #define RTE_SSI_ULP_MASTER_MISO 1 @@ -1465,14 +1524,14 @@ #else //Pintool data #define RTE_SSI_ULP_MASTER_MISO 1 -#define RTE_SSI_ULP_MASTER_MISO_PORT SSI_ULP_MASTER_MISO__PORT -#define RTE_SSI_ULP_MASTER_MISO_PIN SSI_ULP_MASTER_MISO__PIN +#define RTE_SSI_ULP_MASTER_MISO_PORT ULP_SPI_MISO__PORT +#define RTE_SSI_ULP_MASTER_MISO_PIN ULP_SPI_MISO__PIN #define RTE_SSI_ULP_MASTER_MISO_MODE 1 //Pintool data #endif // SSI_ULP_MASTER_MOSI Pin <0=>Not Used <1=>ULP_GPIO_1 <2=>ULP_GPIO_11 -#ifndef SSI_ULP_MASTER_MOSI_LOC +#ifndef ULP_SPI_MOSI_LOC #define RTE_SSI_ULP_MASTER_MOSI_PORT_ID 0 #if (RTE_SSI_ULP_MASTER_MOSI_PORT_ID == 0) #define RTE_SSI_ULP_MASTER_MOSI 1 @@ -1490,14 +1549,14 @@ #else //Pintool data #define RTE_SSI_ULP_MASTER_MOSI 1 -#define RTE_SSI_ULP_MASTER_MOSI_PORT SSI_ULP_MASTER_MOSI__PORT -#define RTE_SSI_ULP_MASTER_MOSI_PIN SSI_ULP_MASTER_MOSI__PIN +#define RTE_SSI_ULP_MASTER_MOSI_PORT ULP_SPI_MOSI__PORT +#define RTE_SSI_ULP_MASTER_MOSI_PIN ULP_SPI_MOSI__PIN #define RTE_SSI_ULP_MASTER_MOSI_MODE 1 //Pintool data #endif // SSI_ULP_MASTER_SCK Pin <0=>Not Used <1=>ULP_GPIO_0 <2=>ULP_GPIO_8 -#ifndef SSI_ULP_MASTER_SCK_LOC +#ifndef ULP_SPI_SCK_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SSI_ULP_MASTER_SCK_PORT_ID 2 #else @@ -1521,14 +1580,14 @@ #else //Pintool data #define RTE_SSI_ULP_MASTER_SCK 1 -#define RTE_SSI_ULP_MASTER_SCK_PORT SSI_ULP_MASTER_SCK__PORT -#define RTE_SSI_ULP_MASTER_SCK_PIN SSI_ULP_MASTER_SCK__PIN +#define RTE_SSI_ULP_MASTER_SCK_PORT ULP_SPI_SCK__PORT +#define RTE_SSI_ULP_MASTER_SCK_PIN ULP_SPI_SCK__PIN #define RTE_SSI_ULP_MASTER_SCK_MODE 1 //Pintool data #endif // CS0 -#ifndef SSI_ULP_MASTER_CS0_LOC +#ifndef ULP_SPI_CS0_LOC #define RTE_SSI_ULP_MASTER_CS0_PORT_ID 1 #if (RTE_SSI_ULP_MASTER_CS0_PORT_ID == 0) #define RTE_SSI_ULP_MASTER_CS0 ULP_SSI_CS0 @@ -1546,30 +1605,30 @@ #else //Pintool data #define RTE_SSI_ULP_MASTER_CS0 ULP_SSI_CS0 -#define RTE_SSI_ULP_MASTER_CS0_PORT SSI_ULP_MASTER_CS0__PORT -#define RTE_SSI_ULP_MASTER_CS0_PIN SSI_ULP_MASTER_CS0__PIN +#define RTE_SSI_ULP_MASTER_CS0_PORT ULP_SPI_CS0__PORT +#define RTE_SSI_ULP_MASTER_CS0_PIN ULP_SPI_CS0__PIN #define RTE_SSI_ULP_MASTER_CS0_MODE 1 //Pintool data #endif // CS1 -#ifndef SSI_ULP_MASTER_CS1_LOC +#ifndef ULP_SPI_CS1_LOC #define RTE_SSI_ULP_MASTER_CS1_PORT 0 #define RTE_SSI_ULP_MASTER_CS1_PIN 4 #else -#define RTE_SSI_ULP_MASTER_CS1_PORT SSI_ULP_MASTER_CS1__PORT -#define RTE_SSI_ULP_MASTER_CS1_PIN SSI_ULP_MASTER_CS1__PIN +#define RTE_SSI_ULP_MASTER_CS1_PORT ULP_SPI_CS1__PORT +#define RTE_SSI_ULP_MASTER_CS1_PIN ULP_SPI_CS1__PIN #endif #define RTE_SSI_ULP_MASTER_CS1 ULP_SSI_CS1 #define RTE_SSI_ULP_MASTER_CS1_MODE 1 // CS2 -#ifndef SSI_ULP_MASTER_CS2_LOC +#ifndef ULP_SPI_CS2_LOC #define RTE_SSI_ULP_MASTER_CS2_PORT 0 #define RTE_SSI_ULP_MASTER_CS2_PIN 6 #else -#define RTE_SSI_ULP_MASTER_CS2_PORT SSI_ULP_MASTER_CS2__PORT -#define RTE_SSI_ULP_MASTER_CS2_PIN SSI_ULP_MASTER_CS2__PIN +#define RTE_SSI_ULP_MASTER_CS2_PORT ULP_SPI_CS2__PORT +#define RTE_SSI_ULP_MASTER_CS2_PIN ULP_SPI_CS2__PIN #endif #define RTE_SSI_ULP_MASTER_CS2 ULP_SSI_CS2 #define RTE_SSI_ULP_MASTER_CS2_MODE 1 @@ -1711,16 +1770,16 @@ #define RTE_I2S0_WSCLK_PORT I2S0_WSCLK_PORT #define RTE_I2S0_WSCLK_PIN I2S0_WSCLK_PIN #define RTE_I2S0_WSCLK_MUX 7 -#if (I2S0_WSCLK_LOC == 0) +#if (I2S0_WSCLK_LOC == 4) #define RTE_I2S0_WSCLK_PAD 4 #endif -#if (I2S0_WSCLK_LOC == 1) +#if (I2S0_WSCLK_LOC == 5) #define RTE_I2S0_WSCLK_PAD 0 #endif -#if (I2S0_WSCLK_LOC == 2) +#if (I2S0_WSCLK_LOC == 6) #define RTE_I2S0_WSCLK_PAD 11 #endif -#if (I2S0_WSCLK_LOC == 3) +#if (I2S0_WSCLK_LOC == 7) #define RTE_I2S0_WSCLK_PAD 17 #endif //Pintool data @@ -1759,16 +1818,16 @@ #define RTE_I2S0_DOUT0_PORT I2S0_DOUT0_PORT #define RTE_I2S0_DOUT0_PIN I2S0_DOUT0_PIN #define RTE_I2S0_DOUT0_MUX 7 -#if (I2S0_DOUT0_LOC == 0) +#if (I2S0_DOUT0_LOC == 8) #define RTE_I2S0_DOUT0_PAD 6 #endif -#if (I2S0_DOUT0_LOC == 1) +#if (I2S0_DOUT0_LOC == 9) #define RTE_I2S0_DOUT0_PAD 0 #endif -#if (I2S0_DOUT0_LOC == 2) +#if (I2S0_DOUT0_LOC == 10) #define RTE_I2S0_DOUT0_PAD 13 #endif -#if (I2S0_DOUT0_LOC == 3) +#if (I2S0_DOUT0_LOC == 11) #define RTE_I2S0_DOUT0_PAD 21 #endif //Pintool data @@ -1807,16 +1866,16 @@ #define RTE_I2S0_DIN0_PORT I2S0_DIN0_PORT #define RTE_I2S0_DIN0_PIN I2S0_DIN0_PIN #define RTE_I2S0_DIN0_MUX 7 -#if (I2S0_DIN0_LOC == 0) +#if (I2S0_DIN0_LOC == 12) #define RTE_I2S0_DIN0_PAD 5 #endif -#if (I2S0_DIN0_LOC == 1) +#if (I2S0_DIN0_LOC == 13) #define RTE_I2S0_DIN0_PAD 0 #endif -#if (I2S0_DIN0_LOC == 2) +#if (I2S0_DIN0_LOC == 14) #define RTE_I2S0_DIN0_PAD 12 #endif -#if (I2S0_DIN0_LOC == 3) +#if (I2S0_DIN0_LOC == 15) #define RTE_I2S0_DIN0_PAD 20 #endif //Pintool data @@ -1859,16 +1918,16 @@ #define RTE_I2S0_DOUT1_PORT I2S0_DOUT1_PORT #define RTE_I2S0_DOUT1_PIN I2S0_DOUT1_PIN #define RTE_I2S0_DOUT1_MUX 7 -#if (I2S0_DOUT1_LOC == 0) +#if (I2S0_DOUT1_LOC == 16) #define RTE_I2S0_DOUT1_PAD 2 #endif -#if (I2S0_DOUT1_LOC == 1) +#if (I2S0_DOUT1_LOC == 17) #define RTE_I2S0_DOUT1_PAD 0 #endif -#if (I2S0_DOUT1_LOC == 2) +#if (I2S0_DOUT1_LOC == 18) #define RTE_I2S0_DOUT1_PAD 15 #endif -#if (I2S0_DOUT1_LOC == 3) +#if (I2S0_DOUT1_LOC == 19) #define RTE_I2S0_DOUT1_PAD 19 #endif //Pintool data @@ -1907,22 +1966,22 @@ #define RTE_I2S0_DIN1_PORT I2S0_DIN1_PORT #define RTE_I2S0_DIN1_PIN I2S0_DIN1_PIN #define RTE_I2S0_DIN1_MUX 7 -#if (I2S0_DIN1_LOC == 0) +#if (I2S0_DIN1_LOC == 20) #define RTE_I2S0_DIN1_PAD 1 #endif -#if (I2S0_DIN1_LOC == 1) +#if (I2S0_DIN1_LOC == 21) #define RTE_I2S0_DIN1_PAD 0 #endif -#if (I2S0_DIN1_LOC == 2) +#if (I2S0_DIN1_LOC == 22) #define RTE_I2S0_DIN1_PAD 14 #endif -#if (I2S0_DIN1_LOC == 3) +#if (I2S0_DIN1_LOC == 23) #define RTE_I2S0_DIN1_PAD 18 #endif //Pintool data #endif -// FIFO level can have value 1 to 7 -#define I2S0_TX_FIFO_LEVEL (2U) +// FIFO level can have value 0 to 7 +#define I2S0_TX_FIFO_LEVEL (0U) #define I2S0_RX_FIFO_LEVEL (2U) // I2S0_TX_RES <0=>12 @@ -1970,14 +2029,14 @@ // -// I2S1 [Driver_I2S1] +// ULP I2S [Driver_I2S1] // Configuration settings for Driver_I2S1 in component ::Drivers:I2S #define RTE_I2S1 1 #define I2S1_IRQHandler IRQ014_Handler // I2S1_SCLK Pin <0=>P0_3 <1=>P0_7 <2=>P0_8 /*I2S1 PINS*/ -#ifndef I2S1_SCLK_LOC +#ifndef ULP_I2S_SCLK_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_I2S1_SCLK_PORT_ID 0 #else @@ -2000,14 +2059,14 @@ #endif #else //Pintool data -#define RTE_I2S1_SCLK_PORT I2S1_SCLK_PORT -#define RTE_I2S1_SCLK_PIN I2S1_SCLK_PIN +#define RTE_I2S1_SCLK_PORT ULP_I2S_SCLK_PORT +#define RTE_I2S1_SCLK_PIN ULP_I2S_SCLK_PIN #define RTE_I2S1_SCLK_MUX 2 //Pintool data #endif // I2S1_WSCLK Pin <0=>P0_2 <1=>P0_4 <2=>P0_10 -#ifndef I2S1_WSCLK_LOC +#ifndef ULP_I2S_WSCLK_LOC #define RTE_I2S1_WSCLK_PORT_ID 0 #if (RTE_I2S1_WSCLK_PORT_ID == 0) #define RTE_I2S1_WSCLK_PORT 0 @@ -2022,14 +2081,14 @@ #endif #else //Pintool data -#define RTE_I2S1_WSCLK_PORT I2S1_WSCLK_PORT -#define RTE_I2S1_WSCLK_PIN I2S1_WSCLK_PIN +#define RTE_I2S1_WSCLK_PORT ULP_I2S_WSCLK_PORT +#define RTE_I2S1_WSCLK_PIN ULP_I2S_WSCLK_PIN #define RTE_I2S1_WSCLK_MUX 2 //Pintool data #endif // I2S1_DOUT0 Pin <0=>P0_1 <1=>P0_5 <2=>P0_11 -#ifndef I2S1_DOUT0_LOC +#ifndef ULP_I2S_DOUT0_LOC #define RTE_I2S1_DOUT0_PORT_ID 0 #if (RTE_I2S1_DOUT0_PORT_ID == 0) #define RTE_I2S1_DOUT0_PORT 0 @@ -2044,14 +2103,14 @@ #endif #else //Pintool data -#define RTE_I2S1_DOUT0_PORT I2S1_DOUT0_PORT -#define RTE_I2S1_DOUT0_PIN I2S1_DOUT0_PIN +#define RTE_I2S1_DOUT0_PORT ULP_I2S_DOUT0_PORT +#define RTE_I2S1_DOUT0_PIN ULP_I2S_DOUT0_PIN #define RTE_I2S1_DOUT0_MUX 2 //Pintool data #endif // I2S1_DIN0 Pin <0=>P0_0 <1=>P0_6 <2=>P0_9 <3=>P0_13 -#ifndef I2S1_DIN0_LOC +#ifndef ULP_I2S_DIN0_LOC #define RTE_I2S1_DIN0_PORT_ID 1 #if (RTE_I2S1_DIN0_PORT_ID == 0) #define RTE_I2S1_DIN0_PORT 0 @@ -2070,14 +2129,14 @@ #endif #else //Pintool data -#define RTE_I2S1_DIN0_PORT I2S1_DIN0_PORT -#define RTE_I2S1_DIN0_PIN I2S1_DIN0_PIN +#define RTE_I2S1_DIN0_PORT ULP_I2S_DIN0_PORT +#define RTE_I2S1_DIN0_PIN ULP_I2S_DIN0_PIN #define RTE_I2S1_DIN0_MUX 2 //Pintool data #endif -// FIFO level can have value 1 to 7 -#define I2S1_TX_FIFO_LEVEL (2U) +// FIFO level can have value 0 to 7 +#define I2S1_TX_FIFO_LEVEL (0U) #define I2S1_RX_FIFO_LEVEL (2U) // I2S1_TX_RES <0=>12 @@ -2180,12 +2239,6 @@ #if (I2C0_SCL_LOC == 2) #define RTE_I2C0_SCL_PIN (I2C0_SCL_PIN + GPIO_MAX_PIN) #define RTE_I2C0_SCL_MUX 4 -#define RTE_I2C0_SCL_PAD 24 -#define RTE_I2C0_SCL_I2C_REN 2 -#endif -#if (I2C0_SCL_LOC == 3) -#define RTE_I2C0_SCL_PIN (I2C0_SCL_PIN + GPIO_MAX_PIN) -#define RTE_I2C0_SCL_MUX 4 #define RTE_I2C0_SCL_PAD 33 #define RTE_I2C0_SCL_I2C_REN 11 #endif @@ -2224,19 +2277,19 @@ #else //Pintool data #define RTE_I2C0_SDA_PORT I2C0_SDA_PORT -#if (I2C0_SDA_LOC == 0) +#if (I2C0_SDA_LOC == 3) #define RTE_I2C0_SDA_PIN I2C0_SDA_PIN #define RTE_I2C0_SDA_MUX 4 #define RTE_I2C0_SDA_PAD 1 #define RTE_I2C0_SDA_I2C_REN 6 #endif -#if (I2C0_SDA_LOC == 1) +#if (I2C0_SDA_LOC == 4) #define RTE_I2C0_SDA_PIN (I2C0_SDA_PIN + GPIO_MAX_PIN) #define RTE_I2C0_SDA_MUX 4 -#define RTE_I2C0_SDA_PAD 25 +#define RTE_I2C0_SDA_PAD 22 #define RTE_I2C0_SDA_I2C_REN 3 #endif -#if (I2C0_SDA_LOC == 2) +#if (I2C0_SDA_LOC == 5) #define RTE_I2C0_SDA_PIN (I2C0_SDA_PIN + GPIO_MAX_PIN) #define RTE_I2C0_SDA_MUX 4 #define RTE_I2C0_SDA_PAD 32 @@ -2253,7 +2306,7 @@ #define DMA_TX_TL 1 #define DMA_RX_TL 1 #endif -// I2C0 [Driver_I2C0] +// I2C1 [Driver_I2C0] // I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1] // Configuration settings for Driver_I2C1 in component ::Drivers:I2C @@ -2330,13 +2383,13 @@ #define RTE_I2C1_SCL_PAD 18 #define RTE_I2C1_SCL_REN 54 #endif -#if (I2C1_SCL_LOC == 5) +#if (I2C1_SCL_LOC == 4) #define RTE_I2C1_SCL_PIN (I2C1_SCL_PIN + GPIO_MAX_PIN) #define RTE_I2C1_SCL_MUX 5 -#define RTE_I2C1_SCL_PAD 24 +#define RTE_I2C1_SCL_PAD 22 #define RTE_I2C1_SCL_REN 2 #endif -#if (I2C1_SCL_LOC == 6) +#if (I2C1_SCL_LOC == 5) #define RTE_I2C1_SCL_PIN (I2C1_SCL_PIN + GPIO_MAX_PIN) #define RTE_I2C1_SCL_MUX 5 #define RTE_I2C1_SCL_PAD 29 @@ -2397,43 +2450,37 @@ #else //Pintool data #define RTE_I2C1_SDA_PORT I2C1_SDA_PORT -#if (I2C1_SDA_LOC == 0) +#if (I2C1_SDA_LOC == 6) #define RTE_I2C1_SDA_PIN I2C1_SDA_PIN #define RTE_I2C1_SDA_MUX 5 #define RTE_I2C1_SDA_PAD 2 #define RTE_I2C1_SDA_REN 7 #endif -#if (I2C1_SDA_LOC == 1) +#if (I2C1_SDA_LOC == 7) #define RTE_I2C1_SDA_PIN I2C1_SDA_PIN #define RTE_I2C1_SDA_MUX 5 #define RTE_I2C1_SDA_PAD 0 //no pad #define RTE_I2C1_SDA_REN 30 #endif -#if (I2C1_SDA_LOC == 2) +#if (I2C1_SDA_LOC == 8) #define RTE_I2C1_SDA_PIN I2C1_SDA_PIN #define RTE_I2C1_SDA_MUX 5 #define RTE_I2C1_SDA_PAD 15 #define RTE_I2C1_SDA_REN 51 #endif -#if (I2C1_SDA_LOC == 3) +#if (I2C1_SDA_LOC == 9) #define RTE_I2C1_SDA_PIN I2C1_SDA_PIN #define RTE_I2C1_SDA_MUX 5 #define RTE_I2C1_SDA_PAD 19 #define RTE_I2C1_SDA_REN 55 #endif -#if (I2C1_SDA_LOC == 4) +#if (I2C1_SDA_LOC == 10) #define RTE_I2C1_SDA_PIN (I2C1_SDA_PIN + GPIO_MAX_PIN) #define RTE_I2C1_SDA_MUX 5 #define RTE_I2C1_SDA_PAD 23 #define RTE_I2C1_SDA_REN 1 #endif -#if (I2C1_SDA_LOC == 5) -#define RTE_I2C1_SDA_PIN (I2C1_SDA_PIN + GPIO_MAX_PIN) -#define RTE_I2C1_SDA_MUX 5 -#define RTE_I2C1_SDA_PAD 25 -#define RTE_I2C1_SDA_REN 3 -#endif -#if (I2C1_SDA_LOC == 6) +#if (I2C1_SDA_LOC == 11) #define RTE_I2C1_SDA_PIN (I2C1_SDA_PIN + GPIO_MAX_PIN) #define RTE_I2C1_SDA_MUX 5 #define RTE_I2C1_SDA_PAD 29 @@ -2453,13 +2500,13 @@ // I2C1 [Driver_I2C1] -// I2C2 (Inter-integrated Circuit Interface 2) [Driver_I2C2] +// ULP I2C (Inter-integrated Circuit Interface 2) [Driver_I2C2] // Configuration settings for Driver_I2C2 in component ::Drivers:I2C #define RTE_I2C2 1 #define I2C2_IRQHandler IRQ013_Handler // I2C2_SCL Pin <0=>P0_1 <1=>P0_5 <2=>P0_7 <3=>P0_8 <4=>P0_13 -#ifndef I2C2_SCL_LOC +#ifndef ULP_I2C_SCL_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_I2C2_SCL_PORT_ID 0 #else @@ -2480,20 +2527,23 @@ #endif #else //Pintool data -#define RTE_I2C2_SCL_PORT I2C2_SCL_PORT -#define RTE_I2C2_SCL_PIN I2C2_SCL_PIN +#define RTE_I2C2_SCL_PORT ULP_I2C_SCL_PORT +#define RTE_I2C2_SCL_PIN ULP_I2C_SCL_PIN #define RTE_I2C2_SCL_MUX 4 -#if (I2C2_SCL_LOC == 0) +#if (ULP_I2C_SCL_LOC == 0) +#define RTE_I2C2_SCL_REN 0 +#elif (ULP_I2C_SCL_LOC == 1) +#define RTE_I2C2_SCL_REN 0 +#elif (ULP_I2C_SCL_LOC == 2) #define RTE_I2C2_SCL_REN 7 -#endif -#if (I2C2_SCL_LOC == 1) +#elif (ULP_I2C_SCL_LOC == 3) #define RTE_I2C2_SCL_REN 8 #endif //Pintool data #endif // I2C2_SDA Pin <0=>P0_0 <1=>P0_4 <2=>P0_6 <3=>P0_9 <4=>P0_11 <5=>P0_12 -#ifndef I2C2_SDA_LOC +#ifndef ULP_I2C_SDA_LOC #define RTE_I2C2_SDA_PORT_ID 0 #if (RTE_I2C2_SDA_PORT_ID == 0) #define RTE_I2C2_SDA_PORT 0 @@ -2501,10 +2551,10 @@ #define RTE_I2C2_SDA_MUX 4 #define RTE_I2C2_SDA_REN 6 #elif (RTE_I2C2_SDA_PORT_ID == 1) -#define RTE_I2C2_SDA_PORT 0 -#define RTE_I2C2_SDA_PIN 9 -#define RTE_I2C2_SDA_MUX 4 -#define RTE_I2C2_SDA_I2C_REN 9 +#define RTE_I2C2_SDA_PORT 0 +#define RTE_I2C2_SDA_PIN 9 +#define RTE_I2C2_SDA_MUX 4 +#define RTE_I2C2_SDA_REN 9 #elif (RTE_I2C2_SDA_PORT_ID == 2) #define RTE_I2C2_SDA_PORT 0 #define RTE_I2C2_SDA_PIN 11 @@ -2518,14 +2568,16 @@ #define RTE_I2C2_SDA_PORT I2C2_SDA_PORT #define RTE_I2C2_SDA_PIN I2C2_SDA_PIN #define RTE_I2C2_SDA_MUX 4 -#if (I2C2_SDA_LOC == 0) +#if (ULP_I2C_SDA_LOC == 4) +#define RTE_I2C2_SDA_REN 0 +#elif (ULP_I2C_SDA_LOC == 5) +#define RTE_I2C2_SDA_REN 0 +#elif (ULP_I2C_SDA_LOC == 6) #define RTE_I2C2_SDA_REN 6 -#endif -#if (I2C2_SDA_LOC == 1) -#define RTE_I2C2_SDA_MUX 4 -#endif -#if (I2C2_SDA_LOC == 2) -#define RTE_I2C2_SDA_MUX 4 +#elif (ULP_I2C_SDA_LOC == 7) +#define RTE_I2C2_SDA_REN 9 +#elif (ULP_I2C_SDA_LOC == 8) +#define RTE_I2C2_SDA_REN 11 #endif //Pintool data #endif @@ -2633,16 +2685,16 @@ #define RTE_GSPI_MASTER_CS0_PORT GSPI_MASTER_CS0__PORT #define RTE_GSPI_MASTER_CS0_PIN GSPI_MASTER_CS0__PIN #define RTE_GSPI_MASTER_CS0_MUX 4 -#if (GSPI_MASTER_CS0_LOC == 0) +#if (GSPI_MASTER_CS0_LOC == 4) #define RTE_GSPI_MASTER_CS0_PAD 4 #endif -#if (GSPI_MASTER_CS0_LOC == 1) +#if (GSPI_MASTER_CS0_LOC == 5) #define RTE_GSPI_MASTER_CS0_PAD 0 #endif -#if (GSPI_MASTER_CS0_LOC == 2) +#if (GSPI_MASTER_CS0_LOC == 6) #define RTE_GSPI_MASTER_CS0_PAD 13 #endif -#if (GSPI_MASTER_CS0_LOC == 3) +#if (GSPI_MASTER_CS0_LOC == 7) #define RTE_GSPI_MASTER_CS0_PAD 17 #endif //Pintool data @@ -2687,16 +2739,16 @@ #define RTE_GSPI_MASTER_CS1_PORT GSPI_MASTER_CS1__PORT #define RTE_GSPI_MASTER_CS1_PIN GSPI_MASTER_CS1__PIN #define RTE_GSPI_MASTER_CS1_MUX 4 -#if (GSPI_MASTER_CS1_LOC == 0) +#if (GSPI_MASTER_CS1_LOC == 8) #define RTE_GSPI_MASTER_CS1_PAD 5 #endif -#if (GSPI_MASTER_CS1_LOC == 1) +#if (GSPI_MASTER_CS1_LOC == 9) #define RTE_GSPI_MASTER_CS1_PAD 0 #endif -#if (GSPI_MASTER_CS1_LOC == 2) +#if (GSPI_MASTER_CS1_LOC == 10) #define RTE_GSPI_MASTER_CS1_PAD 14 #endif -#if (GSPI_MASTER_CS1_LOC == 3) +#if (GSPI_MASTER_CS1_LOC == 11) #define RTE_GSPI_MASTER_CS1_PAD 18 #endif //Pintool data @@ -2741,16 +2793,16 @@ #define RTE_GSPI_MASTER_CS2_PORT GSPI_MASTER_CS2__PORT #define RTE_GSPI_MASTER_CS2_PIN GSPI_MASTER_CS2__PIN #define RTE_GSPI_MASTER_CS2_MUX 4 -#if (GSPI_MASTER_CS2_LOC == 0) +#if (GSPI_MASTER_CS2_LOC == 12) #define RTE_GSPI_MASTER_CS2_PAD 8 #endif -#if (GSPI_MASTER_CS2_LOC == 1) +#if (GSPI_MASTER_CS2_LOC == 13) #define RTE_GSPI_MASTER_CS2_PAD 0 #endif -#if (GSPI_MASTER_CS2_LOC == 2) +#if (GSPI_MASTER_CS2_LOC == 14) #define RTE_GSPI_MASTER_CS2_PAD 15 #endif -#if (GSPI_MASTER_CS2_LOC == 3) +#if (GSPI_MASTER_CS2_LOC == 15) #define RTE_GSPI_MASTER_CS2_PAD 19 #endif //Pintool data @@ -2793,19 +2845,26 @@ //Pintool data #define RTE_GSPI_MASTER_MOSI_PORT GSPI_MASTER_MOSI__PORT #define RTE_GSPI_MASTER_MOSI_PIN GSPI_MASTER_MOSI__PIN -#define RTE_GSPI_MASTER_MOSI_MUX 4 -#if (GSPI_MASTER_MOSI_LOC == 0) +#if (GSPI_MASTER_MOSI_LOC == 16) +#define RTE_GSPI_MASTER_MOSI_MUX 4 #define RTE_GSPI_MASTER_MOSI_PAD 1 #endif -#if (GSPI_MASTER_MOSI_LOC == 1) +#if (GSPI_MASTER_MOSI_LOC == 17) +#define RTE_GSPI_MASTER_MOSI_MUX 4 #define RTE_GSPI_MASTER_MOSI_PAD 0 #endif -#if (GSPI_MASTER_MOSI_LOC == 2) +#if (GSPI_MASTER_MOSI_LOC == 18) +#define RTE_GSPI_MASTER_MOSI_MUX 4 #define RTE_GSPI_MASTER_MOSI_PAD 12 #endif -#if (GSPI_MASTER_MOSI_LOC == 3) +#if (GSPI_MASTER_MOSI_LOC == 19) +#define RTE_GSPI_MASTER_MOSI_MUX 4 #define RTE_GSPI_MASTER_MOSI_PAD 21 #endif +#if (GSPI_MASTER_MOSI_LOC == 20) +#define RTE_GSPI_MASTER_MOSI_MUX 12 +#define RTE_GSPI_MASTER_MOSI_PAD 1 +#endif //Pintool data #endif @@ -2842,16 +2901,16 @@ #define RTE_GSPI_MASTER_MISO_PORT GSPI_MASTER_MISO__PORT #define RTE_GSPI_MASTER_MISO_PIN GSPI_MASTER_MISO__PIN #define RTE_GSPI_MASTER_MISO_MUX 4 -#if (GSPI_MASTER_MISO_LOC == 0) +#if (GSPI_MASTER_MISO_LOC == 21) #define RTE_GSPI_MASTER_MISO_PAD 6 #endif -#if (GSPI_MASTER_MISO_LOC == 1) +#if (GSPI_MASTER_MISO_LOC == 22) #define RTE_GSPI_MASTER_MISO_PAD 0 #endif -#if (GSPI_MASTER_MISO_LOC == 2) +#if (GSPI_MASTER_MISO_LOC == 23) #define RTE_GSPI_MASTER_MISO_PAD 11 #endif -#if (GSPI_MASTER_MISO_LOC == 3) +#if (GSPI_MASTER_MISO_LOC == 24) #define RTE_GSPI_MASTER_MISO_PAD 20 #endif //Pintool data @@ -2897,17 +2956,29 @@ #if (RTE_SCT_IN_0_PORT_ID == 0) #define RTE_SCT_IN_0_PORT 0 #define RTE_SCT_IN_0_PIN 25 +#define RTE_SCT_IN_0_MUX 9 +#define RTE_SCT_IN_0_PAD 0 //no pad #else #error "Invalid RTE_SCT_IN_0_PIN Pin Configuration!" #endif #else //Pintool data #define RTE_SCT_IN_0_PORT SCT_IN0_PORT -#define RTE_SCT_IN_0_PIN SCT_IN0_PIN -//Pintool data -#endif +#if (SCT_IN0_LOC == 0) +#define RTE_SCT_IN_0_PIN SCT_IN0_PIN #define RTE_SCT_IN_0_MUX 9 #define RTE_SCT_IN_0_PAD 0 //no pad +#elif (SCT_IN0_LOC == 1) +#define RTE_SCT_IN_0_PIN (SCT_IN0_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_0_MUX 7 +#define RTE_SCT_IN_0_PAD 22 +#elif (SCT_IN0_LOC == 2) +#define RTE_SCT_IN_0_PIN (SCT_IN0_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_0_MUX 9 +#define RTE_SCT_IN_0_PAD 26 +#endif +//Pintool data +#endif //SCT_IN_1 <0=>GPIO_26 <1=>GPIO_65 <2=>GPIO_69 #ifndef SCT_IN1_LOC @@ -2929,16 +3000,21 @@ #else //Pintool data #define RTE_SCT_IN_1_PORT SCT_IN1_PORT -#if (SCT_IN1_LOC == 0) +#if (SCT_IN1_LOC == 3) #define RTE_SCT_IN_1_PIN SCT_IN1_PIN #define RTE_SCT_IN_1_MUX 9 #define RTE_SCT_IN_1_PAD 0 //no pad #endif -#if (SCT_IN1_LOC == 1) +#if (SCT_IN1_LOC == 4) #define RTE_SCT_IN_1_PIN (SCT_IN1_PIN + GPIO_MAX_PIN) #define RTE_SCT_IN_1_MUX 7 #define RTE_SCT_IN_1_PAD 23 #endif +#if (SCT_IN1_LOC == 5) +#define RTE_SCT_IN_1_PIN (SCT_IN1_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_1_MUX 9 +#define RTE_SCT_IN_1_PAD 27 +#endif //Pintool data #endif @@ -2971,17 +3047,12 @@ #else //Pintool data #define RTE_SCT_IN_2_PORT SCT_IN2_PORT -#if (SCT_IN2_LOC == 0) +#if (SCT_IN2_LOC == 6) #define RTE_SCT_IN_2_PIN SCT_IN2_PIN #define RTE_SCT_IN_2_MUX 9 #define RTE_SCT_IN_2_PAD 0 //no pad #endif -#if (SCT_IN2_LOC == 1) -#define RTE_SCT_IN_2_PIN (SCT_IN2_PIN + GPIO_MAX_PIN) -#define RTE_SCT_IN_2_MUX 7 -#define RTE_SCT_IN_2_PAD 24 -#endif -#if (SCT_IN2_LOC == 2) +#if (SCT_IN2_LOC == 7) #define RTE_SCT_IN_2_PIN (SCT_IN2_PIN + GPIO_MAX_PIN) #define RTE_SCT_IN_2_MUX 9 #define RTE_SCT_IN_2_PAD 28 @@ -3018,17 +3089,12 @@ #else //Pintool data #define RTE_SCT_IN_3_PORT SCT_IN3_PORT -#if (SCT_IN3_LOC == 0) +#if (SCT_IN3_LOC == 8) #define RTE_SCT_IN_3_PIN SCT_IN3_PIN #define RTE_SCT_IN_3_MUX 9 #define RTE_SCT_IN_3_PAD 0 //no pad #endif -#if (SCT_IN3_LOC == 1) -#define RTE_SCT_IN_3_PIN (SCT_IN3_PIN + GPIO_MAX_PIN) -#define RTE_SCT_IN_3_MUX 7 -#define RTE_SCT_IN_3_PAD 25 -#endif -#if (SCT_IN3_LOC == 2) +#if (SCT_IN3_LOC == 9) #define RTE_SCT_IN_3_PIN (SCT_IN3_PIN + GPIO_MAX_PIN) #define RTE_SCT_IN_3_MUX 9 #define RTE_SCT_IN_3_PAD 29 @@ -3042,17 +3108,25 @@ #if (RTE_SCT_OUT_0_PORT_ID == 0) #define RTE_SCT_OUT_0_PORT 0 #define RTE_SCT_OUT_0_PIN 29 +#define RTE_SCT_OUT_0_MUX 9 +#define RTE_SCT_OUT_0_PAD 0 //no pad #else #error "Invalid RTE_SCT_OUT_0_PIN Pin Configuration!" #endif #else //Pintool data #define RTE_SCT_OUT_0_PORT SCT_OUT0_PORT -#define RTE_SCT_OUT_0_PIN SCT_OUT0_PIN -//Pintool data -#endif +#if (SCT_OUT0_LOC == 10) +#define RTE_SCT_OUT_0_PIN SCT_OUT0_PIN #define RTE_SCT_OUT_0_MUX 9 #define RTE_SCT_OUT_0_PAD 0 //no pad +#elif (SCT_OUT0_LOC == 11) +#define RTE_SCT_OUT_0_PIN (SCT_OUT0_PIN + GPIO_MAX_PIN) +#define RTE_SCT_OUT_0_MUX 7 +#define RTE_SCT_OUT_0_PAD 26 +#endif +//Pintool data +#endif // SCT_OUT_1 <0=>GPIO_30 <1=>GPIO_69 #ifndef SCT_OUT1_LOC @@ -3060,17 +3134,67 @@ #if (RTE_SCT_OUT_1_PORT_ID == 0) #define RTE_SCT_OUT_1_PORT 0 #define RTE_SCT_OUT_1_PIN 30 +#define RTE_SCT_OUT_1_MUX 9 +#define RTE_SCT_OUT_1_PAD 0 //no pad #else #error "Invalid RTE_SCT_OUT_1_PIN Pin Configuration!" #endif #else //Pintool data #define RTE_SCT_OUT_1_PORT SCT_OUT1_PORT -#define RTE_SCT_OUT_1_PIN SCT_OUT1_PIN -//Pintool data -#endif +#if (SCT_OUT1_LOC == 12) +#define RTE_SCT_OUT_1_PIN SCT_OUT1_PIN #define RTE_SCT_OUT_1_MUX 9 #define RTE_SCT_OUT_1_PAD 0 //no pad +#elif (SCT_OUT1_LOC == 13) +#define RTE_SCT_OUT_1_PIN (SCT_OUT1_PIN + GPIO_MAX_PIN) +#define RTE_SCT_OUT_1_MUX 7 +#define RTE_SCT_OUT_1_PAD 27 +#endif +//Pintool data +#endif + +//Pintool data +#define RTE_SCT_OUT_2_PORT SCT_OUT2_PORT +#define RTE_SCT_OUT_2_PIN SCT_OUT2_PIN +#define RTE_SCT_OUT_2_MUX 7 +#define RTE_SCT_OUT_2_PAD 28 +//Pintool data + +//Pintool data +#define RTE_SCT_OUT_3_PORT SCT_OUT3_PORT +#define RTE_SCT_OUT_3_PIN SCT_OUT3_PIN +#define RTE_SCT_OUT_3_MUX 7 +#define RTE_SCT_OUT_3_PAD 29 +//Pintool data + +//Pintool data +#define RTE_SCT_OUT_4_PORT SCT_OUT4_PORT +#define RTE_SCT_OUT_4_PIN SCT_OUT4_PIN +#define RTE_SCT_OUT_4_MUX 7 +#define RTE_SCT_OUT_4_PAD 30 +//Pintool data + +//Pintool data +#define RTE_SCT_OUT_5_PORT SCT_OUT5_PORT +#define RTE_SCT_OUT_5_PIN SCT_OUT5_PIN +#define RTE_SCT_OUT_5_MUX 7 +#define RTE_SCT_OUT_5_PAD 31 +//Pintool data + +//Pintool data +#define RTE_SCT_OUT_6_PORT SCT_OUT6_PORT +#define RTE_SCT_OUT_6_PIN SCT_OUT6_PIN +#define RTE_SCT_OUT_6_MUX 7 +#define RTE_SCT_OUT_6_PAD 32 +//Pintool data + +//Pintool data +#define RTE_SCT_OUT_7_PORT SCT_OUT7_PORT +#define RTE_SCT_OUT_7_PIN SCT_OUT7_PIN +#define RTE_SCT_OUT_7_MUX 7 +#define RTE_SCT_OUT_7_PAD 33 +//Pintool data // SIO // //<> Serial Input Output @@ -3110,6 +3234,10 @@ #endif #if (SIO_0_LOC == 2) #define RTE_SIO_0_PIN (SIO_SIO0_PIN + GPIO_MAX_PIN) +#define RTE_SIO_0_PAD 22 +#endif +#if (SIO_0_LOC == 3) +#define RTE_SIO_0_PIN (SIO_SIO0_PIN + GPIO_MAX_PIN) #define RTE_SIO_0_PAD 30 #endif //Pintool data @@ -3150,19 +3278,19 @@ //Pintool data #define RTE_SIO_1_PORT SIO_SIO1_PORT #define RTE_SIO_1_MUX 1 -#if (SIO_1_LOC == 0) +#if (SIO_1_LOC == 4) #define RTE_SIO_1_PIN SIO_SIO1_PIN #define RTE_SIO_1_PAD 2 #endif -#if (SIO_1_LOC == 1) +#if (SIO_1_LOC == 5) #define RTE_SIO_1_PIN SIO_SIO1_PIN #define RTE_SIO_1_PAD 0 #endif -#if (SIO_1_LOC == 2) +#if (SIO_1_LOC == 6) #define RTE_SIO_1_PIN (SIO_SIO1_PIN + GPIO_MAX_PIN) #define RTE_SIO_1_PAD 23 #endif -#if (SIO_1_LOC == 3) +#if (SIO_1_LOC == 7) #define RTE_SIO_1_PIN (SIO_SIO1_PIN + GPIO_MAX_PIN) #define RTE_SIO_1_PAD 31 #endif @@ -3200,19 +3328,15 @@ //Pintool data #define RTE_SIO_2_PORT SIO_SIO2_PORT #define RTE_SIO_2_MUX 1 -#if (SIO_2_LOC == 0) +#if (SIO_2_LOC == 8) #define RTE_SIO_2_PIN SIO_SIO2_PIN #define RTE_SIO_2_PAD 3 #endif -#if (SIO_2_LOC == 1) +#if (SIO_2_LOC == 9) #define RTE_SIO_2_PIN SIO_SIO2_PIN #define RTE_SIO_2_PAD 0 #endif -#if (SIO_2_LOC == 2) -#define RTE_SIO_2_PIN (SIO_SIO2_PIN + GPIO_MAX_PIN) -#define RTE_SIO_2_PAD 24 -#endif -#if (SIO_2_LOC == 3) +#if (SIO_2_LOC == 10) #define RTE_SIO_2_PIN (SIO_SIO2_PIN + GPIO_MAX_PIN) #define RTE_SIO_2_PAD 32 #endif @@ -3250,19 +3374,15 @@ //Pintool data #define RTE_SIO_3_PORT SIO_SIO3_PORT #define RTE_SIO_3_MUX 1 -#if (SIO_3_LOC == 0) +#if (SIO_3_LOC == 11) #define RTE_SIO_3_PIN SIO_SIO3_PIN #define RTE_SIO_3_PAD 4 #endif -#if (SIO_3_LOC == 1) +#if (SIO_3_LOC == 12) #define RTE_SIO_3_PIN SIO_SIO3_PIN #define RTE_SIO_3_PAD 0 #endif -#if (SIO_3_LOC == 2) -#define RTE_SIO_3_PIN (SIO_SIO3_PIN + GPIO_MAX_PIN) -#define RTE_SIO_3_PAD 25 -#endif -#if (SIO_3_LOC == 3) +#if (SIO_3_LOC == 13) #define RTE_SIO_3_PIN (SIO_SIO3_PIN + GPIO_MAX_PIN) #define RTE_SIO_3_PAD 33 #endif @@ -3292,13 +3412,18 @@ #else //Pintool data #define RTE_SIO_4_PORT SIO_SIO4_PORT -#define RTE_SIO_4_PIN SIO_SIO4_PIN #define RTE_SIO_4_MUX 1 -#if (SIO_4_LOC == 0) +#if (SIO_4_LOC == 14) #define RTE_SIO_4_PAD 5 +#define RTE_SIO_4_PIN SIO_SIO4_PIN #endif -#if (SIO_4_LOC == 1) +#if (SIO_4_LOC == 15) #define RTE_SIO_4_PAD 0 +#define RTE_SIO_4_PIN SIO_SIO4_PIN +#endif +#if (SIO_4_LOC == 16) +#define RTE_SIO_4_PAD 26 +#define RTE_SIO_4_PIN (SIO_SIO4_PIN + GPIO_MAX_PIN) #endif //Pintool data #endif @@ -3322,13 +3447,18 @@ #else //Pintool data #define RTE_SIO_5_PORT SIO_SIO5_PORT -#define RTE_SIO_5_PIN SIO_SIO5_PIN #define RTE_SIO_5_MUX 1 -#if (SIO_5_LOC == 0) +#if (SIO_5_LOC == 17) #define RTE_SIO_5_PAD 6 +#define RTE_SIO_5_PIN SIO_SIO5_PIN #endif -#if (SIO_5_LOC == 1) +#if (SIO_5_LOC == 18) #define RTE_SIO_5_PAD 0 +#define RTE_SIO_5_PIN SIO_SIO5_PIN +#endif +#if (SIO_5_LOC == 19) +#define RTE_SIO_5_PAD 0 +#define RTE_SIO_5_PIN (SIO_SIO5_PIN + GPIO_MAX_PIN) #endif //Pintool data #endif @@ -3369,11 +3499,11 @@ //Pintool data #define RTE_SIO_7_PORT SIO_SIO7_PORT #define RTE_SIO_7_MUX 1 -#if (SIO_7_LOC == 0) +#if (SIO_7_LOC == 21) #define RTE_SIO_7_PIN SIO_SIO7_PIN #define RTE_SIO_7_PAD 8 #endif -#if (SIO_7_LOC == 1) +#if (SIO_7_LOC == 22) #define RTE_SIO_7_PIN (SIO_SIO7_PIN + GPIO_MAX_PIN) #define RTE_SIO_7_PAD 29 #endif @@ -3382,7 +3512,7 @@ //<> Pulse Width Modulation //PWM_1H <0=>GPIO_7 <1=>GPIO_64 <2=>GPIO_65 -#ifndef PWM_H1_LOC +#ifndef PWM_1H_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_PWM_1H_PORT_ID 0 #else @@ -3404,14 +3534,14 @@ #endif #else //Pintool data -#define RTE_PWM_1H_PORT PWM_H1_PORT -#if (PWM_H1_LOC == 0) -#define RTE_PWM_1H_PIN PWM_H1_PIN +#define RTE_PWM_1H_PORT PWM_1H_PORT +#if (PWM_1H_LOC == 0) +#define RTE_PWM_1H_PIN PWM_1H_PIN #define RTE_PWM_1H_MUX 10 #define RTE_PWM_1H_PAD 2 #endif -#if (PWM_H1_LOC == 1) -#define RTE_PWM_1H_PIN (PWM_H1_PIN + GPIO_MAX_PIN) +#if (PWM_1H_LOC == 1) +#define RTE_PWM_1H_PIN (PWM_1H_PIN + GPIO_MAX_PIN) #define RTE_PWM_1H_MUX 8 #define RTE_PWM_1H_PAD 22 #endif @@ -3419,7 +3549,7 @@ #endif // PWM_1L <0=>GPIO_6 <1=>GPIO_64 <2=>GPIO_64 -#ifndef PWM_L1_LOC +#ifndef PWM_1L_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_PWM_1L_PORT_ID 0 #else @@ -3429,20 +3559,28 @@ #if (RTE_PWM_1L_PORT_ID == 0) #define RTE_PWM_1L_PORT 0 #define RTE_PWM_1L_PIN 6 +#define RTE_PWM_1L_MUX 10 +#define RTE_PWM_1L_PAD 1 #else #error "Invalid RTE_PWM_1L_PIN Pin Configuration!" #endif #else //Pintool data -#define RTE_PWM_1L_PORT PWM_L1_PORT -#define RTE_PWM_1L_PIN PWM_L1_PIN -//Pintool data -#endif +#define RTE_PWM_1L_PORT PWM_1L_PORT +#if (PWM_1L_LOC == 2) +#define RTE_PWM_1L_PIN PWM_1L_PIN #define RTE_PWM_1L_MUX 10 #define RTE_PWM_1L_PAD 1 +#elif (PWM_1L_LOC == 3) +#define RTE_PWM_1L_PIN (PWM_1L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_1L_MUX 8 +#define RTE_PWM_1L_PAD 22 +#endif +//Pintool data +#endif //PWM_2H <0=>GPIO_9 <1=>GPIO_67 <2=>GPIO_69 -#ifndef PWM_H2_LOC +#ifndef PWM_2H_LOC #define RTE_PWM_2H_PORT_ID 0 #if ((RTE_PWM_2H_PORT_ID == 2)) #error "Invalid RTE_PWM_2H_PIN pin Configuration!" @@ -3463,22 +3601,22 @@ #endif #else //Pintool data -#define RTE_PWM_2H_PORT PWM_H2_PORT -#if (PWM_H2_LOC == 0) -#define RTE_PWM_2H_PIN PWM_H2_PIN +#define RTE_PWM_2H_PORT PWM_2H_PORT +#if (PWM_2H_LOC == 4) +#define RTE_PWM_2H_PIN PWM_2H_PIN #define RTE_PWM_2H_MUX 10 #define RTE_PWM_2H_PAD 4 #endif -#if (PWM_H2_LOC == 1) -#define RTE_PWM_2H_PIN (PWM_H2_PIN + GPIO_MAX_PIN) -#define RTE_PWM_2H_MUX 8 -#define RTE_PWM_2H_PAD 25 +#if (PWM_2H_LOC == 5) +#define RTE_PWM_2H_PIN (PWM_2H_PIN + GPIO_MAX_PIN) +#define RTE_PWM_2H_MUX 12 +#define RTE_PWM_2H_PAD 27 #endif //Pintool data #endif // PWM_2L <0=>GPIO_8 <1=>GPIO_66 <2=>GPIO_68 -#ifndef PWM_L2_LOC +#ifndef PWM_2L_LOC #define RTE_PWM_2L_PORT_ID 0 #if ((RTE_PWM_2L_PORT_ID == 2)) #error "Invalid RTE_PWM_2L_PIN pin Configuration!" @@ -3499,59 +3637,80 @@ #endif #else //Pintool data -#define RTE_PWM_2L_PORT PWM_L2_PORT -#if (PWM_L2_LOC == 0) -#define RTE_PWM_2L_PIN PWM_L2_PIN +#define RTE_PWM_2L_PORT PWM_2L_PORT +#if (PWM_2L_LOC == 6) +#define RTE_PWM_2L_PIN PWM_2L_PIN #define RTE_PWM_2L_MUX 10 #define RTE_PWM_2L_PAD 3 #endif -#if (PWM_L2_LOC == 1) -#define RTE_PWM_2L_PIN (PWM_L2_PIN + GPIO_MAX_PIN) +#if (PWM_2L_LOC == 7) +#define RTE_PWM_2L_PIN (PWM_2L_PIN + GPIO_MAX_PIN) #define RTE_PWM_2L_MUX 8 #define RTE_PWM_2L_PAD 24 #endif +#if (PWM_2L_LOC == 8) +#define RTE_PWM_2L_PIN (PWM_2L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_2L_MUX 12 +#define RTE_PWM_2L_PAD 26 +#endif //Pintool data #endif // PWM_3H <0=>GPIO_11 <1=>GPIO_69 -#ifndef PWM_H3_LOC +#ifndef PWM_3H_LOC #define RTE_PWM_3H_PORT_ID 0 #if (RTE_PWM_3H_PORT_ID == 0) #define RTE_PWM_3H_PORT 0 #define RTE_PWM_3H_PIN 11 +#define RTE_PWM_3H_MUX 10 +#define RTE_PWM_3H_PAD 6 #else #error "Invalid RTE_PWM_3H_PIN Pin Configuration!" #endif #else //Pintool data -#define RTE_PWM_3H_PORT PWM_H3_PORT -#define RTE_PWM_3H_PIN PWM_H3_PIN -//Pintool data -#endif +#define RTE_PWM_3H_PORT PWM_3H_PORT +#if (PWM_3H_LOC == 9) +#define RTE_PWM_3H_PIN PWM_3H_PIN #define RTE_PWM_3H_MUX 10 #define RTE_PWM_3H_PAD 6 +#elif (PWM_3H_LOC == 10) +#define RTE_PWM_3H_PIN (PWM_3H_PIN + GPIO_MAX_PIN) +#define RTE_PWM_3H_MUX 8 +#define RTE_PWM_3H_PAD 27 +#endif +//Pintool data +#endif // PWM_3L <0=>GPIO_10 <1=>GPIO_68 -#ifndef PWM_L3_LOC +#ifndef PWM_3L_LOC #define RTE_PWM_3L_PORT_ID 0 #if (RTE_PWM_3L_PORT_ID == 0) #define RTE_PWM_3L_PORT 0 #define RTE_PWM_3L_PIN 10 +#define RTE_PWM_3L_MUX 10 +#define RTE_PWM_3L_PAD 5 #else #error "Invalid RTE_PWM_3L_PIN Pin Configuration!" #endif #else //Pintool data -#define RTE_PWM_3L_PORT PWM_L3_PORT -#define RTE_PWM_3L_PIN PWM_L3_PIN -//Pintool data -#endif +#define RTE_PWM_3L_PORT PWM_3L_PORT +#if (PWM_3L_LOC == 11) +#define RTE_PWM_3L_PIN PWM_3L_PIN #define RTE_PWM_3L_MUX 10 #define RTE_PWM_3L_PAD 5 +#elif (PWM_3L_LOC == 12) +#define RTE_PWM_3L_PIN (PWM_3L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_3L_MUX 8 +#define RTE_PWM_3L_PAD 26 +#endif +//Pintool data +#endif // PWM_4H <0=>GPIO_15 <1=>GPIO_71 -#ifndef PWM_H4_LOC +#ifndef PWM_4H_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_PWM_4H_PORT_ID 1 #else @@ -3573,22 +3732,15 @@ #endif #else //Pintool data -#define RTE_PWM_4H_PORT PWM_H4_PORT -#if (PWM_H4_LOC == 0) -#define RTE_PWM_4H_PIN PWM_H4_PIN -#define RTE_PWM_4H_MUX 10 -#define RTE_PWM_4H_PAD 8 -#endif -#if (PWM_H4_LOC == 1) -#define RTE_PWM_4H_PIN (PWM_H4_PIN + GPIO_MAX_PIN) -#define RTE_PWM_4H_MUX 8 -#define RTE_PWM_4H_PAD 29 -#endif +#define RTE_PWM_4H_PORT PWM_4H_PORT +#define RTE_PWM_4H_PIN (PWM_4H_PIN + GPIO_MAX_PIN) +#define RTE_PWM_4H_MUX 8 +#define RTE_PWM_4H_PAD 29 //Pintool data #endif // PWM_4H <0=>GPIO_12 <1=>GPIO_70 -#ifndef PWM_L4_LOC +#ifndef PWM_4L_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_PWM_4L_PORT_ID 1 #else @@ -3610,14 +3762,14 @@ #endif #else //Pintool data -#define RTE_PWM_4L_PORT PWM_L4_PORT -#if (PWM_L4_LOC == 0) -#define RTE_PWM_4L_PIN PWM_L4_PIN +#define RTE_PWM_4L_PORT PWM_4L_PORT +#if (PWM_4L_LOC == 14) +#define RTE_PWM_4L_PIN PWM_4L_PIN #define RTE_PWM_4L_MUX 10 #define RTE_PWM_4L_PAD 7 #endif -#if (PWM_L4_LOC == 1) -#define RTE_PWM_4L_PIN (PWM_L4_PIN + GPIO_MAX_PIN) +#if (PWM_4L_LOC == 15) +#define RTE_PWM_4L_PIN (PWM_4L_PIN + GPIO_MAX_PIN) #define RTE_PWM_4L_MUX 8 #define RTE_PWM_4L_PAD 28 #endif @@ -3644,12 +3796,17 @@ #else //Pintool data #define RTE_PWM_FAULTA_PORT PWM_FAULTA_PORT -#if (PWM_FAULTA_LOC == 0) +#if (PWM_FAULTA_LOC == 16) #define RTE_PWM_FAULTA_PIN PWM_FAULTA_PIN #define RTE_PWM_FAULTA_MUX 10 #define RTE_PWM_FAULTA_PAD 0 //no pad #endif -#if (PWM_FAULTA_LOC == 2) +#if (PWM_FAULTA_LOC == 17) +#define RTE_PWM_FAULTA_PIN (PWM_FAULTA_PIN + GPIO_MAX_PIN) +#define RTE_PWM_FAULTA_MUX 10 +#define RTE_PWM_FAULTA_PAD 26 +#endif +#if (PWM_FAULTA_LOC == 18) #define RTE_PWM_FAULTA_PIN (PWM_FAULTA_PIN + GPIO_MAX_PIN) #define RTE_PWM_FAULTA_MUX 8 #define RTE_PWM_FAULTA_PAD 31 @@ -3677,12 +3834,17 @@ #else //Pintool data #define RTE_PWM_FAULTB_PORT PWM_FAULTB_PORT -#if (PWM_FAULTB_LOC == 0) +#if (PWM_FAULTB_LOC == 19) #define RTE_PWM_FAULTB_PIN PWM_FAULTB_PIN #define RTE_PWM_FAULTB_MUX 10 #define RTE_PWM_FAULTB_PAD 0 //no pad #endif -#if (PWM_FAULTB_LOC == 2) +#if (PWM_FAULTB_LOC == 20) +#define RTE_PWM_FAULTB_PIN (PWM_FAULTB_PIN + GPIO_MAX_PIN) +#define RTE_PWM_FAULTB_MUX 10 +#define RTE_PWM_FAULTB_PAD 27 +#endif +#if (PWM_FAULTB_LOC == 21) #define RTE_PWM_FAULTB_PIN (PWM_FAULTB_PIN + GPIO_MAX_PIN) #define RTE_PWM_FAULTB_MUX 8 #define RTE_PWM_FAULTB_PAD 32 @@ -3691,13 +3853,13 @@ #endif //PWM_SLP_EVENT_TRIG GPIO_72 -#ifndef PWM_SLEEPTRIG_LOC +#ifndef PWM_EVTTRIG_LOC #define RTE_PWM_SLP_EVENT_TRIG_PORT 0 #define RTE_PWM_SLP_EVENT_TRIG_PIN 72 #else //Pintool data -#define RTE_PWM_SLP_EVENT_TRIG_PORT PWM_SLEEP_EVENT_TRIG_PORT -#define RTE_PWM_SLP_EVENT_TRIG_PIN (PWM_SLEEP_EVENT_TRIG_PIN + GPIO_MAX_PIN) +#define RTE_PWM_SLP_EVENT_TRIG_PORT PWM_SLEEP_EVT_TRIG_PORT +#define RTE_PWM_SLP_EVENT_TRIG_PIN (PWM_SLEEP_EVT_TRIG_PIN + GPIO_MAX_PIN) //Pintool data #endif #define RTE_PWM_SLP_EVENT_TRIG_MUX 8 @@ -3733,22 +3895,22 @@ #else //Pintool data #define RTE_PWM_TMR_EXT_TRIG_1_PORT PWM_TMR_EXT_TRIG_1_PORT -#if (PWM_EXTTRIG1_LOC == 0) +#if (PWM_EXTTRIG1_LOC == 22) #define RTE_PWM_TMR_EXT_TRIG_1_PIN PWM_TMR_EXT_TRIG_1_PIN #define RTE_PWM_TMR_EXT_TRIG_1_MUX 10 #define RTE_PWM_TMR_EXT_TRIG_1_PAD 0 //no pad #endif -#if (PWM_EXTTRIG1_LOC == 1) +#if (PWM_EXTTRIG1_LOC == 23) #define RTE_PWM_TMR_EXT_TRIG_1_PIN PWM_TMR_EXT_TRIG_1_PIN #define RTE_PWM_TMR_EXT_TRIG_1_MUX 8 #define RTE_PWM_TMR_EXT_TRIG_1_PAD 15 #endif -#if (PWM_EXTTRIG1_LOC == 2) +#if (PWM_EXTTRIG1_LOC == 24) #define RTE_PWM_TMR_EXT_TRIG_1_PIN (PWM_TMR_EXT_TRIG_1_PIN + GPIO_MAX_PIN) #define RTE_PWM_TMR_EXT_TRIG_1_MUX 10 #define RTE_PWM_TMR_EXT_TRIG_1_PAD 28 #endif -#if (PWM_EXTTRIG1_LOC == 3) +#if (PWM_EXTTRIG1_LOC == 25) #define RTE_PWM_TMR_EXT_TRIG_1_PIN (PWM_TMR_EXT_TRIG_1_PIN + GPIO_MAX_PIN) #define RTE_PWM_TMR_EXT_TRIG_1_MUX 8 #define RTE_PWM_TMR_EXT_TRIG_1_PAD 33 @@ -3781,17 +3943,22 @@ #else //Pintool data #define RTE_PWM_TMR_EXT_TRIG_2_PORT PWM_TMR_EXT_TRIG_2_PORT -#if (PWM_EXTTRIG2_LOC == 0) +#if (PWM_EXTTRIG2_LOC == 26) #define RTE_PWM_TMR_EXT_TRIG_2_PIN PWM_TMR_EXT_TRIG_2_PIN #define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 #define RTE_PWM_TMR_EXT_TRIG_2_PAD 0 //no pad #endif -#if (PWM_EXTTRIG2_LOC == 1) +#if (PWM_EXTTRIG2_LOC == 27) #define RTE_PWM_TMR_EXT_TRIG_2_PIN PWM_TMR_EXT_TRIG_2_PIN #define RTE_PWM_TMR_EXT_TRIG_2_MUX 8 #define RTE_PWM_TMR_EXT_TRIG_2_PAD 18 #endif -#if (PWM_EXTTRIG2_LOC == 2) +#if (PWM_EXTTRIG2_LOC == 28) //Combination not available in pin mux +#define RTE_PWM_TMR_EXT_TRIG_2_PIN (PWM_TMR_EXT_TRIG_2_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 29 +#endif +#if (PWM_EXTTRIG2_LOC == 29) #define RTE_PWM_TMR_EXT_TRIG_2_PIN (PWM_TMR_EXT_TRIG_2_PIN + GPIO_MAX_PIN) #define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 #define RTE_PWM_TMR_EXT_TRIG_2_PAD 29 @@ -3799,6 +3966,46 @@ //Pintool data #endif +//PWM_TMR_EXT_TRIG_3 +//Pintool data +#define RTE_PWM_TMR_EXT_TRIG_3_PORT PWM_TMR_EXT_TRIG_3_PORT +#if (PWM_EXTTRIG3_LOC == 30) +#define RTE_PWM_TMR_EXT_TRIG_3_PIN PWM_TMR_EXT_TRIG_3_PIN +#define RTE_PWM_TMR_EXT_TRIG_3_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_3_PAD 0 //no pad +#endif +#if (PWM_EXTTRIG3_LOC == 31) +#define RTE_PWM_TMR_EXT_TRIG_3_PIN PWM_TMR_EXT_TRIG_3_PIN +#define RTE_PWM_TMR_EXT_TRIG_3_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_3_PAD 19 +#endif +#if (PWM_EXTTRIG3_LOC == 32) +#define RTE_PWM_TMR_EXT_TRIG_3_PIN (PWM_TMR_EXT_TRIG_3_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_3_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_3_PAD 30 +#endif +//Pintool data + +//PWM_TMR_EXT_TRIG_4 +//Pintool data +#define RTE_PWM_TMR_EXT_TRIG_4_PORT PWM_TMR_EXT_TRIG_4_PORT +#if (PWM_EXTTRIG4_LOC == 33) +#define RTE_PWM_TMR_EXT_TRIG_4_PIN PWM_TMR_EXT_TRIG_4_PIN +#define RTE_PWM_TMR_EXT_TRIG_4_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_4_PAD 0 //no pad +#endif +#if (PWM_EXTTRIG4_LOC == 34) +#define RTE_PWM_TMR_EXT_TRIG_4_PIN PWM_TMR_EXT_TRIG_4_PIN +#define RTE_PWM_TMR_EXT_TRIG_4_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_4_PAD 14 +#endif +#if (PWM_EXTTRIG4_LOC == 35) +#define RTE_PWM_TMR_EXT_TRIG_4_PIN (PWM_TMR_EXT_TRIG_4_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_4_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_4_PAD 31 +#endif +//Pintool data + //<> QEI (Quadrature Encode Interface) //QEI_DIR <0=>GPIO_28 <1=>GPIO_49 <2=>GPIO_57 <3=>GPIO_67 <4=>GPIO_71 <5=>GPIO_73 <6=>GPIO_11 <7=>GPIO_34 @@ -4672,4 +4879,21 @@ #define RTE_UULP_GPIO_4_PORT 5 #define RTE_UULP_GPIO_4_PIN 4 -#define RTE_UULP_GPIO_4_MODE 0 \ No newline at end of file +#define RTE_UULP_GPIO_4_MODE 0 + +#define RTE_UULP_GPIO_5_PIN 5 +#define RTE_UULP_GPIO_5_MODE 0 + +// UULP GPIO as enable pin for sensors +#define SENSOR_ENABLE_GPIO_MAPPED_TO_UULP +#define SENSOR_ENABLE_GPIO_PIN RTE_UULP_GPIO_1_PIN + +// Memlcd GPIOs +#define RTE_MEMLCD_CS_PIN 10 // Memlcd SPI CS pin +#define RTE_MEMLCD_CS_PORT 0 // Memlcd SPI CS port + +#define RTE_MEMLCD_EXTCOMIN_PIN 3 // Memlcd external communication pin +#define RTE_MEMLCD_EXTCOMIN_PORT 0 // Memlcd external communication port + +#define RTE_MEMLCD_ENABLE_DISPLAY_PIN 0 // Memlcd display enable pin +#define RTE_MEMLCD_ENABLE_DISPLAY_PORT 0 // Memlcd display enable port diff --git a/components/board/silabs/config/brd4342a/pin_config.h b/components/board/silabs/config/brd4342a/pin_config.h index fcbb183c6..2bbc8c59c 100644 --- a/components/board/silabs/config/brd4342a/pin_config.h +++ b/components/board/silabs/config/brd4342a/pin_config.h @@ -16,8 +16,8 @@ // $[I2C1] // [I2C1]$ -// $[I2C2] -// [I2C2]$ +// $[ULP_I2C] +// [ULP_I2C]$ // $[SSI_MASTER] // [SSI_MASTER]$ @@ -25,8 +25,8 @@ // $[SSI_SLAVE] // [SSI_SLAVE]$ -// $[SSI_ULP_MASTER] -// [SSI_ULP_MASTER]$ +// $[ULP_SPI] +// [ULP_SPI]$ // $[GSPI_MASTER] // [GSPI_MASTER]$ @@ -34,8 +34,8 @@ // $[I2S0] // [I2S0]$ -// $[I2S1] -// [I2S1]$ +// $[ULP_I2S] +// [ULP_I2S]$ // $[SCT] // [SCT]$ @@ -46,8 +46,74 @@ // $[PWM] // [PWM]$ -// $[ADC] -// [ADC]$ +// $[PWM_CH0] +// [PWM_CH0]$ + +// $[PWM_CH1] +// [PWM_CH1]$ + +// $[PWM_CH2] +// [PWM_CH2]$ + +// $[PWM_CH3] +// [PWM_CH3]$ + +// $[ADC_CH1] +// [ADC_CH1]$ + +// $[ADC_CH2] +// [ADC_CH2]$ + +// $[ADC_CH3] +// [ADC_CH3]$ + +// $[ADC_CH4] +// [ADC_CH4]$ + +// $[ADC_CH5] +// [ADC_CH5]$ + +// $[ADC_CH6] +// [ADC_CH6]$ + +// $[ADC_CH7] +// [ADC_CH7]$ + +// $[ADC_CH8] +// [ADC_CH8]$ + +// $[ADC_CH9] +// [ADC_CH9]$ + +// $[ADC_CH10] +// [ADC_CH10]$ + +// $[ADC_CH11] +// [ADC_CH11]$ + +// $[ADC_CH12] +// [ADC_CH12]$ + +// $[ADC_CH13] +// [ADC_CH13]$ + +// $[ADC_CH14] +// [ADC_CH14]$ + +// $[ADC_CH15] +// [ADC_CH15]$ + +// $[ADC_CH16] +// [ADC_CH16]$ + +// $[ADC_CH17] +// [ADC_CH17]$ + +// $[ADC_CH18] +// [ADC_CH18]$ + +// $[ADC_CH19] +// [ADC_CH19]$ // $[COMP1] // [COMP1]$ diff --git a/components/board/silabs/config/brd4343a/RTE_Device_917.h b/components/board/silabs/config/brd4343a/RTE_Device_917.h index 611b95331..5d9574cd2 100644 --- a/components/board/silabs/config/brd4343a/RTE_Device_917.h +++ b/components/board/silabs/config/brd4343a/RTE_Device_917.h @@ -46,7 +46,7 @@ #define RTE_BUTTON1_PIN (11U) #define RTE_BUTTON1_PAD 6 -#define RTE_LED0_PORT 0 +#define RTE_LED0_PORT 4 #define RTE_LED0_NUMBER 0 #define RTE_LED0_PIN (0U) @@ -62,7 +62,7 @@ #define RTE_USART0 1 -#define RTE_USART0_CLK_SRC USART_INTFPLLCLK +#define RTE_USART0_CLK_SRC USART_ULPREFCLK #define RTE_USART0_CLK_DIV_FACT 1 #define RTE_USART0_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER @@ -86,6 +86,7 @@ // USART0_CLK <0=>P0_8 <1=>P0_25 <2=>P0_52 <3=>P0_64 // CLK of USART0 +#ifndef USART0_CLK_LOC #define RTE_USART0_CLK_PORT_ID 0 #if (RTE_USART0_CLK_PORT_ID == 0) @@ -106,10 +107,35 @@ #else #error "Invalid USART0 RTE_USART0_CLK_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_CLK_PORT USART0_CLK_PORT +#if (USART0_CLK_LOC == 0) +#define RTE_USART0_CLK_PIN USART0_CLK_PIN +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 3 +#endif +#if (USART0_CLK_LOC == 1) +#define RTE_USART0_CLK_PIN USART0_CLK_PIN +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 0 //NO PAD +#endif +#if (USART0_CLK_LOC == 2) +#define RTE_USART0_CLK_PIN USART0_CLK_PIN +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 16 +#endif +#if (USART0_CLK_LOC == 3) +#define RTE_USART0_CLK_PIN (USART0_CLK_PIN + GPIO_MAX_PIN) +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 22 +#endif +//Pintool data +#endif // USART0_TX <0=>P0_15 <1=>P0_30 <2=>P0_54 <3=>P0_68 <4=>P0_71 // TX for USART0 - +#ifndef USART0_TX_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_USART0_TX_PORT_ID 1 #else @@ -139,10 +165,40 @@ #else #error "Invalid USART0 RTE_USART0_TX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_TX_PORT USART0_TX_PORT +#if (USART0_TX_LOC == 4) +#define RTE_USART0_TX_PIN USART0_TX_PIN +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 8 +#endif +#if (USART0_TX_LOC == 5) +#define RTE_USART0_TX_PIN USART0_TX_PIN +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 0 //NO PAD +#endif +#if (USART0_TX_LOC == 6) +#define RTE_USART0_TX_PIN USART0_TX_PIN +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 18 +#endif +#if (USART0_TX_LOC == 7) +#define RTE_USART0_TX_PIN (USART0_TX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 26 +#endif +#if (USART0_TX_LOC == 8) +#define RTE_USART0_TX_PIN (USART0_TX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_TX_MUX 4 +#define RTE_USART0_TX_PAD 29 +#endif +//Pintool data +#endif // USART0_RX <0=>P0_10 <1=>P0_29 <2=>P0_55 <3=>P0_65 <4=>P0_70 // RX for USART0 - +#ifndef USART0_RX_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_USART0_RX_PORT_ID 1 #else @@ -177,9 +233,40 @@ #else #error "Invalid USART0 RTE_USART0_RX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_RX_PORT USART0_RX_PORT +#if (USART0_RX_LOC == 9) +#define RTE_USART0_RX_PIN USART0_RX_PIN +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 5 +#endif +#if (USART0_RX_LOC == 10) +#define RTE_USART0_RX_PIN USART0_RX_PIN +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 0 //no pad +#endif +#if (USART0_RX_LOC == 11) +#define RTE_USART0_RX_PIN USART0_RX_PIN +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 19 +#endif +#if (USART0_RX_LOC == 12) +#define RTE_USART0_RX_PIN (USART0_RX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 23 +#endif +#if (USART0_RX_LOC == 13) +#define RTE_USART0_RX_PIN (USART0_RX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_RX_MUX 4 +#define RTE_USART0_RX_PAD 28 +#endif +//Pintool data +#endif // USART0_CTS <0=>P0_6 <1=>P0_26 <2=>P0_56 <3=>P0_70 // CTS for USART0 +#ifndef USART0_CTS_LOC #define RTE_USART0_CTS_PORT_ID 0 #if (RTE_USART0_CTS_PORT_ID == 0) @@ -205,9 +292,35 @@ #else #error "Invalid USART0 RTE_USART0_CTS_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_CTS_PORT USART0_CTS_PORT +#if (USART0_CTS_LOC == 14) +#define RTE_USART0_CTS_PIN USART0_CTS_PIN +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 1 +#endif +#if (USART0_CTS_LOC == 15) +#define RTE_USART0_CTS_PIN USART0_CTS_PIN +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 0 //NO PAD +#endif +#if (USART0_CTS_LOC == 16) +#define RTE_USART0_CTS_PIN USART0_CTS_PIN +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 20 +#endif +#if (USART0_CTS_LOC == 17) +#define RTE_USART0_CTS_PIN (USART0_CTS_PIN + GPIO_MAX_PIN) +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 28 +#endif +//Pintool data +#endif // USART0_RTS <0=>P0_9 <1=>P0_28 <2=>P0_53 <3=>P0_69 // RTS for USART0 +#ifndef USART0_RTS_LOC #define RTE_USART0_RTS_PORT_ID 0 #if (RTE_USART0_RTS_PORT_ID == 0) @@ -228,10 +341,35 @@ #else #error "Invalid USART0 RTE_USART0_RTS_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_RTS_PORT USART0_RTS_PORT +#if (USART0_RTS_LOC == 18) +#define RTE_USART0_RTS_PIN USART0_RTS_PIN +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 4 +#endif +#if (USART0_RTS_LOC == 19) +#define RTE_USART0_RTS_PIN USART0_RTS_PIN +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 0 //NO PAD +#endif +#if (USART0_RTS_LOC == 20) +#define RTE_USART0_RTS_PIN USART0_RTS_PIN +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 17 +#endif +#if (USART0_RTS_LOC == 21) +#define RTE_USART0_RTS_PIN (USART0_RTS_PIN + GPIO_MAX_PIN) +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 27 +#endif +//Pintool data +#endif // USART0_IR_TX <0=>P0_48 <1=>P0_72 // IR TX for USART0 - +#ifndef USART0_IRTX_LOC #define RTE_IR_TX_PORT_ID 0 #if ((RTE_IR_TX_PORT_ID == 2)) #error "Invalid USART0 RTE_USART0_IR_TX_PIN Pin Configuration!" @@ -255,10 +393,35 @@ #else #error "Invalid USART0 RTE_USART0_IR_TX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_IR_TX_PORT USART0_IRTX_PORT +#if (USART0_IRTX_LOC == 22) +#define RTE_USART0_IR_TX_PIN USART0_IRTX_PIN +#define RTE_USART0_IR_TX_MUX 13 +#define RTE_USART0_IR_TX_PAD 0 //No pad +#endif +#if (USART0_IRTX_LOC == 23) +#define RTE_USART0_IR_TX_PIN USART0_IRTX_PIN +#define RTE_USART0_IR_TX_MUX 2 +#define RTE_USART0_IR_TX_PAD 12 +#endif +#if (USART0_IRTX_LOC == 24) +#define RTE_USART0_IR_TX_PIN (USART0_IRTX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_IR_TX_MUX 11 +#define RTE_USART0_IR_TX_PAD 23 +#endif +#if (USART0_IRTX_LOC == 25) +#define RTE_USART0_IR_TX_PIN (USART0_IRTX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_IR_TX_MUX 2 +#define RTE_USART0_IR_TX_PAD 30 +#endif +//Pintool data +#endif // USART0_IR_RX <0=>P0_47 <1=>P0_71 <2=>P0_64 <3=>P0_25 // IR RX for USART0 - +#ifndef USART0_IRRX_LOC #define RTE_IR_RX_PORT_ID 0 #if ((RTE_IR_RX_PORT_ID == 2)) #error "Invalid USART0 RTE_USART0_IR_RX_PIN Pin Configuration!" @@ -282,9 +445,35 @@ #else #error "Invalid USART0 RTE_USART0_IR_RX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_IR_RX_PORT USART0_IRRX_PORT +#if (USART0_IRRX_LOC == 26) +#define RTE_USART0_IR_RX_PIN USART0_IRRX_PIN +#define RTE_USART0_IR_RX_MUX 13 +#define RTE_USART0_IR_RX_PAD 0 //no pad +#endif +#if (USART0_IRRX_LOC == 27) +#define RTE_USART0_IR_RX_PIN USART0_IRRX_PIN +#define RTE_USART0_IR_RX_MUX 2 +#define RTE_USART0_IR_RX_PAD 11 +#endif +#if (USART0_IRRX_LOC == 28) +#define RTE_USART0_IR_RX_PIN (USART0_IRRX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_IR_RX_MUX 11 +#define RTE_USART0_IR_RX_PAD 22 +#endif +#if (USART0_IRRX_LOC == 29) +#define RTE_USART0_IR_RX_PIN (USART0_IRRX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_IR_RX_MUX 2 +#define RTE_USART0_IR_RX_PAD 29 +#endif +//Pintool data +#endif // USART0_RI <0=>P0_27 <1=>P0_46 <2=>P0_68 // RI for USART0 +#ifndef USART0_RI_LOC #define RTE_RI_PORT_ID 0 #if (RTE_RI_PORT_ID == 0) @@ -300,9 +489,30 @@ #else #error "Invalid USART0 RTE_USART0_RI_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_RI_PORT USART0_RI_PORT +#if (USART0_RI_LOC == 30) +#define RTE_USART0_RI_PIN USART0_RI_PIN +#define RTE_USART0_RI_MUX 2 +#define RTE_USART0_RI_PAD 0 //no pad +#endif +#if (USART0_RI_LOC == 31) +#define RTE_USART0_RI_PIN USART0_RI_PIN +#define RTE_USART0_RI_MUX 2 +#define RTE_USART0_RI_PAD 10 +#endif +#if (USART0_RI_LOC == 32) +#define RTE_USART0_RI_PIN (USART0_RI_PIN + GPIO_MAX_PIN) +#define RTE_USART0_RI_MUX 11 +#define RTE_USART0_RI_PAD 26 +#endif +//Pintool data +#endif // USART0_DSR <0=>P0_11 <1=>P0_57 // DSR for USART0 +#ifndef USART0_DSR_LOC #define RTE_DSR_PORT_ID 0 #if (RTE_DSR_PORT_ID == 0) @@ -318,27 +528,56 @@ #else #error "Invalid USART0 RTE_USART0_RI_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_DSR_PORT USART0_DSR_PORT +#define RTE_USART0_DSR_PIN USART0_DSR_PIN +#if (USART0_DSR_LOC == 33) +#define RTE_USART0_DSR_MUX 2 +#define RTE_USART0_DSR_PAD 6 +#endif +#if (USART0_DSR_LOC == 34) +#define RTE_USART0_DSR_MUX 2 +#define RTE_USART0_DSR_PAD 21 +#endif +//Pintool data +#endif + // USART0_DCD <0=>P0_12 <1=>P0_29 // DCD for USART0 - +#ifndef USART0_DCD_LOC #define RTE_USART0_DCD_PORT 0 #define RTE_USART0_DCD_PIN 12 -#define RTE_USART0_DCD_MUX 2 -#define RTE_USART0_DCD_PAD 7 +#else +#define RTE_USART0_DCD_PORT USART0_DCD_PORT +#define RTE_USART0_DCD_PIN USART0_DCD_PIN +#if (USART0_DCD_LOC == 35) +#define RTE_USART0_DCD_MUX 2 +#define RTE_USART0_DCD_PAD 7 +#elif (USART0_DCD_LOC == 36) +#define RTE_USART0_DCD_MUX 12 +#define RTE_USART0_DCD_PAD 0 +#endif +#endif // USART0_DTR <0=>P0_7 // DTR for USART0 +#ifndef USART0_DTR_LOC #define RTE_USART0_DTR_PORT 0 #define RTE_USART0_DTR_PIN 7 -#define RTE_USART0_DTR_MUX 2 -#define RTE_USART0_DTR_PAD 2 +#else +#define RTE_USART0_DTR_PORT USART0_DTR_PORT +#define RTE_USART0_DTR_PIN USART0_DTR_PIN +#endif +#define RTE_USART0_DTR_MUX 2 +#define RTE_USART0_DTR_PAD 2 // // UART1 [Driver_UART1] // Configuration settings for Driver_UART1 in component ::CMSIS Driver:USART #define RTE_UART1 1 -#define RTE_UART1_CLK_SRC USART_INTFPLLCLK +#define RTE_UART1_CLK_SRC USART_ULPREFCLK #define RTE_UART1_CLK_DIV_FACT 1 #define RTE_UART1_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER @@ -358,7 +597,7 @@ /*UART1 PINS*/ // UART1_TX <0=>P0_7 <1=>P0_30 <2=>P0_67 <3=>P0_69 <4=>P0_73 <5=>P0_75 <6=>P0_34 // TX of UART1 - +#ifndef UART1_TX_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_UART1_TX_PORT_ID 0 #else @@ -397,10 +636,40 @@ #else #error "Invalid UART1 RTE_UART1_TX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_UART1_TX_PORT UART1_TX_PORT +#if (UART1_TX_LOC == 0) +#define RTE_UART1_TX_PIN UART1_TX_PIN +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 2 +#endif +#if (UART1_TX_LOC == 1) +#define RTE_UART1_TX_PIN UART1_TX_PIN +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 0 //no pad +#endif +#if (UART1_TX_LOC == 2) +#define RTE_UART1_TX_PIN (UART1_TX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 27 +#endif +#if (UART1_TX_LOC == 3) +#define RTE_UART1_TX_PIN (UART1_TX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 31 +#endif +#if (UART1_TX_LOC == 4) +#define RTE_UART1_TX_PIN (UART1_TX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_TX_MUX 9 +#define RTE_UART1_TX_PAD 33 +#endif +//Pintool data +#endif // UART1_RX <0=>P0_6 <1=>P0_29 <2=>P0_66 <3=>P0_68 <4=>P0_72 <5=>P0_74 <6=>P0_33 // RX of UART1 - +#ifndef UART1_RX_LOC #define RTE_UART1_RX_PORT_ID 0 #if (RTE_UART1_RX_PORT_ID == 0) @@ -431,9 +700,40 @@ #else #error "Invalid UART1 RTE_UART1_RX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_UART1_RX_PORT UART1_RX_PORT +#if (UART1_RX_LOC == 5) +#define RTE_UART1_RX_PIN UART1_RX_PIN +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 1 +#endif +#if (UART1_RX_LOC == 6) +#define RTE_UART1_RX_PIN UART1_RX_PIN +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 0 //no pad +#endif +#if (UART1_RX_LOC == 7) +#define RTE_UART1_RX_PIN (UART1_RX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 26 +#endif +#if (UART1_RX_LOC == 8) +#define RTE_UART1_RX_PIN (UART1_RX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 30 +#endif +#if (UART1_RX_LOC == 9) +#define RTE_UART1_RX_PIN (UART1_RX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RX_MUX 9 +#define RTE_UART1_RX_PAD 32 +#endif +//Pintool data +#endif // UART1_CTS <0=>P0_11 <1=>P0_28 <2=>P0_51 <3=>P0_65 <4=>P0_71 <5=>P0_73 <6=>P0_32 // CTS of UART1 +#ifndef UART1_CTS_LOC #define RTE_UART1_CTS_PORT_ID 0 #if (RTE_UART1_CTS_PORT_ID == 0) @@ -464,10 +764,45 @@ #else #error "Invalid UART1 RTE_UART1_CTS_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_UART1_CTS_PORT UART1_CTS_PORT +#if (UART1_CTS_LOC == 10) +#define RTE_UART1_CTS_PIN UART1_CTS_PIN +#define RTE_UART1_CTS_MUX 6 +#define RTE_UART1_CTS_PAD 6 +#endif +#if (UART1_CTS_LOC == 11) +#define RTE_UART1_CTS_PIN UART1_CTS_PIN +#define RTE_UART1_CTS_MUX 6 +#define RTE_UART1_CTS_PAD 0 //no pad +#endif +#if (UART1_CTS_LOC == 12) +#define RTE_UART1_CTS_PIN UART1_CTS_PIN +#define RTE_UART1_CTS_MUX 9 +#define RTE_UART1_CTS_PAD 15 +#endif +#if (UART1_CTS_LOC == 13) +#define RTE_UART1_CTS_PIN (UART1_CTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_CTS_MUX 9 +#define RTE_UART1_CTS_PAD 23 +#endif +#if (UART1_CTS_LOC == 14) +#define RTE_UART1_CTS_PIN (UART1_CTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_CTS_MUX 6 +#define RTE_UART1_CTS_PAD 29 +#endif +#if (UART1_CTS_LOC == 15) +#define RTE_UART1_CTS_PIN (UART1_CTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_CTS_MUX 9 +#define RTE_UART1_CTS_PAD 31 +#endif +//Pintool data +#endif // UART1_RTS <0=>P0_10 <1=>P0_27 <2=>P0_50 <3=>P0_64 <4=>P0_70 <5=>P0_72 <6=>P0_31 // RTS of UART1 - +#ifndef UART1_RTS_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_UART1_RTS_PORT_ID 0 #else @@ -502,6 +837,42 @@ #else #error "Invalid UART1 RTE_UART1_RTS_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_UART1_RTS_PORT UART1_RTS_PORT +#if (UART1_RTS_LOC == 16) +#define RTE_UART1_RTS_PIN UART1_RTS_PIN +#define RTE_UART1_RTS_MUX 6 +#define RTE_UART1_RTS_PAD 5 +#endif +#if (UART1_RTS_LOC == 17) +#define RTE_UART1_RTS_PIN UART1_RTS_PIN +#define RTE_UART1_RTS_MUX 6 +#define RTE_UART1_RTS_PAD 0 //no pad +#endif +#if (UART1_RTS_LOC == 18) +#define RTE_UART1_RTS_PIN UART1_RTS_PIN +#define RTE_UART1_RTS_MUX 9 +#define RTE_UART1_RTS_PAD 14 +#endif +#if (UART1_RTS_LOC == 19) +#define RTE_UART1_RTS_PIN (UART1_RTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RTS_MUX 9 +#define RTE_UART1_RTS_PAD 22 +#endif +#if (UART1_RTS_LOC == 20) +#define RTE_UART1_RTS_PIN (UART1_RTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RTS_MUX 6 +#define RTE_UART1_RTS_PAD 28 +#endif +#if (UART1_RTS_LOC == 21) +#define RTE_UART1_RTS_PIN (UART1_RTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RTS_MUX 9 +#define RTE_UART1_RTS_PAD 30 +#endif +//Pintool data +#endif + // // ULP_UART [Driver_ULP_UART] @@ -528,6 +899,7 @@ /*ULPSS UART PINS*/ // UART1_TX <0=>P0_3 <1=>P0_7 <2=>P0_11 // TX of ULPSS UART +#ifndef ULP_UART_TX_LOC #define RTE_ULP_UART_TX_PORT_ID 1 #if (RTE_ULP_UART_TX_PORT_ID == 0) #define RTE_ULP_UART_TX_PORT 0 @@ -540,9 +912,17 @@ #else #error "Invalid ULPSS UART RTE_ULP_UART_TX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_ULP_UART_TX_PORT ULP_UART_TX_PORT +#define RTE_ULP_UART_TX_PIN ULP_UART_TX_PIN +#define RTE_ULP_UART_TX_MUX 3 +//Pintool data +#endif // UART1_RX <0=>P0_2 <1=>P0_6 <2=>P0_9 // RX of ULPSS UART +#ifndef ULP_UART_RX_LOC #define RTE_ULP_UART_RX_PORT_ID 2 #if (RTE_ULP_UART_RX_PORT_ID == 0) #define RTE_ULP_UART_RX_PORT 0 @@ -559,9 +939,17 @@ #else #error "Invalid ULPSS UART RTE_ULP_UART_RX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_ULP_UART_RX_PORT ULP_UART_RX_PORT +#define RTE_ULP_UART_RX_PIN ULP_UART_RX_PIN +#define RTE_ULP_UART_RX_MUX 3 +//Pintool data +#endif // UART1_CTS <0=>P0_1 <1=>P0_5 <2=>P0_8 // CTS of ULPSS UART +#ifndef ULP_UART_CTS_LOC #define RTE_ULP_UART_CTS_PORT_ID 0 #if (RTE_ULP_UART_CTS_PORT_ID == 0) #define RTE_ULP_UART_CTS_PORT 0 @@ -574,17 +962,30 @@ #else #error "Invalid ULPSS UART RTE_ULP_UART_CTS_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_ULP_UART_CTS_PORT ULP_UART_CTS_PORT +#define RTE_ULP_UART_CTS_PIN ULP_UART_CTS_PIN +#define RTE_ULP_UART_CTS_MUX 3 +//Pintool data +#endif // UART1_RTS <0=>P0_0 <1=>P0_4 <2=>P0_10 // RTS of ULPSS UART +#ifndef ULP_UART_RTS_LOC #define RTE_ULP_UART_RTS_PORT_ID 0 #if (RTE_ULP_UART_RTS_PORT_ID == 0) #define RTE_ULP_UART_RTS_PORT 0 #define RTE_ULP_UART_RTS_PIN 10 -#define RTE_ULP_UART_RTS_MUX 3 #else #error "Invalid ULPSS UART RTE_ULP_UART_RTS_PIN Pin Configuration!" #endif +#else +#define RTE_ULP_UART_RTS_PORT ULP_UART_RTS_PORT +#define RTE_ULP_UART_RTS_PIN ULP_UART_RTS_PIN +#endif +#define RTE_ULP_UART_RTS_MUX 8 + // // SSI_MASTER (Serial Peripheral Interface 1) [Driver_SSI_MASTER] @@ -592,7 +993,7 @@ #define RTE_SSI_MASTER 1 // SSI_MASTER_MISO Pin <0=>GPIO_12 <1=>GPIO_27 <2=>GPIO_57 - +#ifndef SSI_MASTER_DATA1_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SSI_MASTER_MISO_PORT_ID 1 #else @@ -620,8 +1021,26 @@ #else #error "Invalid SSI_MASTER_MISO Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_MASTER_MISO 1 +#define RTE_SSI_MASTER_MISO_PORT SSI_MASTER_MISO_DATA1_PORT +#define RTE_SSI_MASTER_MISO_PIN SSI_MASTER_MISO_DATA1_PIN +#define RTE_SSI_MASTER_MISO_MODE EGPIO_PIN_MUX_MODE3 +#if (SSI_MASTER_DATA1_LOC == 3) +#define RTE_SSI_MASTER_MISO_PADSEL 7 +#endif +#if (SSI_MASTER_DATA1_LOC == 4) +#define RTE_SSI_MASTER_MISO_PADSEL 0 //NO PAD +#endif +#if (SSI_MASTER_DATA1_LOC == 5) +#define RTE_SSI_MASTER_MISO_PADSEL 21 +#endif +//Pintool data +#endif // SSI_MASTER_MOSI Pin <0=>GPIO_11 <1=>GPIO_26 <2=>GPIO_56 +#ifndef SSI_MASTER_DATA0_LOC #define RTE_SSI_MASTER_MOSI_PORT_ID 1 #if (RTE_SSI_MASTER_MOSI_PORT_ID == 0) @@ -645,8 +1064,26 @@ #else #error "Invalid SSI_MASTER_MOSI Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_MASTER_MOSI 1 +#define RTE_SSI_MASTER_MOSI_PORT SSI_MASTER_MOSI_DATA0_PORT +#define RTE_SSI_MASTER_MOSI_PIN SSI_MASTER_MOSI_DATA0_PIN +#define RTE_SSI_MASTER_MOSI_MODE EGPIO_PIN_MUX_MODE3 +#if (SSI_MASTER_DATA0_LOC == 0) +#define RTE_SSI_MASTER_MOSI_PADSEL 6 +#endif +#if (SSI_MASTER_DATA0_LOC == 1) +#define RTE_SSI_MASTER_MOSI_PADSEL 0 //NO PAD +#endif +#if (SSI_MASTER_DATA0_LOC == 2) +#define RTE_SSI_MASTER_MOSI_PADSEL 20 +#endif +//Pintool data +#endif // SSI_MASTER_SCK Pin <0=>GPIO_8 <1=>GPIO_25 <2=>GPIO_52 +#ifndef SSI_MASTER_SCK_LOC #define RTE_SSI_MASTER_SCK_PORT_ID 1 #if (RTE_SSI_MASTER_SCK_PORT_ID == 0) @@ -670,6 +1107,23 @@ #else #error "Invalid SSI_MASTER_SCK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_MASTER_SCK 1 +#define RTE_SSI_MASTER_SCK_PORT SSI_MASTER_SCK__PORT +#define RTE_SSI_MASTER_SCK_PIN SSI_MASTER_SCK__PIN +#define RTE_SSI_MASTER_SCK_MODE EGPIO_PIN_MUX_MODE3 +#if (SSI_MASTER_SCK_LOC == 6) +#define RTE_SSI_MASTER_SCK_PADSEL 3 +#endif +#if (SSI_MASTER_SCK_LOC == 7) +#define RTE_SSI_MASTER_SCK_PADSEL 0 //NO PAD +#endif +#if (SSI_MASTER_SCK_LOC == 8) +#define RTE_SSI_MASTER_SCK_PADSEL 16 +#endif +//Pintool data +#endif #define M4_SSI_CS0 1 #define M4_SSI_CS1 0 @@ -677,6 +1131,7 @@ #define M4_SSI_CS3 0 // SSI_MASTER_CS Pin <0=>GPIO_9 <1=>GPIO_28 <2=>GPIO_53 <3=>GPIO_10 <4=>GPIO_15 <5=>GPIO_50 <6=>GPIO_51 +#ifndef SSI_MASTER_CS0_LOC #define RTE_SSI_MASTER_CS0_PORT_ID 1 #if (RTE_SSI_MASTER_CS0_PORT_ID == 0) @@ -700,20 +1155,43 @@ #else #error "Invalid SSI_MASTER_CS0 Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_MASTER_CS0 M4_SSI_CS0 +#define RTE_SSI_MASTER_CS0_PORT SSI_MASTER_CS0__PORT +#define RTE_SSI_MASTER_CS0_PIN SSI_MASTER_CS0__PIN +#define RTE_SSI_MASTER_CS0_MODE EGPIO_PIN_MUX_MODE3 +#if (SSI_MASTER_CS0_LOC == 9) +#define RTE_SSI_MASTER_CS0_PADSEL 4 +#endif +#if (SSI_MASTER_CS0_LOC == 10) +#define RTE_SSI_MASTER_CS0_PADSEL 0 //NO PAD +#endif +#if (SSI_MASTER_CS0_LOC == 11) +#define RTE_SSI_MASTER_CS0_PADSEL 17 +#endif +//Pintool data +#endif //CS1 +#ifndef SSI_MASTER_CS1_LOC #define RTE_SSI_MASTER_CS1_PORT_ID 0 #if (RTE_SSI_MASTER_CS1_PORT_ID == 0) -#define RTE_SSI_MASTER_CS1 M4_SSI_CS1 -#define RTE_SSI_MASTER_CS1_PORT 0 -#define RTE_SSI_MASTER_CS1_PIN 10 -#define RTE_SSI_MASTER_CS1_MODE EGPIO_PIN_MUX_MODE3 -#define RTE_SSI_MASTER_CS1_PADSEL 5 +#define RTE_SSI_MASTER_CS1_PORT 0 +#define RTE_SSI_MASTER_CS1_PIN 10 #else #error "Invalid SSI_MASTER_CS1 Pin Configuration!" #endif +#else +#define RTE_SSI_MASTER_CS1_PORT SSI_MASTER_CS1__PORT +#define RTE_SSI_MASTER_CS1_PIN SSI_MASTER_CS1__PIN +#endif +#define RTE_SSI_MASTER_CS1 M4_SSI_CS1 +#define RTE_SSI_MASTER_CS1_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS1_PADSEL 5 //CS2 +#ifndef SSI_MASTER_CS2_LOC #define RTE_SSI_MASTER_CS2_PORT_ID 1 #if (RTE_SSI_MASTER_CS2_PORT_ID == 0) #define RTE_SSI_MASTER_CS2 M4_SSI_CS2 @@ -730,18 +1208,37 @@ #else #error "Invalid SSI_MASTER_CS2 Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_MASTER_CS2 M4_SSI_CS2 +#define RTE_SSI_MASTER_CS2_PORT SSI_MASTER_CS2__PORT +#define RTE_SSI_MASTER_CS2_PIN SSI_MASTER_CS2__PIN +#define RTE_SSI_MASTER_CS2_MODE EGPIO_PIN_MUX_MODE3 +#if (SSI_MASTER_CS2_LOC == 13) +#define RTE_SSI_MASTER_CS2_PADSEL 8 +#endif +#if (SSI_MASTER_CS2_LOC == 14) +#define RTE_SSI_MASTER_CS2_PADSEL 14 +#endif +//Pintool data +#endif //CS3 +#ifndef SSI_MASTER_CS3_LOC #define RTE_SSI_MASTER_CS3_PORT_ID 0 #if (RTE_SSI_MASTER_CS3_PORT_ID == 0) -#define RTE_SSI_MASTER_CS3 M4_SSI_CS3 -#define RTE_SSI_MASTER_CS3_PORT 0 -#define RTE_SSI_MASTER_CS3_PIN 51 -#define RTE_SSI_MASTER_CS3_MODE EGPIO_PIN_MUX_MODE3 -#define RTE_SSI_MASTER_CS3_PADSEL 15 +#define RTE_SSI_MASTER_CS3_PORT 0 +#define RTE_SSI_MASTER_CS3_PIN 51 #else #error "Invalid SSI_MASTER_CS3 Pin Configuration!" #endif +#else +#define RTE_SSI_MASTER_CS3_PORT SSI_MASTER_CS3__PORT +#define RTE_SSI_MASTER_CS3_PIN SSI_MASTER_CS3__PIN +#endif +#define RTE_SSI_MASTER_CS3 M4_SSI_CS3 +#define RTE_SSI_MASTER_CS3_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS3_PADSEL 15 // DMA Rx // Channel <28=>28 @@ -763,6 +1260,7 @@ #define RTE_SSI_SLAVE_INPUT_CLOCK SSISLAVE_CLK // SSI_SLAVE_MISO Pin <0=>Not Used <1=>GPIO_11 <2=>GPIO_28 <3=>GPIO_49 <4=>GPIO_57 +#ifndef SSI_SLAVE_MISO_LOC #define RTE_SSI_SLAVE_MISO_PORT_ID 2 #if (RTE_SSI_SLAVE_MISO_PORT_ID == 0) @@ -794,9 +1292,29 @@ #else #error "Invalid SSI_SLAVE_MISO Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_SLAVE_MISO 1 +#define RTE_SSI_SLAVE_MISO_PORT SSI_SLAVE_MISO__PORT +#define RTE_SSI_SLAVE_MISO_PIN SSI_SLAVE_MISO__PIN +#define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8 +#if (SSI_SLAVE_MISO_LOC == 5) +#define RTE_SSI_SLAVE_MISO_PADSEL 6 +#endif +#if (SSI_SLAVE_MISO_LOC == 6) +#define RTE_SSI_SLAVE_MISO_PADSEL 0 //no pad +#endif +#if (SSI_SLAVE_MISO_LOC == 7) +#define RTE_SSI_SLAVE_MISO_PADSEL 13 +#endif +#if (SSI_SLAVE_MISO_LOC == 8) +#define RTE_SSI_SLAVE_MISO_PADSEL 21 +#endif +//Pintool data +#endif // SSI_SLAVE_MOSI Pin <0=>Not Used <1=>GPIO_10 <2=>GPIO_27 <3=>GPIO_48 <4=>GPIO_56 - +#ifndef SSI_SLAVE_MOSI_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SSI_SLAVE_MOSI_PORT_ID 2 #else @@ -832,8 +1350,29 @@ #else #error "Invalid SSI_SLAVE_MOSI Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_SLAVE_MOSI 1 +#define RTE_SSI_SLAVE_MOSI_PORT SSI_SLAVE_MOSI__PORT +#define RTE_SSI_SLAVE_MOSI_PIN SSI_SLAVE_MOSI__PIN +#define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8 +#if (SSI_SLAVE_MOSI_LOC == 1) +#define RTE_SSI_SLAVE_MOSI_PADSEL 5 +#endif +#if (SSI_SLAVE_MOSI_LOC == 2) +#define RTE_SSI_SLAVE_MOSI_PADSEL 0 //no pad +#endif +#if (SSI_SLAVE_MOSI_LOC == 3) +#define RTE_SSI_SLAVE_MOSI_PADSEL 12 +#endif +#if (SSI_SLAVE_MOSI_LOC == 4) +#define RTE_SSI_SLAVE_MOSI_PADSEL 20 +#endif +//Pintool data +#endif // SSI_SLAVE_SCK Pin <0=>Not Used <1=>GPIO_8 <2=>GPIO_26 <3=>GPIO_47 <4=>GPIO_52 +#ifndef SSI_SLAVE_SCK_LOC #define RTE_SSI_SLAVE_SCK_PORT_ID 2 #if (RTE_SSI_SLAVE_SCK_PORT_ID == 0) @@ -865,9 +1404,30 @@ #else #error "Invalid SSI_SLAVE_SCK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_SLAVE_SCK 1 +#define RTE_SSI_SLAVE_SCK_PORT SSI_SLAVE_SCK__PORT +#define RTE_SSI_SLAVE_SCK_PIN SSI_SLAVE_SCK__PIN +#define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8 +#if (SSI_SLAVE_SCK_LOC == 9) +#define RTE_SSI_SLAVE_SCK_PADSEL 3 +#endif +#if (SSI_SLAVE_SCK_LOC == 10) +#define RTE_SSI_SLAVE_SCK_PADSEL 0 //no pad +#endif +#if (SSI_SLAVE_SCK_LOC == 11) +#define RTE_SSI_SLAVE_SCK_PADSEL 11 +#endif +#if (SSI_SLAVE_SCK_LOC == 12) +#define RTE_SSI_SLAVE_SCK_PADSEL 16 +#endif +//Pintool data +#endif // SSI_SLAVE_CS Pin <0=>Not Used <1=>GPIO_9 <2=>GPIO_25 <3=>GPIO_46 <4=>GPIO_53 -#define RTE_SSI_SLAVE_CS_PORT_ID 1 +#ifndef SSI_SLAVE_CS0_LOC +#define RTE_SSI_SLAVE_CS_PORT_ID 2 #if (RTE_SSI_SLAVE_CS_PORT_ID == 0) #define RTE_SSI_SLAVE_CS 0 @@ -898,6 +1458,26 @@ #else #error "Invalid SSI_SLAVE_CS Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_SLAVE_CS 1 +#define RTE_SSI_SLAVE_CS_PORT SSI_SLAVE_CS0__PORT +#define RTE_SSI_SLAVE_CS_PIN SSI_SLAVE_CS0__PIN +#define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8 +#if (SSI_SLAVE_CS0_LOC == 13) +#define RTE_SSI_SLAVE_CS_PADSEL 4 +#endif +#if (SSI_SLAVE_CS0_LOC == 14) +#define RTE_SSI_SLAVE_CS_PADSEL 0 //no pad +#endif +#if (SSI_SLAVE_CS0_LOC == 15) +#define RTE_SSI_SLAVE_CS_PADSEL 10 +#endif +#if (SSI_SLAVE_CS0_LOC == 16) +#define RTE_SSI_SLAVE_CS_PADSEL 17 +#endif +//Pintool data +#endif // DMA Rx // Channel <22=>22 @@ -915,7 +1495,7 @@ // -// SSI_ULP_MASTER (Serial Peripheral Interface 3) [Driver_SSI_ULP_MASTER] +// ULP SPI Peripheral (Serial Peripheral Interface 3) [Driver_SSI_ULP_MASTER] // Configuration settings for Driver_SSI_ULP_MASTER in component ::CMSIS Driver:SPI #define RTE_SSI_ULP_MASTER 1 @@ -925,6 +1505,7 @@ #define ULP_SSI_CS2 0 // SSI_ULP_MASTER_MISO Pin <0=>Not Used <1=>ULP_GPIO_2 <2=>ULP_GPIO_9 +#ifndef ULP_SPI_MISO_LOC #define RTE_SSI_ULP_MASTER_MISO_PORT_ID 0 #if (RTE_SSI_ULP_MASTER_MISO_PORT_ID == 0) #define RTE_SSI_ULP_MASTER_MISO 1 @@ -939,8 +1520,17 @@ #else #error "Invalid SSI_ULP_MISO Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_ULP_MASTER_MISO 1 +#define RTE_SSI_ULP_MASTER_MISO_PORT ULP_SPI_MISO__PORT +#define RTE_SSI_ULP_MASTER_MISO_PIN ULP_SPI_MISO__PIN +#define RTE_SSI_ULP_MASTER_MISO_MODE 1 +//Pintool data +#endif // SSI_ULP_MASTER_MOSI Pin <0=>Not Used <1=>ULP_GPIO_1 <2=>ULP_GPIO_11 +#ifndef ULP_SPI_MOSI_LOC #define RTE_SSI_ULP_MASTER_MOSI_PORT_ID 0 #if (RTE_SSI_ULP_MASTER_MOSI_PORT_ID == 0) #define RTE_SSI_ULP_MASTER_MOSI 1 @@ -955,8 +1545,17 @@ #else #error "Invalid SSI_ULP_MOSI Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_ULP_MASTER_MOSI 1 +#define RTE_SSI_ULP_MASTER_MOSI_PORT ULP_SPI_MOSI__PORT +#define RTE_SSI_ULP_MASTER_MOSI_PIN ULP_SPI_MOSI__PIN +#define RTE_SSI_ULP_MASTER_MOSI_MODE 1 +//Pintool data +#endif // SSI_ULP_MASTER_SCK Pin <0=>Not Used <1=>ULP_GPIO_0 <2=>ULP_GPIO_8 +#ifndef ULP_SPI_SCK_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SSI_ULP_MASTER_SCK_PORT_ID 2 #else @@ -977,8 +1576,17 @@ #else #error "Invalid SSI_ULP_SCK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_ULP_MASTER_SCK 1 +#define RTE_SSI_ULP_MASTER_SCK_PORT ULP_SPI_SCK__PORT +#define RTE_SSI_ULP_MASTER_SCK_PIN ULP_SPI_SCK__PIN +#define RTE_SSI_ULP_MASTER_SCK_MODE 1 +//Pintool data +#endif // CS0 +#ifndef ULP_SPI_CS0_LOC #define RTE_SSI_ULP_MASTER_CS0_PORT_ID 1 #if (RTE_SSI_ULP_MASTER_CS0_PORT_ID == 0) #define RTE_SSI_ULP_MASTER_CS0 ULP_SSI_CS0 @@ -993,17 +1601,35 @@ #else #error "Change RTE_SSI_ULP_MASTER_CS_PORT_ID other than '1' or'3' as per PACKAGE_TYPE" #endif +#else +//Pintool data +#define RTE_SSI_ULP_MASTER_CS0 ULP_SSI_CS0 +#define RTE_SSI_ULP_MASTER_CS0_PORT ULP_SPI_CS0__PORT +#define RTE_SSI_ULP_MASTER_CS0_PIN ULP_SPI_CS0__PIN +#define RTE_SSI_ULP_MASTER_CS0_MODE 1 +//Pintool data +#endif // CS1 -#define RTE_SSI_ULP_MASTER_CS1 ULP_SSI_CS1 +#ifndef ULP_SPI_CS1_LOC #define RTE_SSI_ULP_MASTER_CS1_PORT 0 #define RTE_SSI_ULP_MASTER_CS1_PIN 4 +#else +#define RTE_SSI_ULP_MASTER_CS1_PORT ULP_SPI_CS1__PORT +#define RTE_SSI_ULP_MASTER_CS1_PIN ULP_SPI_CS1__PIN +#endif +#define RTE_SSI_ULP_MASTER_CS1 ULP_SSI_CS1 #define RTE_SSI_ULP_MASTER_CS1_MODE 1 // CS2 -#define RTE_SSI_ULP_MASTER_CS2 ULP_SSI_CS2 +#ifndef ULP_SPI_CS2_LOC #define RTE_SSI_ULP_MASTER_CS2_PORT 0 #define RTE_SSI_ULP_MASTER_CS2_PIN 6 +#else +#define RTE_SSI_ULP_MASTER_CS2_PORT ULP_SPI_CS2__PORT +#define RTE_SSI_ULP_MASTER_CS2_PIN ULP_SPI_CS2__PIN +#endif +#define RTE_SSI_ULP_MASTER_CS2 ULP_SSI_CS2 #define RTE_SSI_ULP_MASTER_CS2_MODE 1 // DMA Rx @@ -1064,6 +1690,7 @@ // I2S0_SCLK <0=>P0_8 <1=>P0_25 <2=>P0_46 <3=>P0_52 // SCLK of I2S0 +#ifndef I2S0_SCLK_LOC #define RTE_I2S0_SCLK_PORT_ID 1 #if (RTE_I2S0_SCLK_PORT_ID == 0) @@ -1089,9 +1716,29 @@ #else #error "Invalid I2S0 RTE_I2S0_SCLK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S0_SCLK_PORT I2S0_SCLK_PORT +#define RTE_I2S0_SCLK_PIN I2S0_SCLK_PIN +#define RTE_I2S0_SCLK_MUX 7 +#if (I2S0_SCLK_LOC == 0) +#define RTE_I2S0_SCLK_PAD 3 +#endif +#if (I2S0_SCLK_LOC == 1) +#define RTE_I2S0_SCLK_PAD 0 //no pad +#endif +#if (I2S0_SCLK_LOC == 2) +#define RTE_I2S0_SCLK_PAD 10 +#endif +#if (I2S0_SCLK_LOC == 3) +#define RTE_I2S0_SCLK_PAD 16 +#endif +//Pintool data +#endif // I2S0_WSCLK <0=>P0_9 <1=>P0_26 <2=>P0_47 <3=>P0_53 // WSCLK for I2S0 +#ifndef I2S0_WSCLK_LOC #define RTE_I2S0_WSCLK_PORT_ID 1 #if (RTE_I2S0_WSCLK_PORT_ID == 0) @@ -1117,9 +1764,29 @@ #else #error "Invalid I2S0 RTE_I2S0_WSCLK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S0_WSCLK_PORT I2S0_WSCLK_PORT +#define RTE_I2S0_WSCLK_PIN I2S0_WSCLK_PIN +#define RTE_I2S0_WSCLK_MUX 7 +#if (I2S0_WSCLK_LOC == 4) +#define RTE_I2S0_WSCLK_PAD 4 +#endif +#if (I2S0_WSCLK_LOC == 5) +#define RTE_I2S0_WSCLK_PAD 0 +#endif +#if (I2S0_WSCLK_LOC == 6) +#define RTE_I2S0_WSCLK_PAD 11 +#endif +#if (I2S0_WSCLK_LOC == 7) +#define RTE_I2S0_WSCLK_PAD 17 +#endif +//Pintool data +#endif // I2S0_DOUT0 <0=>P0_11 <1=>P0_28 <2=>P0_49 <3=>P0_57 // DOUT0 for I2S0 +#ifndef I2S0_DOUT0_LOC #define RTE_I2S0_DOUT0_PORT_ID 1 #if (RTE_I2S0_DOUT0_PORT_ID == 0) @@ -1145,9 +1812,29 @@ #else #error "Invalid I2S0 RTE_I2S0_DOUT0 Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S0_DOUT0_PORT I2S0_DOUT0_PORT +#define RTE_I2S0_DOUT0_PIN I2S0_DOUT0_PIN +#define RTE_I2S0_DOUT0_MUX 7 +#if (I2S0_DOUT0_LOC == 8) +#define RTE_I2S0_DOUT0_PAD 6 +#endif +#if (I2S0_DOUT0_LOC == 9) +#define RTE_I2S0_DOUT0_PAD 0 +#endif +#if (I2S0_DOUT0_LOC == 10) +#define RTE_I2S0_DOUT0_PAD 13 +#endif +#if (I2S0_DOUT0_LOC == 11) +#define RTE_I2S0_DOUT0_PAD 21 +#endif +//Pintool data +#endif // I2S0_DIN0 <0=>P0_10 <1=>P0_27 <2=>P0_48 <3=>P0_56 // DIN0 for I2S0 +#ifndef I2S0_DIN0_LOC #define RTE_I2S0_DIN0_PORT_ID 1 #if (RTE_I2S0_DIN0_PORT_ID == 0) @@ -1173,11 +1860,30 @@ #else #error "Invalid I2S0 RTE_I2S0_DIN0 Pin Configuration!" #endif - -// I2S0_DOUT1 <0=>P0_7 <1=>P0_30 <2=>P0_51 <3=>P0_55 -// DOUT1 for I2S0 - -#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#else +//Pintool data +#define RTE_I2S0_DIN0_PORT I2S0_DIN0_PORT +#define RTE_I2S0_DIN0_PIN I2S0_DIN0_PIN +#define RTE_I2S0_DIN0_MUX 7 +#if (I2S0_DIN0_LOC == 12) +#define RTE_I2S0_DIN0_PAD 5 +#endif +#if (I2S0_DIN0_LOC == 13) +#define RTE_I2S0_DIN0_PAD 0 +#endif +#if (I2S0_DIN0_LOC == 14) +#define RTE_I2S0_DIN0_PAD 12 +#endif +#if (I2S0_DIN0_LOC == 15) +#define RTE_I2S0_DIN0_PAD 20 +#endif +//Pintool data +#endif + +// I2S0_DOUT1 <0=>P0_7 <1=>P0_30 <2=>P0_51 <3=>P0_55 +// DOUT1 for I2S0 +#ifndef I2S0_DOUT1_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_I2S0_DOUT1_PORT_ID 1 #else #define RTE_I2S0_DOUT1_PORT_ID 0 @@ -1206,9 +1912,29 @@ #else #error "Invalid I2S0 RTE_I2S0_DOUT1 Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S0_DOUT1_PORT I2S0_DOUT1_PORT +#define RTE_I2S0_DOUT1_PIN I2S0_DOUT1_PIN +#define RTE_I2S0_DOUT1_MUX 7 +#if (I2S0_DOUT1_LOC == 16) +#define RTE_I2S0_DOUT1_PAD 2 +#endif +#if (I2S0_DOUT1_LOC == 17) +#define RTE_I2S0_DOUT1_PAD 0 +#endif +#if (I2S0_DOUT1_LOC == 18) +#define RTE_I2S0_DOUT1_PAD 15 +#endif +#if (I2S0_DOUT1_LOC == 19) +#define RTE_I2S0_DOUT1_PAD 19 +#endif +//Pintool data +#endif // I2S0_DIN1 <0=>P0_6 <1=>P0_29 <2=>P0_50 <3=>P0_54 // DIN1 for I2S0 +#ifndef I2S0_DIN1_LOC #define RTE_I2S0_DIN1_PORT_ID 0 #if (RTE_I2S0_DIN1_PORT_ID == 0) @@ -1234,8 +1960,27 @@ #else #error "Invalid I2S0 RTE_I2S0_DIN1 Pin Configuration!" #endif -// FIFO level can have value 1 to 7 -#define I2S0_TX_FIFO_LEVEL (2U) +#else +//Pintool data +#define RTE_I2S0_DIN1_PORT I2S0_DIN1_PORT +#define RTE_I2S0_DIN1_PIN I2S0_DIN1_PIN +#define RTE_I2S0_DIN1_MUX 7 +#if (I2S0_DIN1_LOC == 20) +#define RTE_I2S0_DIN1_PAD 1 +#endif +#if (I2S0_DIN1_LOC == 21) +#define RTE_I2S0_DIN1_PAD 0 +#endif +#if (I2S0_DIN1_LOC == 22) +#define RTE_I2S0_DIN1_PAD 14 +#endif +#if (I2S0_DIN1_LOC == 23) +#define RTE_I2S0_DIN1_PAD 18 +#endif +//Pintool data +#endif +// FIFO level can have value 0 to 7 +#define I2S0_TX_FIFO_LEVEL (0U) #define I2S0_RX_FIFO_LEVEL (2U) // I2S0_TX_RES <0=>12 @@ -1283,13 +2028,14 @@ // -// I2S1 [Driver_I2S1] +// ULP I2S [Driver_I2S1] // Configuration settings for Driver_I2S1 in component ::Drivers:I2S #define RTE_I2S1 1 #define I2S1_IRQHandler IRQ014_Handler -// I2S1_SCLK Pin <0=>P0_3 <1=>P0_7 <2=>P0 +// I2S1_SCLK Pin <0=>P0_3 <1=>P0_7 <2=>P0_8 /*I2S1 PINS*/ +#ifndef ULP_I2S_SCLK_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_I2S1_SCLK_PORT_ID 0 #else @@ -1310,8 +2056,16 @@ #else #error "Invalid I2S1 RTE_I2S1_SCLK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S1_SCLK_PORT ULP_I2S_SCLK_PORT +#define RTE_I2S1_SCLK_PIN ULP_I2S_SCLK_PIN +#define RTE_I2S1_SCLK_MUX 2 +//Pintool data +#endif // I2S1_WSCLK Pin <0=>P0_2 <1=>P0_4 <2=>P0_10 +#ifndef ULP_I2S_WSCLK_LOC #define RTE_I2S1_WSCLK_PORT_ID 0 #if (RTE_I2S1_WSCLK_PORT_ID == 0) #define RTE_I2S1_WSCLK_PORT 0 @@ -1324,8 +2078,16 @@ #else #error "Invalid I2S1 RTE_I2S1_WSCLK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S1_WSCLK_PORT ULP_I2S_WSCLK_PORT +#define RTE_I2S1_WSCLK_PIN ULP_I2S_WSCLK_PIN +#define RTE_I2S1_WSCLK_MUX 2 +//Pintool data +#endif // I2S1_DOUT0 Pin <0=>P0_1 <1=>P0_5 <2=>P0_11 +#ifndef ULP_I2S_DOUT0_LOC #define RTE_I2S1_DOUT0_PORT_ID 0 #if (RTE_I2S1_DOUT0_PORT_ID == 0) #define RTE_I2S1_DOUT0_PORT 0 @@ -1338,8 +2100,16 @@ #else #error "Invalid I2S1 RTE_I2S1_DOUT0 Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S1_DOUT0_PORT ULP_I2S_DOUT0_PORT +#define RTE_I2S1_DOUT0_PIN ULP_I2S_DOUT0_PIN +#define RTE_I2S1_DOUT0_MUX 2 +//Pintool data +#endif // I2S1_DIN0 Pin <0=>P0_0 <1=>P0_6 <2=>P0_9 <3=>P0_13 +#ifndef ULP_I2S_DIN0_LOC #define RTE_I2S1_DIN0_PORT_ID 1 #if (RTE_I2S1_DIN0_PORT_ID == 0) #define RTE_I2S1_DIN0_PORT 0 @@ -1356,9 +2126,16 @@ #else #error "Invalid I2S1 RTE_I2S1_DIN0 Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S1_DIN0_PORT ULP_I2S_DIN0_PORT +#define RTE_I2S1_DIN0_PIN ULP_I2S_DIN0_PIN +#define RTE_I2S1_DIN0_MUX 2 +//Pintool data +#endif -// FIFO level can have value 1 to 7 -#define I2S1_TX_FIFO_LEVEL (2U) +// FIFO level can have value 0 to 7 +#define I2S1_TX_FIFO_LEVEL (0U) #define I2S1_RX_FIFO_LEVEL (2U) // I2S1_TX_RES <0=>12 @@ -1413,7 +2190,7 @@ #define I2C0_IRQHandler IRQ042_Handler // I2C0_SCL Pin <0=>P0_7 <1=>P0_65 <2=>P0_66 <3=>P0_75 <4=>P0_32 - +#ifndef I2C0_SCL_LOC #define RTE_I2C0_SCL_PORT_ID 1 #if (RTE_I2C0_SCL_PORT_ID == 0) @@ -1443,9 +2220,32 @@ #else #error "Invalid I2C0 RTE_I2C0_SCL Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2C0_SCL_PORT I2C0_SCL_PORT +#if (I2C0_SCL_LOC == 0) +#define RTE_I2C0_SCL_PIN I2C0_SCL_PIN +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 2 +#define RTE_I2C0_SCL_I2C_REN 7 +#endif +#if (I2C0_SCL_LOC == 1) +#define RTE_I2C0_SCL_PIN (I2C0_SCL_PIN + GPIO_MAX_PIN) +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 23 +#define RTE_I2C0_SCL_I2C_REN 1 +#endif +#if (I2C0_SCL_LOC == 2) +#define RTE_I2C0_SCL_PIN (I2C0_SCL_PIN + GPIO_MAX_PIN) +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 33 +#define RTE_I2C0_SCL_I2C_REN 11 +#endif +//Pintool data +#endif // I2C0_SCL Pin <0=>P0_6 <1=>P0_64 <2=>P0_67 <3=>P0_74 <4=>P0_31 - +#ifndef I2C0_SDA_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_I2C0_SDA_PORT_ID 2 #else @@ -1473,6 +2273,29 @@ #else #error "Invalid I2C0 RTE_I2C0_SDA Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2C0_SDA_PORT I2C0_SDA_PORT +#if (I2C0_SDA_LOC == 3) +#define RTE_I2C0_SDA_PIN I2C0_SDA_PIN +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 1 +#define RTE_I2C0_SDA_I2C_REN 6 +#endif +#if (I2C0_SDA_LOC == 4) +#define RTE_I2C0_SDA_PIN (I2C0_SDA_PIN + GPIO_MAX_PIN) +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 22 +#define RTE_I2C0_SDA_I2C_REN 3 +#endif +#if (I2C0_SDA_LOC == 5) +#define RTE_I2C0_SDA_PIN (I2C0_SDA_PIN + GPIO_MAX_PIN) +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 32 +#define RTE_I2C0_SDA_I2C_REN 10 +#endif +//Pintool data +#endif #define IC_SCL_STUCK_TIMEOUT 20 #define IC_SDA_STUCK_TIMEOUT 20 @@ -1482,7 +2305,7 @@ #define DMA_TX_TL 1 #define DMA_RX_TL 1 #endif -// I2C0 [Driver_I2C0] +// I2C1 [Driver_I2C0] // I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1] // Configuration settings for Driver_I2C1 in component ::Drivers:I2C @@ -1490,6 +2313,7 @@ #define RTE_I2C1 1 #define I2C1_IRQHandler IRQ061_Handler // I2C1_SCL Pin <0=>P0_6 <1=>P0_29 <2=>P0_50 <3=>P0_54 <4=>P0_64 <4=>P0_66 <4=>P0_70 <7=>P0_33 +#ifndef I2C1_SCL_LOC #define RTE_I2C1_SCL_PORT_ID 2 #if (RTE_I2C1_SCL_PORT_ID == 0) @@ -1526,14 +2350,55 @@ #define RTE_I2C1_SCL_PORT 0 #define RTE_I2C1_SCL_PIN 70 #define RTE_I2C1_SCL_MUX 5 -#define RTE_I2C1_SCL_PAD 28 +#define RTE_I2C1_SCL_PAD 29 #define RTE_I2C1_SCL_REN 6 #else #error "Invalid I2C1_SCL Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2C1_SCL_PORT I2C1_SCL_PORT +#if (I2C1_SCL_LOC == 0) +#define RTE_I2C1_SCL_PIN I2C1_SCL_PIN +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 1 +#define RTE_I2C1_SCL_REN 6 +#endif +#if (I2C1_SCL_LOC == 1) +#define RTE_I2C1_SCL_PIN I2C1_SCL_PIN +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 0 //no pad +#define RTE_I2C1_SCL_REN 29 +#endif +#if (I2C1_SCL_LOC == 2) +#define RTE_I2C1_SCL_PIN I2C1_SCL_PIN +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 14 +#define RTE_I2C1_SCL_REN 50 +#endif +#if (I2C1_SCL_LOC == 3) +#define RTE_I2C1_SCL_PIN I2C1_SCL_PIN +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 18 +#define RTE_I2C1_SCL_REN 54 +#endif +#if (I2C1_SCL_LOC == 4) +#define RTE_I2C1_SCL_PIN (I2C1_SCL_PIN + GPIO_MAX_PIN) +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 22 +#define RTE_I2C1_SCL_REN 2 +#endif +#if (I2C1_SCL_LOC == 5) +#define RTE_I2C1_SCL_PIN (I2C1_SCL_PIN + GPIO_MAX_PIN) +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 29 +#define RTE_I2C1_SCL_REN 6 +#endif +//Pintool data +#endif // I2C1_SCL Pin <0=>P0_7 <1=>P0_30 <2=>P0_51 <3=>P0_55 <4=>P0_65 <4=>P0_67 <4=>P0_71 <7=>P0_34 - +#ifndef I2C1_SDA_LOC #define RTE_I2C1_SDA_PORT_ID 2 #if (RTE_I2C1_SDA_PORT_ID == 0) @@ -1581,6 +2446,47 @@ #else #error "Invalid I2C1_SDA Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2C1_SDA_PORT I2C1_SDA_PORT +#if (I2C1_SDA_LOC == 6) +#define RTE_I2C1_SDA_PIN I2C1_SDA_PIN +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 2 +#define RTE_I2C1_SDA_REN 7 +#endif +#if (I2C1_SDA_LOC == 7) +#define RTE_I2C1_SDA_PIN I2C1_SDA_PIN +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 0 //no pad +#define RTE_I2C1_SDA_REN 30 +#endif +#if (I2C1_SDA_LOC == 8) +#define RTE_I2C1_SDA_PIN I2C1_SDA_PIN +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 15 +#define RTE_I2C1_SDA_REN 51 +#endif +#if (I2C1_SDA_LOC == 9) +#define RTE_I2C1_SDA_PIN I2C1_SDA_PIN +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 19 +#define RTE_I2C1_SDA_REN 55 +#endif +#if (I2C1_SDA_LOC == 10) +#define RTE_I2C1_SDA_PIN (I2C1_SDA_PIN + GPIO_MAX_PIN) +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 23 +#define RTE_I2C1_SDA_REN 1 +#endif +#if (I2C1_SDA_LOC == 11) +#define RTE_I2C1_SDA_PIN (I2C1_SDA_PIN + GPIO_MAX_PIN) +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 29 +#define RTE_I2C1_SDA_REN 7 +#endif +//Pintool data +#endif #define IC_SCL_STUCK_TIMEOUT 20 #define IC_SDA_STUCK_TIMEOUT 20 @@ -1593,12 +2499,13 @@ // I2C1 [Driver_I2C1] -// I2C2 (Inter-integrated Circuit Interface 2) [Driver_I2C2] +// ULP I2C (Inter-integrated Circuit Interface 2) [Driver_I2C2] // Configuration settings for Driver_I2C2 in component ::Drivers:I2C #define RTE_I2C2 1 #define I2C2_IRQHandler IRQ013_Handler // I2C2_SCL Pin <0=>P0_1 <1=>P0_5 <2=>P0_7 <3=>P0_8 <4=>P0_13 +#ifndef ULP_I2C_SCL_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_I2C2_SCL_PORT_ID 0 #else @@ -1617,8 +2524,25 @@ #else #error "Invalid I2C2_SCL Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2C2_SCL_PORT ULP_I2C_SCL_PORT +#define RTE_I2C2_SCL_PIN ULP_I2C_SCL_PIN +#define RTE_I2C2_SCL_MUX 4 +#if (ULP_I2C_SCL_LOC == 0) +#define RTE_I2C2_SCL_REN 0 +#elif (ULP_I2C_SCL_LOC == 1) +#define RTE_I2C2_SCL_REN 0 +#elif (ULP_I2C_SCL_LOC == 2) +#define RTE_I2C2_SCL_REN 7 +#elif (ULP_I2C_SCL_LOC == 3) +#define RTE_I2C2_SCL_REN 8 +#endif +//Pintool data +#endif // I2C2_SDA Pin <0=>P0_0 <1=>P0_4 <2=>P0_6 <3=>P0_9 <4=>P0_11 <5=>P0_12 +#ifndef ULP_I2C_SDA_LOC #define RTE_I2C2_SDA_PORT_ID 0 #if (RTE_I2C2_SDA_PORT_ID == 0) #define RTE_I2C2_SDA_PORT 0 @@ -1626,10 +2550,10 @@ #define RTE_I2C2_SDA_MUX 4 #define RTE_I2C2_SDA_REN 6 #elif (RTE_I2C2_SDA_PORT_ID == 1) -#define RTE_I2C2_SDA_PORT 0 -#define RTE_I2C2_SDA_PIN 9 -#define RTE_I2C2_SDA_MUX 4 -#define RTE_I2C2_SDA_I2C_REN 9 +#define RTE_I2C2_SDA_PORT 0 +#define RTE_I2C2_SDA_PIN 9 +#define RTE_I2C2_SDA_MUX 4 +#define RTE_I2C2_SDA_REN 9 #elif (RTE_I2C2_SDA_PORT_ID == 2) #define RTE_I2C2_SDA_PORT 0 #define RTE_I2C2_SDA_PIN 11 @@ -1638,6 +2562,24 @@ #else #error "Invalid I2C2_SDA Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2C2_SDA_PORT I2C2_SDA_PORT +#define RTE_I2C2_SDA_PIN I2C2_SDA_PIN +#define RTE_I2C2_SDA_MUX 4 +#if (ULP_I2C_SDA_LOC == 4) +#define RTE_I2C2_SDA_REN 0 +#elif (ULP_I2C_SDA_LOC == 5) +#define RTE_I2C2_SDA_REN 0 +#elif (ULP_I2C_SDA_LOC == 6) +#define RTE_I2C2_SDA_REN 6 +#elif (ULP_I2C_SDA_LOC == 7) +#define RTE_I2C2_SDA_REN 9 +#elif (ULP_I2C_SDA_LOC == 8) +#define RTE_I2C2_SDA_REN 11 +#endif +//Pintool data +#endif #define IC_SCL_STUCK_TIMEOUT 20 #define IC_SDA_STUCK_TIMEOUT 20 @@ -1656,6 +2598,7 @@ // GSPI_MASTER_CLK <0=>P0_8 <1=>P0_25 <2=>P0_46 <3=>P0_52 // CLK of GSPI0 +#ifndef GSPI_MASTER_SCK_LOC #define RTE_GSPI_MASTER_CLK_PORT_ID 1 #if (RTE_GSPI_MASTER_CLK_PORT_ID == 0) @@ -1681,12 +2624,31 @@ #else #error "Invalid GSPI0 RTE_GSPI_MASTER_CLK_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_GSPI_MASTER_CLK_PORT GSPI_MASTER_SCK__PORT +#define RTE_GSPI_MASTER_CLK_PIN GSPI_MASTER_SCK__PIN +#define RTE_GSPI_MASTER_CLK_MUX 4 +#if (GSPI_MASTER_SCK_LOC == 0) +#define RTE_GSPI_MASTER_CLK_PAD 3 +#endif +#if (GSPI_MASTER_SCK_LOC == 1) +#define RTE_GSPI_MASTER_CLK_PAD 0 +#endif +#if (GSPI_MASTER_SCK_LOC == 2) +#define RTE_GSPI_MASTER_CLK_PAD 10 +#endif +#if (GSPI_MASTER_SCK_LOC == 3) +#define RTE_GSPI_MASTER_CLK_PAD 16 +#endif +//Pintool data +#endif // GSPI_MASTER_CS0 // <0=>P0_9 <1=>P0_28 <2=>P0_49 <3=>P0_53 // CS0 of GSPI0 // - +#ifndef GSPI_MASTER_CS0_LOC #define RTE_GSPI_MASTER_CS0_PORT_ID 1 #if (RTE_GSPI_MASTER_CS0_PORT_ID == 0) @@ -1716,11 +2678,32 @@ #else #error "Invalid GSPI0 RTE_GSPI_MASTER_CS0_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_GSPI_MASTER_CS0 1 +#define RTE_GSPI_MASTER_CS0_PORT GSPI_MASTER_CS0__PORT +#define RTE_GSPI_MASTER_CS0_PIN GSPI_MASTER_CS0__PIN +#define RTE_GSPI_MASTER_CS0_MUX 4 +#if (GSPI_MASTER_CS0_LOC == 4) +#define RTE_GSPI_MASTER_CS0_PAD 4 +#endif +#if (GSPI_MASTER_CS0_LOC == 5) +#define RTE_GSPI_MASTER_CS0_PAD 0 +#endif +#if (GSPI_MASTER_CS0_LOC == 6) +#define RTE_GSPI_MASTER_CS0_PAD 13 +#endif +#if (GSPI_MASTER_CS0_LOC == 7) +#define RTE_GSPI_MASTER_CS0_PAD 17 +#endif +//Pintool data +#endif // GSPI_MASTER_CS1 // <0=>P0_10 <1=>P0_29 <2=>P0_50 <3=>P0_54 // CS1 of GSPI0 // +#ifndef GSPI_MASTER_CS1_LOC #define RTE_GSPI_MASTER_CS1_PORT_ID 1 #if (RTE_GSPI_MASTER_CS1_PORT_ID == 0) #define RTE_GSPI_MASTER_CS1 1 @@ -1749,11 +2732,32 @@ #else #error "Invalid GSPI0 RTE_GSPI_MASTER_CS1_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_GSPI_MASTER_CS1 1 +#define RTE_GSPI_MASTER_CS1_PORT GSPI_MASTER_CS1__PORT +#define RTE_GSPI_MASTER_CS1_PIN GSPI_MASTER_CS1__PIN +#define RTE_GSPI_MASTER_CS1_MUX 4 +#if (GSPI_MASTER_CS1_LOC == 8) +#define RTE_GSPI_MASTER_CS1_PAD 5 +#endif +#if (GSPI_MASTER_CS1_LOC == 9) +#define RTE_GSPI_MASTER_CS1_PAD 0 +#endif +#if (GSPI_MASTER_CS1_LOC == 10) +#define RTE_GSPI_MASTER_CS1_PAD 14 +#endif +#if (GSPI_MASTER_CS1_LOC == 11) +#define RTE_GSPI_MASTER_CS1_PAD 18 +#endif +//Pintool data +#endif // GSPI_MASTER_CS2 // <0=>P0_15 <1=>P0_30 <2=>P0_51 <3=>P0_55 // CS2 of GSPI0 // +#ifndef GSPI_MASTER_CS2_LOC #define RTE_GSPI_MASTER_CS2_PORT_ID 1 #if (RTE_GSPI_MASTER_CS2_PORT_ID == 0) #define RTE_GSPI_MASTER_CS2 1 @@ -1782,10 +2786,30 @@ #else #error "Invalid GSPI0 RTE_GSPI_MASTER_CS2_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_GSPI_MASTER_CS2 1 +#define RTE_GSPI_MASTER_CS2_PORT GSPI_MASTER_CS2__PORT +#define RTE_GSPI_MASTER_CS2_PIN GSPI_MASTER_CS2__PIN +#define RTE_GSPI_MASTER_CS2_MUX 4 +#if (GSPI_MASTER_CS2_LOC == 12) +#define RTE_GSPI_MASTER_CS2_PAD 8 +#endif +#if (GSPI_MASTER_CS2_LOC == 13) +#define RTE_GSPI_MASTER_CS2_PAD 0 +#endif +#if (GSPI_MASTER_CS2_LOC == 14) +#define RTE_GSPI_MASTER_CS2_PAD 15 +#endif +#if (GSPI_MASTER_CS2_LOC == 15) +#define RTE_GSPI_MASTER_CS2_PAD 19 +#endif +//Pintool data +#endif // GSPI_MASTER_MOSI <0=>P0_12 <1=>P0_27 <2=>P0_48 <3=>P0_57 <4=>P0_6 // MOSI of GSPI0 - +#ifndef GSPI_MASTER_MOSI_LOC #define RTE_GSPI_MASTER_MOSI_PORT_ID 1 #if (RTE_GSPI_MASTER_MOSI_PORT_ID == 0) @@ -1816,10 +2840,36 @@ #else #error "Invalid GSPI0 RTE_GSPI_MASTER_MOSI_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_GSPI_MASTER_MOSI_PORT GSPI_MASTER_MOSI__PORT +#define RTE_GSPI_MASTER_MOSI_PIN GSPI_MASTER_MOSI__PIN +#if (GSPI_MASTER_MOSI_LOC == 16) +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 1 +#endif +#if (GSPI_MASTER_MOSI_LOC == 17) +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 0 +#endif +#if (GSPI_MASTER_MOSI_LOC == 18) +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 12 +#endif +#if (GSPI_MASTER_MOSI_LOC == 19) +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 21 +#endif +#if (GSPI_MASTER_MOSI_LOC == 20) +#define RTE_GSPI_MASTER_MOSI_MUX 12 +#define RTE_GSPI_MASTER_MOSI_PAD 1 +#endif +//Pintool data +#endif // GSPI_MASTER_MISO <0=>P0_11 <1=>P0_26 <2=>P0_47 <3=>P0_56 // MISO of GSPI0 - +#ifndef GSPI_MASTER_MISO_LOC #define RTE_GSPI_MASTER_MISO_PORT_ID 1 #if (RTE_GSPI_MASTER_MISO_PORT_ID == 0) @@ -1845,6 +2895,25 @@ #else #error "Invalid GSPI0 RTE_GSPI_MASTER_MISO_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_GSPI_MASTER_MISO_PORT GSPI_MASTER_MISO__PORT +#define RTE_GSPI_MASTER_MISO_PIN GSPI_MASTER_MISO__PIN +#define RTE_GSPI_MASTER_MISO_MUX 4 +#if (GSPI_MASTER_MISO_LOC == 21) +#define RTE_GSPI_MASTER_MISO_PAD 6 +#endif +#if (GSPI_MASTER_MISO_LOC == 22) +#define RTE_GSPI_MASTER_MISO_PAD 0 +#endif +#if (GSPI_MASTER_MISO_LOC == 23) +#define RTE_GSPI_MASTER_MISO_PAD 11 +#endif +#if (GSPI_MASTER_MISO_LOC == 24) +#define RTE_GSPI_MASTER_MISO_PAD 20 +#endif +//Pintool data +#endif #if defined(HIGH_THROUGHPUT_EN) && (HIGH_THROUGHPUT_EN == ENABLE) #define RTE_GSPI_MASTER_CHNL_UDMA_TX_EN 1 @@ -1880,6 +2949,7 @@ //SCT_IN_0 <0=>GPIO_25 <1=>GPIO_64 <2=>GPIO_68 +#ifndef SCT_IN0_LOC #define RTE_SCT_IN_0_PORT_ID 0 #if (RTE_SCT_IN_0_PORT_ID == 0) @@ -1890,9 +2960,27 @@ #else #error "Invalid RTE_SCT_IN_0_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SCT_IN_0_PORT SCT_IN0_PORT +#if (SCT_IN0_LOC == 0) +#define RTE_SCT_IN_0_PIN SCT_IN0_PIN +#define RTE_SCT_IN_0_MUX 9 +#define RTE_SCT_IN_0_PAD 0 //no pad +#elif (SCT_IN0_LOC == 1) +#define RTE_SCT_IN_0_PIN (SCT_IN0_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_0_MUX 7 +#define RTE_SCT_IN_0_PAD 22 +#elif (SCT_IN0_LOC == 2) +#define RTE_SCT_IN_0_PIN (SCT_IN0_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_0_MUX 9 +#define RTE_SCT_IN_0_PAD 26 +#endif +//Pintool data +#endif //SCT_IN_1 <0=>GPIO_26 <1=>GPIO_65 <2=>GPIO_69 - +#ifndef SCT_IN1_LOC #define RTE_SCT_IN_1_PORT_ID 1 #if (RTE_SCT_IN_1_PORT_ID == 0) @@ -1908,9 +2996,29 @@ #else #error "Invalid RTE_SCT_IN_1_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SCT_IN_1_PORT SCT_IN1_PORT +#if (SCT_IN1_LOC == 3) +#define RTE_SCT_IN_1_PIN SCT_IN1_PIN +#define RTE_SCT_IN_1_MUX 9 +#define RTE_SCT_IN_1_PAD 0 //no pad +#endif +#if (SCT_IN1_LOC == 4) +#define RTE_SCT_IN_1_PIN (SCT_IN1_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_1_MUX 7 +#define RTE_SCT_IN_1_PAD 23 +#endif +#if (SCT_IN1_LOC == 5) +#define RTE_SCT_IN_1_PIN (SCT_IN1_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_1_MUX 9 +#define RTE_SCT_IN_1_PAD 27 +#endif +//Pintool data +#endif //SCT_IN_2 <0=>GPIO_27 <1=>GPIO_66 <2=>GPIO_70 - +#ifndef SCT_IN2_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SCT_IN_2_PORT_ID 0 #else @@ -1935,9 +3043,24 @@ #else #error "Invalid RTE_SCT_IN_0_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SCT_IN_2_PORT SCT_IN2_PORT +#if (SCT_IN2_LOC == 6) +#define RTE_SCT_IN_2_PIN SCT_IN2_PIN +#define RTE_SCT_IN_2_MUX 9 +#define RTE_SCT_IN_2_PAD 0 //no pad +#endif +#if (SCT_IN2_LOC == 7) +#define RTE_SCT_IN_2_PIN (SCT_IN2_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_2_MUX 9 +#define RTE_SCT_IN_2_PAD 28 +#endif +//Pintool data +#endif //SCT_IN_3 <0=>GPIO_28 <1=>GPIO_67 <2=>GPIO_71 - +#ifndef SCT_IN3_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SCT_IN_3_PORT_ID 0 #else @@ -1962,8 +3085,24 @@ #else #error "Invalid RTE_SCT_IN_0_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SCT_IN_3_PORT SCT_IN3_PORT +#if (SCT_IN3_LOC == 8) +#define RTE_SCT_IN_3_PIN SCT_IN3_PIN +#define RTE_SCT_IN_3_MUX 9 +#define RTE_SCT_IN_3_PAD 0 //no pad +#endif +#if (SCT_IN3_LOC == 9) +#define RTE_SCT_IN_3_PIN (SCT_IN3_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_3_MUX 9 +#define RTE_SCT_IN_3_PAD 29 +#endif +//Pintool data +#endif // SCT_OUT_0 <0=>GPIO_29 <1=>GPIO_68 +#ifndef SCT_OUT0_LOC #define RTE_SCT_OUT_0_PORT_ID 0 #if (RTE_SCT_OUT_0_PORT_ID == 0) #define RTE_SCT_OUT_0_PORT 0 @@ -1973,8 +3112,23 @@ #else #error "Invalid RTE_SCT_OUT_0_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SCT_OUT_0_PORT SCT_OUT0_PORT +#if (SCT_OUT0_LOC == 10) +#define RTE_SCT_OUT_0_PIN SCT_OUT0_PIN +#define RTE_SCT_OUT_0_MUX 9 +#define RTE_SCT_OUT_0_PAD 0 //no pad +#elif (SCT_OUT0_LOC == 11) +#define RTE_SCT_OUT_0_PIN (SCT_OUT0_PIN + GPIO_MAX_PIN) +#define RTE_SCT_OUT_0_MUX 7 +#define RTE_SCT_OUT_0_PAD 26 +#endif +//Pintool data +#endif // SCT_OUT_1 <0=>GPIO_30 <1=>GPIO_69 +#ifndef SCT_OUT1_LOC #define RTE_SCT_OUT_1_PORT_ID 0 #if (RTE_SCT_OUT_1_PORT_ID == 0) #define RTE_SCT_OUT_1_PORT 0 @@ -1984,117 +3138,67 @@ #else #error "Invalid RTE_SCT_OUT_1_PIN Pin Configuration!" #endif - -/// SCT_OUT_2 <0=>GPIO_70 <1=>GPIO_8 -#define RTE_SCT_OUT_2_PORT_ID 0 -#if ((RTE_SCT_OUT_2_PORT_ID == 1)) -#error "Invalid RTE_SCT_OUT_2_PIN pin Configuration!" +#else +//Pintool data +#define RTE_SCT_OUT_1_PORT SCT_OUT1_PORT +#if (SCT_OUT1_LOC == 12) +#define RTE_SCT_OUT_1_PIN SCT_OUT1_PIN +#define RTE_SCT_OUT_1_MUX 9 +#define RTE_SCT_OUT_1_PAD 0 //no pad +#elif (SCT_OUT1_LOC == 13) +#define RTE_SCT_OUT_1_PIN (SCT_OUT1_PIN + GPIO_MAX_PIN) +#define RTE_SCT_OUT_1_MUX 7 +#define RTE_SCT_OUT_1_PAD 27 +#endif +//Pintool data #endif -#if (RTE_SCT_OUT_2_PORT_ID == 0) -#define RTE_SCT_OUT_2_PORT 0 -#define RTE_SCT_OUT_2_PIN 70 +//Pintool data +#define RTE_SCT_OUT_2_PORT SCT_OUT2_PORT +#define RTE_SCT_OUT_2_PIN SCT_OUT2_PIN #define RTE_SCT_OUT_2_MUX 7 #define RTE_SCT_OUT_2_PAD 28 -#elif (RTE_SCT_OUT_2_PORT_ID == 1) -#define RTE_SCT_OUT_2_PORT 0 -#define RTE_SCT_OUT_2_PIN 8 -#define RTE_SCT_OUT_2_MUX 12 -#define RTE_SCT_OUT_2_PAD 3 -#else -#error "Invalid RTE_SCT_OUT_2_PIN Pin Configuration!" -#endif -/**/ -//SCT_OUT_3 <0=>GPIO_71 <1=>GPIO_9 -#define RTE_SCT_OUT_3_PORT_ID 0 -#if ((RTE_SCT_OUT_3_PORT_ID == 1)) -#error "Invalid RTE_SCT_OUT_3_PIN pin Configuration!" -#endif +//Pintool data -#if (RTE_SCT_OUT_3_PORT_ID == 0) -#define RTE_SCT_OUT_3_PORT 0 -#define RTE_SCT_OUT_3_PIN 71 +//Pintool data +#define RTE_SCT_OUT_3_PORT SCT_OUT3_PORT +#define RTE_SCT_OUT_3_PIN SCT_OUT3_PIN #define RTE_SCT_OUT_3_MUX 7 #define RTE_SCT_OUT_3_PAD 29 -#elif (RTE_SCT_OUT_3_PORT_ID == 1) -#define RTE_SCT_OUT_3_PORT 0 -#define RTE_SCT_OUT_3_PIN 9 -#define RTE_SCT_OUT_3_MUX 12 -#define RTE_SCT_OUT_3_PAD 4 -#else -#error "Invalid RTE_SCT_OUT_3_PIN Pin Configuration!" -#endif +//Pintool data -//SCT_OUT_4 <0=>GPIO_72 <1=>GPIO_68 - -#define RTE_SCT_OUT_4_PORT_ID 0 -#if ((RTE_SCT_OUT_4_PORT_ID == 1)) -#error "Invalid RTE_SCT_OUT_4_PIN pin Configuration!" -#endif - -#if (RTE_SCT_OUT_4_PORT_ID == 0) -/**/ -#define RTE_SCT_OUT_4_PORT 0 -#define RTE_SCT_OUT_4_PIN 72 +//Pintool data +#define RTE_SCT_OUT_4_PORT SCT_OUT4_PORT +#define RTE_SCT_OUT_4_PIN SCT_OUT4_PIN #define RTE_SCT_OUT_4_MUX 7 #define RTE_SCT_OUT_4_PAD 30 -#else -#error "Invalid RTE_SCT_OUT_4_PIN Pin Configuration!" -#endif -//SCT_OUT_5 <0=>GPIO_73 <1=>GPIO_69 - -#define RTE_SCT_OUT_5_PORT_ID 0 -#if ((RTE_SCT_OUT_5_PORT_ID == 1)) -#error "Invalid RTE_SCT_OUT_5_PIN pin Configuration!" -#endif +//Pintool data -#if (RTE_SCT_OUT_5_PORT_ID == 0) -#define RTE_SCT_OUT_5_PORT 2 -#define RTE_SCT_OUT_5_PIN 73 +//Pintool data +#define RTE_SCT_OUT_5_PORT SCT_OUT5_PORT +#define RTE_SCT_OUT_5_PIN SCT_OUT5_PIN #define RTE_SCT_OUT_5_MUX 7 #define RTE_SCT_OUT_5_PAD 31 -#else -#error "Invalid RTE_SCT_OUT_5_PIN Pin Configuration!" -#endif - -//SCT_OUT_6 <0=>GPIO_74 <1=>GPIO_70 +//Pintool data -#define RTE_SCT_OUT_6_PORT_ID 0 -#if ((RTE_SCT_OUT_6_PORT_ID == 1)) -#error "Invalid RTE_SCT_OUT_6_PIN pin Configuration!" -#endif - -#if (RTE_SCT_OUT_6_PORT_ID == 0) -#define RTE_SCT_OUT_6_PORT 0 -#define RTE_SCT_OUT_6_PIN 74 +//Pintool data +#define RTE_SCT_OUT_6_PORT SCT_OUT6_PORT +#define RTE_SCT_OUT_6_PIN SCT_OUT6_PIN #define RTE_SCT_OUT_6_MUX 7 #define RTE_SCT_OUT_6_PAD 32 -#elif (RTE_SCT_OUT_6_PORT_ID == 1) -#define RTE_SCT_OUT_6_PORT 0 -#define RTE_SCT_OUT_6_PIN 70 -#define RTE_SCT_OUT_6_MUX 13 -#define RTE_SCT_OUT_6_PAD 28 -#else -#error "Invalid RTE_SCT_OUT_6_PIN Pin Configuration!" -#endif - -// SCT_OUT_7 <0=>GPIO_75 <1=>GPIO_71 +//Pintool data -#define RTE_SCT_OUT_7_PORT_ID 0 - -#if (RTE_SCT_OUT_7_PORT_ID == 0) -#define RTE_SCT_OUT_7_PORT 0 -#define RTE_SCT_OUT_7_PIN 75 +//Pintool data +#define RTE_SCT_OUT_7_PORT SCT_OUT7_PORT +#define RTE_SCT_OUT_7_PIN SCT_OUT7_PIN #define RTE_SCT_OUT_7_MUX 7 #define RTE_SCT_OUT_7_PAD 33 -#else -#error "Invalid RTE_SCT_OUT_7_PIN Pin Configuration!" -#endif +//Pintool data // SIO // //<> Serial Input Output //SIO_0 <0=>GPIO_6 <1=>GPIO_25 <2=>GPIO_64 <3=>GPIO_72 - +#ifndef SIO_0_LOC #define RTE_SIO_0_PORT_ID 0 #if (RTE_SIO_0_PORT_ID == 0) @@ -2115,9 +3219,31 @@ #else #error "Invalid RTE_SIO_0_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_0_PORT SIO_SIO0_PORT +#define RTE_SIO_0_MUX 1 +#if (SIO_0_LOC == 0) +#define RTE_SIO_0_PIN SIO_SIO0_PIN +#define RTE_SIO_0_PAD 1 +#endif +#if (SIO_0_LOC == 1) +#define RTE_SIO_0_PIN SIO_SIO0_PIN +#define RTE_SIO_0_PAD 0 +#endif +#if (SIO_0_LOC == 2) +#define RTE_SIO_0_PIN (SIO_SIO0_PIN + GPIO_MAX_PIN) +#define RTE_SIO_0_PAD 22 +#endif +#if (SIO_0_LOC == 3) +#define RTE_SIO_0_PIN (SIO_SIO0_PIN + GPIO_MAX_PIN) +#define RTE_SIO_0_PAD 30 +#endif +//Pintool data +#endif //SIO_1 <0=>GPIO_7 <1=>GPIO_26 <2=>GPIO_65 <3=>GPIO_73 - +#ifndef SIO_1_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SIO_1_PORT_ID 1 #else @@ -2147,9 +3273,31 @@ #else #error "Invalid RTE_SIO_1_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_1_PORT SIO_SIO1_PORT +#define RTE_SIO_1_MUX 1 +#if (SIO_1_LOC == 4) +#define RTE_SIO_1_PIN SIO_SIO1_PIN +#define RTE_SIO_1_PAD 2 +#endif +#if (SIO_1_LOC == 5) +#define RTE_SIO_1_PIN SIO_SIO1_PIN +#define RTE_SIO_1_PAD 0 +#endif +#if (SIO_1_LOC == 6) +#define RTE_SIO_1_PIN (SIO_SIO1_PIN + GPIO_MAX_PIN) +#define RTE_SIO_1_PAD 23 +#endif +#if (SIO_1_LOC == 7) +#define RTE_SIO_1_PIN (SIO_SIO1_PIN + GPIO_MAX_PIN) +#define RTE_SIO_1_PAD 31 +#endif +//Pintool data +#endif // SIO_2 <0=>GPIO_8 <1=>GPIO_27 <2=>GPIO_66 <3=>GPIO_74 - +#ifndef SIO_2_LOC #define RTE_SIO_2_PORT_ID 1 #if (RTE_SIO_2_PORT_ID == 0) @@ -2175,9 +3323,27 @@ #else #error "Invalid RTE_SIO_2_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_2_PORT SIO_SIO2_PORT +#define RTE_SIO_2_MUX 1 +#if (SIO_2_LOC == 8) +#define RTE_SIO_2_PIN SIO_SIO2_PIN +#define RTE_SIO_2_PAD 3 +#endif +#if (SIO_2_LOC == 9) +#define RTE_SIO_2_PIN SIO_SIO2_PIN +#define RTE_SIO_2_PAD 0 +#endif +#if (SIO_2_LOC == 10) +#define RTE_SIO_2_PIN (SIO_SIO2_PIN + GPIO_MAX_PIN) +#define RTE_SIO_2_PAD 32 +#endif +//Pintool data +#endif //SIO_3 <0=>GPIO_9 <1=>GPIO_28 <2=>GPIO_67 <3=>GPIO_75 - +#ifndef SIO_3_LOC #define RTE_SIO_3_PORT_ID 1 #if (RTE_SIO_3_PORT_ID == 0) @@ -2203,8 +3369,27 @@ #else #error "Invalid RTE_SIO_3_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_3_PORT SIO_SIO3_PORT +#define RTE_SIO_3_MUX 1 +#if (SIO_3_LOC == 11) +#define RTE_SIO_3_PIN SIO_SIO3_PIN +#define RTE_SIO_3_PAD 4 +#endif +#if (SIO_3_LOC == 12) +#define RTE_SIO_3_PIN SIO_SIO3_PIN +#define RTE_SIO_3_PAD 0 +#endif +#if (SIO_3_LOC == 13) +#define RTE_SIO_3_PIN (SIO_SIO3_PIN + GPIO_MAX_PIN) +#define RTE_SIO_3_PAD 33 +#endif +//Pintool data +#endif //SIO_4 <0=>GPIO_10 <1=>GPIO_29 <2=>GPIO_68 +#ifndef SIO_4_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SIO_4_PORT_ID 1 #else @@ -2223,8 +3408,27 @@ #else #error "Invalid RTE_SIO_3_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_4_PORT SIO_SIO4_PORT +#define RTE_SIO_4_MUX 1 +#if (SIO_4_LOC == 14) +#define RTE_SIO_4_PAD 5 +#define RTE_SIO_4_PIN SIO_SIO4_PIN +#endif +#if (SIO_4_LOC == 15) +#define RTE_SIO_4_PAD 0 +#define RTE_SIO_4_PIN SIO_SIO4_PIN +#endif +#if (SIO_4_LOC == 16) +#define RTE_SIO_4_PAD 26 +#define RTE_SIO_4_PIN (SIO_SIO4_PIN + GPIO_MAX_PIN) +#endif +//Pintool data +#endif // SIO_5 <0=>GPIO_11 <1=>GPIO_30 <2=>GPIO_69 +#ifndef SIO_5_LOC #define RTE_SIO_5_PORT_ID 0 #if (RTE_SIO_5_PORT_ID == 0) #define RTE_SIO_5_PORT 0 @@ -2239,15 +3443,38 @@ #else #error "Invalid RTE_SIO_5_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_5_PORT SIO_SIO5_PORT +#define RTE_SIO_5_MUX 1 +#if (SIO_5_LOC == 17) +#define RTE_SIO_5_PAD 6 +#define RTE_SIO_5_PIN SIO_SIO5_PIN +#endif +#if (SIO_5_LOC == 18) +#define RTE_SIO_5_PAD 0 +#define RTE_SIO_5_PIN SIO_SIO5_PIN +#endif +#if (SIO_5_LOC == 19) +#define RTE_SIO_5_PAD 0 +#define RTE_SIO_5_PIN (SIO_SIO5_PIN + GPIO_MAX_PIN) +#endif +//Pintool data +#endif // SIO_6 GPIO_70 +#ifndef SIO_6_LOC #define RTE_SIO_6_PORT 0 #define RTE_SIO_6_PIN 70 -#define RTE_SIO_6_MUX 1 -#define RTE_SIO_6_PAD 28 +#else +#define RTE_SIO_6_PORT SIO_SIO6_PORT +#define RTE_SIO_6_PIN (SIO_SIO6_PIN + GPIO_MAX_PIN) +#endif +#define RTE_SIO_6_MUX 1 +#define RTE_SIO_6_PAD 28 // SIO_7 <0=>GPIO_15 <1=>GPIO_71 - +#ifndef SIO_7_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SIO_7_PORT_ID 1 #else @@ -2267,10 +3494,24 @@ #else #error "Invalid RTE_SIO_7_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_7_PORT SIO_SIO7_PORT +#define RTE_SIO_7_MUX 1 +#if (SIO_7_LOC == 21) +#define RTE_SIO_7_PIN SIO_SIO7_PIN +#define RTE_SIO_7_PAD 8 +#endif +#if (SIO_7_LOC == 22) +#define RTE_SIO_7_PIN (SIO_SIO7_PIN + GPIO_MAX_PIN) +#define RTE_SIO_7_PAD 29 +#endif +//Pintool data +#endif //<> Pulse Width Modulation //PWM_1H <0=>GPIO_7 <1=>GPIO_64 <2=>GPIO_65 - +#ifndef PWM_1H_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_PWM_1H_PORT_ID 0 #else @@ -2286,13 +3527,28 @@ #define RTE_PWM_1H_PORT 0 #define RTE_PWM_1H_PIN 65 #define RTE_PWM_1H_MUX 8 -#define RTE_PWM_1H_PAD 23 +#define RTE_PWM_1H_PAD 22 #else #error "Invalid RTE_PWM_1H_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_1H_PORT PWM_1H_PORT +#if (PWM_1H_LOC == 0) +#define RTE_PWM_1H_PIN PWM_1H_PIN +#define RTE_PWM_1H_MUX 10 +#define RTE_PWM_1H_PAD 2 +#endif +#if (PWM_1H_LOC == 1) +#define RTE_PWM_1H_PIN (PWM_1H_PIN + GPIO_MAX_PIN) +#define RTE_PWM_1H_MUX 8 +#define RTE_PWM_1H_PAD 22 +#endif +//Pintool data +#endif // PWM_1L <0=>GPIO_6 <1=>GPIO_64 <2=>GPIO_64 - +#ifndef PWM_1L_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_PWM_1L_PORT_ID 0 #else @@ -2307,9 +3563,23 @@ #else #error "Invalid RTE_PWM_1L_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_1L_PORT PWM_1L_PORT +#if (PWM_1L_LOC == 2) +#define RTE_PWM_1L_PIN PWM_1L_PIN +#define RTE_PWM_1L_MUX 10 +#define RTE_PWM_1L_PAD 1 +#elif (PWM_1L_LOC == 3) +#define RTE_PWM_1L_PIN (PWM_1L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_1L_MUX 8 +#define RTE_PWM_1L_PAD 22 +#endif +//Pintool data +#endif //PWM_2H <0=>GPIO_9 <1=>GPIO_67 <2=>GPIO_69 - +#ifndef PWM_2H_LOC #define RTE_PWM_2H_PORT_ID 0 #if ((RTE_PWM_2H_PORT_ID == 2)) #error "Invalid RTE_PWM_2H_PIN pin Configuration!" @@ -2328,9 +3598,24 @@ #else #error "Invalid RTE_PWM_2H_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_2H_PORT PWM_2H_PORT +#if (PWM_2H_LOC == 4) +#define RTE_PWM_2H_PIN PWM_2H_PIN +#define RTE_PWM_2H_MUX 10 +#define RTE_PWM_2H_PAD 4 +#endif +#if (PWM_2H_LOC == 5) +#define RTE_PWM_2H_PIN (PWM_2H_PIN + GPIO_MAX_PIN) +#define RTE_PWM_2H_MUX 12 +#define RTE_PWM_2H_PAD 27 +#endif +//Pintool data +#endif // PWM_2L <0=>GPIO_8 <1=>GPIO_66 <2=>GPIO_68 - +#ifndef PWM_2L_LOC #define RTE_PWM_2L_PORT_ID 0 #if ((RTE_PWM_2L_PORT_ID == 2)) #error "Invalid RTE_PWM_2L_PIN pin Configuration!" @@ -2349,8 +3634,29 @@ #else #error "Invalid RTE_PWM_2L_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_2L_PORT PWM_2L_PORT +#if (PWM_2L_LOC == 6) +#define RTE_PWM_2L_PIN PWM_2L_PIN +#define RTE_PWM_2L_MUX 10 +#define RTE_PWM_2L_PAD 3 +#endif +#if (PWM_2L_LOC == 7) +#define RTE_PWM_2L_PIN (PWM_2L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_2L_MUX 8 +#define RTE_PWM_2L_PAD 24 +#endif +#if (PWM_2L_LOC == 8) +#define RTE_PWM_2L_PIN (PWM_2L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_2L_MUX 12 +#define RTE_PWM_2L_PAD 26 +#endif +//Pintool data +#endif // PWM_3H <0=>GPIO_11 <1=>GPIO_69 +#ifndef PWM_3H_LOC #define RTE_PWM_3H_PORT_ID 0 #if (RTE_PWM_3H_PORT_ID == 0) #define RTE_PWM_3H_PORT 0 @@ -2360,8 +3666,23 @@ #else #error "Invalid RTE_PWM_3H_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_3H_PORT PWM_3H_PORT +#if (PWM_3H_LOC == 9) +#define RTE_PWM_3H_PIN PWM_3H_PIN +#define RTE_PWM_3H_MUX 10 +#define RTE_PWM_3H_PAD 6 +#elif (PWM_3H_LOC == 10) +#define RTE_PWM_3H_PIN (PWM_3H_PIN + GPIO_MAX_PIN) +#define RTE_PWM_3H_MUX 8 +#define RTE_PWM_3H_PAD 27 +#endif +//Pintool data +#endif // PWM_3L <0=>GPIO_10 <1=>GPIO_68 +#ifndef PWM_3L_LOC #define RTE_PWM_3L_PORT_ID 0 #if (RTE_PWM_3L_PORT_ID == 0) @@ -2372,9 +3693,23 @@ #else #error "Invalid RTE_PWM_3L_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_3L_PORT PWM_3L_PORT +#if (PWM_3L_LOC == 11) +#define RTE_PWM_3L_PIN PWM_3L_PIN +#define RTE_PWM_3L_MUX 10 +#define RTE_PWM_3L_PAD 5 +#elif (PWM_3L_LOC == 12) +#define RTE_PWM_3L_PIN (PWM_3L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_3L_MUX 8 +#define RTE_PWM_3L_PAD 26 +#endif +//Pintool data +#endif // PWM_4H <0=>GPIO_15 <1=>GPIO_71 - +#ifndef PWM_4H_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_PWM_4H_PORT_ID 1 #else @@ -2394,9 +3729,17 @@ #else #error "Invalid RTE_PWM_4H_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_4H_PORT PWM_4H_PORT +#define RTE_PWM_4H_PIN (PWM_4H_PIN + GPIO_MAX_PIN) +#define RTE_PWM_4H_MUX 8 +#define RTE_PWM_4H_PAD 29 +//Pintool data +#endif // PWM_4H <0=>GPIO_12 <1=>GPIO_70 - +#ifndef PWM_4L_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_PWM_4L_PORT_ID 1 #else @@ -2416,8 +3759,24 @@ #else #error "Invalid RTE_PWM_4L_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_4L_PORT PWM_4L_PORT +#if (PWM_4L_LOC == 14) +#define RTE_PWM_4L_PIN PWM_4L_PIN +#define RTE_PWM_4L_MUX 10 +#define RTE_PWM_4L_PAD 7 +#endif +#if (PWM_4L_LOC == 15) +#define RTE_PWM_4L_PIN (PWM_4L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_4L_MUX 8 +#define RTE_PWM_4L_PAD 28 +#endif +//Pintool data +#endif // PWM_FAULTA <0=>GPIO_25 <1=>GPIO_68 <1=>GPIO_73 +#ifndef PWM_FAULTA_LOC #define RTE_PWM_FAULTA_PORT_ID 0 #if (RTE_PWM_FAULTA_PORT_ID == 0) @@ -2433,8 +3792,29 @@ #else #error "Invalid RTE_PWM_FAULTA_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_FAULTA_PORT PWM_FAULTA_PORT +#if (PWM_FAULTA_LOC == 16) +#define RTE_PWM_FAULTA_PIN PWM_FAULTA_PIN +#define RTE_PWM_FAULTA_MUX 10 +#define RTE_PWM_FAULTA_PAD 0 //no pad +#endif +#if (PWM_FAULTA_LOC == 17) +#define RTE_PWM_FAULTA_PIN (PWM_FAULTA_PIN + GPIO_MAX_PIN) +#define RTE_PWM_FAULTA_MUX 10 +#define RTE_PWM_FAULTA_PAD 26 +#endif +#if (PWM_FAULTA_LOC == 18) +#define RTE_PWM_FAULTA_PIN (PWM_FAULTA_PIN + GPIO_MAX_PIN) +#define RTE_PWM_FAULTA_MUX 8 +#define RTE_PWM_FAULTA_PAD 31 +#endif +//Pintool data +#endif // PWM_FAULTB <0=>GPIO_26 <1=>GPIO_69 <1=>GPIO_74 +#ifndef PWM_FAULTB_LOC #define RTE_PWM_FAULTB_PORT_ID 0 #if (RTE_PWM_FAULTB_PORT_ID == 0) @@ -2450,13 +3830,42 @@ #else #error "Invalid RTE_PWM_FAULTB_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_FAULTB_PORT PWM_FAULTB_PORT +#if (PWM_FAULTB_LOC == 19) +#define RTE_PWM_FAULTB_PIN PWM_FAULTB_PIN +#define RTE_PWM_FAULTB_MUX 10 +#define RTE_PWM_FAULTB_PAD 0 //no pad +#endif +#if (PWM_FAULTB_LOC == 20) +#define RTE_PWM_FAULTB_PIN (PWM_FAULTB_PIN + GPIO_MAX_PIN) +#define RTE_PWM_FAULTB_MUX 10 +#define RTE_PWM_FAULTB_PAD 27 +#endif +#if (PWM_FAULTB_LOC == 21) +#define RTE_PWM_FAULTB_PIN (PWM_FAULTB_PIN + GPIO_MAX_PIN) +#define RTE_PWM_FAULTB_MUX 8 +#define RTE_PWM_FAULTB_PAD 32 +#endif +//Pintool data +#endif + //PWM_SLP_EVENT_TRIG GPIO_72 +#ifndef PWM_EVTTRIG_LOC #define RTE_PWM_SLP_EVENT_TRIG_PORT 0 #define RTE_PWM_SLP_EVENT_TRIG_PIN 72 -#define RTE_PWM_SLP_EVENT_TRIG_MUX 8 -#define RTE_PWM_SLP_EVENT_TRIG_PAD 30 +#else +//Pintool data +#define RTE_PWM_SLP_EVENT_TRIG_PORT PWM_SLEEP_EVT_TRIG_PORT +#define RTE_PWM_SLP_EVENT_TRIG_PIN (PWM_SLEEP_EVT_TRIG_PIN + GPIO_MAX_PIN) +//Pintool data +#endif +#define RTE_PWM_SLP_EVENT_TRIG_MUX 8 +#define RTE_PWM_SLP_EVENT_TRIG_PAD 30 //PWM_TMR_EXT_TRIG_1 <0=>GPIO_27 <1=>GPIO_51 <2=>GPIO_70 <3=>GPIO_75 +#ifndef PWM_EXTTRIG1_LOC #define RTE_PWM_TMR_EXT_TRIG_1_PORT_ID 0 #if (RTE_PWM_TMR_EXT_TRIG_1_PORT_ID == 0) @@ -2482,8 +3891,34 @@ #else #error "Invalid RTE_PWM_TMR_EXT_TRIG_1_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_TMR_EXT_TRIG_1_PORT PWM_TMR_EXT_TRIG_1_PORT +#if (PWM_EXTTRIG1_LOC == 22) +#define RTE_PWM_TMR_EXT_TRIG_1_PIN PWM_TMR_EXT_TRIG_1_PIN +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 0 //no pad +#endif +#if (PWM_EXTTRIG1_LOC == 23) +#define RTE_PWM_TMR_EXT_TRIG_1_PIN PWM_TMR_EXT_TRIG_1_PIN +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 15 +#endif +#if (PWM_EXTTRIG1_LOC == 24) +#define RTE_PWM_TMR_EXT_TRIG_1_PIN (PWM_TMR_EXT_TRIG_1_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 28 +#endif +#if (PWM_EXTTRIG1_LOC == 25) +#define RTE_PWM_TMR_EXT_TRIG_1_PIN (PWM_TMR_EXT_TRIG_1_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 33 +#endif +//Pintool data +#endif //PWM_TMR_EXT_TRIG_2 <0=>GPIO_28 <1=>GPIO_54 <2=>GPIO_71 +#ifndef PWM_EXTTRIG2_LOC #define RTE_PWM_TMR_EXT_TRIG_2_PORT_ID 0 #if (RTE_PWM_TMR_EXT_TRIG_2_PORT_ID == 0) @@ -2504,6 +3939,71 @@ #else #error "Invalid RTE_PWM_TMR_EXT_TRIG_2_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_TMR_EXT_TRIG_2_PORT PWM_TMR_EXT_TRIG_2_PORT +#if (PWM_EXTTRIG2_LOC == 26) +#define RTE_PWM_TMR_EXT_TRIG_2_PIN PWM_TMR_EXT_TRIG_2_PIN +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 0 //no pad +#endif +#if (PWM_EXTTRIG2_LOC == 27) +#define RTE_PWM_TMR_EXT_TRIG_2_PIN PWM_TMR_EXT_TRIG_2_PIN +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 18 +#endif +#if (PWM_EXTTRIG2_LOC == 28) //Combination not available in pin mux +#define RTE_PWM_TMR_EXT_TRIG_2_PIN (PWM_TMR_EXT_TRIG_2_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 29 +#endif +#if (PWM_EXTTRIG2_LOC == 29) +#define RTE_PWM_TMR_EXT_TRIG_2_PIN (PWM_TMR_EXT_TRIG_2_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 29 +#endif +//Pintool data +#endif + +//PWM_TMR_EXT_TRIG_3 +//Pintool data +#define RTE_PWM_TMR_EXT_TRIG_3_PORT PWM_TMR_EXT_TRIG_3_PORT +#if (PWM_EXTTRIG3_LOC == 30) +#define RTE_PWM_TMR_EXT_TRIG_3_PIN PWM_TMR_EXT_TRIG_3_PIN +#define RTE_PWM_TMR_EXT_TRIG_3_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_3_PAD 0 //no pad +#endif +#if (PWM_EXTTRIG3_LOC == 31) +#define RTE_PWM_TMR_EXT_TRIG_3_PIN PWM_TMR_EXT_TRIG_3_PIN +#define RTE_PWM_TMR_EXT_TRIG_3_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_3_PAD 19 +#endif +#if (PWM_EXTTRIG3_LOC == 32) +#define RTE_PWM_TMR_EXT_TRIG_3_PIN (PWM_TMR_EXT_TRIG_3_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_3_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_3_PAD 30 +#endif +//Pintool data + +//PWM_TMR_EXT_TRIG_4 +//Pintool data +#define RTE_PWM_TMR_EXT_TRIG_4_PORT PWM_TMR_EXT_TRIG_4_PORT +#if (PWM_EXTTRIG4_LOC == 33) +#define RTE_PWM_TMR_EXT_TRIG_4_PIN PWM_TMR_EXT_TRIG_4_PIN +#define RTE_PWM_TMR_EXT_TRIG_4_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_4_PAD 0 //no pad +#endif +#if (PWM_EXTTRIG4_LOC == 34) +#define RTE_PWM_TMR_EXT_TRIG_4_PIN PWM_TMR_EXT_TRIG_4_PIN +#define RTE_PWM_TMR_EXT_TRIG_4_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_4_PAD 14 +#endif +#if (PWM_EXTTRIG4_LOC == 35) +#define RTE_PWM_TMR_EXT_TRIG_4_PIN (PWM_TMR_EXT_TRIG_4_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_4_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_4_PAD 31 +#endif +//Pintool data //<> QEI (Quadrature Encode Interface) @@ -2538,9 +4038,9 @@ #define RTE_QEI_DIR_PAD 29 #elif (RTE_QEI_DIR_PORT_ID == 5) #define RTE_QEI_DIR_PORT 0 -#define RTE_QEI_DIR_PIN 75 +#define RTE_QEI_DIR_PIN 73 #define RTE_QEI_DIR_MUX 3 -#define RTE_QEI_DIR_PAD 33 +#define RTE_QEI_DIR_PAD 31 #else #error "Invalid RTE_QEI_DIR_PIN Pin Configuration!" #endif @@ -2654,6 +4154,339 @@ #endif +//ADC START + +#ifndef ADC_P0_LOC +#define RTE_ADC_P0_PORT 0 +#define RTE_ADC_P0_PIN 0 +#else +#define RTE_ADC_P0_PORT ADC_P0_PORT +#define RTE_ADC_P0_PIN ADC_P0_PIN +#endif +#define RTE_ADC_P0_MUX 1 + +#ifndef ADC_N0_LOC +#define RTE_ADC_N0_PORT 0 +#define RTE_ADC_N0_PIN 1 +#else +#define RTE_ADC_N0_PORT ADC_N0_PORT +#define RTE_ADC_N0_PIN ADC_N0_PIN +#endif +#define RTE_ADC_N0_MUX 1 + +#ifndef ADC_P1_LOC +#define RTE_ADC_P1_PORT 0 +#define RTE_ADC_P1_PIN 2 +#else +#define RTE_ADC_P1_PORT ADC_P1_PORT +#define RTE_ADC_P1_PIN ADC_P1_PIN +#endif +#define RTE_ADC_P1_MUX 1 + +#ifndef ADC_N1_LOC +#define RTE_ADC_N1_PORT 0 +#define RTE_ADC_N1_PIN 3 +#else +#define RTE_ADC_N1_PORT ADC_N1_PORT +#define RTE_ADC_N1_PIN ADC_N1_PIN +#endif +#define RTE_ADC_N1_MUX 1 + +#ifndef ADC_P2_LOC +#define RTE_ADC_P2_PORT 0 +#define RTE_ADC_P2_PIN 4 +#else +#define RTE_ADC_P2_PORT ADC_P2_PORT +#define RTE_ADC_P2_PIN ADC_P2_PIN +#endif +#define RTE_ADC_P2_MUX 1 + +#ifndef ADC_N2_LOC +#define RTE_ADC_N2_PORT 0 +#define RTE_ADC_N2_PIN 5 +#else +#define RTE_ADC_N2_PORT ADC_N2_PORT +#define RTE_ADC_N2_PIN ADC_N2_PIN +#endif +#define RTE_ADC_N2_MUX 1 + +#ifndef ADC_P3_LOC +#define RTE_ADC_P3_PORT 0 +#define RTE_ADC_P3_PIN 6 +#else +#define RTE_ADC_P3_PORT ADC_P3_PORT +#define RTE_ADC_P3_PIN ADC_P3_PIN +#endif +#define RTE_ADC_P3_MUX 1 + +#ifndef ADC_N3_LOC +#define RTE_ADC_N3_PORT 0 +#define RTE_ADC_N3_PIN 11 +#else +#define RTE_ADC_N3_PORT ADC_N3_PORT +#define RTE_ADC_N3_PIN ADC_N3_PIN +#endif +#define RTE_ADC_N3_MUX 1 + +#ifndef ADC_P4_LOC +#define RTE_ADC_P4_PORT 0 +#define RTE_ADC_P4_PIN 8 +#else +#define RTE_ADC_P4_PORT ADC_P4_PORT +#define RTE_ADC_P4_PIN ADC_P4_PIN +#endif +#define RTE_ADC_P4_MUX 1 + +#ifndef ADC_N4_LOC +#define RTE_ADC_N4_PORT 0 +#define RTE_ADC_N4_PIN 9 +#else +#define RTE_ADC_N4_PORT ADC_N4_PORT +#define RTE_ADC_N4_PIN ADC_N4_PIN +#endif +#define RTE_ADC_N4_MUX 1 + +#ifndef ADC_P5_LOC +#define RTE_ADC_P5_PORT 0 +#define RTE_ADC_P5_PIN 10 +#else +#define RTE_ADC_P5_PORT ADC_P5_PORT +#define RTE_ADC_P5_PIN ADC_P5_PIN +#endif +#define RTE_ADC_P5_MUX 1 + +#ifndef ADC_N5_LOC +#define RTE_ADC_N5_PORT 0 +#define RTE_ADC_N5_PIN 7 +#else +#define RTE_ADC_N5_PORT ADC_N5_PORT +#define RTE_ADC_N5_PIN ADC_N5_PIN +#endif +#define RTE_ADC_N5_MUX 1 + +#ifndef ADC_P6_LOC +#define RTE_ADC_P6_PORT 0 +#define RTE_ADC_P6_PIN 25 +#else +#define RTE_ADC_P6_PORT ADC_P6_PORT +#define RTE_ADC_P6_PIN ADC_P6_PIN +#endif +#define RTE_ADC_P6_MUX 1 +#define RTE_ADC_P6_PAD 0 + +#ifndef ADC_N6_LOC +#define RTE_ADC_N6_PORT 0 +#define RTE_ADC_N6_PIN 26 +#else +#define RTE_ADC_N6_PORT ADC_N6_PORT +#define RTE_ADC_N6_PIN ADC_N6_PIN +#endif +#define RTE_ADC_N6_MUX 1 +#define RTE_ADC_N6_PAD 0 + +#ifndef ADC_P7_LOC +#define RTE_ADC_P7_PORT 0 +#define RTE_ADC_P7_PIN 27 +#else +#define RTE_ADC_P7_PORT ADC_P7_PORT +#define RTE_ADC_P7_PIN ADC_P7_PIN +#endif +#define RTE_ADC_P7_MUX 1 +#define RTE_ADC_P7_PAD 0 + +#ifndef ADC_N7_LOC +#define RTE_ADC_N7_PORT 0 +#define RTE_ADC_N7_PIN 28 +#else +#define RTE_ADC_N7_PORT ADC_N7_PORT +#define RTE_ADC_N7_PIN ADC_N7_PIN +#endif +#define RTE_ADC_N7_MUX 1 +#define RTE_ADC_N7_PAD 0 + +#ifndef ADC_P8_LOC +#define RTE_ADC_P8_PORT 0 +#define RTE_ADC_P8_PIN 29 +#else +#define RTE_ADC_P8_PORT ADC_P8_PORT +#define RTE_ADC_P8_PIN ADC_P8_PIN +#endif +#define RTE_ADC_P8_MUX 1 +#define RTE_ADC_P8_PAD 0 + +#ifndef ADC_N8_LOC +#define RTE_ADC_N8_PORT 0 +#define RTE_ADC_N8_PIN 30 +#else +#define RTE_ADC_N8_PORT ADC_N8_PORT +#define RTE_ADC_N8_PIN ADC_N8_PIN +#endif +#define RTE_ADC_N8_MUX 1 +#define RTE_ADC_N8_PAD 0 + +#ifndef ADC_P10_LOC +#define RTE_ADC_P10_PORT 0 +#define RTE_ADC_P10_PIN 1 +#else +#define RTE_ADC_P10_PORT ADC_P10_PORT +#define RTE_ADC_P10_PIN ADC_P10_PIN +#endif +#define RTE_ADC_P10_MUX 1 + +#ifndef ADC_P11_LOC +#define RTE_ADC_P11_PORT 0 +#define RTE_ADC_P11_PIN 3 +#else +#define RTE_ADC_P11_PORT ADC_P11_PORT +#define RTE_ADC_P11_PIN ADC_P11_PIN +#endif +#define RTE_ADC_P11_MUX 1 + +#ifndef ADC_P12_LOC +#define RTE_ADC_P12_PORT 0 +#define RTE_ADC_P12_PIN 5 +#else +#define RTE_ADC_P12_PORT ADC_P12_PORT +#define RTE_ADC_P12_PIN ADC_P12_PIN +#endif +#define RTE_ADC_P12_MUX 1 + +#ifndef ADC_P13_LOC +#define RTE_ADC_P13_PORT 0 +#define RTE_ADC_P13_PIN 11 +#else +#define RTE_ADC_P13_PORT ADC_P13_PORT +#define RTE_ADC_P13_PIN ADC_P13_PIN +#endif +#define RTE_ADC_P13_MUX 1 + +#ifndef ADC_P14_LOC +#define RTE_ADC_P14_PORT 0 +#define RTE_ADC_P14_PIN 9 +#else +#define RTE_ADC_P14_PORT ADC_P14_PORT +#define RTE_ADC_P14_PIN ADC_P14_PIN +#endif +#define RTE_ADC_P14_MUX 1 + +#ifndef ADC_P15_LOC +#define RTE_ADC_P15_PORT 0 +#define RTE_ADC_P15_PIN 7 +#else +#define RTE_ADC_P15_PORT ADC_P15_PORT +#define RTE_ADC_P15_PIN ADC_P15_PIN +#endif +#define RTE_ADC_P15_MUX 1 + +#ifndef ADC_P16_LOC +#define RTE_ADC_P16_PORT 0 +#define RTE_ADC_P16_PIN 26 +#else +#define RTE_ADC_P16_PORT ADC_P16_PORT +#define RTE_ADC_P16_PIN ADC_P16_PIN +#endif +#define RTE_ADC_P16_MUX 1 +#define RTE_ADC_P16_PAD 0 + +#ifndef ADC_P17_LOC +#define RTE_ADC_P17_PORT 0 +#define RTE_ADC_P17_PIN 28 +#else +#define RTE_ADC_P17_PORT ADC_P17_PORT +#define RTE_ADC_P17_PIN ADC_P17_PIN +#endif +#define RTE_ADC_P17_MUX 1 +#define RTE_ADC_P17_PAD 0 + +#ifndef ADC_P18_LOC +#define RTE_ADC_P18_PORT 0 +#define RTE_ADC_P18_PIN 30 +#else +#define RTE_ADC_P18_PORT ADC_P18_PORT +#define RTE_ADC_P18_PIN ADC_P18_PIN +#endif +#define RTE_ADC_P18_MUX 1 +#define RTE_ADC_P18_PAD 0 + +//ADC END + +//COMPARATOR START + +#ifndef COMP1_P0_LOC +#define RTE_COMP1_P0_PORT 0 +#define RTE_COMP1_P0_PIN 0 +#else +#define RTE_COMP1_P0_PORT COMP1_P0_PORT +#define RTE_COMP1_P0_PIN COMP1_P0_PIN +#endif +#define RTE_COMP1_P0_MUX 0 + +#ifndef COMP1_N0_LOC +#define RTE_COMP1_N0_PORT 0 +#define RTE_COMP1_N0_PIN 1 +#else +#define RTE_COMP1_N0_PORT COMP1_N0_PORT +#define RTE_COMP1_N0_PIN COMP1_N0_PIN +#endif +#define RTE_COMP1_N0_MUX 0 + +#ifndef COMP1_P1_LOC +#define RTE_COMP1_P1_PORT 0 +#define RTE_COMP1_P1_PIN 5 +#else +#define RTE_COMP1_P1_PORT COMP1_P1_PORT +#define RTE_COMP1_P1_PIN COMP1_P1_PIN +#endif +#define RTE_COMP1_P1_MUX 0 + +#ifndef COMP1_N1_LOC +#define RTE_COMP1_N1_PORT 0 +#define RTE_COMP1_N1_PIN 4 +#else +#define RTE_COMP1_N1_PORT COMP1_N1_PORT +#define RTE_COMP1_N1_PIN COMP1_N1_PIN +#endif +#define RTE_COMP1_N1_MUX 0 + +#ifndef COMP2_P0_LOC +#define RTE_COMP2_P0_PORT 0 +#define RTE_COMP2_P0_PIN 2 +#else +#define RTE_COMP2_P0_PORT COMP2_P0_PORT +#define RTE_COMP2_P0_PIN COMP2_P0_PIN +#endif +#define RTE_COMP2_P0_MUX 0 + +#ifndef COMP2_N0_LOC +#define RTE_COMP2_N0_PORT 0 +#define RTE_COMP2_N0_PIN 3 +#else +#define RTE_COMP2_N0_PORT COMP2_N0_PORT +#define RTE_COMP2_N0_PIN COMP2_N0_PIN +#endif +#define RTE_COMP2_N0_MUX 0 + +#ifndef COMP2_P1_LOC +#define RTE_COMP2_P1_PORT 0 +#define RTE_COMP2_P1_PIN 27 +#else +#define RTE_COMP2_P1_PORT COMP2_P1_PORT +#define RTE_COMP2_P1_PIN COMP2_P1_PIN +#endif +#define RTE_COMP2_P1_MUX 0 +#define RTE_COMP2_P1_PAD 0 + +#ifndef COMP2_N1_LOC +#define RTE_COMP2_N1_PORT 0 +#define RTE_COMP2_N1_PIN 28 +#else +#define RTE_COMP2_N1_PORT COMP2_N1_PORT +#define RTE_COMP2_N1_PIN COMP2_N1_PIN +#endif +#define RTE_COMP2_N1_MUX 0 + +//COMPARATOR END + #define RTE_GPIO_6_PORT 0 #define RTE_GPIO_6_PAD 1 #define RTE_GPIO_6_PIN 6 @@ -3052,5 +4885,15 @@ // ULP GPIO as enable pin for sensors #define SENSOR_ENABLE_GPIO_MAPPED_TO_ULP -#define SENSOR_ENABLE_GPIO_PORT RTE_GPIO_3_PORT -#define SENSOR_ENABLE_GPIO_PIN RTE_GPIO_3_PIN +#define SENSOR_ENABLE_GPIO_PORT RTE_ULP_GPIO_2_PORT +#define SENSOR_ENABLE_GPIO_PIN RTE_ULP_GPIO_2_PIN + +// Memlcd GPIOs +#define RTE_MEMLCD_CS_PIN 4 // Memlcd SPI CS pin +#define RTE_MEMLCD_CS_PORT 0 // Memlcd SPI CS port + +#define RTE_MEMLCD_EXTCOMIN_PIN 5 // Memlcd external communication pin +#define RTE_MEMLCD_EXTCOMIN_PORT 0 // Memlcd external communication port + +#define RTE_MEMLCD_ENABLE_DISPLAY_PIN 0 // Memlcd display enable pin +#define RTE_MEMLCD_ENABLE_DISPLAY_PORT 0 // Memlcd display enable port \ No newline at end of file diff --git a/components/board/silabs/config/brd4343a/pin_config.h b/components/board/silabs/config/brd4343a/pin_config.h new file mode 100644 index 000000000..2bbc8c59c --- /dev/null +++ b/components/board/silabs/config/brd4343a/pin_config.h @@ -0,0 +1,140 @@ +#ifndef PIN_CONFIG_H +#define PIN_CONFIG_H + +// $[USART0] +// [USART0]$ + +// $[UART1] +// [UART1]$ + +// $[ULP_UART] +// [ULP_UART]$ + +// $[I2C0] +// [I2C0]$ + +// $[I2C1] +// [I2C1]$ + +// $[ULP_I2C] +// [ULP_I2C]$ + +// $[SSI_MASTER] +// [SSI_MASTER]$ + +// $[SSI_SLAVE] +// [SSI_SLAVE]$ + +// $[ULP_SPI] +// [ULP_SPI]$ + +// $[GSPI_MASTER] +// [GSPI_MASTER]$ + +// $[I2S0] +// [I2S0]$ + +// $[ULP_I2S] +// [ULP_I2S]$ + +// $[SCT] +// [SCT]$ + +// $[SIO] +// [SIO]$ + +// $[PWM] +// [PWM]$ + +// $[PWM_CH0] +// [PWM_CH0]$ + +// $[PWM_CH1] +// [PWM_CH1]$ + +// $[PWM_CH2] +// [PWM_CH2]$ + +// $[PWM_CH3] +// [PWM_CH3]$ + +// $[ADC_CH1] +// [ADC_CH1]$ + +// $[ADC_CH2] +// [ADC_CH2]$ + +// $[ADC_CH3] +// [ADC_CH3]$ + +// $[ADC_CH4] +// [ADC_CH4]$ + +// $[ADC_CH5] +// [ADC_CH5]$ + +// $[ADC_CH6] +// [ADC_CH6]$ + +// $[ADC_CH7] +// [ADC_CH7]$ + +// $[ADC_CH8] +// [ADC_CH8]$ + +// $[ADC_CH9] +// [ADC_CH9]$ + +// $[ADC_CH10] +// [ADC_CH10]$ + +// $[ADC_CH11] +// [ADC_CH11]$ + +// $[ADC_CH12] +// [ADC_CH12]$ + +// $[ADC_CH13] +// [ADC_CH13]$ + +// $[ADC_CH14] +// [ADC_CH14]$ + +// $[ADC_CH15] +// [ADC_CH15]$ + +// $[ADC_CH16] +// [ADC_CH16]$ + +// $[ADC_CH17] +// [ADC_CH17]$ + +// $[ADC_CH18] +// [ADC_CH18]$ + +// $[ADC_CH19] +// [ADC_CH19]$ + +// $[COMP1] +// [COMP1]$ + +// $[COMP2] +// [COMP2]$ + +// $[DAC0] +// [DAC0]$ + +// $[DAC1] +// [DAC1]$ + +// $[CUSTOM_PIN_NAME] +#ifndef _PORT +#define _PORT 0 +#endif +#ifndef _PIN +#define _PIN 6 +#endif + +// [CUSTOM_PIN_NAME]$ + +#endif // PIN_CONFIG_H diff --git a/components/board/silabs/config/brd4343b/RTE_Device_917.h b/components/board/silabs/config/brd4343b/RTE_Device_917.h index 32c7e231c..c98d6a0e6 100644 --- a/components/board/silabs/config/brd4343b/RTE_Device_917.h +++ b/components/board/silabs/config/brd4343b/RTE_Device_917.h @@ -46,7 +46,7 @@ #define RTE_BUTTON1_PIN (11U) #define RTE_BUTTON1_PAD 6 -#define RTE_LED0_PORT 0 +#define RTE_LED0_PORT 4 #define RTE_LED0_NUMBER 0 #define RTE_LED0_PIN (0U) @@ -62,7 +62,7 @@ #define RTE_USART0 1 -#define RTE_USART0_CLK_SRC USART_INTFPLLCLK +#define RTE_USART0_CLK_SRC USART_ULPREFCLK #define RTE_USART0_CLK_DIV_FACT 1 #define RTE_USART0_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER @@ -86,6 +86,7 @@ // USART0_CLK <0=>P0_8 <1=>P0_25 <2=>P0_52 <3=>P0_64 // CLK of USART0 +#ifndef USART0_CLK_LOC #define RTE_USART0_CLK_PORT_ID 0 #if (RTE_USART0_CLK_PORT_ID == 0) @@ -106,10 +107,35 @@ #else #error "Invalid USART0 RTE_USART0_CLK_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_CLK_PORT USART0_CLK_PORT +#if (USART0_CLK_LOC == 0) +#define RTE_USART0_CLK_PIN USART0_CLK_PIN +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 3 +#endif +#if (USART0_CLK_LOC == 1) +#define RTE_USART0_CLK_PIN USART0_CLK_PIN +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 0 //NO PAD +#endif +#if (USART0_CLK_LOC == 2) +#define RTE_USART0_CLK_PIN USART0_CLK_PIN +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 16 +#endif +#if (USART0_CLK_LOC == 3) +#define RTE_USART0_CLK_PIN (USART0_CLK_PIN + GPIO_MAX_PIN) +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 22 +#endif +//Pintool data +#endif // USART0_TX <0=>P0_15 <1=>P0_30 <2=>P0_54 <3=>P0_68 <4=>P0_71 // TX for USART0 - +#ifndef USART0_TX_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_USART0_TX_PORT_ID 1 #else @@ -139,10 +165,40 @@ #else #error "Invalid USART0 RTE_USART0_TX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_TX_PORT USART0_TX_PORT +#if (USART0_TX_LOC == 4) +#define RTE_USART0_TX_PIN USART0_TX_PIN +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 8 +#endif +#if (USART0_TX_LOC == 5) +#define RTE_USART0_TX_PIN USART0_TX_PIN +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 0 //NO PAD +#endif +#if (USART0_TX_LOC == 6) +#define RTE_USART0_TX_PIN USART0_TX_PIN +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 18 +#endif +#if (USART0_TX_LOC == 7) +#define RTE_USART0_TX_PIN (USART0_TX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 26 +#endif +#if (USART0_TX_LOC == 8) +#define RTE_USART0_TX_PIN (USART0_TX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_TX_MUX 4 +#define RTE_USART0_TX_PAD 29 +#endif +//Pintool data +#endif // USART0_RX <0=>P0_10 <1=>P0_29 <2=>P0_55 <3=>P0_65 <4=>P0_70 // RX for USART0 - +#ifndef USART0_RX_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_USART0_RX_PORT_ID 1 #else @@ -177,9 +233,40 @@ #else #error "Invalid USART0 RTE_USART0_RX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_RX_PORT USART0_RX_PORT +#if (USART0_RX_LOC == 9) +#define RTE_USART0_RX_PIN USART0_RX_PIN +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 5 +#endif +#if (USART0_RX_LOC == 10) +#define RTE_USART0_RX_PIN USART0_RX_PIN +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 0 //no pad +#endif +#if (USART0_RX_LOC == 11) +#define RTE_USART0_RX_PIN USART0_RX_PIN +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 19 +#endif +#if (USART0_RX_LOC == 12) +#define RTE_USART0_RX_PIN (USART0_RX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 23 +#endif +#if (USART0_RX_LOC == 13) +#define RTE_USART0_RX_PIN (USART0_RX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_RX_MUX 4 +#define RTE_USART0_RX_PAD 28 +#endif +//Pintool data +#endif // USART0_CTS <0=>P0_6 <1=>P0_26 <2=>P0_56 <3=>P0_70 // CTS for USART0 +#ifndef USART0_CTS_LOC #define RTE_USART0_CTS_PORT_ID 0 #if (RTE_USART0_CTS_PORT_ID == 0) @@ -205,9 +292,35 @@ #else #error "Invalid USART0 RTE_USART0_CTS_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_CTS_PORT USART0_CTS_PORT +#if (USART0_CTS_LOC == 14) +#define RTE_USART0_CTS_PIN USART0_CTS_PIN +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 1 +#endif +#if (USART0_CTS_LOC == 15) +#define RTE_USART0_CTS_PIN USART0_CTS_PIN +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 0 //NO PAD +#endif +#if (USART0_CTS_LOC == 16) +#define RTE_USART0_CTS_PIN USART0_CTS_PIN +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 20 +#endif +#if (USART0_CTS_LOC == 17) +#define RTE_USART0_CTS_PIN (USART0_CTS_PIN + GPIO_MAX_PIN) +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 28 +#endif +//Pintool data +#endif // USART0_RTS <0=>P0_9 <1=>P0_28 <2=>P0_53 <3=>P0_69 // RTS for USART0 +#ifndef USART0_RTS_LOC #define RTE_USART0_RTS_PORT_ID 0 #if (RTE_USART0_RTS_PORT_ID == 0) @@ -228,10 +341,35 @@ #else #error "Invalid USART0 RTE_USART0_RTS_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_RTS_PORT USART0_RTS_PORT +#if (USART0_RTS_LOC == 18) +#define RTE_USART0_RTS_PIN USART0_RTS_PIN +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 4 +#endif +#if (USART0_RTS_LOC == 19) +#define RTE_USART0_RTS_PIN USART0_RTS_PIN +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 0 //NO PAD +#endif +#if (USART0_RTS_LOC == 20) +#define RTE_USART0_RTS_PIN USART0_RTS_PIN +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 17 +#endif +#if (USART0_RTS_LOC == 21) +#define RTE_USART0_RTS_PIN (USART0_RTS_PIN + GPIO_MAX_PIN) +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 27 +#endif +//Pintool data +#endif // USART0_IR_TX <0=>P0_48 <1=>P0_72 // IR TX for USART0 - +#ifndef USART0_IRTX_LOC #define RTE_IR_TX_PORT_ID 0 #if ((RTE_IR_TX_PORT_ID == 2)) #error "Invalid USART0 RTE_USART0_IR_TX_PIN Pin Configuration!" @@ -255,10 +393,35 @@ #else #error "Invalid USART0 RTE_USART0_IR_TX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_IR_TX_PORT USART0_IRTX_PORT +#if (USART0_IRTX_LOC == 22) +#define RTE_USART0_IR_TX_PIN USART0_IRTX_PIN +#define RTE_USART0_IR_TX_MUX 13 +#define RTE_USART0_IR_TX_PAD 0 //No pad +#endif +#if (USART0_IRTX_LOC == 23) +#define RTE_USART0_IR_TX_PIN USART0_IRTX_PIN +#define RTE_USART0_IR_TX_MUX 2 +#define RTE_USART0_IR_TX_PAD 12 +#endif +#if (USART0_IRTX_LOC == 24) +#define RTE_USART0_IR_TX_PIN (USART0_IRTX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_IR_TX_MUX 11 +#define RTE_USART0_IR_TX_PAD 23 +#endif +#if (USART0_IRTX_LOC == 25) +#define RTE_USART0_IR_TX_PIN (USART0_IRTX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_IR_TX_MUX 2 +#define RTE_USART0_IR_TX_PAD 30 +#endif +//Pintool data +#endif // USART0_IR_RX <0=>P0_47 <1=>P0_71 <2=>P0_64 <3=>P0_25 // IR RX for USART0 - +#ifndef USART0_IRRX_LOC #define RTE_IR_RX_PORT_ID 0 #if ((RTE_IR_RX_PORT_ID == 2)) #error "Invalid USART0 RTE_USART0_IR_RX_PIN Pin Configuration!" @@ -282,9 +445,35 @@ #else #error "Invalid USART0 RTE_USART0_IR_RX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_IR_RX_PORT USART0_IRRX_PORT +#if (USART0_IRRX_LOC == 26) +#define RTE_USART0_IR_RX_PIN USART0_IRRX_PIN +#define RTE_USART0_IR_RX_MUX 13 +#define RTE_USART0_IR_RX_PAD 0 //no pad +#endif +#if (USART0_IRRX_LOC == 27) +#define RTE_USART0_IR_RX_PIN USART0_IRRX_PIN +#define RTE_USART0_IR_RX_MUX 2 +#define RTE_USART0_IR_RX_PAD 11 +#endif +#if (USART0_IRRX_LOC == 28) +#define RTE_USART0_IR_RX_PIN (USART0_IRRX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_IR_RX_MUX 11 +#define RTE_USART0_IR_RX_PAD 22 +#endif +#if (USART0_IRRX_LOC == 29) +#define RTE_USART0_IR_RX_PIN (USART0_IRRX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_IR_RX_MUX 2 +#define RTE_USART0_IR_RX_PAD 29 +#endif +//Pintool data +#endif // USART0_RI <0=>P0_27 <1=>P0_46 <2=>P0_68 // RI for USART0 +#ifndef USART0_RI_LOC #define RTE_RI_PORT_ID 0 #if (RTE_RI_PORT_ID == 0) @@ -300,9 +489,30 @@ #else #error "Invalid USART0 RTE_USART0_RI_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_RI_PORT USART0_RI_PORT +#if (USART0_RI_LOC == 30) +#define RTE_USART0_RI_PIN USART0_RI_PIN +#define RTE_USART0_RI_MUX 2 +#define RTE_USART0_RI_PAD 0 //no pad +#endif +#if (USART0_RI_LOC == 31) +#define RTE_USART0_RI_PIN USART0_RI_PIN +#define RTE_USART0_RI_MUX 2 +#define RTE_USART0_RI_PAD 10 +#endif +#if (USART0_RI_LOC == 32) +#define RTE_USART0_RI_PIN (USART0_RI_PIN + GPIO_MAX_PIN) +#define RTE_USART0_RI_MUX 11 +#define RTE_USART0_RI_PAD 26 +#endif +//Pintool data +#endif // USART0_DSR <0=>P0_11 <1=>P0_57 // DSR for USART0 +#ifndef USART0_DSR_LOC #define RTE_DSR_PORT_ID 0 #if (RTE_DSR_PORT_ID == 0) @@ -318,27 +528,56 @@ #else #error "Invalid USART0 RTE_USART0_RI_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_USART0_DSR_PORT USART0_DSR_PORT +#define RTE_USART0_DSR_PIN USART0_DSR_PIN +#if (USART0_DSR_LOC == 33) +#define RTE_USART0_DSR_MUX 2 +#define RTE_USART0_DSR_PAD 6 +#endif +#if (USART0_DSR_LOC == 34) +#define RTE_USART0_DSR_MUX 2 +#define RTE_USART0_DSR_PAD 21 +#endif +//Pintool data +#endif + // USART0_DCD <0=>P0_12 <1=>P0_29 // DCD for USART0 - +#ifndef USART0_DCD_LOC #define RTE_USART0_DCD_PORT 0 #define RTE_USART0_DCD_PIN 12 -#define RTE_USART0_DCD_MUX 2 -#define RTE_USART0_DCD_PAD 7 +#else +#define RTE_USART0_DCD_PORT USART0_DCD_PORT +#define RTE_USART0_DCD_PIN USART0_DCD_PIN +#if (USART0_DCD_LOC == 35) +#define RTE_USART0_DCD_MUX 2 +#define RTE_USART0_DCD_PAD 7 +#elif (USART0_DCD_LOC == 36) +#define RTE_USART0_DCD_MUX 12 +#define RTE_USART0_DCD_PAD 0 +#endif +#endif // USART0_DTR <0=>P0_7 // DTR for USART0 +#ifndef USART0_DTR_LOC #define RTE_USART0_DTR_PORT 0 #define RTE_USART0_DTR_PIN 7 -#define RTE_USART0_DTR_MUX 2 -#define RTE_USART0_DTR_PAD 2 +#else +#define RTE_USART0_DTR_PORT USART0_DTR_PORT +#define RTE_USART0_DTR_PIN USART0_DTR_PIN +#endif +#define RTE_USART0_DTR_MUX 2 +#define RTE_USART0_DTR_PAD 2 // // UART1 [Driver_UART1] // Configuration settings for Driver_UART1 in component ::CMSIS Driver:USART #define RTE_UART1 1 -#define RTE_UART1_CLK_SRC USART_INTFPLLCLK +#define RTE_UART1_CLK_SRC USART_ULPREFCLK #define RTE_UART1_CLK_DIV_FACT 1 #define RTE_UART1_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER @@ -358,7 +597,7 @@ /*UART1 PINS*/ // UART1_TX <0=>P0_7 <1=>P0_30 <2=>P0_67 <3=>P0_69 <4=>P0_73 <5=>P0_75 <6=>P0_34 // TX of UART1 - +#ifndef UART1_TX_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_UART1_TX_PORT_ID 0 #else @@ -397,10 +636,40 @@ #else #error "Invalid UART1 RTE_UART1_TX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_UART1_TX_PORT UART1_TX_PORT +#if (UART1_TX_LOC == 0) +#define RTE_UART1_TX_PIN UART1_TX_PIN +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 2 +#endif +#if (UART1_TX_LOC == 1) +#define RTE_UART1_TX_PIN UART1_TX_PIN +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 0 //no pad +#endif +#if (UART1_TX_LOC == 2) +#define RTE_UART1_TX_PIN (UART1_TX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 27 +#endif +#if (UART1_TX_LOC == 3) +#define RTE_UART1_TX_PIN (UART1_TX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 31 +#endif +#if (UART1_TX_LOC == 4) +#define RTE_UART1_TX_PIN (UART1_TX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_TX_MUX 9 +#define RTE_UART1_TX_PAD 33 +#endif +//Pintool data +#endif // UART1_RX <0=>P0_6 <1=>P0_29 <2=>P0_66 <3=>P0_68 <4=>P0_72 <5=>P0_74 <6=>P0_33 // RX of UART1 - +#ifndef UART1_RX_LOC #define RTE_UART1_RX_PORT_ID 0 #if (RTE_UART1_RX_PORT_ID == 0) @@ -431,9 +700,40 @@ #else #error "Invalid UART1 RTE_UART1_RX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_UART1_RX_PORT UART1_RX_PORT +#if (UART1_RX_LOC == 5) +#define RTE_UART1_RX_PIN UART1_RX_PIN +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 1 +#endif +#if (UART1_RX_LOC == 6) +#define RTE_UART1_RX_PIN UART1_RX_PIN +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 0 //no pad +#endif +#if (UART1_RX_LOC == 7) +#define RTE_UART1_RX_PIN (UART1_RX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 26 +#endif +#if (UART1_RX_LOC == 8) +#define RTE_UART1_RX_PIN (UART1_RX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 30 +#endif +#if (UART1_RX_LOC == 9) +#define RTE_UART1_RX_PIN (UART1_RX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RX_MUX 9 +#define RTE_UART1_RX_PAD 32 +#endif +//Pintool data +#endif // UART1_CTS <0=>P0_11 <1=>P0_28 <2=>P0_51 <3=>P0_65 <4=>P0_71 <5=>P0_73 <6=>P0_32 // CTS of UART1 +#ifndef UART1_CTS_LOC #define RTE_UART1_CTS_PORT_ID 0 #if (RTE_UART1_CTS_PORT_ID == 0) @@ -464,10 +764,45 @@ #else #error "Invalid UART1 RTE_UART1_CTS_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_UART1_CTS_PORT UART1_CTS_PORT +#if (UART1_CTS_LOC == 10) +#define RTE_UART1_CTS_PIN UART1_CTS_PIN +#define RTE_UART1_CTS_MUX 6 +#define RTE_UART1_CTS_PAD 6 +#endif +#if (UART1_CTS_LOC == 11) +#define RTE_UART1_CTS_PIN UART1_CTS_PIN +#define RTE_UART1_CTS_MUX 6 +#define RTE_UART1_CTS_PAD 0 //no pad +#endif +#if (UART1_CTS_LOC == 12) +#define RTE_UART1_CTS_PIN UART1_CTS_PIN +#define RTE_UART1_CTS_MUX 9 +#define RTE_UART1_CTS_PAD 15 +#endif +#if (UART1_CTS_LOC == 13) +#define RTE_UART1_CTS_PIN (UART1_CTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_CTS_MUX 9 +#define RTE_UART1_CTS_PAD 23 +#endif +#if (UART1_CTS_LOC == 14) +#define RTE_UART1_CTS_PIN (UART1_CTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_CTS_MUX 6 +#define RTE_UART1_CTS_PAD 29 +#endif +#if (UART1_CTS_LOC == 15) +#define RTE_UART1_CTS_PIN (UART1_CTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_CTS_MUX 9 +#define RTE_UART1_CTS_PAD 31 +#endif +//Pintool data +#endif // UART1_RTS <0=>P0_10 <1=>P0_27 <2=>P0_50 <3=>P0_64 <4=>P0_70 <5=>P0_72 <6=>P0_31 // RTS of UART1 - +#ifndef UART1_RTS_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_UART1_RTS_PORT_ID 0 #else @@ -502,6 +837,42 @@ #else #error "Invalid UART1 RTE_UART1_RTS_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_UART1_RTS_PORT UART1_RTS_PORT +#if (UART1_RTS_LOC == 16) +#define RTE_UART1_RTS_PIN UART1_RTS_PIN +#define RTE_UART1_RTS_MUX 6 +#define RTE_UART1_RTS_PAD 5 +#endif +#if (UART1_RTS_LOC == 17) +#define RTE_UART1_RTS_PIN UART1_RTS_PIN +#define RTE_UART1_RTS_MUX 6 +#define RTE_UART1_RTS_PAD 0 //no pad +#endif +#if (UART1_RTS_LOC == 18) +#define RTE_UART1_RTS_PIN UART1_RTS_PIN +#define RTE_UART1_RTS_MUX 9 +#define RTE_UART1_RTS_PAD 14 +#endif +#if (UART1_RTS_LOC == 19) +#define RTE_UART1_RTS_PIN (UART1_RTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RTS_MUX 9 +#define RTE_UART1_RTS_PAD 22 +#endif +#if (UART1_RTS_LOC == 20) +#define RTE_UART1_RTS_PIN (UART1_RTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RTS_MUX 6 +#define RTE_UART1_RTS_PAD 28 +#endif +#if (UART1_RTS_LOC == 21) +#define RTE_UART1_RTS_PIN (UART1_RTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RTS_MUX 9 +#define RTE_UART1_RTS_PAD 30 +#endif +//Pintool data +#endif + // // ULP_UART [Driver_ULP_UART] @@ -528,6 +899,7 @@ /*ULPSS UART PINS*/ // UART1_TX <0=>P0_3 <1=>P0_7 <2=>P0_11 // TX of ULPSS UART +#ifndef ULP_UART_TX_LOC #define RTE_ULP_UART_TX_PORT_ID 1 #if (RTE_ULP_UART_TX_PORT_ID == 0) #define RTE_ULP_UART_TX_PORT 0 @@ -540,9 +912,17 @@ #else #error "Invalid ULPSS UART RTE_ULP_UART_TX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_ULP_UART_TX_PORT ULP_UART_TX_PORT +#define RTE_ULP_UART_TX_PIN ULP_UART_TX_PIN +#define RTE_ULP_UART_TX_MUX 3 +//Pintool data +#endif // UART1_RX <0=>P0_2 <1=>P0_6 <2=>P0_9 // RX of ULPSS UART +#ifndef ULP_UART_RX_LOC #define RTE_ULP_UART_RX_PORT_ID 2 #if (RTE_ULP_UART_RX_PORT_ID == 0) #define RTE_ULP_UART_RX_PORT 0 @@ -559,9 +939,17 @@ #else #error "Invalid ULPSS UART RTE_ULP_UART_RX_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_ULP_UART_RX_PORT ULP_UART_RX_PORT +#define RTE_ULP_UART_RX_PIN ULP_UART_RX_PIN +#define RTE_ULP_UART_RX_MUX 3 +//Pintool data +#endif // UART1_CTS <0=>P0_1 <1=>P0_5 <2=>P0_8 // CTS of ULPSS UART +#ifndef ULP_UART_CTS_LOC #define RTE_ULP_UART_CTS_PORT_ID 0 #if (RTE_ULP_UART_CTS_PORT_ID == 0) #define RTE_ULP_UART_CTS_PORT 0 @@ -574,17 +962,30 @@ #else #error "Invalid ULPSS UART RTE_ULP_UART_CTS_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_ULP_UART_CTS_PORT ULP_UART_CTS_PORT +#define RTE_ULP_UART_CTS_PIN ULP_UART_CTS_PIN +#define RTE_ULP_UART_CTS_MUX 3 +//Pintool data +#endif // UART1_RTS <0=>P0_0 <1=>P0_4 <2=>P0_10 // RTS of ULPSS UART +#ifndef ULP_UART_RTS_LOC #define RTE_ULP_UART_RTS_PORT_ID 0 #if (RTE_ULP_UART_RTS_PORT_ID == 0) #define RTE_ULP_UART_RTS_PORT 0 #define RTE_ULP_UART_RTS_PIN 10 -#define RTE_ULP_UART_RTS_MUX 3 #else #error "Invalid ULPSS UART RTE_ULP_UART_RTS_PIN Pin Configuration!" #endif +#else +#define RTE_ULP_UART_RTS_PORT ULP_UART_RTS_PORT +#define RTE_ULP_UART_RTS_PIN ULP_UART_RTS_PIN +#endif +#define RTE_ULP_UART_RTS_MUX 8 + // // SSI_MASTER (Serial Peripheral Interface 1) [Driver_SSI_MASTER] @@ -592,7 +993,7 @@ #define RTE_SSI_MASTER 1 // SSI_MASTER_MISO Pin <0=>GPIO_12 <1=>GPIO_27 <2=>GPIO_57 - +#ifndef SSI_MASTER_DATA1_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SSI_MASTER_MISO_PORT_ID 1 #else @@ -620,8 +1021,26 @@ #else #error "Invalid SSI_MASTER_MISO Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_MASTER_MISO 1 +#define RTE_SSI_MASTER_MISO_PORT SSI_MASTER_MISO_DATA1_PORT +#define RTE_SSI_MASTER_MISO_PIN SSI_MASTER_MISO_DATA1_PIN +#define RTE_SSI_MASTER_MISO_MODE EGPIO_PIN_MUX_MODE3 +#if (SSI_MASTER_DATA1_LOC == 3) +#define RTE_SSI_MASTER_MISO_PADSEL 7 +#endif +#if (SSI_MASTER_DATA1_LOC == 4) +#define RTE_SSI_MASTER_MISO_PADSEL 0 //NO PAD +#endif +#if (SSI_MASTER_DATA1_LOC == 5) +#define RTE_SSI_MASTER_MISO_PADSEL 21 +#endif +//Pintool data +#endif // SSI_MASTER_MOSI Pin <0=>GPIO_11 <1=>GPIO_26 <2=>GPIO_56 +#ifndef SSI_MASTER_DATA0_LOC #define RTE_SSI_MASTER_MOSI_PORT_ID 1 #if (RTE_SSI_MASTER_MOSI_PORT_ID == 0) @@ -645,8 +1064,26 @@ #else #error "Invalid SSI_MASTER_MOSI Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_MASTER_MOSI 1 +#define RTE_SSI_MASTER_MOSI_PORT SSI_MASTER_MOSI_DATA0_PORT +#define RTE_SSI_MASTER_MOSI_PIN SSI_MASTER_MOSI_DATA0_PIN +#define RTE_SSI_MASTER_MOSI_MODE EGPIO_PIN_MUX_MODE3 +#if (SSI_MASTER_DATA0_LOC == 0) +#define RTE_SSI_MASTER_MOSI_PADSEL 6 +#endif +#if (SSI_MASTER_DATA0_LOC == 1) +#define RTE_SSI_MASTER_MOSI_PADSEL 0 //NO PAD +#endif +#if (SSI_MASTER_DATA0_LOC == 2) +#define RTE_SSI_MASTER_MOSI_PADSEL 20 +#endif +//Pintool data +#endif // SSI_MASTER_SCK Pin <0=>GPIO_8 <1=>GPIO_25 <2=>GPIO_52 +#ifndef SSI_MASTER_SCK_LOC #define RTE_SSI_MASTER_SCK_PORT_ID 1 #if (RTE_SSI_MASTER_SCK_PORT_ID == 0) @@ -670,6 +1107,23 @@ #else #error "Invalid SSI_MASTER_SCK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_MASTER_SCK 1 +#define RTE_SSI_MASTER_SCK_PORT SSI_MASTER_SCK__PORT +#define RTE_SSI_MASTER_SCK_PIN SSI_MASTER_SCK__PIN +#define RTE_SSI_MASTER_SCK_MODE EGPIO_PIN_MUX_MODE3 +#if (SSI_MASTER_SCK_LOC == 6) +#define RTE_SSI_MASTER_SCK_PADSEL 3 +#endif +#if (SSI_MASTER_SCK_LOC == 7) +#define RTE_SSI_MASTER_SCK_PADSEL 0 //NO PAD +#endif +#if (SSI_MASTER_SCK_LOC == 8) +#define RTE_SSI_MASTER_SCK_PADSEL 16 +#endif +//Pintool data +#endif #define M4_SSI_CS0 1 #define M4_SSI_CS1 0 @@ -677,6 +1131,7 @@ #define M4_SSI_CS3 0 // SSI_MASTER_CS Pin <0=>GPIO_9 <1=>GPIO_28 <2=>GPIO_53 <3=>GPIO_10 <4=>GPIO_15 <5=>GPIO_50 <6=>GPIO_51 +#ifndef SSI_MASTER_CS0_LOC #define RTE_SSI_MASTER_CS0_PORT_ID 1 #if (RTE_SSI_MASTER_CS0_PORT_ID == 0) @@ -700,20 +1155,43 @@ #else #error "Invalid SSI_MASTER_CS0 Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_MASTER_CS0 M4_SSI_CS0 +#define RTE_SSI_MASTER_CS0_PORT SSI_MASTER_CS0__PORT +#define RTE_SSI_MASTER_CS0_PIN SSI_MASTER_CS0__PIN +#define RTE_SSI_MASTER_CS0_MODE EGPIO_PIN_MUX_MODE3 +#if (SSI_MASTER_CS0_LOC == 9) +#define RTE_SSI_MASTER_CS0_PADSEL 4 +#endif +#if (SSI_MASTER_CS0_LOC == 10) +#define RTE_SSI_MASTER_CS0_PADSEL 0 //NO PAD +#endif +#if (SSI_MASTER_CS0_LOC == 11) +#define RTE_SSI_MASTER_CS0_PADSEL 17 +#endif +//Pintool data +#endif //CS1 +#ifndef SSI_MASTER_CS1_LOC #define RTE_SSI_MASTER_CS1_PORT_ID 0 #if (RTE_SSI_MASTER_CS1_PORT_ID == 0) -#define RTE_SSI_MASTER_CS1 M4_SSI_CS1 -#define RTE_SSI_MASTER_CS1_PORT 0 -#define RTE_SSI_MASTER_CS1_PIN 10 -#define RTE_SSI_MASTER_CS1_MODE EGPIO_PIN_MUX_MODE3 -#define RTE_SSI_MASTER_CS1_PADSEL 5 +#define RTE_SSI_MASTER_CS1_PORT 0 +#define RTE_SSI_MASTER_CS1_PIN 10 #else #error "Invalid SSI_MASTER_CS1 Pin Configuration!" #endif +#else +#define RTE_SSI_MASTER_CS1_PORT SSI_MASTER_CS1__PORT +#define RTE_SSI_MASTER_CS1_PIN SSI_MASTER_CS1__PIN +#endif +#define RTE_SSI_MASTER_CS1 M4_SSI_CS1 +#define RTE_SSI_MASTER_CS1_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS1_PADSEL 5 //CS2 +#ifndef SSI_MASTER_CS2_LOC #define RTE_SSI_MASTER_CS2_PORT_ID 1 #if (RTE_SSI_MASTER_CS2_PORT_ID == 0) #define RTE_SSI_MASTER_CS2 M4_SSI_CS2 @@ -730,18 +1208,37 @@ #else #error "Invalid SSI_MASTER_CS2 Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_MASTER_CS2 M4_SSI_CS2 +#define RTE_SSI_MASTER_CS2_PORT SSI_MASTER_CS2__PORT +#define RTE_SSI_MASTER_CS2_PIN SSI_MASTER_CS2__PIN +#define RTE_SSI_MASTER_CS2_MODE EGPIO_PIN_MUX_MODE3 +#if (SSI_MASTER_CS2_LOC == 13) +#define RTE_SSI_MASTER_CS2_PADSEL 8 +#endif +#if (SSI_MASTER_CS2_LOC == 14) +#define RTE_SSI_MASTER_CS2_PADSEL 14 +#endif +//Pintool data +#endif //CS3 +#ifndef SSI_MASTER_CS3_LOC #define RTE_SSI_MASTER_CS3_PORT_ID 0 #if (RTE_SSI_MASTER_CS3_PORT_ID == 0) -#define RTE_SSI_MASTER_CS3 M4_SSI_CS3 -#define RTE_SSI_MASTER_CS3_PORT 0 -#define RTE_SSI_MASTER_CS3_PIN 51 -#define RTE_SSI_MASTER_CS3_MODE EGPIO_PIN_MUX_MODE3 -#define RTE_SSI_MASTER_CS3_PADSEL 15 +#define RTE_SSI_MASTER_CS3_PORT 0 +#define RTE_SSI_MASTER_CS3_PIN 51 #else #error "Invalid SSI_MASTER_CS3 Pin Configuration!" #endif +#else +#define RTE_SSI_MASTER_CS3_PORT SSI_MASTER_CS3__PORT +#define RTE_SSI_MASTER_CS3_PIN SSI_MASTER_CS3__PIN +#endif +#define RTE_SSI_MASTER_CS3 M4_SSI_CS3 +#define RTE_SSI_MASTER_CS3_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS3_PADSEL 15 // DMA Rx // Channel <28=>28 @@ -763,6 +1260,7 @@ #define RTE_SSI_SLAVE_INPUT_CLOCK SSISLAVE_CLK // SSI_SLAVE_MISO Pin <0=>Not Used <1=>GPIO_11 <2=>GPIO_28 <3=>GPIO_49 <4=>GPIO_57 +#ifndef SSI_SLAVE_MISO_LOC #define RTE_SSI_SLAVE_MISO_PORT_ID 2 #if (RTE_SSI_SLAVE_MISO_PORT_ID == 0) @@ -794,9 +1292,29 @@ #else #error "Invalid SSI_SLAVE_MISO Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_SLAVE_MISO 1 +#define RTE_SSI_SLAVE_MISO_PORT SSI_SLAVE_MISO__PORT +#define RTE_SSI_SLAVE_MISO_PIN SSI_SLAVE_MISO__PIN +#define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8 +#if (SSI_SLAVE_MISO_LOC == 5) +#define RTE_SSI_SLAVE_MISO_PADSEL 6 +#endif +#if (SSI_SLAVE_MISO_LOC == 6) +#define RTE_SSI_SLAVE_MISO_PADSEL 0 //no pad +#endif +#if (SSI_SLAVE_MISO_LOC == 7) +#define RTE_SSI_SLAVE_MISO_PADSEL 13 +#endif +#if (SSI_SLAVE_MISO_LOC == 8) +#define RTE_SSI_SLAVE_MISO_PADSEL 21 +#endif +//Pintool data +#endif // SSI_SLAVE_MOSI Pin <0=>Not Used <1=>GPIO_10 <2=>GPIO_27 <3=>GPIO_48 <4=>GPIO_56 - +#ifndef SSI_SLAVE_MOSI_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SSI_SLAVE_MOSI_PORT_ID 2 #else @@ -832,8 +1350,29 @@ #else #error "Invalid SSI_SLAVE_MOSI Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_SLAVE_MOSI 1 +#define RTE_SSI_SLAVE_MOSI_PORT SSI_SLAVE_MOSI__PORT +#define RTE_SSI_SLAVE_MOSI_PIN SSI_SLAVE_MOSI__PIN +#define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8 +#if (SSI_SLAVE_MOSI_LOC == 1) +#define RTE_SSI_SLAVE_MOSI_PADSEL 5 +#endif +#if (SSI_SLAVE_MOSI_LOC == 2) +#define RTE_SSI_SLAVE_MOSI_PADSEL 0 //no pad +#endif +#if (SSI_SLAVE_MOSI_LOC == 3) +#define RTE_SSI_SLAVE_MOSI_PADSEL 12 +#endif +#if (SSI_SLAVE_MOSI_LOC == 4) +#define RTE_SSI_SLAVE_MOSI_PADSEL 20 +#endif +//Pintool data +#endif // SSI_SLAVE_SCK Pin <0=>Not Used <1=>GPIO_8 <2=>GPIO_26 <3=>GPIO_47 <4=>GPIO_52 +#ifndef SSI_SLAVE_SCK_LOC #define RTE_SSI_SLAVE_SCK_PORT_ID 2 #if (RTE_SSI_SLAVE_SCK_PORT_ID == 0) @@ -865,8 +1404,29 @@ #else #error "Invalid SSI_SLAVE_SCK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_SLAVE_SCK 1 +#define RTE_SSI_SLAVE_SCK_PORT SSI_SLAVE_SCK__PORT +#define RTE_SSI_SLAVE_SCK_PIN SSI_SLAVE_SCK__PIN +#define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8 +#if (SSI_SLAVE_SCK_LOC == 9) +#define RTE_SSI_SLAVE_SCK_PADSEL 3 +#endif +#if (SSI_SLAVE_SCK_LOC == 10) +#define RTE_SSI_SLAVE_SCK_PADSEL 0 //no pad +#endif +#if (SSI_SLAVE_SCK_LOC == 11) +#define RTE_SSI_SLAVE_SCK_PADSEL 11 +#endif +#if (SSI_SLAVE_SCK_LOC == 12) +#define RTE_SSI_SLAVE_SCK_PADSEL 16 +#endif +//Pintool data +#endif // SSI_SLAVE_CS Pin <0=>Not Used <1=>GPIO_9 <2=>GPIO_25 <3=>GPIO_46 <4=>GPIO_53 +#ifndef SSI_SLAVE_CS0_LOC #define RTE_SSI_SLAVE_CS_PORT_ID 1 #if (RTE_SSI_SLAVE_CS_PORT_ID == 0) @@ -898,6 +1458,26 @@ #else #error "Invalid SSI_SLAVE_CS Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_SLAVE_CS 1 +#define RTE_SSI_SLAVE_CS_PORT SSI_SLAVE_CS0__PORT +#define RTE_SSI_SLAVE_CS_PIN SSI_SLAVE_CS0__PIN +#define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8 +#if (SSI_SLAVE_CS0_LOC == 13) +#define RTE_SSI_SLAVE_CS_PADSEL 4 +#endif +#if (SSI_SLAVE_CS0_LOC == 14) +#define RTE_SSI_SLAVE_CS_PADSEL 0 //no pad +#endif +#if (SSI_SLAVE_CS0_LOC == 15) +#define RTE_SSI_SLAVE_CS_PADSEL 10 +#endif +#if (SSI_SLAVE_CS0_LOC == 16) +#define RTE_SSI_SLAVE_CS_PADSEL 17 +#endif +//Pintool data +#endif // DMA Rx // Channel <22=>22 @@ -915,7 +1495,7 @@ // -// SSI_ULP_MASTER (Serial Peripheral Interface 3) [Driver_SSI_ULP_MASTER] +// ULP SPI Peripheral (Serial Peripheral Interface 3) [Driver_SSI_ULP_MASTER] // Configuration settings for Driver_SSI_ULP_MASTER in component ::CMSIS Driver:SPI #define RTE_SSI_ULP_MASTER 1 @@ -925,6 +1505,7 @@ #define ULP_SSI_CS2 0 // SSI_ULP_MASTER_MISO Pin <0=>Not Used <1=>ULP_GPIO_2 <2=>ULP_GPIO_9 +#ifndef ULP_SPI_MISO_LOC #define RTE_SSI_ULP_MASTER_MISO_PORT_ID 0 #if (RTE_SSI_ULP_MASTER_MISO_PORT_ID == 0) #define RTE_SSI_ULP_MASTER_MISO 1 @@ -939,8 +1520,17 @@ #else #error "Invalid SSI_ULP_MISO Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_ULP_MASTER_MISO 1 +#define RTE_SSI_ULP_MASTER_MISO_PORT ULP_SPI_MISO__PORT +#define RTE_SSI_ULP_MASTER_MISO_PIN ULP_SPI_MISO__PIN +#define RTE_SSI_ULP_MASTER_MISO_MODE 1 +//Pintool data +#endif // SSI_ULP_MASTER_MOSI Pin <0=>Not Used <1=>ULP_GPIO_1 <2=>ULP_GPIO_11 +#ifndef ULP_SPI_MOSI_LOC #define RTE_SSI_ULP_MASTER_MOSI_PORT_ID 0 #if (RTE_SSI_ULP_MASTER_MOSI_PORT_ID == 0) #define RTE_SSI_ULP_MASTER_MOSI 1 @@ -955,8 +1545,17 @@ #else #error "Invalid SSI_ULP_MOSI Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_ULP_MASTER_MOSI 1 +#define RTE_SSI_ULP_MASTER_MOSI_PORT ULP_SPI_MOSI__PORT +#define RTE_SSI_ULP_MASTER_MOSI_PIN ULP_SPI_MOSI__PIN +#define RTE_SSI_ULP_MASTER_MOSI_MODE 1 +//Pintool data +#endif // SSI_ULP_MASTER_SCK Pin <0=>Not Used <1=>ULP_GPIO_0 <2=>ULP_GPIO_8 +#ifndef ULP_SPI_SCK_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SSI_ULP_MASTER_SCK_PORT_ID 2 #else @@ -977,8 +1576,17 @@ #else #error "Invalid SSI_ULP_SCK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SSI_ULP_MASTER_SCK 1 +#define RTE_SSI_ULP_MASTER_SCK_PORT ULP_SPI_SCK__PORT +#define RTE_SSI_ULP_MASTER_SCK_PIN ULP_SPI_SCK__PIN +#define RTE_SSI_ULP_MASTER_SCK_MODE 1 +//Pintool data +#endif // CS0 +#ifndef ULP_SPI_CS0_LOC #define RTE_SSI_ULP_MASTER_CS0_PORT_ID 1 #if (RTE_SSI_ULP_MASTER_CS0_PORT_ID == 0) #define RTE_SSI_ULP_MASTER_CS0 ULP_SSI_CS0 @@ -993,17 +1601,35 @@ #else #error "Change RTE_SSI_ULP_MASTER_CS_PORT_ID other than '1' or'3' as per PACKAGE_TYPE" #endif +#else +//Pintool data +#define RTE_SSI_ULP_MASTER_CS0 ULP_SSI_CS0 +#define RTE_SSI_ULP_MASTER_CS0_PORT ULP_SPI_CS0__PORT +#define RTE_SSI_ULP_MASTER_CS0_PIN ULP_SPI_CS0__PIN +#define RTE_SSI_ULP_MASTER_CS0_MODE 1 +//Pintool data +#endif // CS1 -#define RTE_SSI_ULP_MASTER_CS1 ULP_SSI_CS1 +#ifndef ULP_SPI_CS1_LOC #define RTE_SSI_ULP_MASTER_CS1_PORT 0 #define RTE_SSI_ULP_MASTER_CS1_PIN 4 +#else +#define RTE_SSI_ULP_MASTER_CS1_PORT ULP_SPI_CS1__PORT +#define RTE_SSI_ULP_MASTER_CS1_PIN ULP_SPI_CS1__PIN +#endif +#define RTE_SSI_ULP_MASTER_CS1 ULP_SSI_CS1 #define RTE_SSI_ULP_MASTER_CS1_MODE 1 // CS2 -#define RTE_SSI_ULP_MASTER_CS2 ULP_SSI_CS2 +#ifndef ULP_SPI_CS2_LOC #define RTE_SSI_ULP_MASTER_CS2_PORT 0 #define RTE_SSI_ULP_MASTER_CS2_PIN 6 +#else +#define RTE_SSI_ULP_MASTER_CS2_PORT ULP_SPI_CS2__PORT +#define RTE_SSI_ULP_MASTER_CS2_PIN ULP_SPI_CS2__PIN +#endif +#define RTE_SSI_ULP_MASTER_CS2 ULP_SSI_CS2 #define RTE_SSI_ULP_MASTER_CS2_MODE 1 // DMA Rx @@ -1064,6 +1690,7 @@ // I2S0_SCLK <0=>P0_8 <1=>P0_25 <2=>P0_46 <3=>P0_52 // SCLK of I2S0 +#ifndef I2S0_SCLK_LOC #define RTE_I2S0_SCLK_PORT_ID 1 #if (RTE_I2S0_SCLK_PORT_ID == 0) @@ -1089,9 +1716,29 @@ #else #error "Invalid I2S0 RTE_I2S0_SCLK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S0_SCLK_PORT I2S0_SCLK_PORT +#define RTE_I2S0_SCLK_PIN I2S0_SCLK_PIN +#define RTE_I2S0_SCLK_MUX 7 +#if (I2S0_SCLK_LOC == 0) +#define RTE_I2S0_SCLK_PAD 3 +#endif +#if (I2S0_SCLK_LOC == 1) +#define RTE_I2S0_SCLK_PAD 0 //no pad +#endif +#if (I2S0_SCLK_LOC == 2) +#define RTE_I2S0_SCLK_PAD 10 +#endif +#if (I2S0_SCLK_LOC == 3) +#define RTE_I2S0_SCLK_PAD 16 +#endif +//Pintool data +#endif // I2S0_WSCLK <0=>P0_9 <1=>P0_26 <2=>P0_47 <3=>P0_53 // WSCLK for I2S0 +#ifndef I2S0_WSCLK_LOC #define RTE_I2S0_WSCLK_PORT_ID 1 #if (RTE_I2S0_WSCLK_PORT_ID == 0) @@ -1117,9 +1764,29 @@ #else #error "Invalid I2S0 RTE_I2S0_WSCLK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S0_WSCLK_PORT I2S0_WSCLK_PORT +#define RTE_I2S0_WSCLK_PIN I2S0_WSCLK_PIN +#define RTE_I2S0_WSCLK_MUX 7 +#if (I2S0_WSCLK_LOC == 4) +#define RTE_I2S0_WSCLK_PAD 4 +#endif +#if (I2S0_WSCLK_LOC == 5) +#define RTE_I2S0_WSCLK_PAD 0 +#endif +#if (I2S0_WSCLK_LOC == 6) +#define RTE_I2S0_WSCLK_PAD 11 +#endif +#if (I2S0_WSCLK_LOC == 7) +#define RTE_I2S0_WSCLK_PAD 17 +#endif +//Pintool data +#endif // I2S0_DOUT0 <0=>P0_11 <1=>P0_28 <2=>P0_49 <3=>P0_57 // DOUT0 for I2S0 +#ifndef I2S0_DOUT0_LOC #define RTE_I2S0_DOUT0_PORT_ID 1 #if (RTE_I2S0_DOUT0_PORT_ID == 0) @@ -1145,9 +1812,29 @@ #else #error "Invalid I2S0 RTE_I2S0_DOUT0 Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S0_DOUT0_PORT I2S0_DOUT0_PORT +#define RTE_I2S0_DOUT0_PIN I2S0_DOUT0_PIN +#define RTE_I2S0_DOUT0_MUX 7 +#if (I2S0_DOUT0_LOC == 8) +#define RTE_I2S0_DOUT0_PAD 6 +#endif +#if (I2S0_DOUT0_LOC == 9) +#define RTE_I2S0_DOUT0_PAD 0 +#endif +#if (I2S0_DOUT0_LOC == 10) +#define RTE_I2S0_DOUT0_PAD 13 +#endif +#if (I2S0_DOUT0_LOC == 11) +#define RTE_I2S0_DOUT0_PAD 21 +#endif +//Pintool data +#endif // I2S0_DIN0 <0=>P0_10 <1=>P0_27 <2=>P0_48 <3=>P0_56 // DIN0 for I2S0 +#ifndef I2S0_DIN0_LOC #define RTE_I2S0_DIN0_PORT_ID 1 #if (RTE_I2S0_DIN0_PORT_ID == 0) @@ -1173,11 +1860,30 @@ #else #error "Invalid I2S0 RTE_I2S0_DIN0 Pin Configuration!" #endif - -// I2S0_DOUT1 <0=>P0_7 <1=>P0_30 <2=>P0_51 <3=>P0_55 -// DOUT1 for I2S0 - -#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#else +//Pintool data +#define RTE_I2S0_DIN0_PORT I2S0_DIN0_PORT +#define RTE_I2S0_DIN0_PIN I2S0_DIN0_PIN +#define RTE_I2S0_DIN0_MUX 7 +#if (I2S0_DIN0_LOC == 12) +#define RTE_I2S0_DIN0_PAD 5 +#endif +#if (I2S0_DIN0_LOC == 13) +#define RTE_I2S0_DIN0_PAD 0 +#endif +#if (I2S0_DIN0_LOC == 14) +#define RTE_I2S0_DIN0_PAD 12 +#endif +#if (I2S0_DIN0_LOC == 15) +#define RTE_I2S0_DIN0_PAD 20 +#endif +//Pintool data +#endif + +// I2S0_DOUT1 <0=>P0_7 <1=>P0_30 <2=>P0_51 <3=>P0_55 +// DOUT1 for I2S0 +#ifndef I2S0_DOUT1_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_I2S0_DOUT1_PORT_ID 1 #else #define RTE_I2S0_DOUT1_PORT_ID 0 @@ -1206,9 +1912,29 @@ #else #error "Invalid I2S0 RTE_I2S0_DOUT1 Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S0_DOUT1_PORT I2S0_DOUT1_PORT +#define RTE_I2S0_DOUT1_PIN I2S0_DOUT1_PIN +#define RTE_I2S0_DOUT1_MUX 7 +#if (I2S0_DOUT1_LOC == 16) +#define RTE_I2S0_DOUT1_PAD 2 +#endif +#if (I2S0_DOUT1_LOC == 17) +#define RTE_I2S0_DOUT1_PAD 0 +#endif +#if (I2S0_DOUT1_LOC == 18) +#define RTE_I2S0_DOUT1_PAD 15 +#endif +#if (I2S0_DOUT1_LOC == 19) +#define RTE_I2S0_DOUT1_PAD 19 +#endif +//Pintool data +#endif // I2S0_DIN1 <0=>P0_6 <1=>P0_29 <2=>P0_50 <3=>P0_54 // DIN1 for I2S0 +#ifndef I2S0_DIN1_LOC #define RTE_I2S0_DIN1_PORT_ID 0 #if (RTE_I2S0_DIN1_PORT_ID == 0) @@ -1234,8 +1960,27 @@ #else #error "Invalid I2S0 RTE_I2S0_DIN1 Pin Configuration!" #endif -// FIFO level can have value 1 to 7 -#define I2S0_TX_FIFO_LEVEL (2U) +#else +//Pintool data +#define RTE_I2S0_DIN1_PORT I2S0_DIN1_PORT +#define RTE_I2S0_DIN1_PIN I2S0_DIN1_PIN +#define RTE_I2S0_DIN1_MUX 7 +#if (I2S0_DIN1_LOC == 20) +#define RTE_I2S0_DIN1_PAD 1 +#endif +#if (I2S0_DIN1_LOC == 21) +#define RTE_I2S0_DIN1_PAD 0 +#endif +#if (I2S0_DIN1_LOC == 22) +#define RTE_I2S0_DIN1_PAD 14 +#endif +#if (I2S0_DIN1_LOC == 23) +#define RTE_I2S0_DIN1_PAD 18 +#endif +//Pintool data +#endif +// FIFO level can have value 0 to 7 +#define I2S0_TX_FIFO_LEVEL (0U) #define I2S0_RX_FIFO_LEVEL (2U) // I2S0_TX_RES <0=>12 @@ -1283,13 +2028,14 @@ // -// I2S1 [Driver_I2S1] +// ULP I2S [Driver_I2S1] // Configuration settings for Driver_I2S1 in component ::Drivers:I2S #define RTE_I2S1 1 #define I2S1_IRQHandler IRQ014_Handler -// I2S1_SCLK Pin <0=>P0_3 <1=>P0_7 <2=>P0 +// I2S1_SCLK Pin <0=>P0_3 <1=>P0_7 <2=>P0_8 /*I2S1 PINS*/ +#ifndef ULP_I2S_SCLK_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_I2S1_SCLK_PORT_ID 0 #else @@ -1310,8 +2056,16 @@ #else #error "Invalid I2S1 RTE_I2S1_SCLK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S1_SCLK_PORT ULP_I2S_SCLK_PORT +#define RTE_I2S1_SCLK_PIN ULP_I2S_SCLK_PIN +#define RTE_I2S1_SCLK_MUX 2 +//Pintool data +#endif // I2S1_WSCLK Pin <0=>P0_2 <1=>P0_4 <2=>P0_10 +#ifndef ULP_I2S_WSCLK_LOC #define RTE_I2S1_WSCLK_PORT_ID 0 #if (RTE_I2S1_WSCLK_PORT_ID == 0) #define RTE_I2S1_WSCLK_PORT 0 @@ -1324,8 +2078,16 @@ #else #error "Invalid I2S1 RTE_I2S1_WSCLK Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S1_WSCLK_PORT ULP_I2S_WSCLK_PORT +#define RTE_I2S1_WSCLK_PIN ULP_I2S_WSCLK_PIN +#define RTE_I2S1_WSCLK_MUX 2 +//Pintool data +#endif // I2S1_DOUT0 Pin <0=>P0_1 <1=>P0_5 <2=>P0_11 +#ifndef ULP_I2S_DOUT0_LOC #define RTE_I2S1_DOUT0_PORT_ID 0 #if (RTE_I2S1_DOUT0_PORT_ID == 0) #define RTE_I2S1_DOUT0_PORT 0 @@ -1338,8 +2100,16 @@ #else #error "Invalid I2S1 RTE_I2S1_DOUT0 Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S1_DOUT0_PORT ULP_I2S_DOUT0_PORT +#define RTE_I2S1_DOUT0_PIN ULP_I2S_DOUT0_PIN +#define RTE_I2S1_DOUT0_MUX 2 +//Pintool data +#endif // I2S1_DIN0 Pin <0=>P0_0 <1=>P0_6 <2=>P0_9 <3=>P0_13 +#ifndef ULP_I2S_DIN0_LOC #define RTE_I2S1_DIN0_PORT_ID 1 #if (RTE_I2S1_DIN0_PORT_ID == 0) #define RTE_I2S1_DIN0_PORT 0 @@ -1356,9 +2126,16 @@ #else #error "Invalid I2S1 RTE_I2S1_DIN0 Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2S1_DIN0_PORT ULP_I2S_DIN0_PORT +#define RTE_I2S1_DIN0_PIN ULP_I2S_DIN0_PIN +#define RTE_I2S1_DIN0_MUX 2 +//Pintool data +#endif -// FIFO level can have value 1 to 7 -#define I2S1_TX_FIFO_LEVEL (2U) +// FIFO level can have value 0 to 7 +#define I2S1_TX_FIFO_LEVEL (0U) #define I2S1_RX_FIFO_LEVEL (2U) // I2S1_TX_RES <0=>12 @@ -1413,7 +2190,7 @@ #define I2C0_IRQHandler IRQ042_Handler // I2C0_SCL Pin <0=>P0_7 <1=>P0_65 <2=>P0_66 <3=>P0_75 <4=>P0_32 - +#ifndef I2C0_SCL_LOC #define RTE_I2C0_SCL_PORT_ID 1 #if (RTE_I2C0_SCL_PORT_ID == 0) @@ -1443,9 +2220,32 @@ #else #error "Invalid I2C0 RTE_I2C0_SCL Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2C0_SCL_PORT I2C0_SCL_PORT +#if (I2C0_SCL_LOC == 0) +#define RTE_I2C0_SCL_PIN I2C0_SCL_PIN +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 2 +#define RTE_I2C0_SCL_I2C_REN 7 +#endif +#if (I2C0_SCL_LOC == 1) +#define RTE_I2C0_SCL_PIN (I2C0_SCL_PIN + GPIO_MAX_PIN) +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 23 +#define RTE_I2C0_SCL_I2C_REN 1 +#endif +#if (I2C0_SCL_LOC == 2) +#define RTE_I2C0_SCL_PIN (I2C0_SCL_PIN + GPIO_MAX_PIN) +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 33 +#define RTE_I2C0_SCL_I2C_REN 11 +#endif +//Pintool data +#endif // I2C0_SCL Pin <0=>P0_6 <1=>P0_64 <2=>P0_67 <3=>P0_74 <4=>P0_31 - +#ifndef I2C0_SDA_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_I2C0_SDA_PORT_ID 2 #else @@ -1473,6 +2273,29 @@ #else #error "Invalid I2C0 RTE_I2C0_SDA Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2C0_SDA_PORT I2C0_SDA_PORT +#if (I2C0_SDA_LOC == 3) +#define RTE_I2C0_SDA_PIN I2C0_SDA_PIN +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 1 +#define RTE_I2C0_SDA_I2C_REN 6 +#endif +#if (I2C0_SDA_LOC == 4) +#define RTE_I2C0_SDA_PIN (I2C0_SDA_PIN + GPIO_MAX_PIN) +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 22 +#define RTE_I2C0_SDA_I2C_REN 3 +#endif +#if (I2C0_SDA_LOC == 5) +#define RTE_I2C0_SDA_PIN (I2C0_SDA_PIN + GPIO_MAX_PIN) +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 32 +#define RTE_I2C0_SDA_I2C_REN 10 +#endif +//Pintool data +#endif #define IC_SCL_STUCK_TIMEOUT 20 #define IC_SDA_STUCK_TIMEOUT 20 @@ -1482,7 +2305,7 @@ #define DMA_TX_TL 1 #define DMA_RX_TL 1 #endif -// I2C0 [Driver_I2C0] +// I2C1 [Driver_I2C0] // I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1] // Configuration settings for Driver_I2C1 in component ::Drivers:I2C @@ -1490,6 +2313,7 @@ #define RTE_I2C1 1 #define I2C1_IRQHandler IRQ061_Handler // I2C1_SCL Pin <0=>P0_6 <1=>P0_29 <2=>P0_50 <3=>P0_54 <4=>P0_64 <4=>P0_66 <4=>P0_70 <7=>P0_33 +#ifndef I2C1_SCL_LOC #define RTE_I2C1_SCL_PORT_ID 2 #if (RTE_I2C1_SCL_PORT_ID == 0) @@ -1526,14 +2350,55 @@ #define RTE_I2C1_SCL_PORT 0 #define RTE_I2C1_SCL_PIN 70 #define RTE_I2C1_SCL_MUX 5 -#define RTE_I2C1_SCL_PAD 28 +#define RTE_I2C1_SCL_PAD 29 #define RTE_I2C1_SCL_REN 6 #else #error "Invalid I2C1_SCL Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2C1_SCL_PORT I2C1_SCL_PORT +#if (I2C1_SCL_LOC == 0) +#define RTE_I2C1_SCL_PIN I2C1_SCL_PIN +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 1 +#define RTE_I2C1_SCL_REN 6 +#endif +#if (I2C1_SCL_LOC == 1) +#define RTE_I2C1_SCL_PIN I2C1_SCL_PIN +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 0 //no pad +#define RTE_I2C1_SCL_REN 29 +#endif +#if (I2C1_SCL_LOC == 2) +#define RTE_I2C1_SCL_PIN I2C1_SCL_PIN +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 14 +#define RTE_I2C1_SCL_REN 50 +#endif +#if (I2C1_SCL_LOC == 3) +#define RTE_I2C1_SCL_PIN I2C1_SCL_PIN +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 18 +#define RTE_I2C1_SCL_REN 54 +#endif +#if (I2C1_SCL_LOC == 4) +#define RTE_I2C1_SCL_PIN (I2C1_SCL_PIN + GPIO_MAX_PIN) +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 22 +#define RTE_I2C1_SCL_REN 2 +#endif +#if (I2C1_SCL_LOC == 5) +#define RTE_I2C1_SCL_PIN (I2C1_SCL_PIN + GPIO_MAX_PIN) +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 29 +#define RTE_I2C1_SCL_REN 6 +#endif +//Pintool data +#endif // I2C1_SCL Pin <0=>P0_7 <1=>P0_30 <2=>P0_51 <3=>P0_55 <4=>P0_65 <4=>P0_67 <4=>P0_71 <7=>P0_34 - +#ifndef I2C1_SDA_LOC #define RTE_I2C1_SDA_PORT_ID 2 #if (RTE_I2C1_SDA_PORT_ID == 0) @@ -1581,6 +2446,47 @@ #else #error "Invalid I2C1_SDA Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2C1_SDA_PORT I2C1_SDA_PORT +#if (I2C1_SDA_LOC == 6) +#define RTE_I2C1_SDA_PIN I2C1_SDA_PIN +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 2 +#define RTE_I2C1_SDA_REN 7 +#endif +#if (I2C1_SDA_LOC == 7) +#define RTE_I2C1_SDA_PIN I2C1_SDA_PIN +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 0 //no pad +#define RTE_I2C1_SDA_REN 30 +#endif +#if (I2C1_SDA_LOC == 8) +#define RTE_I2C1_SDA_PIN I2C1_SDA_PIN +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 15 +#define RTE_I2C1_SDA_REN 51 +#endif +#if (I2C1_SDA_LOC == 9) +#define RTE_I2C1_SDA_PIN I2C1_SDA_PIN +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 19 +#define RTE_I2C1_SDA_REN 55 +#endif +#if (I2C1_SDA_LOC == 10) +#define RTE_I2C1_SDA_PIN (I2C1_SDA_PIN + GPIO_MAX_PIN) +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 23 +#define RTE_I2C1_SDA_REN 1 +#endif +#if (I2C1_SDA_LOC == 11) +#define RTE_I2C1_SDA_PIN (I2C1_SDA_PIN + GPIO_MAX_PIN) +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 29 +#define RTE_I2C1_SDA_REN 7 +#endif +//Pintool data +#endif #define IC_SCL_STUCK_TIMEOUT 20 #define IC_SDA_STUCK_TIMEOUT 20 @@ -1593,12 +2499,13 @@ // I2C1 [Driver_I2C1] -// I2C2 (Inter-integrated Circuit Interface 2) [Driver_I2C2] +// ULP I2C (Inter-integrated Circuit Interface 2) [Driver_I2C2] // Configuration settings for Driver_I2C2 in component ::Drivers:I2C #define RTE_I2C2 1 #define I2C2_IRQHandler IRQ013_Handler // I2C2_SCL Pin <0=>P0_1 <1=>P0_5 <2=>P0_7 <3=>P0_8 <4=>P0_13 +#ifndef ULP_I2C_SCL_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_I2C2_SCL_PORT_ID 0 #else @@ -1617,8 +2524,25 @@ #else #error "Invalid I2C2_SCL Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2C2_SCL_PORT ULP_I2C_SCL_PORT +#define RTE_I2C2_SCL_PIN ULP_I2C_SCL_PIN +#define RTE_I2C2_SCL_MUX 4 +#if (ULP_I2C_SCL_LOC == 0) +#define RTE_I2C2_SCL_REN 0 +#elif (ULP_I2C_SCL_LOC == 1) +#define RTE_I2C2_SCL_REN 0 +#elif (ULP_I2C_SCL_LOC == 2) +#define RTE_I2C2_SCL_REN 7 +#elif (ULP_I2C_SCL_LOC == 3) +#define RTE_I2C2_SCL_REN 8 +#endif +//Pintool data +#endif // I2C2_SDA Pin <0=>P0_0 <1=>P0_4 <2=>P0_6 <3=>P0_9 <4=>P0_11 <5=>P0_12 +#ifndef ULP_I2C_SDA_LOC #define RTE_I2C2_SDA_PORT_ID 0 #if (RTE_I2C2_SDA_PORT_ID == 0) #define RTE_I2C2_SDA_PORT 0 @@ -1626,10 +2550,10 @@ #define RTE_I2C2_SDA_MUX 4 #define RTE_I2C2_SDA_REN 6 #elif (RTE_I2C2_SDA_PORT_ID == 1) -#define RTE_I2C2_SDA_PORT 0 -#define RTE_I2C2_SDA_PIN 9 -#define RTE_I2C2_SDA_MUX 4 -#define RTE_I2C2_SDA_I2C_REN 9 +#define RTE_I2C2_SDA_PORT 0 +#define RTE_I2C2_SDA_PIN 9 +#define RTE_I2C2_SDA_MUX 4 +#define RTE_I2C2_SDA_REN 9 #elif (RTE_I2C2_SDA_PORT_ID == 2) #define RTE_I2C2_SDA_PORT 0 #define RTE_I2C2_SDA_PIN 11 @@ -1638,6 +2562,24 @@ #else #error "Invalid I2C2_SDA Pin Configuration!" #endif +#else +//Pintool data +#define RTE_I2C2_SDA_PORT I2C2_SDA_PORT +#define RTE_I2C2_SDA_PIN I2C2_SDA_PIN +#define RTE_I2C2_SDA_MUX 4 +#if (ULP_I2C_SDA_LOC == 4) +#define RTE_I2C2_SDA_REN 0 +#elif (ULP_I2C_SDA_LOC == 5) +#define RTE_I2C2_SDA_REN 0 +#elif (ULP_I2C_SDA_LOC == 6) +#define RTE_I2C2_SDA_REN 6 +#elif (ULP_I2C_SDA_LOC == 7) +#define RTE_I2C2_SDA_REN 9 +#elif (ULP_I2C_SDA_LOC == 8) +#define RTE_I2C2_SDA_REN 11 +#endif +//Pintool data +#endif #define IC_SCL_STUCK_TIMEOUT 20 #define IC_SDA_STUCK_TIMEOUT 20 @@ -1656,6 +2598,7 @@ // GSPI_MASTER_CLK <0=>P0_8 <1=>P0_25 <2=>P0_46 <3=>P0_52 // CLK of GSPI0 +#ifndef GSPI_MASTER_SCK_LOC #define RTE_GSPI_MASTER_CLK_PORT_ID 1 #if (RTE_GSPI_MASTER_CLK_PORT_ID == 0) @@ -1681,12 +2624,31 @@ #else #error "Invalid GSPI0 RTE_GSPI_MASTER_CLK_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_GSPI_MASTER_CLK_PORT GSPI_MASTER_SCK__PORT +#define RTE_GSPI_MASTER_CLK_PIN GSPI_MASTER_SCK__PIN +#define RTE_GSPI_MASTER_CLK_MUX 4 +#if (GSPI_MASTER_SCK_LOC == 0) +#define RTE_GSPI_MASTER_CLK_PAD 3 +#endif +#if (GSPI_MASTER_SCK_LOC == 1) +#define RTE_GSPI_MASTER_CLK_PAD 0 +#endif +#if (GSPI_MASTER_SCK_LOC == 2) +#define RTE_GSPI_MASTER_CLK_PAD 10 +#endif +#if (GSPI_MASTER_SCK_LOC == 3) +#define RTE_GSPI_MASTER_CLK_PAD 16 +#endif +//Pintool data +#endif // GSPI_MASTER_CS0 // <0=>P0_9 <1=>P0_28 <2=>P0_49 <3=>P0_53 // CS0 of GSPI0 // - +#ifndef GSPI_MASTER_CS0_LOC #define RTE_GSPI_MASTER_CS0_PORT_ID 1 #if (RTE_GSPI_MASTER_CS0_PORT_ID == 0) @@ -1716,11 +2678,32 @@ #else #error "Invalid GSPI0 RTE_GSPI_MASTER_CS0_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_GSPI_MASTER_CS0 1 +#define RTE_GSPI_MASTER_CS0_PORT GSPI_MASTER_CS0__PORT +#define RTE_GSPI_MASTER_CS0_PIN GSPI_MASTER_CS0__PIN +#define RTE_GSPI_MASTER_CS0_MUX 4 +#if (GSPI_MASTER_CS0_LOC == 4) +#define RTE_GSPI_MASTER_CS0_PAD 4 +#endif +#if (GSPI_MASTER_CS0_LOC == 5) +#define RTE_GSPI_MASTER_CS0_PAD 0 +#endif +#if (GSPI_MASTER_CS0_LOC == 6) +#define RTE_GSPI_MASTER_CS0_PAD 13 +#endif +#if (GSPI_MASTER_CS0_LOC == 7) +#define RTE_GSPI_MASTER_CS0_PAD 17 +#endif +//Pintool data +#endif // GSPI_MASTER_CS1 // <0=>P0_10 <1=>P0_29 <2=>P0_50 <3=>P0_54 // CS1 of GSPI0 // +#ifndef GSPI_MASTER_CS1_LOC #define RTE_GSPI_MASTER_CS1_PORT_ID 1 #if (RTE_GSPI_MASTER_CS1_PORT_ID == 0) #define RTE_GSPI_MASTER_CS1 1 @@ -1749,11 +2732,32 @@ #else #error "Invalid GSPI0 RTE_GSPI_MASTER_CS1_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_GSPI_MASTER_CS1 1 +#define RTE_GSPI_MASTER_CS1_PORT GSPI_MASTER_CS1__PORT +#define RTE_GSPI_MASTER_CS1_PIN GSPI_MASTER_CS1__PIN +#define RTE_GSPI_MASTER_CS1_MUX 4 +#if (GSPI_MASTER_CS1_LOC == 8) +#define RTE_GSPI_MASTER_CS1_PAD 5 +#endif +#if (GSPI_MASTER_CS1_LOC == 9) +#define RTE_GSPI_MASTER_CS1_PAD 0 +#endif +#if (GSPI_MASTER_CS1_LOC == 10) +#define RTE_GSPI_MASTER_CS1_PAD 14 +#endif +#if (GSPI_MASTER_CS1_LOC == 11) +#define RTE_GSPI_MASTER_CS1_PAD 18 +#endif +//Pintool data +#endif // GSPI_MASTER_CS2 // <0=>P0_15 <1=>P0_30 <2=>P0_51 <3=>P0_55 // CS2 of GSPI0 // +#ifndef GSPI_MASTER_CS2_LOC #define RTE_GSPI_MASTER_CS2_PORT_ID 1 #if (RTE_GSPI_MASTER_CS2_PORT_ID == 0) #define RTE_GSPI_MASTER_CS2 1 @@ -1782,10 +2786,30 @@ #else #error "Invalid GSPI0 RTE_GSPI_MASTER_CS2_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_GSPI_MASTER_CS2 1 +#define RTE_GSPI_MASTER_CS2_PORT GSPI_MASTER_CS2__PORT +#define RTE_GSPI_MASTER_CS2_PIN GSPI_MASTER_CS2__PIN +#define RTE_GSPI_MASTER_CS2_MUX 4 +#if (GSPI_MASTER_CS2_LOC == 12) +#define RTE_GSPI_MASTER_CS2_PAD 8 +#endif +#if (GSPI_MASTER_CS2_LOC == 13) +#define RTE_GSPI_MASTER_CS2_PAD 0 +#endif +#if (GSPI_MASTER_CS2_LOC == 14) +#define RTE_GSPI_MASTER_CS2_PAD 15 +#endif +#if (GSPI_MASTER_CS2_LOC == 15) +#define RTE_GSPI_MASTER_CS2_PAD 19 +#endif +//Pintool data +#endif // GSPI_MASTER_MOSI <0=>P0_12 <1=>P0_27 <2=>P0_48 <3=>P0_57 <4=>P0_6 // MOSI of GSPI0 - +#ifndef GSPI_MASTER_MOSI_LOC #define RTE_GSPI_MASTER_MOSI_PORT_ID 1 #if (RTE_GSPI_MASTER_MOSI_PORT_ID == 0) @@ -1816,10 +2840,36 @@ #else #error "Invalid GSPI0 RTE_GSPI_MASTER_MOSI_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_GSPI_MASTER_MOSI_PORT GSPI_MASTER_MOSI__PORT +#define RTE_GSPI_MASTER_MOSI_PIN GSPI_MASTER_MOSI__PIN +#if (GSPI_MASTER_MOSI_LOC == 16) +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 1 +#endif +#if (GSPI_MASTER_MOSI_LOC == 17) +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 0 +#endif +#if (GSPI_MASTER_MOSI_LOC == 18) +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 12 +#endif +#if (GSPI_MASTER_MOSI_LOC == 19) +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 21 +#endif +#if (GSPI_MASTER_MOSI_LOC == 20) +#define RTE_GSPI_MASTER_MOSI_MUX 12 +#define RTE_GSPI_MASTER_MOSI_PAD 1 +#endif +//Pintool data +#endif // GSPI_MASTER_MISO <0=>P0_11 <1=>P0_26 <2=>P0_47 <3=>P0_56 // MISO of GSPI0 - +#ifndef GSPI_MASTER_MISO_LOC #define RTE_GSPI_MASTER_MISO_PORT_ID 1 #if (RTE_GSPI_MASTER_MISO_PORT_ID == 0) @@ -1845,6 +2895,25 @@ #else #error "Invalid GSPI0 RTE_GSPI_MASTER_MISO_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_GSPI_MASTER_MISO_PORT GSPI_MASTER_MISO__PORT +#define RTE_GSPI_MASTER_MISO_PIN GSPI_MASTER_MISO__PIN +#define RTE_GSPI_MASTER_MISO_MUX 4 +#if (GSPI_MASTER_MISO_LOC == 21) +#define RTE_GSPI_MASTER_MISO_PAD 6 +#endif +#if (GSPI_MASTER_MISO_LOC == 22) +#define RTE_GSPI_MASTER_MISO_PAD 0 +#endif +#if (GSPI_MASTER_MISO_LOC == 23) +#define RTE_GSPI_MASTER_MISO_PAD 11 +#endif +#if (GSPI_MASTER_MISO_LOC == 24) +#define RTE_GSPI_MASTER_MISO_PAD 20 +#endif +//Pintool data +#endif #if defined(HIGH_THROUGHPUT_EN) && (HIGH_THROUGHPUT_EN == ENABLE) #define RTE_GSPI_MASTER_CHNL_UDMA_TX_EN 1 @@ -1880,6 +2949,7 @@ //SCT_IN_0 <0=>GPIO_25 <1=>GPIO_64 <2=>GPIO_68 +#ifndef SCT_IN0_LOC #define RTE_SCT_IN_0_PORT_ID 0 #if (RTE_SCT_IN_0_PORT_ID == 0) @@ -1890,9 +2960,27 @@ #else #error "Invalid RTE_SCT_IN_0_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SCT_IN_0_PORT SCT_IN0_PORT +#if (SCT_IN0_LOC == 0) +#define RTE_SCT_IN_0_PIN SCT_IN0_PIN +#define RTE_SCT_IN_0_MUX 9 +#define RTE_SCT_IN_0_PAD 0 //no pad +#elif (SCT_IN0_LOC == 1) +#define RTE_SCT_IN_0_PIN (SCT_IN0_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_0_MUX 7 +#define RTE_SCT_IN_0_PAD 22 +#elif (SCT_IN0_LOC == 2) +#define RTE_SCT_IN_0_PIN (SCT_IN0_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_0_MUX 9 +#define RTE_SCT_IN_0_PAD 26 +#endif +//Pintool data +#endif //SCT_IN_1 <0=>GPIO_26 <1=>GPIO_65 <2=>GPIO_69 - +#ifndef SCT_IN1_LOC #define RTE_SCT_IN_1_PORT_ID 1 #if (RTE_SCT_IN_1_PORT_ID == 0) @@ -1908,9 +2996,29 @@ #else #error "Invalid RTE_SCT_IN_1_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SCT_IN_1_PORT SCT_IN1_PORT +#if (SCT_IN1_LOC == 3) +#define RTE_SCT_IN_1_PIN SCT_IN1_PIN +#define RTE_SCT_IN_1_MUX 9 +#define RTE_SCT_IN_1_PAD 0 //no pad +#endif +#if (SCT_IN1_LOC == 4) +#define RTE_SCT_IN_1_PIN (SCT_IN1_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_1_MUX 7 +#define RTE_SCT_IN_1_PAD 23 +#endif +#if (SCT_IN1_LOC == 5) +#define RTE_SCT_IN_1_PIN (SCT_IN1_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_1_MUX 9 +#define RTE_SCT_IN_1_PAD 27 +#endif +//Pintool data +#endif //SCT_IN_2 <0=>GPIO_27 <1=>GPIO_66 <2=>GPIO_70 - +#ifndef SCT_IN2_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SCT_IN_2_PORT_ID 0 #else @@ -1935,9 +3043,24 @@ #else #error "Invalid RTE_SCT_IN_0_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SCT_IN_2_PORT SCT_IN2_PORT +#if (SCT_IN2_LOC == 6) +#define RTE_SCT_IN_2_PIN SCT_IN2_PIN +#define RTE_SCT_IN_2_MUX 9 +#define RTE_SCT_IN_2_PAD 0 //no pad +#endif +#if (SCT_IN2_LOC == 7) +#define RTE_SCT_IN_2_PIN (SCT_IN2_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_2_MUX 9 +#define RTE_SCT_IN_2_PAD 28 +#endif +//Pintool data +#endif //SCT_IN_3 <0=>GPIO_28 <1=>GPIO_67 <2=>GPIO_71 - +#ifndef SCT_IN3_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SCT_IN_3_PORT_ID 0 #else @@ -1962,8 +3085,24 @@ #else #error "Invalid RTE_SCT_IN_0_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SCT_IN_3_PORT SCT_IN3_PORT +#if (SCT_IN3_LOC == 8) +#define RTE_SCT_IN_3_PIN SCT_IN3_PIN +#define RTE_SCT_IN_3_MUX 9 +#define RTE_SCT_IN_3_PAD 0 //no pad +#endif +#if (SCT_IN3_LOC == 9) +#define RTE_SCT_IN_3_PIN (SCT_IN3_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_3_MUX 9 +#define RTE_SCT_IN_3_PAD 29 +#endif +//Pintool data +#endif // SCT_OUT_0 <0=>GPIO_29 <1=>GPIO_68 +#ifndef SCT_OUT0_LOC #define RTE_SCT_OUT_0_PORT_ID 0 #if (RTE_SCT_OUT_0_PORT_ID == 0) #define RTE_SCT_OUT_0_PORT 0 @@ -1973,8 +3112,23 @@ #else #error "Invalid RTE_SCT_OUT_0_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SCT_OUT_0_PORT SCT_OUT0_PORT +#if (SCT_OUT0_LOC == 10) +#define RTE_SCT_OUT_0_PIN SCT_OUT0_PIN +#define RTE_SCT_OUT_0_MUX 9 +#define RTE_SCT_OUT_0_PAD 0 //no pad +#elif (SCT_OUT0_LOC == 11) +#define RTE_SCT_OUT_0_PIN (SCT_OUT0_PIN + GPIO_MAX_PIN) +#define RTE_SCT_OUT_0_MUX 7 +#define RTE_SCT_OUT_0_PAD 26 +#endif +//Pintool data +#endif // SCT_OUT_1 <0=>GPIO_30 <1=>GPIO_69 +#ifndef SCT_OUT1_LOC #define RTE_SCT_OUT_1_PORT_ID 0 #if (RTE_SCT_OUT_1_PORT_ID == 0) #define RTE_SCT_OUT_1_PORT 0 @@ -1984,117 +3138,67 @@ #else #error "Invalid RTE_SCT_OUT_1_PIN Pin Configuration!" #endif - -/// SCT_OUT_2 <0=>GPIO_70 <1=>GPIO_8 -#define RTE_SCT_OUT_2_PORT_ID 0 -#if ((RTE_SCT_OUT_2_PORT_ID == 1)) -#error "Invalid RTE_SCT_OUT_2_PIN pin Configuration!" +#else +//Pintool data +#define RTE_SCT_OUT_1_PORT SCT_OUT1_PORT +#if (SCT_OUT1_LOC == 12) +#define RTE_SCT_OUT_1_PIN SCT_OUT1_PIN +#define RTE_SCT_OUT_1_MUX 9 +#define RTE_SCT_OUT_1_PAD 0 //no pad +#elif (SCT_OUT1_LOC == 13) +#define RTE_SCT_OUT_1_PIN (SCT_OUT1_PIN + GPIO_MAX_PIN) +#define RTE_SCT_OUT_1_MUX 7 +#define RTE_SCT_OUT_1_PAD 27 +#endif +//Pintool data #endif -#if (RTE_SCT_OUT_2_PORT_ID == 0) -#define RTE_SCT_OUT_2_PORT 0 -#define RTE_SCT_OUT_2_PIN 70 +//Pintool data +#define RTE_SCT_OUT_2_PORT SCT_OUT2_PORT +#define RTE_SCT_OUT_2_PIN SCT_OUT2_PIN #define RTE_SCT_OUT_2_MUX 7 #define RTE_SCT_OUT_2_PAD 28 -#elif (RTE_SCT_OUT_2_PORT_ID == 1) -#define RTE_SCT_OUT_2_PORT 0 -#define RTE_SCT_OUT_2_PIN 8 -#define RTE_SCT_OUT_2_MUX 12 -#define RTE_SCT_OUT_2_PAD 3 -#else -#error "Invalid RTE_SCT_OUT_2_PIN Pin Configuration!" -#endif -/**/ -//SCT_OUT_3 <0=>GPIO_71 <1=>GPIO_9 -#define RTE_SCT_OUT_3_PORT_ID 0 -#if ((RTE_SCT_OUT_3_PORT_ID == 1)) -#error "Invalid RTE_SCT_OUT_3_PIN pin Configuration!" -#endif +//Pintool data -#if (RTE_SCT_OUT_3_PORT_ID == 0) -#define RTE_SCT_OUT_3_PORT 0 -#define RTE_SCT_OUT_3_PIN 71 +//Pintool data +#define RTE_SCT_OUT_3_PORT SCT_OUT3_PORT +#define RTE_SCT_OUT_3_PIN SCT_OUT3_PIN #define RTE_SCT_OUT_3_MUX 7 #define RTE_SCT_OUT_3_PAD 29 -#elif (RTE_SCT_OUT_3_PORT_ID == 1) -#define RTE_SCT_OUT_3_PORT 0 -#define RTE_SCT_OUT_3_PIN 9 -#define RTE_SCT_OUT_3_MUX 12 -#define RTE_SCT_OUT_3_PAD 4 -#else -#error "Invalid RTE_SCT_OUT_3_PIN Pin Configuration!" -#endif +//Pintool data -//SCT_OUT_4 <0=>GPIO_72 <1=>GPIO_68 - -#define RTE_SCT_OUT_4_PORT_ID 0 -#if ((RTE_SCT_OUT_4_PORT_ID == 1)) -#error "Invalid RTE_SCT_OUT_4_PIN pin Configuration!" -#endif - -#if (RTE_SCT_OUT_4_PORT_ID == 0) -/**/ -#define RTE_SCT_OUT_4_PORT 0 -#define RTE_SCT_OUT_4_PIN 72 +//Pintool data +#define RTE_SCT_OUT_4_PORT SCT_OUT4_PORT +#define RTE_SCT_OUT_4_PIN SCT_OUT4_PIN #define RTE_SCT_OUT_4_MUX 7 #define RTE_SCT_OUT_4_PAD 30 -#else -#error "Invalid RTE_SCT_OUT_4_PIN Pin Configuration!" -#endif -//SCT_OUT_5 <0=>GPIO_73 <1=>GPIO_69 - -#define RTE_SCT_OUT_5_PORT_ID 0 -#if ((RTE_SCT_OUT_5_PORT_ID == 1)) -#error "Invalid RTE_SCT_OUT_5_PIN pin Configuration!" -#endif +//Pintool data -#if (RTE_SCT_OUT_5_PORT_ID == 0) -#define RTE_SCT_OUT_5_PORT 2 -#define RTE_SCT_OUT_5_PIN 73 +//Pintool data +#define RTE_SCT_OUT_5_PORT SCT_OUT5_PORT +#define RTE_SCT_OUT_5_PIN SCT_OUT5_PIN #define RTE_SCT_OUT_5_MUX 7 #define RTE_SCT_OUT_5_PAD 31 -#else -#error "Invalid RTE_SCT_OUT_5_PIN Pin Configuration!" -#endif - -//SCT_OUT_6 <0=>GPIO_74 <1=>GPIO_70 +//Pintool data -#define RTE_SCT_OUT_6_PORT_ID 0 -#if ((RTE_SCT_OUT_6_PORT_ID == 1)) -#error "Invalid RTE_SCT_OUT_6_PIN pin Configuration!" -#endif - -#if (RTE_SCT_OUT_6_PORT_ID == 0) -#define RTE_SCT_OUT_6_PORT 0 -#define RTE_SCT_OUT_6_PIN 74 +//Pintool data +#define RTE_SCT_OUT_6_PORT SCT_OUT6_PORT +#define RTE_SCT_OUT_6_PIN SCT_OUT6_PIN #define RTE_SCT_OUT_6_MUX 7 #define RTE_SCT_OUT_6_PAD 32 -#elif (RTE_SCT_OUT_6_PORT_ID == 1) -#define RTE_SCT_OUT_6_PORT 0 -#define RTE_SCT_OUT_6_PIN 70 -#define RTE_SCT_OUT_6_MUX 13 -#define RTE_SCT_OUT_6_PAD 28 -#else -#error "Invalid RTE_SCT_OUT_6_PIN Pin Configuration!" -#endif - -// SCT_OUT_7 <0=>GPIO_75 <1=>GPIO_71 +//Pintool data -#define RTE_SCT_OUT_7_PORT_ID 0 - -#if (RTE_SCT_OUT_7_PORT_ID == 0) -#define RTE_SCT_OUT_7_PORT 0 -#define RTE_SCT_OUT_7_PIN 75 +//Pintool data +#define RTE_SCT_OUT_7_PORT SCT_OUT7_PORT +#define RTE_SCT_OUT_7_PIN SCT_OUT7_PIN #define RTE_SCT_OUT_7_MUX 7 #define RTE_SCT_OUT_7_PAD 33 -#else -#error "Invalid RTE_SCT_OUT_7_PIN Pin Configuration!" -#endif +//Pintool data // SIO // //<> Serial Input Output //SIO_0 <0=>GPIO_6 <1=>GPIO_25 <2=>GPIO_64 <3=>GPIO_72 - +#ifndef SIO_0_LOC #define RTE_SIO_0_PORT_ID 0 #if (RTE_SIO_0_PORT_ID == 0) @@ -2115,9 +3219,31 @@ #else #error "Invalid RTE_SIO_0_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_0_PORT SIO_SIO0_PORT +#define RTE_SIO_0_MUX 1 +#if (SIO_0_LOC == 0) +#define RTE_SIO_0_PIN SIO_SIO0_PIN +#define RTE_SIO_0_PAD 1 +#endif +#if (SIO_0_LOC == 1) +#define RTE_SIO_0_PIN SIO_SIO0_PIN +#define RTE_SIO_0_PAD 0 +#endif +#if (SIO_0_LOC == 2) +#define RTE_SIO_0_PIN (SIO_SIO0_PIN + GPIO_MAX_PIN) +#define RTE_SIO_0_PAD 22 +#endif +#if (SIO_0_LOC == 3) +#define RTE_SIO_0_PIN (SIO_SIO0_PIN + GPIO_MAX_PIN) +#define RTE_SIO_0_PAD 30 +#endif +//Pintool data +#endif //SIO_1 <0=>GPIO_7 <1=>GPIO_26 <2=>GPIO_65 <3=>GPIO_73 - +#ifndef SIO_1_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SIO_1_PORT_ID 1 #else @@ -2147,9 +3273,31 @@ #else #error "Invalid RTE_SIO_1_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_1_PORT SIO_SIO1_PORT +#define RTE_SIO_1_MUX 1 +#if (SIO_1_LOC == 4) +#define RTE_SIO_1_PIN SIO_SIO1_PIN +#define RTE_SIO_1_PAD 2 +#endif +#if (SIO_1_LOC == 5) +#define RTE_SIO_1_PIN SIO_SIO1_PIN +#define RTE_SIO_1_PAD 0 +#endif +#if (SIO_1_LOC == 6) +#define RTE_SIO_1_PIN (SIO_SIO1_PIN + GPIO_MAX_PIN) +#define RTE_SIO_1_PAD 23 +#endif +#if (SIO_1_LOC == 7) +#define RTE_SIO_1_PIN (SIO_SIO1_PIN + GPIO_MAX_PIN) +#define RTE_SIO_1_PAD 31 +#endif +//Pintool data +#endif // SIO_2 <0=>GPIO_8 <1=>GPIO_27 <2=>GPIO_66 <3=>GPIO_74 - +#ifndef SIO_2_LOC #define RTE_SIO_2_PORT_ID 1 #if (RTE_SIO_2_PORT_ID == 0) @@ -2175,9 +3323,27 @@ #else #error "Invalid RTE_SIO_2_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_2_PORT SIO_SIO2_PORT +#define RTE_SIO_2_MUX 1 +#if (SIO_2_LOC == 8) +#define RTE_SIO_2_PIN SIO_SIO2_PIN +#define RTE_SIO_2_PAD 3 +#endif +#if (SIO_2_LOC == 9) +#define RTE_SIO_2_PIN SIO_SIO2_PIN +#define RTE_SIO_2_PAD 0 +#endif +#if (SIO_2_LOC == 10) +#define RTE_SIO_2_PIN (SIO_SIO2_PIN + GPIO_MAX_PIN) +#define RTE_SIO_2_PAD 32 +#endif +//Pintool data +#endif //SIO_3 <0=>GPIO_9 <1=>GPIO_28 <2=>GPIO_67 <3=>GPIO_75 - +#ifndef SIO_3_LOC #define RTE_SIO_3_PORT_ID 1 #if (RTE_SIO_3_PORT_ID == 0) @@ -2203,8 +3369,27 @@ #else #error "Invalid RTE_SIO_3_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_3_PORT SIO_SIO3_PORT +#define RTE_SIO_3_MUX 1 +#if (SIO_3_LOC == 11) +#define RTE_SIO_3_PIN SIO_SIO3_PIN +#define RTE_SIO_3_PAD 4 +#endif +#if (SIO_3_LOC == 12) +#define RTE_SIO_3_PIN SIO_SIO3_PIN +#define RTE_SIO_3_PAD 0 +#endif +#if (SIO_3_LOC == 13) +#define RTE_SIO_3_PIN (SIO_SIO3_PIN + GPIO_MAX_PIN) +#define RTE_SIO_3_PAD 33 +#endif +//Pintool data +#endif //SIO_4 <0=>GPIO_10 <1=>GPIO_29 <2=>GPIO_68 +#ifndef SIO_4_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SIO_4_PORT_ID 1 #else @@ -2223,8 +3408,27 @@ #else #error "Invalid RTE_SIO_3_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_4_PORT SIO_SIO4_PORT +#define RTE_SIO_4_MUX 1 +#if (SIO_4_LOC == 14) +#define RTE_SIO_4_PAD 5 +#define RTE_SIO_4_PIN SIO_SIO4_PIN +#endif +#if (SIO_4_LOC == 15) +#define RTE_SIO_4_PAD 0 +#define RTE_SIO_4_PIN SIO_SIO4_PIN +#endif +#if (SIO_4_LOC == 16) +#define RTE_SIO_4_PAD 26 +#define RTE_SIO_4_PIN (SIO_SIO4_PIN + GPIO_MAX_PIN) +#endif +//Pintool data +#endif // SIO_5 <0=>GPIO_11 <1=>GPIO_30 <2=>GPIO_69 +#ifndef SIO_5_LOC #define RTE_SIO_5_PORT_ID 0 #if (RTE_SIO_5_PORT_ID == 0) #define RTE_SIO_5_PORT 0 @@ -2239,15 +3443,38 @@ #else #error "Invalid RTE_SIO_5_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_5_PORT SIO_SIO5_PORT +#define RTE_SIO_5_MUX 1 +#if (SIO_5_LOC == 17) +#define RTE_SIO_5_PAD 6 +#define RTE_SIO_5_PIN SIO_SIO5_PIN +#endif +#if (SIO_5_LOC == 18) +#define RTE_SIO_5_PAD 0 +#define RTE_SIO_5_PIN SIO_SIO5_PIN +#endif +#if (SIO_5_LOC == 19) +#define RTE_SIO_5_PAD 0 +#define RTE_SIO_5_PIN (SIO_SIO5_PIN + GPIO_MAX_PIN) +#endif +//Pintool data +#endif // SIO_6 GPIO_70 +#ifndef SIO_6_LOC #define RTE_SIO_6_PORT 0 #define RTE_SIO_6_PIN 70 -#define RTE_SIO_6_MUX 1 -#define RTE_SIO_6_PAD 28 +#else +#define RTE_SIO_6_PORT SIO_SIO6_PORT +#define RTE_SIO_6_PIN (SIO_SIO6_PIN + GPIO_MAX_PIN) +#endif +#define RTE_SIO_6_MUX 1 +#define RTE_SIO_6_PAD 28 // SIO_7 <0=>GPIO_15 <1=>GPIO_71 - +#ifndef SIO_7_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_SIO_7_PORT_ID 1 #else @@ -2267,10 +3494,24 @@ #else #error "Invalid RTE_SIO_7_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_SIO_7_PORT SIO_SIO7_PORT +#define RTE_SIO_7_MUX 1 +#if (SIO_7_LOC == 21) +#define RTE_SIO_7_PIN SIO_SIO7_PIN +#define RTE_SIO_7_PAD 8 +#endif +#if (SIO_7_LOC == 22) +#define RTE_SIO_7_PIN (SIO_SIO7_PIN + GPIO_MAX_PIN) +#define RTE_SIO_7_PAD 29 +#endif +//Pintool data +#endif //<> Pulse Width Modulation //PWM_1H <0=>GPIO_7 <1=>GPIO_64 <2=>GPIO_65 - +#ifndef PWM_1H_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_PWM_1H_PORT_ID 0 #else @@ -2286,13 +3527,28 @@ #define RTE_PWM_1H_PORT 0 #define RTE_PWM_1H_PIN 65 #define RTE_PWM_1H_MUX 8 -#define RTE_PWM_1H_PAD 23 +#define RTE_PWM_1H_PAD 22 #else #error "Invalid RTE_PWM_1H_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_1H_PORT PWM_1H_PORT +#if (PWM_1H_LOC == 0) +#define RTE_PWM_1H_PIN PWM_1H_PIN +#define RTE_PWM_1H_MUX 10 +#define RTE_PWM_1H_PAD 2 +#endif +#if (PWM_1H_LOC == 1) +#define RTE_PWM_1H_PIN (PWM_1H_PIN + GPIO_MAX_PIN) +#define RTE_PWM_1H_MUX 8 +#define RTE_PWM_1H_PAD 22 +#endif +//Pintool data +#endif // PWM_1L <0=>GPIO_6 <1=>GPIO_64 <2=>GPIO_64 - +#ifndef PWM_1L_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_PWM_1L_PORT_ID 0 #else @@ -2307,9 +3563,23 @@ #else #error "Invalid RTE_PWM_1L_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_1L_PORT PWM_1L_PORT +#if (PWM_1L_LOC == 2) +#define RTE_PWM_1L_PIN PWM_1L_PIN +#define RTE_PWM_1L_MUX 10 +#define RTE_PWM_1L_PAD 1 +#elif (PWM_1L_LOC == 3) +#define RTE_PWM_1L_PIN (PWM_1L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_1L_MUX 8 +#define RTE_PWM_1L_PAD 22 +#endif +//Pintool data +#endif //PWM_2H <0=>GPIO_9 <1=>GPIO_67 <2=>GPIO_69 - +#ifndef PWM_2H_LOC #define RTE_PWM_2H_PORT_ID 0 #if ((RTE_PWM_2H_PORT_ID == 2)) #error "Invalid RTE_PWM_2H_PIN pin Configuration!" @@ -2328,9 +3598,24 @@ #else #error "Invalid RTE_PWM_2H_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_2H_PORT PWM_2H_PORT +#if (PWM_2H_LOC == 4) +#define RTE_PWM_2H_PIN PWM_2H_PIN +#define RTE_PWM_2H_MUX 10 +#define RTE_PWM_2H_PAD 4 +#endif +#if (PWM_2H_LOC == 5) +#define RTE_PWM_2H_PIN (PWM_2H_PIN + GPIO_MAX_PIN) +#define RTE_PWM_2H_MUX 12 +#define RTE_PWM_2H_PAD 27 +#endif +//Pintool data +#endif // PWM_2L <0=>GPIO_8 <1=>GPIO_66 <2=>GPIO_68 - +#ifndef PWM_2L_LOC #define RTE_PWM_2L_PORT_ID 0 #if ((RTE_PWM_2L_PORT_ID == 2)) #error "Invalid RTE_PWM_2L_PIN pin Configuration!" @@ -2349,8 +3634,29 @@ #else #error "Invalid RTE_PWM_2L_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_2L_PORT PWM_2L_PORT +#if (PWM_2L_LOC == 6) +#define RTE_PWM_2L_PIN PWM_2L_PIN +#define RTE_PWM_2L_MUX 10 +#define RTE_PWM_2L_PAD 3 +#endif +#if (PWM_2L_LOC == 7) +#define RTE_PWM_2L_PIN (PWM_2L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_2L_MUX 8 +#define RTE_PWM_2L_PAD 24 +#endif +#if (PWM_2L_LOC == 8) +#define RTE_PWM_2L_PIN (PWM_2L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_2L_MUX 12 +#define RTE_PWM_2L_PAD 26 +#endif +//Pintool data +#endif // PWM_3H <0=>GPIO_11 <1=>GPIO_69 +#ifndef PWM_3H_LOC #define RTE_PWM_3H_PORT_ID 0 #if (RTE_PWM_3H_PORT_ID == 0) #define RTE_PWM_3H_PORT 0 @@ -2360,8 +3666,23 @@ #else #error "Invalid RTE_PWM_3H_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_3H_PORT PWM_3H_PORT +#if (PWM_3H_LOC == 9) +#define RTE_PWM_3H_PIN PWM_3H_PIN +#define RTE_PWM_3H_MUX 10 +#define RTE_PWM_3H_PAD 6 +#elif (PWM_3H_LOC == 10) +#define RTE_PWM_3H_PIN (PWM_3H_PIN + GPIO_MAX_PIN) +#define RTE_PWM_3H_MUX 8 +#define RTE_PWM_3H_PAD 27 +#endif +//Pintool data +#endif // PWM_3L <0=>GPIO_10 <1=>GPIO_68 +#ifndef PWM_3L_LOC #define RTE_PWM_3L_PORT_ID 0 #if (RTE_PWM_3L_PORT_ID == 0) @@ -2372,9 +3693,23 @@ #else #error "Invalid RTE_PWM_3L_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_3L_PORT PWM_3L_PORT +#if (PWM_3L_LOC == 11) +#define RTE_PWM_3L_PIN PWM_3L_PIN +#define RTE_PWM_3L_MUX 10 +#define RTE_PWM_3L_PAD 5 +#elif (PWM_3L_LOC == 12) +#define RTE_PWM_3L_PIN (PWM_3L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_3L_MUX 8 +#define RTE_PWM_3L_PAD 26 +#endif +//Pintool data +#endif // PWM_4H <0=>GPIO_15 <1=>GPIO_71 - +#ifndef PWM_4H_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_PWM_4H_PORT_ID 1 #else @@ -2394,9 +3729,17 @@ #else #error "Invalid RTE_PWM_4H_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_4H_PORT PWM_4H_PORT +#define RTE_PWM_4H_PIN (PWM_4H_PIN + GPIO_MAX_PIN) +#define RTE_PWM_4H_MUX 8 +#define RTE_PWM_4H_PAD 29 +//Pintool data +#endif // PWM_4H <0=>GPIO_12 <1=>GPIO_70 - +#ifndef PWM_4L_LOC #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER #define RTE_PWM_4L_PORT_ID 1 #else @@ -2416,8 +3759,24 @@ #else #error "Invalid RTE_PWM_4L_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_4L_PORT PWM_4L_PORT +#if (PWM_4L_LOC == 14) +#define RTE_PWM_4L_PIN PWM_4L_PIN +#define RTE_PWM_4L_MUX 10 +#define RTE_PWM_4L_PAD 7 +#endif +#if (PWM_4L_LOC == 15) +#define RTE_PWM_4L_PIN (PWM_4L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_4L_MUX 8 +#define RTE_PWM_4L_PAD 28 +#endif +//Pintool data +#endif // PWM_FAULTA <0=>GPIO_25 <1=>GPIO_68 <1=>GPIO_73 +#ifndef PWM_FAULTA_LOC #define RTE_PWM_FAULTA_PORT_ID 0 #if (RTE_PWM_FAULTA_PORT_ID == 0) @@ -2433,8 +3792,29 @@ #else #error "Invalid RTE_PWM_FAULTA_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_FAULTA_PORT PWM_FAULTA_PORT +#if (PWM_FAULTA_LOC == 16) +#define RTE_PWM_FAULTA_PIN PWM_FAULTA_PIN +#define RTE_PWM_FAULTA_MUX 10 +#define RTE_PWM_FAULTA_PAD 0 //no pad +#endif +#if (PWM_FAULTA_LOC == 17) +#define RTE_PWM_FAULTA_PIN (PWM_FAULTA_PIN + GPIO_MAX_PIN) +#define RTE_PWM_FAULTA_MUX 10 +#define RTE_PWM_FAULTA_PAD 26 +#endif +#if (PWM_FAULTA_LOC == 18) +#define RTE_PWM_FAULTA_PIN (PWM_FAULTA_PIN + GPIO_MAX_PIN) +#define RTE_PWM_FAULTA_MUX 8 +#define RTE_PWM_FAULTA_PAD 31 +#endif +//Pintool data +#endif // PWM_FAULTB <0=>GPIO_26 <1=>GPIO_69 <1=>GPIO_74 +#ifndef PWM_FAULTB_LOC #define RTE_PWM_FAULTB_PORT_ID 0 #if (RTE_PWM_FAULTB_PORT_ID == 0) @@ -2450,13 +3830,42 @@ #else #error "Invalid RTE_PWM_FAULTB_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_FAULTB_PORT PWM_FAULTB_PORT +#if (PWM_FAULTB_LOC == 19) +#define RTE_PWM_FAULTB_PIN PWM_FAULTB_PIN +#define RTE_PWM_FAULTB_MUX 10 +#define RTE_PWM_FAULTB_PAD 0 //no pad +#endif +#if (PWM_FAULTB_LOC == 20) +#define RTE_PWM_FAULTB_PIN (PWM_FAULTB_PIN + GPIO_MAX_PIN) +#define RTE_PWM_FAULTB_MUX 10 +#define RTE_PWM_FAULTB_PAD 27 +#endif +#if (PWM_FAULTB_LOC == 21) +#define RTE_PWM_FAULTB_PIN (PWM_FAULTB_PIN + GPIO_MAX_PIN) +#define RTE_PWM_FAULTB_MUX 8 +#define RTE_PWM_FAULTB_PAD 32 +#endif +//Pintool data +#endif + //PWM_SLP_EVENT_TRIG GPIO_72 +#ifndef PWM_EVTTRIG_LOC #define RTE_PWM_SLP_EVENT_TRIG_PORT 0 #define RTE_PWM_SLP_EVENT_TRIG_PIN 72 -#define RTE_PWM_SLP_EVENT_TRIG_MUX 8 -#define RTE_PWM_SLP_EVENT_TRIG_PAD 30 +#else +//Pintool data +#define RTE_PWM_SLP_EVENT_TRIG_PORT PWM_SLEEP_EVT_TRIG_PORT +#define RTE_PWM_SLP_EVENT_TRIG_PIN (PWM_SLEEP_EVT_TRIG_PIN + GPIO_MAX_PIN) +//Pintool data +#endif +#define RTE_PWM_SLP_EVENT_TRIG_MUX 8 +#define RTE_PWM_SLP_EVENT_TRIG_PAD 30 //PWM_TMR_EXT_TRIG_1 <0=>GPIO_27 <1=>GPIO_51 <2=>GPIO_70 <3=>GPIO_75 +#ifndef PWM_EXTTRIG1_LOC #define RTE_PWM_TMR_EXT_TRIG_1_PORT_ID 0 #if (RTE_PWM_TMR_EXT_TRIG_1_PORT_ID == 0) @@ -2482,8 +3891,34 @@ #else #error "Invalid RTE_PWM_TMR_EXT_TRIG_1_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_TMR_EXT_TRIG_1_PORT PWM_TMR_EXT_TRIG_1_PORT +#if (PWM_EXTTRIG1_LOC == 22) +#define RTE_PWM_TMR_EXT_TRIG_1_PIN PWM_TMR_EXT_TRIG_1_PIN +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 0 //no pad +#endif +#if (PWM_EXTTRIG1_LOC == 23) +#define RTE_PWM_TMR_EXT_TRIG_1_PIN PWM_TMR_EXT_TRIG_1_PIN +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 15 +#endif +#if (PWM_EXTTRIG1_LOC == 24) +#define RTE_PWM_TMR_EXT_TRIG_1_PIN (PWM_TMR_EXT_TRIG_1_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 28 +#endif +#if (PWM_EXTTRIG1_LOC == 25) +#define RTE_PWM_TMR_EXT_TRIG_1_PIN (PWM_TMR_EXT_TRIG_1_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 33 +#endif +//Pintool data +#endif //PWM_TMR_EXT_TRIG_2 <0=>GPIO_28 <1=>GPIO_54 <2=>GPIO_71 +#ifndef PWM_EXTTRIG2_LOC #define RTE_PWM_TMR_EXT_TRIG_2_PORT_ID 0 #if (RTE_PWM_TMR_EXT_TRIG_2_PORT_ID == 0) @@ -2504,6 +3939,71 @@ #else #error "Invalid RTE_PWM_TMR_EXT_TRIG_2_PIN Pin Configuration!" #endif +#else +//Pintool data +#define RTE_PWM_TMR_EXT_TRIG_2_PORT PWM_TMR_EXT_TRIG_2_PORT +#if (PWM_EXTTRIG2_LOC == 26) +#define RTE_PWM_TMR_EXT_TRIG_2_PIN PWM_TMR_EXT_TRIG_2_PIN +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 0 //no pad +#endif +#if (PWM_EXTTRIG2_LOC == 27) +#define RTE_PWM_TMR_EXT_TRIG_2_PIN PWM_TMR_EXT_TRIG_2_PIN +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 18 +#endif +#if (PWM_EXTTRIG2_LOC == 28) //Combination not available in pin mux +#define RTE_PWM_TMR_EXT_TRIG_2_PIN (PWM_TMR_EXT_TRIG_2_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 29 +#endif +#if (PWM_EXTTRIG2_LOC == 29) +#define RTE_PWM_TMR_EXT_TRIG_2_PIN (PWM_TMR_EXT_TRIG_2_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 29 +#endif +//Pintool data +#endif + +//PWM_TMR_EXT_TRIG_3 +//Pintool data +#define RTE_PWM_TMR_EXT_TRIG_3_PORT PWM_TMR_EXT_TRIG_3_PORT +#if (PWM_EXTTRIG3_LOC == 30) +#define RTE_PWM_TMR_EXT_TRIG_3_PIN PWM_TMR_EXT_TRIG_3_PIN +#define RTE_PWM_TMR_EXT_TRIG_3_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_3_PAD 0 //no pad +#endif +#if (PWM_EXTTRIG3_LOC == 31) +#define RTE_PWM_TMR_EXT_TRIG_3_PIN PWM_TMR_EXT_TRIG_3_PIN +#define RTE_PWM_TMR_EXT_TRIG_3_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_3_PAD 19 +#endif +#if (PWM_EXTTRIG3_LOC == 32) +#define RTE_PWM_TMR_EXT_TRIG_3_PIN (PWM_TMR_EXT_TRIG_3_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_3_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_3_PAD 30 +#endif +//Pintool data + +//PWM_TMR_EXT_TRIG_4 +//Pintool data +#define RTE_PWM_TMR_EXT_TRIG_4_PORT PWM_TMR_EXT_TRIG_4_PORT +#if (PWM_EXTTRIG4_LOC == 33) +#define RTE_PWM_TMR_EXT_TRIG_4_PIN PWM_TMR_EXT_TRIG_4_PIN +#define RTE_PWM_TMR_EXT_TRIG_4_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_4_PAD 0 //no pad +#endif +#if (PWM_EXTTRIG4_LOC == 34) +#define RTE_PWM_TMR_EXT_TRIG_4_PIN PWM_TMR_EXT_TRIG_4_PIN +#define RTE_PWM_TMR_EXT_TRIG_4_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_4_PAD 14 +#endif +#if (PWM_EXTTRIG4_LOC == 35) +#define RTE_PWM_TMR_EXT_TRIG_4_PIN (PWM_TMR_EXT_TRIG_4_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_4_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_4_PAD 31 +#endif +//Pintool data //<> QEI (Quadrature Encode Interface) @@ -2538,9 +4038,9 @@ #define RTE_QEI_DIR_PAD 29 #elif (RTE_QEI_DIR_PORT_ID == 5) #define RTE_QEI_DIR_PORT 0 -#define RTE_QEI_DIR_PIN 75 +#define RTE_QEI_DIR_PIN 73 #define RTE_QEI_DIR_MUX 3 -#define RTE_QEI_DIR_PAD 33 +#define RTE_QEI_DIR_PAD 31 #else #error "Invalid RTE_QEI_DIR_PIN Pin Configuration!" #endif @@ -2654,6 +4154,339 @@ #endif +//ADC START + +#ifndef ADC_P0_LOC +#define RTE_ADC_P0_PORT 0 +#define RTE_ADC_P0_PIN 0 +#else +#define RTE_ADC_P0_PORT ADC_P0_PORT +#define RTE_ADC_P0_PIN ADC_P0_PIN +#endif +#define RTE_ADC_P0_MUX 1 + +#ifndef ADC_N0_LOC +#define RTE_ADC_N0_PORT 0 +#define RTE_ADC_N0_PIN 1 +#else +#define RTE_ADC_N0_PORT ADC_N0_PORT +#define RTE_ADC_N0_PIN ADC_N0_PIN +#endif +#define RTE_ADC_N0_MUX 1 + +#ifndef ADC_P1_LOC +#define RTE_ADC_P1_PORT 0 +#define RTE_ADC_P1_PIN 2 +#else +#define RTE_ADC_P1_PORT ADC_P1_PORT +#define RTE_ADC_P1_PIN ADC_P1_PIN +#endif +#define RTE_ADC_P1_MUX 1 + +#ifndef ADC_N1_LOC +#define RTE_ADC_N1_PORT 0 +#define RTE_ADC_N1_PIN 3 +#else +#define RTE_ADC_N1_PORT ADC_N1_PORT +#define RTE_ADC_N1_PIN ADC_N1_PIN +#endif +#define RTE_ADC_N1_MUX 1 + +#ifndef ADC_P2_LOC +#define RTE_ADC_P2_PORT 0 +#define RTE_ADC_P2_PIN 4 +#else +#define RTE_ADC_P2_PORT ADC_P2_PORT +#define RTE_ADC_P2_PIN ADC_P2_PIN +#endif +#define RTE_ADC_P2_MUX 1 + +#ifndef ADC_N2_LOC +#define RTE_ADC_N2_PORT 0 +#define RTE_ADC_N2_PIN 5 +#else +#define RTE_ADC_N2_PORT ADC_N2_PORT +#define RTE_ADC_N2_PIN ADC_N2_PIN +#endif +#define RTE_ADC_N2_MUX 1 + +#ifndef ADC_P3_LOC +#define RTE_ADC_P3_PORT 0 +#define RTE_ADC_P3_PIN 6 +#else +#define RTE_ADC_P3_PORT ADC_P3_PORT +#define RTE_ADC_P3_PIN ADC_P3_PIN +#endif +#define RTE_ADC_P3_MUX 1 + +#ifndef ADC_N3_LOC +#define RTE_ADC_N3_PORT 0 +#define RTE_ADC_N3_PIN 11 +#else +#define RTE_ADC_N3_PORT ADC_N3_PORT +#define RTE_ADC_N3_PIN ADC_N3_PIN +#endif +#define RTE_ADC_N3_MUX 1 + +#ifndef ADC_P4_LOC +#define RTE_ADC_P4_PORT 0 +#define RTE_ADC_P4_PIN 8 +#else +#define RTE_ADC_P4_PORT ADC_P4_PORT +#define RTE_ADC_P4_PIN ADC_P4_PIN +#endif +#define RTE_ADC_P4_MUX 1 + +#ifndef ADC_N4_LOC +#define RTE_ADC_N4_PORT 0 +#define RTE_ADC_N4_PIN 9 +#else +#define RTE_ADC_N4_PORT ADC_N4_PORT +#define RTE_ADC_N4_PIN ADC_N4_PIN +#endif +#define RTE_ADC_N4_MUX 1 + +#ifndef ADC_P5_LOC +#define RTE_ADC_P5_PORT 0 +#define RTE_ADC_P5_PIN 10 +#else +#define RTE_ADC_P5_PORT ADC_P5_PORT +#define RTE_ADC_P5_PIN ADC_P5_PIN +#endif +#define RTE_ADC_P5_MUX 1 + +#ifndef ADC_N5_LOC +#define RTE_ADC_N5_PORT 0 +#define RTE_ADC_N5_PIN 7 +#else +#define RTE_ADC_N5_PORT ADC_N5_PORT +#define RTE_ADC_N5_PIN ADC_N5_PIN +#endif +#define RTE_ADC_N5_MUX 1 + +#ifndef ADC_P6_LOC +#define RTE_ADC_P6_PORT 0 +#define RTE_ADC_P6_PIN 25 +#else +#define RTE_ADC_P6_PORT ADC_P6_PORT +#define RTE_ADC_P6_PIN ADC_P6_PIN +#endif +#define RTE_ADC_P6_MUX 1 +#define RTE_ADC_P6_PAD 0 + +#ifndef ADC_N6_LOC +#define RTE_ADC_N6_PORT 0 +#define RTE_ADC_N6_PIN 26 +#else +#define RTE_ADC_N6_PORT ADC_N6_PORT +#define RTE_ADC_N6_PIN ADC_N6_PIN +#endif +#define RTE_ADC_N6_MUX 1 +#define RTE_ADC_N6_PAD 0 + +#ifndef ADC_P7_LOC +#define RTE_ADC_P7_PORT 0 +#define RTE_ADC_P7_PIN 27 +#else +#define RTE_ADC_P7_PORT ADC_P7_PORT +#define RTE_ADC_P7_PIN ADC_P7_PIN +#endif +#define RTE_ADC_P7_MUX 1 +#define RTE_ADC_P7_PAD 0 + +#ifndef ADC_N7_LOC +#define RTE_ADC_N7_PORT 0 +#define RTE_ADC_N7_PIN 28 +#else +#define RTE_ADC_N7_PORT ADC_N7_PORT +#define RTE_ADC_N7_PIN ADC_N7_PIN +#endif +#define RTE_ADC_N7_MUX 1 +#define RTE_ADC_N7_PAD 0 + +#ifndef ADC_P8_LOC +#define RTE_ADC_P8_PORT 0 +#define RTE_ADC_P8_PIN 29 +#else +#define RTE_ADC_P8_PORT ADC_P8_PORT +#define RTE_ADC_P8_PIN ADC_P8_PIN +#endif +#define RTE_ADC_P8_MUX 1 +#define RTE_ADC_P8_PAD 0 + +#ifndef ADC_N8_LOC +#define RTE_ADC_N8_PORT 0 +#define RTE_ADC_N8_PIN 30 +#else +#define RTE_ADC_N8_PORT ADC_N8_PORT +#define RTE_ADC_N8_PIN ADC_N8_PIN +#endif +#define RTE_ADC_N8_MUX 1 +#define RTE_ADC_N8_PAD 0 + +#ifndef ADC_P10_LOC +#define RTE_ADC_P10_PORT 0 +#define RTE_ADC_P10_PIN 1 +#else +#define RTE_ADC_P10_PORT ADC_P10_PORT +#define RTE_ADC_P10_PIN ADC_P10_PIN +#endif +#define RTE_ADC_P10_MUX 1 + +#ifndef ADC_P11_LOC +#define RTE_ADC_P11_PORT 0 +#define RTE_ADC_P11_PIN 3 +#else +#define RTE_ADC_P11_PORT ADC_P11_PORT +#define RTE_ADC_P11_PIN ADC_P11_PIN +#endif +#define RTE_ADC_P11_MUX 1 + +#ifndef ADC_P12_LOC +#define RTE_ADC_P12_PORT 0 +#define RTE_ADC_P12_PIN 5 +#else +#define RTE_ADC_P12_PORT ADC_P12_PORT +#define RTE_ADC_P12_PIN ADC_P12_PIN +#endif +#define RTE_ADC_P12_MUX 1 + +#ifndef ADC_P13_LOC +#define RTE_ADC_P13_PORT 0 +#define RTE_ADC_P13_PIN 11 +#else +#define RTE_ADC_P13_PORT ADC_P13_PORT +#define RTE_ADC_P13_PIN ADC_P13_PIN +#endif +#define RTE_ADC_P13_MUX 1 + +#ifndef ADC_P14_LOC +#define RTE_ADC_P14_PORT 0 +#define RTE_ADC_P14_PIN 9 +#else +#define RTE_ADC_P14_PORT ADC_P14_PORT +#define RTE_ADC_P14_PIN ADC_P14_PIN +#endif +#define RTE_ADC_P14_MUX 1 + +#ifndef ADC_P15_LOC +#define RTE_ADC_P15_PORT 0 +#define RTE_ADC_P15_PIN 7 +#else +#define RTE_ADC_P15_PORT ADC_P15_PORT +#define RTE_ADC_P15_PIN ADC_P15_PIN +#endif +#define RTE_ADC_P15_MUX 1 + +#ifndef ADC_P16_LOC +#define RTE_ADC_P16_PORT 0 +#define RTE_ADC_P16_PIN 26 +#else +#define RTE_ADC_P16_PORT ADC_P16_PORT +#define RTE_ADC_P16_PIN ADC_P16_PIN +#endif +#define RTE_ADC_P16_MUX 1 +#define RTE_ADC_P16_PAD 0 + +#ifndef ADC_P17_LOC +#define RTE_ADC_P17_PORT 0 +#define RTE_ADC_P17_PIN 28 +#else +#define RTE_ADC_P17_PORT ADC_P17_PORT +#define RTE_ADC_P17_PIN ADC_P17_PIN +#endif +#define RTE_ADC_P17_MUX 1 +#define RTE_ADC_P17_PAD 0 + +#ifndef ADC_P18_LOC +#define RTE_ADC_P18_PORT 0 +#define RTE_ADC_P18_PIN 30 +#else +#define RTE_ADC_P18_PORT ADC_P18_PORT +#define RTE_ADC_P18_PIN ADC_P18_PIN +#endif +#define RTE_ADC_P18_MUX 1 +#define RTE_ADC_P18_PAD 0 + +//ADC END + +//COMPARATOR START + +#ifndef COMP1_P0_LOC +#define RTE_COMP1_P0_PORT 0 +#define RTE_COMP1_P0_PIN 0 +#else +#define RTE_COMP1_P0_PORT COMP1_P0_PORT +#define RTE_COMP1_P0_PIN COMP1_P0_PIN +#endif +#define RTE_COMP1_P0_MUX 0 + +#ifndef COMP1_N0_LOC +#define RTE_COMP1_N0_PORT 0 +#define RTE_COMP1_N0_PIN 1 +#else +#define RTE_COMP1_N0_PORT COMP1_N0_PORT +#define RTE_COMP1_N0_PIN COMP1_N0_PIN +#endif +#define RTE_COMP1_N0_MUX 0 + +#ifndef COMP1_P1_LOC +#define RTE_COMP1_P1_PORT 0 +#define RTE_COMP1_P1_PIN 5 +#else +#define RTE_COMP1_P1_PORT COMP1_P1_PORT +#define RTE_COMP1_P1_PIN COMP1_P1_PIN +#endif +#define RTE_COMP1_P1_MUX 0 + +#ifndef COMP1_N1_LOC +#define RTE_COMP1_N1_PORT 0 +#define RTE_COMP1_N1_PIN 4 +#else +#define RTE_COMP1_N1_PORT COMP1_N1_PORT +#define RTE_COMP1_N1_PIN COMP1_N1_PIN +#endif +#define RTE_COMP1_N1_MUX 0 + +#ifndef COMP2_P0_LOC +#define RTE_COMP2_P0_PORT 0 +#define RTE_COMP2_P0_PIN 2 +#else +#define RTE_COMP2_P0_PORT COMP2_P0_PORT +#define RTE_COMP2_P0_PIN COMP2_P0_PIN +#endif +#define RTE_COMP2_P0_MUX 0 + +#ifndef COMP2_N0_LOC +#define RTE_COMP2_N0_PORT 0 +#define RTE_COMP2_N0_PIN 3 +#else +#define RTE_COMP2_N0_PORT COMP2_N0_PORT +#define RTE_COMP2_N0_PIN COMP2_N0_PIN +#endif +#define RTE_COMP2_N0_MUX 0 + +#ifndef COMP2_P1_LOC +#define RTE_COMP2_P1_PORT 0 +#define RTE_COMP2_P1_PIN 27 +#else +#define RTE_COMP2_P1_PORT COMP2_P1_PORT +#define RTE_COMP2_P1_PIN COMP2_P1_PIN +#endif +#define RTE_COMP2_P1_MUX 0 +#define RTE_COMP2_P1_PAD 0 + +#ifndef COMP2_N1_LOC +#define RTE_COMP2_N1_PORT 0 +#define RTE_COMP2_N1_PIN 28 +#else +#define RTE_COMP2_N1_PORT COMP2_N1_PORT +#define RTE_COMP2_N1_PIN COMP2_N1_PIN +#endif +#define RTE_COMP2_N1_MUX 0 + +//COMPARATOR END + #define RTE_GPIO_6_PORT 0 #define RTE_GPIO_6_PAD 1 #define RTE_GPIO_6_PIN 6 @@ -3052,5 +4885,15 @@ // ULP GPIO as enable pin for sensors #define SENSOR_ENABLE_GPIO_MAPPED_TO_ULP -#define SENSOR_ENABLE_GPIO_PORT RTE_GPIO_3_PORT -#define SENSOR_ENABLE_GPIO_PIN RTE_GPIO_3_PIN +#define SENSOR_ENABLE_GPIO_PORT RTE_ULP_GPIO_3_PORT +#define SENSOR_ENABLE_GPIO_PIN RTE_ULP_GPIO_3_PIN + +// Memlcd GPIOs +#define RTE_MEMLCD_CS_PIN 4 // Memlcd SPI CS pin +#define RTE_MEMLCD_CS_PORT 0 // Memlcd SPI CS port + +#define RTE_MEMLCD_EXTCOMIN_PIN 5 // Memlcd external communication pin +#define RTE_MEMLCD_EXTCOMIN_PORT 0 // Memlcd external communication port + +#define RTE_MEMLCD_ENABLE_DISPLAY_PIN 0 // Memlcd display enable pin +#define RTE_MEMLCD_ENABLE_DISPLAY_PORT 0 // Memlcd display enable port diff --git a/components/board/silabs/config/brd4343b/pin_config.h b/components/board/silabs/config/brd4343b/pin_config.h new file mode 100644 index 000000000..2bbc8c59c --- /dev/null +++ b/components/board/silabs/config/brd4343b/pin_config.h @@ -0,0 +1,140 @@ +#ifndef PIN_CONFIG_H +#define PIN_CONFIG_H + +// $[USART0] +// [USART0]$ + +// $[UART1] +// [UART1]$ + +// $[ULP_UART] +// [ULP_UART]$ + +// $[I2C0] +// [I2C0]$ + +// $[I2C1] +// [I2C1]$ + +// $[ULP_I2C] +// [ULP_I2C]$ + +// $[SSI_MASTER] +// [SSI_MASTER]$ + +// $[SSI_SLAVE] +// [SSI_SLAVE]$ + +// $[ULP_SPI] +// [ULP_SPI]$ + +// $[GSPI_MASTER] +// [GSPI_MASTER]$ + +// $[I2S0] +// [I2S0]$ + +// $[ULP_I2S] +// [ULP_I2S]$ + +// $[SCT] +// [SCT]$ + +// $[SIO] +// [SIO]$ + +// $[PWM] +// [PWM]$ + +// $[PWM_CH0] +// [PWM_CH0]$ + +// $[PWM_CH1] +// [PWM_CH1]$ + +// $[PWM_CH2] +// [PWM_CH2]$ + +// $[PWM_CH3] +// [PWM_CH3]$ + +// $[ADC_CH1] +// [ADC_CH1]$ + +// $[ADC_CH2] +// [ADC_CH2]$ + +// $[ADC_CH3] +// [ADC_CH3]$ + +// $[ADC_CH4] +// [ADC_CH4]$ + +// $[ADC_CH5] +// [ADC_CH5]$ + +// $[ADC_CH6] +// [ADC_CH6]$ + +// $[ADC_CH7] +// [ADC_CH7]$ + +// $[ADC_CH8] +// [ADC_CH8]$ + +// $[ADC_CH9] +// [ADC_CH9]$ + +// $[ADC_CH10] +// [ADC_CH10]$ + +// $[ADC_CH11] +// [ADC_CH11]$ + +// $[ADC_CH12] +// [ADC_CH12]$ + +// $[ADC_CH13] +// [ADC_CH13]$ + +// $[ADC_CH14] +// [ADC_CH14]$ + +// $[ADC_CH15] +// [ADC_CH15]$ + +// $[ADC_CH16] +// [ADC_CH16]$ + +// $[ADC_CH17] +// [ADC_CH17]$ + +// $[ADC_CH18] +// [ADC_CH18]$ + +// $[ADC_CH19] +// [ADC_CH19]$ + +// $[COMP1] +// [COMP1]$ + +// $[COMP2] +// [COMP2]$ + +// $[DAC0] +// [DAC0]$ + +// $[DAC1] +// [DAC1]$ + +// $[CUSTOM_PIN_NAME] +#ifndef _PORT +#define _PORT 0 +#endif +#ifndef _PIN +#define _PIN 6 +#endif + +// [CUSTOM_PIN_NAME]$ + +#endif // PIN_CONFIG_H diff --git a/components/board/silabs/config/brd4343q/RTE_Device_917.h b/components/board/silabs/config/brd4343q/RTE_Device_917.h new file mode 100644 index 000000000..4023f0e17 --- /dev/null +++ b/components/board/silabs/config/brd4343q/RTE_Device_917.h @@ -0,0 +1,4899 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2016 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgement in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * $Date: 1. December 2016 + * $Revision: V2.4.4 + * + * Project: RTE Device Configuration for Si91x 2.0 B0 BRD4343Q + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H +#include "rsi_ccp_user_config.h" + +#define GPIO_PORT_0 0 // GPIO port 0 +#define ULP_GPIO_MODE_6 6 // ULP GPIO mode 6 +#define HOST_PAD_GPIO_MIN 25 // GPIO host pad minimum pin number +#define HOST_PAD_GPIO_MAX 30 // GPIO host pad maximum pin number +#define GPIO_MAX_PIN 64 // GPIO maximum pin number + +#define BUTTON_0_GPIO_PIN 2 + +#define RTE_BUTTON0_PORT 0 +#define RTE_BUTTON0_NUMBER 0 +#define RTE_BUTTON0_PIN (2U) + +#define RTE_BUTTON1_PORT 0 +#define RTE_BUTTON1_NUMBER 1 +#define RTE_BUTTON1_PIN (11U) +#define RTE_BUTTON1_PAD 6 + +#define RTE_LED0_PORT 4 +#define RTE_LED0_NUMBER 0 +#define RTE_LED0_PIN (0U) + +#define RTE_LED1_PORT 0 +#define RTE_LED1_NUMBER 1 +#define RTE_LED1_PIN (10U) +#define BOARD_ACTIVITY_LED (0U) // LED0 +#define RTE_LED1_PAD 5 + +// USART0 [Driver_USART0] +// Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART +#define RTE_ENABLE_FIFO 1 + +#define RTE_USART0 1 + +#define RTE_USART0_CLK_SRC USART_ULPREFCLK +#define RTE_USART0_CLK_DIV_FACT 1 +#define RTE_USART0_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER + +#define RTE_USART_MODE 0 //!Usart mode macros +#define RTE_CONTINUOUS_CLOCK_MODE 0 + +#define RTE_USART0_LOOPBACK 0 +#define RTE_USART0_DTR_EANBLE 0 + +#define RTE_USART0_DMA_MODE1_EN 0 //!dma mode + +#define RTE_USART0_TX_FIFO_THRESHOLD USART_TRIGGER_TX_EMPTY +#define RTE_USART0_RX_FIFO_THRESHOLD USART_TRIGGER_RX_AEMPTY + +#define RTE_USART0_DMA_TX_LEN_PER_DES 1024 +#define RTE_USART0_DMA_RX_LEN_PER_DES 1024 + +#define RTE_USART0_CHNL_UDMA_TX_CH 25 + +#define RTE_USART0_CHNL_UDMA_RX_CH 24 + +// USART0_CLK <0=>P0_8 <1=>P0_25 <2=>P0_52 <3=>P0_64 +// CLK of USART0 +#ifndef USART0_CLK_LOC +#define RTE_USART0_CLK_PORT_ID 0 + +#if (RTE_USART0_CLK_PORT_ID == 0) +#define RTE_USART0_CLK_PORT 0 +#define RTE_USART0_CLK_PIN 8 +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 3 +#elif (RTE_USART0_CLK_PORT_ID == 1) +#define RTE_USART0_CLK_PORT 0 +#define RTE_USART0_CLK_PIN 25 +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 0 //NO PAD +#elif (RTE_USART0_CLK_PORT_ID == 2) +#define RTE_USART0_CLK_PORT 0 +#define RTE_USART0_CLK_PIN 52 +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 16 +#else +#error "Invalid USART0 RTE_USART0_CLK_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_USART0_CLK_PORT USART0_CLK_PORT +#if (USART0_CLK_LOC == 0) +#define RTE_USART0_CLK_PIN USART0_CLK_PIN +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 3 +#endif +#if (USART0_CLK_LOC == 1) +#define RTE_USART0_CLK_PIN USART0_CLK_PIN +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 0 //NO PAD +#endif +#if (USART0_CLK_LOC == 2) +#define RTE_USART0_CLK_PIN USART0_CLK_PIN +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 16 +#endif +#if (USART0_CLK_LOC == 3) +#define RTE_USART0_CLK_PIN (USART0_CLK_PIN + GPIO_MAX_PIN) +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 22 +#endif +//Pintool data +#endif + +// USART0_TX <0=>P0_15 <1=>P0_30 <2=>P0_54 <3=>P0_68 <4=>P0_71 +// TX for USART0 +#ifndef USART0_TX_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_USART0_TX_PORT_ID 1 +#else +#define RTE_USART0_TX_PORT_ID 0 +#endif + +#if (RTE_USART0_TX_PORT_ID == 0) +#define RTE_USART0_TX_PORT 0 +#define RTE_USART0_TX_PIN 15 +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 8 +#elif (RTE_USART0_TX_PORT_ID == 1) +#define RTE_USART0_TX_PORT 0 +#define RTE_USART0_TX_PIN 30 +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 0 //NO PAD +#elif (RTE_USART0_TX_PORT_ID == 2) +#define RTE_USART0_TX_PORT 0 +#define RTE_USART0_TX_PIN 54 +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 18 +#elif (RTE_USART0_TX_PORT_ID == 3) +#define RTE_USART0_TX_PORT 0 +#define RTE_USART0_TX_PIN 71 +#define RTE_USART0_TX_MUX 4 +#define RTE_USART0_TX_PAD 29 +#else +#error "Invalid USART0 RTE_USART0_TX_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_USART0_TX_PORT USART0_TX_PORT +#if (USART0_TX_LOC == 4) +#define RTE_USART0_TX_PIN USART0_TX_PIN +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 8 +#endif +#if (USART0_TX_LOC == 5) +#define RTE_USART0_TX_PIN USART0_TX_PIN +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 0 //NO PAD +#endif +#if (USART0_TX_LOC == 6) +#define RTE_USART0_TX_PIN USART0_TX_PIN +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 18 +#endif +#if (USART0_TX_LOC == 7) +#define RTE_USART0_TX_PIN (USART0_TX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 26 +#endif +#if (USART0_TX_LOC == 8) +#define RTE_USART0_TX_PIN (USART0_TX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_TX_MUX 4 +#define RTE_USART0_TX_PAD 29 +#endif +//Pintool data +#endif + +// USART0_RX <0=>P0_10 <1=>P0_29 <2=>P0_55 <3=>P0_65 <4=>P0_70 +// RX for USART0 +#ifndef USART0_RX_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_USART0_RX_PORT_ID 1 +#else +#define RTE_USART0_RX_PORT_ID 0 +#endif + +#if (RTE_USART0_RX_PORT_ID == 0) +#define RTE_USART0_RX_PORT 0 +#define RTE_USART0_RX_PIN 10 +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 5 +#elif (RTE_USART0_RX_PORT_ID == 1) +#define RTE_USART0_RX_PORT 0 +#define RTE_USART0_RX_PIN 29 +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 0 //no pad +#elif (RTE_USART0_RX_PORT_ID == 2) +#define RTE_USART0_RX_PORT 0 +#define RTE_USART0_RX_PIN 55 +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 19 +#elif (RTE_USART0_RX_PORT_ID == 3) +#define RTE_USART0_RX_PORT 0 +#define RTE_USART0_RX_PIN 65 +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 23 +#elif (RTE_USART0_RX_PORT_ID == 4) +#define RTE_USART0_RX_PORT 0 +#define RTE_USART0_RX_PIN 70 +#define RTE_USART0_RX_MUX 4 +#define RTE_USART0_RX_PAD 28 +#else +#error "Invalid USART0 RTE_USART0_RX_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_USART0_RX_PORT USART0_RX_PORT +#if (USART0_RX_LOC == 9) +#define RTE_USART0_RX_PIN USART0_RX_PIN +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 5 +#endif +#if (USART0_RX_LOC == 10) +#define RTE_USART0_RX_PIN USART0_RX_PIN +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 0 //no pad +#endif +#if (USART0_RX_LOC == 11) +#define RTE_USART0_RX_PIN USART0_RX_PIN +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 19 +#endif +#if (USART0_RX_LOC == 12) +#define RTE_USART0_RX_PIN (USART0_RX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 23 +#endif +#if (USART0_RX_LOC == 13) +#define RTE_USART0_RX_PIN (USART0_RX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_RX_MUX 4 +#define RTE_USART0_RX_PAD 28 +#endif +//Pintool data +#endif + +// USART0_CTS <0=>P0_6 <1=>P0_26 <2=>P0_56 <3=>P0_70 +// CTS for USART0 +#ifndef USART0_CTS_LOC +#define RTE_USART0_CTS_PORT_ID 0 + +#if (RTE_USART0_CTS_PORT_ID == 0) +#define RTE_USART0_CTS_PORT 0 +#define RTE_USART0_CTS_PIN 6 +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 1 +#elif (RTE_USART0_CTS_PORT_ID == 1) +#define RTE_USART0_CTS_PORT 0 +#define RTE_USART0_CTS_PIN 26 +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 0 //NO PAD +#elif (RTE_USART0_CTS_PORT_ID == 2) +#define RTE_USART0_CTS_PORT 0 +#define RTE_USART0_CTS_PIN 56 +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 20 +#elif (RTE_USART0_CTS_PORT_ID == 3) +#define RTE_USART0_CTS_PORT 0 +#define RTE_USART0_CTS_PIN 70 +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 28 +#else +#error "Invalid USART0 RTE_USART0_CTS_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_USART0_CTS_PORT USART0_CTS_PORT +#if (USART0_CTS_LOC == 14) +#define RTE_USART0_CTS_PIN USART0_CTS_PIN +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 1 +#endif +#if (USART0_CTS_LOC == 15) +#define RTE_USART0_CTS_PIN USART0_CTS_PIN +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 0 //NO PAD +#endif +#if (USART0_CTS_LOC == 16) +#define RTE_USART0_CTS_PIN USART0_CTS_PIN +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 20 +#endif +#if (USART0_CTS_LOC == 17) +#define RTE_USART0_CTS_PIN (USART0_CTS_PIN + GPIO_MAX_PIN) +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 28 +#endif +//Pintool data +#endif + +// USART0_RTS <0=>P0_9 <1=>P0_28 <2=>P0_53 <3=>P0_69 +// RTS for USART0 +#ifndef USART0_RTS_LOC +#define RTE_USART0_RTS_PORT_ID 0 + +#if (RTE_USART0_RTS_PORT_ID == 0) +#define RTE_USART0_RTS_PORT 0 +#define RTE_USART0_RTS_PIN 9 +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 4 +#elif (RTE_USART0_RTS_PORT_ID == 1) +#define RTE_USART0_RTS_PORT 0 +#define RTE_USART0_RTS_PIN 28 +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 0 //NO PAD +#elif (RTE_USART0_RTS_PORT_ID == 2) +#define RTE_USART0_RTS_PORT 0 +#define RTE_USART0_RTS_PIN 53 +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 17 +#else +#error "Invalid USART0 RTE_USART0_RTS_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_USART0_RTS_PORT USART0_RTS_PORT +#if (USART0_RTS_LOC == 18) +#define RTE_USART0_RTS_PIN USART0_RTS_PIN +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 4 +#endif +#if (USART0_RTS_LOC == 19) +#define RTE_USART0_RTS_PIN USART0_RTS_PIN +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 0 //NO PAD +#endif +#if (USART0_RTS_LOC == 20) +#define RTE_USART0_RTS_PIN USART0_RTS_PIN +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 17 +#endif +#if (USART0_RTS_LOC == 21) +#define RTE_USART0_RTS_PIN (USART0_RTS_PIN + GPIO_MAX_PIN) +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 27 +#endif +//Pintool data +#endif + +// USART0_IR_TX <0=>P0_48 <1=>P0_72 +// IR TX for USART0 +#ifndef USART0_IRTX_LOC +#define RTE_IR_TX_PORT_ID 0 +#if ((RTE_IR_TX_PORT_ID == 2)) +#error "Invalid USART0 RTE_USART0_IR_TX_PIN Pin Configuration!" +#endif + +#if (RTE_IR_TX_PORT_ID == 0) +#define RTE_USART0_IR_TX_PORT 0 +#define RTE_USART0_IR_TX_PIN 48 +#define RTE_USART0_IR_TX_MUX 2 +#define RTE_USART0_IR_TX_PAD 12 +#elif (RTE_IR_TX_PORT_ID == 1) +#define RTE_USART0_IR_TX_PORT 0 +#define RTE_USART0_IR_TX_PIN 72 +#define RTE_USART0_IR_TX_MUX 2 +#define RTE_USART0_IR_TX_PAD 30 +#elif (RTE_IR_TX_PORT_ID == 2) +#define RTE_USART0_IR_TX_PORT 0 +#define RTE_USART0_IR_TX_PIN 26 +#define RTE_USART0_IR_TX_MUX 13 +#define RTE_USART0_IR_TX_PAD 0 //No pad +#else +#error "Invalid USART0 RTE_USART0_IR_TX_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_USART0_IR_TX_PORT USART0_IRTX_PORT +#if (USART0_IRTX_LOC == 22) +#define RTE_USART0_IR_TX_PIN USART0_IRTX_PIN +#define RTE_USART0_IR_TX_MUX 13 +#define RTE_USART0_IR_TX_PAD 0 //No pad +#endif +#if (USART0_IRTX_LOC == 23) +#define RTE_USART0_IR_TX_PIN USART0_IRTX_PIN +#define RTE_USART0_IR_TX_MUX 2 +#define RTE_USART0_IR_TX_PAD 12 +#endif +#if (USART0_IRTX_LOC == 24) +#define RTE_USART0_IR_TX_PIN (USART0_IRTX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_IR_TX_MUX 11 +#define RTE_USART0_IR_TX_PAD 23 +#endif +#if (USART0_IRTX_LOC == 25) +#define RTE_USART0_IR_TX_PIN (USART0_IRTX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_IR_TX_MUX 2 +#define RTE_USART0_IR_TX_PAD 30 +#endif +//Pintool data +#endif + +// USART0_IR_RX <0=>P0_47 <1=>P0_71 <2=>P0_64 <3=>P0_25 +// IR RX for USART0 +#ifndef USART0_IRRX_LOC +#define RTE_IR_RX_PORT_ID 0 +#if ((RTE_IR_RX_PORT_ID == 2)) +#error "Invalid USART0 RTE_USART0_IR_RX_PIN Pin Configuration!" +#endif + +#if (RTE_IR_RX_PORT_ID == 0) +#define RTE_USART0_IR_RX_PORT 0 +#define RTE_USART0_IR_RX_PIN 47 +#define RTE_USART0_IR_RX_MUX 2 +#define RTE_USART0_IR_RX_PAD 11 +#elif (RTE_IR_RX_PORT_ID == 1) +#define RTE_USART0_IR_RX_PORT 0 +#define RTE_USART0_IR_RX_PIN 71 +#define RTE_USART0_IR_RX_MUX 2 +#define RTE_USART0_IR_RX_PAD 29 +#elif (RTE_IR_RX_PORT_ID == 2) +#define RTE_USART0_IR_RX_PORT 0 +#define RTE_USART0_IR_RX_PIN 25 +#define RTE_USART0_IR_RX_MUX 13 +#define RTE_USART0_IR_RX_PAD 0 //no pad +#else +#error "Invalid USART0 RTE_USART0_IR_RX_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_USART0_IR_RX_PORT USART0_IRRX_PORT +#if (USART0_IRRX_LOC == 26) +#define RTE_USART0_IR_RX_PIN USART0_IRRX_PIN +#define RTE_USART0_IR_RX_MUX 13 +#define RTE_USART0_IR_RX_PAD 0 //no pad +#endif +#if (USART0_IRRX_LOC == 27) +#define RTE_USART0_IR_RX_PIN USART0_IRRX_PIN +#define RTE_USART0_IR_RX_MUX 2 +#define RTE_USART0_IR_RX_PAD 11 +#endif +#if (USART0_IRRX_LOC == 28) +#define RTE_USART0_IR_RX_PIN (USART0_IRRX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_IR_RX_MUX 11 +#define RTE_USART0_IR_RX_PAD 22 +#endif +#if (USART0_IRRX_LOC == 29) +#define RTE_USART0_IR_RX_PIN (USART0_IRRX_PIN + GPIO_MAX_PIN) +#define RTE_USART0_IR_RX_MUX 2 +#define RTE_USART0_IR_RX_PAD 29 +#endif +//Pintool data +#endif + +// USART0_RI <0=>P0_27 <1=>P0_46 <2=>P0_68 +// RI for USART0 +#ifndef USART0_RI_LOC +#define RTE_RI_PORT_ID 0 + +#if (RTE_RI_PORT_ID == 0) +#define RTE_USART0_RI_PORT 0 +#define RTE_USART0_RI_PIN 27 +#define RTE_USART0_RI_MUX 2 +#define RTE_USART0_RI_PAD 0 //no pad +#elif (RTE_RI_PORT_ID == 1) +#define RTE_USART0_RI_PORT 0 +#define RTE_USART0_RI_PIN 46 +#define RTE_USART0_RI_MUX 2 +#define RTE_USART0_RI_PAD 10 +#else +#error "Invalid USART0 RTE_USART0_RI_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_USART0_RI_PORT USART0_RI_PORT +#if (USART0_RI_LOC == 30) +#define RTE_USART0_RI_PIN USART0_RI_PIN +#define RTE_USART0_RI_MUX 2 +#define RTE_USART0_RI_PAD 0 //no pad +#endif +#if (USART0_RI_LOC == 31) +#define RTE_USART0_RI_PIN USART0_RI_PIN +#define RTE_USART0_RI_MUX 2 +#define RTE_USART0_RI_PAD 10 +#endif +#if (USART0_RI_LOC == 32) +#define RTE_USART0_RI_PIN (USART0_RI_PIN + GPIO_MAX_PIN) +#define RTE_USART0_RI_MUX 11 +#define RTE_USART0_RI_PAD 26 +#endif +//Pintool data +#endif + +// USART0_DSR <0=>P0_11 <1=>P0_57 +// DSR for USART0 +#ifndef USART0_DSR_LOC +#define RTE_DSR_PORT_ID 0 + +#if (RTE_DSR_PORT_ID == 0) +#define RTE_USART0_DSR_PORT 0 +#define RTE_USART0_DSR_PIN 11 +#define RTE_USART0_DSR_MUX 2 +#define RTE_USART0_DSR_PAD 6 +#elif (RTE_DSR_PORT_ID == 1) +#define RTE_USART0_DSR_PORT 0 +#define RTE_USART0_DSR_PIN 57 +#define RTE_USART0_DSR_MUX 2 +#define RTE_USART0_DSR_PAD 21 +#else +#error "Invalid USART0 RTE_USART0_RI_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_USART0_DSR_PORT USART0_DSR_PORT +#define RTE_USART0_DSR_PIN USART0_DSR_PIN +#if (USART0_DSR_LOC == 33) +#define RTE_USART0_DSR_MUX 2 +#define RTE_USART0_DSR_PAD 6 +#endif +#if (USART0_DSR_LOC == 34) +#define RTE_USART0_DSR_MUX 2 +#define RTE_USART0_DSR_PAD 21 +#endif +//Pintool data +#endif + +// USART0_DCD <0=>P0_12 <1=>P0_29 +// DCD for USART0 +#ifndef USART0_DCD_LOC +#define RTE_USART0_DCD_PORT 0 +#define RTE_USART0_DCD_PIN 12 +#else +#define RTE_USART0_DCD_PORT USART0_DCD_PORT +#define RTE_USART0_DCD_PIN USART0_DCD_PIN +#if (USART0_DCD_LOC == 35) +#define RTE_USART0_DCD_MUX 2 +#define RTE_USART0_DCD_PAD 7 +#elif (USART0_DCD_LOC == 36) +#define RTE_USART0_DCD_MUX 12 +#define RTE_USART0_DCD_PAD 0 +#endif +#endif + +// USART0_DTR <0=>P0_7 +// DTR for USART0 +#ifndef USART0_DTR_LOC +#define RTE_USART0_DTR_PORT 0 +#define RTE_USART0_DTR_PIN 7 +#else +#define RTE_USART0_DTR_PORT USART0_DTR_PORT +#define RTE_USART0_DTR_PIN USART0_DTR_PIN +#endif +#define RTE_USART0_DTR_MUX 2 +#define RTE_USART0_DTR_PAD 2 +// + +// UART1 [Driver_UART1] +// Configuration settings for Driver_UART1 in component ::CMSIS Driver:USART +#define RTE_UART1 1 + +#define RTE_UART1_CLK_SRC USART_ULPREFCLK +#define RTE_UART1_CLK_DIV_FACT 1 +#define RTE_UART1_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER + +#define RTE_UART1_LOOPBACK 0 +#define RTE_UART1_DMA_MODE1_EN 0 + +#define RTE_UART1_TX_FIFO_THRESHOLD USART_TRIGGER_TX_EMPTY +#define RTE_UART1_RX_FIFO_THRESHOLD USART_TRIGGER_RX_AEMPTY + +#define RTE_UART1_DMA_TX_LEN_PER_DES 1024 +#define RTE_UART1_DMA_RX_LEN_PER_DES 1024 + +#define RTE_UART1_CHNL_UDMA_TX_CH 27 + +#define RTE_UART1_CHNL_UDMA_RX_CH 26 + +/*UART1 PINS*/ +// UART1_TX <0=>P0_7 <1=>P0_30 <2=>P0_67 <3=>P0_69 <4=>P0_73 <5=>P0_75 <6=>P0_34 +// TX of UART1 +#ifndef UART1_TX_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_UART1_TX_PORT_ID 0 +#else +#define RTE_UART1_TX_PORT_ID 0 + +#if ((RTE_UART1_TX_PORT_ID == 6)) +#error "Invalid UART1 RTE_UART1_TX_PIN Configuration!" +#endif +#endif + +#if (RTE_UART1_TX_PORT_ID == 0) +#define RTE_UART1_TX_PORT 0 +#define RTE_UART1_TX_PIN 7 +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 2 +#elif (RTE_UART1_TX_PORT_ID == 1) +#define RTE_UART1_TX_PORT 0 +#define RTE_UART1_TX_PIN 30 +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 0 //no pad +#elif (RTE_UART1_TX_PORT_ID == 2) +#define RTE_UART1_TX_PORT 0 +#define RTE_UART1_TX_PIN 67 +#define RTE_UART1_TX_MUX 9 +#define RTE_UART1_TX_PAD 25 +#elif (RTE_UART1_TX_PORT_ID == 3) +#define RTE_UART1_TX_PORT 0 +#define RTE_UART1_TX_PIN 73 +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 31 +#elif (RTE_UART1_TX_PORT_ID == 4) +#define RTE_UART1_TX_PORT 0 +#define RTE_UART1_TX_PIN 75 +#define RTE_UART1_TX_MUX 9 +#define RTE_UART1_TX_PAD 33 +#else +#error "Invalid UART1 RTE_UART1_TX_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_UART1_TX_PORT UART1_TX_PORT +#if (UART1_TX_LOC == 0) +#define RTE_UART1_TX_PIN UART1_TX_PIN +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 2 +#endif +#if (UART1_TX_LOC == 1) +#define RTE_UART1_TX_PIN UART1_TX_PIN +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 0 //no pad +#endif +#if (UART1_TX_LOC == 2) +#define RTE_UART1_TX_PIN (UART1_TX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 27 +#endif +#if (UART1_TX_LOC == 3) +#define RTE_UART1_TX_PIN (UART1_TX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 31 +#endif +#if (UART1_TX_LOC == 4) +#define RTE_UART1_TX_PIN (UART1_TX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_TX_MUX 9 +#define RTE_UART1_TX_PAD 33 +#endif +//Pintool data +#endif + +// UART1_RX <0=>P0_6 <1=>P0_29 <2=>P0_66 <3=>P0_68 <4=>P0_72 <5=>P0_74 <6=>P0_33 +// RX of UART1 +#ifndef UART1_RX_LOC +#define RTE_UART1_RX_PORT_ID 0 + +#if (RTE_UART1_RX_PORT_ID == 0) +#define RTE_UART1_RX_PORT 0 +#define RTE_UART1_RX_PIN 6 +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 1 +#elif (RTE_UART1_RX_PORT_ID == 1) +#define RTE_UART1_RX_PORT 0 +#define RTE_UART1_RX_PIN 29 +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 0 //no pad +#elif (RTE_UART1_RX_PORT_ID == 2) +#define RTE_UART1_RX_PORT 0 +#define RTE_UART1_RX_PIN 66 +#define RTE_UART1_RX_MUX 9 +#define RTE_UART1_RX_PAD 24 +#elif (RTE_UART1_RX_PORT_ID == 3) +#define RTE_UART1_RX_PORT 0 +#define RTE_UART1_RX_PIN 72 +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 30 +#elif (RTE_UART1_RX_PORT_ID == 4) +#define RTE_UART1_RX_PORT 0 +#define RTE_UART1_RX_PIN 74 +#define RTE_UART1_RX_MUX 9 +#define RTE_UART1_RX_PAD 32 +#else +#error "Invalid UART1 RTE_UART1_RX_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_UART1_RX_PORT UART1_RX_PORT +#if (UART1_RX_LOC == 5) +#define RTE_UART1_RX_PIN UART1_RX_PIN +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 1 +#endif +#if (UART1_RX_LOC == 6) +#define RTE_UART1_RX_PIN UART1_RX_PIN +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 0 //no pad +#endif +#if (UART1_RX_LOC == 7) +#define RTE_UART1_RX_PIN (UART1_RX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 26 +#endif +#if (UART1_RX_LOC == 8) +#define RTE_UART1_RX_PIN (UART1_RX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 30 +#endif +#if (UART1_RX_LOC == 9) +#define RTE_UART1_RX_PIN (UART1_RX_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RX_MUX 9 +#define RTE_UART1_RX_PAD 32 +#endif +//Pintool data +#endif + +// UART1_CTS <0=>P0_11 <1=>P0_28 <2=>P0_51 <3=>P0_65 <4=>P0_71 <5=>P0_73 <6=>P0_32 +// CTS of UART1 +#ifndef UART1_CTS_LOC +#define RTE_UART1_CTS_PORT_ID 0 + +#if (RTE_UART1_CTS_PORT_ID == 0) +#define RTE_UART1_CTS_PORT 0 +#define RTE_UART1_CTS_PIN 11 +#define RTE_UART1_CTS_MUX 6 +#define RTE_UART1_CTS_PAD 6 +#elif (RTE_UART1_CTS_PORT_ID == 1) +#define RTE_UART1_CTS_PORT 0 +#define RTE_UART1_CTS_PIN 28 +#define RTE_UART1_CTS_MUX 6 +#define RTE_UART1_CTS_PAD 0 //no pad +#elif (RTE_UART1_CTS_PORT_ID == 2) +#define RTE_UART1_CTS_PORT 0 +#define RTE_UART1_CTS_PIN 51 +#define RTE_UART1_CTS_MUX 9 +#define RTE_UART1_CTS_PAD 15 +#elif (RTE_UART1_CTS_PORT_ID == 3) +#define RTE_UART1_CTS_PORT 0 +#define RTE_UART1_CTS_PIN 65 +#define RTE_UART1_CTS_MUX 9 +#define RTE_UART1_CTS_PAD 23 +#elif (RTE_UART1_CTS_PORT_ID == 4) +#define RTE_UART1_CTS_PORT 0 +#define RTE_UART1_CTS_PIN 71 +#define RTE_UART1_CTS_MUX 6 +#define RTE_UART1_CTS_PAD 29 +#else +#error "Invalid UART1 RTE_UART1_CTS_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_UART1_CTS_PORT UART1_CTS_PORT +#if (UART1_CTS_LOC == 10) +#define RTE_UART1_CTS_PIN UART1_CTS_PIN +#define RTE_UART1_CTS_MUX 6 +#define RTE_UART1_CTS_PAD 6 +#endif +#if (UART1_CTS_LOC == 11) +#define RTE_UART1_CTS_PIN UART1_CTS_PIN +#define RTE_UART1_CTS_MUX 6 +#define RTE_UART1_CTS_PAD 0 //no pad +#endif +#if (UART1_CTS_LOC == 12) +#define RTE_UART1_CTS_PIN UART1_CTS_PIN +#define RTE_UART1_CTS_MUX 9 +#define RTE_UART1_CTS_PAD 15 +#endif +#if (UART1_CTS_LOC == 13) +#define RTE_UART1_CTS_PIN (UART1_CTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_CTS_MUX 9 +#define RTE_UART1_CTS_PAD 23 +#endif +#if (UART1_CTS_LOC == 14) +#define RTE_UART1_CTS_PIN (UART1_CTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_CTS_MUX 6 +#define RTE_UART1_CTS_PAD 29 +#endif +#if (UART1_CTS_LOC == 15) +#define RTE_UART1_CTS_PIN (UART1_CTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_CTS_MUX 9 +#define RTE_UART1_CTS_PAD 31 +#endif +//Pintool data +#endif + +// UART1_RTS <0=>P0_10 <1=>P0_27 <2=>P0_50 <3=>P0_64 <4=>P0_70 <5=>P0_72 <6=>P0_31 +// RTS of UART1 +#ifndef UART1_RTS_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_UART1_RTS_PORT_ID 0 +#else +#define RTE_UART1_RTS_PORT_ID 0 +#endif + +#if (RTE_UART1_RTS_PORT_ID == 0) +#define RTE_UART1_RTS_PORT 0 +#define RTE_UART1_RTS_PIN 10 +#define RTE_UART1_RTS_MUX 6 +#define RTE_UART1_RTS_PAD 5 +#elif (RTE_UART1_RTS_PORT_ID == 1) +#define RTE_UART1_RTS_PORT 0 +#define RTE_UART1_RTS_PIN 27 +#define RTE_UART1_RTS_MUX 6 +#define RTE_UART1_RTS_PAD 0 //no pad +#elif (RTE_UART1_RTS_PORT_ID == 2) +#define RTE_UART1_RTS_PORT 0 +#define RTE_UART1_RTS_PIN 50 +#define RTE_UART1_RTS_MUX 9 +#define RTE_UART1_RTS_PAD 14 +#elif (RTE_UART1_RTS_PORT_ID == 3) +#define RTE_UART1_RTS_PORT 0 +#define RTE_UART1_RTS_PIN 70 +#define RTE_UART1_RTS_MUX 6 +#define RTE_UART1_RTS_PAD 28 +#elif (RTE_UART1_RTS_PORT_ID == 4) +#define RTE_UART1_RTS_PORT 0 +#define RTE_UART1_RTS_PIN 72 +#define RTE_UART1_RTS_MUX 9 +#define RTE_UART1_RTS_PAD 30 +#else +#error "Invalid UART1 RTE_UART1_RTS_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_UART1_RTS_PORT UART1_RTS_PORT +#if (UART1_RTS_LOC == 16) +#define RTE_UART1_RTS_PIN UART1_RTS_PIN +#define RTE_UART1_RTS_MUX 6 +#define RTE_UART1_RTS_PAD 5 +#endif +#if (UART1_RTS_LOC == 17) +#define RTE_UART1_RTS_PIN UART1_RTS_PIN +#define RTE_UART1_RTS_MUX 6 +#define RTE_UART1_RTS_PAD 0 //no pad +#endif +#if (UART1_RTS_LOC == 18) +#define RTE_UART1_RTS_PIN UART1_RTS_PIN +#define RTE_UART1_RTS_MUX 9 +#define RTE_UART1_RTS_PAD 14 +#endif +#if (UART1_RTS_LOC == 19) +#define RTE_UART1_RTS_PIN (UART1_RTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RTS_MUX 9 +#define RTE_UART1_RTS_PAD 22 +#endif +#if (UART1_RTS_LOC == 20) +#define RTE_UART1_RTS_PIN (UART1_RTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RTS_MUX 6 +#define RTE_UART1_RTS_PAD 28 +#endif +#if (UART1_RTS_LOC == 21) +#define RTE_UART1_RTS_PIN (UART1_RTS_PIN + GPIO_MAX_PIN) +#define RTE_UART1_RTS_MUX 9 +#define RTE_UART1_RTS_PAD 30 +#endif +//Pintool data +#endif + +// + +// ULP_UART [Driver_ULP_UART] +// Configuration settings for Driver_ULP_UART in component ::CMSIS Driver:USART +#define RTE_ULP_UART 1 + +#define RTE_ULP_UART_CLK_SRC ULP_UART_REF_CLK +#define RTE_ULP_UART_CLK_DIV_FACT 0 +#define RTE_ULP_UART_FRAC_SEL USART_FRACTIONAL_DIVIDER + +#define RTE_ULP_UART_LOOPBACK 0 +#define RTE_ULP_UART_DMA_MODE1_EN 0 + +#define RTE_ULP_UART_TX_FIFO_THRESHOLD USART_TRIGGER_TX_EMPTY +#define RTE_ULP_UART_RX_FIFO_THRESHOLD USART_TRIGGER_RX_AEMPTY + +#define RTE_ULP_UART_DMA_TX_LEN_PER_DES 1024 +#define RTE_ULP_UART_DMA_RX_LEN_PER_DES 1024 + +#define RTE_ULPUART_CHNL_UDMA_TX_CH 1 + +#define RTE_ULPUART_CHNL_UDMA_RX_CH 0 + +/*ULPSS UART PINS*/ +// UART1_TX <0=>P0_3 <1=>P0_7 <2=>P0_11 +// TX of ULPSS UART +#ifndef ULP_UART_TX_LOC +#define RTE_ULP_UART_TX_PORT_ID 1 +#if (RTE_ULP_UART_TX_PORT_ID == 0) +#define RTE_ULP_UART_TX_PORT 0 +#define RTE_ULP_UART_TX_PIN 7 +#define RTE_ULP_UART_TX_MUX 3 +#elif (RTE_ULP_UART_TX_PORT_ID == 1) +#define RTE_ULP_UART_TX_PORT 0 +#define RTE_ULP_UART_TX_PIN 11 +#define RTE_ULP_UART_TX_MUX 3 +#else +#error "Invalid ULPSS UART RTE_ULP_UART_TX_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_ULP_UART_TX_PORT ULP_UART_TX_PORT +#define RTE_ULP_UART_TX_PIN ULP_UART_TX_PIN +#define RTE_ULP_UART_TX_MUX 3 +//Pintool data +#endif + +// UART1_RX <0=>P0_2 <1=>P0_6 <2=>P0_9 +// RX of ULPSS UART +#ifndef ULP_UART_RX_LOC +#define RTE_ULP_UART_RX_PORT_ID 2 +#if (RTE_ULP_UART_RX_PORT_ID == 0) +#define RTE_ULP_UART_RX_PORT 0 +#define RTE_ULP_UART_RX_PIN 2 +#define RTE_ULP_UART_RX_MUX 3 +#elif (RTE_ULP_UART_RX_PORT_ID == 1) +#define RTE_ULP_UART_RX_PORT 0 +#define RTE_ULP_UART_RX_PIN 6 +#define RTE_ULP_UART_RX_MUX 3 +#elif (RTE_ULP_UART_RX_PORT_ID == 2) +#define RTE_ULP_UART_RX_PORT 0 +#define RTE_ULP_UART_RX_PIN 9 +#define RTE_ULP_UART_RX_MUX 3 +#else +#error "Invalid ULPSS UART RTE_ULP_UART_RX_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_ULP_UART_RX_PORT ULP_UART_RX_PORT +#define RTE_ULP_UART_RX_PIN ULP_UART_RX_PIN +#define RTE_ULP_UART_RX_MUX 3 +//Pintool data +#endif + +// UART1_CTS <0=>P0_1 <1=>P0_5 <2=>P0_8 +// CTS of ULPSS UART +#ifndef ULP_UART_CTS_LOC +#define RTE_ULP_UART_CTS_PORT_ID 0 +#if (RTE_ULP_UART_CTS_PORT_ID == 0) +#define RTE_ULP_UART_CTS_PORT 0 +#define RTE_ULP_UART_CTS_PIN 1 +#define RTE_ULP_UART_CTS_MUX 3 +#elif (RTE_ULP_UART_CTS_PORT_ID == 1) +#define RTE_ULP_UART_CTS_PORT 0 +#define RTE_ULP_UART_CTS_PIN 8 +#define RTE_ULP_UART_CTS_MUX 3 +#else +#error "Invalid ULPSS UART RTE_ULP_UART_CTS_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_ULP_UART_CTS_PORT ULP_UART_CTS_PORT +#define RTE_ULP_UART_CTS_PIN ULP_UART_CTS_PIN +#define RTE_ULP_UART_CTS_MUX 3 +//Pintool data +#endif + +// UART1_RTS <0=>P0_0 <1=>P0_4 <2=>P0_10 +// RTS of ULPSS UART +#ifndef ULP_UART_RTS_LOC +#define RTE_ULP_UART_RTS_PORT_ID 0 +#if (RTE_ULP_UART_RTS_PORT_ID == 0) +#define RTE_ULP_UART_RTS_PORT 0 +#define RTE_ULP_UART_RTS_PIN 10 +#else +#error "Invalid ULPSS UART RTE_ULP_UART_RTS_PIN Pin Configuration!" +#endif +#else +#define RTE_ULP_UART_RTS_PORT ULP_UART_RTS_PORT +#define RTE_ULP_UART_RTS_PIN ULP_UART_RTS_PIN +#endif +#define RTE_ULP_UART_RTS_MUX 8 + +// + +// SSI_MASTER (Serial Peripheral Interface 1) [Driver_SSI_MASTER] +// Configuration settings for Driver_SSI_MASTER in component ::CMSIS Driver:SPI +#define RTE_SSI_MASTER 1 + +// SSI_MASTER_MISO Pin <0=>GPIO_12 <1=>GPIO_27 <2=>GPIO_57 +#ifndef SSI_MASTER_DATA1_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_SSI_MASTER_MISO_PORT_ID 1 +#else +#define RTE_SSI_MASTER_MISO_PORT_ID 0 +#endif + +#if (RTE_SSI_MASTER_MISO_PORT_ID == 0) +#define RTE_SSI_MASTER_MISO 1 +#define RTE_SSI_MASTER_MISO_PORT 0 +#define RTE_SSI_MASTER_MISO_PIN 12 +#define RTE_SSI_MASTER_MISO_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_MISO_PADSEL 7 +#elif (RTE_SSI_MASTER_MISO_PORT_ID == 1) +#define RTE_SSI_MASTER_MISO 1 +#define RTE_SSI_MASTER_MISO_PORT 0 +#define RTE_SSI_MASTER_MISO_PIN 27 +#define RTE_SSI_MASTER_MISO_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_MISO_PADSEL 0 //NO PAD +#elif (RTE_SSI_MASTER_MISO_PORT_ID == 2) +#define RTE_SSI_MASTER_MISO 1 +#define RTE_SSI_MASTER_MISO_PORT 0 +#define RTE_SSI_MASTER_MISO_PIN 57 +#define RTE_SSI_MASTER_MISO_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_MISO_PADSEL 21 +#else +#error "Invalid SSI_MASTER_MISO Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SSI_MASTER_MISO 1 +#define RTE_SSI_MASTER_MISO_PORT SSI_MASTER_MISO_DATA1_PORT +#define RTE_SSI_MASTER_MISO_PIN SSI_MASTER_MISO_DATA1_PIN +#define RTE_SSI_MASTER_MISO_MODE EGPIO_PIN_MUX_MODE3 +#if (SSI_MASTER_DATA1_LOC == 3) +#define RTE_SSI_MASTER_MISO_PADSEL 7 +#endif +#if (SSI_MASTER_DATA1_LOC == 4) +#define RTE_SSI_MASTER_MISO_PADSEL 0 //NO PAD +#endif +#if (SSI_MASTER_DATA1_LOC == 5) +#define RTE_SSI_MASTER_MISO_PADSEL 21 +#endif +//Pintool data +#endif + +// SSI_MASTER_MOSI Pin <0=>GPIO_11 <1=>GPIO_26 <2=>GPIO_56 +#ifndef SSI_MASTER_DATA0_LOC +#define RTE_SSI_MASTER_MOSI_PORT_ID 1 + +#if (RTE_SSI_MASTER_MOSI_PORT_ID == 0) +#define RTE_SSI_MASTER_MOSI 1 +#define RTE_SSI_MASTER_MOSI_PORT 0 +#define RTE_SSI_MASTER_MOSI_PIN 11 +#define RTE_SSI_MASTER_MOSI_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_MOSI_PADSEL 6 +#elif (RTE_SSI_MASTER_MOSI_PORT_ID == 1) +#define RTE_SSI_MASTER_MOSI 1 +#define RTE_SSI_MASTER_MOSI_PORT 0 +#define RTE_SSI_MASTER_MOSI_PIN 26 +#define RTE_SSI_MASTER_MOSI_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_MOSI_PADSEL 0 //NO PAD +#elif (RTE_SSI_MASTER_MOSI_PORT_ID == 2) +#define RTE_SSI_MASTER_MOSI 1 +#define RTE_SSI_MASTER_MOSI_PORT 0 +#define RTE_SSI_MASTER_MOSI_PIN 56 +#define RTE_SSI_MASTER_MOSI_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_MOSI_PADSEL 20 +#else +#error "Invalid SSI_MASTER_MOSI Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SSI_MASTER_MOSI 1 +#define RTE_SSI_MASTER_MOSI_PORT SSI_MASTER_MOSI_DATA0_PORT +#define RTE_SSI_MASTER_MOSI_PIN SSI_MASTER_MOSI_DATA0_PIN +#define RTE_SSI_MASTER_MOSI_MODE EGPIO_PIN_MUX_MODE3 +#if (SSI_MASTER_DATA0_LOC == 0) +#define RTE_SSI_MASTER_MOSI_PADSEL 6 +#endif +#if (SSI_MASTER_DATA0_LOC == 1) +#define RTE_SSI_MASTER_MOSI_PADSEL 0 //NO PAD +#endif +#if (SSI_MASTER_DATA0_LOC == 2) +#define RTE_SSI_MASTER_MOSI_PADSEL 20 +#endif +//Pintool data +#endif + +// SSI_MASTER_SCK Pin <0=>GPIO_8 <1=>GPIO_25 <2=>GPIO_52 +#ifndef SSI_MASTER_SCK_LOC +#define RTE_SSI_MASTER_SCK_PORT_ID 1 + +#if (RTE_SSI_MASTER_SCK_PORT_ID == 0) +#define RTE_SSI_MASTER_SCK 1 +#define RTE_SSI_MASTER_SCK_PORT 0 +#define RTE_SSI_MASTER_SCK_PIN 8 +#define RTE_SSI_MASTER_SCK_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_SCK_PADSEL 3 +#elif (RTE_SSI_MASTER_SCK_PORT_ID == 1) +#define RTE_SSI_MASTER_SCK 1 +#define RTE_SSI_MASTER_SCK_PORT 0 +#define RTE_SSI_MASTER_SCK_PIN 25 +#define RTE_SSI_MASTER_SCK_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_SCK_PADSEL 0 //NO PAD +#elif (RTE_SSI_MASTER_SCK_PORT_ID == 2) +#define RTE_SSI_MASTER_SCK 1 +#define RTE_SSI_MASTER_SCK_PORT 0 +#define RTE_SSI_MASTER_SCK_PIN 52 +#define RTE_SSI_MASTER_SCK_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_SCK_PADSEL 16 +#else +#error "Invalid SSI_MASTER_SCK Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SSI_MASTER_SCK 1 +#define RTE_SSI_MASTER_SCK_PORT SSI_MASTER_SCK__PORT +#define RTE_SSI_MASTER_SCK_PIN SSI_MASTER_SCK__PIN +#define RTE_SSI_MASTER_SCK_MODE EGPIO_PIN_MUX_MODE3 +#if (SSI_MASTER_SCK_LOC == 6) +#define RTE_SSI_MASTER_SCK_PADSEL 3 +#endif +#if (SSI_MASTER_SCK_LOC == 7) +#define RTE_SSI_MASTER_SCK_PADSEL 0 //NO PAD +#endif +#if (SSI_MASTER_SCK_LOC == 8) +#define RTE_SSI_MASTER_SCK_PADSEL 16 +#endif +//Pintool data +#endif + +#define M4_SSI_CS0 1 +#define M4_SSI_CS1 0 +#define M4_SSI_CS2 0 +#define M4_SSI_CS3 0 + +// SSI_MASTER_CS Pin <0=>GPIO_9 <1=>GPIO_28 <2=>GPIO_53 <3=>GPIO_10 <4=>GPIO_15 <5=>GPIO_50 <6=>GPIO_51 +#ifndef SSI_MASTER_CS0_LOC +#define RTE_SSI_MASTER_CS0_PORT_ID 1 + +#if (RTE_SSI_MASTER_CS0_PORT_ID == 0) +#define RTE_SSI_MASTER_CS0 M4_SSI_CS0 +#define RTE_SSI_MASTER_CS0_PORT 0 +#define RTE_SSI_MASTER_CS0_PIN 9 +#define RTE_SSI_MASTER_CS0_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS0_PADSEL 4 +#elif (RTE_SSI_MASTER_CS0_PORT_ID == 1) +#define RTE_SSI_MASTER_CS0 M4_SSI_CS0 +#define RTE_SSI_MASTER_CS0_PORT 0 +#define RTE_SSI_MASTER_CS0_PIN 28 +#define RTE_SSI_MASTER_CS0_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS0_PADSEL 0 //NO PAD +#elif (RTE_SSI_MASTER_CS0_PORT_ID == 2) +#define RTE_SSI_MASTER_CS0 M4_SSI_CS0 +#define RTE_SSI_MASTER_CS0_PORT 0 +#define RTE_SSI_MASTER_CS0_PIN 53 +#define RTE_SSI_MASTER_CS0_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS0_PADSEL 17 +#else +#error "Invalid SSI_MASTER_CS0 Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SSI_MASTER_CS0 M4_SSI_CS0 +#define RTE_SSI_MASTER_CS0_PORT SSI_MASTER_CS0__PORT +#define RTE_SSI_MASTER_CS0_PIN SSI_MASTER_CS0__PIN +#define RTE_SSI_MASTER_CS0_MODE EGPIO_PIN_MUX_MODE3 +#if (SSI_MASTER_CS0_LOC == 9) +#define RTE_SSI_MASTER_CS0_PADSEL 4 +#endif +#if (SSI_MASTER_CS0_LOC == 10) +#define RTE_SSI_MASTER_CS0_PADSEL 0 //NO PAD +#endif +#if (SSI_MASTER_CS0_LOC == 11) +#define RTE_SSI_MASTER_CS0_PADSEL 17 +#endif +//Pintool data +#endif + +//CS1 +#ifndef SSI_MASTER_CS1_LOC +#define RTE_SSI_MASTER_CS1_PORT_ID 0 +#if (RTE_SSI_MASTER_CS1_PORT_ID == 0) +#define RTE_SSI_MASTER_CS1_PORT 0 +#define RTE_SSI_MASTER_CS1_PIN 10 +#else +#error "Invalid SSI_MASTER_CS1 Pin Configuration!" +#endif +#else +#define RTE_SSI_MASTER_CS1_PORT SSI_MASTER_CS1__PORT +#define RTE_SSI_MASTER_CS1_PIN SSI_MASTER_CS1__PIN +#endif +#define RTE_SSI_MASTER_CS1 M4_SSI_CS1 +#define RTE_SSI_MASTER_CS1_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS1_PADSEL 5 + +//CS2 +#ifndef SSI_MASTER_CS2_LOC +#define RTE_SSI_MASTER_CS2_PORT_ID 1 +#if (RTE_SSI_MASTER_CS2_PORT_ID == 0) +#define RTE_SSI_MASTER_CS2 M4_SSI_CS2 +#define RTE_SSI_MASTER_CS2_PORT 0 +#define RTE_SSI_MASTER_CS2_PIN 15 +#define RTE_SSI_MASTER_CS2_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS2_PADSEL 8 +#elif (RTE_SSI_MASTER_CS2_PORT_ID == 1) +#define RTE_SSI_MASTER_CS2 M4_SSI_CS2 +#define RTE_SSI_MASTER_CS2_PORT 0 +#define RTE_SSI_MASTER_CS2_PIN 50 +#define RTE_SSI_MASTER_CS2_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS2_PADSEL 14 +#else +#error "Invalid SSI_MASTER_CS2 Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SSI_MASTER_CS2 M4_SSI_CS2 +#define RTE_SSI_MASTER_CS2_PORT SSI_MASTER_CS2__PORT +#define RTE_SSI_MASTER_CS2_PIN SSI_MASTER_CS2__PIN +#define RTE_SSI_MASTER_CS2_MODE EGPIO_PIN_MUX_MODE3 +#if (SSI_MASTER_CS2_LOC == 13) +#define RTE_SSI_MASTER_CS2_PADSEL 8 +#endif +#if (SSI_MASTER_CS2_LOC == 14) +#define RTE_SSI_MASTER_CS2_PADSEL 14 +#endif +//Pintool data +#endif + +//CS3 +#ifndef SSI_MASTER_CS3_LOC +#define RTE_SSI_MASTER_CS3_PORT_ID 0 +#if (RTE_SSI_MASTER_CS3_PORT_ID == 0) +#define RTE_SSI_MASTER_CS3_PORT 0 +#define RTE_SSI_MASTER_CS3_PIN 51 +#else +#error "Invalid SSI_MASTER_CS3 Pin Configuration!" +#endif +#else +#define RTE_SSI_MASTER_CS3_PORT SSI_MASTER_CS3__PORT +#define RTE_SSI_MASTER_CS3_PIN SSI_MASTER_CS3__PIN +#endif +#define RTE_SSI_MASTER_CS3 M4_SSI_CS3 +#define RTE_SSI_MASTER_CS3_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS3_PADSEL 15 + +// DMA Rx +// Channel <28=>28 +// Selects DMA Channel (only Channel 28 can be used) +// +#define RTE_SSI_MASTER_UDMA_RX_CH 28 + +// DMA Tx +// Channel <29=>29 +// Selects DMA Channel (only Channel 29 can be used) +// +#define RTE_SSI_MASTER_UDMA_TX_CH 29 +// + +// SSI_SLAVE (Serial Peripheral Interface 2) [Driver_SSI_SLAVE] +// Configuration settings for Driver_SSI_SLAVE in component ::CMSIS Driver:SPI +#define RTE_SSI_SLAVE 1 + +#define RTE_SSI_SLAVE_INPUT_CLOCK SSISLAVE_CLK + +// SSI_SLAVE_MISO Pin <0=>Not Used <1=>GPIO_11 <2=>GPIO_28 <3=>GPIO_49 <4=>GPIO_57 +#ifndef SSI_SLAVE_MISO_LOC +#define RTE_SSI_SLAVE_MISO_PORT_ID 2 + +#if (RTE_SSI_SLAVE_MISO_PORT_ID == 0) +#define RTE_SSI_SLAVE_MISO 0 +#elif (RTE_SSI_SLAVE_MISO_PORT_ID == 1) +#define RTE_SSI_SLAVE_MISO 1 +#define RTE_SSI_SLAVE_MISO_PORT 0 +#define RTE_SSI_SLAVE_MISO_PIN 11 +#define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_MISO_PADSEL 6 +#elif (RTE_SSI_SLAVE_MISO_PORT_ID == 2) +#define RTE_SSI_SLAVE_MISO 1 +#define RTE_SSI_SLAVE_MISO_PORT 0 +#define RTE_SSI_SLAVE_MISO_PIN 28 +#define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_MISO_PADSEL 0 //no pad +#elif (RTE_SSI_SLAVE_MISO_PORT_ID == 3) +#define RTE_SSI_SLAVE_MISO 1 +#define RTE_SSI_SLAVE_MISO_PORT 0 +#define RTE_SSI_SLAVE_MISO_PIN 49 +#define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_MISO_PADSEL 13 +#elif (RTE_SSI_SLAVE_MISO_PORT_ID == 4) +#define RTE_SSI_SLAVE_MISO 1 +#define RTE_SSI_SLAVE_MISO_PORT 0 +#define RTE_SSI_SLAVE_MISO_PIN 57 +#define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_MISO_PADSEL 21 +#else +#error "Invalid SSI_SLAVE_MISO Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SSI_SLAVE_MISO 1 +#define RTE_SSI_SLAVE_MISO_PORT SSI_SLAVE_MISO__PORT +#define RTE_SSI_SLAVE_MISO_PIN SSI_SLAVE_MISO__PIN +#define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8 +#if (SSI_SLAVE_MISO_LOC == 5) +#define RTE_SSI_SLAVE_MISO_PADSEL 6 +#endif +#if (SSI_SLAVE_MISO_LOC == 6) +#define RTE_SSI_SLAVE_MISO_PADSEL 0 //no pad +#endif +#if (SSI_SLAVE_MISO_LOC == 7) +#define RTE_SSI_SLAVE_MISO_PADSEL 13 +#endif +#if (SSI_SLAVE_MISO_LOC == 8) +#define RTE_SSI_SLAVE_MISO_PADSEL 21 +#endif +//Pintool data +#endif + +// SSI_SLAVE_MOSI Pin <0=>Not Used <1=>GPIO_10 <2=>GPIO_27 <3=>GPIO_48 <4=>GPIO_56 +#ifndef SSI_SLAVE_MOSI_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_SSI_SLAVE_MOSI_PORT_ID 2 +#else +#define RTE_SSI_SLAVE_MOSI_PORT_ID 1 +#endif + +#if (RTE_SSI_SLAVE_MOSI_PORT_ID == 0) +#define RTE_SSI_SLAVE_MOSI 0 +#elif (RTE_SSI_SLAVE_MOSI_PORT_ID == 1) +#define RTE_SSI_SLAVE_MOSI 1 +#define RTE_SSI_SLAVE_MOSI_PORT 0 +#define RTE_SSI_SLAVE_MOSI_PIN 10 +#define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_MOSI_PADSEL 5 +#elif (RTE_SSI_SLAVE_MOSI_PORT_ID == 2) +#define RTE_SSI_SLAVE_MOSI 1 +#define RTE_SSI_SLAVE_MOSI_PORT 0 +#define RTE_SSI_SLAVE_MOSI_PIN 27 +#define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_MOSI_PADSEL 0 //no pad +#elif (RTE_SSI_SLAVE_MOSI_PORT_ID == 3) +#define RTE_SSI_SLAVE_MOSI 1 +#define RTE_SSI_SLAVE_MOSI_PORT 0 +#define RTE_SSI_SLAVE_MOSI_PIN 48 +#define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_MOSI_PADSEL 12 +#elif (RTE_SSI_SLAVE_MOSI_PORT_ID == 4) +#define RTE_SSI_SLAVE_MOSI 1 +#define RTE_SSI_SLAVE_MOSI_PORT 0 +#define RTE_SSI_SLAVE_MOSI_PIN 56 +#define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_MOSI_PADSEL 20 +#else +#error "Invalid SSI_SLAVE_MOSI Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SSI_SLAVE_MOSI 1 +#define RTE_SSI_SLAVE_MOSI_PORT SSI_SLAVE_MOSI__PORT +#define RTE_SSI_SLAVE_MOSI_PIN SSI_SLAVE_MOSI__PIN +#define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8 +#if (SSI_SLAVE_MOSI_LOC == 1) +#define RTE_SSI_SLAVE_MOSI_PADSEL 5 +#endif +#if (SSI_SLAVE_MOSI_LOC == 2) +#define RTE_SSI_SLAVE_MOSI_PADSEL 0 //no pad +#endif +#if (SSI_SLAVE_MOSI_LOC == 3) +#define RTE_SSI_SLAVE_MOSI_PADSEL 12 +#endif +#if (SSI_SLAVE_MOSI_LOC == 4) +#define RTE_SSI_SLAVE_MOSI_PADSEL 20 +#endif +//Pintool data +#endif + +// SSI_SLAVE_SCK Pin <0=>Not Used <1=>GPIO_8 <2=>GPIO_26 <3=>GPIO_47 <4=>GPIO_52 +#ifndef SSI_SLAVE_SCK_LOC +#define RTE_SSI_SLAVE_SCK_PORT_ID 2 + +#if (RTE_SSI_SLAVE_SCK_PORT_ID == 0) +#define RTE_SSI_SLAVE_SCK 0 +#elif (RTE_SSI_SLAVE_SCK_PORT_ID == 1) +#define RTE_SSI_SLAVE_SCK 1 +#define RTE_SSI_SLAVE_SCK_PORT 0 +#define RTE_SSI_SLAVE_SCK_PIN 8 +#define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_SCK_PADSEL 3 +#elif (RTE_SSI_SLAVE_SCK_PORT_ID == 2) +#define RTE_SSI_SLAVE_SCK 1 +#define RTE_SSI_SLAVE_SCK_PORT 0 +#define RTE_SSI_SLAVE_SCK_PIN 26 +#define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_SCK_PADSEL 0 //no pad +#elif (RTE_SSI_SLAVE_SCK_PORT_ID == 3) +#define RTE_SSI_SLAVE_SCK 1 +#define RTE_SSI_SLAVE_SCK_PORT 0 +#define RTE_SSI_SLAVE_SCK_PIN 47 +#define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_SCK_PADSEL 11 +#elif (RTE_SSI_SLAVE_SCK_PORT_ID == 4) +#define RTE_SSI_SLAVE_SCK 1 +#define RTE_SSI_SLAVE_SCK_PORT 0 +#define RTE_SSI_SLAVE_SCK_PIN 52 +#define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_SCK_PADSEL 16 +#else +#error "Invalid SSI_SLAVE_SCK Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SSI_SLAVE_SCK 1 +#define RTE_SSI_SLAVE_SCK_PORT SSI_SLAVE_SCK__PORT +#define RTE_SSI_SLAVE_SCK_PIN SSI_SLAVE_SCK__PIN +#define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8 +#if (SSI_SLAVE_SCK_LOC == 9) +#define RTE_SSI_SLAVE_SCK_PADSEL 3 +#endif +#if (SSI_SLAVE_SCK_LOC == 10) +#define RTE_SSI_SLAVE_SCK_PADSEL 0 //no pad +#endif +#if (SSI_SLAVE_SCK_LOC == 11) +#define RTE_SSI_SLAVE_SCK_PADSEL 11 +#endif +#if (SSI_SLAVE_SCK_LOC == 12) +#define RTE_SSI_SLAVE_SCK_PADSEL 16 +#endif +//Pintool data +#endif + +// SSI_SLAVE_CS Pin <0=>Not Used <1=>GPIO_9 <2=>GPIO_25 <3=>GPIO_46 <4=>GPIO_53 +#ifndef SSI_SLAVE_CS0_LOC +#define RTE_SSI_SLAVE_CS_PORT_ID 1 + +#if (RTE_SSI_SLAVE_CS_PORT_ID == 0) +#define RTE_SSI_SLAVE_CS 0 +#elif (RTE_SSI_SLAVE_CS_PORT_ID == 1) +#define RTE_SSI_SLAVE_CS 1 +#define RTE_SSI_SLAVE_CS_PORT 0 +#define RTE_SSI_SLAVE_CS_PIN 9 +#define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_CS_PADSEL 4 +#elif (RTE_SSI_SLAVE_CS_PORT_ID == 2) +#define RTE_SSI_SLAVE_CS 1 +#define RTE_SSI_SLAVE_CS_PORT 0 +#define RTE_SSI_SLAVE_CS_PIN 25 +#define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_CS_PADSEL 0 //no pad +#elif (RTE_SSI_SLAVE_CS_PORT_ID == 3) +#define RTE_SSI_SLAVE_CS 1 +#define RTE_SSI_SLAVE_CS_PORT 0 +#define RTE_SSI_SLAVE_CS_PIN 46 +#define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_CS_PADSEL 10 +#elif (RTE_SSI_SLAVE_CS_PORT_ID == 4) +#define RTE_SSI_SLAVE_CS 1 +#define RTE_SSI_SLAVE_CS_PORT 0 +#define RTE_SSI_SLAVE_CS_PIN 53 +#define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_CS_PADSEL 17 +#else +#error "Invalid SSI_SLAVE_CS Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SSI_SLAVE_CS 1 +#define RTE_SSI_SLAVE_CS_PORT SSI_SLAVE_CS0__PORT +#define RTE_SSI_SLAVE_CS_PIN SSI_SLAVE_CS0__PIN +#define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8 +#if (SSI_SLAVE_CS0_LOC == 13) +#define RTE_SSI_SLAVE_CS_PADSEL 4 +#endif +#if (SSI_SLAVE_CS0_LOC == 14) +#define RTE_SSI_SLAVE_CS_PADSEL 0 //no pad +#endif +#if (SSI_SLAVE_CS0_LOC == 15) +#define RTE_SSI_SLAVE_CS_PADSEL 10 +#endif +#if (SSI_SLAVE_CS0_LOC == 16) +#define RTE_SSI_SLAVE_CS_PADSEL 17 +#endif +//Pintool data +#endif + +// DMA Rx +// Channel <22=>22 +// Selects DMA Channel (only Channel 22 can be used) +// +#define RTE_SSI_SLAVE_UDMA_RX_CH 22 +#define RTE_SSI_SLAVE_DMA_RX_LEN_PER_DES 1024 + +// DMA Tx +// Channel <23=>23 +// Selects DMA Channel (only Channel 23 can be used) +// +#define RTE_SSI_SLAVE_UDMA_TX_CH 23 +#define RTE_SSI_SLAVE_DMA_TX_LEN_PER_DES 1024 + +// + +// ULP SPI Peripheral (Serial Peripheral Interface 3) [Driver_SSI_ULP_MASTER] +// Configuration settings for Driver_SSI_ULP_MASTER in component ::CMSIS Driver:SPI +#define RTE_SSI_ULP_MASTER 1 + +// Enable multiple CSN lines +#define ULP_SSI_CS0 1 +#define ULP_SSI_CS1 0 +#define ULP_SSI_CS2 0 + +// SSI_ULP_MASTER_MISO Pin <0=>Not Used <1=>ULP_GPIO_2 <2=>ULP_GPIO_9 +#ifndef ULP_SPI_MISO_LOC +#define RTE_SSI_ULP_MASTER_MISO_PORT_ID 0 +#if (RTE_SSI_ULP_MASTER_MISO_PORT_ID == 0) +#define RTE_SSI_ULP_MASTER_MISO 1 +#define RTE_SSI_ULP_MASTER_MISO_PORT 0 +#define RTE_SSI_ULP_MASTER_MISO_PIN 2 +#define RTE_SSI_ULP_MASTER_MISO_MODE 1 +#elif (RTE_SSI_ULP_MASTER_MISO_PORT_ID == 1) +#define RTE_SSI_ULP_MASTER_MISO 1 +#define RTE_SSI_ULP_MASTER_MISO_PORT 0 +#define RTE_SSI_ULP_MASTER_MISO_PIN 9 +#define RTE_SSI_ULP_MASTER_MISO_MODE 1 +#else +#error "Invalid SSI_ULP_MISO Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SSI_ULP_MASTER_MISO 1 +#define RTE_SSI_ULP_MASTER_MISO_PORT ULP_SPI_MISO__PORT +#define RTE_SSI_ULP_MASTER_MISO_PIN ULP_SPI_MISO__PIN +#define RTE_SSI_ULP_MASTER_MISO_MODE 1 +//Pintool data +#endif + +// SSI_ULP_MASTER_MOSI Pin <0=>Not Used <1=>ULP_GPIO_1 <2=>ULP_GPIO_11 +#ifndef ULP_SPI_MOSI_LOC +#define RTE_SSI_ULP_MASTER_MOSI_PORT_ID 0 +#if (RTE_SSI_ULP_MASTER_MOSI_PORT_ID == 0) +#define RTE_SSI_ULP_MASTER_MOSI 1 +#define RTE_SSI_ULP_MASTER_MOSI_PORT 0 +#define RTE_SSI_ULP_MASTER_MOSI_PIN 1 +#define RTE_SSI_ULP_MASTER_MOSI_MODE 1 +#elif (RTE_SSI_ULP_MASTER_MOSI_PORT_ID == 1) +#define RTE_SSI_ULP_MASTER_MOSI 1 +#define RTE_SSI_ULP_MASTER_MOSI_PORT 0 +#define RTE_SSI_ULP_MASTER_MOSI_PIN 11 +#define RTE_SSI_ULP_MASTER_MOSI_MODE 1 +#else +#error "Invalid SSI_ULP_MOSI Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SSI_ULP_MASTER_MOSI 1 +#define RTE_SSI_ULP_MASTER_MOSI_PORT ULP_SPI_MOSI__PORT +#define RTE_SSI_ULP_MASTER_MOSI_PIN ULP_SPI_MOSI__PIN +#define RTE_SSI_ULP_MASTER_MOSI_MODE 1 +//Pintool data +#endif + +// SSI_ULP_MASTER_SCK Pin <0=>Not Used <1=>ULP_GPIO_0 <2=>ULP_GPIO_8 +#ifndef ULP_SPI_SCK_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_SSI_ULP_MASTER_SCK_PORT_ID 2 +#else +#define RTE_SSI_ULP_MASTER_SCK_PORT_ID 2 +#endif +#if (RTE_SSI_ULP_MASTER_SCK_PORT_ID == 0) +#define RTE_SSI_ULP_MASTER_SCK 0 +#elif (RTE_SSI_ULP_MASTER_SCK_PORT_ID == 1) +#define RTE_SSI_ULP_MASTER_SCK 1 +#define RTE_SSI_ULP_MASTER_SCK_PORT 0 +#define RTE_SSI_ULP_MASTER_SCK_PIN 0 +#define RTE_SSI_ULP_MASTER_SCK_MODE 1 +#elif (RTE_SSI_ULP_MASTER_SCK_PORT_ID == 2) +#define RTE_SSI_ULP_MASTER_SCK 1 +#define RTE_SSI_ULP_MASTER_SCK_PORT 0 +#define RTE_SSI_ULP_MASTER_SCK_PIN 8 +#define RTE_SSI_ULP_MASTER_SCK_MODE 1 +#else +#error "Invalid SSI_ULP_SCK Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SSI_ULP_MASTER_SCK 1 +#define RTE_SSI_ULP_MASTER_SCK_PORT ULP_SPI_SCK__PORT +#define RTE_SSI_ULP_MASTER_SCK_PIN ULP_SPI_SCK__PIN +#define RTE_SSI_ULP_MASTER_SCK_MODE 1 +//Pintool data +#endif + +// CS0 +#ifndef ULP_SPI_CS0_LOC +#define RTE_SSI_ULP_MASTER_CS0_PORT_ID 1 +#if (RTE_SSI_ULP_MASTER_CS0_PORT_ID == 0) +#define RTE_SSI_ULP_MASTER_CS0 ULP_SSI_CS0 +#define RTE_SSI_ULP_MASTER_CS0_PORT 0 +#define RTE_SSI_ULP_MASTER_CS0_PIN 3 +#define RTE_SSI_ULP_MASTER_CS0_MODE 1 +#elif (RTE_SSI_ULP_MASTER_CS0_PORT_ID == 1) +#define RTE_SSI_ULP_MASTER_CS0 ULP_SSI_CS0 +#define RTE_SSI_ULP_MASTER_CS0_PORT 0 +#define RTE_SSI_ULP_MASTER_CS0_PIN 10 +#define RTE_SSI_ULP_MASTER_CS0_MODE 1 +#else +#error "Change RTE_SSI_ULP_MASTER_CS_PORT_ID other than '1' or'3' as per PACKAGE_TYPE" +#endif +#else +//Pintool data +#define RTE_SSI_ULP_MASTER_CS0 ULP_SSI_CS0 +#define RTE_SSI_ULP_MASTER_CS0_PORT ULP_SPI_CS0__PORT +#define RTE_SSI_ULP_MASTER_CS0_PIN ULP_SPI_CS0__PIN +#define RTE_SSI_ULP_MASTER_CS0_MODE 1 +//Pintool data +#endif + +// CS1 +#ifndef ULP_SPI_CS1_LOC +#define RTE_SSI_ULP_MASTER_CS1_PORT 0 +#define RTE_SSI_ULP_MASTER_CS1_PIN 4 +#else +#define RTE_SSI_ULP_MASTER_CS1_PORT ULP_SPI_CS1__PORT +#define RTE_SSI_ULP_MASTER_CS1_PIN ULP_SPI_CS1__PIN +#endif +#define RTE_SSI_ULP_MASTER_CS1 ULP_SSI_CS1 +#define RTE_SSI_ULP_MASTER_CS1_MODE 1 + +// CS2 +#ifndef ULP_SPI_CS2_LOC +#define RTE_SSI_ULP_MASTER_CS2_PORT 0 +#define RTE_SSI_ULP_MASTER_CS2_PIN 6 +#else +#define RTE_SSI_ULP_MASTER_CS2_PORT ULP_SPI_CS2__PORT +#define RTE_SSI_ULP_MASTER_CS2_PIN ULP_SPI_CS2__PIN +#endif +#define RTE_SSI_ULP_MASTER_CS2 ULP_SSI_CS2 +#define RTE_SSI_ULP_MASTER_CS2_MODE 1 + +// DMA Rx +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// +#define RTE_SSI_ULP_MASTER_UDMA_RX_CH 2 +#define RTE_SSI_ULP_MASTER_DMA_RX_LEN_PER_DES 96 + +// DMA Tx +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// +#define RTE_SSI_ULP_MASTER_UDMA_TX_CH 3 +#define RTE_SSI_ULP_MASTER_DMA_TX_LEN_PER_DES 96 + +// +/*=================================================================== + UDMA Defines +====================================================================*/ +// UDMA [Driver_UDMA] +#define DESC_MAX_LEN 0x400 +#define RTE_UDMA0 1 +#define UDMA0_IRQHandler IRQ033_Handler +#define CHNL_MASK_REQ0 0 +#define CHNL_PRIORITY0 0 +#define DMA_PERI_ACK0 0 +#define BURST_REQ0_EN 1 +#define UDMA0_CHNL_PRIO_LVL 1 +#define UDMA0_SRAM_BASE 0x1FC00 + +#define RTE_UDMA1 1 +#define UDMA1_IRQHandler IRQ010_Handler +#define CHNL_MASK_REQ1 0 +#define CHNL_PRIORITY1 0 +#define BURST_REQ1_EN 1 +#define CHNL_HIGH_PRIO_EN1 1 +#define UDMA1_CHNL_PRIO_LVL 1 +#define ULP_SRAM_START_ADDR 0x24060000 +#define ULP_SRAM_END_ADDR 0x24063E00 +// RTE_UDMA1_BASE_MEM <0=>PS2 <1=>PS4 +#define RTE_UDMA1_BASE_MEM 0 +#if (RTE_UDMA1_BASE_MEM == 0) +#define UDMA1_SRAM_BASE 0x24061C00 +#elif (RTE_UDMA1_BASE_MEM == 1) +#define UDMA1_SRAM_BASE 0x1CC00 +#else +#error "Invalid UDMA1 Control Base Address!" +#endif +// + +// I2S0 [Driver_I2S0] +// Configuration settings for Driver_I2S0 in component ::CMSIS Driver:I2S + +#define RTE_I2S0 1 +#define I2S0_IRQHandler IRQ064_Handler +/*I2S0 PINS*/ + +// I2S0_SCLK <0=>P0_8 <1=>P0_25 <2=>P0_46 <3=>P0_52 +// SCLK of I2S0 +#ifndef I2S0_SCLK_LOC +#define RTE_I2S0_SCLK_PORT_ID 1 + +#if (RTE_I2S0_SCLK_PORT_ID == 0) +#define RTE_I2S0_SCLK_PORT 0 +#define RTE_I2S0_SCLK_PIN 8 +#define RTE_I2S0_SCLK_MUX 7 +#define RTE_I2S0_SCLK_PAD 3 +#elif (RTE_I2S0_SCLK_PORT_ID == 1) +#define RTE_I2S0_SCLK_PORT 0 +#define RTE_I2S0_SCLK_PIN 25 +#define RTE_I2S0_SCLK_MUX 7 +#define RTE_I2S0_SCLK_PAD 0 //no pad +#elif (RTE_I2S0_SCLK_PORT_ID == 2) +#define RTE_I2S0_SCLK_PORT 0 +#define RTE_I2S0_SCLK_PIN 46 +#define RTE_I2S0_SCLK_MUX 7 +#define RTE_I2S0_SCLK_PAD 10 +#elif (RTE_I2S0_SCLK_PORT_ID == 3) +#define RTE_I2S0_SCLK_PORT 0 +#define RTE_I2S0_SCLK_PIN 52 +#define RTE_I2S0_SCLK_MUX 7 +#define RTE_I2S0_SCLK_PAD 16 +#else +#error "Invalid I2S0 RTE_I2S0_SCLK Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_I2S0_SCLK_PORT I2S0_SCLK_PORT +#define RTE_I2S0_SCLK_PIN I2S0_SCLK_PIN +#define RTE_I2S0_SCLK_MUX 7 +#if (I2S0_SCLK_LOC == 0) +#define RTE_I2S0_SCLK_PAD 3 +#endif +#if (I2S0_SCLK_LOC == 1) +#define RTE_I2S0_SCLK_PAD 0 //no pad +#endif +#if (I2S0_SCLK_LOC == 2) +#define RTE_I2S0_SCLK_PAD 10 +#endif +#if (I2S0_SCLK_LOC == 3) +#define RTE_I2S0_SCLK_PAD 16 +#endif +//Pintool data +#endif + +// I2S0_WSCLK <0=>P0_9 <1=>P0_26 <2=>P0_47 <3=>P0_53 +// WSCLK for I2S0 +#ifndef I2S0_WSCLK_LOC +#define RTE_I2S0_WSCLK_PORT_ID 1 + +#if (RTE_I2S0_WSCLK_PORT_ID == 0) +#define RTE_I2S0_WSCLK_PORT 0 +#define RTE_I2S0_WSCLK_PIN 9 +#define RTE_I2S0_WSCLK_MUX 7 +#define RTE_I2S0_WSCLK_PAD 4 +#elif (RTE_I2S0_WSCLK_PORT_ID == 1) +#define RTE_I2S0_WSCLK_PORT 0 +#define RTE_I2S0_WSCLK_PIN 26 +#define RTE_I2S0_WSCLK_MUX 7 +#define RTE_I2S0_WSCLK_PAD 0 //no pad +#elif (RTE_I2S0_WSCLK_PORT_ID == 2) +#define RTE_I2S0_WSCLK_PORT 0 +#define RTE_I2S0_WSCLK_PIN 47 +#define RTE_I2S0_WSCLK_MUX 7 +#define RTE_I2S0_WSCLK_PAD 11 +#elif (RTE_I2S0_WSCLK_PORT_ID == 3) +#define RTE_I2S0_WSCLK_PORT 0 +#define RTE_I2S0_WSCLK_PIN 53 +#define RTE_I2S0_WSCLK_MUX 7 +#define RTE_I2S0_WSCLK_PAD 17 +#else +#error "Invalid I2S0 RTE_I2S0_WSCLK Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_I2S0_WSCLK_PORT I2S0_WSCLK_PORT +#define RTE_I2S0_WSCLK_PIN I2S0_WSCLK_PIN +#define RTE_I2S0_WSCLK_MUX 7 +#if (I2S0_WSCLK_LOC == 4) +#define RTE_I2S0_WSCLK_PAD 4 +#endif +#if (I2S0_WSCLK_LOC == 5) +#define RTE_I2S0_WSCLK_PAD 0 +#endif +#if (I2S0_WSCLK_LOC == 6) +#define RTE_I2S0_WSCLK_PAD 11 +#endif +#if (I2S0_WSCLK_LOC == 7) +#define RTE_I2S0_WSCLK_PAD 17 +#endif +//Pintool data +#endif + +// I2S0_DOUT0 <0=>P0_11 <1=>P0_28 <2=>P0_49 <3=>P0_57 +// DOUT0 for I2S0 +#ifndef I2S0_DOUT0_LOC +#define RTE_I2S0_DOUT0_PORT_ID 1 + +#if (RTE_I2S0_DOUT0_PORT_ID == 0) +#define RTE_I2S0_DOUT0_PORT 0 +#define RTE_I2S0_DOUT0_PIN 11 +#define RTE_I2S0_DOUT0_MUX 7 +#define RTE_I2S0_DOUT0_PAD 6 +#elif (RTE_I2S0_DOUT0_PORT_ID == 1) +#define RTE_I2S0_DOUT0_PORT 0 +#define RTE_I2S0_DOUT0_PIN 28 +#define RTE_I2S0_DOUT0_MUX 7 +#define RTE_I2S0_DOUT0_PAD 0 // no pad +#elif (RTE_I2S0_DOUT0_PORT_ID == 2) +#define RTE_I2S0_DOUT0_PORT 0 +#define RTE_I2S0_DOUT0_PIN 49 +#define RTE_I2S0_DOUT0_MUX 7 +#define RTE_I2S0_DOUT0_PAD 13 +#elif (RTE_I2S0_DOUT0_PORT_ID == 3) +#define RTE_I2S0_DOUT0_PORT 0 +#define RTE_I2S0_DOUT0_PIN 57 +#define RTE_I2S0_DOUT0_MUX 7 +#define RTE_I2S0_DOUT0_PAD 21 +#else +#error "Invalid I2S0 RTE_I2S0_DOUT0 Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_I2S0_DOUT0_PORT I2S0_DOUT0_PORT +#define RTE_I2S0_DOUT0_PIN I2S0_DOUT0_PIN +#define RTE_I2S0_DOUT0_MUX 7 +#if (I2S0_DOUT0_LOC == 8) +#define RTE_I2S0_DOUT0_PAD 6 +#endif +#if (I2S0_DOUT0_LOC == 9) +#define RTE_I2S0_DOUT0_PAD 0 +#endif +#if (I2S0_DOUT0_LOC == 10) +#define RTE_I2S0_DOUT0_PAD 13 +#endif +#if (I2S0_DOUT0_LOC == 11) +#define RTE_I2S0_DOUT0_PAD 21 +#endif +//Pintool data +#endif + +// I2S0_DIN0 <0=>P0_10 <1=>P0_27 <2=>P0_48 <3=>P0_56 +// DIN0 for I2S0 +#ifndef I2S0_DIN0_LOC +#define RTE_I2S0_DIN0_PORT_ID 1 + +#if (RTE_I2S0_DIN0_PORT_ID == 0) +#define RTE_I2S0_DIN0_PORT 0 +#define RTE_I2S0_DIN0_PIN 10 +#define RTE_I2S0_DIN0_MUX 7 +#define RTE_I2S0_DIN0_PAD 5 +#elif (RTE_I2S0_DIN0_PORT_ID == 1) +#define RTE_I2S0_DIN0_PORT 0 +#define RTE_I2S0_DIN0_PIN 27 +#define RTE_I2S0_DIN0_MUX 7 +#define RTE_I2S0_DIN0_PAD 0 // no pad +#elif (RTE_I2S0_DIN0_PORT_ID == 2) +#define RTE_I2S0_DIN0_PORT 0 +#define RTE_I2S0_DIN0_PIN 48 +#define RTE_I2S0_DIN0_MUX 7 +#define RTE_I2S0_DIN0_PAD 12 +#elif (RTE_I2S0_DIN0_PORT_ID == 3) +#define RTE_I2S0_DIN0_PORT 0 +#define RTE_I2S0_DIN0_PIN 56 +#define RTE_I2S0_DIN0_MUX 7 +#define RTE_I2S0_DIN0_PAD 20 +#else +#error "Invalid I2S0 RTE_I2S0_DIN0 Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_I2S0_DIN0_PORT I2S0_DIN0_PORT +#define RTE_I2S0_DIN0_PIN I2S0_DIN0_PIN +#define RTE_I2S0_DIN0_MUX 7 +#if (I2S0_DIN0_LOC == 12) +#define RTE_I2S0_DIN0_PAD 5 +#endif +#if (I2S0_DIN0_LOC == 13) +#define RTE_I2S0_DIN0_PAD 0 +#endif +#if (I2S0_DIN0_LOC == 14) +#define RTE_I2S0_DIN0_PAD 12 +#endif +#if (I2S0_DIN0_LOC == 15) +#define RTE_I2S0_DIN0_PAD 20 +#endif +//Pintool data +#endif + +// I2S0_DOUT1 <0=>P0_7 <1=>P0_30 <2=>P0_51 <3=>P0_55 +// DOUT1 for I2S0 +#ifndef I2S0_DOUT1_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_I2S0_DOUT1_PORT_ID 1 +#else +#define RTE_I2S0_DOUT1_PORT_ID 0 +#endif + +#if (RTE_I2S0_DOUT1_PORT_ID == 0) +#define RTE_I2S0_DOUT1_PORT 0 +#define RTE_I2S0_DOUT1_PIN 7 +#define RTE_I2S0_DOUT1_MUX 7 +#define RTE_I2S0_DOUT1_PAD 2 +#elif (RTE_I2S0_DOUT1_PORT_ID == 1) +#define RTE_I2S0_DOUT1_PORT 0 +#define RTE_I2S0_DOUT1_PIN 30 +#define RTE_I2S0_DOUT1_MUX 7 +#define RTE_I2S0_DOUT1_PAD 0 //no pad +#elif (RTE_I2S0_DOUT1_PORT_ID == 2) +#define RTE_I2S0_DOUT1_PORT 0 +#define RTE_I2S0_DOUT1_PIN 51 +#define RTE_I2S0_DOUT1_MUX 7 +#define RTE_I2S0_DOUT1_PAD 15 +#elif (RTE_I2S0_DOUT1_PORT_ID == 3) +#define RTE_I2S0_DOUT1_PORT 0 +#define RTE_I2S0_DOUT1_PIN 55 +#define RTE_I2S0_DOUT1_MUX 7 +#define RTE_I2S0_DOUT1_PAD 19 +#else +#error "Invalid I2S0 RTE_I2S0_DOUT1 Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_I2S0_DOUT1_PORT I2S0_DOUT1_PORT +#define RTE_I2S0_DOUT1_PIN I2S0_DOUT1_PIN +#define RTE_I2S0_DOUT1_MUX 7 +#if (I2S0_DOUT1_LOC == 16) +#define RTE_I2S0_DOUT1_PAD 2 +#endif +#if (I2S0_DOUT1_LOC == 17) +#define RTE_I2S0_DOUT1_PAD 0 +#endif +#if (I2S0_DOUT1_LOC == 18) +#define RTE_I2S0_DOUT1_PAD 15 +#endif +#if (I2S0_DOUT1_LOC == 19) +#define RTE_I2S0_DOUT1_PAD 19 +#endif +//Pintool data +#endif + +// I2S0_DIN1 <0=>P0_6 <1=>P0_29 <2=>P0_50 <3=>P0_54 +// DIN1 for I2S0 +#ifndef I2S0_DIN1_LOC +#define RTE_I2S0_DIN1_PORT_ID 0 + +#if (RTE_I2S0_DIN1_PORT_ID == 0) +#define RTE_I2S0_DIN1_PORT 0 +#define RTE_I2S0_DIN1_PIN 6 +#define RTE_I2S0_DIN1_MUX 7 +#define RTE_I2S0_DIN1_PAD 1 +#elif (RTE_I2S0_DIN1_PORT_ID == 1) +#define RTE_I2S0_DIN1_PORT 0 +#define RTE_I2S0_DIN1_PIN 29 +#define RTE_I2S0_DIN1_MUX 7 +#define RTE_I2S0_DIN1_PAD 0 //no pad +#elif (RTE_I2S0_DIN1_PORT_ID == 2) +#define RTE_I2S0_DIN1_PORT 0 +#define RTE_I2S0_DIN1_PIN 50 +#define RTE_I2S0_DIN1_MUX 7 +#define RTE_I2S0_DIN1_PAD 14 +#elif (RTE_I2S0_DIN1_PORT_ID == 3) +#define RTE_I2S0_DIN1_PORT 0 +#define RTE_I2S0_DIN1_PIN 54 +#define RTE_I2S0_DIN1_MUX 7 +#define RTE_I2S0_DIN1_PAD 18 +#else +#error "Invalid I2S0 RTE_I2S0_DIN1 Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_I2S0_DIN1_PORT I2S0_DIN1_PORT +#define RTE_I2S0_DIN1_PIN I2S0_DIN1_PIN +#define RTE_I2S0_DIN1_MUX 7 +#if (I2S0_DIN1_LOC == 20) +#define RTE_I2S0_DIN1_PAD 1 +#endif +#if (I2S0_DIN1_LOC == 21) +#define RTE_I2S0_DIN1_PAD 0 +#endif +#if (I2S0_DIN1_LOC == 22) +#define RTE_I2S0_DIN1_PAD 14 +#endif +#if (I2S0_DIN1_LOC == 23) +#define RTE_I2S0_DIN1_PAD 18 +#endif +//Pintool data +#endif +// FIFO level can have value 0 to 7 +#define I2S0_TX_FIFO_LEVEL (0U) +#define I2S0_RX_FIFO_LEVEL (2U) + +// I2S0_TX_RES <0=>12 +// <1=>16 +// <2=>20 +// <3=>24 +#define RTE_I2S0_TX_RES 1 +#if (RTE_I2S0_TX_RES == 0) +#define I2S0_TX_RES RES_12_BIT +#elif (RTE_I2S0_TX_RES == 1) +#define I2S0_TX_RES RES_16_BIT +#elif (RTE_I2S0_TX_RES == 2) +#define I2S0_TX_RES RES_20_BIT +#elif (RTE_I2S0_TX_RES == 3) +#define I2S0_TX_RES RES_24_BIT +#else +#error "Invalid I2S0 TX channel resolution!" +#endif + +// I2S0_RX_RES <0=>12 +// <1=>16 +// <2=>20 +// <3=>24 +#define RTE_I2S0_RX_RES 1 +#if (RTE_I2S0_RX_RES == 0) +#define I2S0_RX_RES RES_12_BIT +#elif (RTE_I2S0_RX_RES == 1) +#define I2S0_RX_RES RES_16_BIT +#elif (RTE_I2S0_RX_RES == 2) +#define I2S0_RX_RES RES_20_BIT +#elif (RTE_I2S0_RX_RES == 3) +#define I2S0_RX_RES RES_24_BIT +#else +#error "Invalid I2S0 RX channel resolution!" +#endif + +#define RTE_I2S0_CHNL_UDMA_TX_EN 1 +#define RTE_I2S0_CHNL_UDMA_TX_CH 15 + +#define RTE_I2S0_CHNL_UDMA_RX_EN 1 +#define RTE_I2S0_CHNL_UDMA_RX_CH 14 + +#define RTE_I2S0_DMA_TX_LEN_PER_DES 1024 +#define RTE_I2S0_DMA_RX_LEN_PER_DES 1024 + +// + +// ULP I2S [Driver_I2S1] +// Configuration settings for Driver_I2S1 in component ::Drivers:I2S +#define RTE_I2S1 1 +#define I2S1_IRQHandler IRQ014_Handler + +// I2S1_SCLK Pin <0=>P0_3 <1=>P0_7 <2=>P0_8 +/*I2S1 PINS*/ +#ifndef ULP_I2S_SCLK_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_I2S1_SCLK_PORT_ID 0 +#else +#define RTE_I2S1_SCLK_PORT_ID 2 +#endif +#if (RTE_I2S1_SCLK_PORT_ID == 0) +#define RTE_I2S1_SCLK_PORT 0 +#define RTE_I2S1_SCLK_PIN 3 +#define RTE_I2S1_SCLK_MUX 2 +#elif (RTE_I2S1_SCLK_PORT_ID == 1) +#define RTE_I2S1_SCLK_PORT 0 +#define RTE_I2S1_SCLK_PIN 7 +#define RTE_I2S1_SCLK_MUX 2 +#elif (RTE_I2S1_SCLK_PORT_ID == 2) +#define RTE_I2S1_SCLK_PORT 0 +#define RTE_I2S1_SCLK_PIN 8 +#define RTE_I2S1_SCLK_MUX 2 +#else +#error "Invalid I2S1 RTE_I2S1_SCLK Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_I2S1_SCLK_PORT ULP_I2S_SCLK_PORT +#define RTE_I2S1_SCLK_PIN ULP_I2S_SCLK_PIN +#define RTE_I2S1_SCLK_MUX 2 +//Pintool data +#endif + +// I2S1_WSCLK Pin <0=>P0_2 <1=>P0_4 <2=>P0_10 +#ifndef ULP_I2S_WSCLK_LOC +#define RTE_I2S1_WSCLK_PORT_ID 0 +#if (RTE_I2S1_WSCLK_PORT_ID == 0) +#define RTE_I2S1_WSCLK_PORT 0 +#define RTE_I2S1_WSCLK_PIN 2 +#define RTE_I2S1_WSCLK_MUX 2 +#elif (RTE_I2S1_WSCLK_PORT_ID == 1) +#define RTE_I2S1_WSCLK_PORT 0 +#define RTE_I2S1_WSCLK_PIN 10 +#define RTE_I2S1_WSCLK_MUX 2 +#else +#error "Invalid I2S1 RTE_I2S1_WSCLK Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_I2S1_WSCLK_PORT ULP_I2S_WSCLK_PORT +#define RTE_I2S1_WSCLK_PIN ULP_I2S_WSCLK_PIN +#define RTE_I2S1_WSCLK_MUX 2 +//Pintool data +#endif + +// I2S1_DOUT0 Pin <0=>P0_1 <1=>P0_5 <2=>P0_11 +#ifndef ULP_I2S_DOUT0_LOC +#define RTE_I2S1_DOUT0_PORT_ID 0 +#if (RTE_I2S1_DOUT0_PORT_ID == 0) +#define RTE_I2S1_DOUT0_PORT 0 +#define RTE_I2S1_DOUT0_PIN 1 +#define RTE_I2S1_DOUT0_MUX 2 +#elif (RTE_I2S1_DOUT0_PORT_ID == 1) +#define RTE_I2S1_DOUT0_PORT 0 +#define RTE_I2S1_DOUT0_PIN 11 +#define RTE_I2S1_DOUT0_MUX 2 +#else +#error "Invalid I2S1 RTE_I2S1_DOUT0 Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_I2S1_DOUT0_PORT ULP_I2S_DOUT0_PORT +#define RTE_I2S1_DOUT0_PIN ULP_I2S_DOUT0_PIN +#define RTE_I2S1_DOUT0_MUX 2 +//Pintool data +#endif + +// I2S1_DIN0 Pin <0=>P0_0 <1=>P0_6 <2=>P0_9 <3=>P0_13 +#ifndef ULP_I2S_DIN0_LOC +#define RTE_I2S1_DIN0_PORT_ID 1 +#if (RTE_I2S1_DIN0_PORT_ID == 0) +#define RTE_I2S1_DIN0_PORT 0 +#define RTE_I2S1_DIN0_PIN 0 +#define RTE_I2S1_DIN0_MUX 2 +#elif (RTE_I2S1_DIN0_PORT_ID == 1) +#define RTE_I2S1_DIN0_PORT 0 +#define RTE_I2S1_DIN0_PIN 6 +#define RTE_I2S1_DIN0_MUX 2 +#elif (RTE_I2S1_DIN0_PORT_ID == 2) +#define RTE_I2S1_DIN0_PORT 0 +#define RTE_I2S1_DIN0_PIN 9 +#define RTE_I2S1_DIN0_MUX 2 +#else +#error "Invalid I2S1 RTE_I2S1_DIN0 Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_I2S1_DIN0_PORT ULP_I2S_DIN0_PORT +#define RTE_I2S1_DIN0_PIN ULP_I2S_DIN0_PIN +#define RTE_I2S1_DIN0_MUX 2 +//Pintool data +#endif + +// FIFO level can have value 0 to 7 +#define I2S1_TX_FIFO_LEVEL (0U) +#define I2S1_RX_FIFO_LEVEL (2U) + +// I2S1_TX_RES <0=>12 +// <1=>16 +// <2=>20 +// <3=>24 +#define RTE_I2S1_TX_RES 1 +#if (RTE_I2S1_TX_RES == 0) +#define I2S1_TX_RES RES_12_BIT +#elif (RTE_I2S1_TX_RES == 1) +#define I2S1_TX_RES RES_16_BIT +#elif (RTE_I2S1_TX_RES == 2) +#define I2S1_TX_RES RES_20_BIT +#elif (RTE_I2S1_TX_RES == 3) +#define I2S1_TX_RES RES_24_BIT +#else +#error "Invalid I2S1 TX channel resolution!" +#endif + +// I2S1_RX_RES <0=>12 +// <1=>16 +// <2=>20 +// <3=>24 +#define RTE_I2S1_RX_RES 1 +#if (RTE_I2S1_RX_RES == 0) +#define I2S1_RX_RES RES_12_BIT +#elif (RTE_I2S1_RX_RES == 1) +#define I2S1_RX_RES RES_16_BIT +#elif (RTE_I2S1_RX_RES == 2) +#define I2S1_RX_RES RES_20_BIT +#elif (RTE_I2S1_RX_RES == 3) +#define I2S1_RX_RES RES_24_BIT +#else +#error "Invalid I2S1 RX channel resolution!" +#endif + +#define RTE_I2S1_CHNL_UDMA_TX_EN 1 +#define RTE_I2S1_CHNL_UDMA_TX_CH 7 + +#define RTE_I2S1_CHNL_UDMA_RX_EN 1 +#define RTE_I2S1_CHNL_UDMA_RX_CH 6 + +#define RTE_I2S1_DMA_TX_LEN_PER_DES 1024 +#define RTE_I2S1_DMA_RX_LEN_PER_DES 1024 + +// I2S1 [Driver_I2S1] + +// I2C0 (Inter-integrated Circuit Interface 0) [Driver_I2C0] +// Configuration settings for Driver_I2C0 in component ::Drivers:I2C + +#define RTE_I2C0 1 +#define I2C0_IRQHandler IRQ042_Handler + +// I2C0_SCL Pin <0=>P0_7 <1=>P0_65 <2=>P0_66 <3=>P0_75 <4=>P0_32 +#ifndef I2C0_SCL_LOC +#define RTE_I2C0_SCL_PORT_ID 1 + +#if (RTE_I2C0_SCL_PORT_ID == 0) +#define RTE_I2C0_SCL_PORT 0 +#define RTE_I2C0_SCL_PIN 7 +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 2 +#define RTE_I2C0_SCL_I2C_REN 7 +#elif (RTE_I2C0_SCL_PORT_ID == 1) +#define RTE_I2C0_SCL_PORT 0 +#define RTE_I2C0_SCL_PIN 65 +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 23 +#define RTE_I2C0_SCL_I2C_REN 1 +#elif (RTE_I2C0_SCL_PORT_ID == 2) +#define RTE_I2C0_SCL_PORT 0 +#define RTE_I2C0_SCL_PIN 66 +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 24 +#define RTE_I2C0_SCL_I2C_REN 2 +#elif (RTE_I2C0_SCL_PORT_ID == 3) +#define RTE_I2C0_SCL_PORT 0 +#define RTE_I2C0_SCL_PIN 75 +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 33 +#define RTE_I2C0_SCL_I2C_REN 11 +#else +#error "Invalid I2C0 RTE_I2C0_SCL Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_I2C0_SCL_PORT I2C0_SCL_PORT +#if (I2C0_SCL_LOC == 0) +#define RTE_I2C0_SCL_PIN I2C0_SCL_PIN +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 2 +#define RTE_I2C0_SCL_I2C_REN 7 +#endif +#if (I2C0_SCL_LOC == 1) +#define RTE_I2C0_SCL_PIN (I2C0_SCL_PIN + GPIO_MAX_PIN) +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 23 +#define RTE_I2C0_SCL_I2C_REN 1 +#endif +#if (I2C0_SCL_LOC == 2) +#define RTE_I2C0_SCL_PIN (I2C0_SCL_PIN + GPIO_MAX_PIN) +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 33 +#define RTE_I2C0_SCL_I2C_REN 11 +#endif +//Pintool data +#endif + +// I2C0_SCL Pin <0=>P0_6 <1=>P0_64 <2=>P0_67 <3=>P0_74 <4=>P0_31 +#ifndef I2C0_SDA_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_I2C0_SDA_PORT_ID 2 +#else +#define RTE_I2C0_SDA_PORT_ID 0 +#endif + +#if (RTE_I2C0_SDA_PORT_ID == 0) +#define RTE_I2C0_SDA_PORT 0 +#define RTE_I2C0_SDA_PIN 6 +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 1 +#define RTE_I2C0_SDA_I2C_REN 6 +#elif (RTE_I2C0_SDA_PORT_ID == 1) +#define RTE_I2C0_SDA_PORT 0 +#define RTE_I2C0_SDA_PIN 67 +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 25 +#define RTE_I2C0_SDA_I2C_REN 3 +#elif (RTE_I2C0_SDA_PORT_ID == 2) +#define RTE_I2C0_SDA_PORT 0 +#define RTE_I2C0_SDA_PIN 74 +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 32 +#define RTE_I2C0_SDA_I2C_REN 10 +#else +#error "Invalid I2C0 RTE_I2C0_SDA Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_I2C0_SDA_PORT I2C0_SDA_PORT +#if (I2C0_SDA_LOC == 3) +#define RTE_I2C0_SDA_PIN I2C0_SDA_PIN +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 1 +#define RTE_I2C0_SDA_I2C_REN 6 +#endif +#if (I2C0_SDA_LOC == 4) +#define RTE_I2C0_SDA_PIN (I2C0_SDA_PIN + GPIO_MAX_PIN) +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 22 +#define RTE_I2C0_SDA_I2C_REN 3 +#endif +#if (I2C0_SDA_LOC == 5) +#define RTE_I2C0_SDA_PIN (I2C0_SDA_PIN + GPIO_MAX_PIN) +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 32 +#define RTE_I2C0_SDA_I2C_REN 10 +#endif +//Pintool data +#endif + +#define IC_SCL_STUCK_TIMEOUT 20 +#define IC_SDA_STUCK_TIMEOUT 20 + +#define I2C_DMA 0 +#if (I2C_DMA == 1) +#define DMA_TX_TL 1 +#define DMA_RX_TL 1 +#endif +// I2C1 [Driver_I2C0] + +// I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1] +// Configuration settings for Driver_I2C1 in component ::Drivers:I2C + +#define RTE_I2C1 1 +#define I2C1_IRQHandler IRQ061_Handler +// I2C1_SCL Pin <0=>P0_6 <1=>P0_29 <2=>P0_50 <3=>P0_54 <4=>P0_64 <4=>P0_66 <4=>P0_70 <7=>P0_33 +#ifndef I2C1_SCL_LOC +#define RTE_I2C1_SCL_PORT_ID 2 + +#if (RTE_I2C1_SCL_PORT_ID == 0) +#define RTE_I2C1_SCL_PORT 0 +#define RTE_I2C1_SCL_PIN 6 +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 1 +#define RTE_I2C1_SCL_REN 6 +#elif (RTE_I2C1_SCL_PORT_ID == 1) +#define RTE_I2C1_SCL_PORT 0 +#define RTE_I2C1_SCL_PIN 29 +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 0 //no pad +#define RTE_I2C1_SCL_REN 29 +#elif (RTE_I2C1_SCL_PORT_ID == 2) +#define RTE_I2C1_SCL_PORT 0 +#define RTE_I2C1_SCL_PIN 50 +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 14 +#define RTE_I2C1_SCL_REN 50 +#elif (RTE_I2C1_SCL_PORT_ID == 3) +#define RTE_I2C1_SCL_PORT 0 +#define RTE_I2C1_SCL_PIN 54 +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 18 +#define RTE_I2C1_SCL_REN 54 +#elif (RTE_I2C1_SCL_PORT_ID == 5) +#define RTE_I2C1_SCL_PORT 0 +#define RTE_I2C1_SCL_PIN 66 +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 24 +#define RTE_I2C1_SCL_REN 2 +#elif (RTE_I2C1_SCL_PORT_ID == 6) +#define RTE_I2C1_SCL_PORT 0 +#define RTE_I2C1_SCL_PIN 70 +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 29 +#define RTE_I2C1_SCL_REN 6 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_I2C1_SCL_PORT I2C1_SCL_PORT +#if (I2C1_SCL_LOC == 0) +#define RTE_I2C1_SCL_PIN I2C1_SCL_PIN +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 1 +#define RTE_I2C1_SCL_REN 6 +#endif +#if (I2C1_SCL_LOC == 1) +#define RTE_I2C1_SCL_PIN I2C1_SCL_PIN +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 0 //no pad +#define RTE_I2C1_SCL_REN 29 +#endif +#if (I2C1_SCL_LOC == 2) +#define RTE_I2C1_SCL_PIN I2C1_SCL_PIN +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 14 +#define RTE_I2C1_SCL_REN 50 +#endif +#if (I2C1_SCL_LOC == 3) +#define RTE_I2C1_SCL_PIN I2C1_SCL_PIN +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 18 +#define RTE_I2C1_SCL_REN 54 +#endif +#if (I2C1_SCL_LOC == 4) +#define RTE_I2C1_SCL_PIN (I2C1_SCL_PIN + GPIO_MAX_PIN) +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 22 +#define RTE_I2C1_SCL_REN 2 +#endif +#if (I2C1_SCL_LOC == 5) +#define RTE_I2C1_SCL_PIN (I2C1_SCL_PIN + GPIO_MAX_PIN) +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 29 +#define RTE_I2C1_SCL_REN 6 +#endif +//Pintool data +#endif + +// I2C1_SCL Pin <0=>P0_7 <1=>P0_30 <2=>P0_51 <3=>P0_55 <4=>P0_65 <4=>P0_67 <4=>P0_71 <7=>P0_34 +#ifndef I2C1_SDA_LOC +#define RTE_I2C1_SDA_PORT_ID 2 + +#if (RTE_I2C1_SDA_PORT_ID == 0) +#define RTE_I2C1_SDA_PORT 0 +#define RTE_I2C1_SDA_PIN 7 +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 2 +#define RTE_I2C1_SDA_REN 7 +#elif (RTE_I2C1_SDA_PORT_ID == 1) +#define RTE_I2C1_SDA_PORT 0 +#define RTE_I2C1_SDA_PIN 30 +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 0 //no pad +#define RTE_I2C1_SDA_REN 30 +#elif (RTE_I2C1_SDA_PORT_ID == 2) +#define RTE_I2C1_SDA_PORT 0 +#define RTE_I2C1_SDA_PIN 51 +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 15 +#define RTE_I2C1_SDA_REN 51 +#elif (RTE_I2C1_SDA_PORT_ID == 3) +#define RTE_I2C1_SDA_PORT 0 +#define RTE_I2C1_SDA_PIN 55 +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 19 +#define RTE_I2C1_SDA_REN 55 +#elif (RTE_I2C1_SDA_PORT_ID == 4) +#define RTE_I2C1_SDA_PORT 0 +#define RTE_I2C1_SDA_PIN 65 +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 23 +#define RTE_I2C1_SDA_REN 1 +#elif (RTE_I2C1_SDA_PORT_ID == 5) +#define RTE_I2C1_SDA_PORT 0 +#define RTE_I2C1_SDA_PIN 67 +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 25 +#define RTE_I2C1_SDA_REN 3 +#elif (RTE_I2C1_SDA_PORT_ID == 6) +#define RTE_I2C1_SDA_PORT 0 +#define RTE_I2C1_SDA_PIN 71 +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 29 +#define RTE_I2C1_SDA_REN 7 +#else +#error "Invalid I2C1_SDA Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_I2C1_SDA_PORT I2C1_SDA_PORT +#if (I2C1_SDA_LOC == 6) +#define RTE_I2C1_SDA_PIN I2C1_SDA_PIN +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 2 +#define RTE_I2C1_SDA_REN 7 +#endif +#if (I2C1_SDA_LOC == 7) +#define RTE_I2C1_SDA_PIN I2C1_SDA_PIN +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 0 //no pad +#define RTE_I2C1_SDA_REN 30 +#endif +#if (I2C1_SDA_LOC == 8) +#define RTE_I2C1_SDA_PIN I2C1_SDA_PIN +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 15 +#define RTE_I2C1_SDA_REN 51 +#endif +#if (I2C1_SDA_LOC == 9) +#define RTE_I2C1_SDA_PIN I2C1_SDA_PIN +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 19 +#define RTE_I2C1_SDA_REN 55 +#endif +#if (I2C1_SDA_LOC == 10) +#define RTE_I2C1_SDA_PIN (I2C1_SDA_PIN + GPIO_MAX_PIN) +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 23 +#define RTE_I2C1_SDA_REN 1 +#endif +#if (I2C1_SDA_LOC == 11) +#define RTE_I2C1_SDA_PIN (I2C1_SDA_PIN + GPIO_MAX_PIN) +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 29 +#define RTE_I2C1_SDA_REN 7 +#endif +//Pintool data +#endif + +#define IC_SCL_STUCK_TIMEOUT 20 +#define IC_SDA_STUCK_TIMEOUT 20 + +#define DMA_EN 0 +#if (DMA_EN == 1) +#define DMA_TX_TL 1 +#define DMA_RX_TL 1 +#endif + +// I2C1 [Driver_I2C1] + +// ULP I2C (Inter-integrated Circuit Interface 2) [Driver_I2C2] +// Configuration settings for Driver_I2C2 in component ::Drivers:I2C +#define RTE_I2C2 1 +#define I2C2_IRQHandler IRQ013_Handler + +// I2C2_SCL Pin <0=>P0_1 <1=>P0_5 <2=>P0_7 <3=>P0_8 <4=>P0_13 +#ifndef ULP_I2C_SCL_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_I2C2_SCL_PORT_ID 0 +#else +#define RTE_I2C2_SCL_PORT_ID 0 +#endif +#if (RTE_I2C2_SCL_PORT_ID == 0) +#define RTE_I2C2_SCL_PORT 0 +#define RTE_I2C2_SCL_PIN 7 +#define RTE_I2C2_SCL_MUX 4 +#define RTE_I2C2_SCL_REN 7 +#elif (RTE_I2C2_SCL_PORT_ID == 1) +#define RTE_I2C2_SCL_PORT 0 +#define RTE_I2C2_SCL_PIN 8 +#define RTE_I2C2_SCL_MUX 4 +#define RTE_I2C2_SCL_REN 8 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_I2C2_SCL_PORT ULP_I2C_SCL_PORT +#define RTE_I2C2_SCL_PIN ULP_I2C_SCL_PIN +#define RTE_I2C2_SCL_MUX 4 +#if (ULP_I2C_SCL_LOC == 0) +#define RTE_I2C2_SCL_REN 0 +#elif (ULP_I2C_SCL_LOC == 1) +#define RTE_I2C2_SCL_REN 0 +#elif (ULP_I2C_SCL_LOC == 2) +#define RTE_I2C2_SCL_REN 7 +#elif (ULP_I2C_SCL_LOC == 3) +#define RTE_I2C2_SCL_REN 8 +#endif +//Pintool data +#endif + +// I2C2_SDA Pin <0=>P0_0 <1=>P0_4 <2=>P0_6 <3=>P0_9 <4=>P0_11 <5=>P0_12 +#ifndef ULP_I2C_SDA_LOC +#define RTE_I2C2_SDA_PORT_ID 0 +#if (RTE_I2C2_SDA_PORT_ID == 0) +#define RTE_I2C2_SDA_PORT 0 +#define RTE_I2C2_SDA_PIN 6 +#define RTE_I2C2_SDA_MUX 4 +#define RTE_I2C2_SDA_REN 6 +#elif (RTE_I2C2_SDA_PORT_ID == 1) +#define RTE_I2C2_SDA_PORT 0 +#define RTE_I2C2_SDA_PIN 9 +#define RTE_I2C2_SDA_MUX 4 +#define RTE_I2C2_SDA_REN 9 +#elif (RTE_I2C2_SDA_PORT_ID == 2) +#define RTE_I2C2_SDA_PORT 0 +#define RTE_I2C2_SDA_PIN 11 +#define RTE_I2C2_SDA_MUX 4 +#define RTE_I2C2_SDA_REN 11 +#else +#error "Invalid I2C2_SDA Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_I2C2_SDA_PORT I2C2_SDA_PORT +#define RTE_I2C2_SDA_PIN I2C2_SDA_PIN +#define RTE_I2C2_SDA_MUX 4 +#if (ULP_I2C_SDA_LOC == 4) +#define RTE_I2C2_SDA_REN 0 +#elif (ULP_I2C_SDA_LOC == 5) +#define RTE_I2C2_SDA_REN 0 +#elif (ULP_I2C_SDA_LOC == 6) +#define RTE_I2C2_SDA_REN 6 +#elif (ULP_I2C_SDA_LOC == 7) +#define RTE_I2C2_SDA_REN 9 +#elif (ULP_I2C_SDA_LOC == 8) +#define RTE_I2C2_SDA_REN 11 +#endif +//Pintool data +#endif + +#define IC_SCL_STUCK_TIMEOUT 20 +#define IC_SDA_STUCK_TIMEOUT 20 + +#define DMA_EN 0 +#if (DMA_EN == 1) +#define DMA_TX_TL 1 +#define DMA_RX_TL 1 +#endif + +// I2C2 [Driver_I2C2] + +// GSPI (Generic SPI master) [Driver_GSPI_MASTER] +// Configuration settings for Driver_GSPI_MASTER in component ::Drivers:GSPI +#define RTE_GSPI_MASTER 1 + +// GSPI_MASTER_CLK <0=>P0_8 <1=>P0_25 <2=>P0_46 <3=>P0_52 +// CLK of GSPI0 +#ifndef GSPI_MASTER_SCK_LOC +#define RTE_GSPI_MASTER_CLK_PORT_ID 1 + +#if (RTE_GSPI_MASTER_CLK_PORT_ID == 0) +#define RTE_GSPI_MASTER_CLK_PORT 0 +#define RTE_GSPI_MASTER_CLK_PIN 8 +#define RTE_GSPI_MASTER_CLK_MUX 4 +#define RTE_GSPI_MASTER_CLK_PAD 3 +#elif (RTE_GSPI_MASTER_CLK_PORT_ID == 1) +#define RTE_GSPI_MASTER_CLK_PORT 0 +#define RTE_GSPI_MASTER_CLK_PIN 25 +#define RTE_GSPI_MASTER_CLK_MUX 4 +#define RTE_GSPI_MASTER_CLK_PAD 0 //NO PAD +#elif (RTE_GSPI_MASTER_CLK_PORT_ID == 2) +#define RTE_GSPI_MASTER_CLK_PORT 0 +#define RTE_GSPI_MASTER_CLK_PIN 46 +#define RTE_GSPI_MASTER_CLK_MUX 4 +#define RTE_GSPI_MASTER_CLK_PAD 10 +#elif (RTE_GSPI_MASTER_CLK_PORT_ID == 3) +#define RTE_GSPI_MASTER_CLK_PORT 0 +#define RTE_GSPI_MASTER_CLK_PIN 52 +#define RTE_GSPI_MASTER_CLK_MUX 4 +#define RTE_GSPI_MASTER_CLK_PAD 16 +#else +#error "Invalid GSPI0 RTE_GSPI_MASTER_CLK_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_GSPI_MASTER_CLK_PORT GSPI_MASTER_SCK__PORT +#define RTE_GSPI_MASTER_CLK_PIN GSPI_MASTER_SCK__PIN +#define RTE_GSPI_MASTER_CLK_MUX 4 +#if (GSPI_MASTER_SCK_LOC == 0) +#define RTE_GSPI_MASTER_CLK_PAD 3 +#endif +#if (GSPI_MASTER_SCK_LOC == 1) +#define RTE_GSPI_MASTER_CLK_PAD 0 +#endif +#if (GSPI_MASTER_SCK_LOC == 2) +#define RTE_GSPI_MASTER_CLK_PAD 10 +#endif +#if (GSPI_MASTER_SCK_LOC == 3) +#define RTE_GSPI_MASTER_CLK_PAD 16 +#endif +//Pintool data +#endif + +// GSPI_MASTER_CS0 +// <0=>P0_9 <1=>P0_28 <2=>P0_49 <3=>P0_53 +// CS0 of GSPI0 +// +#ifndef GSPI_MASTER_CS0_LOC +#define RTE_GSPI_MASTER_CS0_PORT_ID 1 + +#if (RTE_GSPI_MASTER_CS0_PORT_ID == 0) +#define RTE_GSPI_MASTER_CS0 1 +#define RTE_GSPI_MASTER_CS0_PORT 0 +#define RTE_GSPI_MASTER_CS0_PIN 9 +#define RTE_GSPI_MASTER_CS0_MUX 4 +#define RTE_GSPI_MASTER_CS0_PAD 4 +#elif (RTE_GSPI_MASTER_CS0_PORT_ID == 1) +#define RTE_GSPI_MASTER_CS0 1 +#define RTE_GSPI_MASTER_CS0_PORT 0 +#define RTE_GSPI_MASTER_CS0_PIN 28 +#define RTE_GSPI_MASTER_CS0_MUX 4 +#define RTE_GSPI_MASTER_CS0_PAD 0 //NO PAD +#elif (RTE_GSPI_MASTER_CS0_PORT_ID == 2) +#define RTE_GSPI_MASTER_CS0 1 +#define RTE_GSPI_MASTER_CS0_PORT 0 +#define RTE_GSPI_MASTER_CS0_PIN 49 +#define RTE_GSPI_MASTER_CS0_MUX 4 +#define RTE_GSPI_MASTER_CS0_PAD 13 +#elif (RTE_GSPI_MASTER_CS0_PORT_ID == 3) +#define RTE_GSPI_MASTER_CS0 1 +#define RTE_GSPI_MASTER_CS0_PORT 0 +#define RTE_GSPI_MASTER_CS0_PIN 53 +#define RTE_GSPI_MASTER_CS0_MUX 4 +#define RTE_GSPI_MASTER_CS0_PAD 17 +#else +#error "Invalid GSPI0 RTE_GSPI_MASTER_CS0_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_GSPI_MASTER_CS0 1 +#define RTE_GSPI_MASTER_CS0_PORT GSPI_MASTER_CS0__PORT +#define RTE_GSPI_MASTER_CS0_PIN GSPI_MASTER_CS0__PIN +#define RTE_GSPI_MASTER_CS0_MUX 4 +#if (GSPI_MASTER_CS0_LOC == 4) +#define RTE_GSPI_MASTER_CS0_PAD 4 +#endif +#if (GSPI_MASTER_CS0_LOC == 5) +#define RTE_GSPI_MASTER_CS0_PAD 0 +#endif +#if (GSPI_MASTER_CS0_LOC == 6) +#define RTE_GSPI_MASTER_CS0_PAD 13 +#endif +#if (GSPI_MASTER_CS0_LOC == 7) +#define RTE_GSPI_MASTER_CS0_PAD 17 +#endif +//Pintool data +#endif + +// GSPI_MASTER_CS1 +// <0=>P0_10 <1=>P0_29 <2=>P0_50 <3=>P0_54 +// CS1 of GSPI0 +// +#ifndef GSPI_MASTER_CS1_LOC +#define RTE_GSPI_MASTER_CS1_PORT_ID 1 +#if (RTE_GSPI_MASTER_CS1_PORT_ID == 0) +#define RTE_GSPI_MASTER_CS1 1 +#define RTE_GSPI_MASTER_CS1_PORT 0 +#define RTE_GSPI_MASTER_CS1_PIN 10 +#define RTE_GSPI_MASTER_CS1_MUX 4 +#define RTE_GSPI_MASTER_CS1_PAD 5 +#elif (RTE_GSPI_MASTER_CS1_PORT_ID == 1) +#define RTE_GSPI_MASTER_CS1 1 +#define RTE_GSPI_MASTER_CS1_PORT 0 +#define RTE_GSPI_MASTER_CS1_PIN 29 +#define RTE_GSPI_MASTER_CS1_MUX 4 +#define RTE_GSPI_MASTER_CS1_PAD 0 //NO PAD +#elif (RTE_GSPI_MASTER_CS1_PORT_ID == 2) +#define RTE_GSPI_MASTER_CS1 1 +#define RTE_GSPI_MASTER_CS1_PORT 0 +#define RTE_GSPI_MASTER_CS1_PIN 50 +#define RTE_GSPI_MASTER_CS1_MUX 4 +#define RTE_GSPI_MASTER_CS1_PAD 14 +#elif (RTE_GSPI_MASTER_CS1_PORT_ID == 3) +#define RTE_GSPI_MASTER_CS1 1 +#define RTE_GSPI_MASTER_CS1_PORT 0 +#define RTE_GSPI_MASTER_CS1_PIN 54 +#define RTE_GSPI_MASTER_CS1_MUX 4 +#define RTE_GSPI_MASTER_CS1_PAD 18 +#else +#error "Invalid GSPI0 RTE_GSPI_MASTER_CS1_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_GSPI_MASTER_CS1 1 +#define RTE_GSPI_MASTER_CS1_PORT GSPI_MASTER_CS1__PORT +#define RTE_GSPI_MASTER_CS1_PIN GSPI_MASTER_CS1__PIN +#define RTE_GSPI_MASTER_CS1_MUX 4 +#if (GSPI_MASTER_CS1_LOC == 8) +#define RTE_GSPI_MASTER_CS1_PAD 5 +#endif +#if (GSPI_MASTER_CS1_LOC == 9) +#define RTE_GSPI_MASTER_CS1_PAD 0 +#endif +#if (GSPI_MASTER_CS1_LOC == 10) +#define RTE_GSPI_MASTER_CS1_PAD 14 +#endif +#if (GSPI_MASTER_CS1_LOC == 11) +#define RTE_GSPI_MASTER_CS1_PAD 18 +#endif +//Pintool data +#endif + +// GSPI_MASTER_CS2 +// <0=>P0_15 <1=>P0_30 <2=>P0_51 <3=>P0_55 +// CS2 of GSPI0 +// +#ifndef GSPI_MASTER_CS2_LOC +#define RTE_GSPI_MASTER_CS2_PORT_ID 1 +#if (RTE_GSPI_MASTER_CS2_PORT_ID == 0) +#define RTE_GSPI_MASTER_CS2 1 +#define RTE_GSPI_MASTER_CS2_PORT 0 +#define RTE_GSPI_MASTER_CS2_PIN 15 +#define RTE_GSPI_MASTER_CS2_MUX 4 +#define RTE_GSPI_MASTER_CS2_PAD 8 +#elif (RTE_GSPI_MASTER_CS2_PORT_ID == 1) +#define RTE_GSPI_MASTER_CS2 1 +#define RTE_GSPI_MASTER_CS2_PORT 0 +#define RTE_GSPI_MASTER_CS2_PIN 30 +#define RTE_GSPI_MASTER_CS2_MUX 4 +#define RTE_GSPI_MASTER_CS2_PAD 0 //NO PAD +#elif (RTE_GSPI_MASTER_CS2_PORT_ID == 2) +#define RTE_GSPI_MASTER_CS2 1 +#define RTE_GSPI_MASTER_CS2_PORT 0 +#define RTE_GSPI_MASTER_CS2_PIN 51 +#define RTE_GSPI_MASTER_CS2_MUX 4 +#define RTE_GSPI_MASTER_CS2_PAD 15 +#elif (RTE_GSPI_MASTER_CS2_PORT_ID == 3) +#define RTE_GSPI_MASTER_CS2 1 +#define RTE_GSPI_MASTER_CS2_PORT 0 +#define RTE_GSPI_MASTER_CS2_PIN 55 +#define RTE_GSPI_MASTER_CS2_MUX 4 +#define RTE_GSPI_MASTER_CS2_PAD 19 +#else +#error "Invalid GSPI0 RTE_GSPI_MASTER_CS2_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_GSPI_MASTER_CS2 1 +#define RTE_GSPI_MASTER_CS2_PORT GSPI_MASTER_CS2__PORT +#define RTE_GSPI_MASTER_CS2_PIN GSPI_MASTER_CS2__PIN +#define RTE_GSPI_MASTER_CS2_MUX 4 +#if (GSPI_MASTER_CS2_LOC == 12) +#define RTE_GSPI_MASTER_CS2_PAD 8 +#endif +#if (GSPI_MASTER_CS2_LOC == 13) +#define RTE_GSPI_MASTER_CS2_PAD 0 +#endif +#if (GSPI_MASTER_CS2_LOC == 14) +#define RTE_GSPI_MASTER_CS2_PAD 15 +#endif +#if (GSPI_MASTER_CS2_LOC == 15) +#define RTE_GSPI_MASTER_CS2_PAD 19 +#endif +//Pintool data +#endif + +// GSPI_MASTER_MOSI <0=>P0_12 <1=>P0_27 <2=>P0_48 <3=>P0_57 <4=>P0_6 +// MOSI of GSPI0 +#ifndef GSPI_MASTER_MOSI_LOC +#define RTE_GSPI_MASTER_MOSI_PORT_ID 1 + +#if (RTE_GSPI_MASTER_MOSI_PORT_ID == 0) +#define RTE_GSPI_MASTER_MOSI_PORT 0 +#define RTE_GSPI_MASTER_MOSI_PIN 12 +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 7 +#elif (RTE_GSPI_MASTER_MOSI_PORT_ID == 1) +#define RTE_GSPI_MASTER_MOSI_PORT 0 +#define RTE_GSPI_MASTER_MOSI_PIN 27 +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 0 //NO PAD +#elif (RTE_GSPI_MASTER_MOSI_PORT_ID == 2) +#define RTE_GSPI_MASTER_MOSI_PORT 0 +#define RTE_GSPI_MASTER_MOSI_PIN 48 +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 12 +#elif (RTE_GSPI_MASTER_MOSI_PORT_ID == 3) +#define RTE_GSPI_MASTER_MOSI_PORT 0 +#define RTE_GSPI_MASTER_MOSI_PIN 57 +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 21 +#elif (RTE_GSPI_MASTER_MOSI_PORT_ID == 4) +#define RTE_GSPI_MASTER_MOSI_PORT 0 +#define RTE_GSPI_MASTER_MOSI_PIN 6 +#define RTE_GSPI_MASTER_MOSI_MUX 12 +#define RTE_GSPI_MASTER_MOSI_PAD 1 +#else +#error "Invalid GSPI0 RTE_GSPI_MASTER_MOSI_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_GSPI_MASTER_MOSI_PORT GSPI_MASTER_MOSI__PORT +#define RTE_GSPI_MASTER_MOSI_PIN GSPI_MASTER_MOSI__PIN +#if (GSPI_MASTER_MOSI_LOC == 16) +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 1 +#endif +#if (GSPI_MASTER_MOSI_LOC == 17) +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 0 +#endif +#if (GSPI_MASTER_MOSI_LOC == 18) +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 12 +#endif +#if (GSPI_MASTER_MOSI_LOC == 19) +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 21 +#endif +#if (GSPI_MASTER_MOSI_LOC == 20) +#define RTE_GSPI_MASTER_MOSI_MUX 12 +#define RTE_GSPI_MASTER_MOSI_PAD 1 +#endif +//Pintool data +#endif + +// GSPI_MASTER_MISO <0=>P0_11 <1=>P0_26 <2=>P0_47 <3=>P0_56 +// MISO of GSPI0 +#ifndef GSPI_MASTER_MISO_LOC +#define RTE_GSPI_MASTER_MISO_PORT_ID 1 + +#if (RTE_GSPI_MASTER_MISO_PORT_ID == 0) +#define RTE_GSPI_MASTER_MISO_PORT 0 +#define RTE_GSPI_MASTER_MISO_PIN 11 +#define RTE_GSPI_MASTER_MISO_MUX 4 +#define RTE_GSPI_MASTER_MISO_PAD 6 +#elif (RTE_GSPI_MASTER_MISO_PORT_ID == 1) +#define RTE_GSPI_MASTER_MISO_PORT 0 +#define RTE_GSPI_MASTER_MISO_PIN 26 +#define RTE_GSPI_MASTER_MISO_MUX 4 +#define RTE_GSPI_MASTER_MISO_PAD 0 //NO PAD +#elif (RTE_GSPI_MASTER_MISO_PORT_ID == 2) +#define RTE_GSPI_MASTER_MISO_PORT 0 +#define RTE_GSPI_MASTER_MISO_PIN 47 +#define RTE_GSPI_MASTER_MISO_MUX 4 +#define RTE_GSPI_MASTER_MISO_PAD 11 +#elif (RTE_GSPI_MASTER_MISO_PORT_ID == 3) +#define RTE_GSPI_MASTER_MISO_PORT 0 +#define RTE_GSPI_MASTER_MISO_PIN 56 +#define RTE_GSPI_MASTER_MISO_MUX 4 +#define RTE_GSPI_MASTER_MISO_PAD 20 +#else +#error "Invalid GSPI0 RTE_GSPI_MASTER_MISO_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_GSPI_MASTER_MISO_PORT GSPI_MASTER_MISO__PORT +#define RTE_GSPI_MASTER_MISO_PIN GSPI_MASTER_MISO__PIN +#define RTE_GSPI_MASTER_MISO_MUX 4 +#if (GSPI_MASTER_MISO_LOC == 21) +#define RTE_GSPI_MASTER_MISO_PAD 6 +#endif +#if (GSPI_MASTER_MISO_LOC == 22) +#define RTE_GSPI_MASTER_MISO_PAD 0 +#endif +#if (GSPI_MASTER_MISO_LOC == 23) +#define RTE_GSPI_MASTER_MISO_PAD 11 +#endif +#if (GSPI_MASTER_MISO_LOC == 24) +#define RTE_GSPI_MASTER_MISO_PAD 20 +#endif +//Pintool data +#endif + +#if defined(HIGH_THROUGHPUT_EN) && (HIGH_THROUGHPUT_EN == ENABLE) +#define RTE_GSPI_MASTER_CHNL_UDMA_TX_EN 1 +#define RTE_GSPI_MASTER_CHNL_UDMA_TX_CH 11 + +#define RTE_GSPI_MASTER_CHNL_UDMA_RX_EN 1 +#define RTE_GSPI_MASTER_CHNL_UDMA_RX_CH 10 + +#define RTE_FIFO_AFULL_THRLD 3 +#define RTE_FIFO_AEMPTY_THRLD 7 + +#define TX_DMA_ARB_SIZE ARBSIZE_4 +#define RX_DMA_ARB_SIZE ARBSIZE_8 +#else +#define RTE_GSPI_MASTER_CHNL_UDMA_TX_EN 0 +#define RTE_GSPI_MASTER_CHNL_UDMA_TX_CH 11 + +#define RTE_GSPI_MASTER_CHNL_UDMA_RX_EN 0 +#define RTE_GSPI_MASTER_CHNL_UDMA_RX_CH 10 + +#define RTE_FIFO_AFULL_THRLD 0 +#define RTE_FIFO_AEMPTY_THRLD 0 + +#define TX_DMA_ARB_SIZE ARBSIZE_1 +#define RX_DMA_ARB_SIZE ARBSIZE_1 +#endif + +// (Generic SPI master)[Driver_GSPI_MASTER] + +// (State Configurable Timer) Interface +#define SCT_CLOCK_SOURCE M4_SOCCLKFOROTHERCLKSCT +#define SCT_CLOCK_DIV_FACT 1 + +//SCT_IN_0 <0=>GPIO_25 <1=>GPIO_64 <2=>GPIO_68 + +#ifndef SCT_IN0_LOC +#define RTE_SCT_IN_0_PORT_ID 0 + +#if (RTE_SCT_IN_0_PORT_ID == 0) +#define RTE_SCT_IN_0_PORT 0 +#define RTE_SCT_IN_0_PIN 25 +#define RTE_SCT_IN_0_MUX 9 +#define RTE_SCT_IN_0_PAD 0 //no pad +#else +#error "Invalid RTE_SCT_IN_0_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SCT_IN_0_PORT SCT_IN0_PORT +#if (SCT_IN0_LOC == 0) +#define RTE_SCT_IN_0_PIN SCT_IN0_PIN +#define RTE_SCT_IN_0_MUX 9 +#define RTE_SCT_IN_0_PAD 0 //no pad +#elif (SCT_IN0_LOC == 1) +#define RTE_SCT_IN_0_PIN (SCT_IN0_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_0_MUX 7 +#define RTE_SCT_IN_0_PAD 22 +#elif (SCT_IN0_LOC == 2) +#define RTE_SCT_IN_0_PIN (SCT_IN0_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_0_MUX 9 +#define RTE_SCT_IN_0_PAD 26 +#endif +//Pintool data +#endif + +//SCT_IN_1 <0=>GPIO_26 <1=>GPIO_65 <2=>GPIO_69 +#ifndef SCT_IN1_LOC +#define RTE_SCT_IN_1_PORT_ID 1 + +#if (RTE_SCT_IN_1_PORT_ID == 0) +#define RTE_SCT_IN_1_PORT 0 +#define RTE_SCT_IN_1_PIN 26 +#define RTE_SCT_IN_1_MUX 9 +#define RTE_SCT_IN_1_PAD 0 //no pad +#elif (RTE_SCT_IN_1_PORT_ID == 1) +#define RTE_SCT_IN_1_PORT 0 +#define RTE_SCT_IN_1_PIN 65 +#define RTE_SCT_IN_1_MUX 7 +#define RTE_SCT_IN_1_PAD 23 +#else +#error "Invalid RTE_SCT_IN_1_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SCT_IN_1_PORT SCT_IN1_PORT +#if (SCT_IN1_LOC == 3) +#define RTE_SCT_IN_1_PIN SCT_IN1_PIN +#define RTE_SCT_IN_1_MUX 9 +#define RTE_SCT_IN_1_PAD 0 //no pad +#endif +#if (SCT_IN1_LOC == 4) +#define RTE_SCT_IN_1_PIN (SCT_IN1_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_1_MUX 7 +#define RTE_SCT_IN_1_PAD 23 +#endif +#if (SCT_IN1_LOC == 5) +#define RTE_SCT_IN_1_PIN (SCT_IN1_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_1_MUX 9 +#define RTE_SCT_IN_1_PAD 27 +#endif +//Pintool data +#endif + +//SCT_IN_2 <0=>GPIO_27 <1=>GPIO_66 <2=>GPIO_70 +#ifndef SCT_IN2_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_SCT_IN_2_PORT_ID 0 +#else +#define RTE_SCT_IN_2_PORT_ID 1 +#endif + +#if (RTE_SCT_IN_2_PORT_ID == 0) +#define RTE_SCT_IN_2_PORT 0 +#define RTE_SCT_IN_2_PIN 27 +#define RTE_SCT_IN_2_MUX 9 +#define RTE_SCT_IN_2_PAD 0 //no pad +#elif (RTE_SCT_IN_2_PORT_ID == 1) +#define RTE_SCT_IN_2_PORT 0 +#define RTE_SCT_IN_2_PIN 66 +#define RTE_SCT_IN_2_MUX 7 +#define RTE_SCT_IN_2_PAD 24 +#elif (RTE_SCT_IN_2_PORT_ID == 2) +#define RTE_SCT_IN_2_PORT 0 +#define RTE_SCT_IN_2_PIN 70 +#define RTE_SCT_IN_2_MUX 9 +#define RTE_SCT_IN_2_PAD 28 +#else +#error "Invalid RTE_SCT_IN_0_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SCT_IN_2_PORT SCT_IN2_PORT +#if (SCT_IN2_LOC == 6) +#define RTE_SCT_IN_2_PIN SCT_IN2_PIN +#define RTE_SCT_IN_2_MUX 9 +#define RTE_SCT_IN_2_PAD 0 //no pad +#endif +#if (SCT_IN2_LOC == 7) +#define RTE_SCT_IN_2_PIN (SCT_IN2_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_2_MUX 9 +#define RTE_SCT_IN_2_PAD 28 +#endif +//Pintool data +#endif + +//SCT_IN_3 <0=>GPIO_28 <1=>GPIO_67 <2=>GPIO_71 +#ifndef SCT_IN3_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_SCT_IN_3_PORT_ID 0 +#else +#define RTE_SCT_IN_3_PORT_ID 1 +#endif + +#if (RTE_SCT_IN_3_PORT_ID == 0) +#define RTE_SCT_IN_3_PORT 0 +#define RTE_SCT_IN_3_PIN 28 +#define RTE_SCT_IN_3_MUX 9 +#define RTE_SCT_IN_3_PAD 0 //no pad +#elif (RTE_SCT_IN_3_PORT_ID == 1) +#define RTE_SCT_IN_3_PORT 0 +#define RTE_SCT_IN_3_PIN 67 +#define RTE_SCT_IN_3_MUX 7 +#define RTE_SCT_IN_3_PAD 25 +#elif (RTE_SCT_IN_3_PORT_ID == 2) +#define RTE_SCT_IN_3_PORT 0 +#define RTE_SCT_IN_3_PIN 71 +#define RTE_SCT_IN_3_MUX 9 +#define RTE_SCT_IN_3_PAD 29 +#else +#error "Invalid RTE_SCT_IN_0_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SCT_IN_3_PORT SCT_IN3_PORT +#if (SCT_IN3_LOC == 8) +#define RTE_SCT_IN_3_PIN SCT_IN3_PIN +#define RTE_SCT_IN_3_MUX 9 +#define RTE_SCT_IN_3_PAD 0 //no pad +#endif +#if (SCT_IN3_LOC == 9) +#define RTE_SCT_IN_3_PIN (SCT_IN3_PIN + GPIO_MAX_PIN) +#define RTE_SCT_IN_3_MUX 9 +#define RTE_SCT_IN_3_PAD 29 +#endif +//Pintool data +#endif + +// SCT_OUT_0 <0=>GPIO_29 <1=>GPIO_68 +#ifndef SCT_OUT0_LOC +#define RTE_SCT_OUT_0_PORT_ID 0 +#if (RTE_SCT_OUT_0_PORT_ID == 0) +#define RTE_SCT_OUT_0_PORT 0 +#define RTE_SCT_OUT_0_PIN 29 +#define RTE_SCT_OUT_0_MUX 9 +#define RTE_SCT_OUT_0_PAD 0 //no pad +#else +#error "Invalid RTE_SCT_OUT_0_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SCT_OUT_0_PORT SCT_OUT0_PORT +#if (SCT_OUT0_LOC == 10) +#define RTE_SCT_OUT_0_PIN SCT_OUT0_PIN +#define RTE_SCT_OUT_0_MUX 9 +#define RTE_SCT_OUT_0_PAD 0 //no pad +#elif (SCT_OUT0_LOC == 11) +#define RTE_SCT_OUT_0_PIN (SCT_OUT0_PIN + GPIO_MAX_PIN) +#define RTE_SCT_OUT_0_MUX 7 +#define RTE_SCT_OUT_0_PAD 26 +#endif +//Pintool data +#endif + +// SCT_OUT_1 <0=>GPIO_30 <1=>GPIO_69 +#ifndef SCT_OUT1_LOC +#define RTE_SCT_OUT_1_PORT_ID 0 +#if (RTE_SCT_OUT_1_PORT_ID == 0) +#define RTE_SCT_OUT_1_PORT 0 +#define RTE_SCT_OUT_1_PIN 30 +#define RTE_SCT_OUT_1_MUX 9 +#define RTE_SCT_OUT_1_PAD 0 //no pad +#else +#error "Invalid RTE_SCT_OUT_1_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SCT_OUT_1_PORT SCT_OUT1_PORT +#if (SCT_OUT1_LOC == 12) +#define RTE_SCT_OUT_1_PIN SCT_OUT1_PIN +#define RTE_SCT_OUT_1_MUX 9 +#define RTE_SCT_OUT_1_PAD 0 //no pad +#elif (SCT_OUT1_LOC == 13) +#define RTE_SCT_OUT_1_PIN (SCT_OUT1_PIN + GPIO_MAX_PIN) +#define RTE_SCT_OUT_1_MUX 7 +#define RTE_SCT_OUT_1_PAD 27 +#endif +//Pintool data +#endif + +//Pintool data +#define RTE_SCT_OUT_2_PORT SCT_OUT2_PORT +#define RTE_SCT_OUT_2_PIN SCT_OUT2_PIN +#define RTE_SCT_OUT_2_MUX 7 +#define RTE_SCT_OUT_2_PAD 28 +//Pintool data + +//Pintool data +#define RTE_SCT_OUT_3_PORT SCT_OUT3_PORT +#define RTE_SCT_OUT_3_PIN SCT_OUT3_PIN +#define RTE_SCT_OUT_3_MUX 7 +#define RTE_SCT_OUT_3_PAD 29 +//Pintool data + +//Pintool data +#define RTE_SCT_OUT_4_PORT SCT_OUT4_PORT +#define RTE_SCT_OUT_4_PIN SCT_OUT4_PIN +#define RTE_SCT_OUT_4_MUX 7 +#define RTE_SCT_OUT_4_PAD 30 +//Pintool data + +//Pintool data +#define RTE_SCT_OUT_5_PORT SCT_OUT5_PORT +#define RTE_SCT_OUT_5_PIN SCT_OUT5_PIN +#define RTE_SCT_OUT_5_MUX 7 +#define RTE_SCT_OUT_5_PAD 31 +//Pintool data + +//Pintool data +#define RTE_SCT_OUT_6_PORT SCT_OUT6_PORT +#define RTE_SCT_OUT_6_PIN SCT_OUT6_PIN +#define RTE_SCT_OUT_6_MUX 7 +#define RTE_SCT_OUT_6_PAD 32 +//Pintool data + +//Pintool data +#define RTE_SCT_OUT_7_PORT SCT_OUT7_PORT +#define RTE_SCT_OUT_7_PIN SCT_OUT7_PIN +#define RTE_SCT_OUT_7_MUX 7 +#define RTE_SCT_OUT_7_PAD 33 +//Pintool data + +// SIO // +//<> Serial Input Output +//SIO_0 <0=>GPIO_6 <1=>GPIO_25 <2=>GPIO_64 <3=>GPIO_72 +#ifndef SIO_0_LOC +#define RTE_SIO_0_PORT_ID 0 + +#if (RTE_SIO_0_PORT_ID == 0) +#define RTE_SIO_0_PORT 0 +#define RTE_SIO_0_PIN 6 +#define RTE_SIO_0_MUX 1 +#define RTE_SIO_0_PAD 1 +#elif (RTE_SIO_0_PORT_ID == 1) +#define RTE_SIO_0_PORT 0 +#define RTE_SIO_0_PIN 25 +#define RTE_SIO_0_MUX 1 +#define RTE_SIO_0_PAD 0 //no pad +#elif (RTE_SIO_0_PORT_ID == 2) +#define RTE_SIO_0_PORT 0 +#define RTE_SIO_0_PIN 72 +#define RTE_SIO_0_MUX 1 +#define RTE_SIO_0_PAD 30 +#else +#error "Invalid RTE_SIO_0_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SIO_0_PORT SIO_SIO0_PORT +#define RTE_SIO_0_MUX 1 +#if (SIO_0_LOC == 0) +#define RTE_SIO_0_PIN SIO_SIO0_PIN +#define RTE_SIO_0_PAD 1 +#endif +#if (SIO_0_LOC == 1) +#define RTE_SIO_0_PIN SIO_SIO0_PIN +#define RTE_SIO_0_PAD 0 +#endif +#if (SIO_0_LOC == 2) +#define RTE_SIO_0_PIN (SIO_SIO0_PIN + GPIO_MAX_PIN) +#define RTE_SIO_0_PAD 22 +#endif +#if (SIO_0_LOC == 3) +#define RTE_SIO_0_PIN (SIO_SIO0_PIN + GPIO_MAX_PIN) +#define RTE_SIO_0_PAD 30 +#endif +//Pintool data +#endif + +//SIO_1 <0=>GPIO_7 <1=>GPIO_26 <2=>GPIO_65 <3=>GPIO_73 +#ifndef SIO_1_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_SIO_1_PORT_ID 1 +#else +#define RTE_SIO_1_PORT_ID 0 +#endif + +#if (RTE_SIO_1_PORT_ID == 0) +#define RTE_SIO_1_PORT 0 +#define RTE_SIO_1_PIN 7 +#define RTE_SIO_1_MUX 1 +#define RTE_SIO_1_PAD 2 +#elif (RTE_SIO_1_PORT_ID == 1) +#define RTE_SIO_1_PORT 0 +#define RTE_SIO_1_PIN 26 +#define RTE_SIO_1_MUX 1 +#define RTE_SIO_1_PAD 0 // no pad +#elif (RTE_SIO_1_PORT_ID == 2) +#define RTE_SIO_1_PORT 0 +#define RTE_SIO_1_PIN 65 +#define RTE_SIO_1_MUX 1 +#define RTE_SIO_1_PAD 23 +#elif (RTE_SIO_1_PORT_ID == 3) +#define RTE_SIO_1_PORT 0 +#define RTE_SIO_1_PIN 73 +#define RTE_SIO_1_MUX 1 +#define RTE_SIO_1_PAD 31 +#else +#error "Invalid RTE_SIO_1_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SIO_1_PORT SIO_SIO1_PORT +#define RTE_SIO_1_MUX 1 +#if (SIO_1_LOC == 4) +#define RTE_SIO_1_PIN SIO_SIO1_PIN +#define RTE_SIO_1_PAD 2 +#endif +#if (SIO_1_LOC == 5) +#define RTE_SIO_1_PIN SIO_SIO1_PIN +#define RTE_SIO_1_PAD 0 +#endif +#if (SIO_1_LOC == 6) +#define RTE_SIO_1_PIN (SIO_SIO1_PIN + GPIO_MAX_PIN) +#define RTE_SIO_1_PAD 23 +#endif +#if (SIO_1_LOC == 7) +#define RTE_SIO_1_PIN (SIO_SIO1_PIN + GPIO_MAX_PIN) +#define RTE_SIO_1_PAD 31 +#endif +//Pintool data +#endif + +// SIO_2 <0=>GPIO_8 <1=>GPIO_27 <2=>GPIO_66 <3=>GPIO_74 +#ifndef SIO_2_LOC +#define RTE_SIO_2_PORT_ID 1 + +#if (RTE_SIO_2_PORT_ID == 0) +#define RTE_SIO_2_PORT 0 +#define RTE_SIO_2_PIN 8 +#define RTE_SIO_2_MUX 1 +#define RTE_SIO_2_PAD 3 +#elif (RTE_SIO_2_PORT_ID == 1) +#define RTE_SIO_2_PORT 0 +#define RTE_SIO_2_PIN 27 +#define RTE_SIO_2_MUX 1 +#define RTE_SIO_2_PAD 0 //no pad +#elif (RTE_SIO_2_PORT_ID == 2) +#define RTE_SIO_2_PORT 0 +#define RTE_SIO_2_PIN 66 +#define RTE_SIO_2_MUX 1 +#define RTE_SIO_2_PAD 24 +#elif (RTE_SIO_2_PORT_ID == 3) +#define RTE_SIO_2_PORT 0 +#define RTE_SIO_2_PIN 74 +#define RTE_SIO_2_MUX 1 +#define RTE_SIO_2_PAD 32 +#else +#error "Invalid RTE_SIO_2_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SIO_2_PORT SIO_SIO2_PORT +#define RTE_SIO_2_MUX 1 +#if (SIO_2_LOC == 8) +#define RTE_SIO_2_PIN SIO_SIO2_PIN +#define RTE_SIO_2_PAD 3 +#endif +#if (SIO_2_LOC == 9) +#define RTE_SIO_2_PIN SIO_SIO2_PIN +#define RTE_SIO_2_PAD 0 +#endif +#if (SIO_2_LOC == 10) +#define RTE_SIO_2_PIN (SIO_SIO2_PIN + GPIO_MAX_PIN) +#define RTE_SIO_2_PAD 32 +#endif +//Pintool data +#endif + +//SIO_3 <0=>GPIO_9 <1=>GPIO_28 <2=>GPIO_67 <3=>GPIO_75 +#ifndef SIO_3_LOC +#define RTE_SIO_3_PORT_ID 1 + +#if (RTE_SIO_3_PORT_ID == 0) +#define RTE_SIO_3_PORT 0 +#define RTE_SIO_3_PIN 9 +#define RTE_SIO_3_MUX 1 +#define RTE_SIO_3_PAD 4 +#elif (RTE_SIO_3_PORT_ID == 1) +#define RTE_SIO_3_PORT 0 +#define RTE_SIO_3_PIN 28 +#define RTE_SIO_3_MUX 1 +#define RTE_SIO_3_PAD 0 //no pad +#elif (RTE_SIO_3_PORT_ID == 2) +#define RTE_SIO_3_PORT 0 +#define RTE_SIO_3_PIN 67 +#define RTE_SIO_3_MUX 1 +#define RTE_SIO_3_PAD 25 +#elif (RTE_SIO_3_PORT_ID == 3) +#define RTE_SIO_3_PORT 0 +#define RTE_SIO_3_PIN 75 +#define RTE_SIO_3_MUX 1 +#define RTE_SIO_3_PAD 33 +#else +#error "Invalid RTE_SIO_3_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SIO_3_PORT SIO_SIO3_PORT +#define RTE_SIO_3_MUX 1 +#if (SIO_3_LOC == 11) +#define RTE_SIO_3_PIN SIO_SIO3_PIN +#define RTE_SIO_3_PAD 4 +#endif +#if (SIO_3_LOC == 12) +#define RTE_SIO_3_PIN SIO_SIO3_PIN +#define RTE_SIO_3_PAD 0 +#endif +#if (SIO_3_LOC == 13) +#define RTE_SIO_3_PIN (SIO_SIO3_PIN + GPIO_MAX_PIN) +#define RTE_SIO_3_PAD 33 +#endif +//Pintool data +#endif + +//SIO_4 <0=>GPIO_10 <1=>GPIO_29 <2=>GPIO_68 +#ifndef SIO_4_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_SIO_4_PORT_ID 1 +#else +#define RTE_SIO_4_PORT_ID 0 +#endif +#if (RTE_SIO_4_PORT_ID == 0) +#define RTE_SIO_4_PORT 0 +#define RTE_SIO_4_PIN 10 +#define RTE_SIO_4_MUX 1 +#define RTE_SIO_4_PAD 5 +#elif (RTE_SIO_4_PORT_ID == 1) +#define RTE_SIO_4_PORT 0 +#define RTE_SIO_4_PIN 29 +#define RTE_SIO_4_MUX 1 +#define RTE_SIO_4_PAD 0 //NO PAD +#else +#error "Invalid RTE_SIO_3_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SIO_4_PORT SIO_SIO4_PORT +#define RTE_SIO_4_MUX 1 +#if (SIO_4_LOC == 14) +#define RTE_SIO_4_PAD 5 +#define RTE_SIO_4_PIN SIO_SIO4_PIN +#endif +#if (SIO_4_LOC == 15) +#define RTE_SIO_4_PAD 0 +#define RTE_SIO_4_PIN SIO_SIO4_PIN +#endif +#if (SIO_4_LOC == 16) +#define RTE_SIO_4_PAD 26 +#define RTE_SIO_4_PIN (SIO_SIO4_PIN + GPIO_MAX_PIN) +#endif +//Pintool data +#endif + +// SIO_5 <0=>GPIO_11 <1=>GPIO_30 <2=>GPIO_69 +#ifndef SIO_5_LOC +#define RTE_SIO_5_PORT_ID 0 +#if (RTE_SIO_5_PORT_ID == 0) +#define RTE_SIO_5_PORT 0 +#define RTE_SIO_5_PIN 11 +#define RTE_SIO_5_MUX 1 +#define RTE_SIO_5_PAD 6 +#elif (RTE_SIO_5_PORT_ID == 1) +#define RTE_SIO_5_PORT 0 +#define RTE_SIO_5_PIN 30 +#define RTE_SIO_5_MUX 1 +#define RTE_SIO_5_PAD 0 //no pad +#else +#error "Invalid RTE_SIO_5_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SIO_5_PORT SIO_SIO5_PORT +#define RTE_SIO_5_MUX 1 +#if (SIO_5_LOC == 17) +#define RTE_SIO_5_PAD 6 +#define RTE_SIO_5_PIN SIO_SIO5_PIN +#endif +#if (SIO_5_LOC == 18) +#define RTE_SIO_5_PAD 0 +#define RTE_SIO_5_PIN SIO_SIO5_PIN +#endif +#if (SIO_5_LOC == 19) +#define RTE_SIO_5_PAD 0 +#define RTE_SIO_5_PIN (SIO_SIO5_PIN + GPIO_MAX_PIN) +#endif +//Pintool data +#endif + +// SIO_6 GPIO_70 +#ifndef SIO_6_LOC +#define RTE_SIO_6_PORT 0 +#define RTE_SIO_6_PIN 70 +#else +#define RTE_SIO_6_PORT SIO_SIO6_PORT +#define RTE_SIO_6_PIN (SIO_SIO6_PIN + GPIO_MAX_PIN) +#endif +#define RTE_SIO_6_MUX 1 +#define RTE_SIO_6_PAD 28 + +// SIO_7 <0=>GPIO_15 <1=>GPIO_71 +#ifndef SIO_7_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_SIO_7_PORT_ID 1 +#else +#define RTE_SIO_7_PORT_ID 0 +#endif + +#if (RTE_SIO_7_PORT_ID == 0) +#define RTE_SIO_7_PORT 0 +#define RTE_SIO_7_PIN 15 +#define RTE_SIO_7_MUX 1 +#define RTE_SIO_7_PAD 8 +#elif (RTE_SIO_7_PORT_ID == 1) +#define RTE_SIO_7_PORT 0 +#define RTE_SIO_7_PIN 71 +#define RTE_SIO_7_MUX 1 +#define RTE_SIO_7_PAD 29 +#else +#error "Invalid RTE_SIO_7_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_SIO_7_PORT SIO_SIO7_PORT +#define RTE_SIO_7_MUX 1 +#if (SIO_7_LOC == 21) +#define RTE_SIO_7_PIN SIO_SIO7_PIN +#define RTE_SIO_7_PAD 8 +#endif +#if (SIO_7_LOC == 22) +#define RTE_SIO_7_PIN (SIO_SIO7_PIN + GPIO_MAX_PIN) +#define RTE_SIO_7_PAD 29 +#endif +//Pintool data +#endif + +//<> Pulse Width Modulation +//PWM_1H <0=>GPIO_7 <1=>GPIO_64 <2=>GPIO_65 +#ifndef PWM_1H_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_PWM_1H_PORT_ID 0 +#else +#define RTE_PWM_1H_PORT_ID 0 +#endif + +#if (RTE_PWM_1H_PORT_ID == 0) +#define RTE_PWM_1H_PORT 0 +#define RTE_PWM_1H_PIN 7 +#define RTE_PWM_1H_MUX 10 +#define RTE_PWM_1H_PAD 2 +#elif (RTE_PWM_1H_PORT_ID == 1) +#define RTE_PWM_1H_PORT 0 +#define RTE_PWM_1H_PIN 65 +#define RTE_PWM_1H_MUX 8 +#define RTE_PWM_1H_PAD 22 +#else +#error "Invalid RTE_PWM_1H_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_PWM_1H_PORT PWM_1H_PORT +#if (PWM_1H_LOC == 0) +#define RTE_PWM_1H_PIN PWM_1H_PIN +#define RTE_PWM_1H_MUX 10 +#define RTE_PWM_1H_PAD 2 +#endif +#if (PWM_1H_LOC == 1) +#define RTE_PWM_1H_PIN (PWM_1H_PIN + GPIO_MAX_PIN) +#define RTE_PWM_1H_MUX 8 +#define RTE_PWM_1H_PAD 22 +#endif +//Pintool data +#endif + +// PWM_1L <0=>GPIO_6 <1=>GPIO_64 <2=>GPIO_64 +#ifndef PWM_1L_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_PWM_1L_PORT_ID 0 +#else +#define RTE_PWM_1L_PORT_ID 1 +#endif + +#if (RTE_PWM_1L_PORT_ID == 0) +#define RTE_PWM_1L_PORT 0 +#define RTE_PWM_1L_PIN 6 +#define RTE_PWM_1L_MUX 10 +#define RTE_PWM_1L_PAD 1 +#else +#error "Invalid RTE_PWM_1L_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_PWM_1L_PORT PWM_1L_PORT +#if (PWM_1L_LOC == 2) +#define RTE_PWM_1L_PIN PWM_1L_PIN +#define RTE_PWM_1L_MUX 10 +#define RTE_PWM_1L_PAD 1 +#elif (PWM_1L_LOC == 3) +#define RTE_PWM_1L_PIN (PWM_1L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_1L_MUX 8 +#define RTE_PWM_1L_PAD 22 +#endif +//Pintool data +#endif + +//PWM_2H <0=>GPIO_9 <1=>GPIO_67 <2=>GPIO_69 +#ifndef PWM_2H_LOC +#define RTE_PWM_2H_PORT_ID 0 +#if ((RTE_PWM_2H_PORT_ID == 2)) +#error "Invalid RTE_PWM_2H_PIN pin Configuration!" +#endif + +#if (RTE_PWM_2H_PORT_ID == 0) +#define RTE_PWM_2H_PORT 0 +#define RTE_PWM_2H_PIN 9 +#define RTE_PWM_2H_MUX 10 +#define RTE_PWM_2H_PAD 4 +#elif (RTE_PWM_2H_PORT_ID == 1) +#define RTE_PWM_2H_PORT 0 +#define RTE_PWM_2H_PIN 67 +#define RTE_PWM_2H_MUX 8 +#define RTE_PWM_2H_PAD 25 +#else +#error "Invalid RTE_PWM_2H_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_PWM_2H_PORT PWM_2H_PORT +#if (PWM_2H_LOC == 4) +#define RTE_PWM_2H_PIN PWM_2H_PIN +#define RTE_PWM_2H_MUX 10 +#define RTE_PWM_2H_PAD 4 +#endif +#if (PWM_2H_LOC == 5) +#define RTE_PWM_2H_PIN (PWM_2H_PIN + GPIO_MAX_PIN) +#define RTE_PWM_2H_MUX 12 +#define RTE_PWM_2H_PAD 27 +#endif +//Pintool data +#endif + +// PWM_2L <0=>GPIO_8 <1=>GPIO_66 <2=>GPIO_68 +#ifndef PWM_2L_LOC +#define RTE_PWM_2L_PORT_ID 0 +#if ((RTE_PWM_2L_PORT_ID == 2)) +#error "Invalid RTE_PWM_2L_PIN pin Configuration!" +#endif + +#if (RTE_PWM_2L_PORT_ID == 0) +#define RTE_PWM_2L_PORT 0 +#define RTE_PWM_2L_PIN 8 +#define RTE_PWM_2L_MUX 10 +#define RTE_PWM_2L_PAD 3 +#elif (RTE_PWM_2L_PORT_ID == 1) +#define RTE_PWM_2L_PORT 0 +#define RTE_PWM_2L_PIN 66 +#define RTE_PWM_2L_MUX 8 +#define RTE_PWM_2L_PAD 24 +#else +#error "Invalid RTE_PWM_2L_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_PWM_2L_PORT PWM_2L_PORT +#if (PWM_2L_LOC == 6) +#define RTE_PWM_2L_PIN PWM_2L_PIN +#define RTE_PWM_2L_MUX 10 +#define RTE_PWM_2L_PAD 3 +#endif +#if (PWM_2L_LOC == 7) +#define RTE_PWM_2L_PIN (PWM_2L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_2L_MUX 8 +#define RTE_PWM_2L_PAD 24 +#endif +#if (PWM_2L_LOC == 8) +#define RTE_PWM_2L_PIN (PWM_2L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_2L_MUX 12 +#define RTE_PWM_2L_PAD 26 +#endif +//Pintool data +#endif + +// PWM_3H <0=>GPIO_11 <1=>GPIO_69 +#ifndef PWM_3H_LOC +#define RTE_PWM_3H_PORT_ID 0 +#if (RTE_PWM_3H_PORT_ID == 0) +#define RTE_PWM_3H_PORT 0 +#define RTE_PWM_3H_PIN 11 +#define RTE_PWM_3H_MUX 10 +#define RTE_PWM_3H_PAD 6 +#else +#error "Invalid RTE_PWM_3H_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_PWM_3H_PORT PWM_3H_PORT +#if (PWM_3H_LOC == 9) +#define RTE_PWM_3H_PIN PWM_3H_PIN +#define RTE_PWM_3H_MUX 10 +#define RTE_PWM_3H_PAD 6 +#elif (PWM_3H_LOC == 10) +#define RTE_PWM_3H_PIN (PWM_3H_PIN + GPIO_MAX_PIN) +#define RTE_PWM_3H_MUX 8 +#define RTE_PWM_3H_PAD 27 +#endif +//Pintool data +#endif + +// PWM_3L <0=>GPIO_10 <1=>GPIO_68 +#ifndef PWM_3L_LOC +#define RTE_PWM_3L_PORT_ID 0 + +#if (RTE_PWM_3L_PORT_ID == 0) +#define RTE_PWM_3L_PORT 0 +#define RTE_PWM_3L_PIN 10 +#define RTE_PWM_3L_MUX 10 +#define RTE_PWM_3L_PAD 5 +#else +#error "Invalid RTE_PWM_3L_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_PWM_3L_PORT PWM_3L_PORT +#if (PWM_3L_LOC == 11) +#define RTE_PWM_3L_PIN PWM_3L_PIN +#define RTE_PWM_3L_MUX 10 +#define RTE_PWM_3L_PAD 5 +#elif (PWM_3L_LOC == 12) +#define RTE_PWM_3L_PIN (PWM_3L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_3L_MUX 8 +#define RTE_PWM_3L_PAD 26 +#endif +//Pintool data +#endif + +// PWM_4H <0=>GPIO_15 <1=>GPIO_71 +#ifndef PWM_4H_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_PWM_4H_PORT_ID 1 +#else +#define RTE_PWM_4H_PORT_ID 0 +#endif + +#if (RTE_PWM_4H_PORT_ID == 0) +#define RTE_PWM_4H_PORT 0 +#define RTE_PWM_4H_PIN 15 +#define RTE_PWM_4H_MUX 10 +#define RTE_PWM_4H_PAD 8 +#elif (RTE_PWM_4H_PORT_ID == 1) +#define RTE_PWM_4H_PORT 0 +#define RTE_PWM_4H_PIN 71 +#define RTE_PWM_4H_MUX 8 +#define RTE_PWM_4H_PAD 29 +#else +#error "Invalid RTE_PWM_4H_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_PWM_4H_PORT PWM_4H_PORT +#define RTE_PWM_4H_PIN (PWM_4H_PIN + GPIO_MAX_PIN) +#define RTE_PWM_4H_MUX 8 +#define RTE_PWM_4H_PAD 29 +//Pintool data +#endif + +// PWM_4H <0=>GPIO_12 <1=>GPIO_70 +#ifndef PWM_4L_LOC +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_PWM_4L_PORT_ID 1 +#else +#define RTE_PWM_4L_PORT_ID 0 +#endif + +#if (RTE_PWM_4L_PORT_ID == 0) +#define RTE_PWM_4L_PORT 0 +#define RTE_PWM_4L_PIN 12 +#define RTE_PWM_4L_MUX 10 +#define RTE_PWM_4L_PAD 7 +#elif (RTE_PWM_4L_PORT_ID == 1) +#define RTE_PWM_4L_PORT 0 +#define RTE_PWM_4L_PIN 70 +#define RTE_PWM_4L_MUX 8 +#define RTE_PWM_4L_PAD 28 +#else +#error "Invalid RTE_PWM_4L_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_PWM_4L_PORT PWM_4L_PORT +#if (PWM_4L_LOC == 14) +#define RTE_PWM_4L_PIN PWM_4L_PIN +#define RTE_PWM_4L_MUX 10 +#define RTE_PWM_4L_PAD 7 +#endif +#if (PWM_4L_LOC == 15) +#define RTE_PWM_4L_PIN (PWM_4L_PIN + GPIO_MAX_PIN) +#define RTE_PWM_4L_MUX 8 +#define RTE_PWM_4L_PAD 28 +#endif +//Pintool data +#endif + +// PWM_FAULTA <0=>GPIO_25 <1=>GPIO_68 <1=>GPIO_73 +#ifndef PWM_FAULTA_LOC +#define RTE_PWM_FAULTA_PORT_ID 0 + +#if (RTE_PWM_FAULTA_PORT_ID == 0) +#define RTE_PWM_FAULTA_PORT 0 +#define RTE_PWM_FAULTA_PIN 25 +#define RTE_PWM_FAULTA_MUX 10 +#define RTE_PWM_FAULTA_PAD 0 //no pad +#elif (RTE_PWM_FAULTA_PORT_ID == 2) +#define RTE_PWM_FAULTA_PORT 0 +#define RTE_PWM_FAULTA_PIN 73 +#define RTE_PWM_FAULTA_MUX 8 +#define RTE_PWM_FAULTA_PAD 31 +#else +#error "Invalid RTE_PWM_FAULTA_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_PWM_FAULTA_PORT PWM_FAULTA_PORT +#if (PWM_FAULTA_LOC == 16) +#define RTE_PWM_FAULTA_PIN PWM_FAULTA_PIN +#define RTE_PWM_FAULTA_MUX 10 +#define RTE_PWM_FAULTA_PAD 0 //no pad +#endif +#if (PWM_FAULTA_LOC == 17) +#define RTE_PWM_FAULTA_PIN (PWM_FAULTA_PIN + GPIO_MAX_PIN) +#define RTE_PWM_FAULTA_MUX 10 +#define RTE_PWM_FAULTA_PAD 26 +#endif +#if (PWM_FAULTA_LOC == 18) +#define RTE_PWM_FAULTA_PIN (PWM_FAULTA_PIN + GPIO_MAX_PIN) +#define RTE_PWM_FAULTA_MUX 8 +#define RTE_PWM_FAULTA_PAD 31 +#endif +//Pintool data +#endif + +// PWM_FAULTB <0=>GPIO_26 <1=>GPIO_69 <1=>GPIO_74 +#ifndef PWM_FAULTB_LOC +#define RTE_PWM_FAULTB_PORT_ID 0 + +#if (RTE_PWM_FAULTB_PORT_ID == 0) +#define RTE_PWM_FAULTB_PORT 0 +#define RTE_PWM_FAULTB_PIN 26 +#define RTE_PWM_FAULTB_MUX 10 +#define RTE_PWM_FAULTB_PAD 0 //no pad +#elif (RTE_PWM_FAULTB_PORT_ID == 2) +#define RTE_PWM_FAULTB_PORT 0 +#define RTE_PWM_FAULTB_PIN 74 +#define RTE_PWM_FAULTB_MUX 8 +#define RTE_PWM_FAULTB_PAD 32 +#else +#error "Invalid RTE_PWM_FAULTB_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_PWM_FAULTB_PORT PWM_FAULTB_PORT +#if (PWM_FAULTB_LOC == 19) +#define RTE_PWM_FAULTB_PIN PWM_FAULTB_PIN +#define RTE_PWM_FAULTB_MUX 10 +#define RTE_PWM_FAULTB_PAD 0 //no pad +#endif +#if (PWM_FAULTB_LOC == 20) +#define RTE_PWM_FAULTB_PIN (PWM_FAULTB_PIN + GPIO_MAX_PIN) +#define RTE_PWM_FAULTB_MUX 10 +#define RTE_PWM_FAULTB_PAD 27 +#endif +#if (PWM_FAULTB_LOC == 21) +#define RTE_PWM_FAULTB_PIN (PWM_FAULTB_PIN + GPIO_MAX_PIN) +#define RTE_PWM_FAULTB_MUX 8 +#define RTE_PWM_FAULTB_PAD 32 +#endif +//Pintool data +#endif + +//PWM_SLP_EVENT_TRIG GPIO_72 +#ifndef PWM_EVTTRIG_LOC +#define RTE_PWM_SLP_EVENT_TRIG_PORT 0 +#define RTE_PWM_SLP_EVENT_TRIG_PIN 72 +#else +//Pintool data +#define RTE_PWM_SLP_EVENT_TRIG_PORT PWM_SLEEP_EVT_TRIG_PORT +#define RTE_PWM_SLP_EVENT_TRIG_PIN (PWM_SLEEP_EVT_TRIG_PIN + GPIO_MAX_PIN) +//Pintool data +#endif +#define RTE_PWM_SLP_EVENT_TRIG_MUX 8 +#define RTE_PWM_SLP_EVENT_TRIG_PAD 30 + +//PWM_TMR_EXT_TRIG_1 <0=>GPIO_27 <1=>GPIO_51 <2=>GPIO_70 <3=>GPIO_75 +#ifndef PWM_EXTTRIG1_LOC +#define RTE_PWM_TMR_EXT_TRIG_1_PORT_ID 0 + +#if (RTE_PWM_TMR_EXT_TRIG_1_PORT_ID == 0) +#define RTE_PWM_TMR_EXT_TRIG_1_PORT 0 +#define RTE_PWM_TMR_EXT_TRIG_1_PIN 27 +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 0 //no pad +#elif (RTE_PWM_TMR_EXT_TRIG_1_PORT_ID == 1) +#define RTE_PWM_TMR_EXT_TRIG_1_PORT 0 +#define RTE_PWM_TMR_EXT_TRIG_1_PIN 51 +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 15 +#elif (RTE_PWM_TMR_EXT_TRIG_1_PORT_ID == 2) +#define RTE_PWM_TMR_EXT_TRIG_1_PORT 0 +#define RTE_PWM_TMR_EXT_TRIG_1_PIN 70 +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 28 +#elif (RTE_PWM_TMR_EXT_TRIG_1_PORT_ID == 3) +#define RTE_PWM_TMR_EXT_TRIG_1_PORT 0 +#define RTE_PWM_TMR_EXT_TRIG_1_PIN 75 +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 33 +#else +#error "Invalid RTE_PWM_TMR_EXT_TRIG_1_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_PWM_TMR_EXT_TRIG_1_PORT PWM_TMR_EXT_TRIG_1_PORT +#if (PWM_EXTTRIG1_LOC == 22) +#define RTE_PWM_TMR_EXT_TRIG_1_PIN PWM_TMR_EXT_TRIG_1_PIN +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 0 //no pad +#endif +#if (PWM_EXTTRIG1_LOC == 23) +#define RTE_PWM_TMR_EXT_TRIG_1_PIN PWM_TMR_EXT_TRIG_1_PIN +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 15 +#endif +#if (PWM_EXTTRIG1_LOC == 24) +#define RTE_PWM_TMR_EXT_TRIG_1_PIN (PWM_TMR_EXT_TRIG_1_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 28 +#endif +#if (PWM_EXTTRIG1_LOC == 25) +#define RTE_PWM_TMR_EXT_TRIG_1_PIN (PWM_TMR_EXT_TRIG_1_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 33 +#endif +//Pintool data +#endif + +//PWM_TMR_EXT_TRIG_2 <0=>GPIO_28 <1=>GPIO_54 <2=>GPIO_71 +#ifndef PWM_EXTTRIG2_LOC +#define RTE_PWM_TMR_EXT_TRIG_2_PORT_ID 0 + +#if (RTE_PWM_TMR_EXT_TRIG_2_PORT_ID == 0) +#define RTE_PWM_TMR_EXT_TRIG_2_PORT 0 +#define RTE_PWM_TMR_EXT_TRIG_2_PIN 28 +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 0 //no pad +#elif (RTE_PWM_TMR_EXT_TRIG_2_PORT_ID == 1) +#define RTE_PWM_TMR_EXT_TRIG_2_PORT 0 +#define RTE_PWM_TMR_EXT_TRIG_2_PIN 54 +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 18 +#elif (RTE_PWM_TMR_EXT_TRIG_2_PORT_ID == 2) +#define RTE_PWM_TMR_EXT_TRIG_2_PORT 0 +#define RTE_PWM_TMR_EXT_TRIG_2_PIN 71 +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 29 +#else +#error "Invalid RTE_PWM_TMR_EXT_TRIG_2_PIN Pin Configuration!" +#endif +#else +//Pintool data +#define RTE_PWM_TMR_EXT_TRIG_2_PORT PWM_TMR_EXT_TRIG_2_PORT +#if (PWM_EXTTRIG2_LOC == 26) +#define RTE_PWM_TMR_EXT_TRIG_2_PIN PWM_TMR_EXT_TRIG_2_PIN +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 0 //no pad +#endif +#if (PWM_EXTTRIG2_LOC == 27) +#define RTE_PWM_TMR_EXT_TRIG_2_PIN PWM_TMR_EXT_TRIG_2_PIN +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 18 +#endif +#if (PWM_EXTTRIG2_LOC == 28) //Combination not available in pin mux +#define RTE_PWM_TMR_EXT_TRIG_2_PIN (PWM_TMR_EXT_TRIG_2_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 29 +#endif +#if (PWM_EXTTRIG2_LOC == 29) +#define RTE_PWM_TMR_EXT_TRIG_2_PIN (PWM_TMR_EXT_TRIG_2_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 29 +#endif +//Pintool data +#endif + +//PWM_TMR_EXT_TRIG_3 +//Pintool data +#define RTE_PWM_TMR_EXT_TRIG_3_PORT PWM_TMR_EXT_TRIG_3_PORT +#if (PWM_EXTTRIG3_LOC == 30) +#define RTE_PWM_TMR_EXT_TRIG_3_PIN PWM_TMR_EXT_TRIG_3_PIN +#define RTE_PWM_TMR_EXT_TRIG_3_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_3_PAD 0 //no pad +#endif +#if (PWM_EXTTRIG3_LOC == 31) +#define RTE_PWM_TMR_EXT_TRIG_3_PIN PWM_TMR_EXT_TRIG_3_PIN +#define RTE_PWM_TMR_EXT_TRIG_3_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_3_PAD 19 +#endif +#if (PWM_EXTTRIG3_LOC == 32) +#define RTE_PWM_TMR_EXT_TRIG_3_PIN (PWM_TMR_EXT_TRIG_3_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_3_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_3_PAD 30 +#endif +//Pintool data + +//PWM_TMR_EXT_TRIG_4 +//Pintool data +#define RTE_PWM_TMR_EXT_TRIG_4_PORT PWM_TMR_EXT_TRIG_4_PORT +#if (PWM_EXTTRIG4_LOC == 33) +#define RTE_PWM_TMR_EXT_TRIG_4_PIN PWM_TMR_EXT_TRIG_4_PIN +#define RTE_PWM_TMR_EXT_TRIG_4_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_4_PAD 0 //no pad +#endif +#if (PWM_EXTTRIG4_LOC == 34) +#define RTE_PWM_TMR_EXT_TRIG_4_PIN PWM_TMR_EXT_TRIG_4_PIN +#define RTE_PWM_TMR_EXT_TRIG_4_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_4_PAD 14 +#endif +#if (PWM_EXTTRIG4_LOC == 35) +#define RTE_PWM_TMR_EXT_TRIG_4_PIN (PWM_TMR_EXT_TRIG_4_PIN + GPIO_MAX_PIN) +#define RTE_PWM_TMR_EXT_TRIG_4_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_4_PAD 31 +#endif +//Pintool data + +//<> QEI (Quadrature Encode Interface) + +//QEI_DIR <0=>GPIO_28 <1=>GPIO_49 <2=>GPIO_57 <3=>GPIO_67 <4=>GPIO_71 <5=>GPIO_73 <6=>GPIO_11 <7=>GPIO_34 + +#define RTE_QEI_DIR_PORT_ID 4 + +#if (RTE_QEI_DIR_PORT_ID == 0) +#define RTE_QEI_DIR_PORT 0 +#define RTE_QEI_DIR_PIN 28 +#define RTE_QEI_DIR_MUX 5 +#define RTE_QEI_DIR_PAD 0 //no pad +#elif (RTE_QEI_DIR_PORT_ID == 1) +#define RTE_QEI_DIR_PORT 0 +#define RTE_QEI_DIR_PIN 49 +#define RTE_QEI_DIR_MUX 3 +#define RTE_QEI_DIR_PAD 13 +#elif (RTE_QEI_DIR_PORT_ID == 2) +#define RTE_QEI_DIR_PORT 0 +#define RTE_QEI_DIR_PIN 57 +#define RTE_QEI_DIR_MUX 5 +#define RTE_QEI_DIR_PAD 21 +#elif (RTE_QEI_DIR_PORT_ID == 3) +#define RTE_QEI_DIR_PORT 0 +#define RTE_QEI_DIR_PIN 67 +#define RTE_QEI_DIR_MUX 3 +#define RTE_QEI_DIR_PAD 25 +#elif (RTE_QEI_DIR_PORT_ID == 4) +#define RTE_QEI_DIR_PORT 0 +#define RTE_QEI_DIR_PIN 71 +#define RTE_QEI_DIR_MUX 3 +#define RTE_QEI_DIR_PAD 29 +#elif (RTE_QEI_DIR_PORT_ID == 5) +#define RTE_QEI_DIR_PORT 0 +#define RTE_QEI_DIR_PIN 73 +#define RTE_QEI_DIR_MUX 3 +#define RTE_QEI_DIR_PAD 31 +#else +#error "Invalid RTE_QEI_DIR_PIN Pin Configuration!" +#endif + +//QEI_IDX <0=>GPIO_25 <1=>GPIO_46 <2=>GPIO_52 <3=>GPIO_64 <4=>GPIO_68 <5=>GPIO_72 <6=>GPIO_8 <7=>GPIO_13 + +#define RTE_QEI_IDX_PORT_ID 3 + +#if (RTE_QEI_IDX_PORT_ID == 0) +#define RTE_QEI_IDX_PORT 0 +#define RTE_QEI_IDX_PIN 25 +#define RTE_QEI_IDX_MUX 5 +#define RTE_QEI_IDX_PAD 0 //no pad +#elif (RTE_QEI_IDX_PORT_ID == 1) +#define RTE_QEI_IDX_PORT 0 +#define RTE_QEI_IDX_PIN 46 +#define RTE_QEI_IDX_MUX 3 +#define RTE_QEI_IDX_PAD 10 +#elif (RTE_QEI_IDX_PORT_ID == 2) +#define RTE_QEI_IDX_PORT 0 +#define RTE_QEI_IDX_PIN 52 +#define RTE_QEI_IDX_MUX 5 +#define RTE_QEI_IDX_PAD 16 +#elif (RTE_QEI_IDX_PORT_ID == 3) +#define RTE_QEI_IDX_PORT 0 +#define RTE_QEI_IDX_PIN 72 +#define RTE_QEI_IDX_MUX 3 +#define RTE_QEI_IDX_PAD 30 +#else +#error "Invalid RTE_QEI_IDX_PIN Pin Configuration!" +#endif + +//QEI_PHA <0=>GPIO_26 <1=>GPIO_47 <2=>GPIO_53 <3=>GPIO_65 <4=>GPIO_69 <5=>GPIO_73 <6=>GPIO_9 <7=>GPIO_32 + +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_QEI_PHA_PORT_ID 3 +#else +#define RTE_QEI_PHA_PORT_ID 5 +#endif + +#if (RTE_QEI_PHA_PORT_ID == 0) +#define RTE_QEI_PHA_PORT 0 +#define RTE_QEI_PHA_PIN 26 +#define RTE_QEI_PHA_MUX 5 +#define RTE_QEI_PHA_PAD 0 //no pad +#elif (RTE_QEI_PHA_PORT_ID == 1) +#define RTE_QEI_PHA_PORT 0 +#define RTE_QEI_PHA_PIN 47 +#define RTE_QEI_PHA_MUX 3 +#define RTE_QEI_PHA_PAD 11 +#elif (RTE_QEI_PHA_PORT_ID == 2) +#define RTE_QEI_PHA_PORT 0 +#define RTE_QEI_PHA_PIN 53 +#define RTE_QEI_PHA_MUX 5 +#define RTE_QEI_PHA_PAD 17 +#elif (RTE_QEI_PHA_PORT_ID == 3) +#define RTE_QEI_PHA_PORT 0 +#define RTE_QEI_PHA_PIN 65 +#define RTE_QEI_PHA_MUX 3 +#define RTE_QEI_PHA_PAD 23 +#elif (RTE_QEI_PHA_PORT_ID == 4) +#define RTE_QEI_PHA_PORT 0 +#define RTE_QEI_PHA_PIN 73 +#define RTE_QEI_PHA_MUX 3 +#define RTE_QEI_PHA_PAD 31 +#else +#error "Invalid RTE_QEI_PHA_PIN Pin Configuration!" +#endif + +//QEI_PHB <0=>GPIO_27 <1=>GPIO_48 <1=>GPIO_56 <1=>GPIO_66 <1=>GPIO_70 <1=>GPIO_74 <7=>GPIO_33 + +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_QEI_PHB_PORT_ID 5 +#else +#define RTE_QEI_PHB_PORT_ID 4 +#endif + +#if (RTE_QEI_PHB_PORT_ID == 0) +#define RTE_QEI_PHB_PORT 0 +#define RTE_QEI_PHB_PIN 27 +#define RTE_QEI_PHB_MUX 5 +#define RTE_QEI_PHB_PAD 0 //no pad +#elif (RTE_QEI_PHB_PORT_ID == 1) +#define RTE_QEI_PHB_PORT 0 +#define RTE_QEI_PHB_PIN 48 +#define RTE_QEI_PHB_MUX 3 +#define RTE_QEI_PHB_PAD 12 +#elif (RTE_QEI_PHB_PORT_ID == 2) +#define RTE_QEI_PHB_PORT 0 +#define RTE_QEI_PHB_PIN 56 +#define RTE_QEI_PHB_MUX 5 +#define RTE_QEI_PHB_PAD 20 +#elif (RTE_QEI_PHB_PORT_ID == 3) +#define RTE_QEI_PHB_PORT 0 +#define RTE_QEI_PHB_PIN 66 +#define RTE_QEI_PHB_MUX 3 +#define RTE_QEI_PHB_PAD 24 +#elif (RTE_QEI_PHB_PORT_ID == 4) +#define RTE_QEI_PHB_PORT 0 +#define RTE_QEI_PHB_PIN 70 +#define RTE_QEI_PHB_MUX 3 +#define RTE_QEI_PHB_PAD 28 +#elif (RTE_QEI_PHB_PORT_ID == 5) +#define RTE_QEI_PHB_PORT 0 +#define RTE_QEI_PHB_PIN 74 +#define RTE_QEI_PHB_MUX 3 +#define RTE_QEI_PHB_PAD 32 +#else +#error "Invalid RTE_QEI_PHB_PIN Pin Configuration!" +#endif + +#endif + +//ADC START + +#ifndef ADC_P0_LOC +#define RTE_ADC_P0_PORT 0 +#define RTE_ADC_P0_PIN 0 +#else +#define RTE_ADC_P0_PORT ADC_P0_PORT +#define RTE_ADC_P0_PIN ADC_P0_PIN +#endif +#define RTE_ADC_P0_MUX 1 + +#ifndef ADC_N0_LOC +#define RTE_ADC_N0_PORT 0 +#define RTE_ADC_N0_PIN 1 +#else +#define RTE_ADC_N0_PORT ADC_N0_PORT +#define RTE_ADC_N0_PIN ADC_N0_PIN +#endif +#define RTE_ADC_N0_MUX 1 + +#ifndef ADC_P1_LOC +#define RTE_ADC_P1_PORT 0 +#define RTE_ADC_P1_PIN 2 +#else +#define RTE_ADC_P1_PORT ADC_P1_PORT +#define RTE_ADC_P1_PIN ADC_P1_PIN +#endif +#define RTE_ADC_P1_MUX 1 + +#ifndef ADC_N1_LOC +#define RTE_ADC_N1_PORT 0 +#define RTE_ADC_N1_PIN 3 +#else +#define RTE_ADC_N1_PORT ADC_N1_PORT +#define RTE_ADC_N1_PIN ADC_N1_PIN +#endif +#define RTE_ADC_N1_MUX 1 + +#ifndef ADC_P2_LOC +#define RTE_ADC_P2_PORT 0 +#define RTE_ADC_P2_PIN 4 +#else +#define RTE_ADC_P2_PORT ADC_P2_PORT +#define RTE_ADC_P2_PIN ADC_P2_PIN +#endif +#define RTE_ADC_P2_MUX 1 + +#ifndef ADC_N2_LOC +#define RTE_ADC_N2_PORT 0 +#define RTE_ADC_N2_PIN 5 +#else +#define RTE_ADC_N2_PORT ADC_N2_PORT +#define RTE_ADC_N2_PIN ADC_N2_PIN +#endif +#define RTE_ADC_N2_MUX 1 + +#ifndef ADC_P3_LOC +#define RTE_ADC_P3_PORT 0 +#define RTE_ADC_P3_PIN 6 +#else +#define RTE_ADC_P3_PORT ADC_P3_PORT +#define RTE_ADC_P3_PIN ADC_P3_PIN +#endif +#define RTE_ADC_P3_MUX 1 + +#ifndef ADC_N3_LOC +#define RTE_ADC_N3_PORT 0 +#define RTE_ADC_N3_PIN 11 +#else +#define RTE_ADC_N3_PORT ADC_N3_PORT +#define RTE_ADC_N3_PIN ADC_N3_PIN +#endif +#define RTE_ADC_N3_MUX 1 + +#ifndef ADC_P4_LOC +#define RTE_ADC_P4_PORT 0 +#define RTE_ADC_P4_PIN 8 +#else +#define RTE_ADC_P4_PORT ADC_P4_PORT +#define RTE_ADC_P4_PIN ADC_P4_PIN +#endif +#define RTE_ADC_P4_MUX 1 + +#ifndef ADC_N4_LOC +#define RTE_ADC_N4_PORT 0 +#define RTE_ADC_N4_PIN 9 +#else +#define RTE_ADC_N4_PORT ADC_N4_PORT +#define RTE_ADC_N4_PIN ADC_N4_PIN +#endif +#define RTE_ADC_N4_MUX 1 + +#ifndef ADC_P5_LOC +#define RTE_ADC_P5_PORT 0 +#define RTE_ADC_P5_PIN 10 +#else +#define RTE_ADC_P5_PORT ADC_P5_PORT +#define RTE_ADC_P5_PIN ADC_P5_PIN +#endif +#define RTE_ADC_P5_MUX 1 + +#ifndef ADC_N5_LOC +#define RTE_ADC_N5_PORT 0 +#define RTE_ADC_N5_PIN 7 +#else +#define RTE_ADC_N5_PORT ADC_N5_PORT +#define RTE_ADC_N5_PIN ADC_N5_PIN +#endif +#define RTE_ADC_N5_MUX 1 + +#ifndef ADC_P6_LOC +#define RTE_ADC_P6_PORT 0 +#define RTE_ADC_P6_PIN 25 +#else +#define RTE_ADC_P6_PORT ADC_P6_PORT +#define RTE_ADC_P6_PIN ADC_P6_PIN +#endif +#define RTE_ADC_P6_MUX 1 +#define RTE_ADC_P6_PAD 0 + +#ifndef ADC_N6_LOC +#define RTE_ADC_N6_PORT 0 +#define RTE_ADC_N6_PIN 26 +#else +#define RTE_ADC_N6_PORT ADC_N6_PORT +#define RTE_ADC_N6_PIN ADC_N6_PIN +#endif +#define RTE_ADC_N6_MUX 1 +#define RTE_ADC_N6_PAD 0 + +#ifndef ADC_P7_LOC +#define RTE_ADC_P7_PORT 0 +#define RTE_ADC_P7_PIN 27 +#else +#define RTE_ADC_P7_PORT ADC_P7_PORT +#define RTE_ADC_P7_PIN ADC_P7_PIN +#endif +#define RTE_ADC_P7_MUX 1 +#define RTE_ADC_P7_PAD 0 + +#ifndef ADC_N7_LOC +#define RTE_ADC_N7_PORT 0 +#define RTE_ADC_N7_PIN 28 +#else +#define RTE_ADC_N7_PORT ADC_N7_PORT +#define RTE_ADC_N7_PIN ADC_N7_PIN +#endif +#define RTE_ADC_N7_MUX 1 +#define RTE_ADC_N7_PAD 0 + +#ifndef ADC_P8_LOC +#define RTE_ADC_P8_PORT 0 +#define RTE_ADC_P8_PIN 29 +#else +#define RTE_ADC_P8_PORT ADC_P8_PORT +#define RTE_ADC_P8_PIN ADC_P8_PIN +#endif +#define RTE_ADC_P8_MUX 1 +#define RTE_ADC_P8_PAD 0 + +#ifndef ADC_N8_LOC +#define RTE_ADC_N8_PORT 0 +#define RTE_ADC_N8_PIN 30 +#else +#define RTE_ADC_N8_PORT ADC_N8_PORT +#define RTE_ADC_N8_PIN ADC_N8_PIN +#endif +#define RTE_ADC_N8_MUX 1 +#define RTE_ADC_N8_PAD 0 + +#ifndef ADC_P10_LOC +#define RTE_ADC_P10_PORT 0 +#define RTE_ADC_P10_PIN 1 +#else +#define RTE_ADC_P10_PORT ADC_P10_PORT +#define RTE_ADC_P10_PIN ADC_P10_PIN +#endif +#define RTE_ADC_P10_MUX 1 + +#ifndef ADC_P11_LOC +#define RTE_ADC_P11_PORT 0 +#define RTE_ADC_P11_PIN 3 +#else +#define RTE_ADC_P11_PORT ADC_P11_PORT +#define RTE_ADC_P11_PIN ADC_P11_PIN +#endif +#define RTE_ADC_P11_MUX 1 + +#ifndef ADC_P12_LOC +#define RTE_ADC_P12_PORT 0 +#define RTE_ADC_P12_PIN 5 +#else +#define RTE_ADC_P12_PORT ADC_P12_PORT +#define RTE_ADC_P12_PIN ADC_P12_PIN +#endif +#define RTE_ADC_P12_MUX 1 + +#ifndef ADC_P13_LOC +#define RTE_ADC_P13_PORT 0 +#define RTE_ADC_P13_PIN 11 +#else +#define RTE_ADC_P13_PORT ADC_P13_PORT +#define RTE_ADC_P13_PIN ADC_P13_PIN +#endif +#define RTE_ADC_P13_MUX 1 + +#ifndef ADC_P14_LOC +#define RTE_ADC_P14_PORT 0 +#define RTE_ADC_P14_PIN 9 +#else +#define RTE_ADC_P14_PORT ADC_P14_PORT +#define RTE_ADC_P14_PIN ADC_P14_PIN +#endif +#define RTE_ADC_P14_MUX 1 + +#ifndef ADC_P15_LOC +#define RTE_ADC_P15_PORT 0 +#define RTE_ADC_P15_PIN 7 +#else +#define RTE_ADC_P15_PORT ADC_P15_PORT +#define RTE_ADC_P15_PIN ADC_P15_PIN +#endif +#define RTE_ADC_P15_MUX 1 + +#ifndef ADC_P16_LOC +#define RTE_ADC_P16_PORT 0 +#define RTE_ADC_P16_PIN 26 +#else +#define RTE_ADC_P16_PORT ADC_P16_PORT +#define RTE_ADC_P16_PIN ADC_P16_PIN +#endif +#define RTE_ADC_P16_MUX 1 +#define RTE_ADC_P16_PAD 0 + +#ifndef ADC_P17_LOC +#define RTE_ADC_P17_PORT 0 +#define RTE_ADC_P17_PIN 28 +#else +#define RTE_ADC_P17_PORT ADC_P17_PORT +#define RTE_ADC_P17_PIN ADC_P17_PIN +#endif +#define RTE_ADC_P17_MUX 1 +#define RTE_ADC_P17_PAD 0 + +#ifndef ADC_P18_LOC +#define RTE_ADC_P18_PORT 0 +#define RTE_ADC_P18_PIN 30 +#else +#define RTE_ADC_P18_PORT ADC_P18_PORT +#define RTE_ADC_P18_PIN ADC_P18_PIN +#endif +#define RTE_ADC_P18_MUX 1 +#define RTE_ADC_P18_PAD 0 + +//ADC END + +//COMPARATOR START + +#ifndef COMP1_P0_LOC +#define RTE_COMP1_P0_PORT 0 +#define RTE_COMP1_P0_PIN 0 +#else +#define RTE_COMP1_P0_PORT COMP1_P0_PORT +#define RTE_COMP1_P0_PIN COMP1_P0_PIN +#endif +#define RTE_COMP1_P0_MUX 0 + +#ifndef COMP1_N0_LOC +#define RTE_COMP1_N0_PORT 0 +#define RTE_COMP1_N0_PIN 1 +#else +#define RTE_COMP1_N0_PORT COMP1_N0_PORT +#define RTE_COMP1_N0_PIN COMP1_N0_PIN +#endif +#define RTE_COMP1_N0_MUX 0 + +#ifndef COMP1_P1_LOC +#define RTE_COMP1_P1_PORT 0 +#define RTE_COMP1_P1_PIN 5 +#else +#define RTE_COMP1_P1_PORT COMP1_P1_PORT +#define RTE_COMP1_P1_PIN COMP1_P1_PIN +#endif +#define RTE_COMP1_P1_MUX 0 + +#ifndef COMP1_N1_LOC +#define RTE_COMP1_N1_PORT 0 +#define RTE_COMP1_N1_PIN 4 +#else +#define RTE_COMP1_N1_PORT COMP1_N1_PORT +#define RTE_COMP1_N1_PIN COMP1_N1_PIN +#endif +#define RTE_COMP1_N1_MUX 0 + +#ifndef COMP2_P0_LOC +#define RTE_COMP2_P0_PORT 0 +#define RTE_COMP2_P0_PIN 2 +#else +#define RTE_COMP2_P0_PORT COMP2_P0_PORT +#define RTE_COMP2_P0_PIN COMP2_P0_PIN +#endif +#define RTE_COMP2_P0_MUX 0 + +#ifndef COMP2_N0_LOC +#define RTE_COMP2_N0_PORT 0 +#define RTE_COMP2_N0_PIN 3 +#else +#define RTE_COMP2_N0_PORT COMP2_N0_PORT +#define RTE_COMP2_N0_PIN COMP2_N0_PIN +#endif +#define RTE_COMP2_N0_MUX 0 + +#ifndef COMP2_P1_LOC +#define RTE_COMP2_P1_PORT 0 +#define RTE_COMP2_P1_PIN 27 +#else +#define RTE_COMP2_P1_PORT COMP2_P1_PORT +#define RTE_COMP2_P1_PIN COMP2_P1_PIN +#endif +#define RTE_COMP2_P1_MUX 0 +#define RTE_COMP2_P1_PAD 0 + +#ifndef COMP2_N1_LOC +#define RTE_COMP2_N1_PORT 0 +#define RTE_COMP2_N1_PIN 28 +#else +#define RTE_COMP2_N1_PORT COMP2_N1_PORT +#define RTE_COMP2_N1_PIN COMP2_N1_PIN +#endif +#define RTE_COMP2_N1_MUX 0 + +//COMPARATOR END + +#define RTE_GPIO_6_PORT 0 +#define RTE_GPIO_6_PAD 1 +#define RTE_GPIO_6_PIN 6 +#define RTE_GPIO_6_MODE 0 + +#define RTE_GPIO_7_PORT 0 +#define RTE_GPIO_7_PAD 2 +#define RTE_GPIO_7_PIN 7 +#define RTE_GPIO_7_MODE 0 + +#define RTE_GPIO_8_PORT 0 +#define RTE_GPIO_8_PAD 3 +#define RTE_GPIO_8_PIN 8 +#define RTE_GPIO_8_MODE 0 + +#define RTE_GPIO_9_PORT 0 +#define RTE_GPIO_9_PAD 4 +#define RTE_GPIO_9_PIN 9 +#define RTE_GPIO_9_MODE 0 + +#define RTE_GPIO_10_PORT 0 +#define RTE_GPIO_10_PAD 5 +#define RTE_GPIO_10_PIN 10 +#define RTE_GPIO_10_MODE 0 + +#define RTE_GPIO_11_PORT 0 +#define RTE_GPIO_11_PAD 6 +#define RTE_GPIO_11_PIN 11 +#define RTE_GPIO_11_MODE 0 + +#define RTE_GPIO_12_PORT 0 +#define RTE_GPIO_12_PAD 7 +#define RTE_GPIO_12_PIN 12 +#define RTE_GPIO_12_MODE 0 + +#define RTE_GPIO_15_PORT 0 +#define RTE_GPIO_15_PAD 8 +#define RTE_GPIO_15_PIN 15 +#define RTE_GPIO_15_MODE 0 + +#define RTE_GPIO_25_PORT 0 +#define RTE_GPIO_25_PIN 25 +#define RTE_GPIO_25_MODE 0 + +#define RTE_GPIO_26_PORT 0 +#define RTE_GPIO_26_PIN 26 +#define RTE_GPIO_26_MODE 0 + +#define RTE_GPIO_27_PORT 0 +#define RTE_GPIO_27_PIN 27 +#define RTE_GPIO_27_MODE 0 + +#define RTE_GPIO_28_PORT 0 +#define RTE_GPIO_28_PIN 28 +#define RTE_GPIO_28_MODE 0 + +#define RTE_GPIO_29_PORT 0 +#define RTE_GPIO_29_PIN 29 +#define RTE_GPIO_29_MODE 0 + +#define RTE_GPIO_30_PORT 0 +#define RTE_GPIO_30_PIN 30 +#define RTE_GPIO_30_MODE 0 + +#define RTE_GPIO_31_PORT 0 +#define RTE_GPIO_31_PAD 9 +#define RTE_GPIO_31_PIN 31 +#define RTE_GPIO_31_MODE 0 + +#define RTE_GPIO_32_PORT 0 +#define RTE_GPIO_32_PAD 9 +#define RTE_GPIO_32_PIN 32 +#define RTE_GPIO_32_MODE 0 + +#define RTE_GPIO_33_PORT 0 +#define RTE_GPIO_33_PAD 9 +#define RTE_GPIO_33_PIN 33 +#define RTE_GPIO_33_MODE 0 + +#define RTE_GPIO_34_PORT 0 +#define RTE_GPIO_34_PAD 9 +#define RTE_GPIO_34_PIN 34 +#define RTE_GPIO_34_MODE 0 + +#define RTE_GPIO_46_PORT 0 +#define RTE_GPIO_46_PAD 10 +#define RTE_GPIO_46_PIN 46 +#define RTE_GPIO_46_MODE 0 + +#define RTE_GPIO_47_PORT 0 +#define RTE_GPIO_47_PAD 11 +#define RTE_GPIO_47_PIN 47 +#define RTE_GPIO_47_MODE 0 + +#define RTE_GPIO_48_PORT 0 +#define RTE_GPIO_48_PAD 12 +#define RTE_GPIO_48_PIN 48 +#define RTE_GPIO_48_MODE 0 + +#define RTE_GPIO_49_PORT 0 +#define RTE_GPIO_49_PAD 13 +#define RTE_GPIO_49_PIN 49 +#define RTE_GPIO_49_MODE 0 + +#define RTE_GPIO_50_PORT 0 +#define RTE_GPIO_50_PAD 14 +#define RTE_GPIO_50_PIN 50 +#define RTE_GPIO_50_MODE 0 + +#define RTE_GPIO_51_PORT 0 +#define RTE_GPIO_51_PAD 15 +#define RTE_GPIO_51_PIN 51 +#define RTE_GPIO_51_MODE 0 + +#define RTE_GPIO_52_PORT 0 +#define RTE_GPIO_52_PAD 16 +#define RTE_GPIO_52_PIN 52 +#define RTE_GPIO_52_MODE 0 + +#define RTE_GPIO_53_PORT 0 +#define RTE_GPIO_53_PAD 17 +#define RTE_GPIO_53_PIN 53 +#define RTE_GPIO_53_MODE 0 + +#define RTE_GPIO_54_PORT 0 +#define RTE_GPIO_54_PAD 18 +#define RTE_GPIO_54_PIN 54 +#define RTE_GPIO_54_MODE 0 + +#define RTE_GPIO_55_PORT 0 +#define RTE_GPIO_55_PAD 19 +#define RTE_GPIO_55_PIN 55 +#define RTE_GPIO_55_MODE 0 + +#define RTE_GPIO_56_PORT 0 +#define RTE_GPIO_56_PAD 20 +#define RTE_GPIO_56_PIN 56 +#define RTE_GPIO_56_MODE 0 + +#define RTE_GPIO_57_PORT 0 +#define RTE_GPIO_57_PAD 21 +#define RTE_GPIO_57_PIN 57 +#define RTE_GPIO_57_MODE 0 + +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_ULP_GPIO_0_PORT_ID 1 +#else +#define RTE_ULP_GPIO_0_PORT_ID 0 +#endif + +#if (RTE_ULP_GPIO_0_PORT_ID == 0) +#define RTE_ULP_GPIO_0_PORT 0 +#define RTE_ULP_GPIO_0_PAD 22 +#define RTE_ULP_GPIO_0_PIN 64 +#define RTE_ULP_GPIO_0_MODE 0 +#elif (RTE_ULP_GPIO_0_PORT_ID == 1) +#define RTE_ULP_GPIO_0_PORT 4 +#define RTE_ULP_GPIO_0_PIN 0 +#define RTE_ULP_GPIO_0_MODE 0 +#else +#error "Invalid RTE_ULP_GPIO_0_PIN Pin Configuration!" +#endif + +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_ULP_GPIO_1_PORT_ID 1 +#else +#define RTE_ULP_GPIO_1_PORT_ID 0 +#endif + +#if (RTE_ULP_GPIO_1_PORT_ID == 0) +#define RTE_ULP_GPIO_1_PORT 0 +#define RTE_ULP_GPIO_1_PAD 23 +#define RTE_ULP_GPIO_1_PIN 65 +#define RTE_ULP_GPIO_1_MODE 0 +#elif (RTE_ULP_GPIO_1_PORT_ID == 1) +#define RTE_ULP_GPIO_1_PORT 4 +#define RTE_ULP_GPIO_1_PIN 1 +#define RTE_ULP_GPIO_1_MODE 0 +#else +#error "Invalid RTE_ULP_GPIO_1_PIN Pin Configuration!" +#endif + +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_ULP_GPIO_2_PORT_ID 1 +#else +#define RTE_ULP_GPIO_2_PORT_ID 0 +#endif + +#if (RTE_ULP_GPIO_2_PORT_ID == 0) +#define RTE_ULP_GPIO_2_PORT 0 +#define RTE_ULP_GPIO_2_PAD 24 +#define RTE_ULP_GPIO_2_PIN 66 +#define RTE_ULP_GPIO_2_MODE 0 +#elif (RTE_ULP_GPIO_2_PORT_ID == 1) +#define RTE_ULP_GPIO_2_PORT 4 +#define RTE_ULP_GPIO_2_PIN 2 +#define RTE_ULP_GPIO_2_MODE 0 +#else +#error "Invalid RTE_ULP_GPIO_2_PIN Pin Configuration!" +#endif + +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_ULP_GPIO_3_PORT_ID 1 +#else +#define RTE_ULP_GPIO_3_PORT_ID 0 +#endif + +#if (RTE_ULP_GPIO_3_PORT_ID == 0) +#define RTE_ULP_GPIO_3_PORT 0 +#define RTE_ULP_GPIO_3_PAD 25 +#define RTE_ULP_GPIO_3_PIN 67 +#define RTE_ULP_GPIO_3_MODE 0 +#elif (RTE_ULP_GPIO_3_PORT_ID == 1) +#define RTE_ULP_GPIO_3_PORT 4 +#define RTE_ULP_GPIO_3_PIN 3 +#define RTE_ULP_GPIO_3_MODE 0 +#else +#error "Invalid RTE_ULP_GPIO_3_PIN Pin Configuration!" +#endif + +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_ULP_GPIO_4_PORT_ID 1 +#else +#define RTE_ULP_GPIO_4_PORT_ID 0 +#endif + +#if (RTE_ULP_GPIO_4_PORT_ID == 0) +#define RTE_ULP_GPIO_4_PORT 0 +#define RTE_ULP_GPIO_4_PAD 26 +#define RTE_ULP_GPIO_4_PIN 68 +#define RTE_ULP_GPIO_4_MODE 0 +#elif (RTE_ULP_GPIO_4_PORT_ID == 1) +#define RTE_ULP_GPIO_4_PORT 4 +#define RTE_ULP_GPIO_4_PIN 4 +#define RTE_ULP_GPIO_4_MODE 0 +#else +#error "Invalid RTE_ULP_GPIO_4_PIN Pin Configuration!" +#endif + +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_ULP_GPIO_5_PORT_ID 1 +#else +#define RTE_ULP_GPIO_5_PORT_ID 0 +#endif + +#if (RTE_ULP_GPIO_5_PORT_ID == 0) +#define RTE_ULP_GPIO_5_PORT 4 +#define RTE_ULP_GPIO_5_PAD 27 +#define RTE_ULP_GPIO_5_PIN 69 +#define RTE_ULP_GPIO_5_MODE 0 +#elif (RTE_ULP_GPIO_5_PORT_ID == 1) +#define RTE_ULP_GPIO_5_PORT 4 +#define RTE_ULP_GPIO_5_PIN 5 +#define RTE_ULP_GPIO_5_MODE 0 +#else +#error "Invalid RTE_ULP_GPIO_5_PIN Pin Configuration!" +#endif + +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_ULP_GPIO_6_PORT_ID 1 +#else +#define RTE_ULP_GPIO_6_PORT_ID 0 +#endif + +#if (RTE_ULP_GPIO_6_PORT_ID == 0) +#define RTE_ULP_GPIO_6_PORT 4 +#define RTE_ULP_GPIO_6_PAD 28 +#define RTE_ULP_GPIO_6_PIN 70 +#define RTE_ULP_GPIO_6_MODE 0 +#elif (RTE_ULP_GPIO_6_PORT_ID == 1) +#define RTE_ULP_GPIO_6_PORT 4 +#define RTE_ULP_GPIO_6_PIN 6 +#define RTE_ULP_GPIO_6_MODE 0 +#else +#error "Invalid RTE_ULP_GPIO_6_PIN Pin Configuration!" +#endif + +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_ULP_GPIO_7_PORT_ID 1 +#else +#define RTE_ULP_GPIO_7_PORT_ID 0 +#endif + +#if (RTE_ULP_GPIO_7_PORT_ID == 0) +#define RTE_ULP_GPIO_7_PORT 4 +#define RTE_ULP_GPIO_7_PAD 29 +#define RTE_ULP_GPIO_7_PIN 71 +#define RTE_ULP_GPIO_7_MODE 0 +#elif (RTE_ULP_GPIO_7_PORT_ID == 1) +#define RTE_ULP_GPIO_7_PORT 4 +#define RTE_ULP_GPIO_7_PIN 7 +#define RTE_ULP_GPIO_7_MODE 0 +#else +#error "Invalid RTE_ULP_GPIO_7_PIN Pin Configuration!" +#endif + +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_ULP_GPIO_8_PORT_ID 1 +#else +#define RTE_ULP_GPIO_8_PORT_ID 0 +#endif + +#if (RTE_ULP_GPIO_8_PORT_ID == 0) +#define RTE_ULP_GPIO_8_PORT 4 +#define RTE_ULP_GPIO_8_PAD 30 +#define RTE_ULP_GPIO_8_PIN 72 +#define RTE_ULP_GPIO_8_MODE 0 +#elif (RTE_ULP_GPIO_8_PORT_ID == 1) +#define RTE_ULP_GPIO_8_PORT 4 +#define RTE_ULP_GPIO_8_PIN 8 +#define RTE_ULP_GPIO_8_MODE 0 +#else +#error "Invalid RTE_ULP_GPIO_8_PIN Pin Configuration!" +#endif + +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_ULP_GPIO_9_PORT_ID 1 +#else +#define RTE_ULP_GPIO_9_PORT_ID 0 +#endif + +#if (RTE_ULP_GPIO_9_PORT_ID == 0) +#define RTE_ULP_GPIO_9_PORT 4 +#define RTE_ULP_GPIO_9_PAD 31 +#define RTE_ULP_GPIO_9_PIN 73 +#define RTE_ULP_GPIO_9_MODE 0 +#elif (RTE_ULP_GPIO_9_PORT_ID == 1) +#define RTE_ULP_GPIO_9_PORT 4 +#define RTE_ULP_GPIO_9_PIN 9 +#define RTE_ULP_GPIO_9_MODE 0 +#else +#error "Invalid RTE_ULP_GPIO_9_PIN Pin Configuration!" +#endif + +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_ULP_GPIO_10_PORT_ID 1 +#else +#define RTE_ULP_GPIO_10_PORT_ID 0 +#endif + +#if (RTE_ULP_GPIO_10_PORT_ID == 0) +#define RTE_ULP_GPIO_10_PORT 4 +#define RTE_ULP_GPIO_10_PAD 32 +#define RTE_ULP_GPIO_10_PIN 74 +#define RTE_ULP_GPIO_10_MODE 0 +#elif (RTE_ULP_GPIO_10_PORT_ID == 1) +#define RTE_ULP_GPIO_10_PORT 4 +#define RTE_ULP_GPIO_10_PIN 10 +#define RTE_ULP_GPIO_10_MODE 0 +#else +#error "Invalid RTE_ULP_GPIO_10_PIN Pin Configuration!" +#endif + +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_ULP_GPIO_11_PORT_ID 1 +#else +#define RTE_ULP_GPIO_11_PORT_ID 0 +#endif + +#if (RTE_ULP_GPIO_11_PORT_ID == 0) +#define RTE_ULP_GPIO_11_PORT 4 +#define RTE_ULP_GPIO_11_PAD 33 +#define RTE_ULP_GPIO_11_PIN 75 +#define RTE_ULP_GPIO_11_MODE 0 +#elif (RTE_ULP_GPIO_11_PORT_ID == 1) +#define RTE_ULP_GPIO_11_PORT 4 +#define RTE_ULP_GPIO_11_PIN 11 +#define RTE_ULP_GPIO_11_MODE 0 +#else +#error "Invalid RTE_ULP_GPIO_11_PIN Pin Configuration!" +#endif + +// RTE_UULP_GPIO_x_PORT refers to port for UULP GPIO pin x +#define RTE_UULP_GPIO_0_PORT 5 +#define RTE_UULP_GPIO_0_PIN 0 +#define RTE_UULP_GPIO_0_MODE 0 + +#define RTE_UULP_GPIO_1_PORT 5 +#define RTE_UULP_GPIO_1_PIN 1 +#define RTE_UULP_GPIO_1_MODE 0 + +#define RTE_UULP_GPIO_2_PORT 5 +#define RTE_UULP_GPIO_2_PIN 2 +#define RTE_UULP_GPIO_2_MODE 0 + +#define RTE_UULP_GPIO_3_PORT 5 +#define RTE_UULP_GPIO_3_PIN 3 +#define RTE_UULP_GPIO_3_MODE 0 + +#define RTE_UULP_GPIO_4_PORT 5 +#define RTE_UULP_GPIO_4_PIN 4 +#define RTE_UULP_GPIO_4_MODE 0 + +#define RTE_UULP_GPIO_5_PIN 5 +#define RTE_UULP_GPIO_5_MODE 0 + +// ULP GPIO as enable pin for sensors +#define SENSOR_ENABLE_GPIO_MAPPED_TO_ULP +#define SENSOR_ENABLE_GPIO_PORT RTE_ULP_GPIO_3_PORT +#define SENSOR_ENABLE_GPIO_PIN RTE_ULP_GPIO_3_PIN + +// Memlcd GPIOs +#define RTE_MEMLCD_CS_PIN 4 // Memlcd SPI CS pin +#define RTE_MEMLCD_CS_PORT 0 // Memlcd SPI CS port + +#define RTE_MEMLCD_EXTCOMIN_PIN 5 // Memlcd external communication pin +#define RTE_MEMLCD_EXTCOMIN_PORT 0 // Memlcd external communication port + +#define RTE_MEMLCD_ENABLE_DISPLAY_PIN 0 // Memlcd display enable pin +#define RTE_MEMLCD_ENABLE_DISPLAY_PORT 0 // Memlcd display enable port diff --git a/components/board/silabs/config/brd4343q/pin_config.h b/components/board/silabs/config/brd4343q/pin_config.h new file mode 100644 index 000000000..2bbc8c59c --- /dev/null +++ b/components/board/silabs/config/brd4343q/pin_config.h @@ -0,0 +1,140 @@ +#ifndef PIN_CONFIG_H +#define PIN_CONFIG_H + +// $[USART0] +// [USART0]$ + +// $[UART1] +// [UART1]$ + +// $[ULP_UART] +// [ULP_UART]$ + +// $[I2C0] +// [I2C0]$ + +// $[I2C1] +// [I2C1]$ + +// $[ULP_I2C] +// [ULP_I2C]$ + +// $[SSI_MASTER] +// [SSI_MASTER]$ + +// $[SSI_SLAVE] +// [SSI_SLAVE]$ + +// $[ULP_SPI] +// [ULP_SPI]$ + +// $[GSPI_MASTER] +// [GSPI_MASTER]$ + +// $[I2S0] +// [I2S0]$ + +// $[ULP_I2S] +// [ULP_I2S]$ + +// $[SCT] +// [SCT]$ + +// $[SIO] +// [SIO]$ + +// $[PWM] +// [PWM]$ + +// $[PWM_CH0] +// [PWM_CH0]$ + +// $[PWM_CH1] +// [PWM_CH1]$ + +// $[PWM_CH2] +// [PWM_CH2]$ + +// $[PWM_CH3] +// [PWM_CH3]$ + +// $[ADC_CH1] +// [ADC_CH1]$ + +// $[ADC_CH2] +// [ADC_CH2]$ + +// $[ADC_CH3] +// [ADC_CH3]$ + +// $[ADC_CH4] +// [ADC_CH4]$ + +// $[ADC_CH5] +// [ADC_CH5]$ + +// $[ADC_CH6] +// [ADC_CH6]$ + +// $[ADC_CH7] +// [ADC_CH7]$ + +// $[ADC_CH8] +// [ADC_CH8]$ + +// $[ADC_CH9] +// [ADC_CH9]$ + +// $[ADC_CH10] +// [ADC_CH10]$ + +// $[ADC_CH11] +// [ADC_CH11]$ + +// $[ADC_CH12] +// [ADC_CH12]$ + +// $[ADC_CH13] +// [ADC_CH13]$ + +// $[ADC_CH14] +// [ADC_CH14]$ + +// $[ADC_CH15] +// [ADC_CH15]$ + +// $[ADC_CH16] +// [ADC_CH16]$ + +// $[ADC_CH17] +// [ADC_CH17]$ + +// $[ADC_CH18] +// [ADC_CH18]$ + +// $[ADC_CH19] +// [ADC_CH19]$ + +// $[COMP1] +// [COMP1]$ + +// $[COMP2] +// [COMP2]$ + +// $[DAC0] +// [DAC0]$ + +// $[DAC1] +// [DAC1]$ + +// $[CUSTOM_PIN_NAME] +#ifndef _PORT +#define _PORT 0 +#endif +#ifndef _PIN +#define _PIN 6 +#endif + +// [CUSTOM_PIN_NAME]$ + +#endif // PIN_CONFIG_H diff --git a/components/board/silabs/config/brd4343q/sl_board_configuration.h b/components/board/silabs/config/brd4343q/sl_board_configuration.h new file mode 100644 index 000000000..47497a756 --- /dev/null +++ b/components/board/silabs/config/brd4343q/sl_board_configuration.h @@ -0,0 +1,23 @@ +/******************************************************************************* +* @file sl_board_configuration.h +* @brief +******************************************************************************* +* # License +* Copyright 2024 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +#pragma once + +#include + +#define DEFAULT_UART NULL +#define DEFAULT_UART_PIN_CONFIG NULL diff --git a/utilities/isp_scripts_common_flash/gen_isp/image_header.c b/components/board/silabs/config/brd4343q/sl_board_control.h similarity index 81% rename from utilities/isp_scripts_common_flash/gen_isp/image_header.c rename to components/board/silabs/config/brd4343q/sl_board_control.h index d1de809f0..decc00585 100644 --- a/utilities/isp_scripts_common_flash/gen_isp/image_header.c +++ b/components/board/silabs/config/brd4343q/sl_board_control.h @@ -1,9 +1,9 @@ /******************************************************************************* -* @file image_header.c +* @file sl_board_control.h * @brief ******************************************************************************* * # License -* Copyright 2023 Silicon Laboratories Inc. www.silabs.com +* Copyright 2024 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this @@ -15,6 +15,8 @@ * ******************************************************************************/ -volatile unsigned int header[] = { -#include "../header.h" -}; +#pragma once + +#include "sl_status.h" + +sl_status_t sl_board_enable_vcom(void); diff --git a/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_10_config.h b/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_10_config.h index 5a0a02434..9c5c6e87d 100644 --- a/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_10_config.h +++ b/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_10_config.h @@ -37,6 +37,7 @@ extern "C" { /******************************************************************************/ /******************************* ADC Channel Configuration **************************/ +#define P10_START_LOCATION_PINTOOL 424 // <<< Use Configuration Wizard in Context Menu >>> // ADC Channel Configuration @@ -57,7 +58,31 @@ extern "C" { // // <<< end of configuration section >>> -#define SL_ADC_CHANNEL_10_POS_INPUT_CHNL_SEL 0 +// <<< sl:start pin_tool >>> +// SL_ADC_CH10 +// $[ADC_CH10_SL_ADC_CH10] +#ifndef SL_ADC_CH10_PERIPHERAL +#define SL_ADC_CH10_PERIPHERAL ADC_CH10 +#endif + +// ADC_CH10 P10 on ULP_GPIO_9/GPIO_73 +#ifndef SL_ADC_CH10_P10_PORT +#define SL_ADC_CH10_P10_PORT 0 +#endif +#ifndef SL_ADC_CH10_P10_PIN +#define SL_ADC_CH10_P10_PIN 9 +#endif +#ifndef SL_ADC_CH10_P10_LOC +#define SL_ADC_CH10_P10_LOC 438 +#endif +// [ADC_CH10_SL_ADC_CH10]$ +// <<< sl:end pin_tool >>> + +#ifdef SL_ADC_CH10_P10_LOC +#define SL_ADC_CHANNEL_10_POS_INPUT_CHNL_SEL (SL_ADC_CH10_P10_LOC - P10_START_LOCATION_PINTOOL) +#else +#define SL_ADC_CHANNEL_10_POS_INPUT_CHNL_SEL 14 +#endif #define SL_ADC_CHANNEL_10_NEG_INPUT_CHNL_SEL 8 #ifdef __cplusplus diff --git a/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_11_config.h b/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_11_config.h index 5a128ab82..64a062c89 100644 --- a/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_11_config.h +++ b/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_11_config.h @@ -37,7 +37,7 @@ extern "C" { /******************************************************************************/ /**************************** ADC Channel Configuration ***********************/ -#define P10_START_LOCATION_PINTOOL 171 +#define P11_START_LOCATION_PINTOOL 171 // <<< Use Configuration Wizard in Context Menu >>> // ADC Channel Configuration @@ -59,26 +59,30 @@ extern "C" { // <<< end of configuration section >>> // <<< sl:start pin_tool >>> -// SL_ADC_CH11 -// $[ADC_SL_ADC_CH11] +// SL_ADC_CH11 +// $[ADC_CH11_SL_ADC_CH11] #ifndef SL_ADC_CH11_PERIPHERAL -#define SL_ADC_CH11_PERIPHERAL ADC +#define SL_ADC_CH11_PERIPHERAL ADC_CH11 #endif -// ADC P10 on ULP_GPIO_1/GPIO_65 -#ifndef SL_ADC_CH11_P10_PORT -#define SL_ADC_CH11_P10_PORT 0 +// ADC_CH11 P11 on ULP_GPIO_1/GPIO_65 +#ifndef SL_ADC_CH11_P11_PORT +#define SL_ADC_CH11_P11_PORT 0 #endif -#ifndef SL_ADC_CH11_P10_PIN -#define SL_ADC_CH11_P10_PIN 1 +#ifndef SL_ADC_CH11_P11_PIN +#define SL_ADC_CH11_P11_PIN 1 #endif -#ifndef SL_ADC_CH11_P10_LOC -#define SL_ADC_CH11_P10_LOC 181 +#ifndef SL_ADC_CH11_P11_LOC +#define SL_ADC_CH11_P11_LOC 181 #endif -// [ADC_SL_ADC_CH11]$ +// [ADC_CH11_SL_ADC_CH11]$ // <<< sl:end pin_tool >>> -#define SL_ADC_CHANNEL_11_POS_INPUT_CHNL_SEL (SL_ADC_CH11_P10_LOC - P10_START_LOCATION_PINTOOL) +#ifdef SL_ADC_CH11_P11_LOC +#define SL_ADC_CHANNEL_11_POS_INPUT_CHNL_SEL (SL_ADC_CH11_P11_LOC - P11_START_LOCATION_PINTOOL) +#else +#define SL_ADC_CHANNEL_11_POS_INPUT_CHNL_SEL 10 +#endif #define SL_ADC_CHANNEL_11_NEG_INPUT_CHNL_SEL 8 #ifdef __cplusplus diff --git a/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_12_config.h b/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_12_config.h index fd5720819..cb6725ac4 100644 --- a/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_12_config.h +++ b/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_12_config.h @@ -37,7 +37,7 @@ extern "C" { /******************************************************************************/ /**************************** ADC Channel Configuration ***********************/ -#define P11_START_LOCATION_PINTOOL 191 +#define P12_START_LOCATION_PINTOOL 191 // <<< Use Configuration Wizard in Context Menu >>> // ADC Channel Configuration @@ -59,26 +59,30 @@ extern "C" { // <<< end of configuration section >>> // <<< sl:start pin_tool >>> -// SL_ADC_CH12 -// $[ADC_SL_ADC_CH12] +// SL_ADC_CH12 +// $[ADC_CH12_SL_ADC_CH12] #ifndef SL_ADC_CH12_PERIPHERAL -#define SL_ADC_CH12_PERIPHERAL ADC +#define SL_ADC_CH12_PERIPHERAL ADC_CH12 #endif -// ADC P11 on ULP_GPIO_1/GPIO_65 -#ifndef SL_ADC_CH12_P11_PORT -#define SL_ADC_CH12_P11_PORT 0 +// ADC_CH12 P12 on ULP_GPIO_1/GPIO_65 +#ifndef SL_ADC_CH12_P12_PORT +#define SL_ADC_CH12_P12_PORT 0 #endif -#ifndef SL_ADC_CH12_P11_PIN -#define SL_ADC_CH12_P11_PIN 1 +#ifndef SL_ADC_CH12_P12_PIN +#define SL_ADC_CH12_P12_PIN 1 #endif -#ifndef SL_ADC_CH12_P11_LOC -#define SL_ADC_CH12_P11_LOC 201 +#ifndef SL_ADC_CH12_P12_LOC +#define SL_ADC_CH12_P12_LOC 201 #endif -// [ADC_SL_ADC_CH12]$ +// [ADC_CH12_SL_ADC_CH12]$ // <<< sl:end pin_tool >>> -#define SL_ADC_CHANNEL_12_POS_INPUT_CHNL_SEL (SL_ADC_CH12_P11_LOC - P11_START_LOCATION_PINTOOL) +#ifdef SL_ADC_CH12_P12_LOC +#define SL_ADC_CHANNEL_12_POS_INPUT_CHNL_SEL (SL_ADC_CH12_P12_LOC - P12_START_LOCATION_PINTOOL) +#else +#define SL_ADC_CHANNEL_12_POS_INPUT_CHNL_SEL 10 +#endif #define SL_ADC_CHANNEL_12_NEG_INPUT_CHNL_SEL 7 #ifdef __cplusplus diff --git a/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_13_config.h b/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_13_config.h index 27861bb7c..c30dcabf6 100644 --- a/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_13_config.h +++ b/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_13_config.h @@ -37,7 +37,7 @@ extern "C" { /******************************************************************************/ /**************************** ADC Channel Configuration ***********************/ -#define P12_START_LOCATION_PINTOOL 210 +#define P13_START_LOCATION_PINTOOL 210 // <<< Use Configuration Wizard in Context Menu >>> // ADC Channel Configuration @@ -59,26 +59,30 @@ extern "C" { // <<< end of configuration section >>> // <<< sl:start pin_tool >>> -// SL_ADC_CH13 -// $[ADC_SL_ADC_CH13] +// SL_ADC_CH13 +// $[ADC_CH13_SL_ADC_CH13] #ifndef SL_ADC_CH13_PERIPHERAL -#define SL_ADC_CH13_PERIPHERAL ADC +#define SL_ADC_CH13_PERIPHERAL ADC_CH13 #endif -// ADC P12 on ULP_GPIO_7/GPIO_71 -#ifndef SL_ADC_CH13_P12_PORT -#define SL_ADC_CH13_P12_PORT 0 +// ADC_CH13 P13 on ULP_GPIO_7/GPIO_71 +#ifndef SL_ADC_CH13_P13_PORT +#define SL_ADC_CH13_P13_PORT 0 #endif -#ifndef SL_ADC_CH13_P12_PIN -#define SL_ADC_CH13_P12_PIN 7 +#ifndef SL_ADC_CH13_P13_PIN +#define SL_ADC_CH13_P13_PIN 7 #endif -#ifndef SL_ADC_CH13_P12_LOC -#define SL_ADC_CH13_P12_LOC 225 +#ifndef SL_ADC_CH13_P13_LOC +#define SL_ADC_CH13_P13_LOC 225 #endif -// [ADC_SL_ADC_CH13]$ +// [ADC_CH13_SL_ADC_CH13]$ // <<< sl:end pin_tool >>> -#define SL_ADC_CHANNEL_13_POS_INPUT_CHNL_SEL (SL_ADC_CH13_P12_LOC - P12_START_LOCATION_PINTOOL) +#ifdef SL_ADC_CH13_P13_LOC +#define SL_ADC_CHANNEL_13_POS_INPUT_CHNL_SEL (SL_ADC_CH13_P13_LOC - P13_START_LOCATION_PINTOOL) +#else +#define SL_ADC_CHANNEL_13_POS_INPUT_CHNL_SEL 15 +#endif #define SL_ADC_CHANNEL_13_NEG_INPUT_CHNL_SEL 6 #ifdef __cplusplus diff --git a/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_14_config.h b/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_14_config.h index a60553000..78c327815 100644 --- a/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_14_config.h +++ b/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_14_config.h @@ -37,7 +37,7 @@ extern "C" { /******************************************************************************/ /******************************* ADC Channel Configuration **************************/ -#define P13_START_LOCATION_PINTOOL 229 +#define P14_START_LOCATION_PINTOOL 229 // <<< Use Configuration Wizard in Context Menu >>> // ADC Channel Configuration @@ -59,26 +59,30 @@ extern "C" { // <<< end of configuration section >>> // <<< sl:start pin_tool >>> -// SL_ADC_CH14 -// $[ADC_SL_ADC_CH14] +// SL_ADC_CH14 +// $[ADC_CH14_SL_ADC_CH14] #ifndef SL_ADC_CH14_PERIPHERAL -#define SL_ADC_CH14_PERIPHERAL ADC +#define SL_ADC_CH14_PERIPHERAL ADC_CH14 #endif -// ADC P13 on GPIO_26 -#ifndef SL_ADC_CH14_P13_PORT -#define SL_ADC_CH14_P13_PORT 0 +// ADC_CH14 P14 on GPIO_26 +#ifndef SL_ADC_CH14_P14_PORT +#define SL_ADC_CH14_P14_PORT 0 #endif -#ifndef SL_ADC_CH14_P13_PIN -#define SL_ADC_CH14_P13_PIN 26 +#ifndef SL_ADC_CH14_P14_PIN +#define SL_ADC_CH14_P14_PIN 26 #endif -#ifndef SL_ADC_CH14_P13_LOC -#define SL_ADC_CH14_P13_LOC 245 +#ifndef SL_ADC_CH14_P14_LOC +#define SL_ADC_CH14_P14_LOC 245 #endif -// [ADC_SL_ADC_CH14]$ +// [ADC_CH14_SL_ADC_CH14]$ // <<< sl:end pin_tool >>> -#define SL_ADC_CHANNEL_14_POS_INPUT_CHNL_SEL (SL_ADC_CH14_P13_LOC - P13_START_LOCATION_PINTOOL) +#ifdef SL_ADC_CH14_P14_LOC +#define SL_ADC_CHANNEL_14_POS_INPUT_CHNL_SEL (SL_ADC_CH14_P14_LOC - P14_START_LOCATION_PINTOOL) +#else +#define SL_ADC_CHANNEL_14_POS_INPUT_CHNL_SEL 16 +#endif #define SL_ADC_CHANNEL_14_NEG_INPUT_CHNL_SEL 5 #ifdef __cplusplus diff --git a/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_15_config.h b/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_15_config.h index 7f75a7d04..30870cfbc 100644 --- a/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_15_config.h +++ b/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_15_config.h @@ -37,7 +37,7 @@ extern "C" { /******************************************************************************/ /**************************** ADC Channel Configuration ***********************/ -#define P14_START_LOCATION_PINTOOL 248 +#define P15_START_LOCATION_PINTOOL 248 // <<< Use Configuration Wizard in Context Menu >>> // ADC Channel Configuration @@ -59,26 +59,30 @@ extern "C" { // <<< end of configuration section >>> // <<< sl:start pin_tool >>> -// SL_ADC_CH15 -// $[ADC_SL_ADC_CH15] +// SL_ADC_CH15 +// $[ADC_CH15_SL_ADC_CH15] #ifndef SL_ADC_CH15_PERIPHERAL -#define SL_ADC_CH15_PERIPHERAL ADC +#define SL_ADC_CH15_PERIPHERAL ADC_CH15 #endif -// ADC P14 on GPIO_30 -#ifndef SL_ADC_CH15_P14_PORT -#define SL_ADC_CH15_P14_PORT 0 +// ADC_CH15 P15 on GPIO_30 +#ifndef SL_ADC_CH15_P15_PORT +#define SL_ADC_CH15_P15_PORT 0 #endif -#ifndef SL_ADC_CH15_P14_PIN -#define SL_ADC_CH15_P14_PIN 30 +#ifndef SL_ADC_CH15_P15_PIN +#define SL_ADC_CH15_P15_PIN 30 #endif -#ifndef SL_ADC_CH15_P14_LOC -#define SL_ADC_CH15_P14_LOC 266 +#ifndef SL_ADC_CH15_P15_LOC +#define SL_ADC_CH15_P15_LOC 266 #endif -// [ADC_SL_ADC_CH15]$ +// [ADC_CH15_SL_ADC_CH15]$ // <<< sl:end pin_tool >>> -#define SL_ADC_CHANNEL_15_POS_INPUT_CHNL_SEL (SL_ADC_CH15_P14_LOC - P14_START_LOCATION_PINTOOL) +#ifdef SL_ADC_CH15_P15_LOC +#define SL_ADC_CHANNEL_15_POS_INPUT_CHNL_SEL (SL_ADC_CH15_P15_LOC - P15_START_LOCATION_PINTOOL) +#else +#define SL_ADC_CHANNEL_15_POS_INPUT_CHNL_SEL 18 +#endif #define SL_ADC_CHANNEL_15_NEG_INPUT_CHNL_SEL 6 #ifdef __cplusplus diff --git a/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_16_config.h b/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_16_config.h index 01750a1db..df904452e 100644 --- a/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_16_config.h +++ b/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_16_config.h @@ -37,7 +37,7 @@ extern "C" { /******************************************************************************/ /******************************* ADC Channel Configuration **************************/ -#define P15_START_LOCATION_PINTOOL 267 +#define P16_START_LOCATION_PINTOOL 267 // <<< Use Configuration Wizard in Context Menu >>> // ADC Channel Configuration @@ -59,26 +59,30 @@ extern "C" { // <<< end of configuration section >>> // <<< sl:start pin_tool >>> -// SL_ADC_CH16 -// $[ADC_SL_ADC_CH16] +// SL_ADC_CH16 +// $[ADC_CH16_SL_ADC_CH16] #ifndef SL_ADC_CH16_PERIPHERAL -#define SL_ADC_CH16_PERIPHERAL ADC +#define SL_ADC_CH16_PERIPHERAL ADC_CH16 #endif -// ADC P15 on GPIO_30 -#ifndef SL_ADC_CH16_P15_PORT -#define SL_ADC_CH16_P15_PORT 0 +// ADC_CH16 P16 on GPIO_30 +#ifndef SL_ADC_CH16_P16_PORT +#define SL_ADC_CH16_P16_PORT 0 #endif -#ifndef SL_ADC_CH16_P15_PIN -#define SL_ADC_CH16_P15_PIN 30 +#ifndef SL_ADC_CH16_P16_PIN +#define SL_ADC_CH16_P16_PIN 30 #endif -#ifndef SL_ADC_CH16_P15_LOC -#define SL_ADC_CH16_P15_LOC 285 +#ifndef SL_ADC_CH16_P16_LOC +#define SL_ADC_CH16_P16_LOC 285 #endif -// [ADC_SL_ADC_CH16]$ +// [ADC_CH16_SL_ADC_CH16]$ // <<< sl:end pin_tool >>> -#define SL_ADC_CHANNEL_16_POS_INPUT_CHNL_SEL (SL_ADC_CH16_P15_LOC - P15_START_LOCATION_PINTOOL) +#ifdef SL_ADC_CH16_P16_LOC +#define SL_ADC_CHANNEL_16_POS_INPUT_CHNL_SEL (SL_ADC_CH16_P16_LOC - P16_START_LOCATION_PINTOOL) +#else +#define SL_ADC_CHANNEL_16_POS_INPUT_CHNL_SEL 18 +#endif #define SL_ADC_CHANNEL_16_NEG_INPUT_CHNL_SEL 5 #ifdef __cplusplus diff --git a/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_1_config.h b/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_1_config.h index a4a61cd56..69d4263f2 100644 --- a/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_1_config.h +++ b/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_1_config.h @@ -37,7 +37,7 @@ extern "C" { /******************************************************************************/ /******************************* ADC Channel Configuration **************************/ -#define N0_START_LOCATION_PINTOOL 343 +#define N1_START_LOCATION_PINTOOL 343 // <<< Use Configuration Wizard in Context Menu >>> // ADC Channel Configuration @@ -59,38 +59,46 @@ extern "C" { // <<< end of configuration section >>> // <<< sl:start pin_tool >>> -// SL_ADC_CH1 -// $[ADC_SL_ADC_CH1] +// SL_ADC_CH1 +// $[ADC_CH1_SL_ADC_CH1] #ifndef SL_ADC_CH1_PERIPHERAL -#define SL_ADC_CH1_PERIPHERAL ADC +#define SL_ADC_CH1_PERIPHERAL ADC_CH1 #endif -// ADC P0 on ULP_GPIO_1/GPIO_65 -#ifndef SL_ADC_CH1_P0_PORT -#define SL_ADC_CH1_P0_PORT 0 +// ADC_CH1 P1 on ULP_GPIO_1/GPIO_65 +#ifndef SL_ADC_CH1_P1_PORT +#define SL_ADC_CH1_P1_PORT 0 #endif -#ifndef SL_ADC_CH1_P0_PIN -#define SL_ADC_CH1_P0_PIN 1 +#ifndef SL_ADC_CH1_P1_PIN +#define SL_ADC_CH1_P1_PIN 1 #endif -#ifndef SL_ADC_CH1_P0_LOC -#define SL_ADC_CH1_P0_LOC 10 +#ifndef SL_ADC_CH1_P1_LOC +#define SL_ADC_CH1_P1_LOC 10 #endif -// ADC N0 on GPIO_28 -#ifndef SL_ADC_CH1_N0_PORT -#define SL_ADC_CH1_N0_PORT 0 +// ADC_CH1 N1 on GPIO_28 +#ifndef SL_ADC_CH1_N1_PORT +#define SL_ADC_CH1_N1_PORT 0 #endif -#ifndef SL_ADC_CH1_N0_PIN -#define SL_ADC_CH1_N0_PIN 28 +#ifndef SL_ADC_CH1_N1_PIN +#define SL_ADC_CH1_N1_PIN 28 #endif -#ifndef SL_ADC_CH1_N0_LOC -#define SL_ADC_CH1_N0_LOC 350 +#ifndef SL_ADC_CH1_N1_LOC +#define SL_ADC_CH1_N1_LOC 350 #endif -// [ADC_SL_ADC_CH1]$ +// [ADC_CH1_SL_ADC_CH1]$ // <<< sl:end pin_tool >>> -#define SL_ADC_CHANNEL_1_POS_INPUT_CHNL_SEL SL_ADC_CH1_P0_LOC -#define SL_ADC_CHANNEL_1_NEG_INPUT_CHNL_SEL (SL_ADC_CH1_N0_LOC - N0_START_LOCATION_PINTOOL) +#ifdef SL_ADC_CH1_P1_LOC +#define SL_ADC_CHANNEL_1_POS_INPUT_CHNL_SEL SL_ADC_CH1_P1_LOC +#else +#define SL_ADC_CHANNEL_1_POS_INPUT_CHNL_SEL 10 +#endif +#ifdef SL_ADC_CH1_N1_LOC +#define SL_ADC_CHANNEL_1_NEG_INPUT_CHNL_SEL (SL_ADC_CH1_N1_LOC - N1_START_LOCATION_PINTOOL) +#else +#define SL_ADC_CHANNEL_1_NEG_INPUT_CHNL_SEL 7 +#endif #ifdef __cplusplus } diff --git a/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_2_config.h b/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_2_config.h index 493d7fa79..ddc310622 100644 --- a/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_2_config.h +++ b/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_2_config.h @@ -37,8 +37,8 @@ extern "C" { /******************************************************************************/ /**************************** ADC Channel Configuration ***********************/ -#define P1_START_LOCATION_PINTOOL 19 -#define N1_START_LOCATION_PINTOOL 352 +#define P2_START_LOCATION_PINTOOL 19 +#define N2_START_LOCATION_PINTOOL 352 // <<< Use Configuration Wizard in Context Menu >>> // ADC Channel Configuration @@ -60,38 +60,46 @@ extern "C" { // <<< end of configuration section >>> // <<< sl:start pin_tool >>> -// SL_ADC_CH2 -// $[ADC_SL_ADC_CH2] +// SL_ADC_CH2 +// $[ADC_CH2_SL_ADC_CH2] #ifndef SL_ADC_CH2_PERIPHERAL -#define SL_ADC_CH2_PERIPHERAL ADC +#define SL_ADC_CH2_PERIPHERAL ADC_CH2 #endif -// ADC P1 on ULP_GPIO_10/GPIO_74 -#ifndef SL_ADC_CH2_P1_PORT -#define SL_ADC_CH2_P1_PORT 0 +// ADC_CH2 P2 on GPIO_27 +#ifndef SL_ADC_CH2_P2_PORT +#define SL_ADC_CH2_P2_PORT 0 #endif -#ifndef SL_ADC_CH2_P1_PIN -#define SL_ADC_CH2_P1_PIN 10 +#ifndef SL_ADC_CH2_P2_PIN +#define SL_ADC_CH2_P2_PIN 27 #endif -#ifndef SL_ADC_CH2_P1_LOC -#define SL_ADC_CH2_P1_LOC 24 +#ifndef SL_ADC_CH2_P2_LOC +#define SL_ADC_CH2_P2_LOC 26 #endif -// ADC N1 on GPIO_30 -#ifndef SL_ADC_CH2_N1_PORT -#define SL_ADC_CH2_N1_PORT 0 +// ADC_CH2 N2 on GPIO_30 +#ifndef SL_ADC_CH2_N2_PORT +#define SL_ADC_CH2_N2_PORT 0 #endif -#ifndef SL_ADC_CH2_N1_PIN -#define SL_ADC_CH2_N1_PIN 30 +#ifndef SL_ADC_CH2_N2_PIN +#define SL_ADC_CH2_N2_PIN 30 #endif -#ifndef SL_ADC_CH2_N1_LOC -#define SL_ADC_CH2_N1_LOC 360 +#ifndef SL_ADC_CH2_N2_LOC +#define SL_ADC_CH2_N2_LOC 360 #endif -// [ADC_SL_ADC_CH2]$ +// [ADC_CH2_SL_ADC_CH2]$ // <<< sl:end pin_tool >>> -#define SL_ADC_CHANNEL_2_POS_INPUT_CHNL_SEL (SL_ADC_CH2_P1_LOC - P1_START_LOCATION_PINTOOL) -#define SL_ADC_CHANNEL_2_NEG_INPUT_CHNL_SEL (SL_ADC_CH2_N1_LOC - N1_START_LOCATION_PINTOOL) +#ifdef SL_ADC_CH2_P2_LOC +#define SL_ADC_CHANNEL_2_POS_INPUT_CHNL_SEL (SL_ADC_CH2_P2_LOC - P2_START_LOCATION_PINTOOL) +#else +#define SL_ADC_CHANNEL_2_POS_INPUT_CHNL_SEL 7 +#endif +#ifdef SL_ADC_CH2_N2_LOC +#define SL_ADC_CHANNEL_2_NEG_INPUT_CHNL_SEL (SL_ADC_CH2_N2_LOC - N2_START_LOCATION_PINTOOL) +#else +#define SL_ADC_CHANNEL_2_NEG_INPUT_CHNL_SEL 8 +#endif #ifdef __cplusplus } diff --git a/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_3_config.h b/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_3_config.h index eb185e586..49bdd8885 100644 --- a/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_3_config.h +++ b/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_3_config.h @@ -37,8 +37,8 @@ extern "C" { /******************************************************************************/ /**************************** ADC Channel Configuration ***********************/ -#define P2_START_LOCATION_PINTOOL 38 -#define N2_START_LOCATION_PINTOOL 361 +#define P3_START_LOCATION_PINTOOL 38 +#define N3_START_LOCATION_PINTOOL 361 // <<< Use Configuration Wizard in Context Menu >>> // ADC Channel Configuration @@ -60,37 +60,45 @@ extern "C" { // <<< end of configuration section >>> // <<< sl:start pin_tool >>> -// SL_ADC_CH3 -// $[ADC_SL_ADC_CH3] +// SL_ADC_CH3 +// $[ADC_CH3_SL_ADC_CH3] #ifndef SL_ADC_CH3_PERIPHERAL -#define SL_ADC_CH3_PERIPHERAL ADC +#define SL_ADC_CH3_PERIPHERAL ADC_CH3 #endif -// ADC P2 on ULP_GPIO_8/GPIO_72 -#ifndef SL_ADC_CH3_P2_PORT -#define SL_ADC_CH3_P2_PORT 0 +// ADC_CH3 P3 on ULP_GPIO_8/GPIO_72 +#ifndef SL_ADC_CH3_P3_PORT +#define SL_ADC_CH3_P3_PORT 0 #endif -#ifndef SL_ADC_CH3_P2_PIN -#define SL_ADC_CH3_P2_PIN 8 +#ifndef SL_ADC_CH3_P3_PIN +#define SL_ADC_CH3_P3_PIN 8 #endif -#ifndef SL_ADC_CH3_P2_LOC -#define SL_ADC_CH3_P2_LOC 42 +#ifndef SL_ADC_CH3_P3_LOC +#define SL_ADC_CH3_P3_LOC 42 #endif -// ADC N2 on GPIO_26 -#ifndef SL_ADC_CH3_N2_PORT -#define SL_ADC_CH3_N2_PORT 0 +// ADC_CH3 N3 on GPIO_26 +#ifndef SL_ADC_CH3_N3_PORT +#define SL_ADC_CH3_N3_PORT 0 #endif -#ifndef SL_ADC_CH3_N2_PIN -#define SL_ADC_CH3_N2_PIN 26 +#ifndef SL_ADC_CH3_N3_PIN +#define SL_ADC_CH3_N3_PIN 26 #endif -#ifndef SL_ADC_CH3_N2_LOC -#define SL_ADC_CH3_N2_LOC 367 +#ifndef SL_ADC_CH3_N3_LOC +#define SL_ADC_CH3_N3_LOC 367 #endif -// [ADC_SL_ADC_CH3]$ +// [ADC_CH3_SL_ADC_CH3]$ // <<< sl:end pin_tool >>> -#define SL_ADC_CHANNEL_3_POS_INPUT_CHNL_SEL (SL_ADC_CH3_P2_LOC - P2_START_LOCATION_PINTOOL) -#define SL_ADC_CHANNEL_3_NEG_INPUT_CHNL_SEL (SL_ADC_CH3_N2_LOC - N2_START_LOCATION_PINTOOL) +#ifdef SL_ADC_CH3_P3_LOC +#define SL_ADC_CHANNEL_3_POS_INPUT_CHNL_SEL (SL_ADC_CH3_P3_LOC - P3_START_LOCATION_PINTOOL) +#else +#define SL_ADC_CHANNEL_3_POS_INPUT_CHNL_SEL 4 +#endif +#ifdef SL_ADC_CH3_N3_LOC +#define SL_ADC_CHANNEL_3_NEG_INPUT_CHNL_SEL (SL_ADC_CH3_N3_LOC - N3_START_LOCATION_PINTOOL) +#else +#define SL_ADC_CHANNEL_3_NEG_INPUT_CHNL_SEL 6 +#endif #ifdef __cplusplus } diff --git a/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_4_config.h b/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_4_config.h index 10bc2c645..6fcc2ce25 100644 --- a/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_4_config.h +++ b/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_4_config.h @@ -37,8 +37,8 @@ extern "C" { /******************************************************************************/ /**************************** ADC Channel Configuration ***********************/ -#define P3_START_LOCATION_PINTOOL 57 -#define N3_START_LOCATION_PINTOOL 370 +#define P4_START_LOCATION_PINTOOL 57 +#define N4_START_LOCATION_PINTOOL 370 // <<< Use Configuration Wizard in Context Menu >>> // ADC Channel Configuration @@ -60,37 +60,45 @@ extern "C" { // <<< end of configuration section >>> // <<< sl:start pin_tool >>> -// SL_ADC_CH4 -// $[ADC_SL_ADC_CH4] +// SL_ADC_CH4 +// $[ADC_CH4_SL_ADC_CH4] #ifndef SL_ADC_CH4_PERIPHERAL -#define SL_ADC_CH4_PERIPHERAL ADC +#define SL_ADC_CH4_PERIPHERAL ADC_CH4 #endif -// ADC P3 on GPIO_25 -#ifndef SL_ADC_CH4_P3_PORT -#define SL_ADC_CH4_P3_PORT 0 +// ADC_CH4 P4 on GPIO_25 +#ifndef SL_ADC_CH4_P4_PORT +#define SL_ADC_CH4_P4_PORT 0 #endif -#ifndef SL_ADC_CH4_P3_PIN -#define SL_ADC_CH4_P3_PIN 25 +#ifndef SL_ADC_CH4_P4_PIN +#define SL_ADC_CH4_P4_PIN 25 #endif -#ifndef SL_ADC_CH4_P3_LOC -#define SL_ADC_CH4_P3_LOC 63 +#ifndef SL_ADC_CH4_P4_LOC +#define SL_ADC_CH4_P4_LOC 63 #endif -// ADC N3 on ULP_GPIO_7/GPIO_71 -#ifndef SL_ADC_CH4_N3_PORT -#define SL_ADC_CH4_N3_PORT 0 +// ADC_CH4 N4 on ULP_GPIO_7/GPIO_71 +#ifndef SL_ADC_CH4_N4_PORT +#define SL_ADC_CH4_N4_PORT 0 #endif -#ifndef SL_ADC_CH4_N3_PIN -#define SL_ADC_CH4_N3_PIN 7 +#ifndef SL_ADC_CH4_N4_PIN +#define SL_ADC_CH4_N4_PIN 7 #endif -#ifndef SL_ADC_CH4_N3_LOC -#define SL_ADC_CH4_N3_LOC 375 +#ifndef SL_ADC_CH4_N4_LOC +#define SL_ADC_CH4_N4_LOC 375 #endif -// [ADC_SL_ADC_CH4]$ +// [ADC_CH4_SL_ADC_CH4]$ // <<< sl:end pin_tool >>> -#define SL_ADC_CHANNEL_4_POS_INPUT_CHNL_SEL (SL_ADC_CH4_P3_LOC - P3_START_LOCATION_PINTOOL) -#define SL_ADC_CHANNEL_4_NEG_INPUT_CHNL_SEL (SL_ADC_CH4_N3_LOC - N3_START_LOCATION_PINTOOL) +#ifdef SL_ADC_CH4_P4_LOC +#define SL_ADC_CHANNEL_4_POS_INPUT_CHNL_SEL (SL_ADC_CH4_P4_LOC - P4_START_LOCATION_PINTOOL) +#else +#define SL_ADC_CHANNEL_4_POS_INPUT_CHNL_SEL 6 +#endif +#ifdef SL_ADC_CH4_N4_LOC +#define SL_ADC_CHANNEL_4_NEG_INPUT_CHNL_SEL (SL_ADC_CH4_N4_LOC - N4_START_LOCATION_PINTOOL) +#else +#define SL_ADC_CHANNEL_4_NEG_INPUT_CHNL_SEL 5 +#endif #ifdef __cplusplus } diff --git a/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_5_config.h b/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_5_config.h index 6a4c83b1f..0f04dfc1f 100644 --- a/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_5_config.h +++ b/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_5_config.h @@ -37,8 +37,8 @@ extern "C" { /******************************************************************************/ /**************************** ADC Channel Configuration ***********************/ -#define P4_START_LOCATION_PINTOOL 76 -#define N4_START_LOCATION_PINTOOL 379 +#define P5_START_LOCATION_PINTOOL 76 +#define N5_START_LOCATION_PINTOOL 379 // <<< Use Configuration Wizard in Context Menu >>> // ADC Channel Configuration @@ -60,38 +60,46 @@ extern "C" { // <<< end of configuration section >>> // <<< sl:start pin_tool >>> -// SL_ADC_CH5 -// $[ADC_SL_ADC_CH5] +// SL_ADC_CH5 +// $[ADC_CH5_SL_ADC_CH5] #ifndef SL_ADC_CH5_PERIPHERAL -#define SL_ADC_CH5_PERIPHERAL ADC +#define SL_ADC_CH5_PERIPHERAL ADC_CH5 #endif -// ADC P4 on ULP_GPIO_8/GPIO_72 -#ifndef SL_ADC_CH5_P4_PORT -#define SL_ADC_CH5_P4_PORT 0 +// ADC_CH5 P5 on ULP_GPIO_8/GPIO_72 +#ifndef SL_ADC_CH5_P5_PORT +#define SL_ADC_CH5_P5_PORT 0 #endif -#ifndef SL_ADC_CH5_P4_PIN -#define SL_ADC_CH5_P4_PIN 8 +#ifndef SL_ADC_CH5_P5_PIN +#define SL_ADC_CH5_P5_PIN 8 #endif -#ifndef SL_ADC_CH5_P4_LOC -#define SL_ADC_CH5_P4_LOC 80 +#ifndef SL_ADC_CH5_P5_LOC +#define SL_ADC_CH5_P5_LOC 80 #endif -// ADC N4 on ULP_GPIO_1/GPIO_65 -#ifndef SL_ADC_CH5_N4_PORT -#define SL_ADC_CH5_N4_PORT 0 +// ADC_CH5 N5 on ULP_GPIO_1/GPIO_65 +#ifndef SL_ADC_CH5_N5_PORT +#define SL_ADC_CH5_N5_PORT 0 #endif -#ifndef SL_ADC_CH5_N4_PIN -#define SL_ADC_CH5_N4_PIN 1 +#ifndef SL_ADC_CH5_N5_PIN +#define SL_ADC_CH5_N5_PIN 1 #endif -#ifndef SL_ADC_CH5_N4_LOC -#define SL_ADC_CH5_N4_LOC 379 +#ifndef SL_ADC_CH5_N5_LOC +#define SL_ADC_CH5_N5_LOC 379 #endif -// [ADC_SL_ADC_CH5]$ +// [ADC_CH5_SL_ADC_CH5]$ // <<< sl:end pin_tool >>> -#define SL_ADC_CHANNEL_5_POS_INPUT_CHNL_SEL (SL_ADC_CH5_P4_LOC - P4_START_LOCATION_PINTOOL) -#define SL_ADC_CHANNEL_5_NEG_INPUT_CHNL_SEL (SL_ADC_CH5_N4_LOC - N4_START_LOCATION_PINTOOL) +#ifdef SL_ADC_CH5_P5_LOC +#define SL_ADC_CHANNEL_5_POS_INPUT_CHNL_SEL (SL_ADC_CH5_P5_LOC - P5_START_LOCATION_PINTOOL) +#else +#define SL_ADC_CHANNEL_5_POS_INPUT_CHNL_SEL 4 +#endif +#ifdef SL_ADC_CH5_N5_LOC +#define SL_ADC_CHANNEL_5_NEG_INPUT_CHNL_SEL (SL_ADC_CH5_N5_LOC - N5_START_LOCATION_PINTOOL) +#else +#define SL_ADC_CHANNEL_5_NEG_INPUT_CHNL_SEL 0 +#endif #ifdef __cplusplus } diff --git a/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_6_config.h b/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_6_config.h index 8a788658a..7672a13d9 100644 --- a/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_6_config.h +++ b/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_6_config.h @@ -37,8 +37,8 @@ extern "C" { /******************************************************************************/ /**************************** ADC Channel Configuration ***********************/ -#define P5_START_LOCATION_PINTOOL 95 -#define N5_START_LOCATION_PINTOOL 388 +#define P6_START_LOCATION_PINTOOL 95 +#define N6_START_LOCATION_PINTOOL 388 // <<< Use Configuration Wizard in Context Menu >>> // ADC Channel Configuration @@ -60,38 +60,46 @@ extern "C" { // <<< end of configuration section >>> // <<< sl:start pin_tool >>> -// SL_ADC_CH6 -// $[ADC_SL_ADC_CH6] +// SL_ADC_CH6 +// $[ADC_CH6_SL_ADC_CH6] #ifndef SL_ADC_CH6_PERIPHERAL -#define SL_ADC_CH6_PERIPHERAL ADC +#define SL_ADC_CH6_PERIPHERAL ADC_CH6 #endif -// ADC P5 on ULP_GPIO_10/GPIO_74 -#ifndef SL_ADC_CH6_P5_PORT -#define SL_ADC_CH6_P5_PORT 0 +// ADC_CH6 P6 on ULP_GPIO_10/GPIO_74 +#ifndef SL_ADC_CH6_P6_PORT +#define SL_ADC_CH6_P6_PORT 0 #endif -#ifndef SL_ADC_CH6_P5_PIN -#define SL_ADC_CH6_P5_PIN 10 +#ifndef SL_ADC_CH6_P6_PIN +#define SL_ADC_CH6_P6_PIN 10 #endif -#ifndef SL_ADC_CH6_P5_LOC -#define SL_ADC_CH6_P5_LOC 100 +#ifndef SL_ADC_CH6_P6_LOC +#define SL_ADC_CH6_P6_LOC 100 #endif -// ADC N5 on ULP_GPIO_7/GPIO_71 -#ifndef SL_ADC_CH6_N5_PORT -#define SL_ADC_CH6_N5_PORT 0 +// ADC_CH6 N6 on ULP_GPIO_7/GPIO_71 +#ifndef SL_ADC_CH6_N6_PORT +#define SL_ADC_CH6_N6_PORT 0 #endif -#ifndef SL_ADC_CH6_N5_PIN -#define SL_ADC_CH6_N5_PIN 7 +#ifndef SL_ADC_CH6_N6_PIN +#define SL_ADC_CH6_N6_PIN 7 #endif -#ifndef SL_ADC_CH6_N5_LOC -#define SL_ADC_CH6_N5_LOC 393 +#ifndef SL_ADC_CH6_N6_LOC +#define SL_ADC_CH6_N6_LOC 393 #endif -// [ADC_SL_ADC_CH6]$ +// [ADC_CH6_SL_ADC_CH6]$ // <<< sl:end pin_tool >>> -#define SL_ADC_CHANNEL_6_POS_INPUT_CHNL_SEL (SL_ADC_CH6_P5_LOC - P5_START_LOCATION_PINTOOL) -#define SL_ADC_CHANNEL_6_NEG_INPUT_CHNL_SEL (SL_ADC_CH6_N5_LOC - N5_START_LOCATION_PINTOOL) +#ifdef SL_ADC_CH6_P6_LOC +#define SL_ADC_CHANNEL_6_POS_INPUT_CHNL_SEL (SL_ADC_CH6_P6_LOC - P6_START_LOCATION_PINTOOL) +#else +#define SL_ADC_CHANNEL_6_POS_INPUT_CHNL_SEL 5 +#endif +#ifdef SL_ADC_CH6_N6_LOC +#define SL_ADC_CHANNEL_6_NEG_INPUT_CHNL_SEL (SL_ADC_CH6_N6_LOC - N6_START_LOCATION_PINTOOL) +#else +#define SL_ADC_CHANNEL_6_NEG_INPUT_CHNL_SEL 5 +#endif #ifdef __cplusplus } diff --git a/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_7_config.h b/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_7_config.h index 9a452a226..fe4e522e9 100644 --- a/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_7_config.h +++ b/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_7_config.h @@ -37,8 +37,8 @@ extern "C" { /******************************************************************************/ /**************************** ADC Channel Configuration ***********************/ -#define P6_START_LOCATION_PINTOOL 114 -#define N6_START_LOCATION_PINTOOL 397 +#define P7_START_LOCATION_PINTOOL 114 +#define N7_START_LOCATION_PINTOOL 397 // <<< Use Configuration Wizard in Context Menu >>> // ADC Channel Configuration @@ -60,38 +60,46 @@ extern "C" { // <<< end of configuration section >>> // <<< sl:start pin_tool >>> -// SL_ADC_CH7 -// $[ADC_SL_ADC_CH7] +// SL_ADC_CH7 +// $[ADC_CH7_SL_ADC_CH7] #ifndef SL_ADC_CH7_PERIPHERAL -#define SL_ADC_CH7_PERIPHERAL ADC +#define SL_ADC_CH7_PERIPHERAL ADC_CH7 #endif -// ADC P6 on GPIO_25 -#ifndef SL_ADC_CH7_P6_PORT -#define SL_ADC_CH7_P6_PORT 0 +// ADC_CH7 P7 on GPIO_25 +#ifndef SL_ADC_CH7_P7_PORT +#define SL_ADC_CH7_P7_PORT 0 #endif -#ifndef SL_ADC_CH7_P6_PIN -#define SL_ADC_CH7_P6_PIN 25 +#ifndef SL_ADC_CH7_P7_PIN +#define SL_ADC_CH7_P7_PIN 25 #endif -#ifndef SL_ADC_CH7_P6_LOC -#define SL_ADC_CH7_P6_LOC 120 +#ifndef SL_ADC_CH7_P7_LOC +#define SL_ADC_CH7_P7_LOC 120 #endif -// ADC N6 on GPIO_26 -#ifndef SL_ADC_CH7_N6_PORT -#define SL_ADC_CH7_N6_PORT 0 +// ADC_CH7 N7 on GPIO_26 +#ifndef SL_ADC_CH7_N7_PORT +#define SL_ADC_CH7_N7_PORT 0 #endif -#ifndef SL_ADC_CH7_N6_PIN -#define SL_ADC_CH7_N6_PIN 26 +#ifndef SL_ADC_CH7_N7_PIN +#define SL_ADC_CH7_N7_PIN 26 #endif -#ifndef SL_ADC_CH7_N6_LOC -#define SL_ADC_CH7_N6_LOC 403 +#ifndef SL_ADC_CH7_N7_LOC +#define SL_ADC_CH7_N7_LOC 403 #endif -// [ADC_SL_ADC_CH7]$ +// [ADC_CH7_SL_ADC_CH7]$ // <<< sl:end pin_tool >>> -#define SL_ADC_CHANNEL_7_POS_INPUT_CHNL_SEL (SL_ADC_CH7_P6_LOC - P6_START_LOCATION_PINTOOL) -#define SL_ADC_CHANNEL_7_NEG_INPUT_CHNL_SEL (SL_ADC_CH7_N6_LOC - N6_START_LOCATION_PINTOOL) +#ifdef SL_ADC_CH7_P7_LOC +#define SL_ADC_CHANNEL_7_POS_INPUT_CHNL_SEL (SL_ADC_CH7_P7_LOC - P7_START_LOCATION_PINTOOL) +#else +#define SL_ADC_CHANNEL_7_POS_INPUT_CHNL_SEL 6 +#endif +#ifdef SL_ADC_CH7_N7_LOC +#define SL_ADC_CHANNEL_7_NEG_INPUT_CHNL_SEL (SL_ADC_CH7_N7_LOC - N7_START_LOCATION_PINTOOL) +#else +#define SL_ADC_CHANNEL_7_NEG_INPUT_CHNL_SEL 6 +#endif #ifdef __cplusplus } diff --git a/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_8_config.h b/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_8_config.h index 226851f1b..fff811862 100644 --- a/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_8_config.h +++ b/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_8_config.h @@ -37,8 +37,8 @@ extern "C" { /******************************************************************************/ /******************************* ADC Channel Configuration **************************/ -#define P7_START_LOCATION_PINTOOL 133 -#define N7_START_LOCATION_PINTOOL 406 +#define P8_START_LOCATION_PINTOOL 133 +#define N8_START_LOCATION_PINTOOL 406 // <<< Use Configuration Wizard in Context Menu >>> // ADC Channel Configuration @@ -60,38 +60,46 @@ extern "C" { // <<< end of configuration section >>> // <<< sl:start pin_tool >>> -// SL_ADC_CH8 -// $[ADC_SL_ADC_CH8] +// SL_ADC_CH8 +// $[ADC_CH8_SL_ADC_CH8] #ifndef SL_ADC_CH8_PERIPHERAL -#define SL_ADC_CH8_PERIPHERAL ADC +#define SL_ADC_CH8_PERIPHERAL ADC_CH8 #endif -// ADC P7 on GPIO_27 -#ifndef SL_ADC_CH8_P7_PORT -#define SL_ADC_CH8_P7_PORT 0 +// ADC_CH8 P8 on GPIO_27 +#ifndef SL_ADC_CH8_P8_PORT +#define SL_ADC_CH8_P8_PORT 0 #endif -#ifndef SL_ADC_CH8_P7_PIN -#define SL_ADC_CH8_P7_PIN 27 +#ifndef SL_ADC_CH8_P8_PIN +#define SL_ADC_CH8_P8_PIN 27 #endif -#ifndef SL_ADC_CH8_P7_LOC -#define SL_ADC_CH8_P7_LOC 140 +#ifndef SL_ADC_CH8_P8_LOC +#define SL_ADC_CH8_P8_LOC 140 #endif -// ADC N7 on GPIO_28 -#ifndef SL_ADC_CH8_N7_PORT -#define SL_ADC_CH8_N7_PORT 0 +// ADC_CH8 N8 on GPIO_28 +#ifndef SL_ADC_CH8_N8_PORT +#define SL_ADC_CH8_N8_PORT 0 #endif -#ifndef SL_ADC_CH8_N7_PIN -#define SL_ADC_CH8_N7_PIN 28 +#ifndef SL_ADC_CH8_N8_PIN +#define SL_ADC_CH8_N8_PIN 28 #endif -#ifndef SL_ADC_CH8_N7_LOC -#define SL_ADC_CH8_N7_LOC 413 +#ifndef SL_ADC_CH8_N8_LOC +#define SL_ADC_CH8_N8_LOC 413 #endif -// [ADC_SL_ADC_CH8]$ +// [ADC_CH8_SL_ADC_CH8]$ // <<< sl:end pin_tool >>> -#define SL_ADC_CHANNEL_8_POS_INPUT_CHNL_SEL (SL_ADC_CH8_P7_LOC - P7_START_LOCATION_PINTOOL) -#define SL_ADC_CHANNEL_8_NEG_INPUT_CHNL_SEL (SL_ADC_CH8_N7_LOC - N7_START_LOCATION_PINTOOL) +#ifdef SL_ADC_CH8_P8_LOC +#define SL_ADC_CHANNEL_8_POS_INPUT_CHNL_SEL (SL_ADC_CH8_P8_LOC - P8_START_LOCATION_PINTOOL) +#else +#define SL_ADC_CHANNEL_8_POS_INPUT_CHNL_SEL 7 +#endif +#ifdef SL_ADC_CH8_N8_LOC +#define SL_ADC_CHANNEL_8_NEG_INPUT_CHNL_SEL (SL_ADC_CH8_N8_LOC - N8_START_LOCATION_PINTOOL) +#else +#define SL_ADC_CHANNEL_8_NEG_INPUT_CHNL_SEL 7 +#endif #ifdef __cplusplus } diff --git a/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_9_config.h b/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_9_config.h index 4fe4bcc92..3890487e5 100644 --- a/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_9_config.h +++ b/components/board/silabs/config/common_config/sl_si91x_adc_init_channel_9_config.h @@ -37,8 +37,8 @@ extern "C" { /******************************************************************************/ /******************************* ADC Channel Configuration **************************/ -#define P8_START_LOCATION_PINTOOL 152 -#define N8_START_LOCATION_PINTOOL 415 +#define P9_START_LOCATION_PINTOOL 152 +#define N9_START_LOCATION_PINTOOL 415 // <<< Use Configuration Wizard in Context Menu >>> // ADC Channel Configuration @@ -60,38 +60,46 @@ extern "C" { // <<< end of configuration section >>> // <<< sl:start pin_tool >>> -// SL_ADC_CH9 -// $[ADC_SL_ADC_CH9] +// SL_ADC_CH9 +// $[ADC_CH9_SL_ADC_CH9] #ifndef SL_ADC_CH9_PERIPHERAL -#define SL_ADC_CH9_PERIPHERAL ADC +#define SL_ADC_CH9_PERIPHERAL ADC_CH9 #endif -// ADC P8 on GPIO_29 -#ifndef SL_ADC_CH9_P8_PORT -#define SL_ADC_CH9_P8_PORT 0 +// ADC_CH9 P9 on GPIO_29 +#ifndef SL_ADC_CH9_P9_PORT +#define SL_ADC_CH9_P9_PORT 0 #endif -#ifndef SL_ADC_CH9_P8_PIN -#define SL_ADC_CH9_P8_PIN 29 +#ifndef SL_ADC_CH9_P9_PIN +#define SL_ADC_CH9_P9_PIN 29 #endif -#ifndef SL_ADC_CH9_P8_LOC -#define SL_ADC_CH9_P8_LOC 160 +#ifndef SL_ADC_CH9_P9_LOC +#define SL_ADC_CH9_P9_LOC 160 #endif -// ADC N8 on GPIO_30 -#ifndef SL_ADC_CH9_N8_PORT -#define SL_ADC_CH9_N8_PORT 0 +// ADC_CH9 N9 on GPIO_30 +#ifndef SL_ADC_CH9_N9_PORT +#define SL_ADC_CH9_N9_PORT 0 #endif -#ifndef SL_ADC_CH9_N8_PIN -#define SL_ADC_CH9_N8_PIN 30 +#ifndef SL_ADC_CH9_N9_PIN +#define SL_ADC_CH9_N9_PIN 30 #endif -#ifndef SL_ADC_CH9_N8_LOC -#define SL_ADC_CH9_N8_LOC 423 +#ifndef SL_ADC_CH9_N9_LOC +#define SL_ADC_CH9_N9_LOC 423 #endif -// [ADC_SL_ADC_CH9]$ +// [ADC_CH9_SL_ADC_CH9]$ // <<< sl:end pin_tool >>> -#define SL_ADC_CHANNEL_9_POS_INPUT_CHNL_SEL (SL_ADC_CH9_P8_LOC - P8_START_LOCATION_PINTOOL) -#define SL_ADC_CHANNEL_9_NEG_INPUT_CHNL_SEL (SL_ADC_CH9_N8_LOC - N8_START_LOCATION_PINTOOL) +#ifdef SL_ADC_CH9_P9_LOC +#define SL_ADC_CHANNEL_9_POS_INPUT_CHNL_SEL (SL_ADC_CH9_P9_LOC - P9_START_LOCATION_PINTOOL) +#else +#define SL_ADC_CHANNEL_9_POS_INPUT_CHNL_SEL 8 +#endif +#ifdef SL_ADC_CH9_N9_LOC +#define SL_ADC_CHANNEL_9_NEG_INPUT_CHNL_SEL (SL_ADC_CH9_N9_LOC - N9_START_LOCATION_PINTOOL) +#else +#define SL_ADC_CHANNEL_9_NEG_INPUT_CHNL_SEL 8 +#endif #ifdef __cplusplus } diff --git a/components/board/silabs/config/common_config/sl_si91x_analog_comparator_comparator2_config.h b/components/board/silabs/config/common_config/sl_si91x_analog_comparator_comparator2_config.h index 07a627993..6abff35df 100644 --- a/components/board/silabs/config/common_config/sl_si91x_analog_comparator_comparator2_config.h +++ b/components/board/silabs/config/common_config/sl_si91x_analog_comparator_comparator2_config.h @@ -102,10 +102,12 @@ // <<< sl:end pin_tool >>> #if (SL_ANALOG_COMPARATOR_NON_INVERTING_INPUT == SL_COMPARATOR_GPIO_INPUT_1) -#define SL_ANALOG_COMPARATOR_NON_INVERTING_PIN_INPUT SL_COMP2_P1_LOC +// Converting location value to get desired pin for comparator2 non-inverting input +#define SL_ANALOG_COMPARATOR_NON_INVERTING_PIN_INPUT SL_COMP2_P1_LOC - 1 #endif #if (SL_ANALOG_COMPARATOR_INVERTING_INPUT == SL_COMPARATOR_GPIO_INPUT_1) -#define SL_ANALOG_COMPARATOR_INVERTING_PIN_INPUT SL_COMP2_N1_LOC +// Converting location value to get desired pin for comparator2 inverting input +#define SL_ANALOG_COMPARATOR_INVERTING_PIN_INPUT SL_COMP2_N1_LOC - 2 #endif #endif // SL_ANALOG_COMPARATOR_COMPARATOR2_CONFIG_H \ No newline at end of file diff --git a/components/board/silabs/config/common_config/sl_si91x_pwm_init_channel_0_config.h b/components/board/silabs/config/common_config/sl_si91x_pwm_init_channel_0_config.h index b9a5fba6f..6b731eb11 100644 --- a/components/board/silabs/config/common_config/sl_si91x_pwm_init_channel_0_config.h +++ b/components/board/silabs/config/common_config/sl_si91x_pwm_init_channel_0_config.h @@ -38,7 +38,6 @@ extern "C" { /******************************************************************************/ /******************************* PWM Configuration **************************/ // PWM CHANNEL_0 Configuration - // Frequency <500-200000> // Default: 25000 #define SL_PWM_CHANNEL_0_FREQUENCY 25000 @@ -90,34 +89,45 @@ extern "C" { // End PWM CHANNEL_0 Configuration /******************************************************************************/ // <<< end of configuration section >>> - // <<< sl:start pin_tool >>> -// SL_PWM_CHANNEL0 -// $[PWM_SL_PWM_CHANNEL0] -#ifndef SL_PWM_CHANNEL0_PERIPHERAL -#define SL_PWM_CHANNEL0_PERIPHERAL PWM +// SL_PWM_OUT_CHANNEL0 +// $[PWM_CH0_SL_PWM_OUT_CHANNEL0] +#ifndef SL_PWM_OUT_CHANNEL0_PERIPHERAL +#define SL_PWM_OUT_CHANNEL0_PERIPHERAL PWM_CH0 +#endif +#ifndef SL_PWM_OUT_CHANNEL0_PERIPHERAL_NO +#define SL_PWM_OUT_CHANNEL0_PERIPHERAL_NO 0 #endif -// PWM 1H on GPIO_7 -#ifndef SL_PWM_CHANNEL0_1H_PORT -#define SL_PWM_CHANNEL0_1H_PORT 0 +// PWM_CH0 0H on GPIO_7 +#ifndef SL_PWM_OUT_CHANNEL0_0H_PORT +#define SL_PWM_OUT_CHANNEL0_0H_PORT 0 #endif -#ifndef SL_PWM_CHANNEL0_1H_PIN -#define SL_PWM_CHANNEL0_1H_PIN 7 +#ifndef SL_PWM_OUT_CHANNEL0_0H_PIN +#define SL_PWM_OUT_CHANNEL0_0H_PIN 7 #endif -#ifndef SL_PWM_CHANNEL0_1H_LOC -#define SL_PWM_CHANNEL0_1H_LOC 0 +#ifndef SL_PWM_OUT_CHANNEL0_0H_LOC +#define SL_PWM_OUT_CHANNEL0_0H_LOC 0 #endif -// PWM 1L on GPIO_6 -#ifndef SL_PWM_CHANNEL0_1L_PORT -#define SL_PWM_CHANNEL0_1L_PORT 0 +// PWM_CH0 0L on GPIO_6 +#ifndef SL_PWM_OUT_CHANNEL0_0L_PORT +#define SL_PWM_OUT_CHANNEL0_0L_PORT 0 +#endif +#ifndef SL_PWM_OUT_CHANNEL0_0L_PIN +#define SL_PWM_OUT_CHANNEL0_0L_PIN 6 #endif -#ifndef SL_PWM_CHANNEL0_1L_PIN -#define SL_PWM_CHANNEL0_1L_PIN 6 +#ifndef SL_PWM_OUT_CHANNEL0_0L_LOC +#define SL_PWM_OUT_CHANNEL0_0L_LOC 2 #endif -#ifndef SL_PWM_CHANNEL0_1L_LOC -#define SL_PWM_CHANNEL0_1L_LOC 2 +// [PWM_CH0_SL_PWM_OUT_CHANNEL0]$ +// <<< sl:end pin_tool >>> + +// <<< sl:start pin_tool >>> +// SL_PWM_CHANNEL0 +// $[PWM_SL_PWM_CHANNEL0] +#ifndef SL_PWM_CHANNEL0_PERIPHERAL +#define SL_PWM_CHANNEL0_PERIPHERAL PWM #endif // PWM FAULTA on GPIO_25 @@ -149,8 +159,8 @@ extern "C" { #ifndef SL_PWM_CHANNEL0_TMR_EXT_TRIG_1_PIN #define SL_PWM_CHANNEL0_TMR_EXT_TRIG_1_PIN 27 #endif -#ifndef SL_PWM_CHANNEL0_TMR_EXT_TRIG_1_LOC -#define SL_PWM_CHANNEL0_TMR_EXT_TRIG_1_LOC 22 +#ifndef SL_PWM_CHANNEL0_EXTTRIG1_LOC +#define SL_PWM_CHANNEL0_EXTTRIG1_LOC 22 #endif // PWM TMR_EXT_TRIG_2 on GPIO_28 @@ -160,8 +170,8 @@ extern "C" { #ifndef SL_PWM_CHANNEL0_TMR_EXT_TRIG_2_PIN #define SL_PWM_CHANNEL0_TMR_EXT_TRIG_2_PIN 28 #endif -#ifndef SL_PWM_CHANNEL0_TMR_EXT_TRIG_2_LOC -#define SL_PWM_CHANNEL0_TMR_EXT_TRIG_2_LOC 26 +#ifndef SL_PWM_CHANNEL0_EXTTRIG2_LOC +#define SL_PWM_CHANNEL0_EXTTRIG2_LOC 26 #endif // [PWM_SL_PWM_CHANNEL0]$ // <<< sl:end pin_tool >>> @@ -169,63 +179,104 @@ extern "C" { // PWM channel number for CHANNEL_0 instance #define SL_PWM_CHANNEL_0_OUTPUT_CHANNEL 0 +#ifdef SL_PWM_OUT_CHANNEL0_0L_LOC // Pin set for CHANNEL_0 PWM channel -#define SL_PWM_CHANNEL_0_PIN_L SL_PWM_CHANNEL0_1L_PIN -#define SL_PWM_CHANNEL_0_PIN_H SL_PWM_CHANNEL0_1H_PIN - -#define SL_PWM_CHANNEL_0_PORT_L SL_PWM_CHANNEL0_1L_PORT -#define SL_PWM_CHANNEL_0_PORT_H SL_PWM_CHANNEL0_1H_PORT +#if (SL_PWM_OUT_CHANNEL0_0L_LOC == 2) +#define SL_PWM_CHANNEL_0_PIN_L SL_PWM_OUT_CHANNEL0_0L_PIN +#else +#define SL_PWM_CHANNEL_0_PIN_L (SL_PWM_OUT_CHANNEL0_0L_PIN + 64) +#endif +#define SL_PWM_CHANNEL_0_PORT_L SL_PWM_OUT_CHANNEL0_0L_PORT +#else +#define SL_PWM_CHANNEL_0_PIN_L SL_SI91X_PWM_0L_PIN +#define SL_PWM_CHANNEL_0_PORT_L SL_SI91X_PWM_0L_PORT +#endif //SL_PWM_OUT_CHANNEL0_0L_LOC +#ifdef SL_PWM_OUT_CHANNEL0_0H_LOC +#if (SL_PWM_OUT_CHANNEL0_0H_LOC == 0) +#define SL_PWM_CHANNEL_0_PIN_H SL_PWM_OUT_CHANNEL0_0H_PIN +#else +#define SL_PWM_CHANNEL_0_PIN_H (SL_PWM_OUT_CHANNEL0_0H_PIN + 64) +#endif +#define SL_PWM_CHANNEL_0_PORT_H SL_PWM_OUT_CHANNEL0_0H_PORT +#else +#define SL_PWM_CHANNEL_0_PIN_H SL_SI91X_PWM_0H_PIN +#define SL_PWM_CHANNEL_0_PORT_H SL_SI91X_PWM_0H_PORT +#endif //SL_PWM_OUT_CHANNEL0_0H_LOC -#define SL_PWM_CHANNEL_0_MUX_L SL_SI91X_PWM_1L_MUX -#define SL_PWM_CHANNEL_0_MUX_H SL_SI91X_PWM_1H_MUX +#define SL_PWM_CHANNEL_0_MUX_L SL_SI91X_PWM_0L_MUX +#define SL_PWM_CHANNEL_0_MUX_H SL_SI91X_PWM_0H_MUX -#define SL_PWM_CHANNEL_0_PAD_L SL_SI91X_PWM_1L_PAD -#define SL_PWM_CHANNEL_0_PAD_H SL_SI91X_PWM_1H_PAD -#define SL_PWM_CHANNEL_0_PAD_HL SL_SI91X_PWM_1H_PAD +#define SL_PWM_CHANNEL_0_PAD_L SL_SI91X_PWM_0L_PAD +#define SL_PWM_CHANNEL_0_PAD_H SL_SI91X_PWM_0H_PAD // PWM Fault Pin set resolution #if (SL_PWM_CHANNEL_0_EVENT == 0) +#ifdef SL_PWM_CHANNEL0_FAULTA_LOC #define SL_PWM_CHANNEL_0_PORT SL_PWM_CHANNEL0_FAULTA_PORT #define SL_PWM_CHANNEL_0_PIN SL_PWM_CHANNEL0_FAULTA_PIN -#define SL_PWM_CHANNEL_0_MUX 0 -#define SL_PWM_CHANNEL_0_PAD SL_SI91X_PWM_FAULTA_PAD +#else +#define SL_PWM_CHANNEL_0_PORT SL_SI91X_PWM_FAULTA_PORT +#define SL_PWM_CHANNEL_0_PIN SL_SI91X_PWM_FAULTA_PIN +#endif //SL_PWM_CHANNEL0_FAULTA_LOC +#define SL_PWM_CHANNEL_0_MUX 0 +#define SL_PWM_CHANNEL_0_PAD SL_SI91X_PWM_FAULTA_PAD #endif #if (SL_PWM_CHANNEL_0_EVENT == 1) +#ifdef SL_PWM_CHANNEL0_FAULTA_LOC #define SL_PWM_CHANNEL_0_PORT SL_PWM_CHANNEL0_FAULTA_PORT #define SL_PWM_CHANNEL_0_PIN SL_PWM_CHANNEL0_FAULTA_PIN -#define SL_PWM_CHANNEL_0_MUX SL_SI91X_PWM_FAULTA_MUX -#define SL_PWM_CHANNEL_0_PAD SL_SI91X_PWM_FAULTA_PAD +#else +#define SL_PWM_CHANNEL_0_PORT SL_SI91X_PWM_FAULTA_PORT +#define SL_PWM_CHANNEL_0_PIN SL_SI91X_PWM_FAULTA_PIN +#endif //SL_PWM_CHANNEL0_FAULTA_LOC +#define SL_PWM_CHANNEL_0_MUX SL_SI91X_PWM_FAULTA_MUX +#define SL_PWM_CHANNEL_0_PAD SL_SI91X_PWM_FAULTA_PAD #endif #if (SL_PWM_CHANNEL_0_EVENT == 2) +#ifdef SL_PWM_CHANNEL0_FAULTB_LOC #define SL_PWM_CHANNEL_0_PORT SL_PWM_CHANNEL0_FAULTB_PORT -#if (SL_PWM_CHANNEL0_FAULTB_LOC == 0) +#if (SL_PWM_CHANNEL0_FAULTB_LOC == 19) #define SL_PWM_CHANNEL_0_PIN SL_PWM_CHANNEL0_FAULTB_PIN #else #define SL_PWM_CHANNEL_0_PIN (SL_PWM_CHANNEL0_FAULTB_PIN + 64) #endif +#else +#define SL_PWM_CHANNEL_0_PORT SL_SI91X_PWM_FAULTB_PORT +#define SL_PWM_CHANNEL_0_PIN SL_SI91X_PWM_FAULTB_PIN +#endif //SL_PWM_CHANNEL0_FAULTB_LOC #define SL_PWM_CHANNEL_0_MUX SL_SI91X_PWM_FAULTB_MUX #define SL_PWM_CHANNEL_0_PAD SL_SI91X_PWM_FAULTB_PAD #endif #if (SL_PWM_CHANNEL_0_EVENT == 3) +#ifdef SL_PWM_CHANNEL0_EXTTRIG1_LOC #define SL_PWM_CHANNEL_0_PORT SL_PWM_CHANNEL0_TMR_EXT_TRIG_1_PORT -#if ((SL_PWM_CHANNEL0_TMR_EXT_TRIG_1_LOC == 2) || (SL_PWM_CHANNEL0_TMR_EXT_TRIG_1_LOC == 3)) +#if ((SL_PWM_CHANNEL0_TMR_EXT_TRIG_1_LOC == 24) || (SL_PWM_CHANNEL0_TMR_EXT_TRIG_1_LOC == 25)) #define SL_PWM_CHANNEL_0_PIN (SL_PWM_CHANNEL0_TMR_EXT_TRIG_1_PIN + 64) #else #define SL_PWM_CHANNEL_0_PIN SL_PWM_CHANNEL0_TMR_EXT_TRIG_1_PIN #endif +#else +#define SL_PWM_CHANNEL_0_PORT SL_SI91X_PWM_TMR_EXT_TRIG_1_PORT +#define SL_PWM_CHANNEL_0_PIN SL_SI91X_PWM_TMR_EXT_TRIG_1_PIN +#endif //SL_PWM_CHANNEL0_EXTTRIG1_LOC #define SL_PWM_CHANNEL_0_MUX SL_SI91X_PWM_TMR_EXT_TRIG_1_MUX #define SL_PWM_CHANNEL_0_PAD SL_SI91X_PWM_TMR_EXT_TRIG_1_PAD #endif #if (SL_PWM_CHANNEL_0_EVENT == 4) +#ifdef SL_PWM_CHANNEL0_EXTTRIG2_LOC #define SL_PWM_CHANNEL_0_PORT SL_PWM_CHANNEL0_TMR_EXT_TRIG_2_PORT -#if (SL_PWM_CHANNEL0_TMR_EXT_TRIG_2_LOC == 2) +#if ((SL_PWM_CHANNEL0_TMR_EXT_TRIG_2_LOC == 28) || (SL_PWM_CHANNEL0_TMR_EXT_TRIG_2_LOC == 29)) #define SL_PWM_CHANNEL_0_PIN (SL_PWM_CHANNEL0_TMR_EXT_TRIG_2_PIN + 64) #else #define SL_PWM_CHANNEL_0_PIN SL_PWM_CHANNEL0_TMR_EXT_TRIG_2_PIN #endif +#else +#define SL_PWM_CHANNEL_0_PORT SL_SI91X_PWM_TMR_EXT_TRIG_2_PORT +#define SL_PWM_CHANNEL_0_PIN SL_SI91X_PWM_TMR_EXT_TRIG_2_PIN +#endif //SL_PWM_CHANNEL0_EXTTRIG2_LOC #define SL_PWM_CHANNEL_0_MUX SL_SI91X_PWM_TMR_EXT_TRIG_2_MUX #define SL_PWM_CHANNEL_0_PAD SL_SI91X_PWM_TMR_EXT_TRIG_2_PAD #endif @@ -234,4 +285,4 @@ extern "C" { } #endif -#endif /* SL_SI91X_PWM_CHANNEL_0_CONFIG_H */ \ No newline at end of file +#endif /* SL_SI91X_PWM_CHANNEL_0_CONFIG_H */ diff --git a/components/board/silabs/config/common_config/sl_si91x_pwm_init_channel_1_config.h b/components/board/silabs/config/common_config/sl_si91x_pwm_init_channel_1_config.h index 39bf0eeee..ddf094130 100644 --- a/components/board/silabs/config/common_config/sl_si91x_pwm_init_channel_1_config.h +++ b/components/board/silabs/config/common_config/sl_si91x_pwm_init_channel_1_config.h @@ -38,7 +38,6 @@ extern "C" { /******************************************************************************/ /******************************* PWM Configuration **************************/ // PWM CHANNEL_1 Configuration - // Frequency <500-200000> // Default: 25000 #define SL_PWM_CHANNEL_1_FREQUENCY 25000 @@ -90,34 +89,45 @@ extern "C" { // End PWM CHANNEL_1 Configuration /******************************************************************************/ // <<< end of configuration section >>> - // <<< sl:start pin_tool >>> -// SL_PWM_CHANNEL1 -// $[PWM_SL_PWM_CHANNEL1] -#ifndef SL_PWM_CHANNEL1_PERIPHERAL -#define SL_PWM_CHANNEL1_PERIPHERAL PWM +// SL_PWM_OUT_CHANNEL1 +// $[PWM_CH1_SL_PWM_OUT_CHANNEL1] +#ifndef SL_PWM_OUT_CHANNEL1_PERIPHERAL +#define SL_PWM_OUT_CHANNEL1_PERIPHERAL PWM_CH1 +#endif +#ifndef SL_PWM_OUT_CHANNEL1_PERIPHERAL_NO +#define SL_PWM_OUT_CHANNEL1_PERIPHERAL_NO 1 #endif -// PWM 2H on GPIO_9 -#ifndef SL_PWM_CHANNEL1_2H_PORT -#define SL_PWM_CHANNEL1_2H_PORT 0 +// PWM_CH1 1H on GPIO_9 +#ifndef SL_PWM_OUT_CHANNEL1_1H_PORT +#define SL_PWM_OUT_CHANNEL1_1H_PORT 0 #endif -#ifndef SL_PWM_CHANNEL1_2H_PIN -#define SL_PWM_CHANNEL1_2H_PIN 9 +#ifndef SL_PWM_OUT_CHANNEL1_1H_PIN +#define SL_PWM_OUT_CHANNEL1_1H_PIN 9 #endif -#ifndef SL_PWM_CHANNEL1_2H_LOC -#define SL_PWM_CHANNEL1_2H_LOC 4 +#ifndef SL_PWM_OUT_CHANNEL1_1H_LOC +#define SL_PWM_OUT_CHANNEL1_1H_LOC 4 #endif -// PWM 2L on GPIO_8 -#ifndef SL_PWM_CHANNEL1_2L_PORT -#define SL_PWM_CHANNEL1_2L_PORT 0 +// PWM_CH1 1L on GPIO_8 +#ifndef SL_PWM_OUT_CHANNEL1_1L_PORT +#define SL_PWM_OUT_CHANNEL1_1L_PORT 0 #endif -#ifndef SL_PWM_CHANNEL1_2L_PIN -#define SL_PWM_CHANNEL1_2L_PIN 8 +#ifndef SL_PWM_OUT_CHANNEL1_1L_PIN +#define SL_PWM_OUT_CHANNEL1_1L_PIN 8 #endif -#ifndef SL_PWM_CHANNEL1_2L_LOC -#define SL_PWM_CHANNEL1_2L_LOC 6 +#ifndef SL_PWM_OUT_CHANNEL1_1L_LOC +#define SL_PWM_OUT_CHANNEL1_1L_LOC 6 +#endif +// [PWM_CH1_SL_PWM_OUT_CHANNEL1]$ +// <<< sl:end pin_tool >>> + +// <<< sl:start pin_tool >>> +// SL_PWM_CHANNEL1 +// $[PWM_SL_PWM_CHANNEL1] +#ifndef SL_PWM_CHANNEL1_PERIPHERAL +#define SL_PWM_CHANNEL1_PERIPHERAL PWM #endif // PWM FAULTA on GPIO_25 @@ -149,8 +159,8 @@ extern "C" { #ifndef SL_PWM_CHANNEL1_TMR_EXT_TRIG_1_PIN #define SL_PWM_CHANNEL1_TMR_EXT_TRIG_1_PIN 27 #endif -#ifndef SL_PWM_CHANNEL1_TMR_EXT_TRIG_1_LOC -#define SL_PWM_CHANNEL1_TMR_EXT_TRIG_1_LOC 22 +#ifndef SL_PWM_CHANNEL1_EXTTRIG1_LOC +#define SL_PWM_CHANNEL1_EXTTRIG1_LOC 22 #endif // PWM TMR_EXT_TRIG_2 on GPIO_28 @@ -160,8 +170,8 @@ extern "C" { #ifndef SL_PWM_CHANNEL1_TMR_EXT_TRIG_2_PIN #define SL_PWM_CHANNEL1_TMR_EXT_TRIG_2_PIN 28 #endif -#ifndef SL_PWM_CHANNEL1_TMR_EXT_TRIG_2_LOC -#define SL_PWM_CHANNEL1_TMR_EXT_TRIG_2_LOC 26 +#ifndef SL_PWM_CHANNEL1_EXTTRIG2_LOC +#define SL_PWM_CHANNEL1_EXTTRIG2_LOC 26 #endif // [PWM_SL_PWM_CHANNEL1]$ // <<< sl:end pin_tool >>> @@ -169,71 +179,105 @@ extern "C" { // PWM channel number for CHANNEL_1 instance #define SL_PWM_CHANNEL_1_OUTPUT_CHANNEL 1 +#ifdef SL_PWM_OUT_CHANNEL1_1L_LOC // Pin set for CHANNEL_1 PWM channel -#if (SL_PWM_CHANNEL1_2L_LOC == 1) -#define SL_PWM_CHANNEL_1_PIN_L (SL_PWM_CHANNEL1_2L_PIN + 64) +#if (SL_PWM_OUT_CHANNEL1_1L_LOC == 6) +#define SL_PWM_CHANNEL_1_PIN_L SL_PWM_OUT_CHANNEL1_1L_PIN #else -#define SL_PWM_CHANNEL_1_PIN_L SL_PWM_CHANNEL1_2L_PIN +#define SL_PWM_CHANNEL_1_PIN_L (SL_PWM_OUT_CHANNEL1_1L_PIN + 64) #endif -#if (SL_PWM_CHANNEL1_2H_LOC == 1) -#define SL_PWM_CHANNEL_1_PIN_H (SL_PWM_CHANNEL1_2H_PIN + 64) +#define SL_PWM_CHANNEL_1_PORT_L SL_PWM_OUT_CHANNEL1_1L_PORT +#else +#define SL_PWM_CHANNEL_1_PIN_L SL_SI91X_PWM_1L_PIN +#define SL_PWM_CHANNEL_1_PORT_L SL_SI91X_PWM_1L_PORT +#endif //SL_PWM_OUT_CHANNEL1_1L_LOC +#ifdef SL_PWM_OUT_CHANNEL1_1H_LOC +#if (SL_PWM_OUT_CHANNEL1_1H_LOC == 5) +#define SL_PWM_CHANNEL_1_PIN_H (SL_PWM_OUT_CHANNEL1_1H_PIN + 64) #else -#define SL_PWM_CHANNEL_1_PIN_H SL_PWM_CHANNEL1_2H_PIN +#define SL_PWM_CHANNEL_1_PIN_H SL_PWM_OUT_CHANNEL1_1H_PIN #endif +#define SL_PWM_CHANNEL_1_PORT_H SL_PWM_OUT_CHANNEL1_1H_PORT +#else +#define SL_PWM_CHANNEL_1_PIN_H SL_SI91X_PWM_1H_PIN +#define SL_PWM_CHANNEL_1_PORT_H SL_SI91X_PWM_1H_PORT +#endif //SL_PWM_OUT_CHANNEL1_1H_LOC -#define SL_PWM_CHANNEL_1_PORT_L SL_PWM_CHANNEL1_2L_PORT -#define SL_PWM_CHANNEL_1_PORT_H SL_PWM_CHANNEL1_2H_PORT - -#define SL_PWM_CHANNEL_1_MUX_L SL_SI91X_PWM_2L_MUX -#define SL_PWM_CHANNEL_1_MUX_H SL_SI91X_PWM_2H_MUX +#define SL_PWM_CHANNEL_1_MUX_L SL_SI91X_PWM_1L_MUX +#define SL_PWM_CHANNEL_1_MUX_H SL_SI91X_PWM_1H_MUX -#define SL_PWM_CHANNEL_1_PAD_L SL_SI91X_PWM_2L_PAD -#define SL_PWM_CHANNEL_1_PAD_H SL_SI91X_PWM_2H_PAD +#define SL_PWM_CHANNEL_1_PAD_L SL_SI91X_PWM_1L_PAD +#define SL_PWM_CHANNEL_1_PAD_H SL_SI91X_PWM_1H_PAD // PWM Fault Pin set resolution #if (SL_PWM_CHANNEL_1_EVENT == 0) +#ifdef SL_PWM_CHANNEL1_FAULTA_LOC #define SL_PWM_CHANNEL_1_PORT SL_PWM_CHANNEL1_FAULTA_PORT #define SL_PWM_CHANNEL_1_PIN SL_PWM_CHANNEL1_FAULTA_PIN -#define SL_PWM_CHANNEL_1_MUX 0 -#define SL_PWM_CHANNEL_1_PAD SL_SI91X_PWM_FAULTA_PAD +#else +#define SL_PWM_CHANNEL_1_PORT SL_SI91X_PWM_FAULTA_PORT +#define SL_PWM_CHANNEL_1_PIN SL_SI91X_PWM_FAULTA_PIN +#endif //SL_PWM_CHANNEL1_FAULTA_LOC +#define SL_PWM_CHANNEL_1_MUX 0 +#define SL_PWM_CHANNEL_1_PAD SL_SI91X_PWM_FAULTA_PAD #endif #if (SL_PWM_CHANNEL_1_EVENT == 1) +#ifdef SL_PWM_CHANNEL1_FAULTA_LOC #define SL_PWM_CHANNEL_1_PORT SL_PWM_CHANNEL1_FAULTA_PORT #define SL_PWM_CHANNEL_1_PIN SL_PWM_CHANNEL1_FAULTA_PIN -#define SL_PWM_CHANNEL_1_MUX SL_SI91X_PWM_FAULTA_MUX -#define SL_PWM_CHANNEL_1_PAD SL_SI91X_PWM_FAULTA_PAD +#else +#define SL_PWM_CHANNEL_1_PORT SL_SI91X_PWM_FAULTA_PORT +#define SL_PWM_CHANNEL_1_PIN SL_SI91X_PWM_FAULTA_PIN +#endif //SL_PWM_CHANNEL1_FAULTA_LOC +#define SL_PWM_CHANNEL_1_MUX SL_SI91X_PWM_FAULTA_MUX +#define SL_PWM_CHANNEL_1_PAD SL_SI91X_PWM_FAULTA_PAD #endif #if (SL_PWM_CHANNEL_1_EVENT == 2) +#ifdef SL_PWM_CHANNEL1_FAULTB_LOC #define SL_PWM_CHANNEL_1_PORT SL_PWM_CHANNEL1_FAULTB_PORT -#if (SL_PWM_CHANNEL1_FAULTB_LOC == 0) +#if (SL_PWM_CHANNEL1_FAULTB_LOC == 19) #define SL_PWM_CHANNEL_1_PIN SL_PWM_CHANNEL1_FAULTB_PIN #else #define SL_PWM_CHANNEL_1_PIN (SL_PWM_CHANNEL1_FAULTB_PIN + 64) #endif +#else +#define SL_PWM_CHANNEL_1_PORT SL_SI91X_PWM_FAULTB_PORT +#define SL_PWM_CHANNEL_1_PIN SL_SI91X_PWM_FAULTB_PIN +#endif //SL_PWM_CHANNEL1_FAULTB_LOC #define SL_PWM_CHANNEL_1_MUX SL_SI91X_PWM_FAULTB_MUX #define SL_PWM_CHANNEL_1_PAD SL_SI91X_PWM_FAULTB_PAD #endif #if (SL_PWM_CHANNEL_1_EVENT == 3) +#ifdef SL_PWM_CHANNEL1_EXTTRIG1_LOC #define SL_PWM_CHANNEL_1_PORT SL_PWM_CHANNEL1_TMR_EXT_TRIG_1_PORT -#if ((SL_PWM_CHANNEL1_TMR_EXT_TRIG_1_LOC == 2) || (SL_PWM_CHANNEL1_TMR_EXT_TRIG_1_LOC == 3)) +#if ((SL_PWM_CHANNEL1_TMR_EXT_TRIG_1_LOC == 24) || (SL_PWM_CHANNEL1_TMR_EXT_TRIG_1_LOC == 25)) #define SL_PWM_CHANNEL_1_PIN (SL_PWM_CHANNEL1_TMR_EXT_TRIG_1_PIN + 64) #else #define SL_PWM_CHANNEL_1_PIN SL_PWM_CHANNEL1_TMR_EXT_TRIG_1_PIN #endif +#else +#define SL_PWM_CHANNEL_1_PORT SL_SI91X_PWM_TMR_EXT_TRIG_1_PORT +#define SL_PWM_CHANNEL_1_PIN SL_SI91X_PWM_TMR_EXT_TRIG_1_PIN +#endif //SL_PWM_CHANNEL1_EXTTRIG1_LOC #define SL_PWM_CHANNEL_1_MUX SL_SI91X_PWM_TMR_EXT_TRIG_1_MUX #define SL_PWM_CHANNEL_1_PAD SL_SI91X_PWM_TMR_EXT_TRIG_1_PAD #endif #if (SL_PWM_CHANNEL_1_EVENT == 4) +#ifdef SL_PWM_CHANNEL1_EXTTRIG2_LOC #define SL_PWM_CHANNEL_1_PORT SL_PWM_CHANNEL1_TMR_EXT_TRIG_2_PORT -#if (SL_PWM_CHANNEL1_TMR_EXT_TRIG_2_LOC == 2) +#if ((SL_PWM_CHANNEL0_TMR_EXT_TRIG_2_LOC == 28) || (SL_PWM_CHANNEL0_TMR_EXT_TRIG_2_LOC == 29)) #define SL_PWM_CHANNEL_1_PIN (SL_PWM_CHANNEL1_TMR_EXT_TRIG_2_PIN + 64) #else #define SL_PWM_CHANNEL_1_PIN SL_PWM_CHANNEL1_TMR_EXT_TRIG_2_PIN #endif +#else +#define SL_PWM_CHANNEL_1_PORT SL_SI91X_PWM_TMR_EXT_TRIG_2_PORT +#define SL_PWM_CHANNEL_1_PIN SL_SI91X_PWM_TMR_EXT_TRIG_2_PIN +#endif //SL_PWM_CHANNEL1_EXTTRIG2_LOC #define SL_PWM_CHANNEL_1_MUX SL_SI91X_PWM_TMR_EXT_TRIG_2_MUX #define SL_PWM_CHANNEL_1_PAD SL_SI91X_PWM_TMR_EXT_TRIG_2_PAD #endif @@ -242,4 +286,4 @@ extern "C" { } #endif -#endif /* SL_SI91X_PWM_CHANNEL_1_CONFIG_H */ \ No newline at end of file +#endif /* SL_SI91X_PWM_CHANNEL_1_CONFIG_H */ diff --git a/components/board/silabs/config/common_config/sl_si91x_pwm_init_channel_2_config.h b/components/board/silabs/config/common_config/sl_si91x_pwm_init_channel_2_config.h index 066b768ae..d57832f0b 100644 --- a/components/board/silabs/config/common_config/sl_si91x_pwm_init_channel_2_config.h +++ b/components/board/silabs/config/common_config/sl_si91x_pwm_init_channel_2_config.h @@ -38,7 +38,6 @@ extern "C" { /******************************************************************************/ /******************************* PWM Configuration **************************/ // PWM CHANNEL_2 Configuration - // Frequency <500-200000> // Default: 25000 #define SL_PWM_CHANNEL_2_FREQUENCY 25000 @@ -90,34 +89,45 @@ extern "C" { // End PWM CHANNEL_2 Configuration /******************************************************************************/ // <<< end of configuration section >>> - // <<< sl:start pin_tool >>> -// SL_PWM_CHANNEL2 -// $[PWM_SL_PWM_CHANNEL2] -#ifndef SL_PWM_CHANNEL2_PERIPHERAL -#define SL_PWM_CHANNEL2_PERIPHERAL PWM +// SL_PWM_OUT_CHANNEL2 +// $[PWM_CH2_SL_PWM_OUT_CHANNEL2] +#ifndef SL_PWM_OUT_CHANNEL2_PERIPHERAL +#define SL_PWM_OUT_CHANNEL2_PERIPHERAL PWM_CH2 +#endif +#ifndef SL_PWM_OUT_CHANNEL2_PERIPHERAL_NO +#define SL_PWM_OUT_CHANNEL2_PERIPHERAL_NO 2 #endif -// PWM 3H on GPIO_11 -#ifndef SL_PWM_CHANNEL2_3H_PORT -#define SL_PWM_CHANNEL2_3H_PORT 0 +// PWM_CH2 2H on GPIO_11 +#ifndef SL_PWM_OUT_CHANNEL2_2H_PORT +#define SL_PWM_OUT_CHANNEL2_2H_PORT 0 #endif -#ifndef SL_PWM_CHANNEL2_3H_PIN -#define SL_PWM_CHANNEL2_3H_PIN 11 +#ifndef SL_PWM_OUT_CHANNEL2_2H_PIN +#define SL_PWM_OUT_CHANNEL2_2H_PIN 11 #endif -#ifndef SL_PWM_CHANNEL2_3H_LOC -#define SL_PWM_CHANNEL2_3H_LOC 9 +#ifndef SL_PWM_OUT_CHANNEL2_2H_LOC +#define SL_PWM_OUT_CHANNEL2_2H_LOC 9 #endif -// PWM 3L on GPIO_10 -#ifndef SL_PWM_CHANNEL2_3L_PORT -#define SL_PWM_CHANNEL2_3L_PORT 0 +// PWM_CH2 2L on GPIO_10 +#ifndef SL_PWM_OUT_CHANNEL2_2L_PORT +#define SL_PWM_OUT_CHANNEL2_2L_PORT 0 +#endif +#ifndef SL_PWM_OUT_CHANNEL2_2L_PIN +#define SL_PWM_OUT_CHANNEL2_2L_PIN 10 #endif -#ifndef SL_PWM_CHANNEL2_3L_PIN -#define SL_PWM_CHANNEL2_3L_PIN 10 +#ifndef SL_PWM_OUT_CHANNEL2_2L_LOC +#define SL_PWM_OUT_CHANNEL2_2L_LOC 11 #endif -#ifndef SL_PWM_CHANNEL2_3L_LOC -#define SL_PWM_CHANNEL2_3L_LOC 11 +// [PWM_CH2_SL_PWM_OUT_CHANNEL2]$ +// <<< sl:end pin_tool >>> + +// <<< sl:start pin_tool >>> +// SL_PWM_CHANNEL2 +// $[PWM_SL_PWM_CHANNEL2] +#ifndef SL_PWM_CHANNEL2_PERIPHERAL +#define SL_PWM_CHANNEL2_PERIPHERAL PWM #endif // PWM FAULTA on GPIO_25 @@ -149,8 +159,8 @@ extern "C" { #ifndef SL_PWM_CHANNEL2_TMR_EXT_TRIG_1_PIN #define SL_PWM_CHANNEL2_TMR_EXT_TRIG_1_PIN 27 #endif -#ifndef SL_PWM_CHANNEL2_TMR_EXT_TRIG_1_LOC -#define SL_PWM_CHANNEL2_TMR_EXT_TRIG_1_LOC 22 +#ifndef SL_PWM_CHANNEL2_EXTTRIG1_LOC +#define SL_PWM_CHANNEL2_EXTTRIG1_LOC 22 #endif // PWM TMR_EXT_TRIG_2 on GPIO_28 @@ -160,8 +170,8 @@ extern "C" { #ifndef SL_PWM_CHANNEL2_TMR_EXT_TRIG_2_PIN #define SL_PWM_CHANNEL2_TMR_EXT_TRIG_2_PIN 28 #endif -#ifndef SL_PWM_CHANNEL2_TMR_EXT_TRIG_2_LOC -#define SL_PWM_CHANNEL2_TMR_EXT_TRIG_2_LOC 26 +#ifndef SL_PWM_CHANNEL2_EXTTRIG2_LOC +#define SL_PWM_CHANNEL2_EXTTRIG2_LOC 26 #endif // [PWM_SL_PWM_CHANNEL2]$ // <<< sl:end pin_tool >>> @@ -169,63 +179,105 @@ extern "C" { // PWM channel number for CHANNEL_2 instance #define SL_PWM_CHANNEL_2_OUTPUT_CHANNEL 2 +#ifdef SL_PWM_OUT_CHANNEL2_2L_LOC // Pin set for CHANNEL_2 PWM channel -#define SL_PWM_CHANNEL_2_PIN_L SL_PWM_CHANNEL2_3L_PIN -#define SL_PWM_CHANNEL_2_PIN_H SL_PWM_CHANNEL2_3H_PIN - -#define SL_PWM_CHANNEL_2_PORT_L SL_PWM_CHANNEL2_3L_PORT -#define SL_PWM_CHANNEL_2_PORT_H SL_PWM_CHANNEL2_3H_PORT +#if (SL_PWM_OUT_CHANNEL2_2L_LOC == 11) +#define SL_PWM_CHANNEL_2_PIN_L SL_PWM_OUT_CHANNEL2_2L_PIN +#else +#define SL_PWM_CHANNEL_2_PIN_L (SL_PWM_OUT_CHANNEL2_2L_PIN + 64) +#endif +#define SL_PWM_CHANNEL_2_PORT_L SL_PWM_OUT_CHANNEL2_2L_PORT +#else +#define SL_PWM_CHANNEL_2_PIN_L SL_SI91X_PWM_2L_PIN +#define SL_PWM_CHANNEL_2_PORT_L SL_SI91X_PWM_2L_PORT +#endif //SL_PWM_OUT_CHANNEL2_2L_LOC +#ifdef SL_PWM_OUT_CHANNEL2_2H_LOC +#if (SL_PWM_OUT_CHANNEL2_2H_LOC == 9) +#define SL_PWM_CHANNEL_2_PIN_H SL_PWM_OUT_CHANNEL2_2H_PIN +#else +#define SL_PWM_CHANNEL_2_PIN_H (SL_PWM_OUT_CHANNEL2_2H_PIN + 64) +#endif +#define SL_PWM_CHANNEL_2_PORT_H SL_PWM_OUT_CHANNEL2_2H_PORT +#else +#define SL_PWM_CHANNEL_2_PIN_H SL_SI91X_PWM_2H_PIN +#define SL_PWM_CHANNEL_2_PORT_H SL_SI91X_PWM_2H_PORT +#endif //SL_PWM_OUT_CHANNEL2_2H_LOC -#define SL_PWM_CHANNEL_2_MUX_L SL_SI91X_PWM_3L_MUX -#define SL_PWM_CHANNEL_2_MUX_H SL_SI91X_PWM_3H_MUX +#define SL_PWM_CHANNEL_2_MUX_L SL_SI91X_PWM_2L_MUX +#define SL_PWM_CHANNEL_2_MUX_H SL_SI91X_PWM_2H_MUX -#define SL_PWM_CHANNEL_2_PAD_L SL_SI91X_PWM_3L_PAD -#define SL_PWM_CHANNEL_2_PAD_H SL_SI91X_PWM_3H_PAD +#define SL_PWM_CHANNEL_2_PAD_L SL_SI91X_PWM_2L_PAD +#define SL_PWM_CHANNEL_2_PAD_H SL_SI91X_PWM_2H_PAD // PWM Fault Pin set resolution #if (SL_PWM_CHANNEL_2_EVENT == 0) +#ifdef SL_PWM_CHANNEL2_FAULTA_LOC #define SL_PWM_CHANNEL_2_PORT SL_PWM_CHANNEL2_FAULTA_PORT #define SL_PWM_CHANNEL_2_PIN SL_PWM_CHANNEL2_FAULTA_PIN -#define SL_PWM_CHANNEL_2_MUX 0 -#define SL_PWM_CHANNEL_2_PAD SL_SI91X_PWM_FAULTA_PAD +#else +#define SL_PWM_CHANNEL_2_PORT SL_SI91X_PWM_FAULTA_PORT +#define SL_PWM_CHANNEL_2_PIN SL_SI91X_PWM_FAULTA_PIN +#endif //SL_PWM_CHANNEL2_FAULTA_LOC +#define SL_PWM_CHANNEL_2_MUX 0 +#define SL_PWM_CHANNEL_2_PAD SL_SI91X_PWM_FAULTA_PAD #endif #if (SL_PWM_CHANNEL_2_EVENT == 1) +#ifdef SL_PWM_CHANNEL2_FAULTA_LOC #define SL_PWM_CHANNEL_2_PORT SL_PWM_CHANNEL2_FAULTA_PORT #define SL_PWM_CHANNEL_2_PIN SL_PWM_CHANNEL2_FAULTA_PIN -#define SL_PWM_CHANNEL_2_MUX SL_SI91X_PWM_FAULTA_MUX -#define SL_PWM_CHANNEL_2_PAD SL_SI91X_PWM_FAULTA_PAD +#else +#define SL_PWM_CHANNEL_2_PORT SL_SI91X_PWM_FAULTA_PORT +#define SL_PWM_CHANNEL_2_PIN SL_SI91X_PWM_FAULTA_PIN +#endif //SL_PWM_CHANNEL2_FAULTA_LOC +#define SL_PWM_CHANNEL_2_MUX SL_SI91X_PWM_FAULTA_MUX +#define SL_PWM_CHANNEL_2_PAD SL_SI91X_PWM_FAULTA_PAD #endif #if (SL_PWM_CHANNEL_2_EVENT == 2) +#ifdef SL_PWM_CHANNEL2_FAULTB_LOC #define SL_PWM_CHANNEL_2_PORT SL_PWM_CHANNEL2_FAULTB_PORT -#if (SL_PWM_CHANNEL2_FAULTB_LOC == 0) +#if (SL_PWM_CHANNEL2_FAULTB_LOC == 19) #define SL_PWM_CHANNEL_2_PIN SL_PWM_CHANNEL2_FAULTB_PIN #else #define SL_PWM_CHANNEL_2_PIN (SL_PWM_CHANNEL2_FAULTB_PIN + 64) #endif +#else +#define SL_PWM_CHANNEL_2_PORT SL_SI91X_PWM_FAULTB_PORT +#define SL_PWM_CHANNEL_2_PIN SL_SI91X_PWM_FAULTB_PIN +#endif //SL_PWM_CHANNEL2_FAULTB_LOC #define SL_PWM_CHANNEL_2_MUX SL_SI91X_PWM_FAULTB_MUX #define SL_PWM_CHANNEL_2_PAD SL_SI91X_PWM_FAULTB_PAD #endif #if (SL_PWM_CHANNEL_2_EVENT == 3) +#ifdef SL_PWM_CHANNEL2_EXTTRIG1_LOC #define SL_PWM_CHANNEL_2_PORT SL_PWM_CHANNEL2_TMR_EXT_TRIG_1_PORT -#if ((SL_PWM_CHANNEL2_TMR_EXT_TRIG_1_LOC == 2) || (SL_PWM_CHANNEL2_TMR_EXT_TRIG_1_LOC == 3)) +#if ((SL_PWM_CHANNEL2_TMR_EXT_TRIG_1_LOC == 24) || (SL_PWM_CHANNEL2_TMR_EXT_TRIG_1_LOC == 25)) #define SL_PWM_CHANNEL_2_PIN (SL_PWM_CHANNEL2_TMR_EXT_TRIG_1_PIN + 64) #else #define SL_PWM_CHANNEL_2_PIN SL_PWM_CHANNEL2_TMR_EXT_TRIG_1_PIN #endif +#else +#define SL_PWM_CHANNEL_2_PORT SL_SI91X_PWM_TMR_EXT_TRIG_1_PORT +#define SL_PWM_CHANNEL_2_PIN SL_SI91X_PWM_TMR_EXT_TRIG_1_PIN +#endif //SL_PWM_CHANNEL2_EXTTRIG1_LOC #define SL_PWM_CHANNEL_2_MUX SL_SI91X_PWM_TMR_EXT_TRIG_1_MUX #define SL_PWM_CHANNEL_2_PAD SL_SI91X_PWM_TMR_EXT_TRIG_1_PAD #endif #if (SL_PWM_CHANNEL_2_EVENT == 4) +#ifdef SL_PWM_CHANNEL2_EXTTRIG2_LOC #define SL_PWM_CHANNEL_2_PORT SL_PWM_CHANNEL2_TMR_EXT_TRIG_2_PORT -#if (SL_PWM_CHANNEL2_TMR_EXT_TRIG_2_LOC == 2) +#if ((SL_PWM_CHANNEL0_TMR_EXT_TRIG_2_LOC == 28) || (SL_PWM_CHANNEL0_TMR_EXT_TRIG_2_LOC == 29)) #define SL_PWM_CHANNEL_2_PIN (SL_PWM_CHANNEL2_TMR_EXT_TRIG_2_PIN + 64) #else #define SL_PWM_CHANNEL_2_PIN SL_PWM_CHANNEL2_TMR_EXT_TRIG_2_PIN #endif +#else +#define SL_PWM_CHANNEL_2_PORT SL_SI91X_PWM_TMR_EXT_TRIG_2_PORT +#define SL_PWM_CHANNEL_2_PIN SL_SI91X_PWM_TMR_EXT_TRIG_2_PIN +#endif //SL_PWM_CHANNEL2_EXTTRIG2_LOC #define SL_PWM_CHANNEL_2_MUX SL_SI91X_PWM_TMR_EXT_TRIG_2_MUX #define SL_PWM_CHANNEL_2_PAD SL_SI91X_PWM_TMR_EXT_TRIG_2_PAD #endif @@ -234,4 +286,4 @@ extern "C" { } #endif -#endif /* SL_SI91X_PWM_CHANNEL_2_CONFIG_H */ \ No newline at end of file +#endif /* SL_SI91X_PWM_CHANNEL_2_CONFIG_H */ diff --git a/components/board/silabs/config/common_config/sl_si91x_pwm_init_channel_3_config.h b/components/board/silabs/config/common_config/sl_si91x_pwm_init_channel_3_config.h index 22367a957..98ca6c820 100644 --- a/components/board/silabs/config/common_config/sl_si91x_pwm_init_channel_3_config.h +++ b/components/board/silabs/config/common_config/sl_si91x_pwm_init_channel_3_config.h @@ -38,7 +38,6 @@ extern "C" { /******************************************************************************/ /******************************* PWM Configuration **************************/ // PWM CHANNEL_3 Configuration - // Frequency <500-200000> // Default: 25000 #define SL_PWM_CHANNEL_3_FREQUENCY 25000 @@ -90,34 +89,45 @@ extern "C" { // End PWM CHANNEL_3 Configuration /******************************************************************************/ // <<< end of configuration section >>> - // <<< sl:start pin_tool >>> -// SL_PWM_CHANNEL3 -// $[PWM_SL_PWM_CHANNEL3] -#ifndef SL_PWM_CHANNEL3_PERIPHERAL -#define SL_PWM_CHANNEL3_PERIPHERAL PWM +// SL_PWM_OUT_CHANNEL3 +// $[PWM_CH3_SL_PWM_OUT_CHANNEL3] +#ifndef SL_PWM_OUT_CHANNEL3_PERIPHERAL +#define SL_PWM_OUT_CHANNEL3_PERIPHERAL PWM_CH3 +#endif +#ifndef SL_PWM_OUT_CHANNEL3_PERIPHERAL_NO +#define SL_PWM_OUT_CHANNEL3_PERIPHERAL_NO 3 #endif -// PWM 4H on ULP_GPIO_7/GPIO_71 -#ifndef SL_PWM_CHANNEL3_4H_PORT -#define SL_PWM_CHANNEL3_4H_PORT 0 +// PWM_CH3 3H on GPIO_15 +#ifndef SL_PWM_OUT_CHANNEL3_3H_PORT +#define SL_PWM_OUT_CHANNEL3_3H_PORT 0 #endif -#ifndef SL_PWM_CHANNEL3_4H_PIN -#define SL_PWM_CHANNEL3_4H_PIN 7 +#ifndef SL_PWM_OUT_CHANNEL3_3H_PIN +#define SL_PWM_OUT_CHANNEL3_3H_PIN 7 #endif -#ifndef SL_PWM_CHANNEL3_4H_LOC -#define SL_PWM_CHANNEL3_4H_LOC 13 +#ifndef SL_PWM_OUT_CHANNEL3_3H_LOC +#define SL_PWM_OUT_CHANNEL3_3H_LOC 13 #endif -// PWM 4L on ULP_GPIO_6/GPIO_70 -#ifndef SL_PWM_CHANNEL3_4L_PORT -#define SL_PWM_CHANNEL3_4L_PORT 0 +// PWM_CH3 3L on ULP_GPIO_6/GPIO_70 +#ifndef SL_PWM_OUT_CHANNEL3_3L_PORT +#define SL_PWM_OUT_CHANNEL3_3L_PORT 0 #endif -#ifndef SL_PWM_CHANNEL3_4L_PIN -#define SL_PWM_CHANNEL3_4L_PIN 6 +#ifndef SL_PWM_OUT_CHANNEL3_3L_PIN +#define SL_PWM_OUT_CHANNEL3_3L_PIN 6 #endif -#ifndef SL_PWM_CHANNEL3_4L_LOC -#define SL_PWM_CHANNEL3_4L_LOC 15 +#ifndef SL_PWM_OUT_CHANNEL3_3L_LOC +#define SL_PWM_OUT_CHANNEL3_3L_LOC 15 +#endif +// [PWM_CH3_SL_PWM_OUT_CHANNEL3]$ +// <<< sl:end pin_tool >>> + +// <<< sl:start pin_tool >>> +// SL_PWM_CHANNEL3 +// $[PWM_SL_PWM_CHANNEL3] +#ifndef SL_PWM_CHANNEL3_PERIPHERAL +#define SL_PWM_CHANNEL3_PERIPHERAL PWM #endif // PWM FAULTA on GPIO_25 @@ -149,8 +159,8 @@ extern "C" { #ifndef SL_PWM_CHANNEL3_TMR_EXT_TRIG_1_PIN #define SL_PWM_CHANNEL3_TMR_EXT_TRIG_1_PIN 27 #endif -#ifndef SL_PWM_CHANNEL3_TMR_EXT_TRIG_1_LOC -#define SL_PWM_CHANNEL3_TMR_EXT_TRIG_1_LOC 22 +#ifndef SL_PWM_CHANNEL3_EXTTRIG1_LOC +#define SL_PWM_CHANNEL3_EXTTRIG1_LOC 22 #endif // PWM TMR_EXT_TRIG_2 on GPIO_28 @@ -160,8 +170,8 @@ extern "C" { #ifndef SL_PWM_CHANNEL3_TMR_EXT_TRIG_2_PIN #define SL_PWM_CHANNEL3_TMR_EXT_TRIG_2_PIN 28 #endif -#ifndef SL_PWM_CHANNEL3_TMR_EXT_TRIG_2_LOC -#define SL_PWM_CHANNEL3_TMR_EXT_TRIG_2_LOC 26 +#ifndef SL_PWM_CHANNEL3_EXTTRIG2_LOC +#define SL_PWM_CHANNEL3_EXTTRIG2_LOC 26 #endif // [PWM_SL_PWM_CHANNEL3]$ // <<< sl:end pin_tool >>> @@ -170,70 +180,105 @@ extern "C" { #define SL_PWM_CHANNEL_3_OUTPUT_CHANNEL 3 // Pin set for CHANNEL_3 PWM channel -#if (SL_PWM_CHANNEL3_4L_LOC == 15) -#define SL_PWM_CHANNEL_3_PIN_L (SL_PWM_CHANNEL3_4L_PIN + 64) +#ifdef SL_PWM_OUT_CHANNEL3_3L_LOC +#if (SL_PWM_OUT_CHANNEL3_3L_LOC == 15) +#define SL_PWM_CHANNEL_3_PIN_L (SL_PWM_OUT_CHANNEL3_3L_PIN + 64) #else -#define SL_PWM_CHANNEL_3_PIN_L SL_PWM_CHANNEL3_4L_PIN +#define SL_PWM_CHANNEL_3_PIN_L SL_PWM_OUT_CHANNEL3_3L_PIN #endif -#if (SL_PWM_CHANNEL3_4H_LOC == 13) -#define SL_PWM_CHANNEL_3_PIN_H (SL_PWM_CHANNEL3_4H_PIN + 64) +#define SL_PWM_CHANNEL_3_PORT_L SL_PWM_OUT_CHANNEL3_3L_PORT #else -#define SL_PWM_CHANNEL_3_PIN_H SL_PWM_CHANNEL3_4H_PIN -#endif +#define SL_PWM_CHANNEL_3_PIN_L SL_SI91X_PWM_3L_PIN +#define SL_PWM_CHANNEL_3_PORT_L SL_SI91X_PWM_3L_PORT +#endif //SL_PWM_OUT_CHANNEL3_3L_LOC -#define SL_PWM_CHANNEL_3_PORT_L SL_PWM_CHANNEL3_4L_PORT -#define SL_PWM_CHANNEL_3_PORT_H SL_PWM_CHANNEL3_4H_PORT +#ifdef SL_PWM_OUT_CHANNEL3_3L_LOC +#if (SL_PWM_OUT_CHANNEL3_3H_LOC == 13) +#define SL_PWM_CHANNEL_3_PIN_H (SL_PWM_OUT_CHANNEL3_3H_PIN + 64) +#else +#define SL_PWM_CHANNEL_3_PIN_H SL_PWM_OUT_CHANNEL3_3H_PIN +#endif +#define SL_PWM_CHANNEL_3_PORT_H SL_PWM_OUT_CHANNEL3_3H_PORT +#else +#define SL_PWM_CHANNEL_3_PIN_H SL_SI91X_PWM_3H_PIN +#define SL_PWM_CHANNEL_3_PORT_H SL_SI91X_PWM_3H_PORT +#endif //SL_PWM_OUT_CHANNEL3_3L_LOC -#define SL_PWM_CHANNEL_3_MUX_L SL_SI91X_PWM_4L_MUX -#define SL_PWM_CHANNEL_3_MUX_H SL_SI91X_PWM_4H_MUX +#define SL_PWM_CHANNEL_3_MUX_L SL_SI91X_PWM_3L_MUX +#define SL_PWM_CHANNEL_3_MUX_H SL_SI91X_PWM_3H_MUX -#define SL_PWM_CHANNEL_3_PAD_L SL_SI91X_PWM_4L_PAD -#define SL_PWM_CHANNEL_3_PAD_H SL_SI91X_PWM_4H_PAD +#define SL_PWM_CHANNEL_3_PAD_L SL_SI91X_PWM_3L_PAD +#define SL_PWM_CHANNEL_3_PAD_H SL_SI91X_PWM_3H_PAD // PWM Fault Pin set resolution #if (SL_PWM_CHANNEL_3_EVENT == 0) +#ifdef SL_PWM_CHANNEL3_FAULTA_LOC #define SL_PWM_CHANNEL_3_PORT SL_PWM_CHANNEL3_FAULTA_PORT #define SL_PWM_CHANNEL_3_PIN SL_PWM_CHANNEL3_FAULTA_PIN -#define SL_PWM_CHANNEL_3_MUX 0 -#define SL_PWM_CHANNEL_3_PAD SL_SI91X_PWM_FAULTA_PAD +#else +#define SL_PWM_CHANNEL_3_PORT SL_SI91X_PWM_FAULTA_PORT +#define SL_PWM_CHANNEL_3_PIN SL_SI91X_PWM_FAULTA_PIN +#endif //SL_PWM_CHANNEL3_FAULTA_LOC +#define SL_PWM_CHANNEL_3_MUX 0 +#define SL_PWM_CHANNEL_3_PAD SL_SI91X_PWM_FAULTA_PAD #endif #if (SL_PWM_CHANNEL_3_EVENT == 1) +#ifdef SL_PWM_CHANNEL3_FAULTA_LOC #define SL_PWM_CHANNEL_3_PORT SL_PWM_CHANNEL3_FAULTA_PORT #define SL_PWM_CHANNEL_3_PIN SL_PWM_CHANNEL3_FAULTA_PIN -#define SL_PWM_CHANNEL_3_MUX SL_SI91X_PWM_FAULTA_MUX -#define SL_PWM_CHANNEL_3_PAD SL_SI91X_PWM_FAULTA_PAD +#else +#define SL_PWM_CHANNEL_3_PORT SL_SI91X_PWM_FAULTA_PORT +#define SL_PWM_CHANNEL_3_PIN SL_SI91X_PWM_FAULTA_PIN +#endif //SL_PWM_CHANNEL3_FAULTA_LOC +#define SL_PWM_CHANNEL_3_MUX SL_SI91X_PWM_FAULTA_MUX +#define SL_PWM_CHANNEL_3_PAD SL_SI91X_PWM_FAULTA_PAD #endif #if (SL_PWM_CHANNEL_3_EVENT == 2) +#ifdef SL_PWM_CHANNEL3_FAULTB_LOC #define SL_PWM_CHANNEL_3_PORT SL_PWM_CHANNEL3_FAULTB_PORT -#if (SL_PWM_CHANNEL3_FAULTB_LOC == 0) +#if (SL_PWM_CHANNEL3_FAULTB_LOC == 19) #define SL_PWM_CHANNEL_3_PIN SL_PWM_CHANNEL3_FAULTB_PIN #else #define SL_PWM_CHANNEL_3_PIN (SL_PWM_CHANNEL3_FAULTB_PIN + 64) #endif +#else +#define SL_PWM_CHANNEL_3_PORT SL_SI91X_PWM_FAULTB_PORT +#define SL_PWM_CHANNEL_3_PIN SL_SI91X_PWM_FAULTB_PIN +#endif //SL_PWM_CHANNEL3_FAULTB_LOC #define SL_PWM_CHANNEL_3_MUX SL_SI91X_PWM_FAULTB_MUX #define SL_PWM_CHANNEL_3_PAD SL_SI91X_PWM_FAULTB_PAD #endif #if (SL_PWM_CHANNEL_3_EVENT == 3) +#ifdef SL_PWM_CHANNEL3_EXTTRIG1_LOC #define SL_PWM_CHANNEL_3_PORT SL_PWM_CHANNEL3_TMR_EXT_TRIG_1_PORT -#if ((SL_PWM_CHANNEL3_TMR_EXT_TRIG_1_LOC == 2) || (SL_PWM_CHANNEL3_TMR_EXT_TRIG_1_LOC == 3)) +#if ((SL_PWM_CHANNEL3_TMR_EXT_TRIG_1_LOC == 24) || (SL_PWM_CHANNEL3_TMR_EXT_TRIG_1_LOC == 25)) #define SL_PWM_CHANNEL_3_PIN (SL_PWM_CHANNEL3_TMR_EXT_TRIG_1_PIN + 64) #else #define SL_PWM_CHANNEL_3_PIN SL_PWM_CHANNEL3_TMR_EXT_TRIG_1_PIN #endif +#else +#define SL_PWM_CHANNEL_3_PORT SL_SI91X_PWM_TMR_EXT_TRIG_1_PORT +#define SL_PWM_CHANNEL_3_PIN SL_SI91X_PWM_TMR_EXT_TRIG_1_PIN +#endif //SL_PWM_CHANNEL3_EXTTRIG1_LOC #define SL_PWM_CHANNEL_3_MUX SL_SI91X_PWM_TMR_EXT_TRIG_1_MUX #define SL_PWM_CHANNEL_3_PAD SL_SI91X_PWM_TMR_EXT_TRIG_1_PAD #endif #if (SL_PWM_CHANNEL_3_EVENT == 4) +#ifdef SL_PWM_CHANNEL3_EXTTRIG2_LOC #define SL_PWM_CHANNEL_3_PORT SL_PWM_CHANNEL3_TMR_EXT_TRIG_2_PORT -#if (SL_PWM_CHANNEL3_TMR_EXT_TRIG_2_LOC == 2) +#if ((SL_PWM_CHANNEL0_TMR_EXT_TRIG_2_LOC == 28) || (SL_PWM_CHANNEL0_TMR_EXT_TRIG_2_LOC == 29)) #define SL_PWM_CHANNEL_3_PIN (SL_PWM_CHANNEL3_TMR_EXT_TRIG_2_PIN + 64) #else #define SL_PWM_CHANNEL_3_PIN SL_PWM_CHANNEL3_TMR_EXT_TRIG_2_PIN #endif +#else +#define SL_PWM_CHANNEL_3_PORT SL_SI91X_PWM_TMR_EXT_TRIG_2_PORT +#define SL_PWM_CHANNEL_3_PIN SL_SI91X_PWM_TMR_EXT_TRIG_2_PIN +#endif //SL_PWM_CHANNEL3_EXTTRIG2_LOC #define SL_PWM_CHANNEL_3_MUX SL_SI91X_PWM_TMR_EXT_TRIG_2_MUX #define SL_PWM_CHANNEL_3_PAD SL_SI91X_PWM_TMR_EXT_TRIG_2_PAD #endif @@ -242,4 +287,4 @@ extern "C" { } #endif -#endif /* SL_SI91X_PWM_CHANNEL_3_CONFIG_H */ \ No newline at end of file +#endif /* SL_SI91X_PWM_CHANNEL_3_CONFIG_H */ diff --git a/components/board/silabs/inc/sl_pwm_board.h b/components/board/silabs/inc/sl_pwm_board.h index 44fe3e869..e896a8d99 100644 --- a/components/board/silabs/inc/sl_pwm_board.h +++ b/components/board/silabs/inc/sl_pwm_board.h @@ -30,45 +30,45 @@ extern "C" { */ #include "RTE_Device_917.h" -#define SL_SI91X_PWM_1L_PORT RTE_PWM_1L_PORT -#define SL_SI91X_PWM_1L_PIN RTE_PWM_1L_PIN -#define SL_SI91X_PWM_1L_MUX RTE_PWM_1L_MUX -#define SL_SI91X_PWM_1L_PAD RTE_PWM_1L_PAD - -#define SL_SI91X_PWM_1H_PORT RTE_PWM_1H_PORT -#define SL_SI91X_PWM_1H_PIN RTE_PWM_1H_PIN -#define SL_SI91X_PWM_1H_MUX RTE_PWM_1H_MUX -#define SL_SI91X_PWM_1H_PAD RTE_PWM_1H_PAD - -#define SL_SI91X_PWM_2L_PORT RTE_PWM_2L_PORT -#define SL_SI91X_PWM_2L_PIN RTE_PWM_2L_PIN -#define SL_SI91X_PWM_2L_MUX RTE_PWM_2L_MUX -#define SL_SI91X_PWM_2L_PAD RTE_PWM_2L_PAD - -#define SL_SI91X_PWM_2H_PORT RTE_PWM_2H_PORT -#define SL_SI91X_PWM_2H_PIN RTE_PWM_2H_PIN -#define SL_SI91X_PWM_2H_MUX RTE_PWM_2H_MUX -#define SL_SI91X_PWM_2H_PAD RTE_PWM_2H_PAD - -#define SL_SI91X_PWM_3L_PORT RTE_PWM_3L_PORT -#define SL_SI91X_PWM_3L_PIN RTE_PWM_3L_PIN -#define SL_SI91X_PWM_3L_MUX RTE_PWM_3L_MUX -#define SL_SI91X_PWM_3L_PAD RTE_PWM_3L_PAD - -#define SL_SI91X_PWM_3H_PORT RTE_PWM_3H_PORT -#define SL_SI91X_PWM_3H_PIN RTE_PWM_3H_PIN -#define SL_SI91X_PWM_3H_MUX RTE_PWM_3H_MUX -#define SL_SI91X_PWM_3H_PAD RTE_PWM_3H_PAD - -#define SL_SI91X_PWM_4L_PORT RTE_PWM_4L_PORT -#define SL_SI91X_PWM_4L_PIN RTE_PWM_4L_PIN -#define SL_SI91X_PWM_4L_MUX RTE_PWM_4L_MUX -#define SL_SI91X_PWM_4L_PAD RTE_PWM_4L_PAD - -#define SL_SI91X_PWM_4H_PORT RTE_PWM_4H_PORT -#define SL_SI91X_PWM_4H_PIN RTE_PWM_4H_PIN -#define SL_SI91X_PWM_4H_MUX RTE_PWM_4H_MUX -#define SL_SI91X_PWM_4H_PAD RTE_PWM_4H_PAD +#define SL_SI91X_PWM_0L_PORT RTE_PWM_1L_PORT +#define SL_SI91X_PWM_0L_PIN RTE_PWM_1L_PIN +#define SL_SI91X_PWM_0L_MUX RTE_PWM_1L_MUX +#define SL_SI91X_PWM_0L_PAD RTE_PWM_1L_PAD + +#define SL_SI91X_PWM_0H_PORT RTE_PWM_1H_PORT +#define SL_SI91X_PWM_0H_PIN RTE_PWM_1H_PIN +#define SL_SI91X_PWM_0H_MUX RTE_PWM_1H_MUX +#define SL_SI91X_PWM_0H_PAD RTE_PWM_1H_PAD + +#define SL_SI91X_PWM_1L_PORT RTE_PWM_2L_PORT +#define SL_SI91X_PWM_1L_PIN RTE_PWM_2L_PIN +#define SL_SI91X_PWM_1L_MUX RTE_PWM_2L_MUX +#define SL_SI91X_PWM_1L_PAD RTE_PWM_2L_PAD + +#define SL_SI91X_PWM_1H_PORT RTE_PWM_2H_PORT +#define SL_SI91X_PWM_1H_PIN RTE_PWM_2H_PIN +#define SL_SI91X_PWM_1H_MUX RTE_PWM_2H_MUX +#define SL_SI91X_PWM_1H_PAD RTE_PWM_2H_PAD + +#define SL_SI91X_PWM_2L_PORT RTE_PWM_3L_PORT +#define SL_SI91X_PWM_2L_PIN RTE_PWM_3L_PIN +#define SL_SI91X_PWM_2L_MUX RTE_PWM_3L_MUX +#define SL_SI91X_PWM_2L_PAD RTE_PWM_3L_PAD + +#define SL_SI91X_PWM_2H_PORT RTE_PWM_3H_PORT +#define SL_SI91X_PWM_2H_PIN RTE_PWM_3H_PIN +#define SL_SI91X_PWM_2H_MUX RTE_PWM_3H_MUX +#define SL_SI91X_PWM_2H_PAD RTE_PWM_3H_PAD + +#define SL_SI91X_PWM_3L_PORT RTE_PWM_4L_PORT +#define SL_SI91X_PWM_3L_PIN RTE_PWM_4L_PIN +#define SL_SI91X_PWM_3L_MUX RTE_PWM_4L_MUX +#define SL_SI91X_PWM_3L_PAD RTE_PWM_4L_PAD + +#define SL_SI91X_PWM_3H_PORT RTE_PWM_4H_PORT +#define SL_SI91X_PWM_3H_PIN RTE_PWM_4H_PIN +#define SL_SI91X_PWM_3H_MUX RTE_PWM_4H_MUX +#define SL_SI91X_PWM_3H_PAD RTE_PWM_4H_PAD #define SL_SI91X_PWM_FAULTA_PORT RTE_PWM_FAULTA_PORT #define SL_SI91X_PWM_FAULTA_PIN RTE_PWM_FAULTA_PIN diff --git a/components/board/silabs/src/rsi_board.c b/components/board/silabs/src/rsi_board.c index 9e26255cb..54da96a9c 100644 --- a/components/board/silabs/src/rsi_board.c +++ b/components/board/silabs/src/rsi_board.c @@ -48,10 +48,9 @@ static const uint32_t ledBitsCnt = sizeof(ledBits) / sizeof(PORT_PIN_T); */ void RSI_Board_Init(void) { - uint32_t i; #if ((defined(SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER) && (SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER == 1)) \ && (defined(SLI_SI91X_MCU_CONFIG_RADIO_BOARD_VER2) && (SLI_SI91X_MCU_CONFIG_RADIO_BOARD_VER2 == 1))) - for (i = 0; i < ledBitsCnt; i++) { + for (uint32_t i = 0; i < ledBitsCnt; i++) { if (i == 0) { /*Set the GPIO pin MUX */ RSI_EGPIO_SetPinMux(EGPIO1, ledBits[i].port, ledBits[i].pin, 0); diff --git a/components/common/inc/sl_constants.h b/components/common/inc/sl_constants.h index 57e7716c2..5caf0741c 100644 --- a/components/common/inc/sl_constants.h +++ b/components/common/inc/sl_constants.h @@ -18,9 +18,9 @@ #define SL_STATUS_SHARED_ENUM(prefix, name) prefix##_##name = (SL_##name) #ifdef __CC_ARM -#define BREAKPOINT() __asm__("bkpt #0"); +#define BREAKPOINT() __asm__("bkpt #0") #else -#define BREAKPOINT() __asm__("bkpt"); +#define BREAKPOINT() __asm__("bkpt") #endif #define SL_IPV4_ADDRESS_LENGTH 4 @@ -37,13 +37,17 @@ #ifndef FUZZING #define SL_ASSERT(condition, ...) \ - if (!(condition)) { \ - BREAKPOINT(); \ - } + do { \ + if (!(condition)) { \ + BREAKPOINT(); \ + } \ + } while (0) #else #define SL_ASSERT(condition, ...) \ - if (!(condition)) { \ - } + do { \ + if (!(condition)) { \ + } \ + } while (0) #endif #ifndef ROUND_UP @@ -160,8 +164,7 @@ } \ } while (0) -#define PRINT_ERROR_STATUS(tag, status) \ - printf("\r\n%s %s:%d: 0x%x \r\n", tag, __FILE__, __LINE__, (unsigned int)status); +#define PRINT_ERROR_STATUS(tag, status) printf("\r\n%s %s:%d: 0x%x \r\n", tag, __FILE__, __LINE__, (unsigned int)status) #ifdef PRINT_DEBUG_LOG extern void sl_debug_log(const char *format, ...); diff --git a/components/common/inc/sl_utility.h b/components/common/inc/sl_utility.h index 838f6ab1a..fdd0954bd 100644 --- a/components/common/inc/sl_utility.h +++ b/components/common/inc/sl_utility.h @@ -75,12 +75,12 @@ sl_status_t convert_string_to_mac_address(const char *line, sl_mac_address_t *ma void print_sl_ip_address(const sl_ip_address_t *sl_ip_address); void print_sl_ipv4_address(const sl_ipv4_address_t *ip_address); void print_sl_ipv6_address(const sl_ipv6_address_t *ip_address); -void print_mac_address(sl_mac_address_t *mac_address); +void print_mac_address(const sl_mac_address_t *mac_address); void convert_uint32_to_bytestream(uint16_t data, uint8_t *buffer); void little_to_big_endian(const unsigned int *source, unsigned char *result, unsigned int length); int sl_inet_pton6(const char *src, const char *src_endp, unsigned char *dst, unsigned int *ptr_result); void reverse_digits(unsigned char *xx, int no_digits); -void print_firmware_version(sl_wifi_firmware_version_t *firmware_version); +void print_firmware_version(const sl_wifi_firmware_version_t *firmware_version); /***************************************************************************/ /** * @brief Print 802.11 packet @@ -89,4 +89,4 @@ void print_firmware_version(sl_wifi_firmware_version_t *firmware_version); * @param[in] packet_length - total packet length (MAC header + payload) * @param[in] max_payload_length - maximum number of payload bytes to print ******************************************************************************/ -void print_80211_packet(uint8_t *packet, uint32_t packet_length, uint16_t max_payload_length); +void print_80211_packet(const uint8_t *packet, uint32_t packet_length, uint16_t max_payload_length); diff --git a/components/common/src/sl_utility.c b/components/common/src/sl_utility.c index 1f525c74b..c287f250f 100644 --- a/components/common/src/sl_utility.c +++ b/components/common/src/sl_utility.c @@ -86,7 +86,7 @@ void print_sl_ipv6_address(const sl_ipv6_address_t *ip_address) printf("%s\r\n", temp_buffer); } -void print_mac_address(sl_mac_address_t *mac_address) +void print_mac_address(const sl_mac_address_t *mac_address) { if (mac_address == NULL) { return; @@ -105,7 +105,8 @@ char *sl_inet_ntop6(const unsigned char *input, char *dst, uint32_t size) char tmp[sizeof "ffff:ffff:ffff:ffff:ffff:ffff:255.255.255.255"]; char *tp; struct { - int base, len; + int base; + int len; } best, cur; unsigned int words[SL_IPV6_ADDRESS_LENGTH / 2]; int i; @@ -202,7 +203,10 @@ void little_to_big_endian(const unsigned int *source, unsigned char *result, uns int sl_inet_pton6(const char *src, const char *src_endp, unsigned char *dst, unsigned int *ptr_result) { - unsigned char tmp[SL_IPV6_ADDRESS_LENGTH], *tp, *endp, *colonp; + unsigned char tmp[SL_IPV6_ADDRESS_LENGTH]; + unsigned char *tp; + unsigned char *endp; + unsigned char *colonp; const char *curtok __attribute__((__unused__)); int ch; size_t xdigits_seen; /* Number of hex digits since colon. */ @@ -311,16 +315,15 @@ sl_status_t convert_string_to_mac_address(const char *line, sl_mac_address_t *ma void reverse_digits(unsigned char *xx, int no_digits) { - int count; uint8_t temp; - for (count = 0; count < (no_digits / 2); count++) { + for (int count = 0; count < (no_digits / 2); count++) { temp = xx[count]; xx[count] = xx[no_digits - count - 1]; xx[no_digits - count - 1] = temp; } } -void print_firmware_version(sl_wifi_firmware_version_t *firmware_version) +void print_firmware_version(const sl_wifi_firmware_version_t *firmware_version) { printf("\r\nFirmware version is: %x%x.%d.%d.%d.%d.%d.%d\r\n", firmware_version->chip_id, diff --git a/components/console/console.c b/components/console/console.c index 99863bee8..7d60c187c 100644 --- a/components/console/console.c +++ b/components/console/console.c @@ -368,8 +368,7 @@ sl_status_t console_parse_arg(console_argument_type_t type, char *line, uint32_t static inline uint8_t parse_enum_arg(const char *line, const char *const *options) { - uint8_t a; - for (a = 0; options[a] != NULL; ++a) { + for (uint8_t a = 0; options[a] != NULL; ++a) { if (strcmp(line, options[a]) == 0) { return a; } diff --git a/components/console/console.mk b/components/console/console.mk index aaa752342..c955d803e 100644 --- a/components/console/console.mk +++ b/components/console/console.mk @@ -2,14 +2,14 @@ ifndef HOST_OS $(error Must define HOST_OS to "windows", "linux", or "macos") endif -$(PROJECT_OUTPUT)/generated/console_variable_database.c: $(PROJECT_OUTPUT)/generated/console_variable_database.yaml | $(PROJECT_OUTPUT)/generated/.directory - components/yinja/yinja-$(HOST_OS) -t $(console_DIRECTORY)/console_variable_table.c.template -y $(PROJECT_OUTPUT)/generated/console_variable_database.yaml > $@ +$(PROJECT_OUTPUT)/generated/console_variable_database.c: $(PROJECT_OUTPUT)/generated/console_variable_database.yaml | $(PROJECT_OUTPUT)/generated/.directory + components/yinja/yinja-$(HOST_OS) -t $(console_DIRECTORY)/console_variable_table.c.template -t $(console_DIRECTORY)/console_variable_group_processing.template -y $(PROJECT_OUTPUT)/generated/console_variable_database.yaml > $@ $(PROJECT_OUTPUT)/generated/console_variable_database.yaml: | $(PROJECT_OUTPUT)/generated/.directory components/yinja/yinja-$(HOST_OS) -t $(console_DIRECTORY)/console_variable_table.yaml.template -j $(PROJECT_OUTPUT)/yakka_summary.json > $@ $(PROJECT_OUTPUT)/generated/console_command_database.c: $(console_DIRECTORY)/console_command_database.c.template | $(PROJECT_OUTPUT)/generated/.directory - components/yinja/yinja-$(HOST_OS) -t $(console_DIRECTORY)/console_command_database.c.template -j $(PROJECT_OUTPUT)/yakka_summary.json > $@ + components/yinja/yinja-$(HOST_OS) -t $(console_DIRECTORY)/console_command_database.c.template -t $(console_DIRECTORY)/console_command_processing.template -j $(PROJECT_OUTPUT)/yakka_summary.json > $@ $(PROJECT_OUTPUT)/generated/console_argument_types.h: $(console_DIRECTORY)/console_argument_types.h.template | $(PROJECT_OUTPUT)/generated/.directory components/yinja/yinja-$(HOST_OS) -t $(console_DIRECTORY)/console_argument_types.h.template -j $(PROJECT_OUTPUT)/yakka_summary.json > $@ diff --git a/components/console/console_minimal_uart_plugin.c b/components/console/console_minimal_uart_plugin.c index 1f9ca8fd7..ea160578c 100644 --- a/components/console/console_minimal_uart_plugin.c +++ b/components/console/console_minimal_uart_plugin.c @@ -196,19 +196,15 @@ static void post_uart_rx_handler(char character) escape_sequence = 0; } } else { - switch (character) { - case 'A': - // Up arrow pressed - current_buffer_index--; - - if (current_buffer_index >= USER_RX_BUFFER_COUNT) { - current_buffer_index = USER_RX_BUFFER_COUNT - 1; - } + if (character == 'A') { + // Up arrow pressed + current_buffer_index--; + if (current_buffer_index >= USER_RX_BUFFER_COUNT) { + current_buffer_index = USER_RX_BUFFER_COUNT - 1; + } - printf("%s", (const char *)&user_rx_buffer[current_buffer_index][0]); - break; + printf("%s", (const char *)&user_rx_buffer[current_buffer_index][0]); } - escape_sequence = 0; } } @@ -310,9 +306,9 @@ static void print_command_database(const console_database_t *database, const cha } } else { printf(" "); - console_print_command_args((console_descriptive_command_t *)database->entries[a].value); + console_print_command_args((const console_descriptive_command_t *)database->entries[a].value); printf("\r\n "); - printf(((console_descriptive_command_t *)database->entries[a].value)->description); + printf(((const console_descriptive_command_t *)database->entries[a].value)->description); } printf("\r\n"); } diff --git a/components/console/variables/console_variables.c b/components/console/variables/console_variables.c index 599c27de4..e5433eee2 100644 --- a/components/console/variables/console_variables.c +++ b/components/console/variables/console_variables.c @@ -16,11 +16,8 @@ ******************************************************************************/ #define _DEFAULT_SOURCE -//#include "console_variable_commands.h" + #include "console.h" -//#include "console_variables.h" -//#include "nvm3.h" -//#include "sl_wifi_types.h" #include "sl_ip_types.h" #include #include @@ -60,8 +57,8 @@ const structure_descriptor_entry_t *find_structure_entry(const char *key, uint32_t table_size); static void print_variable(const structure_descriptor_entry_t *entry, const void *object); -sl_status_t console_variable_get(console_args_t *arguments); -sl_status_t console_variable_set(console_args_t *arguments); +sl_status_t console_variable_get(const console_args_t *arguments); +sl_status_t console_variable_set(const console_args_t *arguments); /****************************************************** * Variable Definitions @@ -86,27 +83,13 @@ static sl_status_t find_variable_node(char **key, const console_variable_node_t while (token != NULL) { // Check for a key match if (strcmp(token, table[iter].key) == 0) { - switch (table[iter].type) { - case SL_CONSOLE_VARIABLE_GROUP_NODE: - table = table[iter].data.group.table; - table_size = table[iter].data.group.table_size; - break; - - default: - *key = strtok_r(NULL, KEY_SEPARATOR, &token_ptr); - *node = &table[iter]; - return SL_STATUS_OK; - - // case SL_CONSOLE_VARIABLE_RAM_STRUCT_NODE: - // return nodes[iter].data.ram_structure.handler(action, arguments, &nodes[iter]); - // break; - // - // case SL_CONSOLE_VARIABLE_CUSTOM_STRUCT_NODE: - // return nodes[iter].data.custom_structure.handler(action, arguments, &nodes[iter]); - // break; - // - // case SL_CONSOLE_VARIABLE_VARIABLE_NODE: - // break; + if (table[iter].type == SL_CONSOLE_VARIABLE_GROUP_NODE) { + table = table[iter].data.group.table; + table_size = table[iter].data.group.table_size; + } else { + *key = strtok_r(NULL, KEY_SEPARATOR, &token_ptr); + *node = &table[iter]; + return SL_STATUS_OK; } } else { ++iter; @@ -193,7 +176,7 @@ static void print_variable(const structure_descriptor_entry_t *entry, const void { switch (entry->type) { case CONSOLE_VARIABLE_BOOL: - if (*(uint8_t *)(object + entry->offset)) { + if (*(const uint8_t *)(object + entry->offset)) { printf("true\n"); } else { printf("false\n"); @@ -203,13 +186,13 @@ static void print_variable(const structure_descriptor_entry_t *entry, const void case CONSOLE_VARIABLE_UINT: switch (entry->size) { case 1: - printf("0x%X\n", *(uint8_t *)(object + entry->offset)); + printf("0x%X\n", *(const uint8_t *)(object + entry->offset)); break; case 2: - printf("0x%X\n", *(uint16_t *)(object + entry->offset)); + printf("0x%X\n", *(const uint16_t *)(object + entry->offset)); break; case 4: - printf("0x%lX\n", *(uint32_t *)(object + entry->offset)); + printf("0x%lX\n", *(const uint32_t *)(object + entry->offset)); break; default: break; @@ -219,13 +202,13 @@ static void print_variable(const structure_descriptor_entry_t *entry, const void case CONSOLE_VARIABLE_INT: switch (entry->size) { case 1: - printf("%d\n", *(int8_t *)(object + entry->offset)); + printf("%d\n", *(const int8_t *)(object + entry->offset)); break; case 2: - printf("%d\n", *(int16_t *)(object + entry->offset)); + printf("%d\n", *(const int16_t *)(object + entry->offset)); break; case 4: - printf("%ld\n", *(int32_t *)(object + entry->offset)); + printf("%ld\n", *(const int32_t *)(object + entry->offset)); break; default: break; @@ -233,11 +216,11 @@ static void print_variable(const structure_descriptor_entry_t *entry, const void break; case CONSOLE_VARIABLE_STRING: - printf("%s\n", (char *)(object + entry->offset)); + printf("%s\n", (const char *)(object + entry->offset)); break; case CONSOLE_VARIABLE_IP_ADDRESS: { - sl_ipv4_address_t *temp = (sl_ipv4_address_t *)(object + entry->offset); + const sl_ipv4_address_t *temp = (const sl_ipv4_address_t *)(object + entry->offset); printf("%d.%d.%d.%d\n", temp->bytes[0], temp->bytes[1], temp->bytes[2], temp->bytes[3]); } break; @@ -259,7 +242,7 @@ const structure_descriptor_entry_t *find_structure_entry(const char *key, return NULL; } -sl_status_t console_variable_get(console_args_t *arguments) +sl_status_t console_variable_get(const console_args_t *arguments) { const console_variable_node_t *node; char *key = (char *)arguments->arg[0]; @@ -275,11 +258,10 @@ sl_status_t console_variable_get(console_args_t *arguments) node->data.custom_structure.handler(SL_CONSOLE_VARIABLE_GET, node, (void *)arguments->arg[1]); } - // process_variable_request(SL_CONSOLE_VARIABLE_GET, arguments); return status; } -sl_status_t console_variable_set(console_args_t *arguments) +sl_status_t console_variable_set(const console_args_t *arguments) { const console_variable_node_t *node; char *key = (char *)arguments->arg[0]; @@ -322,7 +304,7 @@ sl_status_t console_variable_set(console_args_t *arguments) return status; } -sl_status_t console_variable_list(console_args_t *arguments) +sl_status_t console_variable_list(const console_args_t *arguments) { UNUSED_PARAMETER(arguments); if (console_variable_table_size == 0) { @@ -371,24 +353,13 @@ sl_status_t console_variable_list(console_args_t *arguments) --level; break; - // case SL_CONSOLE_VARIABLE_NVM_STRUCT_NODE: - // printf("%.*s- %s: ", level * 2, spaces, current_table[iter].key); - // uint32_t type; - // size_t length; - // sl_status_t status = - // nvm3_getObjectInfo(nvm3_defaultHandle, current_table[iter].data.custom_structure.nvm_id, &type, &length); - // if (status == SL_STATUS_OK) { - // printf("Data available\n"); - // } else { - // printf("No data\n"); - // } - // ++table_index[level]; - // break; - case SL_CONSOLE_VARIABLE_VARIABLE_NODE: printf("%.*s%s:\n", level * 2, spaces, tables[level][iter].key); ++table_index[level]; break; + + default: + break; } // Make sure we have a valid node, otherwise go up the tree until we do diff --git a/components/device/silabs/si91x/mcu/core/chip/component/device_needs_ram_execution.slcc b/components/device/silabs/si91x/mcu/core/chip/component/device_needs_ram_execution.slcc index 7c4566de7..f2586ad14 100644 --- a/components/device/silabs/si91x/mcu/core/chip/component/device_needs_ram_execution.slcc +++ b/components/device/silabs/si91x/mcu/core/chip/component/device_needs_ram_execution.slcc @@ -11,11 +11,11 @@ provides: - name: device_needs_ram_execution define: - name: SLI_SI91X_MCU_ENABLE_RAM_BASED_EXECUTION + - name: SLI_SI91X_MCU_ENABLE_PSRAM_SECTION_FEATURE + condition: [wiseconnect_toolchain_psram_linker] template_contribution: - name: ram_execution value: true - name: device_ram_addr value: 1024 priority: -2 -conflicts: - - name: text_segment_in_psram diff --git a/components/device/silabs/si91x/mcu/core/chip/component/external_psram_2mb.slcc b/components/device/silabs/si91x/mcu/core/chip/component/external_psram_2mb.slcc index 3733e319b..9b548b6bb 100644 --- a/components/device/silabs/si91x/mcu/core/chip/component/external_psram_2mb.slcc +++ b/components/device/silabs/si91x/mcu/core/chip/component/external_psram_2mb.slcc @@ -7,7 +7,8 @@ quality: production provides: - name: external_psram_2mb - name: external_psram_implementation - +define: + - name: SLI_SI91X_MCU_PSRAM_PRESENT template_contribution: - name: psram_present value: 1 diff --git a/components/device/silabs/si91x/mcu/core/chip/component/external_psram_4mb.slcc b/components/device/silabs/si91x/mcu/core/chip/component/external_psram_4mb.slcc index 175891c79..79d59406f 100644 --- a/components/device/silabs/si91x/mcu/core/chip/component/external_psram_4mb.slcc +++ b/components/device/silabs/si91x/mcu/core/chip/component/external_psram_4mb.slcc @@ -7,7 +7,8 @@ quality: production provides: - name: external_psram_4mb - name: external_psram_implementation - +define: + - name: SLI_SI91X_MCU_PSRAM_PRESENT template_contribution: - name: psram_present value: 1 diff --git a/components/device/silabs/si91x/mcu/core/chip/component/external_psram_8mb.slcc b/components/device/silabs/si91x/mcu/core/chip/component/external_psram_8mb.slcc index 0d4acaf85..9be29dea4 100644 --- a/components/device/silabs/si91x/mcu/core/chip/component/external_psram_8mb.slcc +++ b/components/device/silabs/si91x/mcu/core/chip/component/external_psram_8mb.slcc @@ -7,7 +7,8 @@ quality: production provides: - name: external_psram_8mb - name: external_psram_implementation - +define: + - name: SLI_SI91X_MCU_PSRAM_PRESENT template_contribution: - name: psram_present value: 1 diff --git a/components/device/silabs/si91x/mcu/core/chip/component/siwg917m110lgtba.slcc b/components/device/silabs/si91x/mcu/core/chip/component/siwg917m110lgtba.slcc index 6dcb4715b..7baca8a3a 100644 --- a/components/device/silabs/si91x/mcu/core/chip/component/siwg917m110lgtba.slcc +++ b/components/device/silabs/si91x/mcu/core/chip/component/siwg917m110lgtba.slcc @@ -33,7 +33,6 @@ - include: - file_list: - path: system_si91x.h - - path: si91x_mvp.h - path: si91x_device.h path: components/device/silabs/si91x/mcu/core/chip/inc/ - provides: @@ -46,8 +45,6 @@ - name: armv7em - name: device_supports_psram - name: device_has_stacked_flash - - name: device_has_mvp - - name: device_compute_mvp - name: device_has_mpu - requires: - name: rsilib_chip @@ -80,7 +77,6 @@ value: 7168 - name: nvm3_size value: 65536 - - name: flash_present value: 1 @@ -117,8 +113,6 @@ priority: 1000 condition: - si917_mem_config_3 - - - name: device_flash_page_size value: 256 - name: device_ram_addr diff --git a/components/device/silabs/si91x/mcu/core/chip/component/siwg917m121xgtba.slcc b/components/device/silabs/si91x/mcu/core/chip/component/siwg917m121xgtba.slcc index 59a0dad0e..a35c87c8f 100644 --- a/components/device/silabs/si91x/mcu/core/chip/component/siwg917m121xgtba.slcc +++ b/components/device/silabs/si91x/mcu/core/chip/component/siwg917m121xgtba.slcc @@ -28,6 +28,7 @@ unless: [rsilib_board] - name: SLI_SI91X_MCU_CONFIG_RADIO_BOARD_VER2 unless: [rsilib_board] + - name: SLI_SI91X_MCU_PSRAM_PRESENT - source: - path: components/device/silabs/si91x/mcu/core/chip/src/system_si91x.c - path: components/device/silabs/si91x/mcu/core/chip/src/startup_si91x.c diff --git a/components/device/silabs/si91x/mcu/core/chip/component/siwg917m141xgtba.slcc b/components/device/silabs/si91x/mcu/core/chip/component/siwg917m141xgtba.slcc index 640e47167..0a6e7dd8d 100644 --- a/components/device/silabs/si91x/mcu/core/chip/component/siwg917m141xgtba.slcc +++ b/components/device/silabs/si91x/mcu/core/chip/component/siwg917m141xgtba.slcc @@ -28,6 +28,7 @@ unless: [rsilib_board] - name: SLI_SI91X_MCU_CONFIG_RADIO_BOARD_VER2 unless: [rsilib_board] + - name: SLI_SI91X_MCU_PSRAM_PRESENT - source: - path: components/device/silabs/si91x/mcu/core/chip/src/system_si91x.c - path: components/device/silabs/si91x/mcu/core/chip/src/startup_si91x.c diff --git a/components/device/silabs/si91x/mcu/core/chip/component/siwg917y111mgab.slcc b/components/device/silabs/si91x/mcu/core/chip/component/siwg917y111mgab.slcc index 2b6dbcfdf..102307aac 100644 --- a/components/device/silabs/si91x/mcu/core/chip/component/siwg917y111mgab.slcc +++ b/components/device/silabs/si91x/mcu/core/chip/component/siwg917y111mgab.slcc @@ -16,6 +16,8 @@ value: '1' - name: SLI_SI91X_MCU_ENABLE_FLASH_BASED_EXECUTION value: '1' + - name: SL_SI91X_MODULE_BOARD + value: '1' - name: SRAM_BASE value: "0x0cUL" unless: [rsilib_board] diff --git a/components/device/silabs/si91x/mcu/core/chip/component/siwg917y111mgnb.slcc b/components/device/silabs/si91x/mcu/core/chip/component/siwg917y111mgnba.slcc similarity index 92% rename from components/device/silabs/si91x/mcu/core/chip/component/siwg917y111mgnb.slcc rename to components/device/silabs/si91x/mcu/core/chip/component/siwg917y111mgnba.slcc index fef96d5c4..5d7269c9f 100644 --- a/components/device/silabs/si91x/mcu/core/chip/component/siwg917y111mgnb.slcc +++ b/components/device/silabs/si91x/mcu/core/chip/component/siwg917y111mgnba.slcc @@ -1,13 +1,13 @@ !!omap -- id: SIWG917Y111MGNB +- id: SIWG917Y111MGNBA - package: platform-si91x -- description: Silicon Labs CMSIS-Device part headers for SIWG917Y111MGNB. +- description: Silicon Labs CMSIS-Device part headers for SIWG917Y111MGNBA. - category: Platform|Device|Si91x|MCU|Family|SIWG917Y - ui_hints: visibility: never - quality: production - define: - - name: SIWG917Y111MGNB + - name: SIWG917Y111MGNBA unless: - device_content_override - name: SLI_SI917 @@ -16,6 +16,8 @@ value: '1' - name: SLI_SI91X_MCU_ENABLE_FLASH_BASED_EXECUTION value: '1' + - name: SL_SI91X_MODULE_BOARD + value: '1' - name: SRAM_BASE value: "0x0cUL" unless: [rsilib_board] @@ -31,7 +33,7 @@ - path: components/device/silabs/si91x/mcu/core/chip/src/startup_si91x.c unless: [siwx917_soc_custom_startup] - provides: - - name: siwg917y111mgnb + - name: siwg917y111mgnba - name: device_si91x - name: device_family_siwg917 - name: si91x_platform @@ -56,7 +58,7 @@ condition: [freertos] - template_contribution: - name: device_opn - value: SIWG917Y111MGNB + value: SIWG917Y111MGNBA - name: device_arch value: armv7em - name: device_cpu @@ -118,10 +120,10 @@ - name: device_ram_addr value: 12 - tag: - - device:opn:siwg917y111mgnb + - device:opn:siwg917y111mgnba - toolchain_settings: - option: device_opn - value: siwg917y111mgnb + value: siwg917y111mgnba - option: architecture value: armv7e-m - option: cpu @@ -142,4 +144,4 @@ size: 196608 start: 12 type: volatile - opn: siwg917y111mgnb \ No newline at end of file + opn: siwg917y111mgnba \ No newline at end of file diff --git a/components/device/silabs/si91x/mcu/core/chip/component/siwg917y121mgnb.slcc b/components/device/silabs/si91x/mcu/core/chip/component/siwg917y121mgnb.slcc new file mode 100644 index 000000000..c530c14c6 --- /dev/null +++ b/components/device/silabs/si91x/mcu/core/chip/component/siwg917y121mgnb.slcc @@ -0,0 +1,161 @@ +!!omap +- id: SIWG917Y121MGNB +- package: platform-si91x +- description: Silicon Labs CMSIS-Device part headers for SIWG917Y121MGNB. +- category: Platform|Device|Si91x|MCU|Family|SIWG917Y +- ui_hints: + visibility: never +- quality: production +- define: + - name: SIWG917Y121MGNB + unless: + - device_content_override + - name: SLI_SI917 + value: '1' + - name: SLI_SI917B0 + value: '1' + - name: SLI_SI91X_MCU_ENABLE_FLASH_BASED_EXECUTION + value: '1' + - name: SLI_SI91X_MCU_INTERNAL_LDO_FOR_PSRAM + value: '1' + - name: SL_SI91X_MODULE_BOARD + value: '1' + - name: SRAM_BASE + value: "0x0cUL" + unless: [rsilib_board] + - name: SRAM_SIZE + value: "0x2fc00UL" + unless: [rsilib_board] + - name: SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER + unless: [rsilib_board] + - name: SLI_SI91X_MCU_CONFIG_RADIO_BOARD_VER2 + unless: [rsilib_board] +- source: + - path: components/device/silabs/si91x/mcu/core/chip/src/system_si91x.c + - path: components/device/silabs/si91x/mcu/core/chip/src/startup_si91x.c + unless: [siwx917_soc_custom_startup] +- provides: + - name: siwg917y121mgnb + - name: device_si91x + - name: device_family_siwg917 + - name: si91x_platform + - name: device_arm + - name: cortexm4 + - name: armv7em + - name: device_has_mvp + - name: device_compute_mvp + - name: device_supports_psram + - name: device_has_stacked_flash + - name: device_has_mpu + - name: device_is_module + - name: device_no_antenna +- requires: + - name: rsilib_chip + - name: romdriver_clks + - name: si917_mem_config + - name: sl_si91x_mcu + - name: board_configuration_headers + - name: wiseconnect_toolchain_plugin + - name: psram_configuration_headers + condition: [rsilib_board] + - name: freertos_config + condition: [freertos] +- template_contribution: + - name: device_opn + value: SIWG917Y121MGNB + - name: device_arch + value: armv7em + - name: device_cpu + value: cortexm4 + - name: device_family + value: siwg917y + - name: device_fpu + value: true + - name: device_mpu + value: true + - name: default_stack_size + value: 3072 + - name: default_heap_size + value: 7168 + - name: nvm3_size + value: 65536 + - name: psram_present + value: 1 + - name: device_psram_addr + value: 167772160 # 0x0A00_0000 + - name: device_psram_size + value: 2097152 + + - name: flash_present + value: 1 + + # Default Memory configuration + - name: device_flash_addr + value: 136323072 # 0x0820 2000 + priority: -1 + condition: + - si917_mem_config_1 + - name: device_flash_size + value: 2088960 # 0x001F E000 + priority: -1 + condition: + - si917_mem_config_1 + # Medium Memory configuration + - name: device_flash_addr + value: 136323072 # 0x0820 2000 + priority: -1 + condition: + - si917_mem_config_2 + - name: device_flash_size + value: 2088960 # 0x001F E000 + priority: -1 + condition: + - si917_mem_config_2 + # Advanced Memory configuration + - name: device_flash_addr + value: 136323072 # 0x0820 2000 + priority: -1 + condition: + - si917_mem_config_3 + - name: device_flash_size + value: 2088960 # 0x001F E000 + priority: -1 + condition: + - si917_mem_config_3 + + + - name: device_flash_page_size + value: 256 + + - name: device_ram_addr + value: 12 +- tag: + - device:opn:siwg917y121mgnb +- toolchain_settings: + - option: device_opn + value: siwg917y121mgnb + - option: architecture + value: armv7e-m + - option: cpu + value: cortex-m4 + - option: fpu + value: fpv4-sp +- metadata: + device: + memory: + # External flash details will be provided by the External Flash component + - name: Stacked PSRAM + size: 2097152 # 2MB + start: 167772160 # 0x0A00_0000 + type: volatile + - name: Main Flash + page_size: 256 + size: 8388608 + start: 136060928 + type: non-volatile + # TODO: Check these Values + - name: RAM + size: 196608 + start: 12 + type: volatile + opn: siwg917y121mgnb \ No newline at end of file diff --git a/components/device/silabs/si91x/mcu/core/chip/component/ulp_mode_execution.slcc b/components/device/silabs/si91x/mcu/core/chip/component/ulp_mode_execution.slcc deleted file mode 100644 index dbefcc5b4..000000000 --- a/components/device/silabs/si91x/mcu/core/chip/component/ulp_mode_execution.slcc +++ /dev/null @@ -1,13 +0,0 @@ -id: ulp_mode_execution -package: platform -description: Enables ultra-low-power (ULP) mode by executing text section from RAM. -category: Device|Si91x|MCU|Core -label: ULP Platform RAM Execution -quality: production -provides: - - name: ulp_mode_execution -define: - - name: ULP_MODE_EXECUTION -template_contribution: - - name: ulp_mode_execution - value: true \ No newline at end of file diff --git a/components/device/silabs/si91x/mcu/core/chip/config/RTE_Device_917.h b/components/device/silabs/si91x/mcu/core/chip/config/RTE_Device_917.h index bc6e89cfd..4dda89a60 100644 --- a/components/device/silabs/si91x/mcu/core/chip/config/RTE_Device_917.h +++ b/components/device/silabs/si91x/mcu/core/chip/config/RTE_Device_917.h @@ -53,7 +53,7 @@ #define RTE_BUTTON1_PIN (11U) #define RTE_BUTTON1_PAD 6 -#define RTE_LED0_PORT 0 +#define RTE_LED0_PORT 4 #define RTE_LED0_NUMBER 0 #define RTE_LED0_PIN (2U) @@ -69,7 +69,7 @@ #define RTE_USART0 1 -#define RTE_USART0_CLK_SRC USART_INTFPLLCLK +#define RTE_USART0_CLK_SRC USART_ULPREFCLK #define RTE_USART0_CLK_DIV_FACT 1 #define RTE_USART0_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER @@ -231,7 +231,7 @@ #define RTE_USART0_RX_PORT 0 #define RTE_USART0_RX_PIN 65 #define RTE_USART0_RX_MUX 2 -#define RTE_USART0_RX_PAD 24 +#define RTE_USART0_RX_PAD 23 #elif (RTE_USART0_RX_PORT_ID == 4) #define RTE_USART0_RX_PORT 0 #define RTE_USART0_RX_PIN 70 @@ -584,7 +584,7 @@ // Configuration settings for Driver_UART1 in component ::CMSIS Driver:USART #define RTE_UART1 1 -#define RTE_UART1_CLK_SRC USART_INTFPLLCLK +#define RTE_UART1_CLK_SRC USART_ULPREFCLK #define RTE_UART1_CLK_DIV_FACT 1 #define RTE_UART1_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER @@ -4894,4 +4894,24 @@ #define SENSOR_ENABLE_GPIO_MAPPED_TO_UULP #define SENSOR_ENABLE_GPIO_PIN RTE_UULP_GPIO_1_PIN +// Memlcd GPIOs +#ifdef SL_SI91X_MODULE_BOARD +#define RTE_MEMLCD_CS_PIN 4 // Memlcd SPI CS pin +#define RTE_MEMLCD_CS_PORT 0 // Memlcd SPI CS port + +#define RTE_MEMLCD_EXTCOMIN_PIN 5 // Memlcd external communication pin +#define RTE_MEMLCD_EXTCOMIN_PORT 0 // Memlcd external communication port + +#else + +#define RTE_MEMLCD_CS_PIN 10 // Memlcd SPI CS pin +#define RTE_MEMLCD_CS_PORT 0 // Memlcd SPI CS port + +#define RTE_MEMLCD_EXTCOMIN_PIN 3 // Memlcd external communication pin +#define RTE_MEMLCD_EXTCOMIN_PORT 0 // Memlcd external communication port +#endif + +#define RTE_MEMLCD_ENABLE_DISPLAY_PIN 0 // Memlcd display enable pin +#define RTE_MEMLCD_ENABLE_DISPLAY_PORT 0 // Memlcd display enable port + #endif // USER_CONFIGURATION_ENABLE \ No newline at end of file diff --git a/components/device/silabs/si91x/mcu/core/chip/inc/base_types.h b/components/device/silabs/si91x/mcu/core/chip/inc/base_types.h index 1ba81d77e..9993bb142 100644 --- a/components/device/silabs/si91x/mcu/core/chip/inc/base_types.h +++ b/components/device/silabs/si91x/mcu/core/chip/inc/base_types.h @@ -30,7 +30,7 @@ extern "C" { #include #include /*****************************************************************************/ -/* Global pre-processor symbols/macros ('#define') */ +/* Global pre-processor symbols/macros */ /*****************************************************************************/ #ifndef TRUE /** Value is true (boolean_t type) */ diff --git a/components/device/silabs/si91x/mcu/core/chip/inc/rsi_error.h b/components/device/silabs/si91x/mcu/core/chip/inc/rsi_error.h index 8b208062a..eb077b3a8 100644 --- a/components/device/silabs/si91x/mcu/core/chip/inc/rsi_error.h +++ b/components/device/silabs/si91x/mcu/core/chip/inc/rsi_error.h @@ -25,147 +25,147 @@ extern "C" { #endif typedef enum errnoCode { - RSI_FAIL = -1, - RSI_OK = 0, - INVALID_PARAMETERS, + RSI_FAIL = -1, + RSI_OK = 0, + INVALID_PARAMETERS = 1, /*USART error codes*/ - ERROR_USART_BASE = 0x100, - ERROR_USART_CALLBACK_ERR = ERROR_USART_BASE + 1, - ERROR_USART_NOT_SUPPORTED, + ERROR_USART_BASE = 0x100, + ERROR_USART_CALLBACK_ERR = ERROR_USART_BASE + 1, + ERROR_USART_NOT_SUPPORTED = ERROR_USART_CALLBACK_ERR + 1, /* GPDMA error codes */ - ERROR_GPDMA_BASE = 0x200, - ERROR_GPDMA_INVALIDCHNLNUM = ERROR_GPDMA_BASE + 1, - ERROR_GPDMA_FLW_CTRL, - ERROR_GPDMA_BURST, - ERROR_GPDMA_SRC_ADDR, - ERROR_GPDMA_DST_ADDR, - NOERR_GPDMA_FLAG_SET, - ERROR_GPDMA_INVALID_EVENT, - ERROR_GPDMA_INVALID_XFERMODE, - ERROR_GPDMA_INVALID_TRANS_LEN, - ERROR_GPDMA_INVALID_ARG, - ERROR_GPDMA_CHNL_BUSY, - ERROR_GPDMA_NOT_ALIGNMENT, - ERROR_GPDMA_QUEUE_EMPTY, - ERROR_GPDMA_GENERAL, + ERROR_GPDMA_BASE = 0x200, + ERROR_GPDMA_INVALIDCHNLNUM = ERROR_GPDMA_BASE + 1, + ERROR_GPDMA_FLW_CTRL = ERROR_GPDMA_INVALIDCHNLNUM + 1, + ERROR_GPDMA_BURST = ERROR_GPDMA_FLW_CTRL + 1, + ERROR_GPDMA_SRC_ADDR = ERROR_GPDMA_BURST + 1, + ERROR_GPDMA_DST_ADDR = ERROR_GPDMA_SRC_ADDR + 1, + NOERR_GPDMA_FLAG_SET = ERROR_GPDMA_DST_ADDR + 1, + ERROR_GPDMA_INVALID_EVENT = NOERR_GPDMA_FLAG_SET + 1, + ERROR_GPDMA_INVALID_XFERMODE = ERROR_GPDMA_INVALID_EVENT + 1, + ERROR_GPDMA_INVALID_TRANS_LEN = ERROR_GPDMA_INVALID_XFERMODE + 1, + ERROR_GPDMA_INVALID_ARG = ERROR_GPDMA_INVALID_TRANS_LEN + 1, + ERROR_GPDMA_CHNL_BUSY = ERROR_GPDMA_INVALID_ARG + 1, + ERROR_GPDMA_NOT_ALIGNMENT = ERROR_GPDMA_CHNL_BUSY + 1, + ERROR_GPDMA_QUEUE_EMPTY = ERROR_GPDMA_NOT_ALIGNMENT + 1, + ERROR_GPDMA_GENERAL = ERROR_GPDMA_QUEUE_EMPTY + 1, /* UDMA error codes */ - ERROR_UDMA_BASE = 0x300, - ERROR_UDMA_INVALIDCHNLNUM = ERROR_UDMA_BASE + 1, - ERROR_UDMA_CTRL_BASE_INVALID, - ERROR_UDMA_INVALID_XFERMODE, - ERROR_UDMA_INVALID_TRANS_LEN, - ERROR_UDMA_INVALID_ARG, - ERROR_UDMA_SRC_ADDR, - ERROR_UDMA_DST_ADDR, - ERROR_UDMA_CHNL_BUSY, + ERROR_UDMA_BASE = 0x300, + ERROR_UDMA_INVALIDCHNLNUM = ERROR_UDMA_BASE + 1, + ERROR_UDMA_CTRL_BASE_INVALID = ERROR_UDMA_INVALIDCHNLNUM + 1, + ERROR_UDMA_INVALID_XFERMODE = ERROR_UDMA_CTRL_BASE_INVALID + 1, + ERROR_UDMA_INVALID_TRANS_LEN = ERROR_UDMA_INVALID_XFERMODE + 1, + ERROR_UDMA_INVALID_ARG = ERROR_UDMA_INVALID_TRANS_LEN + 1, + ERROR_UDMA_SRC_ADDR = ERROR_UDMA_INVALID_ARG + 1, + ERROR_UDMA_DST_ADDR = ERROR_UDMA_SRC_ADDR + 1, + ERROR_UDMA_CHNL_BUSY = ERROR_UDMA_DST_ADDR + 1, /* I2C error codes */ - ERROR_I2C_BASE = 0x400, - ERROR_I2C_INVALID_ARG = ERROR_I2C_BASE + 1, - ERROR_I2CS_UNKNOWN, - ERROR_I2C_SPIKE_LOGIC, - ERROR_I2C_IGNORE_GC_OR_START, - ERROR_I2C_STATUS_FLAG_NOT_SET, - ERROR_I2C_BUSY_FLAG, - ERROR_I2C_MST_BUSY_FLAG, - ERROR_I2C_SLV_BUSY_FLAG, - ERROR_I2C_SLV_DIS_WHILE_BUSY, - ERROR_I2C_MST_XFER_ABORT, - ERROR_I2C_MST_TX_CMD_BLOCK, - ERROR_I2C_SLV_RX_DATA_LOST, - ERROR_I2C_NO_TX_DATA, - ERROR_I2C_NO_INTR_FLAG, - ERROR_I2C_ERROR_FLAG_NONE, - ERROR_I2C_INVALID_CB, - ERROR_I2C_INVALID_POINTER, - ERROR_I2C_GENERAL_FAILURE, - ERROR_I2C_TXABORT, - ERROR_I2C_SCL_STUCK_ATLOW, - ERROR_I2C_MST_ON_HOLD, - ERROR_I2C_BUFFER_OVERFLOW, - ERROR_I2C_BUFFER_UNDERFLOW, + ERROR_I2C_BASE = 0x400, + ERROR_I2C_INVALID_ARG = ERROR_I2C_BASE + 1, + ERROR_I2CS_UNKNOWN = ERROR_I2C_INVALID_ARG + 1, + ERROR_I2C_SPIKE_LOGIC = ERROR_I2CS_UNKNOWN + 1, + ERROR_I2C_IGNORE_GC_OR_START = ERROR_I2C_SPIKE_LOGIC + 1, + ERROR_I2C_STATUS_FLAG_NOT_SET = ERROR_I2C_IGNORE_GC_OR_START + 1, + ERROR_I2C_BUSY_FLAG = ERROR_I2C_STATUS_FLAG_NOT_SET + 1, + ERROR_I2C_MST_BUSY_FLAG = ERROR_I2C_BUSY_FLAG + 1, + ERROR_I2C_SLV_BUSY_FLAG = ERROR_I2C_MST_BUSY_FLAG + 1, + ERROR_I2C_SLV_DIS_WHILE_BUSY = ERROR_I2C_SLV_BUSY_FLAG + 1, + ERROR_I2C_MST_XFER_ABORT = ERROR_I2C_SLV_DIS_WHILE_BUSY + 1, + ERROR_I2C_MST_TX_CMD_BLOCK = ERROR_I2C_MST_XFER_ABORT + 1, + ERROR_I2C_SLV_RX_DATA_LOST = ERROR_I2C_MST_TX_CMD_BLOCK + 1, + ERROR_I2C_NO_TX_DATA = ERROR_I2C_SLV_RX_DATA_LOST + 1, + ERROR_I2C_NO_INTR_FLAG = ERROR_I2C_NO_TX_DATA + 1, + ERROR_I2C_ERROR_FLAG_NONE = ERROR_I2C_NO_INTR_FLAG + 1, + ERROR_I2C_INVALID_CB = ERROR_I2C_ERROR_FLAG_NONE + 1, + ERROR_I2C_INVALID_POINTER = ERROR_I2C_INVALID_CB + 1, + ERROR_I2C_GENERAL_FAILURE = ERROR_I2C_INVALID_POINTER + 1, + ERROR_I2C_TXABORT = ERROR_I2C_GENERAL_FAILURE + 1, + ERROR_I2C_SCL_STUCK_ATLOW = ERROR_I2C_TXABORT + 1, + ERROR_I2C_MST_ON_HOLD = ERROR_I2C_SCL_STUCK_ATLOW + 1, + ERROR_I2C_BUFFER_OVERFLOW = ERROR_I2C_MST_ON_HOLD + 1, + ERROR_I2C_BUFFER_UNDERFLOW = ERROR_I2C_BUFFER_OVERFLOW + 1, /* I2S error codes */ - ERROR_I2S_BASE = 0x500, - ERROR_I2S_INVALID_ARG = ERROR_I2S_BASE + 1, - ERROR_I2S_INVALID_RES, - ERROR_I2S_INVALID_LENGTH, - ERROR_I2S_BUSY, - ERROR_I2S_TXOVERRUN, - ERROR_I2S_RXOVERRUN, - ERROR_I2S_TXCOMPLETE, - ERROR_I2S_RXCOMPLETE, + ERROR_I2S_BASE = 0x500, + ERROR_I2S_INVALID_ARG = ERROR_I2S_BASE + 1, + ERROR_I2S_INVALID_RES = ERROR_I2S_INVALID_ARG + 1, + ERROR_I2S_INVALID_LENGTH = ERROR_I2S_INVALID_RES + 1, + ERROR_I2S_BUSY = ERROR_I2S_INVALID_LENGTH + 1, + ERROR_I2S_TXOVERRUN = ERROR_I2S_BUSY + 1, + ERROR_I2S_RXOVERRUN = ERROR_I2S_TXOVERRUN + 1, + ERROR_I2S_TXCOMPLETE = ERROR_I2S_RXOVERRUN + 1, + ERROR_I2S_RXCOMPLETE = ERROR_I2S_TXCOMPLETE + 1, /* UART error codes */ ERROR_UART_BASE = 0x600, ERROR_UART_INVALID_ARG = ERROR_UART_BASE + 1, - ERROR_UART_INVALID_RES, + ERROR_UART_INVALID_RES = ERROR_UART_INVALID_ARG + 1, /* PWM error codes */ ERROR_PWM_BASE = 0x700, ERROR_PWM_INVALID_CHNLNUM = ERROR_PWM_BASE + 1, - ERROR_PWM_INVALID_PWMOUT, - ERROR_PWM_NO_INTR, - ERROR_PWM_INVALID_ARG, + ERROR_PWM_INVALID_PWMOUT = ERROR_PWM_INVALID_CHNLNUM + 1, + ERROR_PWM_NO_INTR = ERROR_PWM_INVALID_PWMOUT + 1, + ERROR_PWM_INVALID_ARG = ERROR_PWM_NO_INTR + 1, /* Timers error codes */ - ERROR_TIMER_BASE = 0x800, - ERROR_INVAL_TIMER_NUM = ERROR_TIMER_BASE + 1, - ERROR_INVAL_TIMER_MODE, - ERROR_INVAL_TIMERTYPE, - ERROR_INVAL_COUNTER_DIR, + ERROR_TIMER_BASE = 0x800, + ERROR_INVAL_TIMER_NUM = ERROR_TIMER_BASE + 1, + ERROR_INVAL_TIMER_MODE = ERROR_INVAL_TIMER_NUM + 1, + ERROR_INVAL_TIMERTYPE = ERROR_INVAL_TIMER_MODE + 1, + ERROR_INVAL_COUNTER_DIR = ERROR_INVAL_TIMERTYPE + 1, /* SCT error codes */ ERROR_CT_BASE = 0x900, ERROR_CT_INVALID_COUNTER_NUM = ERROR_CT_BASE + 1, - ERROR_CT_INVALID_ARG, + ERROR_CT_INVALID_ARG = ERROR_CT_INVALID_COUNTER_NUM + 1, /* EFUSE ERROR CODES */ - ERROR_EFUSE_BASE = 0xA00, - ERROR_EFUSE_INVALID_WRITE_ADDRESS = ERROR_EFUSE_BASE + 1, - ERROR_EFUSE_INVALID_WRITE_BIT_POSITION, - ERROR_EFUSE_INVALID_PARAMETERS, + ERROR_EFUSE_BASE = 0xA00, + ERROR_EFUSE_INVALID_WRITE_ADDRESS = ERROR_EFUSE_BASE + 1, + ERROR_EFUSE_INVALID_WRITE_BIT_POSITION = ERROR_EFUSE_INVALID_WRITE_ADDRESS + 1, + ERROR_EFUSE_INVALID_PARAMETERS = ERROR_EFUSE_INVALID_WRITE_BIT_POSITION + 1, /* CCI ERROR CODES */ ERROR_CCI_BASE_ADDRESS = 0xB00, ERROR_CCI_INIT_FAIL = ERROR_CCI_BASE_ADDRESS + 1, - ERROR_CCI_ADDRESS_ERR, + ERROR_CCI_ADDRESS_ERR = ERROR_CCI_INIT_FAIL + 1, /* QEI ERROR CODES */ - ERROR_QEI_BASE = 0xC00, - ERROR_INVALID_WRITE_ADDRESS = ERROR_QEI_BASE + 1, - ERROR_INVALID_WRITE_BIT_POSITION, - ERROR_INVALID_PARAMETERS, + ERROR_QEI_BASE = 0xC00, + ERROR_INVALID_WRITE_ADDRESS = ERROR_QEI_BASE + 1, + ERROR_INVALID_WRITE_BIT_POSITION = ERROR_INVALID_WRITE_ADDRESS + 1, + ERROR_INVALID_PARAMETERS = ERROR_INVALID_WRITE_BIT_POSITION + 1, /* SDIO ERROR CODES */ - ERROR_SSDIO_BASE_ADDRESS = 0xD00, /*!< SDIO Error base address */ - ERROR_SSDIO_INIT_FAIL = ERROR_SSDIO_BASE_ADDRESS + 1, - ERROR_SSDIO_ADDRESS_ERR, - ERROR_SSDIO_INVALID_FN, - ERROR_SSDIO_INVALID_PARAM, + ERROR_SSDIO_BASE_ADDRESS = 0xD00, /*!< SDIO Error base address */ + ERROR_SSDIO_INIT_FAIL = ERROR_SSDIO_BASE_ADDRESS + 1, + ERROR_SSDIO_ADDRESS_ERR = ERROR_SSDIO_INIT_FAIL + 1, + ERROR_SSDIO_INVALID_FN = ERROR_SSDIO_ADDRESS_ERR + 1, + ERROR_SSDIO_INVALID_PARAM = ERROR_SSDIO_INVALID_FN + 1, /* SPI ERROR CODES*/ ERROR_SSPI_BASE_ADDRESS = 0xE00, ERROR_SSPI_INIT_FAIL = ERROR_SSPI_BASE_ADDRESS + 1, - ERROR_SSPI_ADDRESS_ERR, - ERROR_SSPI_CB_ERROR, + ERROR_SSPI_ADDRESS_ERR = ERROR_SSPI_INIT_FAIL + 1, + ERROR_SSPI_CB_ERROR = ERROR_SSPI_ADDRESS_ERR + 1, /* ETHERNET ERROR CODES */ ERROR_ETH_BASE_ADDRESS = 0xF00, ERROR_ETH_INIT_FAIL = ERROR_ETH_BASE_ADDRESS + 1, - ERROR_ETH_PARAM, - ERROR_ETH_NULL, - ERR_DMA_NOT_ALIGNMENT, - ERROR_ETH_CALLBACK_ERR, + ERROR_ETH_PARAM = ERROR_ETH_INIT_FAIL + 1, + ERROR_ETH_NULL = ERROR_ETH_PARAM + 1, + ERR_DMA_NOT_ALIGNMENT = ERROR_ETH_NULL + 1, + ERROR_ETH_CALLBACK_ERR = ERR_DMA_NOT_ALIGNMENT + 1, /*CAN ERROR CODES*/ - ERROR_CAN_BASE = 0x1000, - ERROR_CAN_INVALID_PARAMETERS = ERROR_CAN_BASE + 1, - ERROR_CAN_INVALID_TIMING_PARAMETERS, - ERROR_CAN_OPERATION_IN_PROGRESS, + ERROR_CAN_BASE = 0x1000, + ERROR_CAN_INVALID_PARAMETERS = ERROR_CAN_BASE + 1, + ERROR_CAN_INVALID_TIMING_PARAMETERS = ERROR_CAN_INVALID_PARAMETERS + 1, + ERROR_CAN_OPERATION_IN_PROGRESS = ERROR_CAN_INVALID_TIMING_PARAMETERS + 1, /*GSPI ERROR CODES*/ ERROR_GSPI_BASE = 0x1100, @@ -193,22 +193,22 @@ typedef enum errnoCode { ERROR_RNG_INVALID_ARG = ERROR_RNG_BASE + 1, /*NPSS ERROR CODES*/ - ERROR_BOD_BASE = 0x1500, - ERROR_PS_BASE = ERROR_BOD_BASE + 1, - ERROR_BOD_INVALID_PARAMETERS, - ERROR_PS_INVALID_PARAMETERS, - ERROR_PS_INVALID_STATE, + ERROR_BOD_BASE = 0x1500, + ERROR_PS_BASE = ERROR_BOD_BASE + 1, + ERROR_BOD_INVALID_PARAMETERS = ERROR_PS_BASE + 1, + ERROR_PS_INVALID_PARAMETERS = ERROR_BOD_INVALID_PARAMETERS + 1, + ERROR_PS_INVALID_STATE = ERROR_PS_INVALID_PARAMETERS + 1, /*TIME PERIOD*/ - ERROR_TIMEPERIOD_BASE = 0x1600, - ERROR_TIME_PERIOD_PARAMETERS = ERROR_TIMEPERIOD_BASE + 1, - ERROR_TIME_PERIOD_RC_CALIB_NOT_DONE, - ERROR_CAL_INVALID_PARAMETERS, + ERROR_TIMEPERIOD_BASE = 0x1600, + ERROR_TIME_PERIOD_PARAMETERS = ERROR_TIMEPERIOD_BASE + 1, + ERROR_TIME_PERIOD_RC_CALIB_NOT_DONE = ERROR_TIME_PERIOD_PARAMETERS + 1, + ERROR_CAL_INVALID_PARAMETERS = ERROR_TIME_PERIOD_RC_CALIB_NOT_DONE + 1, /*M4SS CLOCKS */ - ERROR_M4SS_CLK_BASE = 0x1700, - ERROR_CLOCK_NOT_ENABLED = ERROR_M4SS_CLK_BASE + 1, - ERROR_INVALID_INPUT_FREQUENCY, + ERROR_M4SS_CLK_BASE = 0x1700, + ERROR_CLOCK_NOT_ENABLED = ERROR_M4SS_CLK_BASE + 1, + ERROR_INVALID_INPUT_FREQUENCY = ERROR_CLOCK_NOT_ENABLED + 1, /*ULPSS CLOCKS */ ERROR_ULPCLK_BASE = 1800, @@ -236,17 +236,17 @@ typedef enum errnoCode { ERROR_FREQ_VAL = ERROR_NO_PAD_SEL + 1, /*SDMEM*/ - ERROR_ACCESS_RIGHTS = 0x2300, - ERROR_ADDR_ALIGHMENGT = ERROR_ACCESS_RIGHTS + 1, - ERROR_SMIH, - ERROR_INAVLID_MODE, - ERROR_OPERATION_INPROGRESS, - ERROR_NOT_READY, - ERROR_UNINITIALIZED, - ERROR_BUFFER_FULL, - ERROR_TIMEOUT, - CARD_NOT_READY_OP, - CARD_TYPE_MEMCARD, + ERROR_ACCESS_RIGHTS = 0x2300, + ERROR_ADDR_ALIGHMENGT = ERROR_ACCESS_RIGHTS + 1, + ERROR_SMIH = ERROR_ADDR_ALIGHMENGT + 1, + ERROR_INAVLID_MODE = ERROR_SMIH + 1, + ERROR_OPERATION_INPROGRESS = ERROR_INAVLID_MODE + 1, + ERROR_NOT_READY = ERROR_OPERATION_INPROGRESS + 1, + ERROR_UNINITIALIZED = ERROR_NOT_READY + 1, + ERROR_BUFFER_FULL = ERROR_UNINITIALIZED + 1, + ERROR_TIMEOUT = ERROR_BUFFER_FULL + 1, + CARD_NOT_READY_OP = ERROR_TIMEOUT + 1, + CARD_TYPE_MEMCARD = CARD_NOT_READY_OP + 1, } rsi_error_t; #ifdef __cplusplus diff --git a/components/device/silabs/si91x/mcu/core/chip/inc/si91x_device.h b/components/device/silabs/si91x/mcu/core/chip/inc/si91x_device.h index b451ee286..d8c1de052 100644 --- a/components/device/silabs/si91x/mcu/core/chip/inc/si91x_device.h +++ b/components/device/silabs/si91x/mcu/core/chip/inc/si91x_device.h @@ -105,7 +105,7 @@ typedef enum { #ifdef SLI_SI917B0 NPSS_TO_MCU_SYRTC_INTR_IRQn = 22, /*!< 22 NPSS_TO_MCU_SYSRTC_INTR */ #else - NPSS_TO_MCU_CMP_RF_WKP_INTR_IRQn = 22, /*!< 22 NPSS_TO_MCU_CMP_RF_WKP_INTR */ + NPSS_TO_MCU_CMP_RF_WKP_INTR_IRQn = 22, /*!< 22 NPSS_TO_MCU_CMP_RF_WKP_INTR */ #endif NPSS_TO_MCU_BOD_INTR_IRQn = 23, /*!< 23 NPSS_TO_MCU_BOD_INTR */ NPSS_TO_MCU_BUTTON_INTR_IRQn = 24, /*!< 24 NPSS_TO_MCU_BUTTON_INTR */ @@ -221,24 +221,24 @@ typedef enum { */ typedef struct { union { - __IOM uint32_t PWM_DEADTIME_A; /*!< (@ 0x00000000) PWM deadtime for A and + __IOM unsigned int PWM_DEADTIME_A; /*!< (@ 0x00000000) PWM deadtime for A and channel varies from 0 to 3 */ struct { - __IOM uint32_t DEADTIME_A_CH : 6; /*!< [5..0] Dead time A value to load into dead + __IOM unsigned int DEADTIME_A_CH : 6; /*!< [5..0] Dead time A value to load into dead time counter A of channel0 to channel3 */ - __IOM uint32_t RESERVED1 : 26; /*!< [31..6] reserved1 */ + __IOM unsigned int RESERVED1 : 26; /*!< [31..6] reserved1 */ } PWM_DEADTIME_A_b; }; union { - __IOM uint32_t PWM_DEADTIME_B; /*!< (@ 0x00000004) PWM deadtime for B and + __IOM unsigned int PWM_DEADTIME_B; /*!< (@ 0x00000004) PWM deadtime for B and channel varies from 0 to 3 */ struct { - __IOM uint32_t DEADTIME_B_CH : 6; /*!< [5..0] Dead time B value to load into deadtime + __IOM unsigned int DEADTIME_B_CH : 6; /*!< [5..0] Dead time B value to load into deadtime counter B of channel0 to channel3 */ - __IOM uint32_t RESERVED1 : 26; /*!< [31..6] reserved1 */ + __IOM unsigned int RESERVED1 : 26; /*!< [31..6] reserved1 */ } PWM_DEADTIME_B_b; }; } MCPWM_PWM_DEADTIME_Type; /*!< Size = 8 (0x8) */ @@ -248,130 +248,130 @@ typedef struct { */ typedef struct { union { - __IOM uint32_t INTERRUPT_REG; /*!< (@ 0x00000000) Interrupt Register */ + __IOM unsigned int INTERRUPT_REG; /*!< (@ 0x00000000) Interrupt Register */ struct { - __IOM uint32_t GPDMAC_INT_STAT : 8; /*!< [7..0] Interrupt Status */ - __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + __IOM unsigned int GPDMAC_INT_STAT : 8; /*!< [7..0] Interrupt Status */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ } INTERRUPT_REG_b; }; union { - __IOM uint32_t INTERRUPT_MASK_REG; /*!< (@ 0x00000004) Interrupt Mask Register */ + __IOM unsigned int INTERRUPT_MASK_REG; /*!< (@ 0x00000004) Interrupt Mask Register */ struct { - __IOM uint32_t RESERVED1 : 8; /*!< [7..0] reserved1 */ - __IOM uint32_t LINK_LIST_FETCH_MASK : 8; /*!< [15..8] Linked list fetch done + __IOM unsigned int RESERVED1 : 8; /*!< [7..0] reserved1 */ + __IOM unsigned int LINK_LIST_FETCH_MASK : 8; /*!< [15..8] Linked list fetch done interrupt bit mask control. By default, descriptor fetch done interrupt is masked. */ - __IOM uint32_t TFR_DONE_MASK : 8; /*!< [23..16] Transfer done interrupt + __IOM unsigned int TFR_DONE_MASK : 8; /*!< [23..16] Transfer done interrupt bit mask control. */ - __IOM uint32_t RESERVED2 : 8; /*!< [31..24] reserved2 */ + __IOM unsigned int RESERVED2 : 8; /*!< [31..24] reserved2 */ } INTERRUPT_MASK_REG_b; }; union { - __IOM uint32_t INTERRUPT_STAT_REG; /*!< (@ 0x00000008) Interrupt status register */ + __IOM unsigned int INTERRUPT_STAT_REG; /*!< (@ 0x00000008) Interrupt status register */ struct { - __IOM uint32_t HRESP_ERR0 : 1; /*!< [0..0] DMA error bit */ - __IOM uint32_t LINK_LIST_FETCH_DONE0 : 1; /*!< [1..1] This bit indicates the status + __IOM unsigned int HRESP_ERR0 : 1; /*!< [0..0] DMA error bit */ + __IOM unsigned int LINK_LIST_FETCH_DONE0 : 1; /*!< [1..1] This bit indicates the status of linked list descriptor fetch done for channel 0 */ - __IOM uint32_t TFR_DONE0 : 1; /*!< [2..2] This bit indicates the status of DMA + __IOM unsigned int TFR_DONE0 : 1; /*!< [2..2] This bit indicates the status of DMA transfer done interrupt for channel 0 */ - __IOM uint32_t GPDMAC_ERR0 : 1; /*!< [3..3] transfer size or burst size or + __IOM unsigned int GPDMAC_ERR0 : 1; /*!< [3..3] transfer size or burst size or h size mismatch error */ - __IOM uint32_t HRESP_ERR1 : 1; /*!< [4..4] HRESP error bit */ - __IOM uint32_t LINK_LIST_FETCH_DONE1 : 1; /*!< [5..5] This bit indicates the status + __IOM unsigned int HRESP_ERR1 : 1; /*!< [4..4] HRESP error bit */ + __IOM unsigned int LINK_LIST_FETCH_DONE1 : 1; /*!< [5..5] This bit indicates the status of linked list descriptor fetch done for channel 1 */ - __IOM uint32_t TFR_DONE1 : 1; /*!< [6..6] This bit indicates the status of DMA + __IOM unsigned int TFR_DONE1 : 1; /*!< [6..6] This bit indicates the status of DMA transfer done interrupt for channel 1. */ - __IOM uint32_t GPDMAC_ERR1 : 1; /*!< [7..7] transfer size or burst size or + __IOM unsigned int GPDMAC_ERR1 : 1; /*!< [7..7] transfer size or burst size or h size mismatch error */ - __IOM uint32_t HRESP_ERR2 : 1; /*!< [8..8] HRESP error bit */ - __IOM uint32_t LINK_LIST_FETCH_DONE2 : 1; /*!< [9..9] This bit indicates the status + __IOM unsigned int HRESP_ERR2 : 1; /*!< [8..8] HRESP error bit */ + __IOM unsigned int LINK_LIST_FETCH_DONE2 : 1; /*!< [9..9] This bit indicates the status of linked list descriptor fetch done for channel 2. */ - __IOM uint32_t TFR_DONE2 : 1; /*!< [10..10] This bit indicates the status of DMA + __IOM unsigned int TFR_DONE2 : 1; /*!< [10..10] This bit indicates the status of DMA transfer done interrupt for channel 2. */ - __IOM uint32_t GPDMAC_ERR2 : 1; /*!< [11..11] transfer size or burst size + __IOM unsigned int GPDMAC_ERR2 : 1; /*!< [11..11] transfer size or burst size or h size mismatch error */ - __IOM uint32_t HRESP_ERR3 : 1; /*!< [12..12] HRESP error bit */ - __IOM uint32_t LINK_LIST_FETCH_DONE3 : 1; /*!< [13..13] This bit indicates the status + __IOM unsigned int HRESP_ERR3 : 1; /*!< [12..12] HRESP error bit */ + __IOM unsigned int LINK_LIST_FETCH_DONE3 : 1; /*!< [13..13] This bit indicates the status of linked list descriptor fetch done for channel 3. */ - __IOM uint32_t TFR_DONE3 : 1; /*!< [14..14] This bit indicates the status of DMA + __IOM unsigned int TFR_DONE3 : 1; /*!< [14..14] This bit indicates the status of DMA transfer done interrupt for channel 3. */ - __IOM uint32_t GPDMAC_ERR3 : 1; /*!< [15..15] transfer size or burst size + __IOM unsigned int GPDMAC_ERR3 : 1; /*!< [15..15] transfer size or burst size or h size mismatch error */ - __IOM uint32_t HRESP_ERR4 : 1; /*!< [16..16] HRESP error bit */ - __IOM uint32_t LINK_LIST_FETCH_DONE4 : 1; /*!< [17..17] This bit indicates the status + __IOM unsigned int HRESP_ERR4 : 1; /*!< [16..16] HRESP error bit */ + __IOM unsigned int LINK_LIST_FETCH_DONE4 : 1; /*!< [17..17] This bit indicates the status of linked list descriptor fetch done for channel 4. */ - __IOM uint32_t TFR_DONE4 : 1; /*!< [18..18] This bit indicates the status of DMA + __IOM unsigned int TFR_DONE4 : 1; /*!< [18..18] This bit indicates the status of DMA transfer done interrupt for channel 4. */ - __IOM uint32_t GPDMAC_ERR4 : 1; /*!< [19..19] transfer size or burst size + __IOM unsigned int GPDMAC_ERR4 : 1; /*!< [19..19] transfer size or burst size or h size mismatch error */ - __IOM uint32_t HRESP_ERR5 : 1; /*!< [20..20] HRESP error bit */ - __IOM uint32_t LINK_LIST_FETCH_DONE5 : 1; /*!< [21..21] This bit indicates the status + __IOM unsigned int HRESP_ERR5 : 1; /*!< [20..20] HRESP error bit */ + __IOM unsigned int LINK_LIST_FETCH_DONE5 : 1; /*!< [21..21] This bit indicates the status of linked list descriptor fetch done for channel 5. */ - __IOM uint32_t TFR_DONE5 : 1; /*!< [22..22] This bit indicates the status of DMA + __IOM unsigned int TFR_DONE5 : 1; /*!< [22..22] This bit indicates the status of DMA transfer done interrupt for channel 5. */ - __IOM uint32_t GPDMAC_ERR5 : 1; /*!< [23..23] transfer size or burst size + __IOM unsigned int GPDMAC_ERR5 : 1; /*!< [23..23] transfer size or burst size or h size mismatch error */ - __IM uint32_t HRESP_ERR6 : 1; /*!< [24..24] HRESP error bit */ - __IOM uint32_t LINK_LIST_FETCH_DONE6 : 1; /*!< [25..25] This bit indicates the status + __IM unsigned int HRESP_ERR6 : 1; /*!< [24..24] HRESP error bit */ + __IOM unsigned int LINK_LIST_FETCH_DONE6 : 1; /*!< [25..25] This bit indicates the status of linked list descriptor fetch done for channel 6. */ - __IOM uint32_t TFR_DONE6 : 1; /*!< [26..26] This bit indicates the status of DMA + __IOM unsigned int TFR_DONE6 : 1; /*!< [26..26] This bit indicates the status of DMA transfer done interrupt for channel 6. */ - __IOM uint32_t GPDMAC_ERR6 : 1; /*!< [27..27] transfer size or burst size + __IOM unsigned int GPDMAC_ERR6 : 1; /*!< [27..27] transfer size or burst size or h size mismatch error */ - __IOM uint32_t HRESP_ERR7 : 1; /*!< [28..28] HRESP error bit */ - __IOM uint32_t LINK_LIST_FETCH_DONE7 : 1; /*!< [29..29] This bit indicates the status + __IOM unsigned int HRESP_ERR7 : 1; /*!< [28..28] HRESP error bit */ + __IOM unsigned int LINK_LIST_FETCH_DONE7 : 1; /*!< [29..29] This bit indicates the status of linked list descriptor fetch done for channel 7. */ - __IOM uint32_t TFR_DONE7 : 1; /*!< [30..30] This bit indicates the status of DMA + __IOM unsigned int TFR_DONE7 : 1; /*!< [30..30] This bit indicates the status of DMA transfer done interrupt for channel 7. */ - __IOM uint32_t GPDMAC_ERR7 : 1; /*!< [31..31] transfer size or burst size + __IOM unsigned int GPDMAC_ERR7 : 1; /*!< [31..31] transfer size or burst size or h size mismatch error */ } INTERRUPT_STAT_REG_b; }; union { - __IOM uint32_t DMA_CHNL_ENABLE_REG; /*!< (@ 0x0000000C) This register used + __IOM unsigned int DMA_CHNL_ENABLE_REG; /*!< (@ 0x0000000C) This register used for enable DMA channel */ struct { - __IOM uint32_t CH_ENB : 8; /*!< [7..0] CWhen a bit is set to one, it indicates, + __IOM unsigned int CH_ENB : 8; /*!< [7..0] CWhen a bit is set to one, it indicates, corresponding channel is enabled for dma operation */ - __IM uint32_t RESERVED1 : 24; /*!< [31..8] Reserved1 */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] Reserved1 */ } DMA_CHNL_ENABLE_REG_b; }; union { - __IOM uint32_t DMA_CHNL_SQUASH_REG; /*!< (@ 0x00000010) This register used + __IOM unsigned int DMA_CHNL_SQUASH_REG; /*!< (@ 0x00000010) This register used for enable DMA channel squash */ struct { - __IOM uint32_t CH_DIS : 8; /*!< [7..0] CPU Will be masked to write zeros, + __IOM unsigned int CH_DIS : 8; /*!< [7..0] CPU Will be masked to write zeros, CPU is allowed write 1 only */ - __IM uint32_t RESERVED1 : 24; /*!< [31..8] Reserved1 */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] Reserved1 */ } DMA_CHNL_SQUASH_REG_b; }; union { - __IOM uint32_t DMA_CHNL_LOCK_REG; /*!< (@ 0x00000014) This register used for + __IOM unsigned int DMA_CHNL_LOCK_REG; /*!< (@ 0x00000014) This register used for enable DMA channel squash */ struct { - __IOM uint32_t CHNL_LOCK : 8; /*!< [7..0] When set entire DMA block transfer is done, + __IOM unsigned int CHNL_LOCK : 8; /*!< [7..0] When set entire DMA block transfer is done, before other DMA request is serviced */ - __IM uint32_t RESERVED1 : 24; /*!< [31..8] Reserved1 */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] Reserved1 */ } DMA_CHNL_LOCK_REG_b; }; } GPDMA_G_GLOBAL_Type; /*!< Size = 24 (0x18) */ @@ -381,134 +381,134 @@ typedef struct { */ typedef struct { union { - __IOM uint32_t LINK_LIST_PTR_REGS; /*!< (@ 0x00000000) Link List Register + __IOM unsigned int LINK_LIST_PTR_REGS; /*!< (@ 0x00000000) Link List Register for channel 0 to 7 */ struct { - __IOM uint32_t LINK_LIST_PTR_REG_CHNL : 32; /*!< [31..0] This is the address of the + __IOM unsigned int LINK_LIST_PTR_REG_CHNL : 32; /*!< [31..0] This is the address of the memory location from which we get our next descriptor */ } LINK_LIST_PTR_REGS_b; }; union { - __IOM uint32_t SRC_ADDR_REG_CHNL; /*!< (@ 0x00000004) Source Address + __IOM unsigned int SRC_ADDR_REG_CHNL; /*!< (@ 0x00000004) Source Address Register for channel 0 to 7 */ struct { - __IOM uint32_t SRC_ADDR : 32; /*!< [31..0] This is the address of the memory location + __IOM unsigned int SRC_ADDR : 32; /*!< [31..0] This is the address of the memory location from which we get our next descriptor */ } SRC_ADDR_REG_CHNL_b; }; union { - __IOM uint32_t DEST_ADDR_REG_CHNL; /*!< (@ 0x00000008) Source Address + __IOM unsigned int DEST_ADDR_REG_CHNL; /*!< (@ 0x00000008) Source Address Register for channel 0 to 7 */ struct { - __IOM uint32_t DEST_ADDR : 32; /*!< [31..0] This is the destination + __IOM unsigned int DEST_ADDR : 32; /*!< [31..0] This is the destination address to whih the data is sent */ } DEST_ADDR_REG_CHNL_b; }; union { - __IOM uint32_t CHANNEL_CTRL_REG_CHNL; /*!< (@ 0x0000000C) Channel Control + __IOM unsigned int CHANNEL_CTRL_REG_CHNL; /*!< (@ 0x0000000C) Channel Control Register for channel 0 to 7 */ struct { - __IOM uint32_t DMA_BLK_SIZE : 12; /*!< [11..0] This is data to be transmitted. Loaded + __IOM unsigned int DMA_BLK_SIZE : 12; /*!< [11..0] This is data to be transmitted. Loaded at the beginning of the DMA transfer and decremented at every dma transaction. */ - __IOM uint32_t TRNS_TYPE : 2; /*!< [13..12] DMA transfer type */ - __IOM uint32_t DMA_FLOW_CTRL : 2; /*!< [15..14] DMA flow control */ - __IOM uint32_t MSTR_IF_FETCH_SEL : 1; /*!< [16..16] This selects the MASTER IF from + __IOM unsigned int TRNS_TYPE : 2; /*!< [13..12] DMA transfer type */ + __IOM unsigned int DMA_FLOW_CTRL : 2; /*!< [15..14] DMA flow control */ + __IOM unsigned int MSTR_IF_FETCH_SEL : 1; /*!< [16..16] This selects the MASTER IF from which data to be fetched */ - __IOM uint32_t MSTR_IF_SEND_SEL : 1; /*!< [17..17] This selects the MASTER + __IOM unsigned int MSTR_IF_SEND_SEL : 1; /*!< [17..17] This selects the MASTER IF from which data to be sent */ - __IOM uint32_t DEST_DATA_WIDTH : 2; /*!< [19..18] Data transfer to destination. */ - __IOM uint32_t SRC_DATA_WIDTH : 2; /*!< [21..20] Data transfer from source. */ - __IOM uint32_t SRC_ALIGN : 1; /*!< [22..22] Reserved.Value set to 0 We do not do any + __IOM unsigned int DEST_DATA_WIDTH : 2; /*!< [19..18] Data transfer to destination. */ + __IOM unsigned int SRC_DATA_WIDTH : 2; /*!< [21..20] Data transfer from source. */ + __IOM unsigned int SRC_ALIGN : 1; /*!< [22..22] Reserved.Value set to 0 We do not do any singles. We just do burst, save first 3 bytes in to residue buffer in one cycle, In the next cycle send 4 bytes to fifo, save 3 bytes in to residue. This continues on. */ - __IOM uint32_t LINK_LIST_ON : 1; /*!< [23..23] This mode is set, when we + __IOM unsigned int LINK_LIST_ON : 1; /*!< [23..23] This mode is set, when we do link listed operation */ - __IOM uint32_t LINK_LIST_MSTR_SEL : 1; /*!< [24..24] This mode is set, when we do + __IOM unsigned int LINK_LIST_MSTR_SEL : 1; /*!< [24..24] This mode is set, when we do link listed operation */ - __IOM uint32_t SRC_ADDR_CONTIGUOUS : 1; /*!< [25..25] Indicates Address is + __IOM unsigned int SRC_ADDR_CONTIGUOUS : 1; /*!< [25..25] Indicates Address is contiguous from previous */ - __IOM uint32_t DEST_ADDR_CONTIGUOUS : 1; /*!< [26..26] Indicates Address is + __IOM unsigned int DEST_ADDR_CONTIGUOUS : 1; /*!< [26..26] Indicates Address is contiguous from previous */ - __IOM uint32_t RETRY_ON_ERROR : 1; /*!< [27..27] When this bit is set, if + __IOM unsigned int RETRY_ON_ERROR : 1; /*!< [27..27] When this bit is set, if we recieve HRESPERR, We will retry the DMA for that channel. */ - __IOM uint32_t LINK_INTERRUPT : 1; /*!< [28..28] This bit is set in link list + __IOM unsigned int LINK_INTERRUPT : 1; /*!< [28..28] This bit is set in link list descriptor.Hard ware will send an interrupt when the DMA transfer is done for the corresponding link list address */ - __IOM uint32_t SRC_FIFO_MODE : 1; /*!< [29..29] If set to 1; source address will not + __IOM unsigned int SRC_FIFO_MODE : 1; /*!< [29..29] If set to 1; source address will not be incremented(means fifo mode for source) */ - __IOM uint32_t DEST_FIFO_MODE : 1; /*!< [30..30] If set to 1; destination address + __IOM unsigned int DEST_FIFO_MODE : 1; /*!< [30..30] If set to 1; destination address will not be incremented(means fifo mode for destination) */ - __IM uint32_t RESERVED1 : 1; /*!< [31..31] Reserved1 */ + __IM unsigned int RESERVED1 : 1; /*!< [31..31] Reserved1 */ } CHANNEL_CTRL_REG_CHNL_b; }; union { - __IOM uint32_t MISC_CHANNEL_CTRL_REG_CHNL; /*!< (@ 0x00000010) Misc Channel Control + __IOM unsigned int MISC_CHANNEL_CTRL_REG_CHNL; /*!< (@ 0x00000010) Misc Channel Control Register for channel 0 */ struct { - __IOM uint32_t AHB_BURST_SIZE : 3; /*!< [2..0] Burst size */ - __IOM uint32_t DEST_DATA_BURST : 6; /*!< [8..3] Burst writes in beats to + __IOM unsigned int AHB_BURST_SIZE : 3; /*!< [2..0] Burst size */ + __IOM unsigned int DEST_DATA_BURST : 6; /*!< [8..3] Burst writes in beats to destination.(000000-64 beats .....111111-63 beats) */ - __IOM uint32_t SRC_DATA_BURST : 6; /*!< [14..9] Burst writes in beats from + __IOM unsigned int SRC_DATA_BURST : 6; /*!< [14..9] Burst writes in beats from source(000000-64 beats .....111111-63 beats) */ - __IOM uint32_t DEST_CHNL_ID : 6; /*!< [20..15] This is the destination channel Id to + __IOM unsigned int DEST_CHNL_ID : 6; /*!< [20..15] This is the destination channel Id to which the data is sent. Must be set up prior to DMA_CHANNEL_ENABLE */ __IOM - uint32_t SRC_CHNL_ID : 6; /*!< [26..21] This is the source channel Id, + unsigned int SRC_CHNL_ID : 6; /*!< [26..21] This is the source channel Id, from which the data is fetched. must be set up prior to DMA_CHANNEL_ENABLE */ - __IOM uint32_t DMA_PROT : 3; /*!< [29..27] Protection level to go with the data. It + __IOM unsigned int DMA_PROT : 3; /*!< [29..27] Protection level to go with the data. It will be concatenated with 1 b1 as there will be no opcode fetching and directly assign to hprot in AHB interface */ - __IOM uint32_t MEM_FILL_ENABLE : 1; /*!< [30..30] Enable for memory + __IOM unsigned int MEM_FILL_ENABLE : 1; /*!< [30..30] Enable for memory filling with either 1s or 0s. */ - __IOM uint32_t MEM_ONE_FILL : 1; /*!< [31..31] Select for memory filling + __IOM unsigned int MEM_ONE_FILL : 1; /*!< [31..31] Select for memory filling with either 1s or 0s. */ } MISC_CHANNEL_CTRL_REG_CHNL_b; }; union { - __IOM uint32_t FIFO_CONFIG_REGS; /*!< (@ 0x00000014) FIFO Configuration + __IOM unsigned int FIFO_CONFIG_REGS; /*!< (@ 0x00000014) FIFO Configuration Register for channel 1 */ struct { - __IOM uint32_t FIFO_STRT_ADDR : 6; /*!< [5..0] Starting row address of channel */ - __IOM uint32_t FIFO_SIZE : 6; /*!< [11..6] Channel size */ - __IM uint32_t RESERVED1 : 20; /*!< [31..12] Reserved1 */ + __IOM unsigned int FIFO_STRT_ADDR : 6; /*!< [5..0] Starting row address of channel */ + __IOM unsigned int FIFO_SIZE : 6; /*!< [11..6] Channel size */ + __IM unsigned int RESERVED1 : 20; /*!< [31..12] Reserved1 */ } FIFO_CONFIG_REGS_b; }; union { - __IOM uint32_t PRIORITY_CHNL_REGS; /*!< (@ 0x00000018) Priority Register for + __IOM unsigned int PRIORITY_CHNL_REGS; /*!< (@ 0x00000018) Priority Register for channel 0 to 7 */ struct { - __IOM uint32_t PRIORITY_CH : 2; /*!< [1..0] Set a value between 2 b00 to 2 b11. The + __IOM unsigned int PRIORITY_CH : 2; /*!< [1..0] Set a value between 2 b00 to 2 b11. The channel having highest number is the highest priority channel. */ - __IM uint32_t RESERVED1 : 30; /*!< [31..2] Reserved1 */ + __IM unsigned int RESERVED1 : 30; /*!< [31..2] Reserved1 */ } PRIORITY_CHNL_REGS_b; }; - __IM uint32_t RESERVED[57]; + __IM unsigned int RESERVED[57]; } GPDMA_C_CHANNEL_CONFIG_Type; /*!< Size = 256 (0x100) */ /** @@ -516,33 +516,33 @@ typedef struct { */ typedef struct { union { - __IOM uint32_t MCUULP_TMR_MATCH; /*!< (@ 0x00000000) Timer Match Register */ + __IOM unsigned int MCUULP_TMR_MATCH; /*!< (@ 0x00000000) Timer Match Register */ struct { - __IOM uint32_t TMR_MATCH : 32; /*!< [31..0] This bits are used to program the lower + __IOM unsigned int TMR_MATCH : 32; /*!< [31..0] This bits are used to program the lower significant 16-bits of timer time out value in millisecond or number of system clocks */ } MCUULP_TMR_MATCH_b; }; union { - __IOM uint32_t MCUULP_TMR_CNTRL; /*!< (@ 0x00000004) Timer Control Register */ + __IOM unsigned int MCUULP_TMR_CNTRL; /*!< (@ 0x00000004) Timer Control Register */ struct { - __OM uint32_t TMR_START : 1; /*!< [0..0] This Bit are Used to start the timer timer + __OM unsigned int TMR_START : 1; /*!< [0..0] This Bit are Used to start the timer timer gets reset upon setting this bit */ - __OM uint32_t TMR_INTR_CLR : 1; /*!< [1..1] This Bit are Used to clear the + __OM unsigned int TMR_INTR_CLR : 1; /*!< [1..1] This Bit are Used to clear the timer */ - __IOM uint32_t TMR_INTR_ENABLE : 1; /*!< [2..2] This Bit are Used to + __IOM unsigned int TMR_INTR_ENABLE : 1; /*!< [2..2] This Bit are Used to enable the time out interrupt */ - __IOM uint32_t TMR_TYPE : 2; /*!< [4..3] This Bit are Used to select the + __IOM unsigned int TMR_TYPE : 2; /*!< [4..3] This Bit are Used to select the type of timer */ - __IOM uint32_t TMR_MODE : 1; /*!< [5..5] This Bit are Used to select the + __IOM unsigned int TMR_MODE : 1; /*!< [5..5] This Bit are Used to select the mode working of timer */ - __OM uint32_t TMR_STOP : 1; /*!< [6..6] This Bit are Used to stop the timer */ - __IOM uint32_t COUNTER_UP : 1; /*!< [7..7] For reading/tracking counter in + __OM unsigned int TMR_STOP : 1; /*!< [6..6] This Bit are Used to stop the timer */ + __IOM unsigned int COUNTER_UP : 1; /*!< [7..7] For reading/tracking counter in up counting this bit has to be set */ - __IOM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + __IOM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ } MCUULP_TMR_CNTRL_b; }; } TIMERS_MATCH_CTRL_Type; /*!< Size = 8 (0x8) */ @@ -553,183 +553,183 @@ typedef struct { typedef struct { union { union { - __IM uint32_t I2S_LRBR; /*!< (@ 0x00000000) Left Receive Buffer Register */ + __IM unsigned int I2S_LRBR; /*!< (@ 0x00000000) Left Receive Buffer Register */ struct { - __IM uint32_t LRBR : 24; /*!< [23..0] Data received serially from the + __IM unsigned int LRBR : 24; /*!< [23..0] Data received serially from the received channel input */ - __IM uint32_t RESERVED1 : 8; /*!< [31..24] Reserved for future use */ + __IM unsigned int RESERVED1 : 8; /*!< [31..24] Reserved for future use */ } I2S_LRBR_b; }; union { - __OM uint32_t I2S_LTHR; /*!< (@ 0x00000000) Left Receive Buffer Register */ + __OM unsigned int I2S_LTHR; /*!< (@ 0x00000000) Left Receive Buffer Register */ struct { - __OM uint32_t LTHR : 24; /*!< [23..0] The Left Stereo Data to be transmitted + __OM unsigned int LTHR : 24; /*!< [23..0] The Left Stereo Data to be transmitted serially from the Transmitted channel output */ - __OM uint32_t RESERVED1 : 8; /*!< [31..24] Reserved for future use */ + __OM unsigned int RESERVED1 : 8; /*!< [31..24] Reserved for future use */ } I2S_LTHR_b; }; }; union { union { - __IM uint32_t I2S_RRBR; /*!< (@ 0x00000004) Right Receive Buffer Register */ + __IM unsigned int I2S_RRBR; /*!< (@ 0x00000004) Right Receive Buffer Register */ struct { - __IM uint32_t RRBR : 24; /*!< [23..0] The Right Stereo Data received serially from + __IM unsigned int RRBR : 24; /*!< [23..0] The Right Stereo Data received serially from the received channel input through this register */ - __IM uint32_t RESERVED1 : 8; /*!< [31..24] Reserved for future use */ + __IM unsigned int RESERVED1 : 8; /*!< [31..24] Reserved for future use */ } I2S_RRBR_b; }; union { - __OM uint32_t I2S_RTHR; /*!< (@ 0x00000004) Right Transmit Holding Register */ + __OM unsigned int I2S_RTHR; /*!< (@ 0x00000004) Right Transmit Holding Register */ struct { - __OM uint32_t RTHR : 24; /*!< [23..0] The Right Stereo Data to be transmitted + __OM unsigned int RTHR : 24; /*!< [23..0] The Right Stereo Data to be transmitted serially from the Transmit channel output written through this register */ - __OM uint32_t RESERVED1 : 8; /*!< [31..24] Reserved for future use */ + __OM unsigned int RESERVED1 : 8; /*!< [31..24] Reserved for future use */ } I2S_RTHR_b; }; }; union { - __IOM uint32_t I2S_RER; /*!< (@ 0x00000008) Receive Enable Register */ + __IOM unsigned int I2S_RER; /*!< (@ 0x00000008) Receive Enable Register */ struct { - __IOM uint32_t RXCHEN : 1; /*!< [0..0] This Bit enables/disables a receive channel + __IOM unsigned int RXCHEN : 1; /*!< [0..0] This Bit enables/disables a receive channel independently of all other channels */ - __IOM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + __IOM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */ } I2S_RER_b; }; union { - __IOM uint32_t I2S_TER; /*!< (@ 0x0000000C) Transmit Enable Register */ + __IOM unsigned int I2S_TER; /*!< (@ 0x0000000C) Transmit Enable Register */ struct { - __IOM uint32_t TXCHEN : 1; /*!< [0..0] This Bit enables/disables a transmit channel + __IOM unsigned int TXCHEN : 1; /*!< [0..0] This Bit enables/disables a transmit channel independently of all other channels */ - __IOM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + __IOM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */ } I2S_TER_b; }; union { - __IOM uint32_t I2S_RCR; /*!< (@ 0x00000010) Receive Configuration Register */ + __IOM unsigned int I2S_RCR; /*!< (@ 0x00000010) Receive Configuration Register */ struct { - __IOM uint32_t WLEN : 3; /*!< [2..0] This Bits are used to program the desired data + __IOM unsigned int WLEN : 3; /*!< [2..0] This Bits are used to program the desired data resolution of the receiver and enables LSB of the incoming left or right word */ - __IOM uint32_t RESERVED1 : 29; /*!< [31..3] Reserved for future use */ + __IOM unsigned int RESERVED1 : 29; /*!< [31..3] Reserved for future use */ } I2S_RCR_b; }; union { - __IOM uint32_t I2S_TCR; /*!< (@ 0x00000014) Transmit Configuration Register */ + __IOM unsigned int I2S_TCR; /*!< (@ 0x00000014) Transmit Configuration Register */ struct { - __IOM uint32_t WLEN : 3; /*!< [2..0] This Bits are used to program the desired data + __IOM unsigned int WLEN : 3; /*!< [2..0] This Bits are used to program the desired data resolution of the transmitter and ensure that MSB of the data is transmitted first. */ - __IOM uint32_t RESERVED1 : 29; /*!< [31..3] Reserved for future use */ + __IOM unsigned int RESERVED1 : 29; /*!< [31..3] Reserved for future use */ } I2S_TCR_b; }; union { - __IM uint32_t I2S_ISR; /*!< (@ 0x00000018) Interrupt Status Register */ + __IM unsigned int I2S_ISR; /*!< (@ 0x00000018) Interrupt Status Register */ struct { - __IM uint32_t RXDA : 1; /*!< [0..0] Receive Data Available */ - __IM uint32_t RXFO : 1; /*!< [1..1] Receive Data FIFO */ - __IM uint32_t RESERVED1 : 2; /*!< [3..2] Reserved for future use */ - __IM uint32_t TXFE : 1; /*!< [4..4] Transmit FIFO Empty */ - __IM uint32_t TXFO : 1; /*!< [5..5] Transmit FIFO */ - __IM uint32_t RESERVED2 : 26; /*!< [31..6] Reserved for future use */ + __IM unsigned int RXDA : 1; /*!< [0..0] Receive Data Available */ + __IM unsigned int RXFO : 1; /*!< [1..1] Receive Data FIFO */ + __IM unsigned int RESERVED1 : 2; /*!< [3..2] Reserved for future use */ + __IM unsigned int TXFE : 1; /*!< [4..4] Transmit FIFO Empty */ + __IM unsigned int TXFO : 1; /*!< [5..5] Transmit FIFO */ + __IM unsigned int RESERVED2 : 26; /*!< [31..6] Reserved for future use */ } I2S_ISR_b; }; union { - __IOM uint32_t I2S_IMR; /*!< (@ 0x0000001C) Interrupt Mask Register */ + __IOM unsigned int I2S_IMR; /*!< (@ 0x0000001C) Interrupt Mask Register */ struct { - __IOM uint32_t RXDAM : 1; /*!< [0..0] RX Data Available Mask Interrupt */ - __IOM uint32_t RXFOM : 1; /*!< [1..1] RX FIFO Overrun Mask Interrupt */ - __IOM uint32_t RESERVED1 : 2; /*!< [3..2] Reserved for future use */ - __IOM uint32_t TXFEM : 1; /*!< [4..4] TX FIFO Empty Interrupt */ - __IOM uint32_t TXFOM : 1; /*!< [5..5] TX FIFO Overrun Interrupt */ - __IOM uint32_t RESERVED2 : 26; /*!< [31..6] Reserved for future use */ + __IOM unsigned int RXDAM : 1; /*!< [0..0] RX Data Available Mask Interrupt */ + __IOM unsigned int RXFOM : 1; /*!< [1..1] RX FIFO Overrun Mask Interrupt */ + __IOM unsigned int RESERVED1 : 2; /*!< [3..2] Reserved for future use */ + __IOM unsigned int TXFEM : 1; /*!< [4..4] TX FIFO Empty Interrupt */ + __IOM unsigned int TXFOM : 1; /*!< [5..5] TX FIFO Overrun Interrupt */ + __IOM unsigned int RESERVED2 : 26; /*!< [31..6] Reserved for future use */ } I2S_IMR_b; }; union { - __IM uint32_t I2S_ROR; /*!< (@ 0x00000020) Receive Overrun Register */ + __IM unsigned int I2S_ROR; /*!< (@ 0x00000020) Receive Overrun Register */ struct { - __IM uint32_t RXCHO : 1; /*!< [0..0] Read this bit to clear the RX FIFO + __IM unsigned int RXCHO : 1; /*!< [0..0] Read this bit to clear the RX FIFO data overrun interrupt */ - __IM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */ } I2S_ROR_b; }; union { - __IM uint32_t I2S_TOR; /*!< (@ 0x00000024) Transmit Overrun Register */ + __IM unsigned int I2S_TOR; /*!< (@ 0x00000024) Transmit Overrun Register */ struct { - __IM uint32_t TXCHO : 1; /*!< [0..0] Read this bit to clear the TX FIFO + __IM unsigned int TXCHO : 1; /*!< [0..0] Read this bit to clear the TX FIFO data overrun interrupt */ - __IM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */ } I2S_TOR_b; }; union { - __IOM uint32_t I2S_RFCR; /*!< (@ 0x00000028) Receive FIFO Configuration Register0 */ + __IOM unsigned int I2S_RFCR; /*!< (@ 0x00000028) Receive FIFO Configuration Register0 */ struct { - __IOM uint32_t RXCHDT : 4; /*!< [3..0] This bits program the trigger level in the RX + __IOM unsigned int RXCHDT : 4; /*!< [3..0] This bits program the trigger level in the RX FIFO at which the data available interrupt is generated */ - __IOM uint32_t RESERVED1 : 28; /*!< [31..4] Reserved for future use */ + __IOM unsigned int RESERVED1 : 28; /*!< [31..4] Reserved for future use */ } I2S_RFCR_b; }; union { - __IOM uint32_t I2S_TXFCR; /*!< (@ 0x0000002C) Transmit FIFO Configuration Register */ + __IOM unsigned int I2S_TXFCR; /*!< (@ 0x0000002C) Transmit FIFO Configuration Register */ struct { __IOM - uint32_t TXCHET : 4; /*!< [3..0] This bits program the trigger level + unsigned int TXCHET : 4; /*!< [3..0] This bits program the trigger level in the TX FIFO at which the Empty Threshold Reached interrupt is generated */ - __IM uint32_t RESERVED1 : 28; /*!< [31..4] Reserved for future use */ + __IM unsigned int RESERVED1 : 28; /*!< [31..4] Reserved for future use */ } I2S_TXFCR_b; }; union { - __OM uint32_t I2S_RFF; /*!< (@ 0x00000030) Receive FIFO Flush */ + __OM unsigned int I2S_RFF; /*!< (@ 0x00000030) Receive FIFO Flush */ struct { - __OM uint32_t RXCHFR : 1; /*!< [0..0] Writing a 1 to this register flushes an + __OM unsigned int RXCHFR : 1; /*!< [0..0] Writing a 1 to this register flushes an individual RX FIFO RX channel or block must be disable prior to writing to this bit */ - __OM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + __OM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */ } I2S_RFF_b; }; union { - __OM uint32_t I2S_TFF; /*!< (@ 0x00000034) Transmit FIFO Flush */ + __OM unsigned int I2S_TFF; /*!< (@ 0x00000034) Transmit FIFO Flush */ struct { - __OM uint32_t TXCHFR : 1; /*!< [0..0] Writing a 1 to this register flushes an + __OM unsigned int TXCHFR : 1; /*!< [0..0] Writing a 1 to this register flushes an individual TX FIFO TX channel or block must be disable prior to writing to this bit */ - __OM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + __OM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */ } I2S_TFF_b; }; - __IM uint32_t RSVD0; /*!< (@ 0x00000038) none */ - __IM uint32_t RSVD1; /*!< (@ 0x0000003C) none */ + __IM unsigned int RSVD0; /*!< (@ 0x00000038) none */ + __IM unsigned int RSVD1; /*!< (@ 0x0000003C) none */ } I2S0_CHANNEL_CONFIG_Type; /*!< Size = 64 (0x40) */ /** @@ -737,51 +737,51 @@ typedef struct { */ typedef struct { union { - __IOM uint32_t GPIO_CONFIG_REG; /*!< (@ 0x00000000) GPIO Configuration Register */ + __IOM unsigned int GPIO_CONFIG_REG; /*!< (@ 0x00000000) GPIO Configuration Register */ struct { - __IOM uint32_t DIRECTION : 1; /*!< [0..0] Direction of the GPIO pin */ - __IOM uint32_t PORTMASK : 1; /*!< [1..1] Port mask value */ - __IOM uint32_t MODE : 4; /*!< [5..2] GPIO Pin Mode Used for GPIO Pin Muxing */ - __IOM uint32_t RESERVED1 : 2; /*!< [7..6] Reserved1 */ - __IOM uint32_t GROUP_INTERRUPT1_ENABLE : 1; /*!< [8..8] When set, the corresponding + __IOM unsigned int DIRECTION : 1; /*!< [0..0] Direction of the GPIO pin */ + __IOM unsigned int PORTMASK : 1; /*!< [1..1] Port mask value */ + __IOM unsigned int MODE : 4; /*!< [5..2] GPIO Pin Mode Used for GPIO Pin Muxing */ + __IOM unsigned int RESERVED1 : 2; /*!< [7..6] Reserved1 */ + __IOM unsigned int GROUP_INTERRUPT1_ENABLE : 1; /*!< [8..8] When set, the corresponding GPIO is pin is selected for group intr 1 generation */ - __IOM uint32_t GROUP_INTERRUPT1_POLARITY : 1; /*!< [9..9] Decides the active value of + __IOM unsigned int GROUP_INTERRUPT1_POLARITY : 1; /*!< [9..9] Decides the active value of the pin to be considered for group interrupt 1 generation */ - __IOM uint32_t GROUP_INTERRUPT2_ENABLE : 1; /*!< [10..10] When set, the corresponding + __IOM unsigned int GROUP_INTERRUPT2_ENABLE : 1; /*!< [10..10] When set, the corresponding GPIO is pin is selected for group intr 2 generation */ - __IOM uint32_t GROUP_INTERRUPT2_POLARITY : 1; /*!< [11..11] Decides the active value + __IOM unsigned int GROUP_INTERRUPT2_POLARITY : 1; /*!< [11..11] Decides the active value of the pin to be considered for group interrupt 2 generation */ - __IOM uint32_t RESERVED2 : 4; /*!< [15..12] Reserved2 */ - __IOM uint32_t RESERVED3 : 16; /*!< [31..16] Reserved3 */ + __IOM unsigned int RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM unsigned int RESERVED3 : 16; /*!< [31..16] Reserved3 */ } GPIO_CONFIG_REG_b; }; union { - __IOM uint32_t BIT_LOAD_REG; /*!< (@ 0x00000004) Bit Load */ + __IOM unsigned int BIT_LOAD_REG; /*!< (@ 0x00000004) Bit Load */ struct { - __IOM uint32_t BIT_LOAD : 1; /*!< [0..0] Loads 0th bit on to the pin on write. And + __IOM unsigned int BIT_LOAD : 1; /*!< [0..0] Loads 0th bit on to the pin on write. And reads the value on pin on read into 0th bit */ - __IOM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved1 */ + __IOM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved1 */ } BIT_LOAD_REG_b; }; union { - __IOM uint32_t WORD_LOAD_REG; /*!< (@ 0x00000008) Word Load */ + __IOM unsigned int WORD_LOAD_REG; /*!< (@ 0x00000008) Word Load */ struct { - __IOM uint32_t WORD_LOAD : 16; /*!< [15..0] Loads 1 on the pin when any of the bit in + __IOM unsigned int WORD_LOAD : 16; /*!< [15..0] Loads 1 on the pin when any of the bit in load value is 1. On read pass the bit status into all bits. */ - __IOM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved1 */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved1 */ } WORD_LOAD_REG_b; }; - __IM uint32_t RESERVED; + __IM unsigned int RESERVED; } EGPIO_PIN_CONFIG_Type; /*!< Size = 16 (0x10) */ /** @@ -789,66 +789,66 @@ typedef struct { */ typedef struct { union { - __IOM uint32_t PORT_LOAD_REG; /*!< (@ 0x00000000) Port Load */ + __IOM unsigned int PORT_LOAD_REG; /*!< (@ 0x00000000) Port Load */ struct { - __IOM uint32_t PORT_LOAD : 16; /*!< [15..0] Loads the value on to pin on write. And + __IOM unsigned int PORT_LOAD : 16; /*!< [15..0] Loads the value on to pin on write. And reads the value of load register on read */ - __IM uint32_t RES : 16; /*!< [31..16] RES */ + __IM unsigned int RES : 16; /*!< [31..16] RES */ } PORT_LOAD_REG_b; }; union { - __OM uint32_t PORT_SET_REG; /*!< (@ 0x00000004) Port Set Register */ + __OM unsigned int PORT_SET_REG; /*!< (@ 0x00000004) Port Set Register */ struct { - __OM uint32_t PORT_SET : 16; /*!< [15..0] Sets the pin when corresponding bit is + __OM unsigned int PORT_SET : 16; /*!< [15..0] Sets the pin when corresponding bit is high. Writing zero has no effect. */ - __OM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved1 */ + __OM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved1 */ } PORT_SET_REG_b; }; union { - __OM uint32_t PORT_CLEAR_REG; /*!< (@ 0x00000008) Port Clear Register */ + __OM unsigned int PORT_CLEAR_REG; /*!< (@ 0x00000008) Port Clear Register */ struct { - __OM uint32_t PORT_CLEAR : 16; /*!< [15..0] Clears the pin when corresponding bit is + __OM unsigned int PORT_CLEAR : 16; /*!< [15..0] Clears the pin when corresponding bit is high. Writing zero has no effect. */ - __OM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved1 */ + __OM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved1 */ } PORT_CLEAR_REG_b; }; union { - __OM uint32_t PORT_MASKED_LOAD_REG; /*!< (@ 0x0000000C) Port Masked Load Register */ + __OM unsigned int PORT_MASKED_LOAD_REG; /*!< (@ 0x0000000C) Port Masked Load Register */ struct { - __OM uint32_t PORT_MASKED_LOAD : 16; /*!< [15..0] Only loads into pins which are not + __OM unsigned int PORT_MASKED_LOAD : 16; /*!< [15..0] Only loads into pins which are not masked. On read, pass only status unmasked pins */ - __OM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved1 */ + __OM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved1 */ } PORT_MASKED_LOAD_REG_b; }; union { - __OM uint32_t PORT_TOGGLE_REG; /*!< (@ 0x00000010) Port Toggle Register */ + __OM unsigned int PORT_TOGGLE_REG; /*!< (@ 0x00000010) Port Toggle Register */ struct { - __OM uint32_t PORT_TOGGLE : 16; /*!< [15..0] Toggles the pin when corresponding bit + __OM unsigned int PORT_TOGGLE : 16; /*!< [15..0] Toggles the pin when corresponding bit is high. Writing zero has not effect. */ - __OM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved1 */ + __OM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved1 */ } PORT_TOGGLE_REG_b; }; union { - __IM uint32_t PORT_READ_REG; /*!< (@ 0x00000014) Port Read Register */ + __IM unsigned int PORT_READ_REG; /*!< (@ 0x00000014) Port Read Register */ struct { - __IM uint32_t PORT_READ : 16; /*!< [15..0] Reads the value on GPIO pins + __IM unsigned int PORT_READ : 16; /*!< [15..0] Reads the value on GPIO pins irrespective of the pin mode. */ - __IM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved1 */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved1 */ } PORT_READ_REG_b; }; - __IM uint32_t RESERVED[2]; + __IM unsigned int RESERVED[2]; } EGPIO_PORT_CONFIG_Type; /*!< Size = 32 (0x20) */ /** @@ -856,42 +856,42 @@ typedef struct { */ typedef struct { union { - __IOM uint32_t GPIO_INTR_CTRL; /*!< (@ 0x00000000) GPIO Interrupt Control Register */ + __IOM unsigned int GPIO_INTR_CTRL; /*!< (@ 0x00000000) GPIO Interrupt Control Register */ struct { - __IOM uint32_t LEVEL_HIGH_ENABLE : 1; /*!< [0..0] enables interrupt generation when + __IOM unsigned int LEVEL_HIGH_ENABLE : 1; /*!< [0..0] enables interrupt generation when pin level is 1 */ - __IOM uint32_t LEVEL_LOW_ENABLE : 1; /*!< [1..1] enables interrupt generation when + __IOM unsigned int LEVEL_LOW_ENABLE : 1; /*!< [1..1] enables interrupt generation when pin level is 0 */ - __IOM uint32_t RISE_EDGE_ENABLE : 1; /*!< [2..2] enables interrupt generation when + __IOM unsigned int RISE_EDGE_ENABLE : 1; /*!< [2..2] enables interrupt generation when rising edge is detected on pin */ - __IOM uint32_t FALL_EDGE_ENABLE : 1; /*!< [3..3] enables interrupt generation when + __IOM unsigned int FALL_EDGE_ENABLE : 1; /*!< [3..3] enables interrupt generation when Falling edge is detected on pin */ - __IOM uint32_t MASK : 1; /*!< [4..4] Masks the interrupt. Interrupt will still be + __IOM unsigned int MASK : 1; /*!< [4..4] Masks the interrupt. Interrupt will still be seen in status register when enabled */ - __IOM uint32_t RESERVED1 : 3; /*!< [7..5] Reserved1 */ - __IOM uint32_t PIN_NUMBER : 4; /*!< [11..8] GPIO Pin to be chosen for + __IOM unsigned int RESERVED1 : 3; /*!< [7..5] Reserved1 */ + __IOM unsigned int PIN_NUMBER : 4; /*!< [11..8] GPIO Pin to be chosen for interrupt generation */ - __IOM uint32_t PORT_NUMBER : 2; /*!< [13..12] GPIO Port to be chosen for + __IOM unsigned int PORT_NUMBER : 2; /*!< [13..12] GPIO Port to be chosen for interrupt generation */ - __IOM uint32_t RESERVED2 : 18; /*!< [31..14] Reserved2 */ + __IOM unsigned int RESERVED2 : 18; /*!< [31..14] Reserved2 */ } GPIO_INTR_CTRL_b; }; union { - __IOM uint32_t GPIO_INTR_STATUS; /*!< (@ 0x00000004) GPIO Interrupt Status + __IOM unsigned int GPIO_INTR_STATUS; /*!< (@ 0x00000004) GPIO Interrupt Status Register */ struct { - __IOM uint32_t INTERRUPT_STATUS : 1; /*!< [0..0] Gets set when interrupt + __IOM unsigned int INTERRUPT_STATUS : 1; /*!< [0..0] Gets set when interrupt is enabled and occurs. */ - __IOM uint32_t RISE_EDGE_STATUS : 1; /*!< [1..1] Gets set when rise edge + __IOM unsigned int RISE_EDGE_STATUS : 1; /*!< [1..1] Gets set when rise edge is enabled and occurs. */ - __IOM uint32_t FALL_EDGE_STATUS : 1; /*!< [2..2] Gets set when Fall edge + __IOM unsigned int FALL_EDGE_STATUS : 1; /*!< [2..2] Gets set when Fall edge is enabled and occurs. */ - __OM uint32_t MASK_SET : 1; /*!< [3..3] Mask set */ - __OM uint32_t MASK_CLEAR : 1; /*!< [4..4] Mask Clear */ - __IOM uint32_t RESERVED1 : 27; /*!< [31..5] Reserved1 */ + __OM unsigned int MASK_SET : 1; /*!< [3..3] Mask set */ + __OM unsigned int MASK_CLEAR : 1; /*!< [4..4] Mask Clear */ + __IOM unsigned int RESERVED1 : 27; /*!< [31..5] Reserved1 */ } GPIO_INTR_STATUS_b; }; } EGPIO_INTR_Type; /*!< Size = 8 (0x8) */ @@ -901,37 +901,37 @@ typedef struct { */ typedef struct { union { - __IOM uint32_t GPIO_GRP_INTR_CTRL_REG; /*!< (@ 0x00000000) GPIO Interrupt 0 + __IOM unsigned int GPIO_GRP_INTR_CTRL_REG; /*!< (@ 0x00000000) GPIO Interrupt 0 Control Register */ struct { - __IOM uint32_t AND_OR : 1; /*!< [0..0] AND/OR */ - __IOM uint32_t LEVEL_EDGE : 1; /*!< [1..1] Level/Edge */ - __IOM uint32_t ENABLE_WAKEUP : 1; /*!< [2..2] For wakeup generation, actual pin + __IOM unsigned int AND_OR : 1; /*!< [0..0] AND/OR */ + __IOM unsigned int LEVEL_EDGE : 1; /*!< [1..1] Level/Edge */ + __IOM unsigned int ENABLE_WAKEUP : 1; /*!< [2..2] For wakeup generation, actual pin status has to be seen(before double ranking point) */ - __IOM uint32_t ENABLE_INTERRUPT : 1; /*!< [3..3] Enable Interrupt */ - __IOM uint32_t MASK : 1; /*!< [4..4] Mask */ - __IOM uint32_t RESERVED1 : 27; /*!< [31..5] Reserved1 */ + __IOM unsigned int ENABLE_INTERRUPT : 1; /*!< [3..3] Enable Interrupt */ + __IOM unsigned int MASK : 1; /*!< [4..4] Mask */ + __IOM unsigned int RESERVED1 : 27; /*!< [31..5] Reserved1 */ } GPIO_GRP_INTR_CTRL_REG_b; }; union { - __IOM uint32_t GPIO_GRP_INTR_STS; /*!< (@ 0x00000004) GPIO Interrupt 0 + __IOM unsigned int GPIO_GRP_INTR_STS; /*!< (@ 0x00000004) GPIO Interrupt 0 Status Register */ struct { - __IOM uint32_t INTERRUPT_STATUS : 1; /*!< [0..0] Interrupt status is available in + __IOM unsigned int INTERRUPT_STATUS : 1; /*!< [0..0] Interrupt status is available in this bit when interrupt is enabled and generated. When 1 is written, interrupt gets cleared. */ - __IM uint32_t WAKEUP : 1; /*!< [1..1] Double ranked version of wakeup. + __IM unsigned int WAKEUP : 1; /*!< [1..1] Double ranked version of wakeup. Gets set when wakeup is enabled and occurs. When 1 is written it gets cleared */ - __IOM uint32_t RESERVED1 : 1; /*!< [2..2] Reserved1 */ - __IOM uint32_t MASK_SET : 1; /*!< [3..3] Gives zero on read */ - __IOM uint32_t MASK_CLEAR : 1; /*!< [4..4] Gives zero on read */ - __IOM uint32_t RESERVED2 : 27; /*!< [31..5] Reserved2 */ + __IOM unsigned int RESERVED1 : 1; /*!< [2..2] Reserved1 */ + __IOM unsigned int MASK_SET : 1; /*!< [3..3] Gives zero on read */ + __IOM unsigned int MASK_CLEAR : 1; /*!< [4..4] Gives zero on read */ + __IOM unsigned int RESERVED2 : 27; /*!< [31..5] Reserved2 */ } GPIO_GRP_INTR_STS_b; }; } EGPIO_GPIO_GRP_INTR_Type; /*!< Size = 8 (0x8) */ @@ -941,22 +941,22 @@ typedef struct { */ typedef struct { union { - __IOM uint32_t NPSS_GPIO_CTRLS; /*!< (@ 0x00000000) NPSS GPIO Control register */ + __IOM unsigned int NPSS_GPIO_CTRLS; /*!< (@ 0x00000000) NPSS GPIO Control register */ struct { - __IOM uint32_t NPSS_GPIO_MODE : 3; /*!< [2..0] NPSS GPIO 0 mode select. */ - __IOM uint32_t NPSS_GPIO_REN : 1; /*!< [3..3] NPSS GPIO 0 Input Buffer + __IOM unsigned int NPSS_GPIO_MODE : 3; /*!< [2..0] NPSS GPIO 0 mode select. */ + __IOM unsigned int NPSS_GPIO_REN : 1; /*!< [3..3] NPSS GPIO 0 Input Buffer Enable. 1- Enable 0- Disable. */ - __IOM uint32_t NPSS_GPIO_OEN : 1; /*!< [4..4] NPSS GPIO 0 Output Buffer Enable. 1- + __IOM unsigned int NPSS_GPIO_OEN : 1; /*!< [4..4] NPSS GPIO 0 Output Buffer Enable. 1- Input Direction 0- Output Direction. */ - __IOM uint32_t NPSS_GPIO_OUT : 1; /*!< [5..5] NPSS GPIO 0 Output value. */ - __IOM uint32_t RESERVED1 : 2; /*!< [7..6] Reserved1 */ - __IOM uint32_t NPSS_GPIO_POLARITY : 1; /*!< [8..8] NPSS GPIO 0 Polarity 1 + __IOM unsigned int NPSS_GPIO_OUT : 1; /*!< [5..5] NPSS GPIO 0 Output value. */ + __IOM unsigned int RESERVED1 : 2; /*!< [7..6] Reserved1 */ + __IOM unsigned int NPSS_GPIO_POLARITY : 1; /*!< [8..8] NPSS GPIO 0 Polarity 1 - When signal is High 0 - When signal is Ligh. */ - __IOM uint32_t RESERVED2 : 7; /*!< [15..9] Reserved2 */ - __IOM uint32_t USE_ULPSS_PAD : 1; /*!< [16..16] Input from ULPSS GPIOs. */ - __IOM uint32_t RESERVED3 : 15; /*!< [31..17] Reserved3 */ + __IOM unsigned int RESERVED2 : 7; /*!< [15..9] Reserved2 */ + __IOM unsigned int USE_ULPSS_PAD : 1; /*!< [16..16] Input from ULPSS GPIOs. */ + __IOM unsigned int RESERVED3 : 15; /*!< [31..17] Reserved3 */ } NPSS_GPIO_CTRLS_b; }; } MCU_RET_NPSS_GPIO_CNTRL_Type; /*!< Size = 4 (0x4) */ @@ -966,12 +966,12 @@ typedef struct { */ typedef struct { union { - __IOM uint32_t ULP_SOC_GPIO_MODE_REG; /*!< (@ 0x00000000) ulp soc gpio mode + __IOM unsigned int ULP_SOC_GPIO_MODE_REG; /*!< (@ 0x00000000) ulp soc gpio mode register */ struct { - __IOM uint32_t ULP_SOC_GPIO_MODE_REG : 3; /*!< [2..0] mode bits for soc gpio. */ - __IOM uint32_t RESERVED1 : 29; /*!< [31..3] reserved1 */ + __IOM unsigned int ULP_SOC_GPIO_MODE_REG : 3; /*!< [2..0] mode bits for soc gpio. */ + __IOM unsigned int RESERVED1 : 29; /*!< [31..3] reserved1 */ } ULP_SOC_GPIO_MODE_REG_b; }; } ULPCLK_ULP_SOC_GPIO_MODE_REG_Type; /*!< Size = 4 (0x4) */ @@ -982,43 +982,43 @@ typedef struct { */ typedef struct { union { - __IOM uint32_t ADC_CH_BIT_MAP_CONFIG_0; /*!< (@ 0x00000000) This is configuration + __IOM unsigned int ADC_CH_BIT_MAP_CONFIG_0; /*!< (@ 0x00000000) This is configuration register0 to explain the bit map for ADC channels */ struct { - __IOM uint32_t CHANNEL_BITMAP : 32; /*!< [31..0] ADC Channels bit map */ + __IOM unsigned int CHANNEL_BITMAP : 32; /*!< [31..0] ADC Channels bit map */ } ADC_CH_BIT_MAP_CONFIG_0_b; }; union { - __IOM uint32_t ADC_CH_BIT_MAP_CONFIG_1; /*!< (@ 0x00000004) This is configuration + __IOM unsigned int ADC_CH_BIT_MAP_CONFIG_1; /*!< (@ 0x00000004) This is configuration register1 to explain the bit map for ADC channels */ struct { - __IOM uint32_t CHANNEL_BITMAP : 32; /*!< [31..0] ADC Channels bit map */ + __IOM unsigned int CHANNEL_BITMAP : 32; /*!< [31..0] ADC Channels bit map */ } ADC_CH_BIT_MAP_CONFIG_1_b; }; union { - __IOM uint32_t ADC_CH_BIT_MAP_CONFIG_2; /*!< (@ 0x00000008) This is configuration + __IOM unsigned int ADC_CH_BIT_MAP_CONFIG_2; /*!< (@ 0x00000008) This is configuration register2 to explain the bit map for ADC channels */ struct { - __IOM uint32_t CHANNEL_BITMAP : 32; /*!< [31..0] ADC Channels bit map */ + __IOM unsigned int CHANNEL_BITMAP : 32; /*!< [31..0] ADC Channels bit map */ } ADC_CH_BIT_MAP_CONFIG_2_b; }; union { - __IOM uint32_t ADC_CH_BIT_MAP_CONFIG_3; /*!< (@ 0x0000000C) This is configuration + __IOM unsigned int ADC_CH_BIT_MAP_CONFIG_3; /*!< (@ 0x0000000C) This is configuration register3 to explain the bit map for ADC channels */ struct { - __IOM uint32_t CHANNEL_BITMAP : 5; /*!< [4..0] ADC Channels bit map */ - __IOM uint32_t RESERVED1 : 27; /*!< [31..5] Reserved1 */ + __IOM unsigned int CHANNEL_BITMAP : 5; /*!< [4..0] ADC Channels bit map */ + __IOM unsigned int RESERVED1 : 27; /*!< [31..5] Reserved1 */ } ADC_CH_BIT_MAP_CONFIG_3_b; }; } AUX_ADC_DAC_COMP_ADC_CH_BIT_MAP_CONFIG_Type; /*!< Size = 16 (0x10) */ @@ -1052,797 +1052,797 @@ typedef struct { typedef struct { /*!< (@ 0x44010000) I2C0 Structure */ union { - __IOM uint32_t IC_CON; /*!< (@ 0x00000000) This register can be written only + __IOM unsigned int IC_CON; /*!< (@ 0x00000000) This register can be written only when the i2c is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect. */ struct { - __IOM uint32_t MASTER_MODE : 1; /*!< [0..0] This bit controls whether the + __IOM unsigned int MASTER_MODE : 1; /*!< [0..0] This bit controls whether the I2C master is enabled. */ - __IOM uint32_t SPEED : 2; /*!< [2..1] These bits control at which speed + __IOM unsigned int SPEED : 2; /*!< [2..1] These bits control at which speed the I2C operates. Hardware protects against illegal values being programmed by software. */ - __IOM uint32_t IC_10BITADDR_SLAVE : 1; /*!< [3..3] When acting as a slave, + __IOM unsigned int IC_10BITADDR_SLAVE : 1; /*!< [3..3] When acting as a slave, this bit controls whether the I2C responds to 7- or 10-bit addresses. */ - __IM uint32_t IC_10BITADDR_MASTER_RD_ONLY : 1; /*!< [4..4] the function of this bit + __IM unsigned int IC_10BITADDR_MASTER_RD_ONLY : 1; /*!< [4..4] the function of this bit is handled by bit 12 of IC_TAR register, and becomes a read-only copy called IC_10BITADDR_MASTER_rd_onl */ - __IOM uint32_t IC_RESTART_EN : 1; /*!< [5..5] Determines whether RESTART conditions + __IOM unsigned int IC_RESTART_EN : 1; /*!< [5..5] Determines whether RESTART conditions may be sent when acting as a master */ - __IOM uint32_t IC_SLAVE_DISABLE : 1; /*!< [6..6] This bit controls whether + __IOM unsigned int IC_SLAVE_DISABLE : 1; /*!< [6..6] This bit controls whether I2C has its slave disabled */ - __IOM uint32_t STOP_DET_IFADDRESSED : 1; /*!< [7..7] The STOP DETECTION interrupt is + __IOM unsigned int STOP_DET_IFADDRESSED : 1; /*!< [7..7] The STOP DETECTION interrupt is generated only when the transmitted address matches the slave address of SAR */ - __IOM uint32_t TX_EMPTY_CTRL : 1; /*!< [8..8] This bit controls the + __IOM unsigned int TX_EMPTY_CTRL : 1; /*!< [8..8] This bit controls the generation of the TX EMPTY interrupt, as described in the IC RAW INTR STAT register. */ - __IM uint32_t RESERVED1 : 1; /*!< [9..9] reserved1 */ - __IOM uint32_t STOP_DET_IF_MASTER_ACTIVE : 1; /*!< [10..10] In Master mode. */ - __IOM uint32_t BUS_CLEAR_FEATURE_CTRL : 1; /*!< [11..11] In Master mode. */ - __IOM uint32_t RESERVED2 : 20; /*!< [31..12] reserved2 */ + __IM unsigned int RESERVED1 : 1; /*!< [9..9] reserved1 */ + __IOM unsigned int STOP_DET_IF_MASTER_ACTIVE : 1; /*!< [10..10] In Master mode. */ + __IOM unsigned int BUS_CLEAR_FEATURE_CTRL : 1; /*!< [11..11] In Master mode. */ + __IOM unsigned int RESERVED2 : 20; /*!< [31..12] reserved2 */ } IC_CON_b; }; union { - __IOM uint32_t IC_TAR; /*!< (@ 0x00000004) I2C Target Address Register */ + __IOM unsigned int IC_TAR; /*!< (@ 0x00000004) I2C Target Address Register */ struct { - __IOM uint32_t IC_TAR : 10; /*!< [9..0] This is the target address for any + __IOM unsigned int IC_TAR : 10; /*!< [9..0] This is the target address for any master transaction */ - __IOM uint32_t GC_OR_START : 1; /*!< [10..10] If bit 11 (SPECIAL) is set + __IOM unsigned int GC_OR_START : 1; /*!< [10..10] If bit 11 (SPECIAL) is set to 1, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c */ - __IOM uint32_t SPECIAL : 1; /*!< [11..11] This bit indicates whether software + __IOM unsigned int SPECIAL : 1; /*!< [11..11] This bit indicates whether software performs a General Call or START BYTE command */ - __IOM uint32_t IC_10BITADDR_MASTER : 1; /*!< [12..12] This bit controls + __IOM unsigned int IC_10BITADDR_MASTER : 1; /*!< [12..12] This bit controls whether the i2c starts its transfers in 7-or 10-bit addressing mode when acting as a master */ - __IOM uint32_t DEVICE_ID : 1; /*!< [13..13] If bit 11 (SPECIAL) is set to 1, then + __IOM unsigned int DEVICE_ID : 1; /*!< [13..13] If bit 11 (SPECIAL) is set to 1, then this bit indicates whether a Device-ID of a particular slave mentioned in IC_TAR[6:0] is to be performed by the I2C Master */ - __IM uint32_t RESERVED1 : 18; /*!< [31..14] reserved1 */ + __IM unsigned int RESERVED1 : 18; /*!< [31..14] reserved1 */ } IC_TAR_b; }; union { - __IOM uint32_t IC_SAR; /*!< (@ 0x00000008) I2C Slave Address Register */ + __IOM unsigned int IC_SAR; /*!< (@ 0x00000008) I2C Slave Address Register */ struct { - __IOM uint32_t IC_SAR : 10; /*!< [9..0] The IC_SAR holds the slave address when the + __IOM unsigned int IC_SAR : 10; /*!< [9..0] The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used. */ - __IM uint32_t RESERVED1 : 22; /*!< [31..10] reserved1 */ + __IM unsigned int RESERVED1 : 22; /*!< [31..10] reserved1 */ } IC_SAR_b; }; union { - __IOM uint32_t IC_HS_MADDR; /*!< (@ 0x0000000C) I2C High Speed Master Mode + __IOM unsigned int IC_HS_MADDR; /*!< (@ 0x0000000C) I2C High Speed Master Mode Code Address Register */ struct { - __IOM uint32_t IC_HS_MAR : 3; /*!< [2..0] This bit field holds the value + __IOM unsigned int IC_HS_MAR : 3; /*!< [2..0] This bit field holds the value of the I2C HS mode master code */ - __IM uint32_t RESERVED1 : 29; /*!< [31..3] reserved1 */ + __IM unsigned int RESERVED1 : 29; /*!< [31..3] reserved1 */ } IC_HS_MADDR_b; }; union { - __IOM uint32_t IC_DATA_CMD; /*!< (@ 0x00000010) I2C Rx/Tx Data Buffer and + __IOM unsigned int IC_DATA_CMD; /*!< (@ 0x00000010) I2C Rx/Tx Data Buffer and Command Register */ struct { - __IOM uint32_t DAT : 8; /*!< [7..0] This register contains the data to be + __IOM unsigned int DAT : 8; /*!< [7..0] This register contains the data to be transmitted or received on the I2C bus */ - __OM uint32_t CMD : 1; /*!< [8..8] This bit controls whether a read or a + __OM unsigned int CMD : 1; /*!< [8..8] This bit controls whether a read or a write is performed */ - __OM uint32_t STOP : 1; /*!< [9..9] This bit controls whether a STOP is + __OM unsigned int STOP : 1; /*!< [9..9] This bit controls whether a STOP is issued after the byte is sent or received */ - __OM uint32_t RESTART : 1; /*!< [10..10] This bit controls whether a RESTART is + __OM unsigned int RESTART : 1; /*!< [10..10] This bit controls whether a RESTART is issued before the byte is sent or received */ - __IM uint32_t FIRST_DATA_BYTE : 1; /*!< [11..11] Indicates the first data byte + __IM unsigned int FIRST_DATA_BYTE : 1; /*!< [11..11] Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode */ - __IM uint32_t RESERVED1 : 20; /*!< [31..12] reserved1 */ + __IM unsigned int RESERVED1 : 20; /*!< [31..12] reserved1 */ } IC_DATA_CMD_b; }; union { - __IOM uint32_t IC_SS_SCL_HCNT; /*!< (@ 0x00000014) Standard Speed I2C Clock + __IOM unsigned int IC_SS_SCL_HCNT; /*!< (@ 0x00000014) Standard Speed I2C Clock SCL High Count Register */ struct { - __IOM uint32_t IC_SS_SCL_HCNT : 16; /*!< [15..0] This register must be set before any + __IOM unsigned int IC_SS_SCL_HCNT : 16; /*!< [15..0] This register must be set before any I2C bus transaction can take place to ensure proper I/O timing */ - __IM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ } IC_SS_SCL_HCNT_b; }; union { - __IOM uint32_t IC_SS_SCL_LCNT; /*!< (@ 0x00000018) Standard Speed I2C Clock + __IOM unsigned int IC_SS_SCL_LCNT; /*!< (@ 0x00000018) Standard Speed I2C Clock SCL Low Count Register */ struct { - __IOM uint32_t IC_SS_SCL_LCNT : 16; /*!< [15..0] This register must be set before any + __IOM unsigned int IC_SS_SCL_LCNT : 16; /*!< [15..0] This register must be set before any I2C bus transaction can take place to ensure proper I/O timing */ - __IM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ } IC_SS_SCL_LCNT_b; }; union { - __IOM uint32_t IC_FS_SCL_HCNT; /*!< (@ 0x0000001C) Fast Speed I2C Clock SCL + __IOM unsigned int IC_FS_SCL_HCNT; /*!< (@ 0x0000001C) Fast Speed I2C Clock SCL High Count Register */ struct { - __IOM uint32_t IC_FS_SCL_HCNT : 16; /*!< [15..0] This register must be set before any + __IOM unsigned int IC_FS_SCL_HCNT : 16; /*!< [15..0] This register must be set before any I2C bus transaction can take place to ensure proper I/O timing */ - __IM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ } IC_FS_SCL_HCNT_b; }; union { - __IOM uint32_t IC_FS_SCL_LCNT; /*!< (@ 0x00000020) Fast Speed I2C Clock SCL + __IOM unsigned int IC_FS_SCL_LCNT; /*!< (@ 0x00000020) Fast Speed I2C Clock SCL Low Count Register */ struct { - __IOM uint32_t IC_FS_SCL_LCNT : 16; /*!< [15..0] This register must be set before any + __IOM unsigned int IC_FS_SCL_LCNT : 16; /*!< [15..0] This register must be set before any I2C bus transaction can take place to ensure proper I/O timing */ - __IM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ } IC_FS_SCL_LCNT_b; }; union { - __IOM uint32_t IC_HS_SCL_HCNT; /*!< (@ 0x00000024) High Speed I2C Clock SCL + __IOM unsigned int IC_HS_SCL_HCNT; /*!< (@ 0x00000024) High Speed I2C Clock SCL High Count Register */ struct { - __IOM uint32_t IC_HS_SCL_HCNT : 16; /*!< [15..0] This register must be set before any + __IOM unsigned int IC_HS_SCL_HCNT : 16; /*!< [15..0] This register must be set before any I2C bus transaction can take place to ensure proper I/O timing */ - __IM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ } IC_HS_SCL_HCNT_b; }; union { - __IOM uint32_t IC_HS_SCL_LCNT; /*!< (@ 0x00000028) High Speed I2C Clock SCL + __IOM unsigned int IC_HS_SCL_LCNT; /*!< (@ 0x00000028) High Speed I2C Clock SCL Low Count Register */ struct { - __IOM uint32_t IC_HS_SCL_LCNT : 16; /*!< [15..0] This register must be set before any + __IOM unsigned int IC_HS_SCL_LCNT : 16; /*!< [15..0] This register must be set before any I2C bus transaction can take place to ensure proper I/O timing */ - __IM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ } IC_HS_SCL_LCNT_b; }; union { - __IM uint32_t IC_INTR_STAT; /*!< (@ 0x0000002C) I2C Interrupt Status Register */ + __IM unsigned int IC_INTR_STAT; /*!< (@ 0x0000002C) I2C Interrupt Status Register */ struct { - __IM uint32_t R_RX_UNDER : 1; /*!< [0..0] Set if the processor attempts to + __IM unsigned int R_RX_UNDER : 1; /*!< [0..0] Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register */ - __IM uint32_t R_RX_OVER : 1; /*!< [1..1] Set if the receive buffer is completely + __IM unsigned int R_RX_OVER : 1; /*!< [1..1] Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device */ - __IM uint32_t R_RX_FULL : 1; /*!< [2..2] Set when the receive buffer + __IM unsigned int R_RX_FULL : 1; /*!< [2..2] Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. */ - __IM uint32_t R_TX_OVER : 1; /*!< [3..3] Set during transmit if the + __IM unsigned int R_TX_OVER : 1; /*!< [3..3] Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. */ - __IM uint32_t R_TX_EMPTY : 1; /*!< [4..4] This bit is set to 1 when the transmit + __IM unsigned int R_TX_EMPTY : 1; /*!< [4..4] This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. */ - __IM uint32_t R_RD_REQ : 1; /*!< [5..5] This bit is set to 1 when DW_apb_i2c is + __IM unsigned int R_RD_REQ : 1; /*!< [5..5] This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. */ - __IM uint32_t R_TX_ABRT : 1; /*!< [6..6] This bit indicates if DW_apb_i2c, as an I2C + __IM unsigned int R_TX_ABRT : 1; /*!< [6..6] This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO */ - __IM uint32_t R_RX_DONE : 1; /*!< [7..7] When the DW_apb_i2c is acting as a + __IM unsigned int R_RX_DONE : 1; /*!< [7..7] When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte */ - __IM uint32_t R_ACTIVITY : 1; /*!< [8..8] This bit captures DW_apb_i2c activity and + __IM unsigned int R_ACTIVITY : 1; /*!< [8..8] This bit captures DW_apb_i2c activity and stays set until it is cleared */ - __IM uint32_t R_STOP_DET : 1; /*!< [9..9] Indicates whether a STOP + __IM unsigned int R_STOP_DET : 1; /*!< [9..9] Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. */ - __IM uint32_t R_START_DET : 1; /*!< [10..10] Indicates whether a START or + __IM unsigned int R_START_DET : 1; /*!< [10..10] Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. */ - __IM uint32_t R_GEN_CALL : 1; /*!< [11..11] Set only when a General Call address is + __IM unsigned int R_GEN_CALL : 1; /*!< [11..11] Set only when a General Call address is received and it is acknowledged */ - __IM uint32_t R_RESTART_DET : 1; /*!< [12..12] Indicates whether a RESTART condition + __IM unsigned int R_RESTART_DET : 1; /*!< [12..12] Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in slave mode and the slave is the addressed slave */ - __IM uint32_t R_MST_ON_HOLD : 1; /*!< [13..13] Indicates whether a master is holding + __IM unsigned int R_MST_ON_HOLD : 1; /*!< [13..13] Indicates whether a master is holding the bus and the Tx FIFO is empty. */ - __IM uint32_t M_SCL_STUCK_AT_LOW : 1; /*!< [14..14] Indicates whether the + __IM unsigned int M_SCL_STUCK_AT_LOW : 1; /*!< [14..14] Indicates whether the SCL Line is stuck at low for the IC_SCL_STUCK_LOW_TIMOUT number of ic_clk periods */ - __IM uint32_t RESERVED1 : 17; /*!< [31..15] reserved1 */ + __IM unsigned int RESERVED1 : 17; /*!< [31..15] reserved1 */ } IC_INTR_STAT_b; }; union { - __IOM uint32_t IC_INTR_MASK; /*!< (@ 0x00000030) I2C Interrupt Mask Register */ + __IOM unsigned int IC_INTR_MASK; /*!< (@ 0x00000030) I2C Interrupt Mask Register */ struct { - __IOM uint32_t M_RX_UNDER : 1; /*!< [0..0] This bit mask their + __IOM unsigned int M_RX_UNDER : 1; /*!< [0..0] This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. */ - __IOM uint32_t M_RX_OVER : 1; /*!< [1..1] This bit mask their corresponding interrupt + __IOM unsigned int M_RX_OVER : 1; /*!< [1..1] This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. */ - __IOM uint32_t M_RX_FULL : 1; /*!< [2..2] This bit mask their corresponding interrupt + __IOM unsigned int M_RX_FULL : 1; /*!< [2..2] This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. */ - __IOM uint32_t M_TX_OVER : 1; /*!< [3..3] This bit mask their corresponding interrupt + __IOM unsigned int M_TX_OVER : 1; /*!< [3..3] This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register */ - __IOM uint32_t M_TX_EMPTY : 1; /*!< [4..4] This bit mask their + __IOM unsigned int M_TX_EMPTY : 1; /*!< [4..4] This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. */ - __IOM uint32_t M_RD_REQ : 1; /*!< [5..5] This bit mask their corresponding interrupt + __IOM unsigned int M_RD_REQ : 1; /*!< [5..5] This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. */ - __IOM uint32_t M_TX_ABRT : 1; /*!< [6..6] This bit mask their corresponding interrupt + __IOM unsigned int M_TX_ABRT : 1; /*!< [6..6] This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. */ - __IOM uint32_t M_RX_DONE : 1; /*!< [7..7] This bit mask their corresponding interrupt + __IOM unsigned int M_RX_DONE : 1; /*!< [7..7] This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. */ - __IOM uint32_t M_ACTIVITY : 1; /*!< [8..8] This bit mask their + __IOM unsigned int M_ACTIVITY : 1; /*!< [8..8] This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. */ - __IOM uint32_t M_STOP_DET : 1; /*!< [9..9] This bit mask their + __IOM unsigned int M_STOP_DET : 1; /*!< [9..9] This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. */ - __IOM uint32_t M_START_DET : 1; /*!< [10..10] This bit mask their corresponding + __IOM unsigned int M_START_DET : 1; /*!< [10..10] This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. */ - __IOM uint32_t M_GEN_CALL : 1; /*!< [11..11] This bit mask their + __IOM unsigned int M_GEN_CALL : 1; /*!< [11..11] This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. */ - __IOM uint32_t M_RESTART_DET : 1; /*!< [12..12] Indicates whether a RESTART condition + __IOM unsigned int M_RESTART_DET : 1; /*!< [12..12] Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in slave mode and the slave is the addressed slave */ - __IOM uint32_t M_MST_ON_HOLD : 1; /*!< [13..13] Indicates whether a master is holding + __IOM unsigned int M_MST_ON_HOLD : 1; /*!< [13..13] Indicates whether a master is holding the bus and the Tx FIFO is empty. */ - __IOM uint32_t M_SCL_STUCK_AT_LOW : 1; /*!< [14..14] Indicates whether the + __IOM unsigned int M_SCL_STUCK_AT_LOW : 1; /*!< [14..14] Indicates whether the SCL Line is stuck at low for the IC_SCL_STUCK_LOW_TIMOUT number of ic_clk periods */ - __IM uint32_t RESERVED1 : 17; /*!< [31..15] reserved1 */ + __IM unsigned int RESERVED1 : 17; /*!< [31..15] reserved1 */ } IC_INTR_MASK_b; }; union { - __IM uint32_t IC_RAW_INTR_STAT; /*!< (@ 0x00000034) I2C Raw Interrupt Status + __IM unsigned int IC_RAW_INTR_STAT; /*!< (@ 0x00000034) I2C Raw Interrupt Status Register */ struct { - __IM uint32_t RX_UNDER : 1; /*!< [0..0] Set if the processor attempts to read the + __IM unsigned int RX_UNDER : 1; /*!< [0..0] Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register */ - __IM uint32_t RX_OVER : 1; /*!< [1..1] Set if the receive buffer is completely + __IM unsigned int RX_OVER : 1; /*!< [1..1] Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device */ - __IM uint32_t RX_FULL : 1; /*!< [2..2] Set when the receive buffer reaches + __IM unsigned int RX_FULL : 1; /*!< [2..2] Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. */ - __IM uint32_t TX_OVER : 1; /*!< [3..3] Set during transmit if the transmit buffer is + __IM unsigned int TX_OVER : 1; /*!< [3..3] Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. */ - __IM uint32_t TX_EMPTY : 1; /*!< [4..4] This bit is set to 1 when the + __IM unsigned int TX_EMPTY : 1; /*!< [4..4] This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. */ - __IM uint32_t RD_REQ : 1; /*!< [5..5] This bit is set to 1 when DW_apb_i2c is acting + __IM unsigned int RD_REQ : 1; /*!< [5..5] This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. */ - __IM uint32_t TX_ABRT : 1; /*!< [6..6] This bit indicates if DW_apb_i2c, as an I2C + __IM unsigned int TX_ABRT : 1; /*!< [6..6] This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO */ - __IM uint32_t RX_DONE : 1; /*!< [7..7] When the DW_apb_i2c is acting as a + __IM unsigned int RX_DONE : 1; /*!< [7..7] When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte */ - __IM uint32_t ACTIVITY : 1; /*!< [8..8] This bit captures DW_apb_i2c activity and + __IM unsigned int ACTIVITY : 1; /*!< [8..8] This bit captures DW_apb_i2c activity and stays set until it is cleared */ - __IM uint32_t STOP_DET : 1; /*!< [9..9] Indicates whether a STOP condition has + __IM unsigned int STOP_DET : 1; /*!< [9..9] Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. */ - __IM uint32_t START_DET : 1; /*!< [10..10] Indicates whether a START or RESTART + __IM unsigned int START_DET : 1; /*!< [10..10] Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. */ - __IM uint32_t GEN_CALL : 1; /*!< [11..11] Set only when a General Call address is + __IM unsigned int GEN_CALL : 1; /*!< [11..11] Set only when a General Call address is received and it is acknowledged */ - __IM uint32_t RESTART_DET : 1; /*!< [12..12] Indicates whether a RESTART condition + __IM unsigned int RESTART_DET : 1; /*!< [12..12] Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in slave mode and the slave is the addressed slave */ - __IM uint32_t MST_ON_HOLD : 1; /*!< [13..13] Indicates whether a master is holding + __IM unsigned int MST_ON_HOLD : 1; /*!< [13..13] Indicates whether a master is holding the bus and the Tx FIFO is empty. */ - __IM uint32_t SCL_STUCK_AT_LOW : 1; /*!< [14..14] Indicates whether the + __IM unsigned int SCL_STUCK_AT_LOW : 1; /*!< [14..14] Indicates whether the SCL Line is stuck at low for the IC_SCL_STUCK_LOW_TIMOUT number of ic_clk periods */ - __IM uint32_t RESERVED1 : 17; /*!< [31..15] reserved1 */ + __IM unsigned int RESERVED1 : 17; /*!< [31..15] reserved1 */ } IC_RAW_INTR_STAT_b; }; union { - __IOM uint32_t IC_RX_TL; /*!< (@ 0x00000038) I2C Receive FIFO Threshold Register */ + __IOM unsigned int IC_RX_TL; /*!< (@ 0x00000038) I2C Receive FIFO Threshold Register */ struct { - __IOM uint32_t RX_TL : 8; /*!< [7..0] Receive FIFO Threshold Level */ - __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + __IOM unsigned int RX_TL : 8; /*!< [7..0] Receive FIFO Threshold Level */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ } IC_RX_TL_b; }; union { - __IOM uint32_t IC_TX_TL; /*!< (@ 0x0000003C) I2C Transmit FIFO Threshold Register */ + __IOM unsigned int IC_TX_TL; /*!< (@ 0x0000003C) I2C Transmit FIFO Threshold Register */ struct { - __IOM uint32_t TX_TL : 8; /*!< [7..0] Transmit FIFO Threshold Level */ - __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + __IOM unsigned int TX_TL : 8; /*!< [7..0] Transmit FIFO Threshold Level */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ } IC_TX_TL_b; }; union { - __IM uint32_t IC_CLR_INTR; /*!< (@ 0x00000040) Clear Combined and Individual + __IM unsigned int IC_CLR_INTR; /*!< (@ 0x00000040) Clear Combined and Individual Interrupt Register */ struct { - __IM uint32_t CLR_INTR : 1; /*!< [0..0] Read this register to clear the combined + __IM unsigned int CLR_INTR : 1; /*!< [0..0] Read this register to clear the combined interrupt, all individual interrupts, and the IC_TXABRT_SOURCE register */ - __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ } IC_CLR_INTR_b; }; union { - __IM uint32_t IC_CLR_RX_UNDER; /*!< (@ 0x00000044) Clear RX_UNDER Interrupt + __IM unsigned int IC_CLR_RX_UNDER; /*!< (@ 0x00000044) Clear RX_UNDER Interrupt Register */ struct { - __IM uint32_t CLR_RX_UNDER : 1; /*!< [0..0] Read this register to clear + __IM unsigned int CLR_RX_UNDER : 1; /*!< [0..0] Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register. */ - __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ } IC_CLR_RX_UNDER_b; }; union { - __IM uint32_t IC_CLR_RX_OVER; /*!< (@ 0x00000048) Clear RX_OVER Interrupt + __IM unsigned int IC_CLR_RX_OVER; /*!< (@ 0x00000048) Clear RX_OVER Interrupt Register */ struct { - __IM uint32_t CLR_RX_OVER : 1; /*!< [0..0] Read this register to clear the + __IM unsigned int CLR_RX_OVER : 1; /*!< [0..0] Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register */ - __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ } IC_CLR_RX_OVER_b; }; union { - __IM uint32_t IC_CLR_TX_OVER; /*!< (@ 0x0000004C) Clear TX_OVER Interrupt + __IM unsigned int IC_CLR_TX_OVER; /*!< (@ 0x0000004C) Clear TX_OVER Interrupt Register */ struct { - __IM uint32_t CLR_TX_OVER : 1; /*!< [0..0] Read this register to clear the + __IM unsigned int CLR_TX_OVER : 1; /*!< [0..0] Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register. */ - __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ } IC_CLR_TX_OVER_b; }; union { - __IM uint32_t IC_CLR_RD_REQ; /*!< (@ 0x00000050) Clear RD_REQ Interrupt Register */ + __IM unsigned int IC_CLR_RD_REQ; /*!< (@ 0x00000050) Clear RD_REQ Interrupt Register */ struct { - __IM uint32_t CLR_RD_REQ : 1; /*!< [0..0] Read this register to clear the + __IM unsigned int CLR_RD_REQ : 1; /*!< [0..0] Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register. */ - __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ } IC_CLR_RD_REQ_b; }; union { - __IM uint32_t IC_CLR_TX_ABRT; /*!< (@ 0x00000054) Clear TX_ABRT Interrupt + __IM unsigned int IC_CLR_TX_ABRT; /*!< (@ 0x00000054) Clear TX_ABRT Interrupt Register */ struct { - __IM uint32_t CLR_TX_ABRT : 1; /*!< [0..0] Read this register to clear the TX_ABRT + __IM unsigned int CLR_TX_ABRT : 1; /*!< [0..0] Read this register to clear the TX_ABRT interrupt (bit 6) of the C_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register */ - __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ } IC_CLR_TX_ABRT_b; }; union { - __IM uint32_t IC_CLR_RX_DONE; /*!< (@ 0x00000058) Clear RX_DONE Interrupt + __IM unsigned int IC_CLR_RX_DONE; /*!< (@ 0x00000058) Clear RX_DONE Interrupt Register */ struct { - __IM uint32_t CLR_RX_DONE : 1; /*!< [0..0] Read this register to clear the + __IM unsigned int CLR_RX_DONE : 1; /*!< [0..0] Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register */ - __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ } IC_CLR_RX_DONE_b; }; union { - __IM uint32_t IC_CLR_ACTIVITY; /*!< (@ 0x0000005C) Clear ACTIVITY Interrupt + __IM unsigned int IC_CLR_ACTIVITY; /*!< (@ 0x0000005C) Clear ACTIVITY Interrupt Register */ struct { - __IM uint32_t CLR_ACTIVITY : 1; /*!< [0..0] Reading this register clears + __IM unsigned int CLR_ACTIVITY : 1; /*!< [0..0] Reading this register clears the ACTIVITY interrupt if the I2C is not active any more */ - __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ } IC_CLR_ACTIVITY_b; }; union { - __IM uint32_t IC_CLR_STOP_DET; /*!< (@ 0x00000060) Clear STOP_DET Interrupt + __IM unsigned int IC_CLR_STOP_DET; /*!< (@ 0x00000060) Clear STOP_DET Interrupt Register */ struct { - __IM uint32_t CLR_STOP_DET : 1; /*!< [0..0] Read this register to clear + __IM unsigned int CLR_STOP_DET : 1; /*!< [0..0] Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register. */ - __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ } IC_CLR_STOP_DET_b; }; union { - __IM uint32_t IC_CLR_START_DET; /*!< (@ 0x00000064) Clear START_DET + __IM unsigned int IC_CLR_START_DET; /*!< (@ 0x00000064) Clear START_DET Interrupt Register */ struct { - __IM uint32_t CLR_START_DET : 1; /*!< [0..0] Read this register to clear + __IM unsigned int CLR_START_DET : 1; /*!< [0..0] Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register */ - __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ } IC_CLR_START_DET_b; }; union { - __IM uint32_t IC_CLR_GEN_CALL; /*!< (@ 0x00000068) Clear GEN_CALL Interrupt + __IM unsigned int IC_CLR_GEN_CALL; /*!< (@ 0x00000068) Clear GEN_CALL Interrupt Register */ struct { - __IM uint32_t CLR_GEN_CALL : 1; /*!< [0..0] Read this register to clear + __IM unsigned int CLR_GEN_CALL : 1; /*!< [0..0] Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register */ - __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ } IC_CLR_GEN_CALL_b; }; union { - __IOM uint32_t IC_ENABLE; /*!< (@ 0x0000006C) Clear GEN_CALL Interrupt Register */ + __IOM unsigned int IC_ENABLE; /*!< (@ 0x0000006C) Clear GEN_CALL Interrupt Register */ struct { - __IOM uint32_t EN : 1; /*!< [0..0] Controls whether the DW_apb_i2c is enabled */ - __IOM uint32_t ABORT : 1; /*!< [1..1] When set, the controller initiates + __IOM unsigned int EN : 1; /*!< [0..0] Controls whether the DW_apb_i2c is enabled */ + __IOM unsigned int ABORT : 1; /*!< [1..1] When set, the controller initiates the transfer abort */ - __IOM uint32_t TX_CMD_BLOCK : 1; /*!< [2..2] none */ - __IOM uint32_t SDA_STUCK_RECOVERY_ENABLE : 1; /*!< [3..3] SDA STUCK + __IOM unsigned int TX_CMD_BLOCK : 1; /*!< [2..2] none */ + __IOM unsigned int SDA_STUCK_RECOVERY_ENABLE : 1; /*!< [3..3] SDA STUCK RECOVERY ENABLE */ - __IM uint32_t RESERVED1 : 28; /*!< [31..4] reserved1 */ + __IM unsigned int RESERVED1 : 28; /*!< [31..4] reserved1 */ } IC_ENABLE_b; }; union { - __IM uint32_t IC_STATUS; /*!< (@ 0x00000070) I2C Status Register */ + __IM unsigned int IC_STATUS; /*!< (@ 0x00000070) I2C Status Register */ struct { - __IM uint32_t ACTIVITY : 1; /*!< [0..0] I2C Activity Status */ - __IM uint32_t TFNF : 1; /*!< [1..1] Transmit FIFO Not Full */ - __IM uint32_t TFE : 1; /*!< [2..2] Transmit FIFO Completely Empty */ - __IM uint32_t RFNE : 1; /*!< [3..3] Receive FIFO Not Empty */ - __IM uint32_t RFF : 1; /*!< [4..4] Receive FIFO Completely Full */ - __IM uint32_t MST_ACTIVITY : 1; /*!< [5..5] Master FSM Activity Status */ - __IM uint32_t SLV_ACTIVITY : 1; /*!< [6..6] Slave FSM Activity Status */ - __IM uint32_t MST_HOLD_TX_FIFO_EMPTY : 1; /*!< [7..7] The I2C master stalls the + __IM unsigned int ACTIVITY : 1; /*!< [0..0] I2C Activity Status */ + __IM unsigned int TFNF : 1; /*!< [1..1] Transmit FIFO Not Full */ + __IM unsigned int TFE : 1; /*!< [2..2] Transmit FIFO Completely Empty */ + __IM unsigned int RFNE : 1; /*!< [3..3] Receive FIFO Not Empty */ + __IM unsigned int RFF : 1; /*!< [4..4] Receive FIFO Completely Full */ + __IM unsigned int MST_ACTIVITY : 1; /*!< [5..5] Master FSM Activity Status */ + __IM unsigned int SLV_ACTIVITY : 1; /*!< [6..6] Slave FSM Activity Status */ + __IM unsigned int MST_HOLD_TX_FIFO_EMPTY : 1; /*!< [7..7] The I2C master stalls the write transfer when Tx FIFO is empty, and the the last byte does not have the Stop bit set. */ - __IM uint32_t MST_HOLD_RX_FIFO_FULL : 1; /*!< [8..8] This bit indicates the BUS Hold + __IM unsigned int MST_HOLD_RX_FIFO_FULL : 1; /*!< [8..8] This bit indicates the BUS Hold in Master mode due to Rx FIFO is Full and additional byte has been received. */ - __IM uint32_t SLV_HOLD_TX_FIFO_EMPTY : 1; /*!< [9..9] This bit indicates the BUS + __IM unsigned int SLV_HOLD_TX_FIFO_EMPTY : 1; /*!< [9..9] This bit indicates the BUS Hold in Slave mode for the Read request when the Tx FIFO is empty. */ - __IM uint32_t SLV_HOLD_RX_FIFO_FULL : 1; /*!< [10..10] This bit indicates the BUS + __IM unsigned int SLV_HOLD_RX_FIFO_FULL : 1; /*!< [10..10] This bit indicates the BUS Hold in Slave mode due to the Rx FIFO being Full and an additional byte being received. */ - __IM uint32_t SDA_STUCK_NOT_RECOVERED : 1; /*!< [11..11] This bit indicates that an + __IM unsigned int SDA_STUCK_NOT_RECOVERED : 1; /*!< [11..11] This bit indicates that an SDA stuck at low is not recovered after the recovery mechanism. */ - __IM uint32_t RESERVED1 : 20; /*!< [31..12] reserved1 */ + __IM unsigned int RESERVED1 : 20; /*!< [31..12] reserved1 */ } IC_STATUS_b; }; union { - __IM uint32_t IC_TXFLR; /*!< (@ 0x00000074) I2C Transmit FIFO Level Register */ + __IM unsigned int IC_TXFLR; /*!< (@ 0x00000074) I2C Transmit FIFO Level Register */ struct { - __IM uint32_t TXFLR : 4; /*!< [3..0] Contains the number of valid data + __IM unsigned int TXFLR : 4; /*!< [3..0] Contains the number of valid data entries in the transmit FIFO. */ - __IM uint32_t RESERVED1 : 28; /*!< [31..4] reserved1 */ + __IM unsigned int RESERVED1 : 28; /*!< [31..4] reserved1 */ } IC_TXFLR_b; }; union { - __IM uint32_t IC_RXFLR; /*!< (@ 0x00000078) I2C Receive FIFO Level Register */ + __IM unsigned int IC_RXFLR; /*!< (@ 0x00000078) I2C Receive FIFO Level Register */ struct { - __IM uint32_t RXFLR : 4; /*!< [3..0] Receive FIFO Level. Contains the number of + __IM unsigned int RXFLR : 4; /*!< [3..0] Receive FIFO Level. Contains the number of valid data entries in the receive FIFO */ - __IM uint32_t RESERVED1 : 28; /*!< [31..4] reserved1 */ + __IM unsigned int RESERVED1 : 28; /*!< [31..4] reserved1 */ } IC_RXFLR_b; }; union { - __IOM uint32_t IC_SDA_HOLD; /*!< (@ 0x0000007C) I2C SDA Hold Time Length Register */ + __IOM unsigned int IC_SDA_HOLD; /*!< (@ 0x0000007C) I2C SDA Hold Time Length Register */ struct { - __IOM uint32_t IC_SDA_TX_HOLD : 16; /*!< [15..0] Sets the required SDA hold time in + __IOM unsigned int IC_SDA_TX_HOLD : 16; /*!< [15..0] Sets the required SDA hold time in units of ic_clk period,when I2C acts as a transmitter. */ - __IOM uint32_t IC_SDA_RX_HOLD : 8; /*!< [23..16] Sets the required SDA hold time in + __IOM unsigned int IC_SDA_RX_HOLD : 8; /*!< [23..16] Sets the required SDA hold time in units of ic_clk period,when I2C acts as a receiver. */ - __IM uint32_t RESERVED1 : 8; /*!< [31..24] reserved1 */ + __IM unsigned int RESERVED1 : 8; /*!< [31..24] reserved1 */ } IC_SDA_HOLD_b; }; union { - __IM uint32_t IC_TX_ABRT_SOURCE; /*!< (@ 0x00000080) I2C Transmit Abort + __IM unsigned int IC_TX_ABRT_SOURCE; /*!< (@ 0x00000080) I2C Transmit Abort Source Register */ struct { - __IM uint32_t ABRT_7B_ADDR_NOACK : 1; /*!< [0..0] 1: Master is in 7-bit addressing + __IM unsigned int ABRT_7B_ADDR_NOACK : 1; /*!< [0..0] 1: Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave */ - __IM uint32_t ABRT_10ADDR1_NOACK : 1; /*!< [1..1] 1: Master is in 10-bit + __IM unsigned int ABRT_10ADDR1_NOACK : 1; /*!< [1..1] 1: Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave */ - __IM uint32_t ABRT_10ADDR2_NOACK : 1; /*!< [2..2] 1: Master is in 10-bit address + __IM unsigned int ABRT_10ADDR2_NOACK : 1; /*!< [2..2] 1: Master is in 10-bit address mode and the second address byte of the 10-bit address was not acknowledged by any slave */ - __IM uint32_t ABRT_TXDATA_NOACK : 1; /*!< [3..3] 1: This is a master-mode only bit. + __IM unsigned int ABRT_TXDATA_NOACK : 1; /*!< [3..3] 1: This is a master-mode only bit. Master has received an acknowledgement for the address, but when it sent data byte(s) following the address, it did not receive an acknowledge from the remote slave(s) */ - __IM uint32_t ABRT_GCALL_NOACK : 1; /*!< [4..4] 1: DW_apb_i2c in master mode sent a + __IM unsigned int ABRT_GCALL_NOACK : 1; /*!< [4..4] 1: DW_apb_i2c in master mode sent a General Call and no slave on the bus acknowledged the General Call */ - __IM uint32_t ABRT_GCALL_READ : 1; /*!< [5..5] 1: DW_apb_i2c in master mode sent a + __IM unsigned int ABRT_GCALL_READ : 1; /*!< [5..5] 1: DW_apb_i2c in master mode sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1) */ - __IM uint32_t ABRT_HS_ACKDET : 1; /*!< [6..6] 1: Master is in High Speed + __IM unsigned int ABRT_HS_ACKDET : 1; /*!< [6..6] 1: Master is in High Speed mode and the High Speed Master code was acknowledged */ - __IM uint32_t ABRT_SBYTE_ACKDET : 1; /*!< [7..7] 1: Master has sent a START Byte and + __IM unsigned int ABRT_SBYTE_ACKDET : 1; /*!< [7..7] 1: Master has sent a START Byte and the START Byte was acknowledged (wrong behavior) */ - __IM uint32_t ABRT_HS_NORSTRT : 1; /*!< [8..8] 1: The restart is disabled + __IM unsigned int ABRT_HS_NORSTRT : 1; /*!< [8..8] 1: The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) = 0) and the user is trying to use the master to transfer data in High Speed mode */ - __IM uint32_t ABRT_SBYTE_NORSTRT : 1; /*!< [9..9] 1: The restart is disabled + __IM unsigned int ABRT_SBYTE_NORSTRT : 1; /*!< [9..9] 1: The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) = 0) and the user is trying to send a START Byte */ - __IM uint32_t ABRT_10B_RD_NORSTRT : 1; /*!< [10..10] 1: The restart is disabled + __IM unsigned int ABRT_10B_RD_NORSTRT : 1; /*!< [10..10] 1: The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) = 0) and the master sends a read command in 10-bit addressing mode */ - __IM uint32_t ABRT_MASTER_DIS : 1; /*!< [11..11] 1: User tries to initiate a Master + __IM unsigned int ABRT_MASTER_DIS : 1; /*!< [11..11] 1: User tries to initiate a Master operation with the Master mode disabled */ - __IM uint32_t ARB_LOST : 1; /*!< [12..12] 1: Master has lost arbitration, or if + __IM unsigned int ARB_LOST : 1; /*!< [12..12] 1: Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration */ - __IM uint32_t ABRT_SLVFLUSH_TXFIFO : 1; /*!< [13..13] 1: Slave has received a + __IM unsigned int ABRT_SLVFLUSH_TXFIFO : 1; /*!< [13..13] 1: Slave has received a read command and some data exists in the TX FIFO so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO */ - __IM uint32_t ABRT_SLV_ARBLOST : 1; /*!< [14..14] 1: Slave lost the bus + __IM unsigned int ABRT_SLV_ARBLOST : 1; /*!< [14..14] 1: Slave lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time */ - __IM uint32_t ABRT_SLVRD_INTX : 1; /*!< [15..15] 1: When the processor side responds + __IM unsigned int ABRT_SLVRD_INTX : 1; /*!< [15..15] 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register */ - __IM uint32_t ABRT_USER_ABRT : 1; /*!< [16..16] This is a master-mode-only bit. + __IM unsigned int ABRT_USER_ABRT : 1; /*!< [16..16] This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1]). */ - __IM uint32_t ABRT_SDA_STUCK_AT_LOW : 1; /*!< [17..17] Master detects the + __IM unsigned int ABRT_SDA_STUCK_AT_LOW : 1; /*!< [17..17] Master detects the SDA is Stuck at low for the IC_SDA_STUCK_AT_LOW_TI EOUT value of ic_clks */ - __IM uint32_t ABRT_DEVICE_NOACK : 1; /*!< [18..18] Master initiates the DEVICE_ID + __IM unsigned int ABRT_DEVICE_NOACK : 1; /*!< [18..18] Master initiates the DEVICE_ID transfer and the device ID sent is not acknowledged by any slave */ - __IM uint32_t ABRT_DEVICE_SLVADDR_NOACK : 1; /*!< [19..19] Master is initiating the + __IM unsigned int ABRT_DEVICE_SLVADDR_NOACK : 1; /*!< [19..19] Master is initiating the DEVICE_ID transfer and the slave address sent was not acknowledged by any slave */ - __IM uint32_t ABRT_DEVICE_WRITE : 1; /*!< [20..20] Master is initiating the + __IM unsigned int ABRT_DEVICE_WRITE : 1; /*!< [20..20] Master is initiating the DEVICE_ID transfer and the Tx- FIFO consists of write commands. */ - __IM uint32_t RESERVED1 : 2; /*!< [22..21] reserved1 */ - __IM uint32_t TX_FLUSH_CNT : 9; /*!< [31..23] This field indicates the number of Tx + __IM unsigned int RESERVED1 : 2; /*!< [22..21] reserved1 */ + __IM unsigned int TX_FLUSH_CNT : 9; /*!< [31..23] This field indicates the number of Tx FIFO data commands that are flushed due to TX_ABRT interrupt */ } IC_TX_ABRT_SOURCE_b; }; union { - __IOM uint32_t IC_SLV_DATA_NACK_ONLY; /*!< (@ 0x00000084) Generate Slave + __IOM unsigned int IC_SLV_DATA_NACK_ONLY; /*!< (@ 0x00000084) Generate Slave Data NACK Register */ struct { - __IOM uint32_t NACK : 1; /*!< [0..0] Generate NACK. This NACK generation only occurs + __IOM unsigned int NACK : 1; /*!< [0..0] Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave receiver. */ - __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ } IC_SLV_DATA_NACK_ONLY_b; }; union { - __IOM uint32_t IC_DMA_CR; /*!< (@ 0x00000088) DMA Control Register */ + __IOM unsigned int IC_DMA_CR; /*!< (@ 0x00000088) DMA Control Register */ struct { - __IOM uint32_t RDMAE : 1; /*!< [0..0] Receive DMA Enable */ - __IOM uint32_t TDMAE : 1; /*!< [1..1] Transmit DMA Enable.This bit enables/disables + __IOM unsigned int RDMAE : 1; /*!< [0..0] Receive DMA Enable */ + __IOM unsigned int TDMAE : 1; /*!< [1..1] Transmit DMA Enable.This bit enables/disables the transmit FIFO DMA channel */ - __IM uint32_t RESERVED1 : 30; /*!< [31..2] reserved1 */ + __IM unsigned int RESERVED1 : 30; /*!< [31..2] reserved1 */ } IC_DMA_CR_b; }; union { - __IOM uint32_t IC_DMA_TDLR; /*!< (@ 0x0000008C) DMA Transmit Data Level Register */ + __IOM unsigned int IC_DMA_TDLR; /*!< (@ 0x0000008C) DMA Transmit Data Level Register */ struct { - __IOM uint32_t DMATDL : 4; /*!< [3..0] This bit field controls the level at which a + __IOM unsigned int DMATDL : 4; /*!< [3..0] This bit field controls the level at which a DMA request is made by the transmit logic */ - __IM uint32_t RESERVED1 : 28; /*!< [31..4] reserved1 */ + __IM unsigned int RESERVED1 : 28; /*!< [31..4] reserved1 */ } IC_DMA_TDLR_b; }; union { - __IOM uint32_t IC_DMA_RDLR; /*!< (@ 0x00000090) I2C Receive Data Level Register */ + __IOM unsigned int IC_DMA_RDLR; /*!< (@ 0x00000090) I2C Receive Data Level Register */ struct { - __IOM uint32_t DMARDL : 4; /*!< [3..0] This bit field controls the level at which a + __IOM unsigned int DMARDL : 4; /*!< [3..0] This bit field controls the level at which a DMA request is made by the receive logic */ - __IM uint32_t RESERVED1 : 28; /*!< [31..4] reserved1 */ + __IM unsigned int RESERVED1 : 28; /*!< [31..4] reserved1 */ } IC_DMA_RDLR_b; }; union { - __IOM uint32_t IC_SDA_SETUP; /*!< (@ 0x00000094) I2C SDA Setup Register */ + __IOM unsigned int IC_SDA_SETUP; /*!< (@ 0x00000094) I2C SDA Setup Register */ struct { - __IOM uint32_t SDA_SETUP : 8; /*!< [7..0] This register controls the amount of time + __IOM unsigned int SDA_SETUP : 8; /*!< [7..0] This register controls the amount of time delay (in terms of number of ic_clk clock periods) */ - __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ } IC_SDA_SETUP_b; }; union { - __IOM uint32_t IC_ACK_GENERAL_CALL; /*!< (@ 0x00000098) I2C ACK General Call + __IOM unsigned int IC_ACK_GENERAL_CALL; /*!< (@ 0x00000098) I2C ACK General Call Register */ struct { - __IOM uint32_t ACK_GEN_CALL : 1; /*!< [0..0] ACK General Call */ - __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + __IOM unsigned int ACK_GEN_CALL : 1; /*!< [0..0] ACK General Call */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ } IC_ACK_GENERAL_CALL_b; }; union { - __IM uint32_t IC_ENABLE_STATUS; /*!< (@ 0x0000009C) I2C Enable Status Register */ + __IM unsigned int IC_ENABLE_STATUS; /*!< (@ 0x0000009C) I2C Enable Status Register */ struct { - __IM uint32_t IC_EN : 1; /*!< [0..0] This bit always reflects the value + __IM unsigned int IC_EN : 1; /*!< [0..0] This bit always reflects the value driven on the output port ic_en. */ - __IM uint32_t SLV_DISABLED_WHILE_BUSY : 1; /*!< [1..1] This bit indicates if a + __IM unsigned int SLV_DISABLED_WHILE_BUSY : 1; /*!< [1..1] This bit indicates if a potential or active Slave operation has been aborted due to the setting of the IC_ENABLE register from 1 to 0 */ - __IM uint32_t SLV_RX_DATA_LOST : 1; /*!< [2..2] Slave Received Data Lost */ - __IM uint32_t RESERVED1 : 29; /*!< [31..3] reserved1 */ + __IM unsigned int SLV_RX_DATA_LOST : 1; /*!< [2..2] Slave Received Data Lost */ + __IM unsigned int RESERVED1 : 29; /*!< [31..3] reserved1 */ } IC_ENABLE_STATUS_b; }; union { - __IOM uint32_t IC_FS_SPKLEN; /*!< (@ 0x000000A0) I2C SS and FS Spike + __IOM unsigned int IC_FS_SPKLEN; /*!< (@ 0x000000A0) I2C SS and FS Spike Suppression Limit Register */ struct { - __IOM uint32_t IC_FS_SPKLEN : 8; /*!< [7..0] This register sets the + __IOM unsigned int IC_FS_SPKLEN : 8; /*!< [7..0] This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that are filtered out by the spike suppression logic */ - __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ } IC_FS_SPKLEN_b; }; union { - __IOM uint32_t IC_HS_SPKLEN; /*!< (@ 0x000000A4) I2C HS Spike Suppression + __IOM unsigned int IC_HS_SPKLEN; /*!< (@ 0x000000A4) I2C HS Spike Suppression Limit Register */ struct { - __IOM uint32_t IC_HS_SPKLEN : 8; /*!< [7..0] This register sets the + __IOM unsigned int IC_HS_SPKLEN : 8; /*!< [7..0] This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that are filtered out by the spike suppression logic */ - __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ } IC_HS_SPKLEN_b; }; union { - __IM uint32_t IC_CLR_RESTART_DET; /*!< (@ 0x000000A8) Clear RESTART_DET + __IM unsigned int IC_CLR_RESTART_DET; /*!< (@ 0x000000A8) Clear RESTART_DET Interrupt Register */ struct { - __IM uint32_t CLR_RESTART_DET : 1; /*!< [0..0] Read this register to clear + __IM unsigned int CLR_RESTART_DET : 1; /*!< [0..0] Read this register to clear the RESTART_DET interrupt (bit 12) of the IC_RAW_INTR_STAT registe */ - __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ } IC_CLR_RESTART_DET_b; }; union { - __IOM uint32_t IC_SCL_STUCK_AT_LOW_TIMEOUT; /*!< (@ 0x000000AC) I2C SCL + __IOM unsigned int IC_SCL_STUCK_AT_LOW_TIMEOUT; /*!< (@ 0x000000AC) I2C SCL Stuck at Low Timeout */ struct { - __IOM uint32_t IC_SCL_STUCK_LOW_TIMEOUT : 32; /*!< [31..0] Generates the interrupt to + __IOM unsigned int IC_SCL_STUCK_LOW_TIMEOUT : 32; /*!< [31..0] Generates the interrupt to indicate SCL stuck at low if it detects the SCL stuck at low for the IC_SCL_STUCK_LOW_TIMEOUT in units of @@ -1851,11 +1851,11 @@ typedef struct { /*!< (@ 0x44010000) I2C0 Structure */ }; union { - __IOM uint32_t IC_SDA_STUCK_AT_LOW_TIMEOUT; /*!< (@ 0x000000B0) I2C SDA + __IOM unsigned int IC_SDA_STUCK_AT_LOW_TIMEOUT; /*!< (@ 0x000000B0) I2C SDA Stuck at Low Timeout */ struct { - __IOM uint32_t IC_SDA_STUCK_LOW_TIMEOUT : 32; /*!< [31..0] Initiates the recovery of + __IOM unsigned int IC_SDA_STUCK_LOW_TIMEOUT : 32; /*!< [31..0] Initiates the recovery of SDA line , if it detects the SDA stuck at low for the IC_SDA_STUCK_LOW_TIMEOUT in units of @@ -1864,151 +1864,151 @@ typedef struct { /*!< (@ 0x44010000) I2C0 Structure */ }; union { - __IM uint32_t IC_CLR_SCL_STUCK_DET; /*!< (@ 0x000000B4) Clear SCL Stuck at + __IM unsigned int IC_CLR_SCL_STUCK_DET; /*!< (@ 0x000000B4) Clear SCL Stuck at Low Detect Interrupt Register */ struct { - __IM uint32_t CLR_SCL_STUCK : 1; /*!< [0..0] Read this register to clear + __IM unsigned int CLR_SCL_STUCK : 1; /*!< [0..0] Read this register to clear the SCL_STUCK_DET interrupt */ - __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ } IC_CLR_SCL_STUCK_DET_b; }; union { - __IM uint32_t IC_DEVICE_ID; /*!< (@ 0x000000B8) I2C Device ID */ + __IM unsigned int IC_DEVICE_ID; /*!< (@ 0x000000B8) I2C Device ID */ struct { - __IM uint32_t DEVICE_ID : 24; /*!< [23..0] Contains the Device-ID of the component + __IM unsigned int DEVICE_ID : 24; /*!< [23..0] Contains the Device-ID of the component assigned through the configuration parameter */ - __IM uint32_t RESERVED1 : 8; /*!< [31..24] reserved1 */ + __IM unsigned int RESERVED1 : 8; /*!< [31..24] reserved1 */ } IC_DEVICE_ID_b; }; union { - __IOM uint32_t IC_SMBUS_CLOCK_LOW_SEXT; /*!< (@ 0x000000BC) SMBUS Slave Clock Extend + __IOM unsigned int IC_SMBUS_CLOCK_LOW_SEXT; /*!< (@ 0x000000BC) SMBUS Slave Clock Extend Timeout Register */ struct { - __IOM uint32_t SMBUS_CLK_LOW_SEXT_TIMEOUT : 32; /*!< [31..0] The values in this + __IOM unsigned int SMBUS_CLK_LOW_SEXT_TIMEOUT : 32; /*!< [31..0] The values in this register are in units of ic_clk period. */ } IC_SMBUS_CLOCK_LOW_SEXT_b; }; union { - __IOM uint32_t IC_SMBUS_CLOCK_LOW_MEXT; /*!< (@ 0x000000C0) SMBUS Master extend clock + __IOM unsigned int IC_SMBUS_CLOCK_LOW_MEXT; /*!< (@ 0x000000C0) SMBUS Master extend clock Timeout Register */ struct { - __IOM uint32_t SMBUS_CLK_LOW_MEXT_TIMEOUT : 32; /*!< [31..0] The values in this + __IOM unsigned int SMBUS_CLK_LOW_MEXT_TIMEOUT : 32; /*!< [31..0] The values in this register are in units of ic_clk period.. */ } IC_SMBUS_CLOCK_LOW_MEXT_b; }; union { - __IOM uint32_t IC_SMBUS_THIGH_MAX_IDLE_COUNT; /*!< (@ 0x000000C4) SMBus Thigh MAX + __IOM unsigned int IC_SMBUS_THIGH_MAX_IDLE_COUNT; /*!< (@ 0x000000C4) SMBus Thigh MAX Bus-Idle count Register */ struct { - __IOM uint32_t SMBUS_THIGH_MAX_BUS_IDLE_CNT : 16; /*!< [15..0] The values in this + __IOM unsigned int SMBUS_THIGH_MAX_BUS_IDLE_CNT : 16; /*!< [15..0] The values in this register are in units of ic_clk period. */ - __IOM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved1 */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved1 */ } IC_SMBUS_THIGH_MAX_IDLE_COUNT_b; }; union { - __IOM uint32_t IC_SMBUS_INTR_STAT; /*!< (@ 0x000000C8) SMBUS Interrupt + __IOM unsigned int IC_SMBUS_INTR_STAT; /*!< (@ 0x000000C8) SMBUS Interrupt Status Register */ struct { - __IOM uint32_t RESERVED1 : 32; /*!< [31..0] Reserved1 */ + __IOM unsigned int RESERVED1 : 32; /*!< [31..0] Reserved1 */ } IC_SMBUS_INTR_STAT_b; }; union { - __IOM uint32_t IC_SMBUS_INTR_MASK; /*!< (@ 0x000000CC) Interrupt Mask Register */ + __IOM unsigned int IC_SMBUS_INTR_MASK; /*!< (@ 0x000000CC) Interrupt Mask Register */ struct { - __IOM uint32_t RESERVED1 : 32; /*!< [31..0] Reserved1 */ + __IOM unsigned int RESERVED1 : 32; /*!< [31..0] Reserved1 */ } IC_SMBUS_INTR_MASK_b; }; union { - __IOM uint32_t IC_SMBUS_INTR_RAW_STATUS; /*!< (@ 0x000000D0) SMBUS Raw + __IOM unsigned int IC_SMBUS_INTR_RAW_STATUS; /*!< (@ 0x000000D0) SMBUS Raw Interrupt Status Register */ struct { - __IOM uint32_t RESERVED1 : 32; /*!< [31..0] Reserved1. */ + __IOM unsigned int RESERVED1 : 32; /*!< [31..0] Reserved1. */ } IC_SMBUS_INTR_RAW_STATUS_b; }; union { - __IOM uint32_t IC_CLR_SMBUS_INTR; /*!< (@ 0x000000D4) Clear SMBUS Interrupt + __IOM unsigned int IC_CLR_SMBUS_INTR; /*!< (@ 0x000000D4) Clear SMBUS Interrupt Register */ struct { - __IOM uint32_t RESERVED1 : 32; /*!< [31..0] RESERVED1 */ + __IOM unsigned int RESERVED1 : 32; /*!< [31..0] RESERVED1 */ } IC_CLR_SMBUS_INTR_b; }; union { - __IOM uint32_t IC_OPTIONAL_SAR; /*!< (@ 0x000000D8) Optional Slave Address + __IOM unsigned int IC_OPTIONAL_SAR; /*!< (@ 0x000000D8) Optional Slave Address Register */ struct { - __IOM uint32_t RESERVED1 : 32; /*!< [31..0] Reserved1. */ + __IOM unsigned int RESERVED1 : 32; /*!< [31..0] Reserved1. */ } IC_OPTIONAL_SAR_b; }; union { - __IOM uint32_t IC_SMBUS_UDID_LSB; /*!< (@ 0x000000DC) SMBUS ARP UDID LSB Register */ + __IOM unsigned int IC_SMBUS_UDID_LSB; /*!< (@ 0x000000DC) SMBUS ARP UDID LSB Register */ struct { - __IOM uint32_t IC_SMBUS_ARP_UDID_LSB : 32; /*!< [31..0] This field is used to store + __IOM unsigned int IC_SMBUS_ARP_UDID_LSB : 32; /*!< [31..0] This field is used to store the LSB 32 bit value of slave unique device identifier used in Address Resolution Protocol. */ } IC_SMBUS_UDID_LSB_b; }; - __IM uint32_t RESERVED[5]; + __IM unsigned int RESERVED[5]; union { - __IM uint32_t IC_COMP_PARAM_1; /*!< (@ 0x000000F4) I2C HS Spike Suppression + __IM unsigned int IC_COMP_PARAM_1; /*!< (@ 0x000000F4) I2C HS Spike Suppression Limit Register */ struct { - __IM uint32_t CLR_RESTART_DET : 2; /*!< [1..0] Read this register to clear the + __IM unsigned int CLR_RESTART_DET : 2; /*!< [1..0] Read this register to clear the RESTART_DET interrupt (bit 12) of the IC_RAW_INTR_STAT register */ - __IM uint32_t MAX_SPEED_MODE : 2; /*!< [3..2] Maximum Speed Mode */ - __IM uint32_t HC_COUNT_VALUES : 1; /*!< [4..4] Hard Code the count values */ - __IM uint32_t INTR_IO : 1; /*!< [5..5] Single Interrupt Output port */ - __IM uint32_t HAS_DMA : 1; /*!< [6..6] DMA Handshake Interface signal */ - __IM uint32_t ADD_ENCODED_PARAMS : 1; /*!< [7..7] Add Encoded Parameters */ - __IM uint32_t RX_BUFFER_DEPTH : 8; /*!< [15..8] Depth of receive buffer;the buffer + __IM unsigned int MAX_SPEED_MODE : 2; /*!< [3..2] Maximum Speed Mode */ + __IM unsigned int HC_COUNT_VALUES : 1; /*!< [4..4] Hard Code the count values */ + __IM unsigned int INTR_IO : 1; /*!< [5..5] Single Interrupt Output port */ + __IM unsigned int HAS_DMA : 1; /*!< [6..6] DMA Handshake Interface signal */ + __IM unsigned int ADD_ENCODED_PARAMS : 1; /*!< [7..7] Add Encoded Parameters */ + __IM unsigned int RX_BUFFER_DEPTH : 8; /*!< [15..8] Depth of receive buffer;the buffer is 8 bits wide;2 to 256 */ - __IM uint32_t TX_BUFFER_DEPTH : 8; /*!< [23..16] Depth of Transmit buffer;the buffer + __IM unsigned int TX_BUFFER_DEPTH : 8; /*!< [23..16] Depth of Transmit buffer;the buffer is 8 bits wide;2 to 256 */ - __IM uint32_t RESERVED1 : 8; /*!< [31..24] reserved1 */ + __IM unsigned int RESERVED1 : 8; /*!< [31..24] reserved1 */ } IC_COMP_PARAM_1_b; }; union { - __IM uint32_t IC_COMP_VERSION; /*!< (@ 0x000000F8) I2C Component Version Register */ + __IM unsigned int IC_COMP_VERSION; /*!< (@ 0x000000F8) I2C Component Version Register */ struct { - __IM uint32_t IC_COMP_VERSION : 32; /*!< [31..0] Signifies the component + __IM unsigned int IC_COMP_VERSION : 32; /*!< [31..0] Signifies the component version */ } IC_COMP_VERSION_b; }; union { - __IM uint32_t IC_COMP_TYPE; /*!< (@ 0x000000FC) I2C Component Type Register */ + __IM unsigned int IC_COMP_TYPE; /*!< (@ 0x000000FC) I2C Component Type Register */ struct { - __IM uint32_t IC_COMP_TYPE : 32; /*!< [31..0] Design ware Component Type + __IM unsigned int IC_COMP_TYPE : 32; /*!< [31..0] Design ware Component Type number = 0x44_57_01_40 */ } IC_COMP_TYPE_b; }; @@ -2030,740 +2030,740 @@ typedef struct { /*!< (@ 0x44010000) I2C0 Structure */ typedef struct { /*!< (@ 0x47070000) MCPWM Structure */ union { - __IM uint32_t PWM_INTR_STS; /*!< (@ 0x00000000) PWM Interrupt Status Register */ + __IM unsigned int PWM_INTR_STS; /*!< (@ 0x00000000) PWM Interrupt Status Register */ struct { - __IM uint32_t RISE_PWM_TIME_PERIOD_MATCH_INTR_CH0 : 1; /*!< [0..0] This time base + __IM unsigned int RISE_PWM_TIME_PERIOD_MATCH_INTR_CH0 : 1; /*!< [0..0] This time base interrupt for 0th channel without considering postscaler */ - __IM uint32_t PWM_TIME_PRD_MATCH_INTR_CH0 : 1; /*!< [1..1] This time base interrupt + __IM unsigned int PWM_TIME_PRD_MATCH_INTR_CH0 : 1; /*!< [1..1] This time base interrupt for 0th channel, which considers postscaler value */ - __IM uint32_t FLT_A_INTR : 1; /*!< [2..2] When the fault A pin is driven + __IM unsigned int FLT_A_INTR : 1; /*!< [2..2] When the fault A pin is driven low, this interrupt is raised. */ - __IM uint32_t FLT_B_INTR : 1; /*!< [3..3] When the fault B pin is driven + __IM unsigned int FLT_B_INTR : 1; /*!< [3..3] When the fault B pin is driven low, this interrupt is raised. */ - __IM uint32_t RISE_PWM_TIME_PERIOD_MATCH_INTR_CH1 : 1; /*!< [4..4] This time base + __IM unsigned int RISE_PWM_TIME_PERIOD_MATCH_INTR_CH1 : 1; /*!< [4..4] This time base interrupt for 1st channel without considering postscaler value */ - __IM uint32_t PWM_TIME_PRD_MATCH_INTR_CH1 : 1; /*!< [5..5] This time base interrupt + __IM unsigned int PWM_TIME_PRD_MATCH_INTR_CH1 : 1; /*!< [5..5] This time base interrupt for 1st channel, which considers postscaler value. */ - __IM uint32_t RISE_PWM_TIME_PERIOD_MATCH_INTR_CH2 : 1; /*!< [6..6] This time base + __IM unsigned int RISE_PWM_TIME_PERIOD_MATCH_INTR_CH2 : 1; /*!< [6..6] This time base interrupt for 2nd channel without considering postscaler value. */ - __IM uint32_t PWM_TIME_PRD_MATCH_INTR_CH2 : 1; /*!< [7..7] This time base interrupt + __IM unsigned int PWM_TIME_PRD_MATCH_INTR_CH2 : 1; /*!< [7..7] This time base interrupt for 2nd channel, which considers postscaler value */ - __IM uint32_t RISE_PWM_TIME_PERIOD_MATCH_INTR_CH3 : 1; /*!< [8..8] This time base + __IM unsigned int RISE_PWM_TIME_PERIOD_MATCH_INTR_CH3 : 1; /*!< [8..8] This time base interrupt for 3rd channel without considering postscaler value. */ - __IM uint32_t PWM_TIME_PRD_MATCH_INTR_CH3 : 1; /*!< [9..9] This time base interrupt + __IM unsigned int PWM_TIME_PRD_MATCH_INTR_CH3 : 1; /*!< [9..9] This time base interrupt for 3rd channel, which considers postscaler value. */ - __IM uint32_t RESERVED1 : 22; /*!< [31..10] reserved1 */ + __IM unsigned int RESERVED1 : 22; /*!< [31..10] reserved1 */ } PWM_INTR_STS_b; }; union { - __IOM uint32_t PWM_INTR_UNMASK; /*!< (@ 0x00000004) PWM Interrupt Unmask Register */ + __IOM unsigned int PWM_INTR_UNMASK; /*!< (@ 0x00000004) PWM Interrupt Unmask Register */ struct { - __IOM uint32_t PWM_INTR_UNMASK : 16; /*!< [15..0] Interrupt Unmask */ - __IOM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + __IOM unsigned int PWM_INTR_UNMASK : 16; /*!< [15..0] Interrupt Unmask */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ } PWM_INTR_UNMASK_b; }; union { - __IOM uint32_t PWM_INTR_MASK; /*!< (@ 0x00000008) PWM Interrupt mask Register */ + __IOM unsigned int PWM_INTR_MASK; /*!< (@ 0x00000008) PWM Interrupt mask Register */ struct { - __IOM uint32_t PWM_INTR_UNMASK : 16; /*!< [15..0] Interrupt Mask */ - __IOM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + __IOM unsigned int PWM_INTR_UNMASK : 16; /*!< [15..0] Interrupt Mask */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ } PWM_INTR_MASK_b; }; union { - __IOM uint32_t PWM_INTR_ACK; /*!< (@ 0x0000000C) PWM Interrupt + __IOM unsigned int PWM_INTR_ACK; /*!< (@ 0x0000000C) PWM Interrupt Acknowledgement Register */ struct { - __OM uint32_t RISE_PWM_TIME_PERIOD_MATCH_CH0_ACK : 1; /*!< [0..0] pwm time + __OM unsigned int RISE_PWM_TIME_PERIOD_MATCH_CH0_ACK : 1; /*!< [0..0] pwm time period match interrupt for 0th channel will be cleared. */ - __OM uint32_t PWM_TIME_PRD_MATCH_INTR_CH0_ACK : 1; /*!< [1..1] pwm time period match + __OM unsigned int PWM_TIME_PRD_MATCH_INTR_CH0_ACK : 1; /*!< [1..1] pwm time period match interrupt for 0th channel will be cleared */ - __OM uint32_t FLT_A_INTR_ACK : 1; /*!< [2..2] pwm fault A interrupt will + __OM unsigned int FLT_A_INTR_ACK : 1; /*!< [2..2] pwm fault A interrupt will be cleared. */ - __OM uint32_t FLT_B_INTR_ACK : 1; /*!< [3..3] pwm fault B interrupt will + __OM unsigned int FLT_B_INTR_ACK : 1; /*!< [3..3] pwm fault B interrupt will be cleared. */ - __OM uint32_t RISE_PWM_TIME_PERIOD_MATCH_CH1_ACK : 1; /*!< [4..4] pwm time + __OM unsigned int RISE_PWM_TIME_PERIOD_MATCH_CH1_ACK : 1; /*!< [4..4] pwm time period match interrupt for 1st channel will be cleared */ - __OM uint32_t PWM_TIME_PRD_MATCH_INTR_CH1_ACK : 1; /*!< [5..5] pwm time period match + __OM unsigned int PWM_TIME_PRD_MATCH_INTR_CH1_ACK : 1; /*!< [5..5] pwm time period match interrupt for 1st channel will be cleared. */ - __OM uint32_t RISE_PWM_TIME_PERIOD_MATCH_CH2_ACK : 1; /*!< [6..6] pwm time + __OM unsigned int RISE_PWM_TIME_PERIOD_MATCH_CH2_ACK : 1; /*!< [6..6] pwm time period match interrupt for 2nd channel will be cleared. */ - __OM uint32_t PWM_TIME_PRD_MATCH_INTR_CH2_ACK : 1; /*!< [7..7] pwm time period match + __OM unsigned int PWM_TIME_PRD_MATCH_INTR_CH2_ACK : 1; /*!< [7..7] pwm time period match interrupt for 2nd channel will be cleared. */ - __OM uint32_t RISE_PWM_TIME_PERIOD_MATCH_CH3_ACK : 1; /*!< [8..8] pwm time + __OM unsigned int RISE_PWM_TIME_PERIOD_MATCH_CH3_ACK : 1; /*!< [8..8] pwm time period match interrupt for 3rd channel will be cleared. */ - __OM uint32_t PWM_TIME_PRD_MATCH_INTR_CH3_ACK : 1; /*!< [9..9] pwm time period match + __OM unsigned int PWM_TIME_PRD_MATCH_INTR_CH3_ACK : 1; /*!< [9..9] pwm time period match interrupt for 3rd channel will be cleared. */ - __IOM uint32_t RESERVED1 : 22; /*!< [31..10] reserved1 */ + __IOM unsigned int RESERVED1 : 22; /*!< [31..10] reserved1 */ } PWM_INTR_ACK_b; }; - __IM uint32_t RESERVED[6]; + __IM unsigned int RESERVED[6]; union { - __IOM uint32_t PWM_TIME_PRD_WR_REG_CH0; /*!< (@ 0x00000028) Base timer + __IOM unsigned int PWM_TIME_PRD_WR_REG_CH0; /*!< (@ 0x00000028) Base timer period register of channel 0 */ struct { - __IOM uint32_t PWM_TIME_PRD_REG_WR_VALUE_CH0 : 16; /*!< [15..0] Value to update the + __IOM unsigned int PWM_TIME_PRD_REG_WR_VALUE_CH0 : 16; /*!< [15..0] Value to update the base timer period register of channel 0 */ - __IOM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ } PWM_TIME_PRD_WR_REG_CH0_b; }; union { - __IOM uint32_t PWM_TIME_PRD_CNTR_WR_REG_CH0; /*!< (@ 0x0000002C) Base time + __IOM unsigned int PWM_TIME_PRD_CNTR_WR_REG_CH0; /*!< (@ 0x0000002C) Base time counter initial value register for channel 0 */ struct { - __IOM uint32_t PWM_TIME_PRD_CNTR_WR_REG_CH0 : 16; /*!< [15..0] To update the base + __IOM unsigned int PWM_TIME_PRD_CNTR_WR_REG_CH0 : 16; /*!< [15..0] To update the base time counter initial value for channel 0 */ - __IOM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ } PWM_TIME_PRD_CNTR_WR_REG_CH0_b; }; union { - __IOM uint32_t PWM_TIME_PRD_PARAM_REG_CH0; /*!< (@ 0x00000030) Base time period config + __IOM unsigned int PWM_TIME_PRD_PARAM_REG_CH0; /*!< (@ 0x00000030) Base time period config parameter's register for channel0 */ struct { - __IOM uint32_t TMR_OPEARATING_MODE_CH0 : 3; /*!< [2..0] Base timer operating mode for + __IOM unsigned int TMR_OPEARATING_MODE_CH0 : 3; /*!< [2..0] Base timer operating mode for channel0 */ - __IOM uint32_t RESERVED1 : 1; /*!< [3..3] reserved1 */ - __IOM uint32_t PWM_TIME_PRD_PRE_SCALAR_VALUE_CH0 : 3; /*!< [6..4] Base timer input + __IOM unsigned int RESERVED1 : 1; /*!< [3..3] reserved1 */ + __IOM unsigned int PWM_TIME_PRD_PRE_SCALAR_VALUE_CH0 : 3; /*!< [6..4] Base timer input clock pre scale select value for channel0. */ - __IOM uint32_t RESERVED2 : 1; /*!< [7..7] reserved2 */ - __IOM uint32_t PWM_TIME_PRD_POST_SCALAR_VALUE_CH0 : 4; /*!< [11..8] Time base output + __IOM unsigned int RESERVED2 : 1; /*!< [7..7] reserved2 */ + __IOM unsigned int PWM_TIME_PRD_POST_SCALAR_VALUE_CH0 : 4; /*!< [11..8] Time base output post scale bits for channel0 */ - __IOM uint32_t RESERVED3 : 20; /*!< [31..12] reserved3 */ + __IOM unsigned int RESERVED3 : 20; /*!< [31..12] reserved3 */ } PWM_TIME_PRD_PARAM_REG_CH0_b; }; union { - __IOM uint32_t PWM_TIME_PRD_CTRL_REG_CH0; /*!< (@ 0x00000034) Base time counter initial + __IOM unsigned int PWM_TIME_PRD_CTRL_REG_CH0; /*!< (@ 0x00000034) Base time counter initial value register for channel 0 */ struct { - __IOM uint32_t PWM_TIME_PRD_CNTR_RST_FRM_REG : 1; /*!< [0..0] Time period counter + __IOM unsigned int PWM_TIME_PRD_CNTR_RST_FRM_REG : 1; /*!< [0..0] Time period counter soft reset */ - __IOM uint32_t PWM_TIME_BASE_EN_FRM_REG_CH0 : 1; /*!< [1..1] Base timer enable for + __IOM unsigned int PWM_TIME_BASE_EN_FRM_REG_CH0 : 1; /*!< [1..1] Base timer enable for channnel0 */ - __IOM uint32_t PWM_SFT_RST : 1; /*!< [2..2] MC PWM soft reset */ - __IM uint32_t RESERVED1 : 29; /*!< [31..3] reserved1 */ + __IOM unsigned int PWM_SFT_RST : 1; /*!< [2..2] MC PWM soft reset */ + __IM unsigned int RESERVED1 : 29; /*!< [31..3] reserved1 */ } PWM_TIME_PRD_CTRL_REG_CH0_b; }; union { - __IM uint32_t PWM_TIME_PRD_STS_REG_CH0; /*!< (@ 0x00000038) Base time period + __IM unsigned int PWM_TIME_PRD_STS_REG_CH0; /*!< (@ 0x00000038) Base time period status register for channel0 */ struct { - __IM uint32_t PWM_TIME_PRD_DIR_STS_CH0 : 1; /*!< [0..0] Time period counter + __IM unsigned int PWM_TIME_PRD_DIR_STS_CH0 : 1; /*!< [0..0] Time period counter direction status for channel0 */ - __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ } PWM_TIME_PRD_STS_REG_CH0_b; }; union { - __IM uint32_t PWM_TIME_PRD_CNTR_VALUE_CH0; /*!< (@ 0x0000003C) Base Time + __IM unsigned int PWM_TIME_PRD_CNTR_VALUE_CH0; /*!< (@ 0x0000003C) Base Time period counter current value register for channel0 */ struct { - __IM uint32_t PWM_TIME_PRD_CNTR_VALUE_CH0 : 16; /*!< [15..0] Time period counter + __IM unsigned int PWM_TIME_PRD_CNTR_VALUE_CH0 : 16; /*!< [15..0] Time period counter current value for channel0 */ - __IM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ } PWM_TIME_PRD_CNTR_VALUE_CH0_b; }; - __IM uint32_t RESERVED1[4]; + __IM unsigned int RESERVED1[4]; union { - __IOM uint32_t PWM_DUTYCYCLE_CTRL_SET_REG; /*!< (@ 0x00000050) Duty cycle + __IOM unsigned int PWM_DUTYCYCLE_CTRL_SET_REG; /*!< (@ 0x00000050) Duty cycle Control Set Register */ struct { - __IOM uint32_t IMDT_DUTYCYCLE_UPDATE_EN : 4; /*!< [3..0] Enable to update the duty + __IOM unsigned int IMDT_DUTYCYCLE_UPDATE_EN : 4; /*!< [3..0] Enable to update the duty cycle immediately */ - __IOM uint32_t DUTYCYCLE_UPDATE_DISABLE : 4; /*!< [7..4] Duty cycle register updation + __IOM unsigned int DUTYCYCLE_UPDATE_DISABLE : 4; /*!< [7..4] Duty cycle register updation disable. There is a separate bit for each channel */ - __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ } PWM_DUTYCYCLE_CTRL_SET_REG_b; }; union { - __IOM uint32_t PWM_DUTYCYCLE_CTRL_RESET_REG; /*!< (@ 0x00000054) Duty cycle + __IOM unsigned int PWM_DUTYCYCLE_CTRL_RESET_REG; /*!< (@ 0x00000054) Duty cycle Control Reset Register */ struct { - __IOM uint32_t IMDT_DUTYCYCLE_UPDATE_EN : 4; /*!< [3..0] Enable to update the duty + __IOM unsigned int IMDT_DUTYCYCLE_UPDATE_EN : 4; /*!< [3..0] Enable to update the duty cycle immediately */ - __IOM uint32_t DUTYCYCLE_UPDATE_DISABLE : 4; /*!< [7..4] Duty cycle + __IOM unsigned int DUTYCYCLE_UPDATE_DISABLE : 4; /*!< [7..4] Duty cycle register updation disable. There is a separate bit for each channel. */ - __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ } PWM_DUTYCYCLE_CTRL_RESET_REG_b; }; union { - __IOM uint32_t PWM_DUTYCYCLE_REG_WR_VALUE[4]; /*!< (@ 0x00000058) Duty cycle Value + __IOM unsigned int PWM_DUTYCYCLE_REG_WR_VALUE[4]; /*!< (@ 0x00000058) Duty cycle Value Register for Channel0 to channel3 */ struct { - __IOM uint32_t PWM_DUTYCYCLE_REG_WR_VALUE_CH : 16; /*!< [15..0] Duty cycle value for + __IOM unsigned int PWM_DUTYCYCLE_REG_WR_VALUE_CH : 16; /*!< [15..0] Duty cycle value for channel0 to channel3 */ - __IM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ } PWM_DUTYCYCLE_REG_WR_VALUE_b[4]; }; - __IM uint32_t RESERVED2[4]; + __IM unsigned int RESERVED2[4]; union { - __IOM uint32_t PWM_DEADTIME_CTRL_SET_REG; /*!< (@ 0x00000078) Dead time + __IOM unsigned int PWM_DEADTIME_CTRL_SET_REG; /*!< (@ 0x00000078) Dead time Control Set Register */ struct { - __IOM uint32_t DEADTIME_SELECT_ACTIVE : 4; /*!< [3..0] Dead time select bits for PWM + __IOM unsigned int DEADTIME_SELECT_ACTIVE : 4; /*!< [3..0] Dead time select bits for PWM going active */ - __IOM uint32_t DEADTIME_SELECT_INACTIVE : 4; /*!< [7..4] Dead time select bits for + __IOM unsigned int DEADTIME_SELECT_INACTIVE : 4; /*!< [7..4] Dead time select bits for PWM going inactive */ - __IOM uint32_t DEADTIME_DISABLE_FRM_REG : 4; /*!< [11..8] Dead time counter soft + __IOM unsigned int DEADTIME_DISABLE_FRM_REG : 4; /*!< [11..8] Dead time counter soft reset for each channel. */ - __IM uint32_t RESERVED1 : 20; /*!< [31..12] reserved1 */ + __IM unsigned int RESERVED1 : 20; /*!< [31..12] reserved1 */ } PWM_DEADTIME_CTRL_SET_REG_b; }; union { - __IOM uint32_t PWM_DEADTIME_CTRL_RESET_REG; /*!< (@ 0x0000007C) Dead time + __IOM unsigned int PWM_DEADTIME_CTRL_RESET_REG; /*!< (@ 0x0000007C) Dead time Control Reset Register */ struct { - __IOM uint32_t DEADTIME_SELECT_ACTIVE : 4; /*!< [3..0] Dead time select bits for PWM + __IOM unsigned int DEADTIME_SELECT_ACTIVE : 4; /*!< [3..0] Dead time select bits for PWM going active */ - __IOM uint32_t DEADTIME_SELECT_INACTIVE : 4; /*!< [7..4] Dead time select bits for + __IOM unsigned int DEADTIME_SELECT_INACTIVE : 4; /*!< [7..4] Dead time select bits for PWM going inactive */ - __IOM uint32_t DEADTIME_DISABLE_FRM_REG : 4; /*!< [11..8] Dead time counter soft + __IOM unsigned int DEADTIME_DISABLE_FRM_REG : 4; /*!< [11..8] Dead time counter soft reset for each channel. */ - __IM uint32_t RESERVED1 : 20; /*!< [31..12] reserved1 */ + __IM unsigned int RESERVED1 : 20; /*!< [31..12] reserved1 */ } PWM_DEADTIME_CTRL_RESET_REG_b; }; union { - __IOM uint32_t PWM_DEADTIME_PRESCALE_SELECT_A; /*!< (@ 0x00000080) Dead time Prescale + __IOM unsigned int PWM_DEADTIME_PRESCALE_SELECT_A; /*!< (@ 0x00000080) Dead time Prescale Select Register for A */ struct { - __IOM uint32_t DEADTIME_PRESCALE_SELECT_A : 8; /*!< [7..0] Dead time prescale + __IOM unsigned int DEADTIME_PRESCALE_SELECT_A : 8; /*!< [7..0] Dead time prescale selection bits for unit A. */ - __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ } PWM_DEADTIME_PRESCALE_SELECT_A_b; }; union { - __IOM uint32_t PWM_DEADTIME_PRESCALE_SELECT_B; /*!< (@ 0x00000084) Dead time Prescale + __IOM unsigned int PWM_DEADTIME_PRESCALE_SELECT_B; /*!< (@ 0x00000084) Dead time Prescale Select Register for B */ struct { - __IOM uint32_t DEADTIME_PRESCALE_SELECT_B : 8; /*!< [7..0] Dead time prescale + __IOM unsigned int DEADTIME_PRESCALE_SELECT_B : 8; /*!< [7..0] Dead time prescale selection bits for unit B */ - __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ } PWM_DEADTIME_PRESCALE_SELECT_B_b; }; __IOM MCPWM_PWM_DEADTIME_Type PWM_DEADTIME[4]; /*!< (@ 0x00000088) [0..3] */ - __IM uint32_t RESERVED3[8]; + __IM unsigned int RESERVED3[8]; union { - __IOM uint32_t PWM_OP_OVERRIDE_CTRL_SET_REG; /*!< (@ 0x000000C8) output override + __IOM unsigned int PWM_OP_OVERRIDE_CTRL_SET_REG; /*!< (@ 0x000000C8) output override control set register */ struct { - __IOM uint32_t OP_OVERRIDE_SYNC : 1; /*!< [0..0] Output override is synced with pwm + __IOM unsigned int OP_OVERRIDE_SYNC : 1; /*!< [0..0] Output override is synced with pwm time period depending on operating mode */ - __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ } PWM_OP_OVERRIDE_CTRL_SET_REG_b; }; union { - __IOM uint32_t PWM_OP_OVERRIDE_CTRL_RESET_REG; /*!< (@ 0x000000CC) output override + __IOM unsigned int PWM_OP_OVERRIDE_CTRL_RESET_REG; /*!< (@ 0x000000CC) output override control reset register */ struct { - __IOM uint32_t OP_OVERRIDE_SYNC : 1; /*!< [0..0] Output override is synced with pwm + __IOM unsigned int OP_OVERRIDE_SYNC : 1; /*!< [0..0] Output override is synced with pwm time period depending on operating mode */ - __IOM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + __IOM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ } PWM_OP_OVERRIDE_CTRL_RESET_REG_b; }; union { - __IOM uint32_t PWM_OP_OVERRIDE_ENABLE_SET_REG; /*!< (@ 0x000000D0) output override + __IOM unsigned int PWM_OP_OVERRIDE_ENABLE_SET_REG; /*!< (@ 0x000000D0) output override enable set register */ struct { - __IOM uint32_t PWM_OP_OVERRIDE_ENABLE_REG : 8; /*!< [7..0] Pwm output over + __IOM unsigned int PWM_OP_OVERRIDE_ENABLE_REG : 8; /*!< [7..0] Pwm output over ride enable */ - __IOM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + __IOM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ } PWM_OP_OVERRIDE_ENABLE_SET_REG_b; }; union { - __IOM uint32_t PWM_OP_OVERRIDE_ENABLE_RESET_REG; /*!< (@ 0x000000D4) output override + __IOM unsigned int PWM_OP_OVERRIDE_ENABLE_RESET_REG; /*!< (@ 0x000000D4) output override enable reset register */ struct { - __IOM uint32_t PWM_OP_OVERRIDE_ENABLE_REG : 8; /*!< [7..0] Pwm output over + __IOM unsigned int PWM_OP_OVERRIDE_ENABLE_REG : 8; /*!< [7..0] Pwm output over ride enable */ - __IOM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + __IOM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ } PWM_OP_OVERRIDE_ENABLE_RESET_REG_b; }; union { - __IOM uint32_t PWM_OP_OVERRIDE_VALUE_SET_REG; /*!< (@ 0x000000D8) output override value + __IOM unsigned int PWM_OP_OVERRIDE_VALUE_SET_REG; /*!< (@ 0x000000D8) output override value set register */ struct { - __IOM uint32_t OP_OVERRIDE_VALUE : 8; /*!< [7..0] Pwm output over ride value. */ - __IOM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + __IOM unsigned int OP_OVERRIDE_VALUE : 8; /*!< [7..0] Pwm output over ride value. */ + __IOM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ } PWM_OP_OVERRIDE_VALUE_SET_REG_b; }; union { - __IOM uint32_t PWM_OP_OVERRIDE_VALUE_RESET_REG; /*!< (@ 0x000000DC) output override + __IOM unsigned int PWM_OP_OVERRIDE_VALUE_RESET_REG; /*!< (@ 0x000000DC) output override enable reset register */ struct { - __IOM uint32_t OP_OVERRIDE_VALUE : 8; /*!< [7..0] Pwm output over ride value. */ - __IOM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + __IOM unsigned int OP_OVERRIDE_VALUE : 8; /*!< [7..0] Pwm output over ride value. */ + __IOM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ } PWM_OP_OVERRIDE_VALUE_RESET_REG_b; }; union { - __IOM uint32_t PWM_FLT_OVERRIDE_CTRL_SET_REG; /*!< (@ 0x000000E0) fault override + __IOM unsigned int PWM_FLT_OVERRIDE_CTRL_SET_REG; /*!< (@ 0x000000E0) fault override control set register */ struct { - __IOM uint32_t FLT_A_MODE : 1; /*!< [0..0] Fault A mode */ - __IOM uint32_t FLT_B_MODE : 1; /*!< [1..1] Fault B mode */ - __IOM uint32_t OP_POLARITY_H : 1; /*!< [2..2] Ouput polarity for high (H3, + __IOM unsigned int FLT_A_MODE : 1; /*!< [0..0] Fault A mode */ + __IOM unsigned int FLT_B_MODE : 1; /*!< [1..1] Fault B mode */ + __IOM unsigned int OP_POLARITY_H : 1; /*!< [2..2] Ouput polarity for high (H3, H2, H1, H0) side signals */ - __IOM uint32_t OP_POLARITY_L : 1; /*!< [3..3] Ouput polarity for low (L3, + __IOM unsigned int OP_POLARITY_L : 1; /*!< [3..3] Ouput polarity for low (L3, L2, L1, L0) side signals. */ - __IOM uint32_t FLT_A_ENABLE : 4; /*!< [7..4] Fault A enable. Separate + __IOM unsigned int FLT_A_ENABLE : 4; /*!< [7..4] Fault A enable. Separate enable bit is present for channel */ - __IOM uint32_t FLT_B_ENABLE : 4; /*!< [11..8] Fault B enable. Separate + __IOM unsigned int FLT_B_ENABLE : 4; /*!< [11..8] Fault B enable. Separate enable bit is present for channel */ - __IOM uint32_t COMPLEMENTARY_MODE : 4; /*!< [15..12] PWM I/O pair mode */ - __IOM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + __IOM unsigned int COMPLEMENTARY_MODE : 4; /*!< [15..12] PWM I/O pair mode */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ } PWM_FLT_OVERRIDE_CTRL_SET_REG_b; }; union { - __IOM uint32_t PWM_FLT_OVERRIDE_CTRL_RESET_REG; /*!< (@ 0x000000E4) fault override + __IOM unsigned int PWM_FLT_OVERRIDE_CTRL_RESET_REG; /*!< (@ 0x000000E4) fault override control reset register */ struct { - __IOM uint32_t FLT_A_MODE : 1; /*!< [0..0] Fault B mode */ - __IOM uint32_t FLT_B_MODE : 1; /*!< [1..1] Fault B mode */ - __IOM uint32_t OP_POLARITY_H : 1; /*!< [2..2] Ouput polarity for high (H3, + __IOM unsigned int FLT_A_MODE : 1; /*!< [0..0] Fault B mode */ + __IOM unsigned int FLT_B_MODE : 1; /*!< [1..1] Fault B mode */ + __IOM unsigned int OP_POLARITY_H : 1; /*!< [2..2] Ouput polarity for high (H3, H2, H1, H0) side signals */ - __IOM uint32_t OP_POLARITY_L : 1; /*!< [3..3] Ouput polarity for low (L3, + __IOM unsigned int OP_POLARITY_L : 1; /*!< [3..3] Ouput polarity for low (L3, L2, L1, L0) side signals. */ - __IOM uint32_t FLT_A_ENABLE : 4; /*!< [7..4] Fault A enable. Separate + __IOM unsigned int FLT_A_ENABLE : 4; /*!< [7..4] Fault A enable. Separate enable bit is present for channel */ - __IOM uint32_t FLT_B_ENABLE : 4; /*!< [11..8] Fault B enable. Separate + __IOM unsigned int FLT_B_ENABLE : 4; /*!< [11..8] Fault B enable. Separate enable bit is present for channel */ - __IOM uint32_t COMPLEMENTARY_MODE : 4; /*!< [15..12] PWM I/O pair mode */ - __IOM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + __IOM unsigned int COMPLEMENTARY_MODE : 4; /*!< [15..12] PWM I/O pair mode */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ } PWM_FLT_OVERRIDE_CTRL_RESET_REG_b; }; union { - __IOM uint32_t PWM_FLT_A_OVERRIDE_VALUE_REG; /*!< (@ 0x000000E8) Fault input + __IOM unsigned int PWM_FLT_A_OVERRIDE_VALUE_REG; /*!< (@ 0x000000E8) Fault input A PWM override value */ struct { - __IOM uint32_t PWM_FLT_A_OVERRIDE_VALUE_L0 : 1; /*!< [0..0] 0 bit for L0 */ - __IOM uint32_t PWM_FLT_A_OVERRIDE_VALUE_L1 : 1; /*!< [1..1] 1 bit for L1 */ - __IOM uint32_t PWM_FLT_A_OVERRIDE_VALUE_L2 : 1; /*!< [2..2] 2 bit for L2 */ - __IOM uint32_t PWM_FLT_A_OVERRIDE_VALUE_L3 : 1; /*!< [3..3] 3 bit for L3 */ - __IOM uint32_t PWM_FLT_A_OVERRIDE_VALUE_H0 : 1; /*!< [4..4] 4 bit for H0 */ - __IOM uint32_t PWM_FLT_A_OVERRIDE_VALUE_H1 : 1; /*!< [5..5] 5 bit for H1 */ - __IOM uint32_t PWM_FLT_A_OVERRIDE_VALUE_H2 : 1; /*!< [6..6] 6 bit for H2 */ - __IOM uint32_t PWM_FLT_A_OVERRIDE_VALUE_H3 : 1; /*!< [7..7] 7 bit for H3 */ - __IOM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + __IOM unsigned int PWM_FLT_A_OVERRIDE_VALUE_L0 : 1; /*!< [0..0] 0 bit for L0 */ + __IOM unsigned int PWM_FLT_A_OVERRIDE_VALUE_L1 : 1; /*!< [1..1] 1 bit for L1 */ + __IOM unsigned int PWM_FLT_A_OVERRIDE_VALUE_L2 : 1; /*!< [2..2] 2 bit for L2 */ + __IOM unsigned int PWM_FLT_A_OVERRIDE_VALUE_L3 : 1; /*!< [3..3] 3 bit for L3 */ + __IOM unsigned int PWM_FLT_A_OVERRIDE_VALUE_H0 : 1; /*!< [4..4] 4 bit for H0 */ + __IOM unsigned int PWM_FLT_A_OVERRIDE_VALUE_H1 : 1; /*!< [5..5] 5 bit for H1 */ + __IOM unsigned int PWM_FLT_A_OVERRIDE_VALUE_H2 : 1; /*!< [6..6] 6 bit for H2 */ + __IOM unsigned int PWM_FLT_A_OVERRIDE_VALUE_H3 : 1; /*!< [7..7] 7 bit for H3 */ + __IOM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ } PWM_FLT_A_OVERRIDE_VALUE_REG_b; }; union { - __IOM uint32_t PWM_FLT_B_OVERRIDE_VALUE_REG; /*!< (@ 0x000000EC) Fault input + __IOM unsigned int PWM_FLT_B_OVERRIDE_VALUE_REG; /*!< (@ 0x000000EC) Fault input B PWM override value */ struct { - __IOM uint32_t PWM_FLT_B_OVERRIDE_VALUE_L0 : 1; /*!< [0..0] 0 bit for L0 */ - __IOM uint32_t PWM_FLT_B_OVERRIDE_VALUE_L1 : 1; /*!< [1..1] 1 bit for L1 */ - __IOM uint32_t PWM_FLT_B_OVERRIDE_VALUE_L2 : 1; /*!< [2..2] 2 bit for L2 */ - __IOM uint32_t PWM_FLT_B_OVERRIDE_VALUE_L3 : 1; /*!< [3..3] 3 bit for L3 */ - __IOM uint32_t PWM_FLT_B_OVERRIDE_VALUE_H0 : 1; /*!< [4..4] 4 bit for H0 */ - __IOM uint32_t PWM_FLT_B_OVERRIDE_VALUE_H1 : 1; /*!< [5..5] 5 bit for H1 */ - __IOM uint32_t PWM_FLT_B_OVERRIDE_VALUE_H2 : 1; /*!< [6..6] 6 bit for H2 */ - __IOM uint32_t PWM_FLT_B_OVERRIDE_VALUE_H3 : 1; /*!< [7..7] 7 bit for H3 */ - __IOM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + __IOM unsigned int PWM_FLT_B_OVERRIDE_VALUE_L0 : 1; /*!< [0..0] 0 bit for L0 */ + __IOM unsigned int PWM_FLT_B_OVERRIDE_VALUE_L1 : 1; /*!< [1..1] 1 bit for L1 */ + __IOM unsigned int PWM_FLT_B_OVERRIDE_VALUE_L2 : 1; /*!< [2..2] 2 bit for L2 */ + __IOM unsigned int PWM_FLT_B_OVERRIDE_VALUE_L3 : 1; /*!< [3..3] 3 bit for L3 */ + __IOM unsigned int PWM_FLT_B_OVERRIDE_VALUE_H0 : 1; /*!< [4..4] 4 bit for H0 */ + __IOM unsigned int PWM_FLT_B_OVERRIDE_VALUE_H1 : 1; /*!< [5..5] 5 bit for H1 */ + __IOM unsigned int PWM_FLT_B_OVERRIDE_VALUE_H2 : 1; /*!< [6..6] 6 bit for H2 */ + __IOM unsigned int PWM_FLT_B_OVERRIDE_VALUE_H3 : 1; /*!< [7..7] 7 bit for H3 */ + __IOM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ } PWM_FLT_B_OVERRIDE_VALUE_REG_b; }; union { - __IOM uint32_t PWM_SVT_CTRL_SET_REG; /*!< (@ 0x000000F0) NONE */ + __IOM unsigned int PWM_SVT_CTRL_SET_REG; /*!< (@ 0x000000F0) NONE */ struct { - __IOM uint32_t SVT_ENABLE_FRM : 1; /*!< [0..0] Special event trigger enable. This is + __IOM unsigned int SVT_ENABLE_FRM : 1; /*!< [0..0] Special event trigger enable. This is used to enable generation special event trigger */ - __IOM uint32_t SVT_DIRECTION_FRM : 1; /*!< [1..1] Special event trigger + __IOM unsigned int SVT_DIRECTION_FRM : 1; /*!< [1..1] Special event trigger for time base direction */ - __IOM uint32_t RESERVED1 : 30; /*!< [31..2] reserved1 */ + __IOM unsigned int RESERVED1 : 30; /*!< [31..2] reserved1 */ } PWM_SVT_CTRL_SET_REG_b; }; union { - __IOM uint32_t PWM_SVT_CTRL_RESET_REG; /*!< (@ 0x000000F4) Special event + __IOM unsigned int PWM_SVT_CTRL_RESET_REG; /*!< (@ 0x000000F4) Special event control reset register */ struct { - __IOM uint32_t SVT_ENABLE_FRM : 1; /*!< [0..0] Special event trigger enable. This is + __IOM unsigned int SVT_ENABLE_FRM : 1; /*!< [0..0] Special event trigger enable. This is used to enable generation special event trigger */ - __IOM uint32_t SVT_DIRECTION_FRM : 1; /*!< [1..1] Special event trigger + __IOM unsigned int SVT_DIRECTION_FRM : 1; /*!< [1..1] Special event trigger for time base direction */ - __IOM uint32_t RESERVED1 : 30; /*!< [31..2] reserved1 */ + __IOM unsigned int RESERVED1 : 30; /*!< [31..2] reserved1 */ } PWM_SVT_CTRL_RESET_REG_b; }; union { - __IOM uint32_t PWM_SVT_PARAM_REG; /*!< (@ 0x000000F8) Special event + __IOM unsigned int PWM_SVT_PARAM_REG; /*!< (@ 0x000000F8) Special event parameter register */ struct { - __IOM uint32_t SVT_POSTSCALER_SELECT : 4; /*!< [3..0] PWM special event trigger + __IOM unsigned int SVT_POSTSCALER_SELECT : 4; /*!< [3..0] PWM special event trigger output postscale select bits */ - __IOM uint32_t RESERVED1 : 28; /*!< [31..4] reserved1 */ + __IOM unsigned int RESERVED1 : 28; /*!< [31..4] reserved1 */ } PWM_SVT_PARAM_REG_b; }; union { - __IOM uint32_t PWM_SVT_COMPARE_VALUE_REG; /*!< (@ 0x000000FC) Special event + __IOM unsigned int PWM_SVT_COMPARE_VALUE_REG; /*!< (@ 0x000000FC) Special event compare value register */ struct { - __IOM uint32_t PWM_SVT_COMPARE_VALUE : 16; /*!< [15..0] Special event compare value. + __IOM unsigned int PWM_SVT_COMPARE_VALUE : 16; /*!< [15..0] Special event compare value. This is used to compare with pwm time period counter to generate special event trigger */ - __IOM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ } PWM_SVT_COMPARE_VALUE_REG_b; }; union { - __IOM uint32_t PWM_TIME_PRD_WR_REG_CH1; /*!< (@ 0x00000100) Base timer + __IOM unsigned int PWM_TIME_PRD_WR_REG_CH1; /*!< (@ 0x00000100) Base timer period register of channel1 */ struct { - __IOM uint32_t PWM_TIME_PRD_REG_WR_VALUE_CH1 : 16; /*!< [15..0] Value to update the + __IOM unsigned int PWM_TIME_PRD_REG_WR_VALUE_CH1 : 16; /*!< [15..0] Value to update the base timer period register of channel 1 */ - __IOM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ } PWM_TIME_PRD_WR_REG_CH1_b; }; union { - __IOM uint32_t PWM_TIME_PRD_CNTR_WR_REG_CH1; /*!< (@ 0x00000104) Base time + __IOM unsigned int PWM_TIME_PRD_CNTR_WR_REG_CH1; /*!< (@ 0x00000104) Base time counter initial value register for channel1 */ struct { - __IOM uint32_t PWM_TIME_PRD_CNTR_WR_REG_CH1 : 16; /*!< [15..0] To update the base + __IOM unsigned int PWM_TIME_PRD_CNTR_WR_REG_CH1 : 16; /*!< [15..0] To update the base time counter initial value for channel 1 */ - __IOM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ } PWM_TIME_PRD_CNTR_WR_REG_CH1_b; }; union { - __IOM uint32_t PWM_TIME_PRD_PARAM_REG_CH1; /*!< (@ 0x00000108) NONE */ + __IOM unsigned int PWM_TIME_PRD_PARAM_REG_CH1; /*!< (@ 0x00000108) NONE */ struct { - __IOM uint32_t TMR_OPEARATING_MODE_CH1 : 3; /*!< [2..0] Base timer operating mode for + __IOM unsigned int TMR_OPEARATING_MODE_CH1 : 3; /*!< [2..0] Base timer operating mode for channel1 */ - __IOM uint32_t RESERVED1 : 1; /*!< [3..3] reserved1 */ - __IOM uint32_t PWM_TIME_PRD_PRE_SCALAR_VALUE_CH1 : 3; /*!< [6..4] Base timer input + __IOM unsigned int RESERVED1 : 1; /*!< [3..3] reserved1 */ + __IOM unsigned int PWM_TIME_PRD_PRE_SCALAR_VALUE_CH1 : 3; /*!< [6..4] Base timer input clock prescale select value for channel1. */ - __IOM uint32_t RESERVED2 : 1; /*!< [7..7] reserved2 */ - __IOM uint32_t PWM_TIME_PRD_POST_SCALAR_VALUE_CH1 : 4; /*!< [11..8] Time base output + __IOM unsigned int RESERVED2 : 1; /*!< [7..7] reserved2 */ + __IOM unsigned int PWM_TIME_PRD_POST_SCALAR_VALUE_CH1 : 4; /*!< [11..8] Time base output post scale bits for channel1 */ - __IOM uint32_t RESERVED3 : 20; /*!< [31..12] reserved3 */ + __IOM unsigned int RESERVED3 : 20; /*!< [31..12] reserved3 */ } PWM_TIME_PRD_PARAM_REG_CH1_b; }; union { - __IOM uint32_t PWM_TIME_PRD_CTRL_REG_CH1; /*!< (@ 0x0000010C) Base time period control + __IOM unsigned int PWM_TIME_PRD_CTRL_REG_CH1; /*!< (@ 0x0000010C) Base time period control register for channel1 */ struct { - __IOM uint32_t PWM_TIME_PRD_CNTR_RST_FRM_REG : 1; /*!< [0..0] Time period counter + __IOM unsigned int PWM_TIME_PRD_CNTR_RST_FRM_REG : 1; /*!< [0..0] Time period counter soft reset */ - __IOM uint32_t PWM_TIME_BASE_EN_FRM_REG_CH1 : 1; /*!< [1..1] Base timer enable for + __IOM unsigned int PWM_TIME_BASE_EN_FRM_REG_CH1 : 1; /*!< [1..1] Base timer enable for channnel1 */ - __IOM uint32_t PWM_SFT_RST : 1; /*!< [2..2] MC PWM soft reset */ - __IOM uint32_t RESERVED1 : 29; /*!< [31..3] reserved1 */ + __IOM unsigned int PWM_SFT_RST : 1; /*!< [2..2] MC PWM soft reset */ + __IOM unsigned int RESERVED1 : 29; /*!< [31..3] reserved1 */ } PWM_TIME_PRD_CTRL_REG_CH1_b; }; union { - __IM uint32_t PWM_TIME_PRD_STS_REG_CH1; /*!< (@ 0x00000110) Base time period + __IM unsigned int PWM_TIME_PRD_STS_REG_CH1; /*!< (@ 0x00000110) Base time period status register for channel1 */ struct { - __IM uint32_t PWM_TIME_PRD_DIR_STS_CH1 : 1; /*!< [0..0] Time period counter + __IM unsigned int PWM_TIME_PRD_DIR_STS_CH1 : 1; /*!< [0..0] Time period counter direction status for channel1. */ - __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ } PWM_TIME_PRD_STS_REG_CH1_b; }; union { - __IOM uint32_t PWM_TIME_PRD_CNTR_VALUE_CH1; /*!< (@ 0x00000114) Time period counter + __IOM unsigned int PWM_TIME_PRD_CNTR_VALUE_CH1; /*!< (@ 0x00000114) Time period counter current value for channel1 */ struct { - __IOM uint32_t PWM_TIME_PRD_CNTR_VALUE_CH1 : 1; /*!< [0..0] Time period counter + __IOM unsigned int PWM_TIME_PRD_CNTR_VALUE_CH1 : 1; /*!< [0..0] Time period counter current value for channel1 */ - __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ } PWM_TIME_PRD_CNTR_VALUE_CH1_b; }; union { - __IOM uint32_t PWM_TIME_PRD_WR_REG_CH2; /*!< (@ 0x00000118) Base timer + __IOM unsigned int PWM_TIME_PRD_WR_REG_CH2; /*!< (@ 0x00000118) Base timer period register of channel2 */ struct { - __IOM uint32_t PWM_TIME_PRD_REG_WR_VALUE_CH2 : 16; /*!< [15..0] Value to update the + __IOM unsigned int PWM_TIME_PRD_REG_WR_VALUE_CH2 : 16; /*!< [15..0] Value to update the base timer period register of channel 2 */ - __IOM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ } PWM_TIME_PRD_WR_REG_CH2_b; }; union { - __IOM uint32_t PWM_TIME_PRD_CNTR_WR_REG_CH2; /*!< (@ 0x0000011C) Base time + __IOM unsigned int PWM_TIME_PRD_CNTR_WR_REG_CH2; /*!< (@ 0x0000011C) Base time counter initial value register for channel2 */ struct { - __IOM uint32_t PWM_TIME_PRD_CNTR_WR_REG_CH2 : 16; /*!< [15..0] To update the base + __IOM unsigned int PWM_TIME_PRD_CNTR_WR_REG_CH2 : 16; /*!< [15..0] To update the base time counter initial value for channel 2 */ - __IOM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ } PWM_TIME_PRD_CNTR_WR_REG_CH2_b; }; union { - __IOM uint32_t PWM_TIME_PRD_PARAM_REG_CH2; /*!< (@ 0x00000120) Base time period config + __IOM unsigned int PWM_TIME_PRD_PARAM_REG_CH2; /*!< (@ 0x00000120) Base time period config parameter's register for channel2 */ struct { - __IOM uint32_t TMR_OPEARATING_MODE_CH2 : 3; /*!< [2..0] Base timer operating mode for + __IOM unsigned int TMR_OPEARATING_MODE_CH2 : 3; /*!< [2..0] Base timer operating mode for channel2 */ - __IOM uint32_t RESERVED1 : 1; /*!< [3..3] reserved1 */ - __IOM uint32_t PWM_TIME_PRD_PRE_SCALAR_VALUE_CH2 : 3; /*!< [6..4] Base timer input + __IOM unsigned int RESERVED1 : 1; /*!< [3..3] reserved1 */ + __IOM unsigned int PWM_TIME_PRD_PRE_SCALAR_VALUE_CH2 : 3; /*!< [6..4] Base timer input clock pre scale select value for channel2. */ - __IOM uint32_t RESERVED2 : 1; /*!< [7..7] reserved2 */ - __IOM uint32_t PWM_TIME_PRD_POST_SCALAR_VALUE_CH2 : 4; /*!< [11..8] Time base output + __IOM unsigned int RESERVED2 : 1; /*!< [7..7] reserved2 */ + __IOM unsigned int PWM_TIME_PRD_POST_SCALAR_VALUE_CH2 : 4; /*!< [11..8] Time base output post scale bits for channel2 */ - __IOM uint32_t RESERVED3 : 20; /*!< [31..12] reserved3 */ + __IOM unsigned int RESERVED3 : 20; /*!< [31..12] reserved3 */ } PWM_TIME_PRD_PARAM_REG_CH2_b; }; union { - __IOM uint32_t PWM_TIME_PRD_CTRL_REG_CH2; /*!< (@ 0x00000124) Base time period control + __IOM unsigned int PWM_TIME_PRD_CTRL_REG_CH2; /*!< (@ 0x00000124) Base time period control register for channel2 */ struct { - __IOM uint32_t PWM_TIME_PRD_CNTR_RST_FRM_REG : 1; /*!< [0..0] Time period counter + __IOM unsigned int PWM_TIME_PRD_CNTR_RST_FRM_REG : 1; /*!< [0..0] Time period counter soft reset */ - __IOM uint32_t PWM_TIME_BASE_EN_FRM_REG_CH2 : 1; /*!< [1..1] Base timer enable for + __IOM unsigned int PWM_TIME_BASE_EN_FRM_REG_CH2 : 1; /*!< [1..1] Base timer enable for channnel2 */ - __IOM uint32_t PWM_SFT_RST : 1; /*!< [2..2] MC PWM soft reset */ - __IOM uint32_t RESERVED1 : 29; /*!< [31..3] reserved1 */ + __IOM unsigned int PWM_SFT_RST : 1; /*!< [2..2] MC PWM soft reset */ + __IOM unsigned int RESERVED1 : 29; /*!< [31..3] reserved1 */ } PWM_TIME_PRD_CTRL_REG_CH2_b; }; union { - __IM uint32_t PWM_TIME_PRD_STS_REG_CH2; /*!< (@ 0x00000128) Base time period + __IM unsigned int PWM_TIME_PRD_STS_REG_CH2; /*!< (@ 0x00000128) Base time period status register for channel2 */ struct { - __IM uint32_t PWM_TIME_PRD_DIR_STS_CH2 : 1; /*!< [0..0] Time period counter + __IM unsigned int PWM_TIME_PRD_DIR_STS_CH2 : 1; /*!< [0..0] Time period counter direction status for channel2. */ - __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ } PWM_TIME_PRD_STS_REG_CH2_b; }; union { - __IM uint32_t PWM_TIME_PRD_CNTR_VALUE_CH2; /*!< (@ 0x0000012C) Time period counter + __IM unsigned int PWM_TIME_PRD_CNTR_VALUE_CH2; /*!< (@ 0x0000012C) Time period counter current value register for channel2 */ struct { - __IM uint32_t PWM_TIME_PRD_CNTR_VALUE_CH2 : 1; /*!< [0..0] Time period counter + __IM unsigned int PWM_TIME_PRD_CNTR_VALUE_CH2 : 1; /*!< [0..0] Time period counter current value for channel2 */ - __IM uint32_t RESERVED1 : 11; /*!< [11..1] reserved1 */ - __IM uint32_t RESERVED2 : 20; /*!< [31..12] reserved2 */ + __IM unsigned int RESERVED1 : 11; /*!< [11..1] reserved1 */ + __IM unsigned int RESERVED2 : 20; /*!< [31..12] reserved2 */ } PWM_TIME_PRD_CNTR_VALUE_CH2_b; }; union { - __IOM uint32_t PWM_TIME_PRD_WR_REG_CH3; /*!< (@ 0x00000130) Base timer + __IOM unsigned int PWM_TIME_PRD_WR_REG_CH3; /*!< (@ 0x00000130) Base timer period register of channel3 */ struct { - __IOM uint32_t PWM_TIME_PRD_REG_WR_VALUE_CH3 : 16; /*!< [15..0] To update the base + __IOM unsigned int PWM_TIME_PRD_REG_WR_VALUE_CH3 : 16; /*!< [15..0] To update the base time counter initial value for channel 3 */ - __IOM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ } PWM_TIME_PRD_WR_REG_CH3_b; }; union { - __IOM uint32_t PWM_TIME_PRD_CNTR_WR_REG_CH3; /*!< (@ 0x00000134) Base time + __IOM unsigned int PWM_TIME_PRD_CNTR_WR_REG_CH3; /*!< (@ 0x00000134) Base time counter initial value register for channel3 */ struct { - __IOM uint32_t PWM_TIME_PRD_CNTR_WR_REG_CH3 : 16; /*!< [15..0] Value to update the + __IOM unsigned int PWM_TIME_PRD_CNTR_WR_REG_CH3 : 16; /*!< [15..0] Value to update the base timer period register of channel 3 */ - __IOM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ } PWM_TIME_PRD_CNTR_WR_REG_CH3_b; }; union { - __IOM uint32_t PWM_TIME_PRD_PARAM_REG_CH3; /*!< (@ 0x00000138) Base time period config + __IOM unsigned int PWM_TIME_PRD_PARAM_REG_CH3; /*!< (@ 0x00000138) Base time period config parameter's register for channel3 */ struct { - __IOM uint32_t TMR_OPEARATING_MODE_CH3 : 3; /*!< [2..0] Base timer operating mode for + __IOM unsigned int TMR_OPEARATING_MODE_CH3 : 3; /*!< [2..0] Base timer operating mode for channel3 */ - __IOM uint32_t RESERVED1 : 1; /*!< [3..3] reserved1 */ - __IOM uint32_t PWM_TIME_PRD_PRE_SCALAR_VALUE_CH3 : 3; /*!< [6..4] Base timer input + __IOM unsigned int RESERVED1 : 1; /*!< [3..3] reserved1 */ + __IOM unsigned int PWM_TIME_PRD_PRE_SCALAR_VALUE_CH3 : 3; /*!< [6..4] Base timer input clock pre scale select value for channel2. */ - __IOM uint32_t RESERVED2 : 1; /*!< [7..7] reserved2 */ - __IOM uint32_t PWM_TIME_PRD_POST_SCALAR_VALUE_CH3 : 4; /*!< [11..8] Time base output + __IOM unsigned int RESERVED2 : 1; /*!< [7..7] reserved2 */ + __IOM unsigned int PWM_TIME_PRD_POST_SCALAR_VALUE_CH3 : 4; /*!< [11..8] Time base output post scale bits for channel3 */ - __IOM uint32_t RESERVED3 : 20; /*!< [31..12] reserved3 */ + __IOM unsigned int RESERVED3 : 20; /*!< [31..12] reserved3 */ } PWM_TIME_PRD_PARAM_REG_CH3_b; }; union { - __IOM uint32_t PWM_TIME_PRD_CTRL_REG_CH3; /*!< (@ 0x0000013C) Base time period control + __IOM unsigned int PWM_TIME_PRD_CTRL_REG_CH3; /*!< (@ 0x0000013C) Base time period control register for channel3 */ struct { - __IOM uint32_t PWM_TIME_PRD_CNTR_RST_FRM_REG : 1; /*!< [0..0] Time period counter + __IOM unsigned int PWM_TIME_PRD_CNTR_RST_FRM_REG : 1; /*!< [0..0] Time period counter soft reset */ - __IOM uint32_t PWM_TIME_BASE_EN_FRM_REG_CH3 : 1; /*!< [1..1] Base timer enable for + __IOM unsigned int PWM_TIME_BASE_EN_FRM_REG_CH3 : 1; /*!< [1..1] Base timer enable for channnel3 */ - __IOM uint32_t PWM_SFT_RST : 1; /*!< [2..2] MC PWM soft reset */ - __IOM uint32_t RESERVED1 : 29; /*!< [31..3] reserved1 */ + __IOM unsigned int PWM_SFT_RST : 1; /*!< [2..2] MC PWM soft reset */ + __IOM unsigned int RESERVED1 : 29; /*!< [31..3] reserved1 */ } PWM_TIME_PRD_CTRL_REG_CH3_b; }; union { - __IM uint32_t PWM_TIME_PRD_STS_REG_CH3; /*!< (@ 0x00000140) Base time period + __IM unsigned int PWM_TIME_PRD_STS_REG_CH3; /*!< (@ 0x00000140) Base time period status register for channel3 */ struct { - __IM uint32_t PWM_TIME_PRD_DIR_STS_CH3 : 1; /*!< [0..0] Time period counter + __IM unsigned int PWM_TIME_PRD_DIR_STS_CH3 : 1; /*!< [0..0] Time period counter direction status for channel3. */ - __IM uint32_t RESERVED1 : 15; /*!< [15..1] reserved1 */ - __IM uint32_t RESERVED2 : 16; /*!< [31..16] reserved2 */ + __IM unsigned int RESERVED1 : 15; /*!< [15..1] reserved1 */ + __IM unsigned int RESERVED2 : 16; /*!< [31..16] reserved2 */ } PWM_TIME_PRD_STS_REG_CH3_b; }; union { - __IM uint32_t PWM_TIME_PRD_CNTR_VALUE_CH3; /*!< (@ 0x00000144) Time period counter + __IM unsigned int PWM_TIME_PRD_CNTR_VALUE_CH3; /*!< (@ 0x00000144) Time period counter current value register for channel3 */ struct { - __IM uint32_t PWM_TIME_PRD_CNTR_VALUE_CH3 : 16; /*!< [15..0] Time period counter + __IM unsigned int PWM_TIME_PRD_CNTR_VALUE_CH3 : 16; /*!< [15..0] Time period counter current value for channe3 */ - __IM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ } PWM_TIME_PRD_CNTR_VALUE_CH3_b; }; union { - __IOM uint32_t PWM_TIME_PRD_COMMON_REG; /*!< (@ 0x00000148) Time period + __IOM unsigned int PWM_TIME_PRD_COMMON_REG; /*!< (@ 0x00000148) Time period common register */ struct { - __IOM uint32_t PWM_TIME_PRD_USE_0TH_TIMER_ONLY : 1; /*!< [0..0] Instead of use four + __IOM unsigned int PWM_TIME_PRD_USE_0TH_TIMER_ONLY : 1; /*!< [0..0] Instead of use four base timers for four channels, use only one base timer for all channels. */ - __IOM uint32_t PWM_TIME_PRD_COMMON_TIMER_VALUE : 2; /*!< [2..1] Base timers select to + __IOM unsigned int PWM_TIME_PRD_COMMON_TIMER_VALUE : 2; /*!< [2..1] Base timers select to generate special event trigger */ - __IOM uint32_t USE_EXT_TIMER_TRIG_FRM_REG : 1; /*!< [3..3] Enable to use external + __IOM unsigned int USE_EXT_TIMER_TRIG_FRM_REG : 1; /*!< [3..3] Enable to use external trigger for base time counter increment or decrement. */ - __IOM uint32_t RESERVED1 : 28; /*!< [31..4] reserved1 */ + __IOM unsigned int RESERVED1 : 28; /*!< [31..4] reserved1 */ } PWM_TIME_PRD_COMMON_REG_b; }; } MCPWM_Type; /*!< Size = 332 (0x14c) */ @@ -2783,28 +2783,28 @@ typedef struct { /*!< (@ 0x47070000) MCPWM Structure */ typedef struct { /*!< (@ 0x44030000) UDMA0 Structure */ union { - __IM uint32_t DMA_STATUS; /*!< (@ 0x00000000) UDMA Status Register */ + __IM unsigned int DMA_STATUS; /*!< (@ 0x00000000) UDMA Status Register */ struct { - __IM uint32_t MASTER_ENABLE : 1; /*!< [0..0] Enable status of controller */ - __IM uint32_t RESERVED1 : 3; /*!< [3..1] Reserved1 */ - __IM uint32_t STATE : 4; /*!< [7..4] Current state of the control state machine */ - __IM uint32_t RESERVED2 : 8; /*!< [15..8] Reserved2 */ - __IM uint32_t CHNLS_MINUS1 : 5; /*!< [20..16] Number of available DMA + __IM unsigned int MASTER_ENABLE : 1; /*!< [0..0] Enable status of controller */ + __IM unsigned int RESERVED1 : 3; /*!< [3..1] Reserved1 */ + __IM unsigned int STATE : 4; /*!< [7..4] Current state of the control state machine */ + __IM unsigned int RESERVED2 : 8; /*!< [15..8] Reserved2 */ + __IM unsigned int CHNLS_MINUS1 : 5; /*!< [20..16] Number of available DMA channels minus one */ - __IM uint32_t RESERVED3 : 7; /*!< [27..21] Reserved3 */ - __IM uint32_t TEST_STATUS : 4; /*!< [31..28] To reduce the gate count you + __IM unsigned int RESERVED3 : 7; /*!< [27..21] Reserved3 */ + __IM unsigned int TEST_STATUS : 4; /*!< [31..28] To reduce the gate count you can configure the controller */ } DMA_STATUS_b; }; union { - __OM uint32_t DMA_CFG; /*!< (@ 0x00000004) DMA Configuration */ + __OM unsigned int DMA_CFG; /*!< (@ 0x00000004) DMA Configuration */ struct { - __OM uint32_t MASTER_ENABLE : 1; /*!< [0..0] Enable for the controller */ - __OM uint32_t RESERVED1 : 4; /*!< [4..1] Reserved1 */ - __OM uint32_t CHNL_PROT_CTRL : 3; /*!< [7..5] Sets the AHB-Lite protection by + __OM unsigned int MASTER_ENABLE : 1; /*!< [0..0] Enable for the controller */ + __OM unsigned int RESERVED1 : 4; /*!< [4..1] Reserved1 */ + __OM unsigned int CHNL_PROT_CTRL : 3; /*!< [7..5] Sets the AHB-Lite protection by controlling the HPROT[3:1]] signal levels as follows Bit[7]-Controls HPROT[3] to indicate if cacheable access is occurring Bit[6]-Controls @@ -2812,76 +2812,76 @@ typedef struct { /*!< (@ 0x44030000) UDMA0 Structure */ occurring Bit[5]-Controls HPROT[1] to indicate if cacheable access is occurring */ - __OM uint32_t RESERVED2 : 24; /*!< [31..8] Reserved2 */ + __OM unsigned int RESERVED2 : 24; /*!< [31..8] Reserved2 */ } DMA_CFG_b; }; union { - __IOM uint32_t CTRL_BASE_PTR; /*!< (@ 0x00000008) Channel Control Data Base + __IOM unsigned int CTRL_BASE_PTR; /*!< (@ 0x00000008) Channel Control Data Base Pointer */ struct { - __OM uint32_t RESERVED1 : 10; /*!< [9..0] Reserved1 */ - __IOM uint32_t CTRL_BASE_PTR : 22; /*!< [31..10] Pointer to the base address of the + __OM unsigned int RESERVED1 : 10; /*!< [9..0] Reserved1 */ + __IOM unsigned int CTRL_BASE_PTR : 22; /*!< [31..10] Pointer to the base address of the primary data structure */ } CTRL_BASE_PTR_b; }; union { - __IM uint32_t ALT_CTRL_BASE_PTR; /*!< (@ 0x0000000C) Channel Alternate + __IM unsigned int ALT_CTRL_BASE_PTR; /*!< (@ 0x0000000C) Channel Alternate Control Data Base Pointer */ struct { - __IM uint32_t ALT_CTRL_BASE_PTR : 32; /*!< [31..0] Base address of the + __IM unsigned int ALT_CTRL_BASE_PTR : 32; /*!< [31..0] Base address of the alternative data structure */ } ALT_CTRL_BASE_PTR_b; }; union { - __IM uint32_t DMA_WAITONREQUEST_STATUS; /*!< (@ 0x00000010) Channel Wait on + __IM unsigned int DMA_WAITONREQUEST_STATUS; /*!< (@ 0x00000010) Channel Wait on request status register */ struct { - __IM uint32_t DMA_WAITONREQ_STATUS : 32; /*!< [31..0] Per Channel wait on + __IM unsigned int DMA_WAITONREQ_STATUS : 32; /*!< [31..0] Per Channel wait on request status */ } DMA_WAITONREQUEST_STATUS_b; }; union { - __OM uint32_t CHNL_SW_REQUEST; /*!< (@ 0x00000014) Channel Software Request */ + __OM unsigned int CHNL_SW_REQUEST; /*!< (@ 0x00000014) Channel Software Request */ struct { - __OM uint32_t CHNL_SW_REQUEST : 32; /*!< [31..0] Set the appropriate bit to generate + __OM unsigned int CHNL_SW_REQUEST : 32; /*!< [31..0] Set the appropriate bit to generate a software DMA request on the corresponding DMA channel */ } CHNL_SW_REQUEST_b; }; union { - __IOM uint32_t CHNL_USEBURST_SET; /*!< (@ 0x00000018) UDMA Channel use burst set */ + __IOM unsigned int CHNL_USEBURST_SET; /*!< (@ 0x00000018) UDMA Channel use burst set */ struct { - __IOM uint32_t CHNL_USEBURST_SET : 32; /*!< [31..0] The use burst status, + __IOM unsigned int CHNL_USEBURST_SET : 32; /*!< [31..0] The use burst status, or disables dma_sreq[C] from generating DMA requests. */ } CHNL_USEBURST_SET_b; }; union { - __OM uint32_t CHNL_USEBURST_CLR; /*!< (@ 0x0000001C) UDMA Channel use burst clear */ + __OM unsigned int CHNL_USEBURST_CLR; /*!< (@ 0x0000001C) UDMA Channel use burst clear */ struct { - __OM uint32_t CHNL_USEBURST_CLR : 32; /*!< [31..0] Set the appropriate bit to enable + __OM unsigned int CHNL_USEBURST_CLR : 32; /*!< [31..0] Set the appropriate bit to enable dma_sreq[] to generate requests */ } CHNL_USEBURST_CLR_b; }; union { - __IOM uint32_t CHNL_REQ_MASK_SET; /*!< (@ 0x00000020) UDMA Channel request + __IOM unsigned int CHNL_REQ_MASK_SET; /*!< (@ 0x00000020) UDMA Channel request mask set Register */ struct { - __IOM uint32_t CHNL_REQ_MASK_SET : 32; /*!< [31..0] Returns the request mask status + __IOM unsigned int CHNL_REQ_MASK_SET : 32; /*!< [31..0] Returns the request mask status of dma_req[] and dma_sreq[], or disables the corresponding channel from generating DMA requests */ @@ -2889,11 +2889,11 @@ typedef struct { /*!< (@ 0x44030000) UDMA0 Structure */ }; union { - __OM uint32_t CHNL_REQ_MASK_CLR; /*!< (@ 0x00000024) UDMA Channel request + __OM unsigned int CHNL_REQ_MASK_CLR; /*!< (@ 0x00000024) UDMA Channel request mask clear */ struct { - __OM uint32_t CHNL_REQ_MASK_CLR : 32; /*!< [31..0] Set the appropriate bit + __OM unsigned int CHNL_REQ_MASK_CLR : 32; /*!< [31..0] Set the appropriate bit to enable DMA requests for the channel corresponding to dma_req[] and dma_sreq[] */ @@ -2901,30 +2901,30 @@ typedef struct { /*!< (@ 0x44030000) UDMA0 Structure */ }; union { - __IOM uint32_t CHNL_ENABLE_SET; /*!< (@ 0x00000028) UDMA Channel enable register */ + __IOM unsigned int CHNL_ENABLE_SET; /*!< (@ 0x00000028) UDMA Channel enable register */ struct { - __IOM uint32_t CHNL_ENABLE_SET : 32; /*!< [31..0] This Bits are Used to Load the + __IOM unsigned int CHNL_ENABLE_SET : 32; /*!< [31..0] This Bits are Used to Load the 16bits of Source address */ } CHNL_ENABLE_SET_b; }; union { - __OM uint32_t CHNL_ENABLE_CLR; /*!< (@ 0x0000002C) UDMA Channel enable clear + __OM unsigned int CHNL_ENABLE_CLR; /*!< (@ 0x0000002C) UDMA Channel enable clear register */ struct { - __OM uint32_t CHNL_ENABLE_CLR : 32; /*!< [31..0] Set the appropriate bit to disable + __OM unsigned int CHNL_ENABLE_CLR : 32; /*!< [31..0] Set the appropriate bit to disable the corresponding DMA channel */ } CHNL_ENABLE_CLR_b; }; union { - __IOM uint32_t CHNL_PRI_ALT_SET; /*!< (@ 0x00000030) UDMA Channel primary or + __IOM unsigned int CHNL_PRI_ALT_SET; /*!< (@ 0x00000030) UDMA Channel primary or alternate set */ struct { - __IOM uint32_t CHNL_PRI_ALT_SET : 32; /*!< [31..0] Returns the channel control data + __IOM unsigned int CHNL_PRI_ALT_SET : 32; /*!< [31..0] Returns the channel control data structure status or selects the alternate data structure for the corresponding DMA channel */ @@ -2932,265 +2932,265 @@ typedef struct { /*!< (@ 0x44030000) UDMA0 Structure */ }; union { - __OM uint32_t CHNL_PRI_ALT_CLR; /*!< (@ 0x00000034) UDMA Channel primary + __OM unsigned int CHNL_PRI_ALT_CLR; /*!< (@ 0x00000034) UDMA Channel primary alternate clear */ struct { - __OM uint32_t CHNL_PRI_ALT_CLR : 32; /*!< [31..0] Set the appropriate bit to select + __OM unsigned int CHNL_PRI_ALT_CLR : 32; /*!< [31..0] Set the appropriate bit to select the primary data structure for the corresponding DMA channel */ } CHNL_PRI_ALT_CLR_b; }; union { - __IOM uint32_t CHNL_PRIORITY_SET; /*!< (@ 0x00000038) UDMA Channel Priority Set */ + __IOM unsigned int CHNL_PRIORITY_SET; /*!< (@ 0x00000038) UDMA Channel Priority Set */ struct { - __IOM uint32_t CHNL_PRIORITY_SET : 32; /*!< [31..0] Set the appropriate bit to select + __IOM unsigned int CHNL_PRIORITY_SET : 32; /*!< [31..0] Set the appropriate bit to select the primary data structure for the corresponding DMA channel */ } CHNL_PRIORITY_SET_b; }; union { - __OM uint32_t CHNL_PRIORITY_CLR; /*!< (@ 0x0000003C) UDMA Channel Priority Clear */ + __OM unsigned int CHNL_PRIORITY_CLR; /*!< (@ 0x0000003C) UDMA Channel Priority Clear */ struct { - __OM uint32_t CHNL_PRIORITY_CLR : 32; /*!< [31..0] Set the appropriate bit to select + __OM unsigned int CHNL_PRIORITY_CLR : 32; /*!< [31..0] Set the appropriate bit to select the default priority level for the specified DMA channel */ } CHNL_PRIORITY_CLR_b; }; - __IM uint32_t RESERVED[3]; + __IM unsigned int RESERVED[3]; union { - __IOM uint32_t ERR_CLR; /*!< (@ 0x0000004C) UDMA Bus Error Clear Register */ + __IOM unsigned int ERR_CLR; /*!< (@ 0x0000004C) UDMA Bus Error Clear Register */ struct { - __IOM uint32_t ERR_CLR : 1; /*!< [0..0] Returns the status of dma_err */ - __IOM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved1 */ + __IOM unsigned int ERR_CLR : 1; /*!< [0..0] Returns the status of dma_err */ + __IOM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved1 */ } ERR_CLR_b; }; union { - __IOM uint32_t UDMA_SKIP_DESC_FETCH_REG; /*!< (@ 0x00000050) UDMA skip + __IOM unsigned int UDMA_SKIP_DESC_FETCH_REG; /*!< (@ 0x00000050) UDMA skip descriptor fetch Register */ struct { - __IOM uint32_t SKIP_DESC_FETCH : 32; /*!< [31..0] improving the + __IOM unsigned int SKIP_DESC_FETCH : 32; /*!< [31..0] improving the performance of transfer and saves bus cycles. This features has to be enabled always. */ } UDMA_SKIP_DESC_FETCH_REG_b; }; - __IM uint32_t RESERVED1[491]; + __IM unsigned int RESERVED1[491]; union { - __IOM uint32_t UDMA_DONE_STATUS_REG; /*!< (@ 0x00000800) UDMA Done status Register */ + __IOM unsigned int UDMA_DONE_STATUS_REG; /*!< (@ 0x00000800) UDMA Done status Register */ struct { - __IOM uint32_t DONE_STATUS_CHANNEL_0 : 1; /*!< [0..0] UDMA done Status of + __IOM unsigned int DONE_STATUS_CHANNEL_0 : 1; /*!< [0..0] UDMA done Status of the channel 0 */ - __IOM uint32_t DONE_STATUS_CHANNEL_1 : 1; /*!< [1..1] UDMA done Status of + __IOM unsigned int DONE_STATUS_CHANNEL_1 : 1; /*!< [1..1] UDMA done Status of the channel 1 */ - __IOM uint32_t DONE_STATUS_CHANNEL_2 : 1; /*!< [2..2] UDMA done Status of + __IOM unsigned int DONE_STATUS_CHANNEL_2 : 1; /*!< [2..2] UDMA done Status of the channel 2 */ - __IOM uint32_t DONE_STATUS_CHANNEL_3 : 1; /*!< [3..3] UDMA done Status of + __IOM unsigned int DONE_STATUS_CHANNEL_3 : 1; /*!< [3..3] UDMA done Status of the channel 3 */ - __IOM uint32_t DONE_STATUS_CHANNEL_4 : 1; /*!< [4..4] UDMA done Status of + __IOM unsigned int DONE_STATUS_CHANNEL_4 : 1; /*!< [4..4] UDMA done Status of the channel 4 */ - __IOM uint32_t DONE_STATUS_CHANNEL_5 : 1; /*!< [5..5] UDMA done Status of + __IOM unsigned int DONE_STATUS_CHANNEL_5 : 1; /*!< [5..5] UDMA done Status of the channel 5 */ - __IOM uint32_t DONE_STATUS_CHANNEL_6 : 1; /*!< [6..6] UDMA done Status of + __IOM unsigned int DONE_STATUS_CHANNEL_6 : 1; /*!< [6..6] UDMA done Status of the channel 6 */ - __IOM uint32_t DONE_STATUS_CHANNEL_7 : 1; /*!< [7..7] UDMA done Status of + __IOM unsigned int DONE_STATUS_CHANNEL_7 : 1; /*!< [7..7] UDMA done Status of the channel 7 */ - __IOM uint32_t DONE_STATUS_CHANNEL_8 : 1; /*!< [8..8] UDMA done Status of + __IOM unsigned int DONE_STATUS_CHANNEL_8 : 1; /*!< [8..8] UDMA done Status of the channel 8 */ - __IOM uint32_t DONE_STATUS_CHANNEL_9 : 1; /*!< [9..9] UDMA done Status of + __IOM unsigned int DONE_STATUS_CHANNEL_9 : 1; /*!< [9..9] UDMA done Status of the channel 9 */ - __IOM uint32_t DONE_STATUS_CHANNEL_10 : 1; /*!< [10..10] UDMA done Status + __IOM unsigned int DONE_STATUS_CHANNEL_10 : 1; /*!< [10..10] UDMA done Status of the channel 10 */ - __IOM uint32_t DONE_STATUS_CHANNEL_11 : 1; /*!< [11..11] UDMA done Status + __IOM unsigned int DONE_STATUS_CHANNEL_11 : 1; /*!< [11..11] UDMA done Status of the channel 3 */ - __IOM uint32_t DONE_STATUS_CHANNEL_12 : 1; /*!< [12..12] UDMA done Status + __IOM unsigned int DONE_STATUS_CHANNEL_12 : 1; /*!< [12..12] UDMA done Status of the channel 12 */ - __IOM uint32_t DONE_STATUS_CHANNEL_13 : 1; /*!< [13..13] UDMA done Status + __IOM unsigned int DONE_STATUS_CHANNEL_13 : 1; /*!< [13..13] UDMA done Status of the channel 13 */ - __IOM uint32_t DONE_STATUS_CHANNEL_14 : 1; /*!< [14..14] UDMA done Status + __IOM unsigned int DONE_STATUS_CHANNEL_14 : 1; /*!< [14..14] UDMA done Status of the channel 14 */ - __IOM uint32_t DONE_STATUS_CHANNEL_15 : 1; /*!< [15..15] UDMA done Status + __IOM unsigned int DONE_STATUS_CHANNEL_15 : 1; /*!< [15..15] UDMA done Status of the channel 15 */ - __IOM uint32_t DONE_STATUS_CHANNEL_16 : 1; /*!< [16..16] UDMA done Status + __IOM unsigned int DONE_STATUS_CHANNEL_16 : 1; /*!< [16..16] UDMA done Status of the channel 16 */ - __IOM uint32_t DONE_STATUS_CHANNEL_17 : 1; /*!< [17..17] UDMA done Status + __IOM unsigned int DONE_STATUS_CHANNEL_17 : 1; /*!< [17..17] UDMA done Status of the channel 17 */ - __IOM uint32_t DONE_STATUS_CHANNEL_18 : 1; /*!< [18..18] UDMA done Status + __IOM unsigned int DONE_STATUS_CHANNEL_18 : 1; /*!< [18..18] UDMA done Status of the channel 18 */ - __IOM uint32_t DONE_STATUS_CHANNEL_19 : 1; /*!< [19..19] UDMA done Status + __IOM unsigned int DONE_STATUS_CHANNEL_19 : 1; /*!< [19..19] UDMA done Status of the channel 19 */ - __IOM uint32_t DONE_STATUS_CHANNEL_20 : 1; /*!< [20..20] UDMA done Status + __IOM unsigned int DONE_STATUS_CHANNEL_20 : 1; /*!< [20..20] UDMA done Status of the channel 3 */ - __IOM uint32_t DONE_STATUS_CHANNEL_21 : 1; /*!< [21..21] UDMA done Status + __IOM unsigned int DONE_STATUS_CHANNEL_21 : 1; /*!< [21..21] UDMA done Status of the channel 21 */ - __IOM uint32_t DONE_STATUS_CHANNEL_22 : 1; /*!< [22..22] UDMA done Status + __IOM unsigned int DONE_STATUS_CHANNEL_22 : 1; /*!< [22..22] UDMA done Status of the channel 22 */ - __IOM uint32_t DONE_STATUS_CHANNEL_23 : 1; /*!< [23..23] UDMA done Status + __IOM unsigned int DONE_STATUS_CHANNEL_23 : 1; /*!< [23..23] UDMA done Status of the channel 23 */ - __IOM uint32_t DONE_STATUS_CHANNEL_24 : 1; /*!< [24..24] UDMA done Status + __IOM unsigned int DONE_STATUS_CHANNEL_24 : 1; /*!< [24..24] UDMA done Status of the channel 24 */ - __IOM uint32_t DONE_STATUS_CHANNEL_25 : 1; /*!< [25..25] UDMA done Status + __IOM unsigned int DONE_STATUS_CHANNEL_25 : 1; /*!< [25..25] UDMA done Status of the channel 25 */ - __IOM uint32_t DONE_STATUS_CHANNEL_26 : 1; /*!< [26..26] UDMA done Status + __IOM unsigned int DONE_STATUS_CHANNEL_26 : 1; /*!< [26..26] UDMA done Status of the channel 26 */ - __IOM uint32_t DONE_STATUS_CHANNEL_27 : 1; /*!< [27..27] UDMA done Status + __IOM unsigned int DONE_STATUS_CHANNEL_27 : 1; /*!< [27..27] UDMA done Status of the channel 27 */ - __IOM uint32_t DONE_STATUS_CHANNEL_28 : 1; /*!< [28..28] UDMA done Status + __IOM unsigned int DONE_STATUS_CHANNEL_28 : 1; /*!< [28..28] UDMA done Status of the channel 28 */ - __IOM uint32_t DONE_STATUS_CHANNEL_29 : 1; /*!< [29..29] UDMA done Status + __IOM unsigned int DONE_STATUS_CHANNEL_29 : 1; /*!< [29..29] UDMA done Status of the channel 29 */ - __IOM uint32_t DONE_STATUS_CHANNEL_30 : 1; /*!< [30..30] UDMA done Status + __IOM unsigned int DONE_STATUS_CHANNEL_30 : 1; /*!< [30..30] UDMA done Status of the channel 30 */ - __IOM uint32_t DONE_STATUS_CHANNEL_31 : 1; /*!< [31..31] UDMA done Status + __IOM unsigned int DONE_STATUS_CHANNEL_31 : 1; /*!< [31..31] UDMA done Status of the channel 31 */ } UDMA_DONE_STATUS_REG_b; }; union { - __IM uint32_t CHANNEL_STATUS_REG; /*!< (@ 0x00000804) Channel status Register */ + __IM unsigned int CHANNEL_STATUS_REG; /*!< (@ 0x00000804) Channel status Register */ struct { - __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_0 : 1; /*!< [0..0] Reading 1 indicates + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_0 : 1; /*!< [0..0] Reading 1 indicates that the channel 0 is busy */ - __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_1 : 1; /*!< [1..1] Reading 1 indicates + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_1 : 1; /*!< [1..1] Reading 1 indicates that the channel 1 is busy */ - __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_2 : 1; /*!< [2..2] Reading 1 indicates + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_2 : 1; /*!< [2..2] Reading 1 indicates that the channel 2 is busy */ - __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_3 : 1; /*!< [3..3] Reading 1 indicates + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_3 : 1; /*!< [3..3] Reading 1 indicates that the channel 3 is busy */ - __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_4 : 1; /*!< [4..4] Reading 1 indicates + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_4 : 1; /*!< [4..4] Reading 1 indicates that the channel 4 is busy */ - __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_5 : 1; /*!< [5..5] Reading 1 indicates + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_5 : 1; /*!< [5..5] Reading 1 indicates that the channel 5 is busy */ - __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_6 : 1; /*!< [6..6] Reading 1 indicates + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_6 : 1; /*!< [6..6] Reading 1 indicates that the channel 6 is busy */ - __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_7 : 1; /*!< [7..7] Reading 1 indicates + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_7 : 1; /*!< [7..7] Reading 1 indicates that the channel 7 is busy */ - __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_8 : 1; /*!< [8..8] Reading 1 indicates + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_8 : 1; /*!< [8..8] Reading 1 indicates that the channel 8 is busy */ - __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_9 : 1; /*!< [9..9] Reading 1 indicates + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_9 : 1; /*!< [9..9] Reading 1 indicates that the channel 9 is busy */ - __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_10 : 1; /*!< [10..10] Reading 1 + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_10 : 1; /*!< [10..10] Reading 1 indicates that the channel 10 is busy */ - __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_11 : 1; /*!< [11..11] Reading 1 + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_11 : 1; /*!< [11..11] Reading 1 indicates that the channel 11 is busy */ - __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_12 : 1; /*!< [12..12] Reading 1 + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_12 : 1; /*!< [12..12] Reading 1 indicates that the channel 12 is busy */ - __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_13 : 1; /*!< [13..13] Reading 1 + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_13 : 1; /*!< [13..13] Reading 1 indicates that the channel 13 is busy */ - __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_14 : 1; /*!< [14..14] Reading 1 + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_14 : 1; /*!< [14..14] Reading 1 indicates that the channel 14 is busy */ - __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_15 : 1; /*!< [15..15] Reading 1 + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_15 : 1; /*!< [15..15] Reading 1 indicates that the channel 15 is busy */ - __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_16 : 1; /*!< [16..16] Reading 1 + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_16 : 1; /*!< [16..16] Reading 1 indicates that the channel 16 is busy */ - __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_17 : 1; /*!< [17..17] Reading 1 + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_17 : 1; /*!< [17..17] Reading 1 indicates that the channel 17 is busy */ - __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_18 : 1; /*!< [18..18] Reading 1 + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_18 : 1; /*!< [18..18] Reading 1 indicates that the channel 18 is busy */ - __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_19 : 1; /*!< [19..19] Reading 1 + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_19 : 1; /*!< [19..19] Reading 1 indicates that the channel 19 is busy */ - __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_20 : 1; /*!< [20..20] Reading 1 + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_20 : 1; /*!< [20..20] Reading 1 indicates that the channel 20 is busy */ - __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_21 : 1; /*!< [21..21] Reading 1 + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_21 : 1; /*!< [21..21] Reading 1 indicates that the channel 21 is busy */ - __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_22 : 1; /*!< [22..22] Reading 1 + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_22 : 1; /*!< [22..22] Reading 1 indicates that the channel 22 is busy */ - __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_23 : 1; /*!< [23..23] Reading 1 + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_23 : 1; /*!< [23..23] Reading 1 indicates that the channel 23 is busy */ - __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_24 : 1; /*!< [24..24] Reading 1 + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_24 : 1; /*!< [24..24] Reading 1 indicates that the channel 24 is busy */ - __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_25 : 1; /*!< [25..25] Reading 1 + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_25 : 1; /*!< [25..25] Reading 1 indicates that the channel 25 is busy */ - __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_26 : 1; /*!< [26..26] Reading 1 + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_26 : 1; /*!< [26..26] Reading 1 indicates that the channel 26 is busy */ - __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_27 : 1; /*!< [27..27] Reading 1 + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_27 : 1; /*!< [27..27] Reading 1 indicates that the channel 27 is busy */ - __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_28 : 1; /*!< [28..28] Reading 1 + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_28 : 1; /*!< [28..28] Reading 1 indicates that the channel 28 is busy */ - __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_29 : 1; /*!< [29..29] Reading 1 + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_29 : 1; /*!< [29..29] Reading 1 indicates that the channel 29 is busy */ - __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_30 : 1; /*!< [30..30] Reading 1 + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_30 : 1; /*!< [30..30] Reading 1 indicates that the channel 30 is busy */ - __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_31 : 1; /*!< [31..31] Reading 1 + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_31 : 1; /*!< [31..31] Reading 1 indicates that the channel 31 is busy */ } CHANNEL_STATUS_REG_b; }; - __IM uint32_t RESERVED2[8]; + __IM unsigned int RESERVED2[8]; union { - __IOM uint32_t UDMA_CONFIG_CTRL_REG; /*!< (@ 0x00000828) DMA Controller + __IOM unsigned int UDMA_CONFIG_CTRL_REG; /*!< (@ 0x00000828) DMA Controller Transfer Length Register */ struct { - __IOM uint32_t SINGLE_REQUEST_ENABLE : 1; /*!< [0..0] Enabled signal for + __IOM unsigned int SINGLE_REQUEST_ENABLE : 1; /*!< [0..0] Enabled signal for single request */ - __IOM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use. */ + __IOM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use. */ } UDMA_CONFIG_CTRL_REG_b; }; union { - __IOM uint32_t UDMA_INTR_MASK_REG; /*!< (@ 0x0000082C) Mask the uDMA + __IOM unsigned int UDMA_INTR_MASK_REG; /*!< (@ 0x0000082C) Mask the uDMA interrupt register */ struct { - __IOM uint32_t UDMA_INTR_MASK : 12; /*!< [11..0] Mask the uDMA interrupt + __IOM unsigned int UDMA_INTR_MASK : 12; /*!< [11..0] Mask the uDMA interrupt register */ - __IM uint32_t RESERVED1 : 20; /*!< [31..12] RESERVED1 */ + __IM unsigned int RESERVED1 : 20; /*!< [31..12] RESERVED1 */ } UDMA_INTR_MASK_REG_b; }; } UDMA0_Type; /*!< Size = 2096 (0x830) */ @@ -3208,7 +3208,7 @@ typedef struct { /*!< (@ 0x44030000) UDMA0 Structure */ */ typedef struct { /*!< (@ 0x21080000) GPDMA_G Structure */ - __IM uint32_t RESERVED[1057]; + __IM unsigned int RESERVED[1057]; __IOM GPDMA_G_GLOBAL_Type GLOBAL; /*!< (@ 0x00001084) GLOBAL */ } GPDMA_G_Type; /*!< Size = 4252 (0x109c) */ @@ -3244,26 +3244,26 @@ typedef struct { /*!< (@ 0x21081004) GPDMA typedef struct { /*!< (@ 0x45090000) HWRNG Structure */ union { - __IOM uint32_t HWRNG_CTRL_REG; /*!< (@ 0x00000000) Random Number Generator + __IOM unsigned int HWRNG_CTRL_REG; /*!< (@ 0x00000000) Random Number Generator Control Register */ struct { - __IOM uint32_t HWRNG_RNG_ST : 1; /*!< [0..0] This bit is used to start the + __IOM unsigned int HWRNG_RNG_ST : 1; /*!< [0..0] This bit is used to start the true number generation. */ - __IOM uint32_t HWRNG_PRBS_ST : 1; /*!< [1..1] This bit is used to start the pseudo + __IOM unsigned int HWRNG_PRBS_ST : 1; /*!< [1..1] This bit is used to start the pseudo random number generation */ - __IOM uint32_t SOFT_RESET : 1; /*!< [2..2] This bit is used to start the + __IOM unsigned int SOFT_RESET : 1; /*!< [2..2] This bit is used to start the pseudo random number generation */ - __IM uint32_t RESERVED1 : 29; /*!< [31..3] RESERVED1 */ + __IM unsigned int RESERVED1 : 29; /*!< [31..3] RESERVED1 */ } HWRNG_CTRL_REG_b; }; union { - __IM uint32_t HWRNG_RAND_NUM_REG; /*!< (@ 0x00000004) Hardware Random Number + __IM unsigned int HWRNG_RAND_NUM_REG; /*!< (@ 0x00000004) Hardware Random Number Register */ struct { - __IM uint32_t HWRNG_RAND_NUM : 32; /*!< [31..0] Generated random number + __IM unsigned int HWRNG_RAND_NUM : 32; /*!< [31..0] Generated random number can be read from this register. */ } HWRNG_RAND_NUM_REG_b; }; @@ -3283,87 +3283,87 @@ typedef struct { /*!< (@ 0x45090000) HWRNG Structure */ typedef struct { /*!< (@ 0x24042000) TIMERS Structure */ __IOM TIMERS_MATCH_CTRL_Type MATCH_CTRL[4]; /*!< (@ 0x00000000) [0..3] */ - __IM uint32_t RESERVED[24]; + __IM unsigned int RESERVED[24]; union { - __IOM uint32_t MCUULP_TMR_INTR_STAT; /*!< (@ 0x00000080) Timer Status Register */ + __IOM unsigned int MCUULP_TMR_INTR_STAT; /*!< (@ 0x00000080) Timer Status Register */ struct { - __IOM uint32_t TMR0_INTR_STATUS : 1; /*!< [0..0] This bit indicates status of the + __IOM unsigned int TMR0_INTR_STATUS : 1; /*!< [0..0] This bit indicates status of the interrupt generated by timer 0 */ - __IOM uint32_t TMR1_INTR_STATUS : 1; /*!< [1..1] This bit indicates status of the + __IOM unsigned int TMR1_INTR_STATUS : 1; /*!< [1..1] This bit indicates status of the interrupt generated by timer 1 */ - __IOM uint32_t TMR2_INTR_STATUS : 1; /*!< [2..2] This bit indicates status of the + __IOM unsigned int TMR2_INTR_STATUS : 1; /*!< [2..2] This bit indicates status of the interrupt generated by timer 2 */ - __IOM uint32_t TMR3_INTR_STATUS : 1; /*!< [3..3] This bit indicates status of the + __IOM unsigned int TMR3_INTR_STATUS : 1; /*!< [3..3] This bit indicates status of the interrupt generated by timer 3 */ - __IM uint32_t RESERVED1 : 28; /*!< [31..4] reserved1 */ + __IM unsigned int RESERVED1 : 28; /*!< [31..4] reserved1 */ } MCUULP_TMR_INTR_STAT_b; }; union { - __IOM uint32_t MCUULP_TMR_US_PERIOD_INT; /*!< (@ 0x00000084) Timer micro second period + __IOM unsigned int MCUULP_TMR_US_PERIOD_INT; /*!< (@ 0x00000084) Timer micro second period Integral Part Register */ struct { - __IOM uint32_t TMR_US_PERIOD_INT : 16; /*!< [15..0] This bits are used to program the + __IOM unsigned int TMR_US_PERIOD_INT : 16; /*!< [15..0] This bits are used to program the integer part of number of clock cycles per microseconds of the system clock used */ - __IM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ } MCUULP_TMR_US_PERIOD_INT_b; }; union { - __IOM uint32_t MCUULP_TMR_US_PERIOD_FRAC; /*!< (@ 0x00000088) Timer microsecond period + __IOM unsigned int MCUULP_TMR_US_PERIOD_FRAC; /*!< (@ 0x00000088) Timer microsecond period Fractional Part Register */ struct { - __IOM uint32_t TMR_US_PERIOD_FRAC : 8; /*!< [7..0] This bits are used to program the + __IOM unsigned int TMR_US_PERIOD_FRAC : 8; /*!< [7..0] This bits are used to program the fractional part of number of clock cycles per microseconds of the system clock used */ - __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ } MCUULP_TMR_US_PERIOD_FRAC_b; }; union { - __IOM uint32_t MCUULP_TMR_MS_PERIOD_INT; /*!< (@ 0x0000008C) Timer 256 microsecond + __IOM unsigned int MCUULP_TMR_MS_PERIOD_INT; /*!< (@ 0x0000008C) Timer 256 microsecond period Integral Part Register */ struct { - __IOM uint32_t TMR_MS_PERIOD_INT : 16; /*!< [15..0] This bits are used to program the + __IOM unsigned int TMR_MS_PERIOD_INT : 16; /*!< [15..0] This bits are used to program the integer part of number of clock cycles per 256 microseconds of the system clock used */ - __IM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ } MCUULP_TMR_MS_PERIOD_INT_b; }; union { - __IOM uint32_t MCUULP_TMR_MS_PERIOD_FRAC; /*!< (@ 0x00000090) Timer 256 microsecond + __IOM unsigned int MCUULP_TMR_MS_PERIOD_FRAC; /*!< (@ 0x00000090) Timer 256 microsecond period Fractional Part Register */ struct { - __IOM uint32_t TMR_MS_PERIOD_FRAC : 8; /*!< [7..0] This bits are used to program the + __IOM unsigned int TMR_MS_PERIOD_FRAC : 8; /*!< [7..0] This bits are used to program the fractional part of number of clock cycles per 256 microseconds of the system clock used */ - __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ } MCUULP_TMR_MS_PERIOD_FRAC_b; }; - __IM uint32_t RESERVED1[2]; + __IM unsigned int RESERVED1[2]; union { - __IM uint32_t MCUULP_TMR_ACTIVE_STATUS; /*!< (@ 0x0000009C) Timer Active + __IM unsigned int MCUULP_TMR_ACTIVE_STATUS; /*!< (@ 0x0000009C) Timer Active Status Register */ struct { - __IM uint32_t TIMER_ACTIVE : 4; /*!< [3..0] Timer active status for each + __IM unsigned int TIMER_ACTIVE : 4; /*!< [3..0] Timer active status for each timer. LSB bit specifies the status for 0th timer and so on. */ - __IM uint32_t RESERVED1 : 28; /*!< [31..4] reserved1 */ + __IM unsigned int RESERVED1 : 28; /*!< [31..4] reserved1 */ } MCUULP_TMR_ACTIVE_STATUS_b; }; } TIMERS_Type; /*!< Size = 160 (0xa0) */ @@ -3383,315 +3383,315 @@ typedef struct { /*!< (@ 0x24042000) TIMERS Structu typedef struct { /*!< (@ 0x47060000) QEI Structure */ union { - __IM uint32_t QEI_STATUS_REG; /*!< (@ 0x00000000) Quadrature Encoder status + __IM unsigned int QEI_STATUS_REG; /*!< (@ 0x00000000) Quadrature Encoder status register */ struct { - __IM uint32_t QEI_INDEX : 1; /*!< [0..0] This is a direct value from the + __IM unsigned int QEI_INDEX : 1; /*!< [0..0] This is a direct value from the position signal generator */ - __IM uint32_t QEI_POSITION_B : 1; /*!< [1..1] This is a direct value from the + __IM unsigned int QEI_POSITION_B : 1; /*!< [1..1] This is a direct value from the position signal generator.Value refers to the signal Position_B from the generator. */ - __IM uint32_t QEI_POSITION_A : 1; /*!< [2..2] This is a direct value from the + __IM unsigned int QEI_POSITION_A : 1; /*!< [2..2] This is a direct value from the position signal generator.Value refers to the signal Position_A from the generator. */ - __IM uint32_t POSITION_CNTR_ERR : 1; /*!< [3..3] Count Error Status Flag bit */ - __IM uint32_t POSITION_CNTR_DIRECTION : 1; /*!< [4..4] Position Counter + __IM unsigned int POSITION_CNTR_ERR : 1; /*!< [3..3] Count Error Status Flag bit */ + __IM unsigned int POSITION_CNTR_DIRECTION : 1; /*!< [4..4] Position Counter Direction Status bit */ - __IM uint32_t RESERVED1 : 27; /*!< [31..5] Reserved1 */ + __IM unsigned int RESERVED1 : 27; /*!< [31..5] Reserved1 */ } QEI_STATUS_REG_b; }; union { - __IOM uint32_t QEI_CTRL_REG_SET; /*!< (@ 0x00000004) Quadrature Encoder + __IOM unsigned int QEI_CTRL_REG_SET; /*!< (@ 0x00000004) Quadrature Encoder control set register */ struct { - __IM uint32_t QEI_SFT_RST : 1; /*!< [0..0] Quadrature encoder soft reset. + __IM unsigned int QEI_SFT_RST : 1; /*!< [0..0] Quadrature encoder soft reset. It is self reset signal. */ - __IOM uint32_t QEI_SWAP_PHASE_AB : 1; /*!< [1..1] Phase A and Phase B + __IOM unsigned int QEI_SWAP_PHASE_AB : 1; /*!< [1..1] Phase A and Phase B Input Swap Select bit */ - __IOM uint32_t POS_CNT_RST_WITH_INDEX_EN : 1; /*!< [2..2] Phase A and Phase B Input + __IOM unsigned int POS_CNT_RST_WITH_INDEX_EN : 1; /*!< [2..2] Phase A and Phase B Input Swap Select bit */ - __IOM uint32_t RESERVED1 : 1; /*!< [3..3] Reserved1 */ - __IOM uint32_t POS_CNT_DIRECTION_CTRL : 1; /*!< [4..4] NONE */ - __IOM uint32_t POS_CNT_DIR_FRM_REG : 1; /*!< [5..5] Position Counter Direction + __IOM unsigned int RESERVED1 : 1; /*!< [3..3] Reserved1 */ + __IOM unsigned int POS_CNT_DIRECTION_CTRL : 1; /*!< [4..4] NONE */ + __IOM unsigned int POS_CNT_DIR_FRM_REG : 1; /*!< [5..5] Position Counter Direction indication from user */ - __IOM uint32_t RESERVED2 : 1; /*!< [6..6] Reserved2 */ - __IOM uint32_t RESERVED3 : 1; /*!< [7..7] Reserved3 */ - __IOM uint32_t INDEX_CNT_RST_EN : 1; /*!< [8..8] Index count reset enable */ - __IOM uint32_t DIGITAL_FILTER_BYPASS : 1; /*!< [9..9] NONE */ - __IOM uint32_t TIMER_MODE : 1; /*!< [10..10] NONE */ - __IOM uint32_t START_VELOCITY_CNTR : 1; /*!< [11..11] Starting the velocity counter. + __IOM unsigned int RESERVED2 : 1; /*!< [6..6] Reserved2 */ + __IOM unsigned int RESERVED3 : 1; /*!< [7..7] Reserved3 */ + __IOM unsigned int INDEX_CNT_RST_EN : 1; /*!< [8..8] Index count reset enable */ + __IOM unsigned int DIGITAL_FILTER_BYPASS : 1; /*!< [9..9] NONE */ + __IOM unsigned int TIMER_MODE : 1; /*!< [10..10] NONE */ + __IOM unsigned int START_VELOCITY_CNTR : 1; /*!< [11..11] Starting the velocity counter. It is self reset bit. */ - __IOM uint32_t QEI_STOP_IN_IDLE : 1; /*!< [12..12] NONE */ - __IOM uint32_t QEI_POS_CNT_16_BIT_MODE : 1; /*!< [13..13] Qei position counter 16 bit + __IOM unsigned int QEI_STOP_IN_IDLE : 1; /*!< [12..12] NONE */ + __IOM unsigned int QEI_POS_CNT_16_BIT_MODE : 1; /*!< [13..13] Qei position counter 16 bit mode enable */ - __IOM uint32_t POS_CNT_RST : 1; /*!< [14..14] 1=position counter is going + __IOM unsigned int POS_CNT_RST : 1; /*!< [14..14] 1=position counter is going to reset */ - __IOM uint32_t INDEX_CNT_RST : 1; /*!< [15..15] 1= index counter is going + __IOM unsigned int INDEX_CNT_RST : 1; /*!< [15..15] 1= index counter is going to reset. */ - __IOM uint32_t RESERVED4 : 16; /*!< [31..16] Reserved4 */ + __IOM unsigned int RESERVED4 : 16; /*!< [31..16] Reserved4 */ } QEI_CTRL_REG_SET_b; }; union { - __IOM uint32_t QEI_CTRL_REG_RESET; /*!< (@ 0x00000008) Quadrature Encoder + __IOM unsigned int QEI_CTRL_REG_RESET; /*!< (@ 0x00000008) Quadrature Encoder control reset register */ struct { - __IM uint32_t QEI_SFT_RST : 1; /*!< [0..0] Quadrature encoder soft reset. + __IM unsigned int QEI_SFT_RST : 1; /*!< [0..0] Quadrature encoder soft reset. It is self reset signal */ - __IOM uint32_t QEI_SWAP_PHASE_AB : 1; /*!< [1..1] Phase A and Phase B + __IOM unsigned int QEI_SWAP_PHASE_AB : 1; /*!< [1..1] Phase A and Phase B Input Swap Select bit */ - __IOM uint32_t POS_CNT_RST_WITH_INDEX_EN : 1; /*!< [2..2] Phase A and Phase B Input + __IOM unsigned int POS_CNT_RST_WITH_INDEX_EN : 1; /*!< [2..2] Phase A and Phase B Input Swap Select bit */ - __IOM uint32_t RESERVED1 : 1; /*!< [3..3] Reserved1 */ - __IOM uint32_t POS_CNT_DIRECTION_CTRL : 1; /*!< [4..4] NONE */ - __IOM uint32_t POS_CNT_DIR_FRM_REG : 1; /*!< [5..5] Position Counter Direction + __IOM unsigned int RESERVED1 : 1; /*!< [3..3] Reserved1 */ + __IOM unsigned int POS_CNT_DIRECTION_CTRL : 1; /*!< [4..4] NONE */ + __IOM unsigned int POS_CNT_DIR_FRM_REG : 1; /*!< [5..5] Position Counter Direction indication from user */ - __IOM uint32_t RESERVED2 : 1; /*!< [6..6] Reserved2 */ - __IOM uint32_t RESERVED3 : 1; /*!< [7..7] Reserved3 */ - __IOM uint32_t INDEX_CNT_RST_EN : 1; /*!< [8..8] NONE */ - __IOM uint32_t DIGITAL_FILTER_BYPASS : 1; /*!< [9..9] NONE */ - __IOM uint32_t TIMER_MODE : 1; /*!< [10..10] NONE */ - __IOM uint32_t START_VELOCITY_CNTR : 1; /*!< [11..11] Starting the velocity counter. + __IOM unsigned int RESERVED2 : 1; /*!< [6..6] Reserved2 */ + __IOM unsigned int RESERVED3 : 1; /*!< [7..7] Reserved3 */ + __IOM unsigned int INDEX_CNT_RST_EN : 1; /*!< [8..8] NONE */ + __IOM unsigned int DIGITAL_FILTER_BYPASS : 1; /*!< [9..9] NONE */ + __IOM unsigned int TIMER_MODE : 1; /*!< [10..10] NONE */ + __IOM unsigned int START_VELOCITY_CNTR : 1; /*!< [11..11] Starting the velocity counter. It is self reset bit. */ - __IOM uint32_t QEI_STOP_IN_IDLE : 1; /*!< [12..12] NONE */ - __IOM uint32_t QEI_POS_CNT_16_BIT_MODE : 1; /*!< [13..13] Qei position counter 16 bit + __IOM unsigned int QEI_STOP_IN_IDLE : 1; /*!< [12..12] NONE */ + __IOM unsigned int QEI_POS_CNT_16_BIT_MODE : 1; /*!< [13..13] Qei position counter 16 bit mode enable */ - __IOM uint32_t POS_CNT_RST : 1; /*!< [14..14] 1=position counter is going + __IOM unsigned int POS_CNT_RST : 1; /*!< [14..14] 1=position counter is going to reset */ - __IOM uint32_t INDEX_CNT_RST : 1; /*!< [15..15] 1= index counter is going + __IOM unsigned int INDEX_CNT_RST : 1; /*!< [15..15] 1= index counter is going to reset. */ - __IOM uint32_t RESERVED4 : 16; /*!< [31..16] Reserved4 */ + __IOM unsigned int RESERVED4 : 16; /*!< [31..16] Reserved4 */ } QEI_CTRL_REG_RESET_b; }; union { - __IOM uint32_t QEI_CNTLR_INIT_REG; /*!< (@ 0x0000000C) Quadrature Encoder + __IOM unsigned int QEI_CNTLR_INIT_REG; /*!< (@ 0x0000000C) Quadrature Encoder initialization register */ struct { - __IOM uint32_t QEI_ENCODING_MODE : 2; /*!< [1..0] NONE */ - __IOM uint32_t RESERVED1 : 2; /*!< [3..2] Reserved1 */ - __IOM uint32_t INDEX_MATCH_VALUE : 2; /*!< [5..4] These bits allow user to specify + __IOM unsigned int QEI_ENCODING_MODE : 2; /*!< [1..0] NONE */ + __IOM unsigned int RESERVED1 : 2; /*!< [3..2] Reserved1 */ + __IOM unsigned int INDEX_MATCH_VALUE : 2; /*!< [5..4] These bits allow user to specify the state of position A and B during index pulse generation. */ - __IOM uint32_t DF_CLK_DIVIDE_SLT : 4; /*!< [9..6] Digital Filter Clock + __IOM unsigned int DF_CLK_DIVIDE_SLT : 4; /*!< [9..6] Digital Filter Clock Divide Select bits */ - __IOM uint32_t UNIDIRECTIONAL_VELOCITY : 1; /*!< [10..10] Uni directional + __IOM unsigned int UNIDIRECTIONAL_VELOCITY : 1; /*!< [10..10] Uni directional velocity enable. */ - __IOM uint32_t UNIDIRECTIONAL_INDEX : 1; /*!< [11..11] Uni directional + __IOM unsigned int UNIDIRECTIONAL_INDEX : 1; /*!< [11..11] Uni directional index enable. */ - __IOM uint32_t INDEX_CNT_INIT : 1; /*!< [12..12] Index counter initial value in + __IOM unsigned int INDEX_CNT_INIT : 1; /*!< [12..12] Index counter initial value in unidirectional index enable mode. */ - __IOM uint32_t RESERVED2 : 19; /*!< [31..13] Reserved2 */ + __IOM unsigned int RESERVED2 : 19; /*!< [31..13] Reserved2 */ } QEI_CNTLR_INIT_REG_b; }; union { - __IOM uint32_t QEI_INDEX_CNT_REG; /*!< (@ 0x00000010) Quadrature Encoder + __IOM unsigned int QEI_INDEX_CNT_REG; /*!< (@ 0x00000010) Quadrature Encoder index counter register */ struct { - __IOM uint32_t QEI_INDEX_CNT : 16; /*!< [15..0] Index counter value.User + __IOM unsigned int QEI_INDEX_CNT : 16; /*!< [15..0] Index counter value.User can initialize/change the index counter using this register */ - __IOM uint32_t QEI_INDEX_CNT_WR_VALUE : 16; /*!< [31..16] User can initialize/change + __IOM unsigned int QEI_INDEX_CNT_WR_VALUE : 16; /*!< [31..16] User can initialize/change the index counter using this register. */ } QEI_INDEX_CNT_REG_b; }; union { - __IOM uint32_t QEI_INDEX_MAX_CNT_REG; /*!< (@ 0x00000014) Quadrature Encoder maximum + __IOM unsigned int QEI_INDEX_MAX_CNT_REG; /*!< (@ 0x00000014) Quadrature Encoder maximum index counter value register */ struct { - __IOM uint32_t QEI_INDEX_MAX_CNT : 16; /*!< [15..0] This is a maximum count value + __IOM unsigned int QEI_INDEX_MAX_CNT : 16; /*!< [15..0] This is a maximum count value that is allowed to increment in the index counter. If index counter reaches this value, will get reset to zero */ - __IOM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved1 */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved1 */ } QEI_INDEX_MAX_CNT_REG_b; }; union { - __IOM uint32_t QEI_POSITION_CNT_REG; /*!< (@ 0x00000018) Quadrature Encoder maximum + __IOM unsigned int QEI_POSITION_CNT_REG; /*!< (@ 0x00000018) Quadrature Encoder maximum position counter value register */ struct { - __IOM uint32_t QEI_POSITION_CNT_WR_VALUE_L : 16; /*!< [15..0] This is a maximum count + __IOM unsigned int QEI_POSITION_CNT_WR_VALUE_L : 16; /*!< [15..0] This is a maximum count value that is allowed to increment in the position counter. */ - __IOM uint32_t QEI_POSITION_CNT_WR_VALUE_H : 16; /*!< [31..16] This is a maximum + __IOM unsigned int QEI_POSITION_CNT_WR_VALUE_H : 16; /*!< [31..16] This is a maximum count value that is allowed to increment in the position counter. */ } QEI_POSITION_CNT_REG_b; }; - __IM uint32_t RESERVED; + __IM unsigned int RESERVED; union { - __IOM uint32_t QEI_POSITION_MAX_CNT_LSW_REG; /*!< (@ 0x00000020) Quadrature + __IOM unsigned int QEI_POSITION_MAX_CNT_LSW_REG; /*!< (@ 0x00000020) Quadrature Encoder maximum position counter value register */ struct { - __IOM uint32_t QEI_POSITION_MAX_CNT_L : 16; /*!< [15..0] This is a maximum + __IOM unsigned int QEI_POSITION_MAX_CNT_L : 16; /*!< [15..0] This is a maximum count value that is allowed to increment in the position counter. */ - __IOM uint32_t QEI_POSITION_MAX_CNT_H : 16; /*!< [31..16] This is a maximum count + __IOM unsigned int QEI_POSITION_MAX_CNT_H : 16; /*!< [31..16] This is a maximum count value that is allowed to increment in the position counter. */ } QEI_POSITION_MAX_CNT_LSW_REG_b; }; - __IM uint32_t RESERVED1; + __IM unsigned int RESERVED1; union { - __IM uint32_t QEI_INTR_STS_REG; /*!< (@ 0x00000028) Quadrature Encoder + __IM unsigned int QEI_INTR_STS_REG; /*!< (@ 0x00000028) Quadrature Encoder interrupt status register */ struct { - __IM uint32_t QEI_POSITION_CNT_RESET_INTR_LEV : 1; /*!< [0..0] This is raised when + __IM unsigned int QEI_POSITION_CNT_RESET_INTR_LEV : 1; /*!< [0..0] This is raised when the position counter reaches it's extremes */ - __IM uint32_t QEI_INDEX_CNT_MATCH_INTR_LEV : 1; /*!< [1..1] This is raised when + __IM unsigned int QEI_INDEX_CNT_MATCH_INTR_LEV : 1; /*!< [1..1] This is raised when index counter reaches max value loaded in to index_max_cnt register. */ - __IM uint32_t POSITION_CNTR_ERR_INTR_LEV : 1; /*!< [2..2] Whenever number of + __IM unsigned int POSITION_CNTR_ERR_INTR_LEV : 1; /*!< [2..2] Whenever number of possible positions are mismatched with actual positions are received between two index pulses this will raised */ - __IM uint32_t VELOCITY_LESS_THAN_INTR_LEV : 1; /*!< [3..3] When velocity count is + __IM unsigned int VELOCITY_LESS_THAN_INTR_LEV : 1; /*!< [3..3] When velocity count is less than the value given in velocity_value_to_c mpare register, interrupt is raised */ - __IM uint32_t QEI_POSITION_CNT_MATCH_INTR_LEV : 1; /*!< [4..4] This is raised when + __IM unsigned int QEI_POSITION_CNT_MATCH_INTR_LEV : 1; /*!< [4..4] This is raised when the position counter reaches position match value, which is programmable. */ - __IM uint32_t QEI_VELOCITY_COMPUTATION_OVER_INTR_LEV : 1; /*!< [5..5] When velocity + __IM unsigned int QEI_VELOCITY_COMPUTATION_OVER_INTR_LEV : 1; /*!< [5..5] When velocity count is computed for given delta time, than interrupt is raised. */ - __IM uint32_t RESERVED1 : 26; /*!< [31..6] Reserved1 */ + __IM unsigned int RESERVED1 : 26; /*!< [31..6] Reserved1 */ } QEI_INTR_STS_REG_b; }; union { - __IOM uint32_t QEI_INTR_ACK_REG; /*!< (@ 0x0000002C) Quadrature Encoder + __IOM unsigned int QEI_INTR_ACK_REG; /*!< (@ 0x0000002C) Quadrature Encoder interrupt acknowledge register */ struct { - __IOM uint32_t QEI_POSITION_CNT_RESET_INTR_LEV : 1; /*!< [0..0] + __IOM unsigned int QEI_POSITION_CNT_RESET_INTR_LEV : 1; /*!< [0..0] Qei_position_cnt_reset_intr_ack */ - __IOM uint32_t QEI_INDEX_CNT_MATCH_INTR_LEV : 1; /*!< [1..1] NONE */ - __IOM uint32_t POSITION_CNTR_ERR_INTR_LEV : 1; /*!< [2..2] Position_cntr_err_intr_ack + __IOM unsigned int QEI_INDEX_CNT_MATCH_INTR_LEV : 1; /*!< [1..1] NONE */ + __IOM unsigned int POSITION_CNTR_ERR_INTR_LEV : 1; /*!< [2..2] Position_cntr_err_intr_ack */ - __IOM uint32_t VELOCITY_LESS_THAN_INTR_LEV : 1; /*!< [3..3] + __IOM unsigned int VELOCITY_LESS_THAN_INTR_LEV : 1; /*!< [3..3] Velocity_less_than_intr_ack */ - __IOM uint32_t QEI_POSITION_CNT_MATCH_INTR_LEV : 1; /*!< [4..4] + __IOM unsigned int QEI_POSITION_CNT_MATCH_INTR_LEV : 1; /*!< [4..4] Qei_position_cnt_match_intr_ack */ - __IOM uint32_t VELOCITY_COMPUTATION_OVER_INTR_LEV : 1; /*!< [5..5] + __IOM unsigned int VELOCITY_COMPUTATION_OVER_INTR_LEV : 1; /*!< [5..5] Velocity_computation_over_intr_ack */ - __IOM uint32_t RESERVED1 : 26; /*!< [31..6] Reserved1 */ + __IOM unsigned int RESERVED1 : 26; /*!< [31..6] Reserved1 */ } QEI_INTR_ACK_REG_b; }; union { - __IOM uint32_t QEI_INTR_MASK_REG; /*!< (@ 0x00000030) Quadrature Encoder + __IOM unsigned int QEI_INTR_MASK_REG; /*!< (@ 0x00000030) Quadrature Encoder interrupt mask register */ struct { - __IOM uint32_t QEI_POSITION_CNT_RESET_INTR_MASK : 1; /*!< [0..0] + __IOM unsigned int QEI_POSITION_CNT_RESET_INTR_MASK : 1; /*!< [0..0] Qei_position_cnt_reset_intr_mask */ - __IOM uint32_t QEI_INDEX_CNT_MATCH_INTR_MASK : 1; /*!< [1..1] + __IOM unsigned int QEI_INDEX_CNT_MATCH_INTR_MASK : 1; /*!< [1..1] Qei_index_cnt_match_intr_mask */ - __IOM uint32_t POSITION_CNTR_ERR_INTR_MASK : 1; /*!< [2..2] + __IOM unsigned int POSITION_CNTR_ERR_INTR_MASK : 1; /*!< [2..2] Position_cntr_err_intr_mask */ - __IOM uint32_t VELOCITY_LESS_THAN_INTR_MASK : 1; /*!< [3..3] + __IOM unsigned int VELOCITY_LESS_THAN_INTR_MASK : 1; /*!< [3..3] Velocity_less_than_intr_mask */ - __IOM uint32_t QEI_POSITION_CNT_MATCH_INTR_MASK : 1; /*!< [4..4] + __IOM unsigned int QEI_POSITION_CNT_MATCH_INTR_MASK : 1; /*!< [4..4] Qei_position_cnt_match_intr_mask */ - __IOM uint32_t VELOCITY_COMPUTATION_OVER_INTR_MASK : 1; /*!< [5..5] + __IOM unsigned int VELOCITY_COMPUTATION_OVER_INTR_MASK : 1; /*!< [5..5] Velocity_computation_over_intr_mask */ - __IOM uint32_t RESERVED1 : 26; /*!< [31..6] Reserved1 */ + __IOM unsigned int RESERVED1 : 26; /*!< [31..6] Reserved1 */ } QEI_INTR_MASK_REG_b; }; union { - __IOM uint32_t QEI_INTR_UNMASK_REg; /*!< (@ 0x00000034) Quadrature Encoder + __IOM unsigned int QEI_INTR_UNMASK_REg; /*!< (@ 0x00000034) Quadrature Encoder interrupt unmask register */ struct { - __IOM uint32_t QEI_POSITION_CNT_RESET_INTR_UNMASK : 1; /*!< [0..0] + __IOM unsigned int QEI_POSITION_CNT_RESET_INTR_UNMASK : 1; /*!< [0..0] Qei_position_cnt_reset_intr_unmask */ - __IOM uint32_t QEI_INDEX_CNT_MATCH_INTR_UNMASK : 1; /*!< [1..1] + __IOM unsigned int QEI_INDEX_CNT_MATCH_INTR_UNMASK : 1; /*!< [1..1] Qei_index_cnt_match_intr_unmask */ - __IOM uint32_t POSITION_CNTR_ERR_INTR_UNMASK : 1; /*!< [2..2] + __IOM unsigned int POSITION_CNTR_ERR_INTR_UNMASK : 1; /*!< [2..2] Position_cntr_err_intr_unmask */ - __IOM uint32_t VELOCITY_LESS_THAN_INTR_UNMASK : 1; /*!< [3..3] + __IOM unsigned int VELOCITY_LESS_THAN_INTR_UNMASK : 1; /*!< [3..3] Velocity_less_than_intr_unmask */ - __IOM uint32_t QEI_POSITION_CNT_MATCH_INTR_UNMASK : 1; /*!< [4..4] + __IOM unsigned int QEI_POSITION_CNT_MATCH_INTR_UNMASK : 1; /*!< [4..4] Qei_position_cnt_match_intr_unmask */ - __IOM uint32_t RESERVED1 : 27; /*!< [31..5] Reserved1 */ + __IOM unsigned int RESERVED1 : 27; /*!< [31..5] Reserved1 */ } QEI_INTR_UNMASK_REg_b; }; union { - __IOM uint32_t QEI_CLK_FREQ_REG; /*!< (@ 0x00000038) Quadrature Encoder + __IOM unsigned int QEI_CLK_FREQ_REG; /*!< (@ 0x00000038) Quadrature Encoder clock frequency register */ struct { - __IOM uint32_t QEI_CLK_FREQ : 9; /*!< [8..0] Indication of clock frequency on which + __IOM unsigned int QEI_CLK_FREQ : 9; /*!< [8..0] Indication of clock frequency on which QEI controller is running. */ - __IOM uint32_t RESERVED1 : 23; /*!< [31..9] Reserved1 */ + __IOM unsigned int RESERVED1 : 23; /*!< [31..9] Reserved1 */ } QEI_CLK_FREQ_REG_b; }; union { - __IOM uint32_t QEI_DELTA_TIME_REG; /*!< (@ 0x0000003C) Quadrature Delta time + __IOM unsigned int QEI_DELTA_TIME_REG; /*!< (@ 0x0000003C) Quadrature Delta time register */ struct { - __IOM uint32_t DELTA_TIME_FOR_VELOCITY : 20; /*!< [19..0] Delta time LSW + __IOM unsigned int DELTA_TIME_FOR_VELOCITY : 20; /*!< [19..0] Delta time LSW to compute velocity */ - __IOM uint32_t RESERVED1 : 12; /*!< [31..20] Reserved1 */ + __IOM unsigned int RESERVED1 : 12; /*!< [31..20] Reserved1 */ } QEI_DELTA_TIME_REG_b; }; - __IM uint32_t RESERVED2; + __IM unsigned int RESERVED2; union { - __IOM uint32_t QEI_VELOCITY_REG; /*!< (@ 0x00000044) Quadrature velocity register */ + __IOM unsigned int QEI_VELOCITY_REG; /*!< (@ 0x00000044) Quadrature velocity register */ struct { - __IOM uint32_t VELOCITY_VALUE_TO_COMPARE_L : 16; /*!< [15..0] For read operation :It + __IOM unsigned int VELOCITY_VALUE_TO_COMPARE_L : 16; /*!< [15..0] For read operation :It is the velocity count to compare using TA firmware For write operation :It is the velocity value to compare with velocity count */ - __IOM uint32_t VELOCITY_VALUE_TO_COMPARE_H : 16; /*!< [31..16] For read operation :It + __IOM unsigned int VELOCITY_VALUE_TO_COMPARE_H : 16; /*!< [31..16] For read operation :It is the velocity count to compare using TA firmware For write operation :It is the @@ -3699,16 +3699,16 @@ typedef struct { /*!< (@ 0x47060000) QEI Structure */ velocity count */ } QEI_VELOCITY_REG_b; }; - __IM uint32_t RESERVED3; + __IM unsigned int RESERVED3; union { - __IOM uint32_t QEI_POSITION_MATCH_REG; /*!< (@ 0x0000004C) Quadrature + __IOM unsigned int QEI_POSITION_MATCH_REG; /*!< (@ 0x0000004C) Quadrature position match register */ struct { - __IOM uint32_t POSTION_MATCH_VALUE_L : 16; /*!< [15..0] Position match value to + __IOM unsigned int POSTION_MATCH_VALUE_L : 16; /*!< [15..0] Position match value to compare the position counter. */ - __IOM uint32_t POSTION_MATCH_VALUE_H : 16; /*!< [31..16] Position match value to + __IOM unsigned int POSTION_MATCH_VALUE_H : 16; /*!< [31..16] Position match value to compare the position counter. */ } QEI_POSITION_MATCH_REG_b; }; @@ -3730,548 +3730,548 @@ typedef struct { /*!< (@ 0x44000100) USART0 Structure */ union { union { - __IOM uint32_t DLL; /*!< (@ 0x00000000) Divisor Latch Low */ + __IOM unsigned int DLL; /*!< (@ 0x00000000) Divisor Latch Low */ struct { - __IOM uint32_t DLL : 8; /*!< [7..0] Lower 8-bits of a 16-bit, read/write, Divisor + __IOM unsigned int DLL : 8; /*!< [7..0] Lower 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. */ - __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ } DLL_b; }; union { - __OM uint32_t THR; /*!< (@ 0x00000000) Transmit Holding Register */ + __OM unsigned int THR; /*!< (@ 0x00000000) Transmit Holding Register */ struct { - __OM uint32_t THR : 8; /*!< [7..0] Data to be transmitted on serial + __OM unsigned int THR : 8; /*!< [7..0] Data to be transmitted on serial output port */ - __OM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + __OM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ } THR_b; }; union { - __IM uint32_t RBR; /*!< (@ 0x00000000) Receive Buffer Register */ + __IM unsigned int RBR; /*!< (@ 0x00000000) Receive Buffer Register */ struct { - __IM uint32_t RBR : 8; /*!< [7..0] Receive Buffer Field */ - __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + __IM unsigned int RBR : 8; /*!< [7..0] Receive Buffer Field */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ } RBR_b; }; }; union { union { - __IOM uint32_t IER; /*!< (@ 0x00000004) Interrupt Enable Register */ + __IOM unsigned int IER; /*!< (@ 0x00000004) Interrupt Enable Register */ struct { - __IOM uint32_t ERBFI : 1; /*!< [0..0] Enable Received Data Available Interrupt */ - __IOM uint32_t ETBEI : 1; /*!< [1..1] Enable Transmit Holding Register + __IOM unsigned int ERBFI : 1; /*!< [0..0] Enable Received Data Available Interrupt */ + __IOM unsigned int ETBEI : 1; /*!< [1..1] Enable Transmit Holding Register Empty Interrupt */ - __IOM uint32_t ELSI : 1; /*!< [2..2] Enable Receiver Line Status Interrupt */ - __IOM uint32_t EDSSI : 1; /*!< [3..3] Enable Modem Status Interrupt */ - __IM uint32_t RESERVED1 : 3; /*!< [6..4] reserved1 */ - __IOM uint32_t PTIME : 1; /*!< [7..7] Programmable THRE Interrupt Mode Enable */ - __IM uint32_t RESERVED2 : 24; /*!< [31..8] reserved2 */ + __IOM unsigned int ELSI : 1; /*!< [2..2] Enable Receiver Line Status Interrupt */ + __IOM unsigned int EDSSI : 1; /*!< [3..3] Enable Modem Status Interrupt */ + __IM unsigned int RESERVED1 : 3; /*!< [6..4] reserved1 */ + __IOM unsigned int PTIME : 1; /*!< [7..7] Programmable THRE Interrupt Mode Enable */ + __IM unsigned int RESERVED2 : 24; /*!< [31..8] reserved2 */ } IER_b; }; union { - __IOM uint32_t DLH; /*!< (@ 0x00000004) Divisor Latch High */ + __IOM unsigned int DLH; /*!< (@ 0x00000004) Divisor Latch High */ struct { - __IOM uint32_t DLH : 8; /*!< [7..0] Upper 8-bits of a 16-bit, read/write, Divisor + __IOM unsigned int DLH : 8; /*!< [7..0] Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART */ - __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ } DLH_b; }; }; union { union { - __OM uint32_t FCR; /*!< (@ 0x00000008) FIFO Control Register */ + __OM unsigned int FCR; /*!< (@ 0x00000008) FIFO Control Register */ struct { - __OM uint32_t FIFOE : 1; /*!< [0..0] This enables/disables the transmit + __OM unsigned int FIFOE : 1; /*!< [0..0] This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs */ - __OM uint32_t RFIFOR : 1; /*!< [1..1] RCVR FIFO Reset */ - __OM uint32_t XFIFOR : 1; /*!< [2..2] XMIT FIFO Reset */ - __OM uint32_t DMAM : 1; /*!< [3..3] DMA signalling mode */ - __OM uint32_t TET : 2; /*!< [5..4] TX Empty Trigger */ - __OM uint32_t RT : 2; /*!< [7..6] This is used to select the trigger level in the + __OM unsigned int RFIFOR : 1; /*!< [1..1] RCVR FIFO Reset */ + __OM unsigned int XFIFOR : 1; /*!< [2..2] XMIT FIFO Reset */ + __OM unsigned int DMAM : 1; /*!< [3..3] DMA signalling mode */ + __OM unsigned int TET : 2; /*!< [5..4] TX Empty Trigger */ + __OM unsigned int RT : 2; /*!< [7..6] This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated */ - __OM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + __OM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ } FCR_b; }; union { - __IM uint32_t IIR; /*!< (@ 0x00000008) Interrupt Identity Register */ + __IM unsigned int IIR; /*!< (@ 0x00000008) Interrupt Identity Register */ struct { - __IM uint32_t IID : 4; /*!< [3..0] Interrupt ID */ - __IM uint32_t RESERVED1 : 2; /*!< [5..4] reserved1 */ - __IM uint32_t FIFOSE : 2; /*!< [7..6] This is used to indicate whether + __IM unsigned int IID : 4; /*!< [3..0] Interrupt ID */ + __IM unsigned int RESERVED1 : 2; /*!< [5..4] reserved1 */ + __IM unsigned int FIFOSE : 2; /*!< [7..6] This is used to indicate whether the FIFOs are enabled or disabled. */ - __IM uint32_t RESERVED2 : 24; /*!< [31..8] reserved2 */ + __IM unsigned int RESERVED2 : 24; /*!< [31..8] reserved2 */ } IIR_b; }; }; union { - __IOM uint32_t LCR; /*!< (@ 0x0000000C) Line Control Register */ + __IOM unsigned int LCR; /*!< (@ 0x0000000C) Line Control Register */ struct { - __IOM uint32_t DLS : 2; /*!< [1..0] Data Length Select,This is used to + __IOM unsigned int DLS : 2; /*!< [1..0] Data Length Select,This is used to select the number of data bits per character that the peripheral transmits and receives */ - __IOM uint32_t STOP : 1; /*!< [2..2] This is used to select the number of + __IOM unsigned int STOP : 1; /*!< [2..2] This is used to select the number of stop bits per character that the peripheral transmits and receives */ - __IOM uint32_t PEN : 1; /*!< [3..3] This bit is used to enable and disable parity + __IOM unsigned int PEN : 1; /*!< [3..3] This bit is used to enable and disable parity generation and detection in transmitted and received serial character */ - __IOM uint32_t EPS : 1; /*!< [4..4] This is used to select between even + __IOM unsigned int EPS : 1; /*!< [4..4] This is used to select between even and odd parity */ - __IOM uint32_t STICK_PARITY : 1; /*!< [5..5] This bit is used to force + __IOM unsigned int STICK_PARITY : 1; /*!< [5..5] This bit is used to force parity value */ - __IOM uint32_t BC : 1; /*!< [6..6] This is used to cause a break condition + __IOM unsigned int BC : 1; /*!< [6..6] This is used to cause a break condition to be transmitted to the receiving device */ - __IOM uint32_t DLAB : 1; /*!< [7..7] This bit is used to enable reading + __IOM unsigned int DLAB : 1; /*!< [7..7] This bit is used to enable reading and writing of the Divisor Latch register to set the baud rate of the UART */ - __IOM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + __IOM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ } LCR_b; }; union { - __IOM uint32_t MCR; /*!< (@ 0x00000010) Modem Control Register */ + __IOM unsigned int MCR; /*!< (@ 0x00000010) Modem Control Register */ struct { - __IOM uint32_t DTR : 1; /*!< [0..0] This is used to directly control the + __IOM unsigned int DTR : 1; /*!< [0..0] This is used to directly control the Data Terminal Ready (dtr_n) output */ - __IOM uint32_t RTS : 1; /*!< [1..1] This is used to directly control the + __IOM unsigned int RTS : 1; /*!< [1..1] This is used to directly control the Request to Send (rts_n) output */ - __IOM uint32_t OUT1 : 1; /*!< [2..2] This is used to directly control the + __IOM unsigned int OUT1 : 1; /*!< [2..2] This is used to directly control the user-designated Output1 (out1_n) output */ - __IOM uint32_t OUT2 : 1; /*!< [3..3] This is used to directly control the + __IOM unsigned int OUT2 : 1; /*!< [3..3] This is used to directly control the user-designated Output2 (out2_n) output */ - __IOM uint32_t LB : 1; /*!< [4..4] This is used to put the UART into a + __IOM unsigned int LB : 1; /*!< [4..4] This is used to put the UART into a diagnostic mode for test purposes */ - __IOM uint32_t AFCE : 1; /*!< [5..5] This is used to directly control the + __IOM unsigned int AFCE : 1; /*!< [5..5] This is used to directly control the user-designated Output2 (out2_n) output */ - __IOM uint32_t SIRE : 1; /*!< [6..6] This is used to enable/disable the + __IOM unsigned int SIRE : 1; /*!< [6..6] This is used to enable/disable the IrDA SIR Mode features */ - __IM uint32_t RESERVED1 : 25; /*!< [31..7] reserved1 */ + __IM unsigned int RESERVED1 : 25; /*!< [31..7] reserved1 */ } MCR_b; }; union { - __IM uint32_t LSR; /*!< (@ 0x00000014) Line Status Register */ + __IM unsigned int LSR; /*!< (@ 0x00000014) Line Status Register */ struct { - __IM uint32_t DR : 1; /*!< [0..0] This is used to indicate that the + __IM unsigned int DR : 1; /*!< [0..0] This is used to indicate that the receiver contains at least one character in the RBR or the receiver FIFO */ - __IM uint32_t OE : 1; /*!< [1..1] This is used to indicate the occurrence + __IM unsigned int OE : 1; /*!< [1..1] This is used to indicate the occurrence of an overrun error */ - __IM uint32_t PE : 1; /*!< [2..2] This is used to indicate the occurrence + __IM unsigned int PE : 1; /*!< [2..2] This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PEN) bit (LCR[3]) is set */ - __IM uint32_t FE : 1; /*!< [3..3] This is used to indicate the occurrence + __IM unsigned int FE : 1; /*!< [3..3] This is used to indicate the occurrence of a framing error in the receiver */ - __IM uint32_t BI : 1; /*!< [4..4] his is used to indicate the detection of + __IM unsigned int BI : 1; /*!< [4..4] his is used to indicate the detection of a break sequence on the serial input data */ - __IM uint32_t THRE : 1; /*!< [5..5] Transmit Holding Register Empty bit */ - __IM uint32_t TEMT : 1; /*!< [6..6] Transmitter Empty bit */ - __IM uint32_t RFE : 1; /*!< [7..7] This is used to indicate if there is at + __IM unsigned int THRE : 1; /*!< [5..5] Transmit Holding Register Empty bit */ + __IM unsigned int TEMT : 1; /*!< [6..6] Transmitter Empty bit */ + __IM unsigned int RFE : 1; /*!< [7..7] This is used to indicate if there is at least one parity error,framing error, or break indication in the FIFO */ - __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ } LSR_b; }; union { - __IM uint32_t MSR; /*!< (@ 0x00000018) Modem Status Register */ + __IM unsigned int MSR; /*!< (@ 0x00000018) Modem Status Register */ struct { - __IM uint32_t DCTS : 1; /*!< [0..0] This is used to indicate that the modem control + __IM unsigned int DCTS : 1; /*!< [0..0] This is used to indicate that the modem control line cts_n has changed since the last time the MSR was read */ - __IM uint32_t DDSR : 1; /*!< [1..1] This is used to indicate that the modem control + __IM unsigned int DDSR : 1; /*!< [1..1] This is used to indicate that the modem control line dsr_n has changed since the last time the MSR was read */ - __IM uint32_t TERI : 1; /*!< [2..2] This is used to indicate that a change on the + __IM unsigned int TERI : 1; /*!< [2..2] This is used to indicate that a change on the input ri_n(from an active-low to an inactive-high state) has occurred since the last time the MSR was read */ - __IM uint32_t DDCD : 1; /*!< [3..3] This is used to indicate that the modem control + __IM unsigned int DDCD : 1; /*!< [3..3] This is used to indicate that the modem control line dcd_n has changed since the last time the MSR was read */ - __IM uint32_t CTS : 1; /*!< [4..4] This is used to indicate the current + __IM unsigned int CTS : 1; /*!< [4..4] This is used to indicate the current state of the modem control line cts_n */ - __IM uint32_t DSR : 1; /*!< [5..5] This is used to indicate the current + __IM unsigned int DSR : 1; /*!< [5..5] This is used to indicate the current state of the modem control line dsr_n */ - __IM uint32_t RI : 1; /*!< [6..6] This is used to indicate the current + __IM unsigned int RI : 1; /*!< [6..6] This is used to indicate the current state of the modem control line ri_n */ - __IM uint32_t DCD : 1; /*!< [7..7] This is used to indicate the current + __IM unsigned int DCD : 1; /*!< [7..7] This is used to indicate the current state of the modem control line dcd_n */ - __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ } MSR_b; }; union { - __IOM uint32_t SCR; /*!< (@ 0x0000001C) Scratch pad Register */ + __IOM unsigned int SCR; /*!< (@ 0x0000001C) Scratch pad Register */ struct { - __IOM uint32_t SCRATCH_PAD : 8; /*!< [7..0] This register is for programmers to use + __IOM unsigned int SCRATCH_PAD : 8; /*!< [7..0] This register is for programmers to use as a temporary storage space. It has no defined purpose */ - __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ } SCR_b; }; union { - __IOM uint32_t LPDLL; /*!< (@ 0x00000020) Low Power Divisor Latch Low Register */ + __IOM unsigned int LPDLL; /*!< (@ 0x00000020) Low Power Divisor Latch Low Register */ struct { - __IOM uint32_t LOW_POWER_DLL : 8; /*!< [7..0] This register makes up the lower 8-bits + __IOM unsigned int LOW_POWER_DLL : 8; /*!< [7..0] This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K */ - __IOM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + __IOM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ } LPDLL_b; }; union { - __IOM uint32_t LPDLH; /*!< (@ 0x00000024) Low Power Divisor Latch High Register */ + __IOM unsigned int LPDLH; /*!< (@ 0x00000024) Low Power Divisor Latch High Register */ struct { - __IOM uint32_t LOW_POWER_DLH : 8; /*!< [7..0] This register makes up the upper 8-bits + __IOM unsigned int LOW_POWER_DLH : 8; /*!< [7..0] This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115200 */ - __IOM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + __IOM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ } LPDLH_b; }; - __IM uint32_t RESERVED[6]; + __IM unsigned int RESERVED[6]; union { - __IOM uint32_t HDEN; /*!< (@ 0x00000040) none */ + __IOM unsigned int HDEN; /*!< (@ 0x00000040) none */ struct { - __IOM uint32_t FULL_DUPLEX_MODE : 1; /*!< [0..0] none */ - __IOM uint32_t TX_MODE_RX_MODE : 1; /*!< [1..1] This signal is valid when + __IOM unsigned int FULL_DUPLEX_MODE : 1; /*!< [0..0] none */ + __IOM unsigned int TX_MODE_RX_MODE : 1; /*!< [1..1] This signal is valid when full_duplex_mode is disabled */ - __IM uint32_t RESERVED1 : 30; /*!< [31..2] reserved1 */ + __IM unsigned int RESERVED1 : 30; /*!< [31..2] reserved1 */ } HDEN_b; }; - __IM uint32_t RESERVED1[5]; + __IM unsigned int RESERVED1[5]; union { - __IOM uint32_t SMCR; /*!< (@ 0x00000058) none */ + __IOM unsigned int SMCR; /*!< (@ 0x00000058) none */ struct { - __IOM uint32_t SYNC_MODE : 1; /*!< [0..0] none */ - __IOM uint32_t MST_MODE : 1; /*!< [1..1] none */ - __IOM uint32_t RESERVED1 : 2; /*!< [3..2] reserved1 */ - __IOM uint32_t CONTI_CLK_MODE : 1; /*!< [4..4] none */ - __IOM uint32_t START_STOP_EN : 1; /*!< [5..5] none */ - __IOM uint32_t RESERVED2 : 26; /*!< [31..6] reserved2 */ + __IOM unsigned int SYNC_MODE : 1; /*!< [0..0] none */ + __IOM unsigned int MST_MODE : 1; /*!< [1..1] none */ + __IOM unsigned int RESERVED1 : 2; /*!< [3..2] reserved1 */ + __IOM unsigned int CONTI_CLK_MODE : 1; /*!< [4..4] none */ + __IOM unsigned int START_STOP_EN : 1; /*!< [5..5] none */ + __IOM unsigned int RESERVED2 : 26; /*!< [31..6] reserved2 */ } SMCR_b; }; - __IM uint32_t RESERVED2[5]; + __IM unsigned int RESERVED2[5]; union { - __IOM uint32_t FAR; /*!< (@ 0x00000070) none */ + __IOM unsigned int FAR; /*!< (@ 0x00000070) none */ struct { - __IOM uint32_t SYNC_MODE : 1; /*!< [0..0] none */ - __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + __IOM unsigned int SYNC_MODE : 1; /*!< [0..0] none */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ } FAR_b; }; union { - __IM uint32_t TFR; /*!< (@ 0x00000074) none */ + __IM unsigned int TFR; /*!< (@ 0x00000074) none */ struct { - __IM uint32_t TX_FIFO_RD : 8; /*!< [7..0] Transmit FIFO Read */ - __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + __IM unsigned int TX_FIFO_RD : 8; /*!< [7..0] Transmit FIFO Read */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ } TFR_b; }; union { - __IOM uint32_t RFW; /*!< (@ 0x00000078) none */ + __IOM unsigned int RFW; /*!< (@ 0x00000078) none */ struct { - __IOM uint32_t RFWD : 8; /*!< [7..0] Receive FIFO Write Data */ - __IOM uint32_t RFPE : 1; /*!< [8..8] Receive FIFO Parity Error */ - __IOM uint32_t RFFE : 1; /*!< [9..9] Receive FIFO Framing Error */ - __IM uint32_t RESERVED1 : 22; /*!< [31..10] reserved1 */ + __IOM unsigned int RFWD : 8; /*!< [7..0] Receive FIFO Write Data */ + __IOM unsigned int RFPE : 1; /*!< [8..8] Receive FIFO Parity Error */ + __IOM unsigned int RFFE : 1; /*!< [9..9] Receive FIFO Framing Error */ + __IM unsigned int RESERVED1 : 22; /*!< [31..10] reserved1 */ } RFW_b; }; union { - __IM uint32_t USR; /*!< (@ 0x0000007C) UART Status Register */ + __IM unsigned int USR; /*!< (@ 0x0000007C) UART Status Register */ struct { - __IM uint32_t BUSY : 1; /*!< [0..0] Indicates that a serial transfer is in + __IM unsigned int BUSY : 1; /*!< [0..0] Indicates that a serial transfer is in progress */ - __IM uint32_t TFNF : 1; /*!< [1..1] To Indicate that the transmit FIFO is + __IM unsigned int TFNF : 1; /*!< [1..1] To Indicate that the transmit FIFO is not full */ - __IM uint32_t TFE : 1; /*!< [2..2] To Indicate that the transmit FIFO is + __IM unsigned int TFE : 1; /*!< [2..2] To Indicate that the transmit FIFO is completely empty */ - __IM uint32_t RFNE : 1; /*!< [3..3] To Indicate that the receive FIFO + __IM unsigned int RFNE : 1; /*!< [3..3] To Indicate that the receive FIFO contains one or more entries */ - __IM uint32_t RFE : 1; /*!< [4..4] To Indicate that the receive FIFO is + __IM unsigned int RFE : 1; /*!< [4..4] To Indicate that the receive FIFO is completely full */ - __IM uint32_t RESERVED1 : 27; /*!< [31..5] reserved1 */ + __IM unsigned int RESERVED1 : 27; /*!< [31..5] reserved1 */ } USR_b; }; union { - __IM uint32_t TFL; /*!< (@ 0x00000080) Transmit FIFO Level */ + __IM unsigned int TFL; /*!< (@ 0x00000080) Transmit FIFO Level */ struct { - __IM uint32_t FIFO_ADDR_WIDTH : 30; /*!< [29..0] Transmit FIFO Level. This + __IM unsigned int FIFO_ADDR_WIDTH : 30; /*!< [29..0] Transmit FIFO Level. This is indicates the number of data entries in the transmit FIFO. */ - __IM uint32_t RESERVED1 : 2; /*!< [31..30] reserved1 */ + __IM unsigned int RESERVED1 : 2; /*!< [31..30] reserved1 */ } TFL_b; }; union { - __IM uint32_t RFL; /*!< (@ 0x00000084) Receive FIFO Level */ + __IM unsigned int RFL; /*!< (@ 0x00000084) Receive FIFO Level */ struct { - __IM uint32_t FIFO_ADDR_WIDTH : 30; /*!< [29..0] Receive FIFO Level. This + __IM unsigned int FIFO_ADDR_WIDTH : 30; /*!< [29..0] Receive FIFO Level. This is indicates the number of data entries in the receive FIFO. */ - __IM uint32_t RESERVED1 : 2; /*!< [31..30] reserved1 */ + __IM unsigned int RESERVED1 : 2; /*!< [31..30] reserved1 */ } RFL_b; }; union { - __OM uint32_t SRR; /*!< (@ 0x00000088) Software Reset Register */ + __OM unsigned int SRR; /*!< (@ 0x00000088) Software Reset Register */ struct { - __OM uint32_t UR : 1; /*!< [0..0] UART Reset */ - __OM uint32_t RFR : 1; /*!< [1..1] RCVR FIFO Reset */ - __OM uint32_t XFR : 1; /*!< [2..2] XMIT FIFO Reset */ - __OM uint32_t RESERVED1 : 29; /*!< [31..3] reserved1 */ + __OM unsigned int UR : 1; /*!< [0..0] UART Reset */ + __OM unsigned int RFR : 1; /*!< [1..1] RCVR FIFO Reset */ + __OM unsigned int XFR : 1; /*!< [2..2] XMIT FIFO Reset */ + __OM unsigned int RESERVED1 : 29; /*!< [31..3] reserved1 */ } SRR_b; }; union { - __IOM uint32_t SRTS; /*!< (@ 0x0000008C) Shadow Request to Send */ + __IOM unsigned int SRTS; /*!< (@ 0x0000008C) Shadow Request to Send */ struct { - __IOM uint32_t SRTS : 1; /*!< [0..0] Shadow Request to Send. */ - __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + __IOM unsigned int SRTS : 1; /*!< [0..0] Shadow Request to Send. */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ } SRTS_b; }; union { - __IOM uint32_t SBCR; /*!< (@ 0x00000090) Shadow Break Control Register */ + __IOM unsigned int SBCR; /*!< (@ 0x00000090) Shadow Break Control Register */ struct { - __IOM uint32_t SBCR : 1; /*!< [0..0] Shadow Break Control Bit */ - __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + __IOM unsigned int SBCR : 1; /*!< [0..0] Shadow Break Control Bit */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ } SBCR_b; }; union { - __IOM uint32_t SDMAM; /*!< (@ 0x00000094) Shadow DMA Mode */ + __IOM unsigned int SDMAM; /*!< (@ 0x00000094) Shadow DMA Mode */ struct { - __IOM uint32_t SDMAM : 1; /*!< [0..0] Shadow DMA Mode */ - __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + __IOM unsigned int SDMAM : 1; /*!< [0..0] Shadow DMA Mode */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ } SDMAM_b; }; union { - __IOM uint32_t SFE; /*!< (@ 0x00000098) Shadow FIFO Enable */ + __IOM unsigned int SFE; /*!< (@ 0x00000098) Shadow FIFO Enable */ struct { - __IOM uint32_t SFE : 1; /*!< [0..0] Shadow FIFO Enable */ - __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + __IOM unsigned int SFE : 1; /*!< [0..0] Shadow FIFO Enable */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ } SFE_b; }; union { - __IOM uint32_t SRT; /*!< (@ 0x0000009C) Shadow RCVR Trigger */ + __IOM unsigned int SRT; /*!< (@ 0x0000009C) Shadow RCVR Trigger */ struct { - __IOM uint32_t SRT : 2; /*!< [1..0] Shadow RCVR Trigger */ - __IM uint32_t RESERVED1 : 30; /*!< [31..2] reserved1 */ + __IOM unsigned int SRT : 2; /*!< [1..0] Shadow RCVR Trigger */ + __IM unsigned int RESERVED1 : 30; /*!< [31..2] reserved1 */ } SRT_b; }; union { - __IOM uint32_t STET; /*!< (@ 0x000000A0) Shadow TX Empty Trigger */ + __IOM unsigned int STET; /*!< (@ 0x000000A0) Shadow TX Empty Trigger */ struct { - __IOM uint32_t STET : 2; /*!< [1..0] Shadow TX Empty Trigger */ - __IM uint32_t RESERVED1 : 30; /*!< [31..2] reserved1 */ + __IOM unsigned int STET : 2; /*!< [1..0] Shadow TX Empty Trigger */ + __IM unsigned int RESERVED1 : 30; /*!< [31..2] reserved1 */ } STET_b; }; union { - __IOM uint32_t HTX; /*!< (@ 0x000000A4) Halt Transmit */ + __IOM unsigned int HTX; /*!< (@ 0x000000A4) Halt Transmit */ struct { - __IOM uint32_t HALT_TX : 1; /*!< [0..0] This register is use to halt + __IOM unsigned int HALT_TX : 1; /*!< [0..0] This register is use to halt transmissions for testing */ - __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ } HTX_b; }; union { - __IOM uint32_t DMASA; /*!< (@ 0x000000A8) DMA Software Acknowledge */ + __IOM unsigned int DMASA; /*!< (@ 0x000000A8) DMA Software Acknowledge */ struct { - __OM uint32_t DMA_SOFTWARE_ACK : 1; /*!< [0..0] This register is use to perform a + __OM unsigned int DMA_SOFTWARE_ACK : 1; /*!< [0..0] This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition */ - __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ } DMASA_b; }; union { - __IOM uint32_t TCR; /*!< (@ 0x000000AC) Transceiver Control Register. */ + __IOM unsigned int TCR; /*!< (@ 0x000000AC) Transceiver Control Register. */ struct { - __IOM uint32_t RS485_EN : 1; /*!< [0..0] RS485 Transfer Enable. */ - __IOM uint32_t RE_POL : 1; /*!< [1..1] Receiver Enable Polarity. */ - __IOM uint32_t DE_POL : 1; /*!< [2..2] Driver Enable Polarity. */ - __IOM uint32_t XFER_MODE : 2; /*!< [4..3] Transfer Mode. */ - __IM uint32_t RESERVED1 : 27; /*!< [31..5] reserved1 */ + __IOM unsigned int RS485_EN : 1; /*!< [0..0] RS485 Transfer Enable. */ + __IOM unsigned int RE_POL : 1; /*!< [1..1] Receiver Enable Polarity. */ + __IOM unsigned int DE_POL : 1; /*!< [2..2] Driver Enable Polarity. */ + __IOM unsigned int XFER_MODE : 2; /*!< [4..3] Transfer Mode. */ + __IM unsigned int RESERVED1 : 27; /*!< [31..5] reserved1 */ } TCR_b; }; union { - __IOM uint32_t DE_EN; /*!< (@ 0x000000B0) Driver Output Enable Register. */ + __IOM unsigned int DE_EN; /*!< (@ 0x000000B0) Driver Output Enable Register. */ struct { - __IOM uint32_t DE_EN : 1; /*!< [0..0] DE Enable control. */ - __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + __IOM unsigned int DE_EN : 1; /*!< [0..0] DE Enable control. */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ } DE_EN_b; }; union { - __IOM uint32_t RE_EN; /*!< (@ 0x000000B4) Receiver Output Enable Register. */ + __IOM unsigned int RE_EN; /*!< (@ 0x000000B4) Receiver Output Enable Register. */ struct { - __IOM uint32_t RE_EN : 1; /*!< [0..0] RE Enable control. */ - __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + __IOM unsigned int RE_EN : 1; /*!< [0..0] RE Enable control. */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ } RE_EN_b; }; union { - __IOM uint32_t DET; /*!< (@ 0x000000B8) Driver Output Enable Timing Register. */ + __IOM unsigned int DET; /*!< (@ 0x000000B8) Driver Output Enable Timing Register. */ struct { - __IOM uint32_t DE_ASSERT_TIME : 8; /*!< [7..0] Driver enable assertion time. */ - __IOM uint32_t RES : 8; /*!< [15..8] reserved. */ - __IOM uint32_t DE_DE_ASSERT_TIME : 8; /*!< [23..16] Driver enable + __IOM unsigned int DE_ASSERT_TIME : 8; /*!< [7..0] Driver enable assertion time. */ + __IOM unsigned int RES : 8; /*!< [15..8] reserved. */ + __IOM unsigned int DE_DE_ASSERT_TIME : 8; /*!< [23..16] Driver enable de-assertion time. */ - __IM uint32_t RESERVED1 : 8; /*!< [31..24] reserved1 */ + __IM unsigned int RESERVED1 : 8; /*!< [31..24] reserved1 */ } DET_b; }; union { - __IOM uint32_t TAT; /*!< (@ 0x000000BC) TurnAround Timing Register */ + __IOM unsigned int TAT; /*!< (@ 0x000000BC) TurnAround Timing Register */ struct { - __IOM uint32_t DE_RE : 16; /*!< [15..0] Driver Enable to Receiver Enable + __IOM unsigned int DE_RE : 16; /*!< [15..0] Driver Enable to Receiver Enable TurnAround time. */ - __IOM uint32_t RE_DE : 16; /*!< [31..16] Receiver Enable to Driver Enable + __IOM unsigned int RE_DE : 16; /*!< [31..16] Receiver Enable to Driver Enable TurnAround time. */ } TAT_b; }; union { - __IOM uint32_t DLF; /*!< (@ 0x000000C0) Divisor Latch Fraction Register. */ + __IOM unsigned int DLF; /*!< (@ 0x000000C0) Divisor Latch Fraction Register. */ struct { - __IOM uint32_t DLF : 6; /*!< [5..0] Fractional part of divisor. */ - __IM uint32_t : 1; - __IM uint32_t RESERVED1 : 25; /*!< [31..7] reserved1 */ + __IOM unsigned int DLF : 6; /*!< [5..0] Fractional part of divisor. */ + __IM unsigned int : 1; + __IM unsigned int RESERVED1 : 25; /*!< [31..7] reserved1 */ } DLF_b; }; union { - __IOM uint32_t RAR; /*!< (@ 0x000000C4) Receive Address Register. */ + __IOM unsigned int RAR; /*!< (@ 0x000000C4) Receive Address Register. */ struct { - __IOM uint32_t RAR : 8; /*!< [7..0] This is an address matching register + __IOM unsigned int RAR : 8; /*!< [7..0] This is an address matching register during receive mode. */ - __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ } RAR_b; }; union { - __IOM uint32_t TAR; /*!< (@ 0x000000C8) Transmit Address Register. */ + __IOM unsigned int TAR; /*!< (@ 0x000000C8) Transmit Address Register. */ struct { - __IOM uint32_t TAR : 8; /*!< [7..0] This is an address matching register + __IOM unsigned int TAR : 8; /*!< [7..0] This is an address matching register during transmit mode. */ - __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ } TAR_b; }; union { - __IOM uint32_t LCR_EXT; /*!< (@ 0x000000CC) Line Extended Control Register */ + __IOM unsigned int LCR_EXT; /*!< (@ 0x000000CC) Line Extended Control Register */ struct { - __IOM uint32_t DLS_E : 1; /*!< [0..0] Extension for DLS. */ - __IOM uint32_t ADDR_MATCH : 1; /*!< [1..1] Address Match Mode. */ - __IOM uint32_t SEND_ADDR : 1; /*!< [2..2] Send address control bit. */ - __IOM uint32_t TRANSMIT_MODE : 1; /*!< [3..3] Transmit mode control bit. */ - __IM uint32_t RESERVED1 : 28; /*!< [31..4] reserved1 */ + __IOM unsigned int DLS_E : 1; /*!< [0..0] Extension for DLS. */ + __IOM unsigned int ADDR_MATCH : 1; /*!< [1..1] Address Match Mode. */ + __IOM unsigned int SEND_ADDR : 1; /*!< [2..2] Send address control bit. */ + __IOM unsigned int TRANSMIT_MODE : 1; /*!< [3..3] Transmit mode control bit. */ + __IM unsigned int RESERVED1 : 28; /*!< [31..4] reserved1 */ } LCR_EXT_b; }; - __IM uint32_t RESERVED3[9]; + __IM unsigned int RESERVED3[9]; union { - __IM uint32_t CPR; /*!< (@ 0x000000F4) Component Parameter Register */ + __IM unsigned int CPR; /*!< (@ 0x000000F4) Component Parameter Register */ struct { - __IM uint32_t APB_DATA_WIDTH : 2; /*!< [1..0] APB data width register. */ - __IM uint32_t RESERVED1 : 2; /*!< [3..2] reserved1 */ - __IM uint32_t AFCE_MODE : 1; /*!< [4..4] none */ - __IM uint32_t THRE_MODE : 1; /*!< [5..5] none */ - __IM uint32_t SIR_MODE : 1; /*!< [6..6] none */ - __IM uint32_t SIR_LP_MODE : 1; /*!< [7..7] none */ - __IM uint32_t ADDITIONAL_FEAT : 1; /*!< [8..8] none */ - __IM uint32_t FIFO_ACCESS : 1; /*!< [9..9] none */ - __IM uint32_t FIFO_STAT : 1; /*!< [10..10] none */ - __IM uint32_t SHADOW : 1; /*!< [11..11] none */ - __IM uint32_t UART_ADD_ENCODED_PARAMS : 1; /*!< [12..12] none */ - __IM uint32_t DMA_EXTRA : 1; /*!< [13..13] none */ - __IM uint32_t RESERVED2 : 2; /*!< [15..14] reserved2 */ - __IM uint32_t FIFO_MODE : 8; /*!< [23..16] none */ - __IM uint32_t RESERVED3 : 8; /*!< [31..24] reserved3 */ + __IM unsigned int APB_DATA_WIDTH : 2; /*!< [1..0] APB data width register. */ + __IM unsigned int RESERVED1 : 2; /*!< [3..2] reserved1 */ + __IM unsigned int AFCE_MODE : 1; /*!< [4..4] none */ + __IM unsigned int THRE_MODE : 1; /*!< [5..5] none */ + __IM unsigned int SIR_MODE : 1; /*!< [6..6] none */ + __IM unsigned int SIR_LP_MODE : 1; /*!< [7..7] none */ + __IM unsigned int ADDITIONAL_FEAT : 1; /*!< [8..8] none */ + __IM unsigned int FIFO_ACCESS : 1; /*!< [9..9] none */ + __IM unsigned int FIFO_STAT : 1; /*!< [10..10] none */ + __IM unsigned int SHADOW : 1; /*!< [11..11] none */ + __IM unsigned int UART_ADD_ENCODED_PARAMS : 1; /*!< [12..12] none */ + __IM unsigned int DMA_EXTRA : 1; /*!< [13..13] none */ + __IM unsigned int RESERVED2 : 2; /*!< [15..14] reserved2 */ + __IM unsigned int FIFO_MODE : 8; /*!< [23..16] none */ + __IM unsigned int RESERVED3 : 8; /*!< [31..24] reserved3 */ } CPR_b; }; union { - __IM uint32_t UCV; /*!< (@ 0x000000F8) UART Component Version */ + __IM unsigned int UCV; /*!< (@ 0x000000F8) UART Component Version */ struct { - __IM uint32_t UART_COMP_VER : 32; /*!< [31..0] ASCII value for each number + __IM unsigned int UART_COMP_VER : 32; /*!< [31..0] ASCII value for each number in the version, followed by * */ } UCV_b; }; union { - __IM uint32_t CTR; /*!< (@ 0x000000FC) Component Type Register */ + __IM unsigned int CTR; /*!< (@ 0x000000FC) Component Type Register */ struct { - __IM uint32_t UART_COMP_VER : 32; /*!< [31..0] This register contains the + __IM unsigned int UART_COMP_VER : 32; /*!< [31..0] This register contains the peripherals identification code. */ } CTR_b; }; @@ -4292,256 +4292,256 @@ typedef struct { /*!< (@ 0x44000100) USART0 Structure */ typedef struct { /*!< (@ 0x45030000) GSPI0 Structure */ union { - __IOM uint32_t GSPI_CLK_CONFIG; /*!< (@ 0x00000000) GSPI Clock Configuration + __IOM unsigned int GSPI_CLK_CONFIG; /*!< (@ 0x00000000) GSPI Clock Configuration Register */ struct { - __IOM uint32_t GSPI_CLK_SYNC : 1; /*!< [0..0] If the clock frequency to FLASH + __IOM unsigned int GSPI_CLK_SYNC : 1; /*!< [0..0] If the clock frequency to FLASH (spi_clk) and SOC clk is same. */ - __IOM uint32_t GSPI_CLK_EN : 1; /*!< [1..1] GSPI clock enable */ - __IOM uint32_t RESERVED1 : 30; /*!< [31..2] reserved for future use */ + __IOM unsigned int GSPI_CLK_EN : 1; /*!< [1..1] GSPI clock enable */ + __IOM unsigned int RESERVED1 : 30; /*!< [31..2] reserved for future use */ } GSPI_CLK_CONFIG_b; }; union { - __IOM uint32_t GSPI_BUS_MODE; /*!< (@ 0x00000004) GSPI Bus Mode Register */ + __IOM unsigned int GSPI_BUS_MODE; /*!< (@ 0x00000004) GSPI Bus Mode Register */ struct { - __IOM uint32_t GSPI_DATA_SAMPLE_EDGE : 1; /*!< [0..0] Samples MISO data on + __IOM unsigned int GSPI_DATA_SAMPLE_EDGE : 1; /*!< [0..0] Samples MISO data on clock edges. This should be ZERO for mode3 clock */ - __IOM uint32_t GSPI_CLK_MODE_CSN0 : 1; /*!< [1..1] NONE */ - __IOM uint32_t GSPI_CLK_MODE_CSN1 : 1; /*!< [2..2] NONE */ - __IOM uint32_t GSPI_CLK_MODE_CSN2 : 1; /*!< [3..3] NONE */ - __IOM uint32_t GSPI_CLK_MODE_CSN3 : 1; /*!< [4..4] NONE */ - __IOM uint32_t GSPI_GPIO_MODE_ENABLES : 6; /*!< [10..5] These bits are used to map + __IOM unsigned int GSPI_CLK_MODE_CSN0 : 1; /*!< [1..1] NONE */ + __IOM unsigned int GSPI_CLK_MODE_CSN1 : 1; /*!< [2..2] NONE */ + __IOM unsigned int GSPI_CLK_MODE_CSN2 : 1; /*!< [3..3] NONE */ + __IOM unsigned int GSPI_CLK_MODE_CSN3 : 1; /*!< [4..4] NONE */ + __IOM unsigned int GSPI_GPIO_MODE_ENABLES : 6; /*!< [10..5] These bits are used to map GSPI on GPIO pins */ - __IOM uint32_t SPI_HIGH_PERFORMANCE_EN : 1; /*!< [11..11] High performance + __IOM unsigned int SPI_HIGH_PERFORMANCE_EN : 1; /*!< [11..11] High performance features are enabled when this bit is set to one */ - __IOM uint32_t RESERVED1 : 20; /*!< [31..12] reserved for future use */ + __IOM unsigned int RESERVED1 : 20; /*!< [31..12] reserved for future use */ } GSPI_BUS_MODE_b; }; - __IM uint32_t RESERVED[2]; + __IM unsigned int RESERVED[2]; union { - __IOM uint32_t GSPI_CONFIG1; /*!< (@ 0x00000010) GSPI Configuration 1 Register */ + __IOM unsigned int GSPI_CONFIG1; /*!< (@ 0x00000010) GSPI Configuration 1 Register */ struct { - __IOM uint32_t GSPI_MANUAL_CSN : 1; /*!< [0..0] SPI CS in manual mode */ - __IOM uint32_t GSPI_MANUAL_WR : 1; /*!< [1..1] Write enable for manual + __IOM unsigned int GSPI_MANUAL_CSN : 1; /*!< [0..0] SPI CS in manual mode */ + __IOM unsigned int GSPI_MANUAL_WR : 1; /*!< [1..1] Write enable for manual mode when CS is low. */ - __IOM uint32_t GSPI_MANUAL_RD : 1; /*!< [2..2] Read enable for manual mode + __IOM unsigned int GSPI_MANUAL_RD : 1; /*!< [2..2] Read enable for manual mode when CS is low */ - __IOM uint32_t GSPI_MANUAL_RD_CNT : 10; /*!< [12..3] Indicates total + __IOM unsigned int GSPI_MANUAL_RD_CNT : 10; /*!< [12..3] Indicates total number of bytes to be read */ - __IOM uint32_t GSPI_MANUAL_CSN_SELECT : 2; /*!< [14..13] Indicates which CSn is + __IOM unsigned int GSPI_MANUAL_CSN_SELECT : 2; /*!< [14..13] Indicates which CSn is valid. Can be programmable in manual mode */ - __IOM uint32_t SPI_FULL_DUPLEX_EN : 1; /*!< [15..15] Full duplex mode enable */ - __IOM uint32_t RESERVED1 : 16; /*!< [31..16] reserved for future use */ + __IOM unsigned int SPI_FULL_DUPLEX_EN : 1; /*!< [15..15] Full duplex mode enable */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] reserved for future use */ } GSPI_CONFIG1_b; }; union { - __IOM uint32_t GSPI_CONFIG2; /*!< (@ 0x00000014) GSPI Manual Configuration 2 + __IOM unsigned int GSPI_CONFIG2; /*!< (@ 0x00000014) GSPI Manual Configuration 2 Register */ struct { - __IOM uint32_t GSPI_WR_DATA_SWAP_MNL_CSN0 : 1; /*!< [0..0] Swap the write data inside + __IOM unsigned int GSPI_WR_DATA_SWAP_MNL_CSN0 : 1; /*!< [0..0] Swap the write data inside the GSPI controller it-self. */ - __IOM uint32_t GSPI_WR_DATA_SWAP_MNL_CSN1 : 1; /*!< [1..1] Swap the write data inside + __IOM unsigned int GSPI_WR_DATA_SWAP_MNL_CSN1 : 1; /*!< [1..1] Swap the write data inside the GSPI controller it-self. */ - __IOM uint32_t GSPI_WR_DATA_SWAP_MNL_CSN2 : 1; /*!< [2..2] Swap the write data inside + __IOM unsigned int GSPI_WR_DATA_SWAP_MNL_CSN2 : 1; /*!< [2..2] Swap the write data inside the GSPI controller it-self. */ - __IOM uint32_t GSPI_WR_DATA_SWAP_MNL_CSN3 : 1; /*!< [3..3] Swap the write data inside + __IOM unsigned int GSPI_WR_DATA_SWAP_MNL_CSN3 : 1; /*!< [3..3] Swap the write data inside the GSPI controller it-self. */ - __IOM uint32_t GSPI_RD_DATA_SWAP_MNL_CSN0 : 1; /*!< [4..4] Swap the read data inside + __IOM unsigned int GSPI_RD_DATA_SWAP_MNL_CSN0 : 1; /*!< [4..4] Swap the read data inside the GSPI controller it-self. */ - __IOM uint32_t GSPI_RD_DATA_SWAP_MNL_CSN1 : 1; /*!< [5..5] Swap the read data inside + __IOM unsigned int GSPI_RD_DATA_SWAP_MNL_CSN1 : 1; /*!< [5..5] Swap the read data inside the GSPI controller it-self. */ - __IOM uint32_t GSPI_RD_DATA_SWAP_MNL_CSN2 : 1; /*!< [6..6] Swap the read data inside + __IOM unsigned int GSPI_RD_DATA_SWAP_MNL_CSN2 : 1; /*!< [6..6] Swap the read data inside the GSPI controller it-self. */ - __IOM uint32_t GSPI_RD_DATA_SWAP_MNL_CSN3 : 1; /*!< [7..7] Swap the read data inside + __IOM unsigned int GSPI_RD_DATA_SWAP_MNL_CSN3 : 1; /*!< [7..7] Swap the read data inside the GSPI controller it-self. */ - __IOM uint32_t GSPI_MANUAL_SIZE_FRM_REG : 1; /*!< [8..8] Manual reads and + __IOM unsigned int GSPI_MANUAL_SIZE_FRM_REG : 1; /*!< [8..8] Manual reads and manual writes */ - __IOM uint32_t RESERVED1 : 1; /*!< [9..9] reserved for future use */ - __IOM uint32_t TAKE_GSPI_MANUAL_WR_SIZE_FRM_REG : 1; /*!< [10..10] NONE */ - __IOM uint32_t MANUAL_GSPI_MODE : 1; /*!< [11..11] Internally the priority + __IOM unsigned int RESERVED1 : 1; /*!< [9..9] reserved for future use */ + __IOM unsigned int TAKE_GSPI_MANUAL_WR_SIZE_FRM_REG : 1; /*!< [10..10] NONE */ + __IOM unsigned int MANUAL_GSPI_MODE : 1; /*!< [11..11] Internally the priority is given to manual mode */ - __IOM uint32_t RESERVED2 : 20; /*!< [31..12] reserved for future use */ + __IOM unsigned int RESERVED2 : 20; /*!< [31..12] reserved for future use */ } GSPI_CONFIG2_b; }; union { - __IOM uint32_t GSPI_WRITE_DATA2; /*!< (@ 0x00000018) GSPI Write Data 2 Register */ + __IOM unsigned int GSPI_WRITE_DATA2; /*!< (@ 0x00000018) GSPI Write Data 2 Register */ struct { - __IOM uint32_t GSPI_MANUAL_WRITE_DATA2 : 4; /*!< [3..0] Number of bits to be written + __IOM unsigned int GSPI_MANUAL_WRITE_DATA2 : 4; /*!< [3..0] Number of bits to be written in write mode */ - __IOM uint32_t RESERVED1 : 3; /*!< [6..4] reserved for future use */ - __IOM uint32_t USE_PREV_LENGTH : 1; /*!< [7..7] Use previous length */ - __IOM uint32_t RESERVED2 : 24; /*!< [31..8] reserved for future use */ + __IOM unsigned int RESERVED1 : 3; /*!< [6..4] reserved for future use */ + __IOM unsigned int USE_PREV_LENGTH : 1; /*!< [7..7] Use previous length */ + __IOM unsigned int RESERVED2 : 24; /*!< [31..8] reserved for future use */ } GSPI_WRITE_DATA2_b; }; union { - __IOM uint32_t GSPI_FIFO_THRLD; /*!< (@ 0x0000001C) GSPI FIFO Threshold Register */ + __IOM unsigned int GSPI_FIFO_THRLD; /*!< (@ 0x0000001C) GSPI FIFO Threshold Register */ struct { - __IOM uint32_t FIFO_AEMPTY_THRLD : 4; /*!< [3..0] FIFO almost empty threshold */ - __IOM uint32_t FIFO_AFULL_THRLD : 4; /*!< [7..4] FIFO almost full threshold */ - __IOM uint32_t WFIFO_RESET : 1; /*!< [8..8] Write FIFO reset */ - __IOM uint32_t RFIFO_RESET : 1; /*!< [9..9] read FIFO reset */ - __IOM uint32_t RESERVED1 : 22; /*!< [31..10] reserved for future use */ + __IOM unsigned int FIFO_AEMPTY_THRLD : 4; /*!< [3..0] FIFO almost empty threshold */ + __IOM unsigned int FIFO_AFULL_THRLD : 4; /*!< [7..4] FIFO almost full threshold */ + __IOM unsigned int WFIFO_RESET : 1; /*!< [8..8] Write FIFO reset */ + __IOM unsigned int RFIFO_RESET : 1; /*!< [9..9] read FIFO reset */ + __IOM unsigned int RESERVED1 : 22; /*!< [31..10] reserved for future use */ } GSPI_FIFO_THRLD_b; }; union { - __IM uint32_t GSPI_STATUS; /*!< (@ 0x00000020) GSPI Status Register */ + __IM unsigned int GSPI_STATUS; /*!< (@ 0x00000020) GSPI Status Register */ struct { - __IM uint32_t GSPI_BUSY : 1; /*!< [0..0] State of Manual mode */ - __IM uint32_t FIFO_FULL_WFIFO_S : 1; /*!< [1..1] Full status indication + __IM unsigned int GSPI_BUSY : 1; /*!< [0..0] State of Manual mode */ + __IM unsigned int FIFO_FULL_WFIFO_S : 1; /*!< [1..1] Full status indication for Wfifo in manual mode */ - __IM uint32_t FIFO_AFULL_WFIFO_S : 1; /*!< [2..2] Almost full status indication for + __IM unsigned int FIFO_AFULL_WFIFO_S : 1; /*!< [2..2] Almost full status indication for Wfifo in manual mode */ - __IM uint32_t FIFO_EMPTY_WFIFO : 1; /*!< [3..3] Empty status indication + __IM unsigned int FIFO_EMPTY_WFIFO : 1; /*!< [3..3] Empty status indication for Wfifo in manual mode */ - __IM uint32_t RESERVED1 : 1; /*!< [4..4] reserved for future use */ - __IM uint32_t FIFO_FULL_RFIFO : 1; /*!< [5..5] Full status indication for + __IM unsigned int RESERVED1 : 1; /*!< [4..4] reserved for future use */ + __IM unsigned int FIFO_FULL_RFIFO : 1; /*!< [5..5] Full status indication for Rfifo in manual mode */ - __IM uint32_t RESERVED2 : 1; /*!< [6..6] reserved for future use */ - __IM uint32_t FIFO_EMPTY_RFIFO_S : 1; /*!< [7..7] Empty status indication + __IM unsigned int RESERVED2 : 1; /*!< [6..6] reserved for future use */ + __IM unsigned int FIFO_EMPTY_RFIFO_S : 1; /*!< [7..7] Empty status indication for Rfifo in manual mode */ - __IM uint32_t FIFO_AEMPTY_RFIFO_S : 1; /*!< [8..8] Aempty status indication for + __IM unsigned int FIFO_AEMPTY_RFIFO_S : 1; /*!< [8..8] Aempty status indication for Rfifo in manual mode */ - __IM uint32_t GSPI_MANUAL_RD_CNT : 1; /*!< [9..9] This is a result of 10 + __IM unsigned int GSPI_MANUAL_RD_CNT : 1; /*!< [9..9] This is a result of 10 bits ORing counter */ - __IM uint32_t GSPI_MANUAL_CSN : 1; /*!< [10..10] Provide the status of + __IM unsigned int GSPI_MANUAL_CSN : 1; /*!< [10..10] Provide the status of chip select signal */ - __IM uint32_t RESERVED3 : 21; /*!< [31..11] reserved for future use */ + __IM unsigned int RESERVED3 : 21; /*!< [31..11] reserved for future use */ } GSPI_STATUS_b; }; union { - __IOM uint32_t GSPI_INTR_MASK; /*!< (@ 0x00000024) GSPI Interrupt Mask Register */ + __IOM unsigned int GSPI_INTR_MASK; /*!< (@ 0x00000024) GSPI Interrupt Mask Register */ struct { - __IOM uint32_t GSPI_INTR_MASK : 1; /*!< [0..0] GSPI Interrupt mask bit */ - __IOM uint32_t FIFO_AEMPTY_RFIFO_MASK : 1; /*!< [1..1] NONE */ - __IOM uint32_t FIFO_AFULL_RFIFO_MASK : 1; /*!< [2..2] NONE */ - __IOM uint32_t FIFO_AEMPTY_WFIFO_MASK : 1; /*!< [3..3] NONE */ - __IOM uint32_t FIFO_AFULL_WFIFO_MASK : 1; /*!< [4..4] NONE */ - __IOM uint32_t FIFO_FULL_WFIFO_MASK : 1; /*!< [5..5] NONE */ - __IOM uint32_t FIFO_EMPTY_RFIFO_MASK : 1; /*!< [6..6] NONE */ - __IOM uint32_t RESERVED1 : 25; /*!< [31..7] reserved for future use */ + __IOM unsigned int GSPI_INTR_MASK : 1; /*!< [0..0] GSPI Interrupt mask bit */ + __IOM unsigned int FIFO_AEMPTY_RFIFO_MASK : 1; /*!< [1..1] NONE */ + __IOM unsigned int FIFO_AFULL_RFIFO_MASK : 1; /*!< [2..2] NONE */ + __IOM unsigned int FIFO_AEMPTY_WFIFO_MASK : 1; /*!< [3..3] NONE */ + __IOM unsigned int FIFO_AFULL_WFIFO_MASK : 1; /*!< [4..4] NONE */ + __IOM unsigned int FIFO_FULL_WFIFO_MASK : 1; /*!< [5..5] NONE */ + __IOM unsigned int FIFO_EMPTY_RFIFO_MASK : 1; /*!< [6..6] NONE */ + __IOM unsigned int RESERVED1 : 25; /*!< [31..7] reserved for future use */ } GSPI_INTR_MASK_b; }; union { - __IOM uint32_t GSPI_INTR_UNMASK; /*!< (@ 0x00000028) GSPI Interrupt Unmask + __IOM unsigned int GSPI_INTR_UNMASK; /*!< (@ 0x00000028) GSPI Interrupt Unmask Register */ struct { - __IOM uint32_t GSPI_INTR_UNMASK : 1; /*!< [0..0] GSPI Interrupt unmask bit */ - __IOM uint32_t FIFO_AEMPTY_RFIFO_UNMASK : 1; /*!< [1..1] NONE */ - __IOM uint32_t FIFO_AFULL_RFIFO_UNMASK : 1; /*!< [2..2] NONE */ - __IOM uint32_t FIFO_AEMPTY_WFIFO_UNMASK : 1; /*!< [3..3] NONE */ - __IOM uint32_t FIFO_AFULL_WFIFO_UNMASK : 1; /*!< [4..4] NONE */ - __IOM uint32_t FIFO_FULL_WFIFO_UNMASK : 1; /*!< [5..5] NONE */ - __IOM uint32_t FIFO_EMPTY_RFIFO_UNMASK : 1; /*!< [6..6] NONE */ - __IOM uint32_t RESERVED1 : 25; /*!< [31..7] reserved for future use */ + __IOM unsigned int GSPI_INTR_UNMASK : 1; /*!< [0..0] GSPI Interrupt unmask bit */ + __IOM unsigned int FIFO_AEMPTY_RFIFO_UNMASK : 1; /*!< [1..1] NONE */ + __IOM unsigned int FIFO_AFULL_RFIFO_UNMASK : 1; /*!< [2..2] NONE */ + __IOM unsigned int FIFO_AEMPTY_WFIFO_UNMASK : 1; /*!< [3..3] NONE */ + __IOM unsigned int FIFO_AFULL_WFIFO_UNMASK : 1; /*!< [4..4] NONE */ + __IOM unsigned int FIFO_FULL_WFIFO_UNMASK : 1; /*!< [5..5] NONE */ + __IOM unsigned int FIFO_EMPTY_RFIFO_UNMASK : 1; /*!< [6..6] NONE */ + __IOM unsigned int RESERVED1 : 25; /*!< [31..7] reserved for future use */ } GSPI_INTR_UNMASK_b; }; union { - __IM uint32_t GSPI_INTR_STS; /*!< (@ 0x0000002C) GSPI Interrupt Status Register */ + __IM unsigned int GSPI_INTR_STS; /*!< (@ 0x0000002C) GSPI Interrupt Status Register */ struct { - __IM uint32_t GSPI_INTR_LVL : 1; /*!< [0..0] GSPI Interrupt status bit */ - __IM uint32_t FIFO_AEMPTY_RFIFO_LVL : 1; /*!< [1..1] NONE */ - __IM uint32_t FIFO_AFULL_RFIFO_LVL : 1; /*!< [2..2] NONE */ - __IM uint32_t FIFO_AEMPTY_WFIFO_LVL : 1; /*!< [3..3] NONE */ - __IM uint32_t FIFO_AFULL_WFIFO_LVL : 1; /*!< [4..4] NONE */ - __IM uint32_t FIFO_FULL_WFIFO_LVL : 1; /*!< [5..5] NONE */ - __IM uint32_t FIFO_EMPTY_RFIFO_LVL : 1; /*!< [6..6] NONE */ - __IM uint32_t RESERVED2 : 25; /*!< [31..7] reserved for future use */ + __IM unsigned int GSPI_INTR_LVL : 1; /*!< [0..0] GSPI Interrupt status bit */ + __IM unsigned int FIFO_AEMPTY_RFIFO_LVL : 1; /*!< [1..1] NONE */ + __IM unsigned int FIFO_AFULL_RFIFO_LVL : 1; /*!< [2..2] NONE */ + __IM unsigned int FIFO_AEMPTY_WFIFO_LVL : 1; /*!< [3..3] NONE */ + __IM unsigned int FIFO_AFULL_WFIFO_LVL : 1; /*!< [4..4] NONE */ + __IM unsigned int FIFO_FULL_WFIFO_LVL : 1; /*!< [5..5] NONE */ + __IM unsigned int FIFO_EMPTY_RFIFO_LVL : 1; /*!< [6..6] NONE */ + __IM unsigned int RESERVED2 : 25; /*!< [31..7] reserved for future use */ } GSPI_INTR_STS_b; }; union { - __OM uint32_t GSPI_INTR_ACK; /*!< (@ 0x00000030) GSPI Interrupt Acknowledge + __OM unsigned int GSPI_INTR_ACK; /*!< (@ 0x00000030) GSPI Interrupt Acknowledge Register */ struct { - __OM uint32_t GSPI_INTR_ACK : 1; /*!< [0..0] GSPI Interrupt status bit */ - __OM uint32_t FIFO_AEMPTY_RFIFO_ACK : 1; /*!< [1..1] NONE */ - __OM uint32_t FIFO_AFULL_RFIFO_ACK : 1; /*!< [2..2] NONE */ - __OM uint32_t FIFO_AEMPTY_WFIFO_ACK : 1; /*!< [3..3] NONE */ - __OM uint32_t FIFO_AFULL_WFIFO_ACK : 1; /*!< [4..4] NONE */ - __OM uint32_t FIFO_FULL_WFIFO_ACK : 1; /*!< [5..5] NONE */ - __OM uint32_t FIFO_EMPTY_RFIFO_ACK : 1; /*!< [6..6] NONE */ - __OM uint32_t RESERVED2 : 25; /*!< [31..7] reserved1 */ + __OM unsigned int GSPI_INTR_ACK : 1; /*!< [0..0] GSPI Interrupt status bit */ + __OM unsigned int FIFO_AEMPTY_RFIFO_ACK : 1; /*!< [1..1] NONE */ + __OM unsigned int FIFO_AFULL_RFIFO_ACK : 1; /*!< [2..2] NONE */ + __OM unsigned int FIFO_AEMPTY_WFIFO_ACK : 1; /*!< [3..3] NONE */ + __OM unsigned int FIFO_AFULL_WFIFO_ACK : 1; /*!< [4..4] NONE */ + __OM unsigned int FIFO_FULL_WFIFO_ACK : 1; /*!< [5..5] NONE */ + __OM unsigned int FIFO_EMPTY_RFIFO_ACK : 1; /*!< [6..6] NONE */ + __OM unsigned int RESERVED2 : 25; /*!< [31..7] reserved1 */ } GSPI_INTR_ACK_b; }; union { - __IM uint32_t GSPI_STS_MC; /*!< (@ 0x00000034) GSPI State Machine Monitor + __IM unsigned int GSPI_STS_MC; /*!< (@ 0x00000034) GSPI State Machine Monitor Register */ struct { - __IM uint32_t BUS_CTRL_PSTATE : 3; /*!< [2..0] Provides SPI bus controller + __IM unsigned int BUS_CTRL_PSTATE : 3; /*!< [2..0] Provides SPI bus controller present state */ - __IM uint32_t SPI_RD_CNT : 13; /*!< [15..3] number of pending bytes to be + __IM unsigned int SPI_RD_CNT : 13; /*!< [15..3] number of pending bytes to be read by device */ - __IM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ } GSPI_STS_MC_b; }; union { - __IOM uint32_t GSPI_CLK_DIV; /*!< (@ 0x00000038) GSPI Clock Division Factor + __IOM unsigned int GSPI_CLK_DIV; /*!< (@ 0x00000038) GSPI Clock Division Factor Register */ struct { - __IOM uint32_t GSPI_CLK_DIV_FACTOR : 8; /*!< [7..0] Provides GSPI clock division + __IOM unsigned int GSPI_CLK_DIV_FACTOR : 8; /*!< [7..0] Provides GSPI clock division factor to the clock divider, which takes SOC clock as input clock and generates required clock according to division factor */ - __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ } GSPI_CLK_DIV_b; }; union { - __IOM uint32_t GSPI_CONFIG3; /*!< (@ 0x0000003C) GSPI Configuration 3 Register */ + __IOM unsigned int GSPI_CONFIG3; /*!< (@ 0x0000003C) GSPI Configuration 3 Register */ struct { - __IOM uint32_t SPI_MANUAL_RD_LNTH_TO_BC : 15; /*!< [14..0] Bits are used to indicate + __IOM unsigned int SPI_MANUAL_RD_LNTH_TO_BC : 15; /*!< [14..0] Bits are used to indicate the total number of bytes to read from flash during read operation */ - __IOM uint32_t RESERVED1 : 17; /*!< [31..15] reserved1 */ + __IOM unsigned int RESERVED1 : 17; /*!< [31..15] reserved1 */ } GSPI_CONFIG3_b; }; - __IM uint32_t RESERVED1[16]; + __IM unsigned int RESERVED1[16]; union { union { - __OM uint32_t GSPI_WRITE_FIFO[16]; /*!< (@ 0x00000080) GSPI fifo */ + __OM unsigned int GSPI_WRITE_FIFO[16]; /*!< (@ 0x00000080) GSPI fifo */ struct { - __OM uint32_t WRITE_FIFO : 32; /*!< [31..0] FIFO data is write to this + __OM unsigned int WRITE_FIFO : 32; /*!< [31..0] FIFO data is write to this address space */ } GSPI_WRITE_FIFO_b[16]; }; union { - __IM uint32_t GSPI_READ_FIFO[16]; /*!< (@ 0x00000080) GSPI READ FIFO */ + __IM unsigned int GSPI_READ_FIFO[16]; /*!< (@ 0x00000080) GSPI READ FIFO */ struct { - __IM uint32_t READ_FIFO : 32; /*!< [31..0] FIFO data is read from this + __IM unsigned int READ_FIFO : 32; /*!< [31..0] FIFO data is read from this address space */ } GSPI_READ_FIFO_b[16]; }; @@ -4562,343 +4562,343 @@ typedef struct { /*!< (@ 0x45030000) GSPI0 Structure */ typedef struct { /*!< (@ 0x44020000) SSI0 Structure */ union { - __IOM uint32_t CTRLR0; /*!< (@ 0x00000000) Control Register 0 */ + __IOM unsigned int CTRLR0; /*!< (@ 0x00000000) Control Register 0 */ struct { - __IOM uint32_t DFS : 4; /*!< [3..0] Select the data frame length (4-bit to + __IOM unsigned int DFS : 4; /*!< [3..0] Select the data frame length (4-bit to 16-bit serial data transfers) */ - __IOM uint32_t FRF : 2; /*!< [5..4] Frame Format, Selects which serial + __IOM unsigned int FRF : 2; /*!< [5..4] Frame Format, Selects which serial protocol transfers the data */ - __IOM uint32_t SCPH : 1; /*!< [6..6] Serial Clock Phase. Valid when the + __IOM unsigned int SCPH : 1; /*!< [6..6] Serial Clock Phase. Valid when the frame format (FRF) is set to Motorola SPI */ - __IOM uint32_t SCPOL : 1; /*!< [7..7] Serial Clock Polarity. Valid when the frame + __IOM unsigned int SCPOL : 1; /*!< [7..7] Serial Clock Polarity. Valid when the frame format (FRF) is set to Motorola SPI */ - __IOM uint32_t TMOD : 2; /*!< [9..8] Selects the mode of transfer for + __IOM unsigned int TMOD : 2; /*!< [9..8] Selects the mode of transfer for serial communication */ - __IOM uint32_t SLV_OE : 1; /*!< [10..10] DW_apb_ssi is configured as a + __IOM unsigned int SLV_OE : 1; /*!< [10..10] DW_apb_ssi is configured as a serial-slave device */ - __IOM uint32_t SRL : 1; /*!< [11..11] Shift Register Loop Used for testing + __IOM unsigned int SRL : 1; /*!< [11..11] Shift Register Loop Used for testing purposes only */ - __IOM uint32_t CFS : 4; /*!< [15..12] Control Frame Size Selects the length of the + __IOM unsigned int CFS : 4; /*!< [15..12] Control Frame Size Selects the length of the control word for the Micro wire frame format */ - __IOM uint32_t DFS_32 : 5; /*!< [20..16] Selects the data frame length */ - __IOM uint32_t SPI_FRF : 2; /*!< [22..21] Selects data frame format for + __IOM unsigned int DFS_32 : 5; /*!< [20..16] Selects the data frame length */ + __IOM unsigned int SPI_FRF : 2; /*!< [22..21] Selects data frame format for transmitting or receiving data */ - __IOM uint32_t RESERVED1 : 9; /*!< [31..23] Reserved for future use */ + __IOM unsigned int RESERVED1 : 9; /*!< [31..23] Reserved for future use */ } CTRLR0_b; }; union { - __IOM uint32_t CTRLR1; /*!< (@ 0x00000004) Control Register 1 */ + __IOM unsigned int CTRLR1; /*!< (@ 0x00000004) Control Register 1 */ struct { - __IOM uint32_t NDF : 16; /*!< [15..0] Number of Data Frames.When TMOD = 10 or TMOD = + __IOM unsigned int NDF : 16; /*!< [15..0] Number of Data Frames.When TMOD = 10 or TMOD = 11, this register field sets the number of data frames to be continuously received by the ssi_master */ - __IOM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use. */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use. */ } CTRLR1_b; }; union { - __IOM uint32_t SSIENR; /*!< (@ 0x00000008) SSI Enable Register */ + __IOM unsigned int SSIENR; /*!< (@ 0x00000008) SSI Enable Register */ struct { - __IOM uint32_t SSI_EN : 1; /*!< [0..0] Enables and disables all ssi operations */ - __IOM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + __IOM unsigned int SSI_EN : 1; /*!< [0..0] Enables and disables all ssi operations */ + __IOM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */ } SSIENR_b; }; union { - __IOM uint32_t MWCR; /*!< (@ 0x0000000C) Micro wire Control Register */ + __IOM unsigned int MWCR; /*!< (@ 0x0000000C) Micro wire Control Register */ struct { - __IOM uint32_t MWMOD : 1; /*!< [0..0] The Micro wire transfer is + __IOM unsigned int MWMOD : 1; /*!< [0..0] The Micro wire transfer is sequential or non-sequential */ - __IOM uint32_t MDD : 1; /*!< [1..1] The direction of the data word when + __IOM unsigned int MDD : 1; /*!< [1..1] The direction of the data word when the Micro wire serial protocol is used */ - __IOM uint32_t MHS : 1; /*!< [2..2] Microwire Handshaking. Used to enable + __IOM unsigned int MHS : 1; /*!< [2..2] Microwire Handshaking. Used to enable and disable the busy/ready handshaking interface for the Microwire protocol */ - __IOM uint32_t RESERVED1 : 29; /*!< [31..3] Reserved for future use */ + __IOM unsigned int RESERVED1 : 29; /*!< [31..3] Reserved for future use */ } MWCR_b; }; union { - __IOM uint32_t SER; /*!< (@ 0x00000010) SLAVE ENABLE REGISTER */ + __IOM unsigned int SER; /*!< (@ 0x00000010) SLAVE ENABLE REGISTER */ struct { - __IOM uint32_t SER : 4; /*!< [3..0] Each bit in this register corresponds to a slave + __IOM unsigned int SER : 4; /*!< [3..0] Each bit in this register corresponds to a slave select line (ss_x_n) from the SSI master. */ - __IOM uint32_t RESERVED1 : 28; /*!< [31..4] Reserved for future use */ + __IOM unsigned int RESERVED1 : 28; /*!< [31..4] Reserved for future use */ } SER_b; }; union { - __IOM uint32_t BAUDR; /*!< (@ 0x00000014) Baud Rate Select Register */ + __IOM unsigned int BAUDR; /*!< (@ 0x00000014) Baud Rate Select Register */ struct { - __IOM uint32_t SCKDV : 16; /*!< [15..0] SSI Clock Divider.The LSB for this + __IOM unsigned int SCKDV : 16; /*!< [15..0] SSI Clock Divider.The LSB for this field is always set to 0 and is unaffected by a write operation, which ensures an even value is held in this register */ - __IOM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use */ } BAUDR_b; }; union { - __IOM uint32_t TXFTLR; /*!< (@ 0x00000018) Transmit FIFO Threshold Level Register */ + __IOM unsigned int TXFTLR; /*!< (@ 0x00000018) Transmit FIFO Threshold Level Register */ struct { - __IOM uint32_t TFT : 4; /*!< [3..0] Controls the level of entries (or below) at which + __IOM unsigned int TFT : 4; /*!< [3..0] Controls the level of entries (or below) at which the transmit FIFO controller triggers an interrupt */ - __IOM uint32_t RESERVED1 : 28; /*!< [31..4] Reserved for future use */ + __IOM unsigned int RESERVED1 : 28; /*!< [31..4] Reserved for future use */ } TXFTLR_b; }; union { - __IOM uint32_t RXFTLR; /*!< (@ 0x0000001C) Receive FIFO Threshold Level */ + __IOM unsigned int RXFTLR; /*!< (@ 0x0000001C) Receive FIFO Threshold Level */ struct { - __IOM uint32_t RFT : 4; /*!< [3..0] Controls the level of entries (or above) at which + __IOM unsigned int RFT : 4; /*!< [3..0] Controls the level of entries (or above) at which the receive FIFO controller triggers an interrupt */ - __IOM uint32_t RESERVED1 : 28; /*!< [31..4] Reserved for future use */ + __IOM unsigned int RESERVED1 : 28; /*!< [31..4] Reserved for future use */ } RXFTLR_b; }; union { - __IM uint32_t TXFLR; /*!< (@ 0x00000020) Transmit FIFO Level Register */ + __IM unsigned int TXFLR; /*!< (@ 0x00000020) Transmit FIFO Level Register */ struct { - __IM uint32_t TXTFL : 5; /*!< [4..0] Contains the number of valid data + __IM unsigned int TXTFL : 5; /*!< [4..0] Contains the number of valid data entries in the transmit FIFO */ - __IM uint32_t RESERVED1 : 27; /*!< [31..5] Reserved for future use */ + __IM unsigned int RESERVED1 : 27; /*!< [31..5] Reserved for future use */ } TXFLR_b; }; union { - __IM uint32_t RXFLR; /*!< (@ 0x00000024) Receive FIFO Level Register */ + __IM unsigned int RXFLR; /*!< (@ 0x00000024) Receive FIFO Level Register */ struct { - __IM uint32_t RXTFL : 5; /*!< [4..0] Contains the number of valid data + __IM unsigned int RXTFL : 5; /*!< [4..0] Contains the number of valid data entries in the receive FIFO */ - __IM uint32_t RESERVED1 : 27; /*!< [31..5] Reserved for future use */ + __IM unsigned int RESERVED1 : 27; /*!< [31..5] Reserved for future use */ } RXFLR_b; }; union { - __IM uint32_t SR; /*!< (@ 0x00000028) Status Register */ + __IM unsigned int SR; /*!< (@ 0x00000028) Status Register */ struct { - __IM uint32_t BUSY : 1; /*!< [0..0] indicates that a serial transfer is in + __IM unsigned int BUSY : 1; /*!< [0..0] indicates that a serial transfer is in progress */ - __IM uint32_t TFNF : 1; /*!< [1..1] Set when the transmit FIFO contains one or more + __IM unsigned int TFNF : 1; /*!< [1..1] Set when the transmit FIFO contains one or more empty locations and is cleared when the FIFO is full */ - __IM uint32_t TFE : 1; /*!< [2..2] When the transmit FIFO is completely + __IM unsigned int TFE : 1; /*!< [2..2] When the transmit FIFO is completely empty this bit is set */ - __IM uint32_t RFNE : 1; /*!< [3..3] Set when the receive FIFO contains one + __IM unsigned int RFNE : 1; /*!< [3..3] Set when the receive FIFO contains one or more entries and is cleared when the receive FIFO is empty */ - __IM uint32_t RFF : 1; /*!< [4..4] When the receive FIFO is completely + __IM unsigned int RFF : 1; /*!< [4..4] When the receive FIFO is completely full this bit is set */ - __IM uint32_t TXE : 1; /*!< [5..5] This bit is cleared when read */ - __IM uint32_t DCOL : 1; /*!< [6..6] This bit is set if the ss_in_n input + __IM unsigned int TXE : 1; /*!< [5..5] This bit is cleared when read */ + __IM unsigned int DCOL : 1; /*!< [6..6] This bit is set if the ss_in_n input is asserted by another master, while the ssi master is in the middle of the transfer */ - __IM uint32_t RESERVED1 : 25; /*!< [31..7] Reserved for future use */ + __IM unsigned int RESERVED1 : 25; /*!< [31..7] Reserved for future use */ } SR_b; }; union { - __IOM uint32_t IMR; /*!< (@ 0x0000002C) Interrupt Mask Register */ + __IOM unsigned int IMR; /*!< (@ 0x0000002C) Interrupt Mask Register */ struct { - __IOM uint32_t TXEIM : 1; /*!< [0..0] Transmit FIFO Empty Interrupt Mask */ - __IOM uint32_t TXOIM : 1; /*!< [1..1] Transmit FIFO Overflow Interrupt Mask */ - __IOM uint32_t RXUIM : 1; /*!< [2..2] Receive FIFO Underflow Interrupt Mask */ - __IOM uint32_t RXOIM : 1; /*!< [3..3] Receive FIFO Overflow Interrupt Mask */ - __IOM uint32_t RXFIM : 1; /*!< [4..4] Receive FIFO Full Interrupt Mask */ - __IOM uint32_t MSTIM : 1; /*!< [5..5] Multi-Master Contention Interrupt Mask */ - __IM uint32_t RESERVED1 : 26; /*!< [31..6] Reserved for future use */ + __IOM unsigned int TXEIM : 1; /*!< [0..0] Transmit FIFO Empty Interrupt Mask */ + __IOM unsigned int TXOIM : 1; /*!< [1..1] Transmit FIFO Overflow Interrupt Mask */ + __IOM unsigned int RXUIM : 1; /*!< [2..2] Receive FIFO Underflow Interrupt Mask */ + __IOM unsigned int RXOIM : 1; /*!< [3..3] Receive FIFO Overflow Interrupt Mask */ + __IOM unsigned int RXFIM : 1; /*!< [4..4] Receive FIFO Full Interrupt Mask */ + __IOM unsigned int MSTIM : 1; /*!< [5..5] Multi-Master Contention Interrupt Mask */ + __IM unsigned int RESERVED1 : 26; /*!< [31..6] Reserved for future use */ } IMR_b; }; union { - __IM uint32_t ISR; /*!< (@ 0x00000030) Interrupt Status Register */ + __IM unsigned int ISR; /*!< (@ 0x00000030) Interrupt Status Register */ struct { - __IM uint32_t TXEIS : 1; /*!< [0..0] Transmit FIFO Empty Interrupt Status */ - __IM uint32_t TXOIS : 1; /*!< [1..1] Transmit FIFO Overflow Interrupt Status */ - __IM uint32_t RXUIS : 1; /*!< [2..2] Receive FIFO Underflow Interrupt Status */ - __IM uint32_t RXOIS : 1; /*!< [3..3] Receive FIFO Overflow Interrupt Status */ - __IM uint32_t RXFIS : 1; /*!< [4..4] Receive FIFO Full Interrupt Status */ - __IM uint32_t MSTIS : 1; /*!< [5..5] Multi-Master Contention Interrupt Status */ - __IM uint32_t RESERVED1 : 26; /*!< [31..6] Reserved for future use */ + __IM unsigned int TXEIS : 1; /*!< [0..0] Transmit FIFO Empty Interrupt Status */ + __IM unsigned int TXOIS : 1; /*!< [1..1] Transmit FIFO Overflow Interrupt Status */ + __IM unsigned int RXUIS : 1; /*!< [2..2] Receive FIFO Underflow Interrupt Status */ + __IM unsigned int RXOIS : 1; /*!< [3..3] Receive FIFO Overflow Interrupt Status */ + __IM unsigned int RXFIS : 1; /*!< [4..4] Receive FIFO Full Interrupt Status */ + __IM unsigned int MSTIS : 1; /*!< [5..5] Multi-Master Contention Interrupt Status */ + __IM unsigned int RESERVED1 : 26; /*!< [31..6] Reserved for future use */ } ISR_b; }; union { - __IM uint32_t RISR; /*!< (@ 0x00000034) Raw Interrupt Status Register */ + __IM unsigned int RISR; /*!< (@ 0x00000034) Raw Interrupt Status Register */ struct { - __IM uint32_t TXEIR : 1; /*!< [0..0] Transmit FIFO Empty Raw Interrupt Status */ - __IM uint32_t TXOIR : 1; /*!< [1..1] Transmit FIFO Overflow Raw Interrupt + __IM unsigned int TXEIR : 1; /*!< [0..0] Transmit FIFO Empty Raw Interrupt Status */ + __IM unsigned int TXOIR : 1; /*!< [1..1] Transmit FIFO Overflow Raw Interrupt Status */ - __IM uint32_t RXUIR : 1; /*!< [2..2] Receive FIFO Underflow Raw Interrupt + __IM unsigned int RXUIR : 1; /*!< [2..2] Receive FIFO Underflow Raw Interrupt Status */ - __IM uint32_t RXOIR : 1; /*!< [3..3] Receive FIFO Overflow Raw Interrupt Status */ - __IM uint32_t RXFIR : 1; /*!< [4..4] Receive FIFO Full Raw Interrupt Status */ - __IM uint32_t MSTIR : 1; /*!< [5..5] Multi-Master Contention Raw Interrupt + __IM unsigned int RXOIR : 1; /*!< [3..3] Receive FIFO Overflow Raw Interrupt Status */ + __IM unsigned int RXFIR : 1; /*!< [4..4] Receive FIFO Full Raw Interrupt Status */ + __IM unsigned int MSTIR : 1; /*!< [5..5] Multi-Master Contention Raw Interrupt Status */ - __IM uint32_t RESERVED1 : 26; /*!< [31..6] Reserved for future use */ + __IM unsigned int RESERVED1 : 26; /*!< [31..6] Reserved for future use */ } RISR_b; }; union { - __IM uint32_t TXOICR; /*!< (@ 0x00000038) Transmit FIFO Overflow Interrupt + __IM unsigned int TXOICR; /*!< (@ 0x00000038) Transmit FIFO Overflow Interrupt Clear Register */ struct { - __IM uint32_t TXOICR : 1; /*!< [0..0] Clear Transmit FIFO Overflow Interrupt This + __IM unsigned int TXOICR : 1; /*!< [0..0] Clear Transmit FIFO Overflow Interrupt This register reflects the status of the interrupt */ - __IM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */ } TXOICR_b; }; union { - __IM uint32_t RXOICR; /*!< (@ 0x0000003C) Receive FIFO Overflow Interrupt + __IM unsigned int RXOICR; /*!< (@ 0x0000003C) Receive FIFO Overflow Interrupt Clear Register */ struct { - __IM uint32_t RXOICR : 1; /*!< [0..0] This register reflects the status of + __IM unsigned int RXOICR : 1; /*!< [0..0] This register reflects the status of the interrupt A read from this register clears the ssi_rxo_intr interrupt */ - __IM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */ } RXOICR_b; }; union { - __IM uint32_t RXUICR; /*!< (@ 0x00000040) Receive FIFO Underflow Interrupt + __IM unsigned int RXUICR; /*!< (@ 0x00000040) Receive FIFO Underflow Interrupt Clear Register */ struct { - __IM uint32_t RXUICR : 1; /*!< [0..0] This register reflects the status of + __IM unsigned int RXUICR : 1; /*!< [0..0] This register reflects the status of the interrupt A read from this register clears the ssi_rxu_intr interrupt */ - __IM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */ } RXUICR_b; }; union { - __IM uint32_t MSTICR; /*!< (@ 0x00000044) Multi-Master Interrupt Clear Register */ + __IM unsigned int MSTICR; /*!< (@ 0x00000044) Multi-Master Interrupt Clear Register */ struct { - __IM uint32_t MSTICR : 1; /*!< [0..0] This register reflects the status of + __IM unsigned int MSTICR : 1; /*!< [0..0] This register reflects the status of the interrupt A read from this register clears the ssi_mst_intr interrupt */ - __IM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */ } MSTICR_b; }; union { - __IM uint32_t ICR; /*!< (@ 0x00000048) Interrupt Clear Register */ + __IM unsigned int ICR; /*!< (@ 0x00000048) Interrupt Clear Register */ struct { - __IM uint32_t ICR : 1; /*!< [0..0] This register is set if any of the + __IM unsigned int ICR : 1; /*!< [0..0] This register is set if any of the interrupts below are active A read clears the ssi_txo_intr, ssi_rxu_intr, ssi_rxo_intr, and the ssi_mst_intr interrupts */ - __IM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */ } ICR_b; }; union { - __IOM uint32_t DMACR; /*!< (@ 0x0000004C) DMA Control Register */ + __IOM unsigned int DMACR; /*!< (@ 0x0000004C) DMA Control Register */ struct { - __IOM uint32_t RDMAE : 1; /*!< [0..0] This bit enables/disables the + __IOM unsigned int RDMAE : 1; /*!< [0..0] This bit enables/disables the receive FIFO DMA channel */ - __IOM uint32_t TDMAE : 1; /*!< [1..1] This bit enables/disables the + __IOM unsigned int TDMAE : 1; /*!< [1..1] This bit enables/disables the transmit FIFO DMA channel */ - __IM uint32_t RESERVED1 : 30; /*!< [31..2] Reserved for future use */ + __IM unsigned int RESERVED1 : 30; /*!< [31..2] Reserved for future use */ } DMACR_b; }; union { - __IOM uint32_t DMATDLR; /*!< (@ 0x00000050) DMA Transmit Data Level */ + __IOM unsigned int DMATDLR; /*!< (@ 0x00000050) DMA Transmit Data Level */ struct { - __IOM uint32_t DMATDL : 4; /*!< [3..0] This bit field controls the level at which a + __IOM unsigned int DMATDL : 4; /*!< [3..0] This bit field controls the level at which a DMA request is made by the transmit logic */ - __IM uint32_t RESERVED1 : 28; /*!< [31..4] Reserved for future use */ + __IM unsigned int RESERVED1 : 28; /*!< [31..4] Reserved for future use */ } DMATDLR_b; }; union { - __IOM uint32_t DMARDLR; /*!< (@ 0x00000054) DMA Receive Data Level Register */ + __IOM unsigned int DMARDLR; /*!< (@ 0x00000054) DMA Receive Data Level Register */ struct { - __IOM uint32_t DMARDL : 4; /*!< [3..0] This bit field controls the level at which a + __IOM unsigned int DMARDL : 4; /*!< [3..0] This bit field controls the level at which a DMA request is made by the receive logic */ - __IOM uint32_t RESERVED1 : 28; /*!< [31..4] Reserved for future use */ + __IOM unsigned int RESERVED1 : 28; /*!< [31..4] Reserved for future use */ } DMARDLR_b; }; union { - __IM uint32_t IDR; /*!< (@ 0x00000058) Identification Register */ + __IM unsigned int IDR; /*!< (@ 0x00000058) Identification Register */ struct { - __IM uint32_t IDCODE : 32; /*!< [31..0] This register contains the + __IM unsigned int IDCODE : 32; /*!< [31..0] This register contains the peripherals identification code */ } IDR_b; }; union { - __IM uint32_t SSI_COMP_VERSION; /*!< (@ 0x0000005C) coreKit version ID register */ + __IM unsigned int SSI_COMP_VERSION; /*!< (@ 0x0000005C) coreKit version ID register */ struct { - __IM uint32_t SSI_COMP_VERSION : 32; /*!< [31..0] Contains the hex representation of + __IM unsigned int SSI_COMP_VERSION : 32; /*!< [31..0] Contains the hex representation of the Synopsys component version */ } SSI_COMP_VERSION_b; }; union { - __IOM uint32_t DR; /*!< (@ 0x00000060) Data Register */ + __IOM unsigned int DR; /*!< (@ 0x00000060) Data Register */ struct { - __IOM uint32_t DR : 32; /*!< [31..0] When writing to this register must + __IOM unsigned int DR : 32; /*!< [31..0] When writing to this register must right-justify the data */ } DR_b; }; - __IM uint32_t RESERVED[35]; + __IM unsigned int RESERVED[35]; union { - __IOM uint32_t RX_SAMPLE_DLY; /*!< (@ 0x000000F0) Rx Sample Delay Register */ + __IOM unsigned int RX_SAMPLE_DLY; /*!< (@ 0x000000F0) Rx Sample Delay Register */ struct { - __IOM uint32_t RSD : 8; /*!< [7..0] Receive Data (rxd) Sample Delay. This register is + __IOM unsigned int RSD : 8; /*!< [7..0] Receive Data (rxd) Sample Delay. This register is used to delay the sample of the rxd input signal. */ - __IOM uint32_t RESERVED1 : 24; /*!< [31..8] Reserved for future use */ + __IOM unsigned int RESERVED1 : 24; /*!< [31..8] Reserved for future use */ } RX_SAMPLE_DLY_b; }; union { - __IOM uint32_t SPI_CTRLR0; /*!< (@ 0x000000F4) SPI control Register */ + __IOM unsigned int SPI_CTRLR0; /*!< (@ 0x000000F4) SPI control Register */ struct { - __IOM uint32_t TRANS_TYPE : 2; /*!< [1..0] Address and instruction + __IOM unsigned int TRANS_TYPE : 2; /*!< [1..0] Address and instruction transfer format */ - __IOM uint32_t ADDR_L : 4; /*!< [5..2] This bit defines length of address to be + __IOM unsigned int ADDR_L : 4; /*!< [5..2] This bit defines length of address to be transmitted, The transfer begins only after these many bits are programmed into the FIFO */ - __IM uint32_t RESERVED1 : 2; /*!< [7..6] Reserved for future use */ - __IOM uint32_t INST_L : 2; /*!< [9..8] DUAL/QUAD length in bits */ - __IM uint32_t RESERVED2 : 1; /*!< [10..10] Reserved for future use */ - __IOM uint32_t WAIT_CYCLES : 4; /*!< [14..11] This bit defines the wait cycles in + __IM unsigned int RESERVED1 : 2; /*!< [7..6] Reserved for future use */ + __IOM unsigned int INST_L : 2; /*!< [9..8] DUAL/QUAD length in bits */ + __IM unsigned int RESERVED2 : 1; /*!< [10..10] Reserved for future use */ + __IOM unsigned int WAIT_CYCLES : 4; /*!< [14..11] This bit defines the wait cycles in dual/quad mode between control frames transmit and data reception, Specified as number of SPI clock cycles */ - __IM uint32_t RESERVED3 : 17; /*!< [31..15] Reserved for future use */ + __IM unsigned int RESERVED3 : 17; /*!< [31..15] Reserved for future use */ } SPI_CTRLR0_b; }; } SSI0_Type; /*!< Size = 248 (0xf8) */ @@ -4917,526 +4917,526 @@ typedef struct { /*!< (@ 0x44020000) SSI0 Structure */ typedef struct { /*!< (@ 0x47000000) SIO Structure */ union { - __IOM uint32_t SIO_ENABLE_REG; /*!< (@ 0x00000000) ENABLE REGISTER */ + __IOM unsigned int SIO_ENABLE_REG; /*!< (@ 0x00000000) ENABLE REGISTER */ struct { - __IOM uint32_t SIO_OPERATION_ENABLE : 16; /*!< [15..0] Contains the + __IOM unsigned int SIO_OPERATION_ENABLE : 16; /*!< [15..0] Contains the Enables for all SIO */ - __IM uint32_t RESERVED3 : 16; /*!< [31..16] Reserved for future use */ + __IM unsigned int RESERVED3 : 16; /*!< [31..16] Reserved for future use */ } SIO_ENABLE_REG_b; }; union { - __IOM uint32_t SIO_PAUSE_REG; /*!< (@ 0x00000004) PAUSE REGISTER */ + __IOM unsigned int SIO_PAUSE_REG; /*!< (@ 0x00000004) PAUSE REGISTER */ struct { - __IOM uint32_t SIO_POSITION_COUNTER_DISABLE : 16; /*!< [15..0] Contains + __IOM unsigned int SIO_POSITION_COUNTER_DISABLE : 16; /*!< [15..0] Contains sio position counter disable for all SIOs */ - __IM uint32_t RESERVED3 : 16; /*!< [31..16] Reserved for future use */ + __IM unsigned int RESERVED3 : 16; /*!< [31..16] Reserved for future use */ } SIO_PAUSE_REG_b; }; union { - __IM uint32_t SIO_GPIO_IN_REG; /*!< (@ 0x00000008) GPIO Input Register */ + __IM unsigned int SIO_GPIO_IN_REG; /*!< (@ 0x00000008) GPIO Input Register */ struct { - __IM uint32_t IN_VALUE : 32; /*!< [31..0] GPIO input pin status */ + __IM unsigned int IN_VALUE : 32; /*!< [31..0] GPIO input pin status */ } SIO_GPIO_IN_REG_b; }; union { - __IOM uint32_t SIO_GPIO_OUT_REG; /*!< (@ 0x0000000C) GPIO Output Register */ + __IOM unsigned int SIO_GPIO_OUT_REG; /*!< (@ 0x0000000C) GPIO Output Register */ struct { - __IOM uint32_t OUT_VALUE : 32; /*!< [31..0] Value to be loaded on GPIO out pins */ + __IOM unsigned int OUT_VALUE : 32; /*!< [31..0] Value to be loaded on GPIO out pins */ } SIO_GPIO_OUT_REG_b; }; union { - __IOM uint32_t SIO_GPIO_OEN_REG; /*!< (@ 0x00000010) GPIO Output enable Register */ + __IOM unsigned int SIO_GPIO_OEN_REG; /*!< (@ 0x00000010) GPIO Output enable Register */ struct { - __IOM uint32_t OEN_VALUE : 32; /*!< [31..0] OEN for the GPIO pins */ + __IOM unsigned int OEN_VALUE : 32; /*!< [31..0] OEN for the GPIO pins */ } SIO_GPIO_OEN_REG_b; }; union { - __IOM uint32_t SIO_GPIO_INTR_EN_SET_REG; /*!< (@ 0x00000014) GPIO Interrupt + __IOM unsigned int SIO_GPIO_INTR_EN_SET_REG; /*!< (@ 0x00000014) GPIO Interrupt Enable Set Register */ struct { - __OM uint32_t INTR_ENABLE_SET : 16; /*!< [15..0] gpio interrupt enable set + __OM unsigned int INTR_ENABLE_SET : 16; /*!< [15..0] gpio interrupt enable set register for all SIOs */ - __IM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use */ } SIO_GPIO_INTR_EN_SET_REG_b; }; union { - __OM uint32_t SIO_GPIO_INTR_EN_CLEAR_REG; /*!< (@ 0x00000018) GPIO Interrupt + __OM unsigned int SIO_GPIO_INTR_EN_CLEAR_REG; /*!< (@ 0x00000018) GPIO Interrupt Enable Clear Register */ struct { - __OM uint32_t INTR_ENABLE_CLEAR : 16; /*!< [15..0] gpio interrupt enable + __OM unsigned int INTR_ENABLE_CLEAR : 16; /*!< [15..0] gpio interrupt enable Clear register for all SIOs */ - __OM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + __OM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use */ } SIO_GPIO_INTR_EN_CLEAR_REG_b; }; union { - __IOM uint32_t SIO_GPIO_INTR_MASK_SET_REG; /*!< (@ 0x0000001C) GPIO Interrupt Enable + __IOM unsigned int SIO_GPIO_INTR_MASK_SET_REG; /*!< (@ 0x0000001C) GPIO Interrupt Enable Clear Register */ struct { - __IOM uint32_t INTR_MASK_SET : 16; /*!< [15..0] Common gpio interrupt mask + __IOM unsigned int INTR_MASK_SET : 16; /*!< [15..0] Common gpio interrupt mask set register for all SIOs */ - __IM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use */ } SIO_GPIO_INTR_MASK_SET_REG_b; }; union { - __OM uint32_t SIO_GPIO_INTR_MASK_CLEAR_REG; /*!< (@ 0x00000020) GPIO Interrupt Enable + __OM unsigned int SIO_GPIO_INTR_MASK_CLEAR_REG; /*!< (@ 0x00000020) GPIO Interrupt Enable Clear Register */ struct { - __OM uint32_t INTR_MASK_CLEAR : 16; /*!< [15..0] gpio interrupt mask clear + __OM unsigned int INTR_MASK_CLEAR : 16; /*!< [15..0] gpio interrupt mask clear register for all SIOs */ - __OM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + __OM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use */ } SIO_GPIO_INTR_MASK_CLEAR_REG_b; }; union { - __IOM uint32_t SIO_GPIO_INTR_STATUS_REG; /*!< (@ 0x00000024) GPIO Interrupt + __IOM unsigned int SIO_GPIO_INTR_STATUS_REG; /*!< (@ 0x00000024) GPIO Interrupt Status Register */ struct { - __OM uint32_t INTR_MASK_SET : 16; /*!< [15..0] Common gpio interrupt + __OM unsigned int INTR_MASK_SET : 16; /*!< [15..0] Common gpio interrupt status register for all SIOs */ - __IM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use */ } SIO_GPIO_INTR_STATUS_REG_b; }; union { - __IM uint32_t SIO_SHIFT_COUNTER[16]; /*!< (@ 0x00000028) Shift counter register */ + __IM unsigned int SIO_SHIFT_COUNTER[16]; /*!< (@ 0x00000028) Shift counter register */ struct { - __IM uint32_t SHIFT_COUNTER : 14; /*!< [13..0] shift counter current value */ - __IM uint32_t RESERVED1 : 18; /*!< [31..14] Reserved for future use */ + __IM unsigned int SHIFT_COUNTER : 14; /*!< [13..0] shift counter current value */ + __IM unsigned int RESERVED1 : 18; /*!< [31..14] Reserved for future use */ } SIO_SHIFT_COUNTER_b[16]; }; union { - __IOM uint32_t SIO_BUFFER_REG[16]; /*!< (@ 0x00000068) Buffer Register */ + __IOM unsigned int SIO_BUFFER_REG[16]; /*!< (@ 0x00000068) Buffer Register */ struct { - __IOM uint32_t DATA : 32; /*!< [31..0] Data to load into the shift register */ + __IOM unsigned int DATA : 32; /*!< [31..0] Data to load into the shift register */ } SIO_BUFFER_REG_b[16]; }; union { - __IOM uint32_t SIO_SHIFT_COUNT_PRELOAD_REG[16]; /*!< (@ 0x000000A8) Shift counter + __IOM unsigned int SIO_SHIFT_COUNT_PRELOAD_REG[16]; /*!< (@ 0x000000A8) Shift counter Reload Register */ struct { - __IOM uint32_t RELOAD_VALUE : 14; /*!< [13..0] division factor required to + __IOM unsigned int RELOAD_VALUE : 14; /*!< [13..0] division factor required to generate shift clock */ - __IM uint32_t RESERVED1 : 1; /*!< [14..14] Reserved for future use */ - __IOM uint32_t REVERSE_LOAD : 1; /*!< [15..15] When set, the data on APB is loaded to + __IM unsigned int RESERVED1 : 1; /*!< [14..14] Reserved for future use */ + __IOM unsigned int REVERSE_LOAD : 1; /*!< [15..15] When set, the data on APB is loaded to buffer is reverse order */ - __IM uint32_t RESERVED2 : 16; /*!< [31..16] Reserved for future use */ + __IM unsigned int RESERVED2 : 16; /*!< [31..16] Reserved for future use */ } SIO_SHIFT_COUNT_PRELOAD_REG_b[16]; }; union { - __IOM uint32_t SIO_DATA_POS_COUNT_REG[16]; /*!< (@ 0x000000E8) Data Position + __IOM unsigned int SIO_DATA_POS_COUNT_REG[16]; /*!< (@ 0x000000E8) Data Position Counter Register */ struct { - __IOM uint32_t RELOAD_VALUE : 8; /*!< [7..0] No. of shifts to happen before reloading + __IOM unsigned int RELOAD_VALUE : 8; /*!< [7..0] No. of shifts to happen before reloading the shift register with data/ pausing the operation */ - __IOM uint32_t POSITION_COUNTER : 8; /*!< [15..8] The position counter can + __IOM unsigned int POSITION_COUNTER : 8; /*!< [15..8] The position counter can be loaded via AHB */ - __IM uint32_t RESERVED3 : 16; /*!< [31..16] Reserved for future use */ + __IM unsigned int RESERVED3 : 16; /*!< [31..16] Reserved for future use */ } SIO_DATA_POS_COUNT_REG_b[16]; }; union { - __IOM uint32_t SIO_CONFIG_REG[16]; /*!< (@ 0x00000128) Configuration Register */ + __IOM unsigned int SIO_CONFIG_REG[16]; /*!< (@ 0x00000128) Configuration Register */ struct { - __IOM uint32_t FULL_ENABLE : 1; /*!< [0..0] When set, fifo full indication would be + __IOM unsigned int FULL_ENABLE : 1; /*!< [0..0] When set, fifo full indication would be asserted when internal buffer is full */ - __IOM uint32_t EMPTY_ENABLE : 1; /*!< [1..1] When set, fifo full indication would be + __IOM unsigned int EMPTY_ENABLE : 1; /*!< [1..1] When set, fifo full indication would be asserted when internal buffer is empty */ - __IOM uint32_t EDGE_SEL : 1; /*!< [2..2] edge selection */ - __IOM uint32_t CLK_SEL : 1; /*!< [3..3] clock selection */ - __IOM uint32_t IGNORE_FIRST_SHIFT_CONDITION : 1; /*!< [4..4] data shift + __IOM unsigned int EDGE_SEL : 1; /*!< [2..2] edge selection */ + __IOM unsigned int CLK_SEL : 1; /*!< [3..3] clock selection */ + __IOM unsigned int IGNORE_FIRST_SHIFT_CONDITION : 1; /*!< [4..4] data shift condition */ - __IOM uint32_t FLOW_CONTROL_ENABLED : 1; /*!< [5..5] flow control */ - __IOM uint32_t PATTERN_MATCH_ENABLE : 1; /*!< [6..6] pattern match */ - __IOM uint32_t QUALIFIER_MODE : 1; /*!< [7..7] qualifier mode */ - __IOM uint32_t QUALIFY_CLOCK : 1; /*!< [8..8] qualify clock */ - __IOM uint32_t INVERT_CLOCK : 1; /*!< [9..9] invert clock */ - __IOM uint32_t PARALLEL_MODE : 2; /*!< [11..10] No. of bits to + __IOM unsigned int FLOW_CONTROL_ENABLED : 1; /*!< [5..5] flow control */ + __IOM unsigned int PATTERN_MATCH_ENABLE : 1; /*!< [6..6] pattern match */ + __IOM unsigned int QUALIFIER_MODE : 1; /*!< [7..7] qualifier mode */ + __IOM unsigned int QUALIFY_CLOCK : 1; /*!< [8..8] qualify clock */ + __IOM unsigned int INVERT_CLOCK : 1; /*!< [9..9] invert clock */ + __IOM unsigned int PARALLEL_MODE : 2; /*!< [11..10] No. of bits to shift/capture at valid clk edge */ - __IOM uint32_t PIN_DETECTION_MODE : 2; /*!< [13..12] Pin mode to be considered for + __IOM unsigned int PIN_DETECTION_MODE : 2; /*!< [13..12] Pin mode to be considered for gpio interrupt */ - __IOM uint32_t SET_CLK_OUT : 1; /*!< [14..14] When high sets the sio clock_out port. + __IOM unsigned int SET_CLK_OUT : 1; /*!< [14..14] When high sets the sio clock_out port. This is used only when sio is not enabled */ - __IOM uint32_t RESET_CLK_OUT : 1; /*!< [15..15] When high resets the sio + __IOM unsigned int RESET_CLK_OUT : 1; /*!< [15..15] When high resets the sio clock_out port. This is used only when sio is not enabled */ - __IOM uint32_t LOAD_DATA_POS_CNTR_VIA_APB : 1; /*!< [16..16] When set, data position + __IOM unsigned int LOAD_DATA_POS_CNTR_VIA_APB : 1; /*!< [16..16] When set, data position counter can be loaded via APB */ - __IM uint32_t RESERVED1 : 15; /*!< [31..17] Reserved for future use */ + __IM unsigned int RESERVED1 : 15; /*!< [31..17] Reserved for future use */ } SIO_CONFIG_REG_b[16]; }; union { - __IOM uint32_t SIO_PATTERN_MATCH_MASK_REG_SLICE_0; /*!< (@ 0x00000168) Pattern Match + __IOM unsigned int SIO_PATTERN_MATCH_MASK_REG_SLICE_0; /*!< (@ 0x00000168) Pattern Match Mask Register 0 */ struct { - __IOM uint32_t MATCH_MASK_LOWER16_BITS : 32; /*!< [31..0] Enable for lower + __IOM unsigned int MATCH_MASK_LOWER16_BITS : 32; /*!< [31..0] Enable for lower 16 bits */ } SIO_PATTERN_MATCH_MASK_REG_SLICE_0_b; }; union { - __IOM uint32_t SIO_PATTERN_MATCH_MASK_REG_SLICE_1; /*!< (@ 0x0000016C) Pattern Match + __IOM unsigned int SIO_PATTERN_MATCH_MASK_REG_SLICE_1; /*!< (@ 0x0000016C) Pattern Match Mask Register Slice 1 */ struct { - __IOM uint32_t MATCH_MASK_LOWER16_BITS : 32; /*!< [31..0] Enable for lower + __IOM unsigned int MATCH_MASK_LOWER16_BITS : 32; /*!< [31..0] Enable for lower 16 bits */ } SIO_PATTERN_MATCH_MASK_REG_SLICE_1_b; }; union { - __IOM uint32_t SIO_PATTERN_MATCH_MASK_REG_SLICE_2; /*!< (@ 0x00000170) Pattern Match + __IOM unsigned int SIO_PATTERN_MATCH_MASK_REG_SLICE_2; /*!< (@ 0x00000170) Pattern Match Mask Register Slice 2 */ struct { - __IOM uint32_t MATCH_MASK_LOWER16_BITS : 32; /*!< [31..0] Enable for lower + __IOM unsigned int MATCH_MASK_LOWER16_BITS : 32; /*!< [31..0] Enable for lower 16 bits */ } SIO_PATTERN_MATCH_MASK_REG_SLICE_2_b; }; - __IM uint32_t RESERVED[5]; + __IM unsigned int RESERVED[5]; union { - __IOM uint32_t SIO_PATTERN_MATCH_MASK_REG_SLICE_8; /*!< (@ 0x00000188) Pattern Match + __IOM unsigned int SIO_PATTERN_MATCH_MASK_REG_SLICE_8; /*!< (@ 0x00000188) Pattern Match Mask Register Slice 8 */ struct { - __IOM uint32_t MATCH_MASK_LOWER16_BITS : 32; /*!< [31..0] Enable for lower + __IOM unsigned int MATCH_MASK_LOWER16_BITS : 32; /*!< [31..0] Enable for lower 16 bits */ } SIO_PATTERN_MATCH_MASK_REG_SLICE_8_b; }; union { - __IOM uint32_t SIO_PATTERN_MATCH_MASK_REG_SLICE_9; /*!< (@ 0x0000018C) Pattern Match + __IOM unsigned int SIO_PATTERN_MATCH_MASK_REG_SLICE_9; /*!< (@ 0x0000018C) Pattern Match Mask Register Slice 9 */ struct { - __IOM uint32_t MATCH_MASK_LOWER16_BITS : 32; /*!< [31..0] Enable for lower + __IOM unsigned int MATCH_MASK_LOWER16_BITS : 32; /*!< [31..0] Enable for lower 16 bits */ } SIO_PATTERN_MATCH_MASK_REG_SLICE_9_b; }; union { - __IOM uint32_t SIO_PATTERN_MATCH_MASK_REG_SLICE_10; /*!< (@ 0x00000190) Pattern Match + __IOM unsigned int SIO_PATTERN_MATCH_MASK_REG_SLICE_10; /*!< (@ 0x00000190) Pattern Match Mask Register Slice 10 */ struct { - __IOM uint32_t MATCH_MASK_LOWER16_BITS : 32; /*!< [31..0] Enable for lower + __IOM unsigned int MATCH_MASK_LOWER16_BITS : 32; /*!< [31..0] Enable for lower 16 bits */ } SIO_PATTERN_MATCH_MASK_REG_SLICE_10_b; }; - __IM uint32_t RESERVED1[5]; + __IM unsigned int RESERVED1[5]; union { - __IOM uint32_t SIO_PATTERN_MATCH_REG_SLICE_0; /*!< (@ 0x000001A8) Pattern Match Mask + __IOM unsigned int SIO_PATTERN_MATCH_REG_SLICE_0; /*!< (@ 0x000001A8) Pattern Match Mask Register Slice 0 */ struct { - __IOM uint32_t PATTERN_MATCH_LOWER16_BITS : 32; /*!< [31..0] Lower 16-bits of pattern + __IOM unsigned int PATTERN_MATCH_LOWER16_BITS : 32; /*!< [31..0] Lower 16-bits of pattern to be detected */ } SIO_PATTERN_MATCH_REG_SLICE_0_b; }; union { - __IOM uint32_t SIO_PATTERN_MATCH_REG_SLICE_1; /*!< (@ 0x000001AC) Pattern Match Mask + __IOM unsigned int SIO_PATTERN_MATCH_REG_SLICE_1; /*!< (@ 0x000001AC) Pattern Match Mask Register Slice 1 */ struct { - __IOM uint32_t PATTERN_MATCH_LOWER16_BITS : 32; /*!< [31..0] Lower 16-bits of pattern + __IOM unsigned int PATTERN_MATCH_LOWER16_BITS : 32; /*!< [31..0] Lower 16-bits of pattern to be detected */ } SIO_PATTERN_MATCH_REG_SLICE_1_b; }; union { - __IOM uint32_t SIO_PATTERN_MATCH_REG_SLICE_2; /*!< (@ 0x000001B0) Pattern Match Mask + __IOM unsigned int SIO_PATTERN_MATCH_REG_SLICE_2; /*!< (@ 0x000001B0) Pattern Match Mask Register Slice 2 */ struct { - __IOM uint32_t PATTERN_MATCH_LOWER16_BITS : 32; /*!< [31..0] Lower 16-bits of pattern + __IOM unsigned int PATTERN_MATCH_LOWER16_BITS : 32; /*!< [31..0] Lower 16-bits of pattern to be detected */ } SIO_PATTERN_MATCH_REG_SLICE_2_b; }; - __IM uint32_t RESERVED2[5]; + __IM unsigned int RESERVED2[5]; union { - __IOM uint32_t SIO_PATTERN_MATCH_REG_SLICE_8; /*!< (@ 0x000001C8) Pattern Match Mask + __IOM unsigned int SIO_PATTERN_MATCH_REG_SLICE_8; /*!< (@ 0x000001C8) Pattern Match Mask Register Slice 8 */ struct { - __IOM uint32_t PATTERN_MATCH_LOWER16_BITS : 32; /*!< [31..0] Lower 16 bits of pattern + __IOM unsigned int PATTERN_MATCH_LOWER16_BITS : 32; /*!< [31..0] Lower 16 bits of pattern to be detected */ } SIO_PATTERN_MATCH_REG_SLICE_8_b; }; union { - __IOM uint32_t SIO_PATTERN_MATCH_REG_SLICE_9; /*!< (@ 0x000001CC) Pattern Match Mask + __IOM unsigned int SIO_PATTERN_MATCH_REG_SLICE_9; /*!< (@ 0x000001CC) Pattern Match Mask Register Slice 9 */ struct { - __IOM uint32_t PATTERN_MATCH_LOWER16_BITS : 32; /*!< [31..0] Lower 16 bits of pattern + __IOM unsigned int PATTERN_MATCH_LOWER16_BITS : 32; /*!< [31..0] Lower 16 bits of pattern to be detected */ } SIO_PATTERN_MATCH_REG_SLICE_9_b; }; union { - __IOM uint32_t SIO_PATTERN_MATCH_REG_SLICE_10; /*!< (@ 0x000001D0) Pattern Match Mask + __IOM unsigned int SIO_PATTERN_MATCH_REG_SLICE_10; /*!< (@ 0x000001D0) Pattern Match Mask Register Slice 10 */ struct { - __IOM uint32_t PATTERN_MATCH_LOWER16_BITS : 32; /*!< [31..0] Lower 16 bits of pattern + __IOM unsigned int PATTERN_MATCH_LOWER16_BITS : 32; /*!< [31..0] Lower 16 bits of pattern to be detected */ } SIO_PATTERN_MATCH_REG_SLICE_10_b; }; - __IM uint32_t RESERVED3[7]; + __IM unsigned int RESERVED3[7]; union { - __IOM uint32_t SIO_SHIFT_INTR_EN_SET_REG; /*!< (@ 0x000001F0) Shift Interrupt Enable + __IOM unsigned int SIO_SHIFT_INTR_EN_SET_REG; /*!< (@ 0x000001F0) Shift Interrupt Enable Set Register */ struct { - __IOM uint32_t INTR_ENABLE_SET : 16; /*!< [15..0] Common shift interrupt enable set + __IOM unsigned int INTR_ENABLE_SET : 16; /*!< [15..0] Common shift interrupt enable set register for all SIOs */ - __IM uint32_t RESERVED3 : 16; /*!< [31..16] Reserved for future use */ + __IM unsigned int RESERVED3 : 16; /*!< [31..16] Reserved for future use */ } SIO_SHIFT_INTR_EN_SET_REG_b; }; union { - __OM uint32_t SIO_SHIFT_INTR_EN_CLEAR_REG; /*!< (@ 0x000001F4) Shift Interrupt Enable + __OM unsigned int SIO_SHIFT_INTR_EN_CLEAR_REG; /*!< (@ 0x000001F4) Shift Interrupt Enable Clear Register */ struct { - __OM uint32_t INRT_ENABLE_CLEAR : 16; /*!< [15..0] Common shift interrupt enable + __OM unsigned int INRT_ENABLE_CLEAR : 16; /*!< [15..0] Common shift interrupt enable Clear register for all SIOs */ - __OM uint32_t RESERVED3 : 16; /*!< [31..16] Reserved for future use */ + __OM unsigned int RESERVED3 : 16; /*!< [31..16] Reserved for future use */ } SIO_SHIFT_INTR_EN_CLEAR_REG_b; }; union { - __IOM uint32_t SIO_SHIFT_INTR_MASK_SET_REG; /*!< (@ 0x000001F8) Shift Interrupt Mask + __IOM unsigned int SIO_SHIFT_INTR_MASK_SET_REG; /*!< (@ 0x000001F8) Shift Interrupt Mask Set Register */ struct { - __IOM uint32_t INTR_MASK_SET : 16; /*!< [15..0] Common shift interrupt enable Set + __IOM unsigned int INTR_MASK_SET : 16; /*!< [15..0] Common shift interrupt enable Set register for all SIOs */ - __IM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use */ } SIO_SHIFT_INTR_MASK_SET_REG_b; }; union { - __OM uint32_t SIO_SHIFT_INTR_MASK_CLEAR_REG; /*!< (@ 0x000001FC) Shift Interrupt Mask + __OM unsigned int SIO_SHIFT_INTR_MASK_CLEAR_REG; /*!< (@ 0x000001FC) Shift Interrupt Mask Clear Register */ struct { - __OM uint32_t INTR_MASK_CLEAR : 16; /*!< [15..0] Common shift interrupt mask clear + __OM unsigned int INTR_MASK_CLEAR : 16; /*!< [15..0] Common shift interrupt mask clear register for all SIOs */ - __OM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + __OM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use */ } SIO_SHIFT_INTR_MASK_CLEAR_REG_b; }; union { - __IOM uint32_t SIO_SHIFT_INTR_STATUS_REG; /*!< (@ 0x00000200) Shift + __IOM unsigned int SIO_SHIFT_INTR_STATUS_REG; /*!< (@ 0x00000200) Shift Interrupt Status Register */ struct { - __IOM uint32_t INTR_ENABLE_SET : 16; /*!< [15..0] Common shift interrupt mask clear + __IOM unsigned int INTR_ENABLE_SET : 16; /*!< [15..0] Common shift interrupt mask clear register for all SIOs */ - __IM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use */ } SIO_SHIFT_INTR_STATUS_REG_b; }; union { - __IOM uint32_t SIO_SWAP_INTR_EN_SET_REG; /*!< (@ 0x00000204) Swap Interrupt + __IOM unsigned int SIO_SWAP_INTR_EN_SET_REG; /*!< (@ 0x00000204) Swap Interrupt Enable Set Register */ struct { - __IOM uint32_t INTR_ENABLE_SET : 16; /*!< [15..0] Swap interrupt enable + __IOM unsigned int INTR_ENABLE_SET : 16; /*!< [15..0] Swap interrupt enable set register for all SIOs */ - __IM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use */ } SIO_SWAP_INTR_EN_SET_REG_b; }; union { - __OM uint32_t SIO_SWAP_INTR_EN_CLEAR_REG; /*!< (@ 0x00000208) Swap Interrupt + __OM unsigned int SIO_SWAP_INTR_EN_CLEAR_REG; /*!< (@ 0x00000208) Swap Interrupt Enable Clear Register */ struct { - __OM uint32_t INTR_ENABLE_CLEAR : 16; /*!< [15..0] Swap interrupt enable + __OM unsigned int INTR_ENABLE_CLEAR : 16; /*!< [15..0] Swap interrupt enable Clear register for all SIOs */ - __OM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + __OM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use */ } SIO_SWAP_INTR_EN_CLEAR_REG_b; }; union { - __IOM uint32_t SIO_SWAP_INTR_MASK_SET_REG; /*!< (@ 0x0000020C) Swap Interrupt Mask Set + __IOM unsigned int SIO_SWAP_INTR_MASK_SET_REG; /*!< (@ 0x0000020C) Swap Interrupt Mask Set Register */ struct { - __IOM uint32_t INTR_MASK_SET : 16; /*!< [15..0] Common swap interrupt mask + __IOM unsigned int INTR_MASK_SET : 16; /*!< [15..0] Common swap interrupt mask set register for all SIOs */ - __IM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use */ } SIO_SWAP_INTR_MASK_SET_REG_b; }; union { - __OM uint32_t SIO_SWAP_INTR_MASK_CLEAR_REG; /*!< (@ 0x00000210) Swap Interrupt Mask + __OM unsigned int SIO_SWAP_INTR_MASK_CLEAR_REG; /*!< (@ 0x00000210) Swap Interrupt Mask Clear Register */ struct { - __OM uint32_t INTR_MASK_CLEAR : 16; /*!< [15..0] Common swap interrupt mask Clear + __OM unsigned int INTR_MASK_CLEAR : 16; /*!< [15..0] Common swap interrupt mask Clear register for all SIOs */ - __OM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + __OM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use */ } SIO_SWAP_INTR_MASK_CLEAR_REG_b; }; union { - __IOM uint32_t SIO_SWAP_INTR_STATUS_REG; /*!< (@ 0x00000214) Swap Interrupt + __IOM unsigned int SIO_SWAP_INTR_STATUS_REG; /*!< (@ 0x00000214) Swap Interrupt Statusr Register */ struct { - __IOM uint32_t INTR_ENABLE_SET : 16; /*!< [15..0] Common swap interrupt + __IOM unsigned int INTR_ENABLE_SET : 16; /*!< [15..0] Common swap interrupt status register for all SIOs */ - __IM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use */ } SIO_SWAP_INTR_STATUS_REG_b; }; union { - __IOM uint32_t SIO_PATTERN_MATCH_INTR_EN_SET_REG; /*!< (@ 0x00000218) Pattern Match + __IOM unsigned int SIO_PATTERN_MATCH_INTR_EN_SET_REG; /*!< (@ 0x00000218) Pattern Match Interrupt Enable Set Register */ struct { - __IOM uint32_t INTR_ENABLE_SET : 16; /*!< [15..0] Common pattern or buffer under run + __IOM unsigned int INTR_ENABLE_SET : 16; /*!< [15..0] Common pattern or buffer under run interrupt enable set register for all SIOs. Each bit corresponds to one SIO */ - __IM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use */ } SIO_PATTERN_MATCH_INTR_EN_SET_REG_b; }; union { - __OM uint32_t SIO_PATTERN_MATCH_INTR_EN_CLEAR_REG; /*!< (@ 0x0000021C) Pattern Match + __OM unsigned int SIO_PATTERN_MATCH_INTR_EN_CLEAR_REG; /*!< (@ 0x0000021C) Pattern Match Interrupt Enable Clear Register */ struct { - __OM uint32_t INRT_ENABLE_CLEAR : 16; /*!< [15..0] Common pattern or buffer under + __OM unsigned int INRT_ENABLE_CLEAR : 16; /*!< [15..0] Common pattern or buffer under run interrupt enable clear register for all SIOs */ - __OM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + __OM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use */ } SIO_PATTERN_MATCH_INTR_EN_CLEAR_REG_b; }; union { - __IOM uint32_t SIO_PATTERN_MATCH_INTR_MASK_SET_REG; /*!< (@ 0x00000220) Pattern Match + __IOM unsigned int SIO_PATTERN_MATCH_INTR_MASK_SET_REG; /*!< (@ 0x00000220) Pattern Match Interrupt Mask Set Register */ struct { - __IOM uint32_t INTR_MASK_SET : 16; /*!< [15..0] Common pattern or buffer under run + __IOM unsigned int INTR_MASK_SET : 16; /*!< [15..0] Common pattern or buffer under run interrupt mask set register for all SIOs */ - __IM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use */ } SIO_PATTERN_MATCH_INTR_MASK_SET_REG_b; }; union { - __OM uint32_t SIO_PATTERN_MATCH_INTR_MASK_CLEAR_REG; /*!< (@ 0x00000224) Pattern Match + __OM unsigned int SIO_PATTERN_MATCH_INTR_MASK_CLEAR_REG; /*!< (@ 0x00000224) Pattern Match Interrupt Mask Clear Register */ struct { - __OM uint32_t INTR_MASK_CLEAR : 16; /*!< [15..0] Common pattern or buffer + __OM unsigned int INTR_MASK_CLEAR : 16; /*!< [15..0] Common pattern or buffer under run interrupt mask clear register for all SIOs */ - __OM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + __OM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use */ } SIO_PATTERN_MATCH_INTR_MASK_CLEAR_REG_b; }; union { - __IOM uint32_t SIO_PATTERN_MATCH_INTR_STATUS_REG; /*!< (@ 0x00000228) Pattern Match + __IOM unsigned int SIO_PATTERN_MATCH_INTR_STATUS_REG; /*!< (@ 0x00000228) Pattern Match Interrupt Status Register */ struct { - __IOM uint32_t INTR_STATUS : 16; /*!< [15..0] Common pattern interrupt + __IOM unsigned int INTR_STATUS : 16; /*!< [15..0] Common pattern interrupt status register for all SIOs */ - __IM uint32_t RESERVED3 : 16; /*!< [31..16] Reserved for future use */ + __IM unsigned int RESERVED3 : 16; /*!< [31..16] Reserved for future use */ } SIO_PATTERN_MATCH_INTR_STATUS_REG_b; }; union { - __IOM uint32_t SIO_BUFFER_INTR_STATUS_REG; /*!< (@ 0x0000022C) Buffer + __IOM unsigned int SIO_BUFFER_INTR_STATUS_REG; /*!< (@ 0x0000022C) Buffer Interrupt Status Register */ struct { - __IOM uint32_t INTR_STATUS : 16; /*!< [15..0] Common pattern interrupt + __IOM unsigned int INTR_STATUS : 16; /*!< [15..0] Common pattern interrupt status register for all SIOs */ - __IM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use */ } SIO_BUFFER_INTR_STATUS_REG_b; }; union { - __IOM uint32_t SIO_OUT_MUX_REG[16]; /*!< (@ 0x00000230) Output muxing Register */ + __IOM unsigned int SIO_OUT_MUX_REG[16]; /*!< (@ 0x00000230) Output muxing Register */ struct { - __IOM uint32_t DOUT_OEN_SEL : 3; /*!< [2..0] OEN select for GPIO pin 0 */ - __IOM uint32_t DOUT_SEL : 3; /*!< [5..3] Output mux select for GPIO pin 0 */ - __IM uint32_t RESERVED1 : 26; /*!< [31..6] Reserved for future use */ + __IOM unsigned int DOUT_OEN_SEL : 3; /*!< [2..0] OEN select for GPIO pin 0 */ + __IOM unsigned int DOUT_SEL : 3; /*!< [5..3] Output mux select for GPIO pin 0 */ + __IM unsigned int RESERVED1 : 26; /*!< [31..6] Reserved for future use */ } SIO_OUT_MUX_REG_b[16]; }; union { - __IOM uint32_t SIO_INPUT_MUX_REG[16]; /*!< (@ 0x00000270) Input muxing Register */ + __IOM unsigned int SIO_INPUT_MUX_REG[16]; /*!< (@ 0x00000270) Input muxing Register */ struct { - __IOM uint32_t CLK_SEL : 3; /*!< [2..0] Input clock select for SIO 0 */ - __IOM uint32_t QUALIFIER_SELECT : 2; /*!< [4..3] qualifier select */ - __IOM uint32_t QUALIFIER_MODE : 2; /*!< [6..5] qualifier mode */ - __IOM uint32_t DIN_SEL : 3; /*!< [9..7] Data in mux select */ - __IM uint32_t RESERVED1 : 22; /*!< [31..10] Reserved for future use */ + __IOM unsigned int CLK_SEL : 3; /*!< [2..0] Input clock select for SIO 0 */ + __IOM unsigned int QUALIFIER_SELECT : 2; /*!< [4..3] qualifier select */ + __IOM unsigned int QUALIFIER_MODE : 2; /*!< [6..5] qualifier mode */ + __IOM unsigned int DIN_SEL : 3; /*!< [9..7] Data in mux select */ + __IM unsigned int RESERVED1 : 22; /*!< [31..10] Reserved for future use */ } SIO_INPUT_MUX_REG_b[16]; }; union { - __IOM uint32_t SIO_FIFO_WR_RD_REG; /*!< (@ 0x000002B0) FIFO READ/WRITE Register */ + __IOM unsigned int SIO_FIFO_WR_RD_REG; /*!< (@ 0x000002B0) FIFO READ/WRITE Register */ struct { - __IOM uint32_t FIFO_DATA_REGISTER : 32; /*!< [31..0] Writes and read into + __IOM unsigned int FIFO_DATA_REGISTER : 32; /*!< [31..0] Writes and read into this register will be written into SIO buffer register */ } SIO_FIFO_WR_RD_REG_b; }; union { - __IOM uint32_t SIO_FIFO_WR_OFFSET_START_REG; /*!< (@ 0x000002B4) Points to start slice + __IOM unsigned int SIO_FIFO_WR_OFFSET_START_REG; /*!< (@ 0x000002B4) Points to start slice number forming the FIFO */ struct { - __IOM uint32_t SIO_START_SLICE_NUMBER : 32; /*!< [31..0] Points to start slice number + __IOM unsigned int SIO_START_SLICE_NUMBER : 32; /*!< [31..0] Points to start slice number forming the FIFO,On write, FIFO_WR_OFFSET_CNT_REG will also be reset to the value pointed written @@ -5445,52 +5445,52 @@ typedef struct { /*!< (@ 0x47000000) SIO Structure */ }; union { - __IOM uint32_t SIO_FIFO_WR_OFFSET_END_REG; /*!< (@ 0x000002B8) SIO last slice no + __IOM unsigned int SIO_FIFO_WR_OFFSET_END_REG; /*!< (@ 0x000002B8) SIO last slice no indication Register */ struct { - __IOM uint32_t SIO_END_SLICE_NUMBER : 32; /*!< [31..0] points to last + __IOM unsigned int SIO_END_SLICE_NUMBER : 32; /*!< [31..0] points to last slice no forming fifo */ } SIO_FIFO_WR_OFFSET_END_REG_b; }; union { - __IOM uint32_t SIO_FIFO_WR_OFFSET_CNT_REG; /*!< (@ 0x000002BC) Points to current slice + __IOM unsigned int SIO_FIFO_WR_OFFSET_CNT_REG; /*!< (@ 0x000002BC) Points to current slice number forming the FIFO */ struct { - __IOM uint32_t SIO_CURRENT_SLICE_NUMBER : 32; /*!< [31..0] Next FIFO operation will + __IOM unsigned int SIO_CURRENT_SLICE_NUMBER : 32; /*!< [31..0] Next FIFO operation will happen to buffer in the slice pointed by this register */ } SIO_FIFO_WR_OFFSET_CNT_REG_b; }; union { - __IOM uint32_t SIO_FIFO_RD_OFFSET_START_REG; /*!< (@ 0x000002C0) Points to start slice + __IOM unsigned int SIO_FIFO_RD_OFFSET_START_REG; /*!< (@ 0x000002C0) Points to start slice number forming the FIFO */ struct { - __IOM uint32_t SIO_START_SLICE_NUMBER : 32; /*!< [31..0] Points to start slice number + __IOM unsigned int SIO_START_SLICE_NUMBER : 32; /*!< [31..0] Points to start slice number forming the FIFO */ } SIO_FIFO_RD_OFFSET_START_REG_b; }; union { - __IOM uint32_t SIO_FIFO_RD_OFFSET_END_REG; /*!< (@ 0x000002C4) Points to last slice + __IOM unsigned int SIO_FIFO_RD_OFFSET_END_REG; /*!< (@ 0x000002C4) Points to last slice number forming the FIFO */ struct { - __IOM uint32_t SIO_END_SLICE_NUMBER : 32; /*!< [31..0] Points to last slice number + __IOM unsigned int SIO_END_SLICE_NUMBER : 32; /*!< [31..0] Points to last slice number forming the FIFO */ } SIO_FIFO_RD_OFFSET_END_REG_b; }; union { - __IOM uint32_t SIO_FIFO_RD_OFFSET_CNT_REG; /*!< (@ 0x000002C8) Points to start current + __IOM unsigned int SIO_FIFO_RD_OFFSET_CNT_REG; /*!< (@ 0x000002C8) Points to start current number forming the FIFO */ struct { - __IOM uint32_t SIO_CURRENT_SLICE_NUMBER : 32; /*!< [31..0] Next FIFO operation will + __IOM unsigned int SIO_CURRENT_SLICE_NUMBER : 32; /*!< [31..0] Next FIFO operation will happen to buffer in the slice pointed by this register This register has to be set to zero before starting fresh @@ -5514,159 +5514,159 @@ typedef struct { /*!< (@ 0x47000000) SIO Structure */ typedef struct { /*!< (@ 0x12000000) QSPI Structure */ union { - __IOM uint32_t QSPI_CLK_CONFIG; /*!< (@ 0x00000000) QSPI Clock Configuration + __IOM unsigned int QSPI_CLK_CONFIG; /*!< (@ 0x00000000) QSPI Clock Configuration Register */ struct { - __IOM uint32_t QSPI_AUTO_CSN_HIGH_CNT : 5; /*!< [4..0] Minimum SOC clock cycles, + __IOM unsigned int QSPI_AUTO_CSN_HIGH_CNT : 5; /*!< [4..0] Minimum SOC clock cycles, during which QSPI auto csn should be high between consecutive CSN assertions */ - __IOM uint32_t QSPI_CLK_SYNC : 1; /*!< [5..5] If the clock frequency to + __IOM unsigned int QSPI_CLK_SYNC : 1; /*!< [5..5] If the clock frequency to FLASH(spi_clk) and QSPI(hclk) controller is same, this bit can be set to one to by-pass the syncros results in time consumption */ - __IOM uint32_t RESERVED1 : 2; /*!< [7..6] reserved1 */ - __IOM uint32_t QSPI_CLK_EN : 1; /*!< [8..8] QSPI clock enable */ - __IOM uint32_t RESERVED2 : 3; /*!< [11..9] reserved2 */ - __IOM uint32_t SPI_CLK_DELAY_VAL : 6; /*!< [17..12] Delay value programmed to RX QSPI + __IOM unsigned int RESERVED1 : 2; /*!< [7..6] reserved1 */ + __IOM unsigned int QSPI_CLK_EN : 1; /*!< [8..8] QSPI clock enable */ + __IOM unsigned int RESERVED2 : 3; /*!< [11..9] reserved2 */ + __IOM unsigned int SPI_CLK_DELAY_VAL : 6; /*!< [17..12] Delay value programmed to RX QSPI DLL on read side. This delay is used to delay the pad clock/DQS according to the requirement */ - __IOM uint32_t OCTA_MODE_ENABLE_WITH_DQS : 1; /*!< [18..18] Enables SPI octa mode + __IOM unsigned int OCTA_MODE_ENABLE_WITH_DQS : 1; /*!< [18..18] Enables SPI octa mode along with DQS in DDR mode */ - __IOM uint32_t QSPI_DLL_ENABLE : 1; /*!< [19..19] Enable for RX QSPI DLL in read + __IOM unsigned int QSPI_DLL_ENABLE : 1; /*!< [19..19] Enable for RX QSPI DLL in read mode.This is used in M4SS QSPI DDR pads to delay the pad clock DQS input */ - __IOM uint32_t DDR_CLK_POLARITY_FROM_REG : 1; /*!< [20..20] Used this bit to sample + __IOM unsigned int DDR_CLK_POLARITY_FROM_REG : 1; /*!< [20..20] Used this bit to sample the data at posedge negedge after interface FFs with internal qspi clock 0-Sample at negedge 1-Sample at posedge */ - __IOM uint32_t QSPI_DLL_ENABLE_TX : 1; /*!< [21..21] Enable for TX QSPI DLL in write + __IOM unsigned int QSPI_DLL_ENABLE_TX : 1; /*!< [21..21] Enable for TX QSPI DLL in write path. This is used in M4SS QSPI DDR pads to delay the qspi clock output. 0–DLL is disabled bypassed 1–DLL is enabled */ - __IOM uint32_t SPI_CLK_DELAY_VAL_TX : 6; /*!< [27..22] Delay value programmed to TX + __IOM unsigned int SPI_CLK_DELAY_VAL_TX : 6; /*!< [27..22] Delay value programmed to TX QSPI DLL in write path. This delay is used to delay the qspi clock output according to the requirement */ - __IOM uint32_t QSPI_RX_DQS_DLL_CALIB : 1; /*!< [28..28] Delay value programmed to TX + __IOM unsigned int QSPI_RX_DQS_DLL_CALIB : 1; /*!< [28..28] Delay value programmed to TX QSPI DLL in write path. This delay is used to delay the qspi clock output according to the requirement */ - __IOM uint32_t RESERVED3 : 3; /*!< [31..29] reserved3 */ + __IOM unsigned int RESERVED3 : 3; /*!< [31..29] reserved3 */ } QSPI_CLK_CONFIG_b; }; union { - __IOM uint32_t QSPI_BUS_MODE; /*!< (@ 0x00000004) QSPI Bus Mode Register */ + __IOM unsigned int QSPI_BUS_MODE; /*!< (@ 0x00000004) QSPI Bus Mode Register */ struct { - __IOM uint32_t QSPI_9116_FEATURE_EN : 1; /*!< [0..0] 9115 specific features are + __IOM unsigned int QSPI_9116_FEATURE_EN : 1; /*!< [0..0] 9115 specific features are enabled with this enable */ - __IOM uint32_t QSPI_MAN_MODE_CONF_CSN0 : 2; /*!< [2..1] Configures the QSPI flash for + __IOM unsigned int QSPI_MAN_MODE_CONF_CSN0 : 2; /*!< [2..1] Configures the QSPI flash for Single/Dual/Quad mode operation in manual mode */ - __IOM uint32_t AUTO_MODE_RESET : 1; /*!< [3..3] QSPI Auto controller reset. This is + __IOM unsigned int AUTO_MODE_RESET : 1; /*!< [3..3] QSPI Auto controller reset. This is not a Self clearing bit */ - __IOM uint32_t QSPI_PREFETCH_EN : 1; /*!< [4..4] Pre-fetch of data from the model + __IOM unsigned int QSPI_PREFETCH_EN : 1; /*!< [4..4] Pre-fetch of data from the model which is connected to QSPI, automatically with out reading on AHB and is supplied to AHB, when address is matched with AHB read transaction address */ - __IOM uint32_t QSPI_WRAP_EN : 1; /*!< [5..5] Model wrap is considered with this bit + __IOM unsigned int QSPI_WRAP_EN : 1; /*!< [5..5] Model wrap is considered with this bit and uses wrap instruction to read from FLASH */ - __IOM uint32_t QSPI_AUTO_MODE_FRM_REG : 1; /*!< [6..6] QSPI Mode of Operation */ - __IOM uint32_t PROGRAMMABLE_AUTO_CSN_BASE_ADDR_EN : 1; /*!< [7..7] Programmable auto + __IOM unsigned int QSPI_AUTO_MODE_FRM_REG : 1; /*!< [6..6] QSPI Mode of Operation */ + __IOM unsigned int PROGRAMMABLE_AUTO_CSN_BASE_ADDR_EN : 1; /*!< [7..7] Programmable auto csn mode enable */ - __IOM uint32_t QSPI_D2_OEN_CSN0 : 1; /*!< [8..8] Direction Control for SPI_IO2 in + __IOM unsigned int QSPI_D2_OEN_CSN0 : 1; /*!< [8..8] Direction Control for SPI_IO2 in case of dual/single mode for chip select0 csn0. It is used both in Auto and Manual Mode */ - __IOM uint32_t QSPI_D3_OEN_CSN0 : 1; /*!< [9..9] Direction Control for SPI_IO3 in + __IOM unsigned int QSPI_D3_OEN_CSN0 : 1; /*!< [9..9] Direction Control for SPI_IO3 in case of dual/single mode for chip select0 csn0. It is used both in Auto and Manual Mode. */ - __IOM uint32_t QSPI_D2_DATA_CSN0 : 1; /*!< [10..10] Value of SPI_IO2 in case of + __IOM unsigned int QSPI_D2_DATA_CSN0 : 1; /*!< [10..10] Value of SPI_IO2 in case of dual/single mode for chip select0 csn0. It is used both in Auto and Manual Mode. */ - __IOM uint32_t QSPI_D3_DATA_CSN0 : 1; /*!< [11..11] Value of SPI_IO3 in case of + __IOM unsigned int QSPI_D3_DATA_CSN0 : 1; /*!< [11..11] Value of SPI_IO3 in case of dual/single mode for chip select0 csn0. It is used both in Auto and Manual Mode */ - __IOM uint32_t QSPI_D2_OEN_CSN1 : 1; /*!< [12..12] Direction Control for + __IOM unsigned int QSPI_D2_OEN_CSN1 : 1; /*!< [12..12] Direction Control for SPI_IO2 in case of dual/single mode for chip select1 csn1 */ - __IOM uint32_t QSPI_D3_OEN_CSN1 : 1; /*!< [13..13] Direction Control for + __IOM unsigned int QSPI_D3_OEN_CSN1 : 1; /*!< [13..13] Direction Control for SPI_IO3 in case of dual/single mode for chip select1 csn1 */ - __IOM uint32_t QSPI_D2_DATA_CSN1 : 1; /*!< [14..14] Direction Control for + __IOM unsigned int QSPI_D2_DATA_CSN1 : 1; /*!< [14..14] Direction Control for SPI_IO3 in case of dual/single mode for chip select1 csn1 */ - __IOM uint32_t QSPI_D3_DATA_CSN1 : 1; /*!< [15..15] Value of SPI_IO3 in case of + __IOM unsigned int QSPI_D3_DATA_CSN1 : 1; /*!< [15..15] Value of SPI_IO3 in case of dual/single mode for chip select1 csn1 */ - __IOM uint32_t QSPI_DATA_SAMPLE_EDGE : 1; /*!< [16..16] Samples MISO data + __IOM unsigned int QSPI_DATA_SAMPLE_EDGE : 1; /*!< [16..16] Samples MISO data on clock edges */ - __IOM uint32_t QSPI_CLK_MODE_CSN0 : 1; /*!< [17..17] QSPI Clock Mode */ - __IOM uint32_t QSPI_CLK_MODE_CSN1 : 1; /*!< [18..18] QSPI Clock Mode */ - __IOM uint32_t QSPI_CLK_MODE_CSN2 : 1; /*!< [19..19] QSPI Clock Mode */ - __IOM uint32_t QSPI_CLK_MODE_CSN3 : 1; /*!< [20..20] QSPI Clock Mode */ - __IOM uint32_t FLASH_AW_FIFO_LS_EN : 1; /*!< [21..21] Qspi flash auto write fifo + __IOM unsigned int QSPI_CLK_MODE_CSN0 : 1; /*!< [17..17] QSPI Clock Mode */ + __IOM unsigned int QSPI_CLK_MODE_CSN1 : 1; /*!< [18..18] QSPI Clock Mode */ + __IOM unsigned int QSPI_CLK_MODE_CSN2 : 1; /*!< [19..19] QSPI Clock Mode */ + __IOM unsigned int QSPI_CLK_MODE_CSN3 : 1; /*!< [20..20] QSPI Clock Mode */ + __IOM unsigned int FLASH_AW_FIFO_LS_EN : 1; /*!< [21..21] Qspi flash auto write fifo light sleep enable */ - __IOM uint32_t FLASH_SEC_AES_LS_EN : 1; /*!< [22..22] Qspi flash auto write fifo + __IOM unsigned int FLASH_SEC_AES_LS_EN : 1; /*!< [22..22] Qspi flash auto write fifo light sleep enable */ - __IOM uint32_t RESERVED1 : 1; /*!< [23..23] reserved1 */ - __IOM uint32_t QSPI_D2_OEN_CSN2 : 1; /*!< [24..24] Direction Control for SPI_IO2 in + __IOM unsigned int RESERVED1 : 1; /*!< [23..23] reserved1 */ + __IOM unsigned int QSPI_D2_OEN_CSN2 : 1; /*!< [24..24] Direction Control for SPI_IO2 in case of dual/single mode for chip select2 csn2 */ - __IOM uint32_t QSPI_D3_OEN_CSN2 : 1; /*!< [25..25] Direction Control for SPI_IO3 in + __IOM unsigned int QSPI_D3_OEN_CSN2 : 1; /*!< [25..25] Direction Control for SPI_IO3 in case of dual/single mode for chip select2 csn2 */ - __IOM uint32_t QSPI_D2_DATA_CSN2 : 1; /*!< [26..26] Value of SPI_IO2 in case of + __IOM unsigned int QSPI_D2_DATA_CSN2 : 1; /*!< [26..26] Value of SPI_IO2 in case of dual/single mode for chip select2 csn2 */ - __IOM uint32_t QSPI_D3_DATA_CSN2 : 1; /*!< [27..27] Value of SPI_IO3 in case of + __IOM unsigned int QSPI_D3_DATA_CSN2 : 1; /*!< [27..27] Value of SPI_IO3 in case of dual/single mode for chip select2 csn2 */ - __IOM uint32_t QSPI_D2_OEN_CSN3 : 1; /*!< [28..28] Direction Control for SPI_IO2 in + __IOM unsigned int QSPI_D2_OEN_CSN3 : 1; /*!< [28..28] Direction Control for SPI_IO2 in case of dual/single mode for chip select3 csn3 */ - __IOM uint32_t QSPI_D3_OEN_CSN3 : 1; /*!< [29..29] Direction Control for SPI_IO3 in + __IOM unsigned int QSPI_D3_OEN_CSN3 : 1; /*!< [29..29] Direction Control for SPI_IO3 in case of dual/single mode for chip select3 csn3 */ - __IOM uint32_t QSPI_D2_DATA_CSN3 : 1; /*!< [30..30] Value of SPI_IO2 in case of + __IOM unsigned int QSPI_D2_DATA_CSN3 : 1; /*!< [30..30] Value of SPI_IO2 in case of dual/single mode for chip select3 csn3 */ - __IOM uint32_t QSPI_D3_DATA_CSN3 : 1; /*!< [31..31] Value of SPI_IO3 in case of + __IOM unsigned int QSPI_D3_DATA_CSN3 : 1; /*!< [31..31] Value of SPI_IO3 in case of dual/single mode for chip select3 csn3 */ } QSPI_BUS_MODE_b; }; union { - __IOM uint32_t QSPI_AUTO_CONFIG_1; /*!< (@ 0x00000008) QSPI Auto Controller + __IOM unsigned int QSPI_AUTO_CONFIG_1; /*!< (@ 0x00000008) QSPI Auto Controller Configuration 1 Register */ struct { - __IOM uint32_t QSPI_EXT_BYTE_MODE_CSN0 : 2; /*!< [1..0] Mode of operation of QSPI in + __IOM unsigned int QSPI_EXT_BYTE_MODE_CSN0 : 2; /*!< [1..0] Mode of operation of QSPI in the extra byte phase */ - __IOM uint32_t QSPI_DUMMY_MODE_CSN0 : 2; /*!< [3..2] Mode of operation of + __IOM unsigned int QSPI_DUMMY_MODE_CSN0 : 2; /*!< [3..2] Mode of operation of QSPI in instruction phase */ - __IOM uint32_t QSPI_ADDR_MODE_CSN0 : 2; /*!< [5..4] Mode of operation of + __IOM unsigned int QSPI_ADDR_MODE_CSN0 : 2; /*!< [5..4] Mode of operation of QSPI in instruction phase */ - __IOM uint32_t QSPI_CMD_MODE_CSN0 : 2; /*!< [7..6] Mode of operation of + __IOM unsigned int QSPI_CMD_MODE_CSN0 : 2; /*!< [7..6] Mode of operation of QSPI in instruction phase */ - __IOM uint32_t QSPI_DATA_MODE_CSN0 : 2; /*!< [9..8] Mode of operation of + __IOM unsigned int QSPI_DATA_MODE_CSN0 : 2; /*!< [9..8] Mode of operation of QSPI in DATA phase */ - __IOM uint32_t QSPI_EXTRA_BYTE_CSN0 : 8; /*!< [17..10] Value of the extra byte to be + __IOM unsigned int QSPI_EXTRA_BYTE_CSN0 : 8; /*!< [17..10] Value of the extra byte to be transmitted, if the extra byte mode is enabled */ - __IOM uint32_t QSPI_EXTRA_BYTE_EN_CSN0 : 2; /*!< [19..18] Value of the extra byte to + __IOM unsigned int QSPI_EXTRA_BYTE_EN_CSN0 : 2; /*!< [19..18] Value of the extra byte to be transmitted, if the extra byte mode is enabled */ - __IOM uint32_t QSPI_WRAP_SIZE : 2; /*!< [21..20] Qspi auto wrap size */ - __IOM uint32_t RESERVED1 : 1; /*!< [22..22] reserved1 */ - __IOM uint32_t QSPI_PG_JUMP_CSN0 : 1; /*!< [23..23] NONE */ - __IOM uint32_t QSPI_DUMMY_BYTES_INCR_CSN0 : 4; /*!< [27..24] Specifies the number of + __IOM unsigned int QSPI_WRAP_SIZE : 2; /*!< [21..20] Qspi auto wrap size */ + __IOM unsigned int RESERVED1 : 1; /*!< [22..22] reserved1 */ + __IOM unsigned int QSPI_PG_JUMP_CSN0 : 1; /*!< [23..23] NONE */ + __IOM unsigned int QSPI_DUMMY_BYTES_INCR_CSN0 : 4; /*!< [27..24] Specifies the number of dummy bytes 0 to 7 for the selected SPI mode */ - __IOM uint32_t QSPI_DUMMY_BYTES_WRAP_CSN0 : 4; /*!< [31..28] Specifies the number of + __IOM unsigned int QSPI_DUMMY_BYTES_WRAP_CSN0 : 4; /*!< [31..28] Specifies the number of dummy bytes 0 to 7 for the selected SPI mode in case of wrap instruction */ @@ -5674,378 +5674,378 @@ typedef struct { /*!< (@ 0x12000000) QSPI Structure */ }; union { - __IOM uint32_t QSPI_AUTO_CONFIG_2; /*!< (@ 0x0000000C) QSPI Auto Controller + __IOM unsigned int QSPI_AUTO_CONFIG_2; /*!< (@ 0x0000000C) QSPI Auto Controller Configuration 2 Register */ struct { - __IOM uint32_t QSPI_RD_DATA_SWAP_AUTO_CSN0 : 1; /*!< [0..0] NONE */ - __IOM uint32_t QSPI_ADR_SIZE_16_BIT_AUTO_MODE_CSN0 : 1; /*!< [1..1] NONE */ - __IOM uint32_t QSPI_CONTI_RD_EN_CSN0 : 1; /*!< [2..2] NONE */ - __IOM uint32_t DUMMY_BYTES_WR_RD_CSN0 : 1; /*!< [3..3] Dummy bytes to the model to be + __IOM unsigned int QSPI_RD_DATA_SWAP_AUTO_CSN0 : 1; /*!< [0..0] NONE */ + __IOM unsigned int QSPI_ADR_SIZE_16_BIT_AUTO_MODE_CSN0 : 1; /*!< [1..1] NONE */ + __IOM unsigned int QSPI_CONTI_RD_EN_CSN0 : 1; /*!< [2..2] NONE */ + __IOM unsigned int DUMMY_BYTES_WR_RD_CSN0 : 1; /*!< [3..3] Dummy bytes to the model to be read or to be write */ - __IOM uint32_t QSPI_DUMMY_BYTES_JMP_CSN : 4; /*!< [7..4] Dummy cycles to be selected + __IOM unsigned int QSPI_DUMMY_BYTES_JMP_CSN : 4; /*!< [7..4] Dummy cycles to be selected in case of JUMP */ - __IOM uint32_t QSPI_RD_INST_CSN0 : 8; /*!< [15..8] Read instruction to be used for + __IOM unsigned int QSPI_RD_INST_CSN0 : 8; /*!< [15..8] Read instruction to be used for the selected SPI modes and when wrap */ - __IOM uint32_t QSPI_RD_WRAP_INT_CSN0 : 8; /*!< [23..16] Read instruction + __IOM unsigned int QSPI_RD_WRAP_INT_CSN0 : 8; /*!< [23..16] Read instruction to be used, when wrap mode is supported by QSPI flash */ - __IOM uint32_t QSPI_PG_JUMP_INST_CSN0 : 8; /*!< [31..24] Read instruction to be used, + __IOM unsigned int QSPI_PG_JUMP_INST_CSN0 : 8; /*!< [31..24] Read instruction to be used, when Page jump is to be used */ } QSPI_AUTO_CONFIG_2_b; }; union { - __IOM uint32_t QSPI_MANUAL_CONFIG1; /*!< (@ 0x00000010) QSPI Manual + __IOM unsigned int QSPI_MANUAL_CONFIG1; /*!< (@ 0x00000010) QSPI Manual Configuration 1 Register */ struct { - __IOM uint32_t QSPI_MANUAL_CSN : 1; /*!< [0..0] SPI CS in manual mode */ - __IOM uint32_t QSPI_MANUAL_WR : 1; /*!< [1..1] Write enable for manual + __IOM unsigned int QSPI_MANUAL_CSN : 1; /*!< [0..0] SPI CS in manual mode */ + __IOM unsigned int QSPI_MANUAL_WR : 1; /*!< [1..1] Write enable for manual mode when CS is low */ - __IOM uint32_t QSPI_MANUAL_RD : 1; /*!< [2..2] Read enable for manual mode + __IOM unsigned int QSPI_MANUAL_RD : 1; /*!< [2..2] Read enable for manual mode when CS is low */ - __IOM uint32_t QSPI_MANUAL_RD_CNT : 10; /*!< [12..3] Indicates total number of bytes + __IOM unsigned int QSPI_MANUAL_RD_CNT : 10; /*!< [12..3] Indicates total number of bytes to be read along with 31:27 bits of this register. Maximum length supported is 32k bytes */ - __IOM uint32_t QSPI_MANUAL_CSN_SELECT : 2; /*!< [14..13] Indicates which + __IOM unsigned int QSPI_MANUAL_CSN_SELECT : 2; /*!< [14..13] Indicates which CSn is valid */ - __IOM uint32_t RESERVED1 : 4; /*!< [18..15] reserved1 */ - __IOM uint32_t QSPI_MANUAL_SIZE_FRM_REG : 2; /*!< [20..19] Manual reads and manual + __IOM unsigned int RESERVED1 : 4; /*!< [18..15] reserved1 */ + __IOM unsigned int QSPI_MANUAL_SIZE_FRM_REG : 2; /*!< [20..19] Manual reads and manual writes follow this size */ - __IOM uint32_t TAKE_QSPI_MANUAL_WR_SIZE_FRM_REG : 1; /*!< [21..21] NONE */ - __IOM uint32_t QSPI_FULL_DUPLEX_EN : 1; /*!< [22..22] Full duplex mode enable. */ - __IOM uint32_t RESERVED2 : 2; /*!< [24..23] reserved2 */ - __IOM uint32_t HW_CTRLD_QSPI_MODE_CTRL : 1; /*!< [25..25] Hardware controlled qspi + __IOM unsigned int TAKE_QSPI_MANUAL_WR_SIZE_FRM_REG : 1; /*!< [21..21] NONE */ + __IOM unsigned int QSPI_FULL_DUPLEX_EN : 1; /*!< [22..22] Full duplex mode enable. */ + __IOM unsigned int RESERVED2 : 2; /*!< [24..23] reserved2 */ + __IOM unsigned int HW_CTRLD_QSPI_MODE_CTRL : 1; /*!< [25..25] Hardware controlled qspi mode in between AUTO and manual */ - __IOM uint32_t QSPI_MANUAL_QSPI_MODE : 1; /*!< [26..26] Internally the priority is + __IOM unsigned int QSPI_MANUAL_QSPI_MODE : 1; /*!< [26..26] Internally the priority is given to manual mode */ - __IOM uint32_t QSPI_MANUAL_RD_CNT1 : 5; /*!< [31..27] Indicates total + __IOM unsigned int QSPI_MANUAL_RD_CNT1 : 5; /*!< [31..27] Indicates total number of bytes or bits */ } QSPI_MANUAL_CONFIG1_b; }; union { - __IOM uint32_t QSPI_MANUAL_CONFIG2; /*!< (@ 0x00000014) QSPI Manual + __IOM unsigned int QSPI_MANUAL_CONFIG2; /*!< (@ 0x00000014) QSPI Manual Configuration 2 Register */ struct { - __IOM uint32_t QSPI_WR_DATA_SWAP_MNL_CSN0 : 1; /*!< [0..0] Swap the write data inside + __IOM unsigned int QSPI_WR_DATA_SWAP_MNL_CSN0 : 1; /*!< [0..0] Swap the write data inside the QSPI controller it-self */ - __IOM uint32_t QSPI_WR_DATA_SWAP_MNL_CSN1 : 1; /*!< [1..1] Swap the write data inside + __IOM unsigned int QSPI_WR_DATA_SWAP_MNL_CSN1 : 1; /*!< [1..1] Swap the write data inside the QSPI controller it-self. */ - __IOM uint32_t QSPI_WR_DATA_SWAP_MNL_CSN2 : 1; /*!< [2..2] Swap the write data inside + __IOM unsigned int QSPI_WR_DATA_SWAP_MNL_CSN2 : 1; /*!< [2..2] Swap the write data inside the QSPI controller itself. */ - __IOM uint32_t QSPI_WR_DATA_SWAP_MNL_CSN3 : 1; /*!< [3..3] Swap the write data inside + __IOM unsigned int QSPI_WR_DATA_SWAP_MNL_CSN3 : 1; /*!< [3..3] Swap the write data inside the QSPI controller itself. */ - __IOM uint32_t QSPI_RD_DATA_SWAP_MNL_CSN0 : 1; /*!< [4..4] Swap the read data inside + __IOM unsigned int QSPI_RD_DATA_SWAP_MNL_CSN0 : 1; /*!< [4..4] Swap the read data inside the QSPIcontroller it self. */ - __IOM uint32_t QSPI_RD_DATA_SWAP_MNL_CSN1 : 1; /*!< [5..5] Swap the read data inside + __IOM unsigned int QSPI_RD_DATA_SWAP_MNL_CSN1 : 1; /*!< [5..5] Swap the read data inside the QSPIcontroller itself. */ - __IOM uint32_t QSPI_RD_DATA_SWAP_MNL_CSN2 : 1; /*!< [6..6] Swap the read data inside + __IOM unsigned int QSPI_RD_DATA_SWAP_MNL_CSN2 : 1; /*!< [6..6] Swap the read data inside the QSPIcontroller it-self */ - __IOM uint32_t QSPI_RD_DATA_SWAP_MNL_CSN3 : 1; /*!< [7..7] Swap the read data inside + __IOM unsigned int QSPI_RD_DATA_SWAP_MNL_CSN3 : 1; /*!< [7..7] Swap the read data inside the QSPIcontroller itself */ - __IOM uint32_t QSPI_MAN_MODE_CONF_CSN1 : 2; /*!< [9..8] Configures the QSPI flash for + __IOM unsigned int QSPI_MAN_MODE_CONF_CSN1 : 2; /*!< [9..8] Configures the QSPI flash for Single/Dual/Quad mode operation in manual mode for chip select1 csn1 */ - __IOM uint32_t QSPI_MAN_MODE_CONF_CSN2 : 2; /*!< [11..10] Configures the QSPI flash + __IOM unsigned int QSPI_MAN_MODE_CONF_CSN2 : 2; /*!< [11..10] Configures the QSPI flash for Single or Dual or Quad mode operation in manual mode for chip select2 csn2 */ - __IOM uint32_t QSPI_MAN_MODE_CONF_CSN3 : 2; /*!< [13..12] Configures the QSPI flash + __IOM unsigned int QSPI_MAN_MODE_CONF_CSN3 : 2; /*!< [13..12] Configures the QSPI flash for Single or Dual or Quad mode operation in manual mode for chip select3 csn3 */ - __IOM uint32_t LOOP_BACK_EN : 1; /*!< [14..14] Internal loop back test mode. */ - __IOM uint32_t QSPI_MANUAL_DDR_PHASE : 1; /*!< [15..15] DDR operations can be + __IOM unsigned int LOOP_BACK_EN : 1; /*!< [14..14] Internal loop back test mode. */ + __IOM unsigned int QSPI_MANUAL_DDR_PHASE : 1; /*!< [15..15] DDR operations can be performed even in manual mode */ - __IOM uint32_t QSPI_DDR_CLK_EN : 1; /*!< [16..16] DDR operations can be + __IOM unsigned int QSPI_DDR_CLK_EN : 1; /*!< [16..16] DDR operations can be performed even in manual mode */ - __IOM uint32_t RESERVED1 : 1; /*!< [17..17] reserved1 */ - __IOM uint32_t QSPI_RD_DATA_SWAP_WORD_LVL_MNL_CSN0 : 1; /*!< [18..18] Set this bit + __IOM unsigned int RESERVED1 : 1; /*!< [17..17] reserved1 */ + __IOM unsigned int QSPI_RD_DATA_SWAP_WORD_LVL_MNL_CSN0 : 1; /*!< [18..18] Set this bit for read data byte swapping within the word. It is valid only for octa ddr mode. It is valid for csn0. */ - __IOM uint32_t QSPI_RD_DATA_SWAP_WORD_LVL_MNL_CSN1 : 1; /*!< [19..19] Set this bit + __IOM unsigned int QSPI_RD_DATA_SWAP_WORD_LVL_MNL_CSN1 : 1; /*!< [19..19] Set this bit for read data byte swapping within the word. It is valid only for octa ddr mode. It is valid for csn1. */ - __IOM uint32_t QSPI_RD_DATA_SWAP_WORD_LVL_MNL_CSN2 : 1; /*!< [20..20] Set this bit + __IOM unsigned int QSPI_RD_DATA_SWAP_WORD_LVL_MNL_CSN2 : 1; /*!< [20..20] Set this bit for read data byte swapping within the word. It is valid only for octa ddr mode. It is valid for csn2. */ - __IOM uint32_t QSPI_WR_DATA_SWAP_WORD_LVL_MNL_CSN0 : 1; /*!< [21..21] Set this bit + __IOM unsigned int QSPI_WR_DATA_SWAP_WORD_LVL_MNL_CSN0 : 1; /*!< [21..21] Set this bit for write data byte swapping within the word. It is valid only for octa ddr mode. It is valid for csn0. */ - __IOM uint32_t QSPI_WR_DATA_SWAP_WORD_LVL_MNL_CSN1 : 1; /*!< [22..22] Set this bit + __IOM unsigned int QSPI_WR_DATA_SWAP_WORD_LVL_MNL_CSN1 : 1; /*!< [22..22] Set this bit for write data byte swapping within the word. It is valid only for octa ddr mode. It is valid for csn1. */ - __IOM uint32_t QSPI_WR_DATA_SWAP_WORD_LVL_MNL_CSN2 : 1; /*!< [23..23] Set this bit + __IOM unsigned int QSPI_WR_DATA_SWAP_WORD_LVL_MNL_CSN2 : 1; /*!< [23..23] Set this bit for write data byte swapping within the word. It is valid only for octa ddr mode. It is valid for csn2. */ - __IOM uint32_t QSPI_WR_DATA_SWAP_WORD_LVL_MNL_CSN3 : 1; /*!< [24..24] Set this bit + __IOM unsigned int QSPI_WR_DATA_SWAP_WORD_LVL_MNL_CSN3 : 1; /*!< [24..24] Set this bit for write data byte swapping within the word. It is valid only for octa ddr mode. It is valid for csn3. */ - __IOM uint32_t QSPI_MANUAL_DUMMY_BYTE_OR_BIT_MODE : 1; /*!< [25..25] Indicates + __IOM unsigned int QSPI_MANUAL_DUMMY_BYTE_OR_BIT_MODE : 1; /*!< [25..25] Indicates qspi_manual_rd_cnt values are dummy bytes or bits in manual mode. */ - __IOM uint32_t RESERVED2 : 6; /*!< [31..26] reserved2 */ + __IOM unsigned int RESERVED2 : 6; /*!< [31..26] reserved2 */ } QSPI_MANUAL_CONFIG2_b; }; - __IM uint32_t RESERVED; + __IM unsigned int RESERVED; union { - __IOM uint32_t QSPI_FIFO_THRLD; /*!< (@ 0x0000001C) QSPI FIFO Threshold Register */ + __IOM unsigned int QSPI_FIFO_THRLD; /*!< (@ 0x0000001C) QSPI FIFO Threshold Register */ struct { - __IOM uint32_t FIFO_AEMPTY_THRLD : 4; /*!< [3..0] FIFO almost empty threshold */ - __IOM uint32_t FIFO_AFULL_THRLD : 4; /*!< [7..4] FIFO almost full threshold */ - __IOM uint32_t WFIFO_RESET : 1; /*!< [8..8] Write fifo reset */ - __IOM uint32_t RFIFO_RESET : 1; /*!< [9..9] Read fifo reset */ - __IOM uint32_t RESERVED1 : 22; /*!< [31..10] reserved1 */ + __IOM unsigned int FIFO_AEMPTY_THRLD : 4; /*!< [3..0] FIFO almost empty threshold */ + __IOM unsigned int FIFO_AFULL_THRLD : 4; /*!< [7..4] FIFO almost full threshold */ + __IOM unsigned int WFIFO_RESET : 1; /*!< [8..8] Write fifo reset */ + __IOM unsigned int RFIFO_RESET : 1; /*!< [9..9] Read fifo reset */ + __IOM unsigned int RESERVED1 : 22; /*!< [31..10] reserved1 */ } QSPI_FIFO_THRLD_b; }; union { - __IM uint32_t QSPI_MANUAL_STATUS; /*!< (@ 0x00000020) QSPI Manual Status Register */ + __IM unsigned int QSPI_MANUAL_STATUS; /*!< (@ 0x00000020) QSPI Manual Status Register */ struct { - __IM uint32_t QSPI_BUSY : 1; /*!< [0..0] State of Manual mode. */ - __IM uint32_t FIFO_FULL_WFIFO_S : 1; /*!< [1..1] Status indication for + __IM unsigned int QSPI_BUSY : 1; /*!< [0..0] State of Manual mode. */ + __IM unsigned int FIFO_FULL_WFIFO_S : 1; /*!< [1..1] Status indication for Wfifo in manual mode */ - __IM uint32_t FIFO_AFULL_WFIFO_S : 1; /*!< [2..2] Status indication for + __IM unsigned int FIFO_AFULL_WFIFO_S : 1; /*!< [2..2] Status indication for Wfifo in manual mode */ - __IM uint32_t FIFO_EMPTY_WFIFO : 1; /*!< [3..3] Status indication for + __IM unsigned int FIFO_EMPTY_WFIFO : 1; /*!< [3..3] Status indication for Wfifo in manual mode */ - __IM uint32_t FIFO_AEMPTY_WFIFO : 1; /*!< [4..4] Status indication for + __IM unsigned int FIFO_AEMPTY_WFIFO : 1; /*!< [4..4] Status indication for Wfifo in manual mode */ - __IM uint32_t FIFO_FULL_RFIFO : 1; /*!< [5..5] Status indication for Rfifo + __IM unsigned int FIFO_FULL_RFIFO : 1; /*!< [5..5] Status indication for Rfifo in manual mode */ - __IM uint32_t FIFO_AFULL_RFIFO : 1; /*!< [6..6] Status indication for + __IM unsigned int FIFO_AFULL_RFIFO : 1; /*!< [6..6] Status indication for Rfifo in manual mode */ - __IM uint32_t FIFO_EMPTY_RFIFO_S : 1; /*!< [7..7] Status indication for + __IM unsigned int FIFO_EMPTY_RFIFO_S : 1; /*!< [7..7] Status indication for Rfifo in manual mode */ - __IM uint32_t FIFO_AEMPTY_RFIFO_S : 1; /*!< [8..8] Status indication for + __IM unsigned int FIFO_AEMPTY_RFIFO_S : 1; /*!< [8..8] Status indication for Rfifo in manual mode */ - __IM uint32_t GSPI_MANUAL_RD_CNT : 1; /*!< [9..9] This is a result of 10 + __IM unsigned int GSPI_MANUAL_RD_CNT : 1; /*!< [9..9] This is a result of 10 bits ORing counter */ - __IM uint32_t AUTO_MODE_FSM_IDLE_SCLK : 1; /*!< [10..10] Auto mode idle signal to + __IM unsigned int AUTO_MODE_FSM_IDLE_SCLK : 1; /*!< [10..10] Auto mode idle signal to track auto controller is busy or idle. */ - __IM uint32_t QSPI_AUTO_MODE : 1; /*!< [11..11] QSPI controller status. */ - __IM uint32_t QSPI_AUTO_MODE_FRM_REG_SCLK : 1; /*!< [12..12] QSPI auto mode status. + __IM unsigned int QSPI_AUTO_MODE : 1; /*!< [11..11] QSPI controller status. */ + __IM unsigned int QSPI_AUTO_MODE_FRM_REG_SCLK : 1; /*!< [12..12] QSPI auto mode status. Valid only when HW_CTRLD_QSPI_MODE_CTRL is zero. */ - __IM uint32_t HW_CTRLD_MODE_SCLK : 1; /*!< [13..13] QSPI mode status in + __IM unsigned int HW_CTRLD_MODE_SCLK : 1; /*!< [13..13] QSPI mode status in HW_CTRLD_MODE */ - __IM uint32_t HW_CTRLD_MODE_CTRL_SCLK : 1; /*!< [14..14] HW_CTRLD_MODE status */ - __IM uint32_t AW_CTRL_BUSY : 1; /*!< [15..15] Auto write busy indication. */ - __IM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + __IM unsigned int HW_CTRLD_MODE_CTRL_SCLK : 1; /*!< [14..14] HW_CTRLD_MODE status */ + __IM unsigned int AW_CTRL_BUSY : 1; /*!< [15..15] Auto write busy indication. */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ } QSPI_MANUAL_STATUS_b; }; union { - __IOM uint32_t QSPI_INTR_MASK; /*!< (@ 0x00000024) QSPI Interrupt Mask Register */ + __IOM unsigned int QSPI_INTR_MASK; /*!< (@ 0x00000024) QSPI Interrupt Mask Register */ struct { - __IOM uint32_t QSPI_INTR_MASK : 1; /*!< [0..0] Interrupt Status bit */ - __IOM uint32_t FIFO_AEMPTY_RFIFO_MASK : 1; /*!< [1..1] NONE */ - __IOM uint32_t FIFO_AFULL_RFIFO_MASK : 1; /*!< [2..2] NONE */ - __IOM uint32_t FIFO_AEMPTY_WFIFO_MASK : 1; /*!< [3..3] NONE */ - __IOM uint32_t FIFO_AFULL_WFIFO_MASK : 1; /*!< [4..4] NONE */ - __IOM uint32_t FIFO_FULL_WFIFO_MASK : 1; /*!< [5..5] NONE */ - __IOM uint32_t FIFO_EMPTY_RFIFO_MASK : 1; /*!< [6..6] NONE */ - __IOM uint32_t AHB_AUTO_WRITE_INTR_MASK : 1; /*!< [7..7] Rising interrupt for any + __IOM unsigned int QSPI_INTR_MASK : 1; /*!< [0..0] Interrupt Status bit */ + __IOM unsigned int FIFO_AEMPTY_RFIFO_MASK : 1; /*!< [1..1] NONE */ + __IOM unsigned int FIFO_AFULL_RFIFO_MASK : 1; /*!< [2..2] NONE */ + __IOM unsigned int FIFO_AEMPTY_WFIFO_MASK : 1; /*!< [3..3] NONE */ + __IOM unsigned int FIFO_AFULL_WFIFO_MASK : 1; /*!< [4..4] NONE */ + __IOM unsigned int FIFO_FULL_WFIFO_MASK : 1; /*!< [5..5] NONE */ + __IOM unsigned int FIFO_EMPTY_RFIFO_MASK : 1; /*!< [6..6] NONE */ + __IOM unsigned int AHB_AUTO_WRITE_INTR_MASK : 1; /*!< [7..7] Rising interrupt for any auto write operation on AHB bus. This bit is a mask for this interrupt */ - __IOM uint32_t QSPI_AUTO_BASE_ADDR_ERR_INTR_MASK : 1; /*!< [8..8] Rising interrupt + __IOM unsigned int QSPI_AUTO_BASE_ADDR_ERR_INTR_MASK : 1; /*!< [8..8] Rising interrupt when no csn is selected using programmable auto base address. This bit is a mask for this interrupt. */ - __IOM uint32_t M4QSPI_MANUAL_BLOCKED_INTR_MASK : 1; /*!< [9..9] Rising interrupt when + __IOM unsigned int M4QSPI_MANUAL_BLOCKED_INTR_MASK : 1; /*!< [9..9] Rising interrupt when M4 QSPI tries to do manual mode transactions in Common flash mode (3). This bit is a mask for this interrupt. */ - __IOM uint32_t M4_AUTO_READ_OUT_range_intr_mask : 1; /*!< [10..10] Rising interrupt + __IOM unsigned int M4_AUTO_READ_OUT_range_intr_mask : 1; /*!< [10..10] Rising interrupt when M4 QSPI tries to read TA locations in Common flash mode (3). This bit is a mask for this interrupt. */ - __IOM uint32_t RESERVED1 : 21; /*!< [31..11] reserved1 */ + __IOM unsigned int RESERVED1 : 21; /*!< [31..11] reserved1 */ } QSPI_INTR_MASK_b; }; union { - __IOM uint32_t QSPI_INTR_UNMASK; /*!< (@ 0x00000028) QSPI Interrupt Unmask + __IOM unsigned int QSPI_INTR_UNMASK; /*!< (@ 0x00000028) QSPI Interrupt Unmask Register */ struct { - __IOM uint32_t QSPI_INTR_UNMASK : 1; /*!< [0..0] Interrupt Status bit */ - __IOM uint32_t FIFO_AEMPTY_RFIFO_UN : 1; /*!< [1..1] NONE */ - __IOM uint32_t FIFO_AFULL_RFIFO_UNMASK : 1; /*!< [2..2] NONE */ - __IOM uint32_t FIFO_AEMPTY_WFIFO_UNMASK : 1; /*!< [3..3] NONE */ - __IOM uint32_t FIFO_AFULL_WFIFO_UNMASK : 1; /*!< [4..4] NONE */ - __IOM uint32_t FIFO_FULL_WFIFO_UNMASK : 1; /*!< [5..5] NONE */ - __IOM uint32_t FIFO_EMPTY_RFIFO_UNMASK : 1; /*!< [6..6] NONE */ - __IOM uint32_t AHB_AUTO_WRITE_INTR_UNMASK : 1; /*!< [7..7] Rising interrupt for any + __IOM unsigned int QSPI_INTR_UNMASK : 1; /*!< [0..0] Interrupt Status bit */ + __IOM unsigned int FIFO_AEMPTY_RFIFO_UN : 1; /*!< [1..1] NONE */ + __IOM unsigned int FIFO_AFULL_RFIFO_UNMASK : 1; /*!< [2..2] NONE */ + __IOM unsigned int FIFO_AEMPTY_WFIFO_UNMASK : 1; /*!< [3..3] NONE */ + __IOM unsigned int FIFO_AFULL_WFIFO_UNMASK : 1; /*!< [4..4] NONE */ + __IOM unsigned int FIFO_FULL_WFIFO_UNMASK : 1; /*!< [5..5] NONE */ + __IOM unsigned int FIFO_EMPTY_RFIFO_UNMASK : 1; /*!< [6..6] NONE */ + __IOM unsigned int AHB_AUTO_WRITE_INTR_UNMASK : 1; /*!< [7..7] Rising interrupt for any auto write operation on AHB bus. This bit is a unmask for this interrupt. */ - __IOM uint32_t QSPI_AUTO_BASE_ADDR_ERR_INTR_UNMASK : 1; /*!< [8..8] Rising interrupt + __IOM unsigned int QSPI_AUTO_BASE_ADDR_ERR_INTR_UNMASK : 1; /*!< [8..8] Rising interrupt when M4 QSPI tries to do manual mode transactions in Common flash mode (3). This bit is a unmask for this interrupt. */ - __IOM uint32_t M4QSPI_MANUAL_BLOCKED_INTR_UNMASK : 1; /*!< [9..9] Rising interrupt + __IOM unsigned int M4QSPI_MANUAL_BLOCKED_INTR_UNMASK : 1; /*!< [9..9] Rising interrupt when M4 QSPI tries to do manual mode transactions in Common flash mode (3). This bit is a unmask for this interrupt. */ - __IOM uint32_t M4_AUTO_READ_OUT_RANGE_INTR_UNMASK : 1; /*!< [10..10] Rising interrupt + __IOM unsigned int M4_AUTO_READ_OUT_RANGE_INTR_UNMASK : 1; /*!< [10..10] Rising interrupt when M4 QSPI tries to read TA locations in Common flash mode (3). This bit is a unmask for this interrupt. */ - __IOM uint32_t RESERVED1 : 21; /*!< [31..11] reserved1 */ + __IOM unsigned int RESERVED1 : 21; /*!< [31..11] reserved1 */ } QSPI_INTR_UNMASK_b; }; union { - __IM uint32_t QSPI_INTR_STS; /*!< (@ 0x0000002C) QSPI Interrupt Status Register */ + __IM unsigned int QSPI_INTR_STS; /*!< (@ 0x0000002C) QSPI Interrupt Status Register */ struct { - __IM uint32_t QSPI_INTR_LVL : 1; /*!< [0..0] Interrupt Status bit */ - __IM uint32_t FIFO_AEMPTY_RFIFO_LVL : 1; /*!< [1..1] NONE */ - __IM uint32_t FIFO_AFULL_RFIFO_LVL : 1; /*!< [2..2] NONE */ - __IM uint32_t FIFO_AEMPTY_WFIFO_LVL : 1; /*!< [3..3] NONE */ - __IM uint32_t FIFO_AFULL_WFIFO_LVL : 1; /*!< [4..4] NONE */ - __IM uint32_t FIFO_FULL_WFIFO_LVL : 1; /*!< [5..5] NONE */ - __IM uint32_t FIFO_EMPTY_RFIFO_LVL : 1; /*!< [6..6] NONE */ - __IM uint32_t AHB_AUTO_WRITE_INTR_LEV : 1; /*!< [7..7] rising interrupt for any auto + __IM unsigned int QSPI_INTR_LVL : 1; /*!< [0..0] Interrupt Status bit */ + __IM unsigned int FIFO_AEMPTY_RFIFO_LVL : 1; /*!< [1..1] NONE */ + __IM unsigned int FIFO_AFULL_RFIFO_LVL : 1; /*!< [2..2] NONE */ + __IM unsigned int FIFO_AEMPTY_WFIFO_LVL : 1; /*!< [3..3] NONE */ + __IM unsigned int FIFO_AFULL_WFIFO_LVL : 1; /*!< [4..4] NONE */ + __IM unsigned int FIFO_FULL_WFIFO_LVL : 1; /*!< [5..5] NONE */ + __IM unsigned int FIFO_EMPTY_RFIFO_LVL : 1; /*!< [6..6] NONE */ + __IM unsigned int AHB_AUTO_WRITE_INTR_LEV : 1; /*!< [7..7] rising interrupt for any auto write operation on AHB bus. */ - __IM uint32_t QSPI_AUTO_BASE_ADDR_ERR_INTR_LVL : 1; /*!< [8..8] Rising interrupt + __IM unsigned int QSPI_AUTO_BASE_ADDR_ERR_INTR_LVL : 1; /*!< [8..8] Rising interrupt when no csn is selected using programmable auto base address. */ - __IM uint32_t M4QSPI_MANUAL_BLOCKED_LVL : 1; /*!< [9..9] Rising interrupt when M4 + __IM unsigned int M4QSPI_MANUAL_BLOCKED_LVL : 1; /*!< [9..9] Rising interrupt when M4 QSPI tries to do manual mode transactions in Common flash mode (3). */ - __IM uint32_t M4_AUTO_READ_OUT_RANGE_LVL : 1; /*!< [10..10] Rising interrupt when M4 + __IM unsigned int M4_AUTO_READ_OUT_RANGE_LVL : 1; /*!< [10..10] Rising interrupt when M4 QSPI tries to read TA locations in Common flash mode (3). */ - __IM uint32_t RESERVED1 : 21; /*!< [31..11] reserved1 */ + __IM unsigned int RESERVED1 : 21; /*!< [31..11] reserved1 */ } QSPI_INTR_STS_b; }; union { - __IOM uint32_t QSPI_INTR_ACK; /*!< (@ 0x00000030) QSPI Interrupt Acknowledge + __IOM unsigned int QSPI_INTR_ACK; /*!< (@ 0x00000030) QSPI Interrupt Acknowledge Register */ struct { - __OM uint32_t QSPI_INTR_ACK : 1; /*!< [0..0] Interrupt Status bit */ - __OM uint32_t FIFO_AEMPTY_RFIFO_ACK : 1; /*!< [1..1] NONE */ - __OM uint32_t FIFO_AFULL_RFIFO_ACK : 1; /*!< [2..2] NONE */ - __OM uint32_t FIFO_AEMPTY_WFIFO_ACK : 1; /*!< [3..3] NONE */ - __OM uint32_t FIFO_AFULL_WFIFO_ACK : 1; /*!< [4..4] NONE */ - __OM uint32_t FIFO_FULL_WFIFO_ACK : 1; /*!< [5..5] NONE */ - __OM uint32_t FIFO_EMPTY_RFIFO_ACK : 1; /*!< [6..6] NONE */ - __OM uint32_t AHB_AUTO_WRITE_INTR_ACK : 1; /*!< [7..7] Rising interrupt for any auto + __OM unsigned int QSPI_INTR_ACK : 1; /*!< [0..0] Interrupt Status bit */ + __OM unsigned int FIFO_AEMPTY_RFIFO_ACK : 1; /*!< [1..1] NONE */ + __OM unsigned int FIFO_AFULL_RFIFO_ACK : 1; /*!< [2..2] NONE */ + __OM unsigned int FIFO_AEMPTY_WFIFO_ACK : 1; /*!< [3..3] NONE */ + __OM unsigned int FIFO_AFULL_WFIFO_ACK : 1; /*!< [4..4] NONE */ + __OM unsigned int FIFO_FULL_WFIFO_ACK : 1; /*!< [5..5] NONE */ + __OM unsigned int FIFO_EMPTY_RFIFO_ACK : 1; /*!< [6..6] NONE */ + __OM unsigned int AHB_AUTO_WRITE_INTR_ACK : 1; /*!< [7..7] Rising interrupt for any auto write operation on AHB bus. This bit is an ack for this interrupt. */ - __OM uint32_t QSPI_AUTO_BASE_ADDR_ERR_INTR_ACK : 1; /*!< [8..8] Rising interrupt + __OM unsigned int QSPI_AUTO_BASE_ADDR_ERR_INTR_ACK : 1; /*!< [8..8] Rising interrupt when no csn is selected using programmable auto base address. This bit is an ack for this interrupt. */ - __IOM uint32_t M4QSPI_MANUAL_BLOCKED_INTR_ACK : 1; /*!< [9..9] Rising interrupt when + __IOM unsigned int M4QSPI_MANUAL_BLOCKED_INTR_ACK : 1; /*!< [9..9] Rising interrupt when M4 QSPI tries to do manual mode transactions in Common flash mode (3). This bit is an ack for this interrupt. */ - __IOM uint32_t M4_AUTO_READ_OUT_RANGE_INTR_ACK : 1; /*!< [10..10] Rising interrupt + __IOM unsigned int M4_AUTO_READ_OUT_RANGE_INTR_ACK : 1; /*!< [10..10] Rising interrupt when M4 QSPI tries to read TA locations in Common flash mode (3). This bit is an ack for this interrupt. */ - __OM uint32_t RESERVED1 : 21; /*!< [31..11] reserved1 */ + __OM unsigned int RESERVED1 : 21; /*!< [31..11] reserved1 */ } QSPI_INTR_ACK_b; }; union { - __IM uint32_t QSPI_STS_MC; /*!< (@ 0x00000034) QSPI State Machine Monitor + __IM unsigned int QSPI_STS_MC; /*!< (@ 0x00000034) QSPI State Machine Monitor Register */ struct { - __IM uint32_t BUS_CTRL_PSTATE : 4; /*!< [3..0] Bus controller present state */ - __IM uint32_t AUTO_CTRL_PSTATE : 3; /*!< [6..4] Auto controller present state */ - __IM uint32_t QSPI_MASTER_PSTATE : 3; /*!< [9..7] Qspi master present state */ - __IM uint32_t QSPI_MANUAL_RD_CNT : 15; /*!< [24..10] Qspi manual read + __IM unsigned int BUS_CTRL_PSTATE : 4; /*!< [3..0] Bus controller present state */ + __IM unsigned int AUTO_CTRL_PSTATE : 3; /*!< [6..4] Auto controller present state */ + __IM unsigned int QSPI_MASTER_PSTATE : 3; /*!< [9..7] Qspi master present state */ + __IM unsigned int QSPI_MANUAL_RD_CNT : 15; /*!< [24..10] Qspi manual read counter value */ - __IM uint32_t RESERVED1 : 7; /*!< [31..25] reserved1 */ + __IM unsigned int RESERVED1 : 7; /*!< [31..25] reserved1 */ } QSPI_STS_MC_b; }; union { - __IOM uint32_t QSPI_AUTO_CONFIG_1_CSN1; /*!< (@ 0x00000038) QSPI Auto Controller + __IOM unsigned int QSPI_AUTO_CONFIG_1_CSN1; /*!< (@ 0x00000038) QSPI Auto Controller Configuration 1 CSN1 Register */ struct { - __IOM uint32_t QSPI_EXT_BYTE_MODE_CSN1 : 2; /*!< [1..0] Mode of operation of QSPI in + __IOM unsigned int QSPI_EXT_BYTE_MODE_CSN1 : 2; /*!< [1..0] Mode of operation of QSPI in instruction phase. */ - __IOM uint32_t QSPI_DUMMY_MODE_CSN1 : 2; /*!< [3..2] Mode of operation of + __IOM unsigned int QSPI_DUMMY_MODE_CSN1 : 2; /*!< [3..2] Mode of operation of QSPI in instruction phase */ - __IOM uint32_t QSPI_ADDR_MODE_CSN1 : 2; /*!< [5..4] Mode of operation of + __IOM unsigned int QSPI_ADDR_MODE_CSN1 : 2; /*!< [5..4] Mode of operation of QSPI in instruction phase. */ - __IOM uint32_t QSPI_CMD_MODE_CSN1 : 2; /*!< [7..6] Mode of operation of + __IOM unsigned int QSPI_CMD_MODE_CSN1 : 2; /*!< [7..6] Mode of operation of QSPI in instruction phase. */ - __IOM uint32_t QSPI_DATA_MODE_CSN1 : 2; /*!< [9..8] Mode of operation of + __IOM unsigned int QSPI_DATA_MODE_CSN1 : 2; /*!< [9..8] Mode of operation of QSPI in DATA phase. */ - __IM uint32_t QSPI_EXTRA_BYTE_CSN1 : 8; /*!< [17..10] Value of the extra byte to be + __IM unsigned int QSPI_EXTRA_BYTE_CSN1 : 8; /*!< [17..10] Value of the extra byte to be transmitted, if the extra byte mode is enabled. */ - __IOM uint32_t QSPI_EXTRA_BYTE_EN_CSN1 : 2; /*!< [19..18] Mode of operation of QSPI + __IOM unsigned int QSPI_EXTRA_BYTE_EN_CSN1 : 2; /*!< [19..18] Mode of operation of QSPI in DATA phase. */ - __IOM uint32_t QSPI_WRAP_SIZE : 2; /*!< [21..20] Qspi auto wrap size */ - __IOM uint32_t RESERVED1 : 1; /*!< [22..22] reserved1 */ - __OM uint32_t QSPI_PG_JUMP_CSN1 : 1; /*!< [23..23] NONE */ - __IM uint32_t QSPI_DUMMY_BYTES_INCR_CSN1 : 4; /*!< [27..24] Specifies the number of + __IOM unsigned int QSPI_WRAP_SIZE : 2; /*!< [21..20] Qspi auto wrap size */ + __IOM unsigned int RESERVED1 : 1; /*!< [22..22] reserved1 */ + __OM unsigned int QSPI_PG_JUMP_CSN1 : 1; /*!< [23..23] NONE */ + __IM unsigned int QSPI_DUMMY_BYTES_INCR_CSN1 : 4; /*!< [27..24] Specifies the number of dummy bytes 0 to 7 for the selected SPI mode. */ - __IM uint32_t QSPI_DUMMY_BYTES_WRAP_CSN1 : 4; /*!< [31..28] Specifies the number of + __IM unsigned int QSPI_DUMMY_BYTES_WRAP_CSN1 : 4; /*!< [31..28] Specifies the number of dummy bytes 0 to 7 for the selected SPI mode in case of wrap instruction. */ @@ -6053,81 +6053,81 @@ typedef struct { /*!< (@ 0x12000000) QSPI Structure */ }; union { - __IOM uint32_t QSPI_AUTO_CONFIG_2_CSN1_REG; /*!< (@ 0x0000003C) QSPI Auto Controller + __IOM unsigned int QSPI_AUTO_CONFIG_2_CSN1_REG; /*!< (@ 0x0000003C) QSPI Auto Controller Configuration 2 CSN1 Register */ struct { - __IOM uint32_t QSPI_RD_SWAP_AUTO_CSN1 : 1; /*!< [0..0] Swap the read data from the + __IOM unsigned int QSPI_RD_SWAP_AUTO_CSN1 : 1; /*!< [0..0] Swap the read data from the flash in byte order for chip select1 csn1 in auto mode. */ - __IOM uint32_t QSPI_ADR_SIZE_16BIT_AUTO_MODE_CSN1 : 1; /*!< [1..1] NONE */ - __IOM uint32_t QSPI_CONTI_RD_EN_CSN1 : 1; /*!< [2..2] Continuous read + __IOM unsigned int QSPI_ADR_SIZE_16BIT_AUTO_MODE_CSN1 : 1; /*!< [1..1] NONE */ + __IOM unsigned int QSPI_CONTI_RD_EN_CSN1 : 1; /*!< [2..2] Continuous read enable bit. */ - __IOM uint32_t DUMMY_BYTES_WR_RD : 1; /*!< [3..3] Dummy bytes to the model + __IOM unsigned int DUMMY_BYTES_WR_RD : 1; /*!< [3..3] Dummy bytes to the model to be read or to be write. */ - __IOM uint32_t QSPI_DUMMY_BYTES_JMP_CSN1 : 4; /*!< [7..4] Dummy cycles to be selected + __IOM unsigned int QSPI_DUMMY_BYTES_JMP_CSN1 : 4; /*!< [7..4] Dummy cycles to be selected in case of JUMP */ - __IOM uint32_t QSPI_RD_INST_CSN1 : 8; /*!< [15..8] Read instruction to be + __IOM unsigned int QSPI_RD_INST_CSN1 : 8; /*!< [15..8] Read instruction to be used for the selected SPI modes and when wrap is not needed or supported */ - __IOM uint32_t QSPI_RD_WRAP_INST_CSN1 : 8; /*!< [23..16] Read instruction to be used + __IOM unsigned int QSPI_RD_WRAP_INST_CSN1 : 8; /*!< [23..16] Read instruction to be used for the selected SPI modes and when wrap is not needed or supported */ - __IOM uint32_t QSPI_PG_JMP_INST_CSN1 : 8; /*!< [31..24] Read instruction to be used, + __IOM unsigned int QSPI_PG_JMP_INST_CSN1 : 8; /*!< [31..24] Read instruction to be used, when Page jump is to be used. */ } QSPI_AUTO_CONFIG_2_CSN1_REG_b; }; - __IOM uint32_t QSPI_MANUAL_RDWR_FIFO[16]; /*!< (@ 0x00000040) QSPI FIFOs */ + __IOM unsigned int QSPI_MANUAL_RDWR_FIFO[16]; /*!< (@ 0x00000040) QSPI FIFOs */ union { - __IOM uint32_t QSPI_MANUAL_WRITE_DATA2; /*!< (@ 0x00000080) QSPI Manual + __IOM unsigned int QSPI_MANUAL_WRITE_DATA2; /*!< (@ 0x00000080) QSPI Manual Write Data 2 Register */ struct { - __IOM uint32_t QSPI_MANUAL_WRITE_DATA2 : 5; /*!< [4..0] Number of bits to be written + __IOM unsigned int QSPI_MANUAL_WRITE_DATA2 : 5; /*!< [4..0] Number of bits to be written in write mode */ - __IOM uint32_t RESERVED1 : 2; /*!< [6..5] reserved1 */ - __IOM uint32_t USE_PREV_LENGTH : 1; /*!< [7..7] Use previous length. */ - __IOM uint32_t QSPI_CLK_ENABLE_HCLK : 1; /*!< [8..8] reserved2 */ - __IOM uint32_t RESERVED2 : 23; /*!< [31..9] reserved2 */ + __IOM unsigned int RESERVED1 : 2; /*!< [6..5] reserved1 */ + __IOM unsigned int USE_PREV_LENGTH : 1; /*!< [7..7] Use previous length. */ + __IOM unsigned int QSPI_CLK_ENABLE_HCLK : 1; /*!< [8..8] reserved2 */ + __IOM unsigned int RESERVED2 : 23; /*!< [31..9] reserved2 */ } QSPI_MANUAL_WRITE_DATA2_b; }; - __IM uint32_t RESERVED1[3]; + __IM unsigned int RESERVED1[3]; union { - __IOM uint32_t QSPI_AUTO_CONFIG_3_CSN0_REG; /*!< (@ 0x00000090) QSPI Auto Controller + __IOM unsigned int QSPI_AUTO_CONFIG_3_CSN0_REG; /*!< (@ 0x00000090) QSPI Auto Controller Configuration 3 CSN0 Register */ struct { - __IOM uint32_t QSPI_DUMMY_BYTE_OR_BIT_CSN0 : 1; /*!< [0..0] Indicates all above + __IOM unsigned int QSPI_DUMMY_BYTE_OR_BIT_CSN0 : 1; /*!< [0..0] Indicates all above mention values are dummy bytes or bits in auto mode. */ - __IOM uint32_t QSPI_DUMMY_BYTES_INCR_CSN0 : 4; /*!< [4..1] Specifies the number of + __IOM unsigned int QSPI_DUMMY_BYTES_INCR_CSN0 : 4; /*!< [4..1] Specifies the number of dummy bytes for the selected SPI mode. It contains MS nibble for byte. */ - __IOM uint32_t QSPI_DUMMY_BYTES_WRAP_CSN0 : 4; /*!< [8..5] Specifies the number of + __IOM unsigned int QSPI_DUMMY_BYTES_WRAP_CSN0 : 4; /*!< [8..5] Specifies the number of dummy bytes for the selected SPI mode in case of wrap instruction. It contains MS nibble for byte. */ - __IOM uint32_t RESERVED1 : 3; /*!< [11..9] reserved1 */ - __IOM uint32_t QSPI_DDR_CMD_MODE_CSN0 : 1; /*!< [12..12] DDR Command mode */ - __IOM uint32_t QSPI_DDR_ADDR_MODE_CSN0 : 1; /*!< [13..13] DDR Address mode */ - __IOM uint32_t QSPI_DDR_DUMMY_MODE_CSN0 : 1; /*!< [14..14] DDR Address mode */ - __IOM uint32_t QSPI_DDR_EXTRA_MODE_CSN0 : 1; /*!< [15..15] DDR Address mode */ - __IOM uint32_t QSPI_DDR_DATA_MODE_CSN0 : 1; /*!< [16..16] DDR Address mode */ - __IOM uint32_t QSPI_AUTO_DDR_CMD_MODE_CSN0 : 1; /*!< [17..17] DDR data mode. */ - __IOM uint32_t QSPI_CMD_SIZE_16BIT_CSN0 : 1; /*!< [18..18] Enable for 16 read cmd + __IOM unsigned int RESERVED1 : 3; /*!< [11..9] reserved1 */ + __IOM unsigned int QSPI_DDR_CMD_MODE_CSN0 : 1; /*!< [12..12] DDR Command mode */ + __IOM unsigned int QSPI_DDR_ADDR_MODE_CSN0 : 1; /*!< [13..13] DDR Address mode */ + __IOM unsigned int QSPI_DDR_DUMMY_MODE_CSN0 : 1; /*!< [14..14] DDR Address mode */ + __IOM unsigned int QSPI_DDR_EXTRA_MODE_CSN0 : 1; /*!< [15..15] DDR Address mode */ + __IOM unsigned int QSPI_DDR_DATA_MODE_CSN0 : 1; /*!< [16..16] DDR Address mode */ + __IOM unsigned int QSPI_AUTO_DDR_CMD_MODE_CSN0 : 1; /*!< [17..17] DDR data mode. */ + __IOM unsigned int QSPI_CMD_SIZE_16BIT_CSN0 : 1; /*!< [18..18] Enable for 16 read cmd size for csn0. */ - __IOM uint32_t QSPI_ADR_SIZE_32BIT_AUTO_MODE : 1; /*!< [19..19] 32 bit addressing + __IOM unsigned int QSPI_ADR_SIZE_32BIT_AUTO_MODE : 1; /*!< [19..19] 32 bit addressing support enable. */ - __IOM uint32_t QSPI_RD_DATA_SWAP_WORD_LVL_AUTO_CSN0 : 1; /*!< [20..20] Rd data swap + __IOM unsigned int QSPI_RD_DATA_SWAP_WORD_LVL_AUTO_CSN0 : 1; /*!< [20..20] Rd data swap at word level in auto mode for csn0. It is valid for octa mode. */ - __IOM uint32_t RESERVED3 : 3; /*!< [23..21] reserved3 */ - __IOM uint32_t QSPI_RD_INST_CSN0_MSB : 8; /*!< [31..24] Read instruction MS byte to + __IOM unsigned int RESERVED3 : 3; /*!< [23..21] reserved3 */ + __IOM unsigned int QSPI_RD_INST_CSN0_MSB : 8; /*!< [31..24] Read instruction MS byte to be used the selected SPI modes and when wrap is not needed or supported. */ @@ -6135,49 +6135,49 @@ typedef struct { /*!< (@ 0x12000000) QSPI Structure */ }; union { - __IOM uint32_t QSPI_AUTO_CONFIG_3_CSN1_REG; /*!< (@ 0x00000094) QSPI Auto Controller + __IOM unsigned int QSPI_AUTO_CONFIG_3_CSN1_REG; /*!< (@ 0x00000094) QSPI Auto Controller Configuration 3 CSN1 Register */ struct { - __IOM uint32_t QSPI_DUMMY_BYTE_OR_BIT_CSN1 : 1; /*!< [0..0] Indicates all above + __IOM unsigned int QSPI_DUMMY_BYTE_OR_BIT_CSN1 : 1; /*!< [0..0] Indicates all above mention values are dummy bytes or bits in auto mode. */ - __IOM uint32_t QSPI_DUMMY_BYTES_INCR_CSN1 : 4; /*!< [4..1] Specifies the number of + __IOM unsigned int QSPI_DUMMY_BYTES_INCR_CSN1 : 4; /*!< [4..1] Specifies the number of dummy bytes for the selected SPI mode. It contains MS nibble for byte. */ - __IOM uint32_t QSPI_DUMMY_BYTES_WRAP_CSN1 : 4; /*!< [8..5] Specifies the number of + __IOM unsigned int QSPI_DUMMY_BYTES_WRAP_CSN1 : 4; /*!< [8..5] Specifies the number of dummy bytes for the selected SPI mode in case of wrap instruction. It contains MS nibble for byte. */ - __IOM uint32_t RESERVED1 : 3; /*!< [11..9] reserved1 */ - __IOM uint32_t QSPI_DDR_CMD_MODE_CSN1 : 1; /*!< [12..12] DDR Command mode */ - __IOM uint32_t QSPI_DDR_ADDR_MODE_CSN1 : 1; /*!< [13..13] DDR Address mode */ - __IOM uint32_t QSPI_DDR_DUMMY_MODE_CSN1 : 1; /*!< [14..14] DDR Address mode */ - __IOM uint32_t QSPI_DDR_EXTRA_MODE_CSN1 : 1; /*!< [15..15] DDR Address mode */ - __IOM uint32_t QSPI_DDR_DATA_MODE_CSN1 : 1; /*!< [16..16] DDR Address mode */ - __IOM uint32_t QSPI_AUTO_DDR_CMD_MODE_CSN1 : 1; /*!< [17..17] DDR data mode. */ - __IOM uint32_t QSPI_CMD_SIZE_16BIT_CSN1 : 1; /*!< [18..18] Enable for 16 read cmd + __IOM unsigned int RESERVED1 : 3; /*!< [11..9] reserved1 */ + __IOM unsigned int QSPI_DDR_CMD_MODE_CSN1 : 1; /*!< [12..12] DDR Command mode */ + __IOM unsigned int QSPI_DDR_ADDR_MODE_CSN1 : 1; /*!< [13..13] DDR Address mode */ + __IOM unsigned int QSPI_DDR_DUMMY_MODE_CSN1 : 1; /*!< [14..14] DDR Address mode */ + __IOM unsigned int QSPI_DDR_EXTRA_MODE_CSN1 : 1; /*!< [15..15] DDR Address mode */ + __IOM unsigned int QSPI_DDR_DATA_MODE_CSN1 : 1; /*!< [16..16] DDR Address mode */ + __IOM unsigned int QSPI_AUTO_DDR_CMD_MODE_CSN1 : 1; /*!< [17..17] DDR data mode. */ + __IOM unsigned int QSPI_CMD_SIZE_16BIT_CSN1 : 1; /*!< [18..18] Enable for 16 read cmd size for csn1. */ - __IOM uint32_t RESERVED3 : 1; /*!< [19..19] RESERVED3 */ - __IOM uint32_t QSPI_RD_DATA_SWAP_WORD_LVL_AUTO_CSN1 : 1; /*!< [20..20] Rd data swap + __IOM unsigned int RESERVED3 : 1; /*!< [19..19] RESERVED3 */ + __IOM unsigned int QSPI_RD_DATA_SWAP_WORD_LVL_AUTO_CSN1 : 1; /*!< [20..20] Rd data swap at word level in auto mode for csn1. It is valid for octa mode. */ - __IOM uint32_t RESERVED4 : 3; /*!< [23..21] reserved4 */ - __IOM uint32_t QSPI_RD_INST_CSN1_MSB : 8; /*!< [31..24] Read instruction MS byte to + __IOM unsigned int RESERVED4 : 3; /*!< [23..21] reserved4 */ + __IOM unsigned int QSPI_RD_INST_CSN1_MSB : 8; /*!< [31..24] Read instruction MS byte to be used the selected SPI modes and when wrap is not needed or supported. */ } QSPI_AUTO_CONFIG_3_CSN1_REG_b; }; - __IM uint32_t RESERVED2[2]; + __IM unsigned int RESERVED2[2]; union { - __IOM uint32_t QSPI_AUTO_BASE_ADDR_CSN0; /*!< (@ 0x000000A0) none */ + __IOM unsigned int QSPI_AUTO_BASE_ADDR_CSN0; /*!< (@ 0x000000A0) none */ struct { - __IOM uint32_t QSPI_AUTO_BASE_ADDR_CSN0 : 32; /*!< [31..0] Holds the 32 bit base + __IOM unsigned int QSPI_AUTO_BASE_ADDR_CSN0 : 32; /*!< [31..0] Holds the 32 bit base address for select chip select0 in programmable auto csn mode. It is valid only programmable @@ -6186,52 +6186,52 @@ typedef struct { /*!< (@ 0x12000000) QSPI Structure */ }; union { - __IOM uint32_t QSPI_AUTO_BASE_ADDR_CSN1; /*!< (@ 0x000000A4) none */ + __IOM unsigned int QSPI_AUTO_BASE_ADDR_CSN1; /*!< (@ 0x000000A4) none */ struct { - __IOM uint32_t QSPI_AUTO_BASE_ADDR_CSN1 : 32; /*!< [31..0] Holds the 32 bit base + __IOM unsigned int QSPI_AUTO_BASE_ADDR_CSN1 : 32; /*!< [31..0] Holds the 32 bit base address for select chip select1 in programmable auto csn mode. It is valid only programmable auto csn mode is enabled. */ } QSPI_AUTO_BASE_ADDR_CSN1_b; }; - __IM uint32_t RESERVED3[2]; + __IM unsigned int RESERVED3[2]; union { - __IOM uint32_t OCTASPI_BUS_CONTROLLER; /*!< (@ 0x000000B0) none */ + __IOM unsigned int OCTASPI_BUS_CONTROLLER; /*!< (@ 0x000000B0) none */ struct { - __IOM uint32_t QSPI_D7TOD4_DATA_CSN0 : 4; /*!< [3..0] Value of SPI_IO7,6,5 and 4 in + __IOM unsigned int QSPI_D7TOD4_DATA_CSN0 : 4; /*!< [3..0] Value of SPI_IO7,6,5 and 4 in case of quad/dual/single mode for chip select1 (cs_n0). It is used both in Auto and Manual Mode. */ - __IOM uint32_t QSPI_D7TOD4_OEN_CSN0 : 4; /*!< [7..4] Direction Control for SPI_IO + __IOM unsigned int QSPI_D7TOD4_OEN_CSN0 : 4; /*!< [7..4] Direction Control for SPI_IO 7,6,5 and 4 in case of quad/dual/single mode for chip select0 (cs_n0). It is used both in Auto and Manual Mode. */ - __IOM uint32_t QSPI_D7TOD4_DATA_CSN1 : 4; /*!< [11..8] Value of SPI_IO7,6,5 and 4 in + __IOM unsigned int QSPI_D7TOD4_DATA_CSN1 : 4; /*!< [11..8] Value of SPI_IO7,6,5 and 4 in case of quad/dual/single mode for chip select1 (cs_n1). It is used both in Auto and Manual Mode. */ - __IOM uint32_t QSPI_D7TOD4_OEN_CSN1 : 4; /*!< [15..12] Direction Control for SPI_IO + __IOM unsigned int QSPI_D7TOD4_OEN_CSN1 : 4; /*!< [15..12] Direction Control for SPI_IO 7,6,5 and 4 in case of quad/dual/single mode for chip select1 (cs_n1). It is used both in Auto and Manual Mode. */ - __IOM uint32_t QSPI_D7TOD4_DATA_CSN2 : 4; /*!< [19..16] Value of SPI_IO7,6,5 and 4 in + __IOM unsigned int QSPI_D7TOD4_DATA_CSN2 : 4; /*!< [19..16] Value of SPI_IO7,6,5 and 4 in case of quad/dual/single mode for chip select2 (cs_n2). It is used both in Auto and Manual Mode. */ - __IOM uint32_t QSPI_D7TOD4_OEN_CSN2 : 4; /*!< [23..20] Direction Control for SPI_IO + __IOM unsigned int QSPI_D7TOD4_OEN_CSN2 : 4; /*!< [23..20] Direction Control for SPI_IO 7,6,5 and 4 in case of quad/dual/single mode for chip select2 (cs_n2). It is used both in Auto and Manual Mode. */ - __IOM uint32_t QSPI_D7TOD4_DATA_CSN3 : 4; /*!< [27..24] Value of SPI_IO7,6,5 and 4 in + __IOM unsigned int QSPI_D7TOD4_DATA_CSN3 : 4; /*!< [27..24] Value of SPI_IO7,6,5 and 4 in case of quad/dual/single mode for chip select3 (cs_n3). It is used both in Auto and Manual Mode. */ - __IOM uint32_t QSPI_D7TOD4_OEN_CSN3 : 4; /*!< [31..28] Direction Control for SPI_IO + __IOM unsigned int QSPI_D7TOD4_OEN_CSN3 : 4; /*!< [31..28] Direction Control for SPI_IO 7,6,5 and 4 in case of quad/dual/single mode for chip select3 (cs_n3). It is used both in Auto and Manual Mode. */ @@ -6239,10 +6239,10 @@ typedef struct { /*!< (@ 0x12000000) QSPI Structure */ }; union { - __IOM uint32_t QSPI_AUTO_BASE_ADDR_UNMASK_CSN0; /*!< (@ 0x000000B4) none */ + __IOM unsigned int QSPI_AUTO_BASE_ADDR_UNMASK_CSN0; /*!< (@ 0x000000B4) none */ struct { - __IOM uint32_t QSPI_AUTO_BASE_ADDR_UNMASK_CSN0 : 32; /*!< [31..0] Holds the 32 bit + __IOM unsigned int QSPI_AUTO_BASE_ADDR_UNMASK_CSN0 : 32; /*!< [31..0] Holds the 32 bit base address unmask value for select chip select0 in programmable auto csn mode. @@ -6253,10 +6253,10 @@ typedef struct { /*!< (@ 0x12000000) QSPI Structure */ }; union { - __IOM uint32_t QSPI_AUTO_BASE_ADDR_UNMASK_CSN1; /*!< (@ 0x000000B8) none */ + __IOM unsigned int QSPI_AUTO_BASE_ADDR_UNMASK_CSN1; /*!< (@ 0x000000B8) none */ struct { - __IOM uint32_t QSPI_AUTO_BASE_ADDR_UNMASK_CSN1 : 32; /*!< [31..0] Holds the 32 bit + __IOM unsigned int QSPI_AUTO_BASE_ADDR_UNMASK_CSN1 : 32; /*!< [31..0] Holds the 32 bit base address unmask value for select chip select1 in programmable auto csn mode. @@ -6265,362 +6265,362 @@ typedef struct { /*!< (@ 0x12000000) QSPI Structure */ csn mode is enabled. */ } QSPI_AUTO_BASE_ADDR_UNMASK_CSN1_b; }; - __IM uint32_t RESERVED4[2]; + __IM unsigned int RESERVED4[2]; union { - __IOM uint32_t OCTASPI_BUS_CONTROLLER_2_REG; /*!< (@ 0x000000C4) none */ + __IOM unsigned int OCTASPI_BUS_CONTROLLER_2_REG; /*!< (@ 0x000000C4) none */ struct { - __IOM uint32_t SET_IP_MODE : 1; /*!< [0..0] This bit enables the qspi + __IOM unsigned int SET_IP_MODE : 1; /*!< [0..0] This bit enables the qspi interface pins into HiZ mode */ - __IOM uint32_t AES_NONCE_INIT : 1; /*!< [1..1] This bit enables the AES + __IOM unsigned int AES_NONCE_INIT : 1; /*!< [1..1] This bit enables the AES initialization with nonce */ - __IOM uint32_t AES_SEC_ENABLE : 1; /*!< [2..2] This bit enables the AES + __IOM unsigned int AES_SEC_ENABLE : 1; /*!< [2..2] This bit enables the AES security enable or not */ - __IOM uint32_t DUAL_MODE_EN : 1; /*!< [3..3] Dual flash mode enable control. */ - __IOM uint32_t CSN0_2_CSN : 2; /*!< [5..4] Map csn0 to the programmed csn. It is + __IOM unsigned int DUAL_MODE_EN : 1; /*!< [3..3] Dual flash mode enable control. */ + __IOM unsigned int CSN0_2_CSN : 2; /*!< [5..4] Map csn0 to the programmed csn. It is valid for both manual and auto modes */ - __IOM uint32_t CSN1_2_CSN : 2; /*!< [7..6] Map csn1 to the programmed csn. It is + __IOM unsigned int CSN1_2_CSN : 2; /*!< [7..6] Map csn1 to the programmed csn. It is valid for both manual and auto modes */ - __IOM uint32_t CSN2_2_CSN : 2; /*!< [9..8] Map csn2 to the programmed csn. It is + __IOM unsigned int CSN2_2_CSN : 2; /*!< [9..8] Map csn2 to the programmed csn. It is valid for both manual and auto modes */ - __IOM uint32_t CSN3_2_CSN : 2; /*!< [11..10] Map csn3 to the programmed csn. It is + __IOM unsigned int CSN3_2_CSN : 2; /*!< [11..10] Map csn3 to the programmed csn. It is valid for both manual and auto modes */ - __IOM uint32_t AES_SEC_ENABLE_SG1 : 1; /*!< [12..12] This bit enables the AES + __IOM unsigned int AES_SEC_ENABLE_SG1 : 1; /*!< [12..12] This bit enables the AES security enable or not for segment 1 */ - __IOM uint32_t AES_SEC_ENABLE_SG2 : 1; /*!< [13..13] This bit enables the AES + __IOM unsigned int AES_SEC_ENABLE_SG2 : 1; /*!< [13..13] This bit enables the AES security enable or not for segment 2 */ - __IOM uint32_t AES_SEC_ENABLE_SG3 : 1; /*!< [14..14] This bit enables the AES + __IOM unsigned int AES_SEC_ENABLE_SG3 : 1; /*!< [14..14] This bit enables the AES security enable or not for segment 3 */ - __IOM uint32_t AES_SEC_ENABLE_SG4 : 1; /*!< [15..15] This bit enables the AES + __IOM unsigned int AES_SEC_ENABLE_SG4 : 1; /*!< [15..15] This bit enables the AES security enable or not for segment 4 */ - __IOM uint32_t DUAL_MODE_SWAP_LINES : 1; /*!< [16..16] This bit controls the 8 lines + __IOM unsigned int DUAL_MODE_SWAP_LINES : 1; /*!< [16..16] This bit controls the 8 lines of qspi with 4 bit swap manner */ - __IOM uint32_t AUTO_MODE_IN_DEFAULT_EN : 1; /*!< [17..17] Qspi works in auto mode if + __IOM unsigned int AUTO_MODE_IN_DEFAULT_EN : 1; /*!< [17..17] Qspi works in auto mode if set this is bit by default. */ - __IOM uint32_t OTP_KEY_LOAD : 1; /*!< [18..18] Enable to load key from OTP/KH */ - __IOM uint32_t DUAL_STAGE_EN_MANUAL : 1; /*!< [19..19] Dual stage en for + __IOM unsigned int OTP_KEY_LOAD : 1; /*!< [18..18] Enable to load key from OTP/KH */ + __IOM unsigned int DUAL_STAGE_EN_MANUAL : 1; /*!< [19..19] Dual stage en for dual flash mode */ - __IOM uint32_t RESERVED2 : 12; /*!< [31..20] reserved2 */ + __IOM unsigned int RESERVED2 : 12; /*!< [31..20] reserved2 */ } OCTASPI_BUS_CONTROLLER_2_REG_b; }; union { - __IOM uint32_t QSPI_AES_CONFIG; /*!< (@ 0x000000C8) QSPI AES CONFIG REG */ + __IOM unsigned int QSPI_AES_CONFIG; /*!< (@ 0x000000C8) QSPI AES CONFIG REG */ struct { - __IOM uint32_t QSPI_AES_MODE : 9; /*!< [8..0] AES mode of decryption CTR/XTS */ - __IOM uint32_t QSPI_AES_DECKEYCAL : 1; /*!< [9..9] Enables pre-calculation of KEY + __IOM unsigned int QSPI_AES_MODE : 9; /*!< [8..0] AES mode of decryption CTR/XTS */ + __IOM unsigned int QSPI_AES_DECKEYCAL : 1; /*!< [9..9] Enables pre-calculation of KEY before decryption operation */ - __IOM uint32_t FLIP_KEY_FRM_REG : 1; /*!< [10..10] writing 1 to this Flips the 32-bit + __IOM unsigned int FLIP_KEY_FRM_REG : 1; /*!< [10..10] writing 1 to this Flips the 32-bit endian key taken from kh */ - __IOM uint32_t FLIP_KEY_FRM_KH : 1; /*!< [11..11] writing 1 to this Flips the 32-bit + __IOM unsigned int FLIP_KEY_FRM_KH : 1; /*!< [11..11] writing 1 to this Flips the 32-bit endian key taken from kh */ - __OM uint32_t QSPI_AES_SRST : 1; /*!< [12..12] Synchronous soft reset for + __OM unsigned int QSPI_AES_SRST : 1; /*!< [12..12] Synchronous soft reset for AES Module. Write only bit. Reading this bit gives alway 0 */ - __IOM uint32_t RESERVED1 : 19; /*!< [31..13] reserved1 */ + __IOM unsigned int RESERVED1 : 19; /*!< [31..13] reserved1 */ } QSPI_AES_CONFIG_b; }; union { - __IOM uint32_t QSPI_AES_KEY_IV_VALID; /*!< (@ 0x000000CC) QSPI AES KEYS and + __IOM unsigned int QSPI_AES_KEY_IV_VALID; /*!< (@ 0x000000CC) QSPI AES KEYS and IVS VALID */ struct { - __IOM uint32_t QSPI_AES_KEY1_VALID : 4; /*!< [3..0] Write enables for AES KEY 1. + __IOM unsigned int QSPI_AES_KEY1_VALID : 4; /*!< [3..0] Write enables for AES KEY 1. Denotes which bytes of key1 is valid */ - __IOM uint32_t RESERVED1 : 4; /*!< [7..4] reserved1 */ - __IOM uint32_t QSPI_AES_KEY2_VALID : 4; /*!< [11..8] Write enables for AES KEY 2. + __IOM unsigned int RESERVED1 : 4; /*!< [7..4] reserved1 */ + __IOM unsigned int QSPI_AES_KEY2_VALID : 4; /*!< [11..8] Write enables for AES KEY 2. Denotes which bytes of key2 is valid */ - __IOM uint32_t RESERVED2 : 4; /*!< [15..12] reserved2 */ - __IOM uint32_t QSPI_AES_IV1_VALID : 4; /*!< [19..16] Write enables for AES IV 1. + __IOM unsigned int RESERVED2 : 4; /*!< [15..12] reserved2 */ + __IOM unsigned int QSPI_AES_IV1_VALID : 4; /*!< [19..16] Write enables for AES IV 1. Denotes which bytes of IV1 is valid */ - __IOM uint32_t RESERVED3 : 12; /*!< [31..20] reserved3 */ + __IOM unsigned int RESERVED3 : 12; /*!< [31..20] reserved3 */ } QSPI_AES_KEY_IV_VALID_b; }; union { - __IM uint32_t QSPI_CMNFLASH_STS; /*!< (@ 0x000000D0) QSPI Common Flash Status */ + __IM unsigned int QSPI_CMNFLASH_STS; /*!< (@ 0x000000D0) QSPI Common Flash Status */ struct { - __IM uint32_t QSPI_MANUAL_BLOCKED : 1; /*!< [0..0] 1 - Manual read/write transaction + __IM unsigned int QSPI_MANUAL_BLOCKED : 1; /*!< [0..0] 1 - Manual read/write transaction initiated is blocked.0- No manual transactions */ - __IM uint32_t AUTO_READ_OUT_RANGE : 1; /*!< [1..1] 1- Auto read transaction is out + __IM unsigned int AUTO_READ_OUT_RANGE : 1; /*!< [1..1] 1- Auto read transaction is out of M4 Address range 0- Auto read transaction is in Address range */ - __IM uint32_t QSPI_AUTO_RD_BUSY : 1; /*!< [2..2] 1 - Auto read transactions in + __IM unsigned int QSPI_AUTO_RD_BUSY : 1; /*!< [2..2] 1 - Auto read transactions in progress.0 - No Auto read transactions */ - __IM uint32_t RESERVED1 : 29; /*!< [31..3] reserved1 */ + __IM unsigned int RESERVED1 : 29; /*!< [31..3] reserved1 */ } QSPI_CMNFLASH_STS_b; }; - __IM uint32_t RESERVED5[4]; + __IM unsigned int RESERVED5[4]; union { - __IOM uint32_t QSPI_AES_SEC_SEG_LS_ADDR_1; /*!< (@ 0x000000E4) + __IOM unsigned int QSPI_AES_SEC_SEG_LS_ADDR_1; /*!< (@ 0x000000E4) QSPI_AES_SEC_SEG_LS_ADDR_1 */ struct { - __IOM uint32_t QSPI_AES_SEC_SEG_LS_ADDR_1 : 32; /*!< [31..0] This register specifies + __IOM unsigned int QSPI_AES_SEC_SEG_LS_ADDR_1 : 32; /*!< [31..0] This register specifies the lower boundary address of 1st segment */ } QSPI_AES_SEC_SEG_LS_ADDR_1_b; }; union { - __IOM uint32_t QSPI_AES_SEC_SEG_MS_ADDR_1; /*!< (@ 0x000000E8) + __IOM unsigned int QSPI_AES_SEC_SEG_MS_ADDR_1; /*!< (@ 0x000000E8) QSPI_AES_SEC_SEG_MS_ADDR_1 */ struct { - __IOM uint32_t QSPI_AES_SEC_SEG_MS_ADDR_1 : 32; /*!< [31..0] This register specifies + __IOM unsigned int QSPI_AES_SEC_SEG_MS_ADDR_1 : 32; /*!< [31..0] This register specifies the upper boundary address of 1st segment */ } QSPI_AES_SEC_SEG_MS_ADDR_1_b; }; union { - __IOM uint32_t QSPI_AES_SEC_SEG_LS_ADDR_2; /*!< (@ 0x000000EC) + __IOM unsigned int QSPI_AES_SEC_SEG_LS_ADDR_2; /*!< (@ 0x000000EC) QSPI_AES_SEC_SEG_LS_ADDR_2 */ struct { - __IOM uint32_t QSPI_AES_SEC_SEG_LS_ADDR_2 : 32; /*!< [31..0] This register specifies + __IOM unsigned int QSPI_AES_SEC_SEG_LS_ADDR_2 : 32; /*!< [31..0] This register specifies the lower boundary address of 2nd segment */ } QSPI_AES_SEC_SEG_LS_ADDR_2_b; }; union { - __IOM uint32_t QSPI_AES_SEC_SEG_MS_ADDR_2; /*!< (@ 0x000000F0) + __IOM unsigned int QSPI_AES_SEC_SEG_MS_ADDR_2; /*!< (@ 0x000000F0) QSPI_AES_SEC_SEG_MS_ADDR_2 */ struct { - __IOM uint32_t QSPI_AES_SEC_SEG_MS_ADDR_2 : 32; /*!< [31..0] This register specifies + __IOM unsigned int QSPI_AES_SEC_SEG_MS_ADDR_2 : 32; /*!< [31..0] This register specifies the upper boundary address of 2nd segment */ } QSPI_AES_SEC_SEG_MS_ADDR_2_b; }; union { - __IOM uint32_t QSPI_AES_SEC_SEG_LS_ADDR_3; /*!< (@ 0x000000F4) + __IOM unsigned int QSPI_AES_SEC_SEG_LS_ADDR_3; /*!< (@ 0x000000F4) QSPI_AES_SEC_SEG_LS_ADDR_3 */ struct { - __IOM uint32_t QSPI_AES_SEC_SEG_LS_ADDR_3 : 32; /*!< [31..0] This register specifies + __IOM unsigned int QSPI_AES_SEC_SEG_LS_ADDR_3 : 32; /*!< [31..0] This register specifies the lower boundary address of 3rd segment */ } QSPI_AES_SEC_SEG_LS_ADDR_3_b; }; union { - __IOM uint32_t QSPI_AES_SEC_SEG_MS_ADDR_3; /*!< (@ 0x000000F8) + __IOM unsigned int QSPI_AES_SEC_SEG_MS_ADDR_3; /*!< (@ 0x000000F8) QSPI_AES_SEC_SEG_MS_ADDR_3 */ struct { - __IOM uint32_t QSPI_AES_SEC_SEG_MS_ADDR_3 : 32; /*!< [31..0] This register specifies + __IOM unsigned int QSPI_AES_SEC_SEG_MS_ADDR_3 : 32; /*!< [31..0] This register specifies the upper boundary address of 3rd segment */ } QSPI_AES_SEC_SEG_MS_ADDR_3_b; }; union { - __IOM uint32_t QSPI_AES_SEC_SEG_LS_ADDR_4; /*!< (@ 0x000000FC) + __IOM unsigned int QSPI_AES_SEC_SEG_LS_ADDR_4; /*!< (@ 0x000000FC) QSPI_AES_SEC_SEG_LS_ADDR_4 */ struct { - __IOM uint32_t QSPI_AES_SEC_SEG_LS_ADDR_4 : 32; /*!< [31..0] This register specifies + __IOM unsigned int QSPI_AES_SEC_SEG_LS_ADDR_4 : 32; /*!< [31..0] This register specifies the lower boundary address of 4th segment */ } QSPI_AES_SEC_SEG_LS_ADDR_4_b; }; union { - __IOM uint32_t QSPI_AES_SEC_SEG_MS_ADDR_4; /*!< (@ 0x00000100) + __IOM unsigned int QSPI_AES_SEC_SEG_MS_ADDR_4; /*!< (@ 0x00000100) QSPI_AES_SEC_SEG_MS_ADDR_4 */ struct { - __IOM uint32_t QSPI_AES_SEC_SEG_MS_ADDR_4 : 32; /*!< [31..0] This register specifies + __IOM unsigned int QSPI_AES_SEC_SEG_MS_ADDR_4 : 32; /*!< [31..0] This register specifies the upper boundary address of 4th segment */ } QSPI_AES_SEC_SEG_MS_ADDR_4_b; }; union { - __IOM uint32_t QSPI_SRAM_CTRL_CSN_REG[4]; /*!< (@ 0x00000104) QSPI SRAM CTRL CSN */ + __IOM unsigned int QSPI_SRAM_CTRL_CSN_REG[4]; /*!< (@ 0x00000104) QSPI SRAM CTRL CSN */ struct { - __IOM uint32_t BIT_8_MODE : 1; /*!< [0..0] Flash 8bit (1 byte) boundary mode */ - __IOM uint32_t BYTE_32_MODE : 1; /*!< [1..1] Flash 32 byte boundary mode */ - __IOM uint32_t ADDR_16BIT_MODE : 1; /*!< [2..2] Send only lower 16bits of + __IOM unsigned int BIT_8_MODE : 1; /*!< [0..0] Flash 8bit (1 byte) boundary mode */ + __IOM unsigned int BYTE_32_MODE : 1; /*!< [1..1] Flash 32 byte boundary mode */ + __IOM unsigned int ADDR_16BIT_MODE : 1; /*!< [2..2] Send only lower 16bits of Address enable. */ - __IOM uint32_t RESERVED1 : 5; /*!< [7..3] reserved1 */ - __IOM uint32_t CMD_MODE : 2; /*!< [9..8] writing cmd mode */ - __IOM uint32_t ADDR_MODE : 2; /*!< [11..10] writing address mode */ - __IOM uint32_t DATA_MODE : 2; /*!< [13..12] writing address mode */ - __IOM uint32_t RESERVED2 : 2; /*!< [15..14] reserved2 */ - __IOM uint32_t WR_CMD : 8; /*!< [23..16] Command to be used for writing */ - __IOM uint32_t RESERVED3 : 8; /*!< [31..24] reserved3 */ + __IOM unsigned int RESERVED1 : 5; /*!< [7..3] reserved1 */ + __IOM unsigned int CMD_MODE : 2; /*!< [9..8] writing cmd mode */ + __IOM unsigned int ADDR_MODE : 2; /*!< [11..10] writing address mode */ + __IOM unsigned int DATA_MODE : 2; /*!< [13..12] writing address mode */ + __IOM unsigned int RESERVED2 : 2; /*!< [15..14] reserved2 */ + __IOM unsigned int WR_CMD : 8; /*!< [23..16] Command to be used for writing */ + __IOM unsigned int RESERVED3 : 8; /*!< [31..24] reserved3 */ } QSPI_SRAM_CTRL_CSN_REG_b[4]; }; - __IM uint32_t RESERVED6[2]; + __IM unsigned int RESERVED6[2]; __IOM - uint32_t SEMI_AUTO_MODE_ADDR_REG; /*!< (@ 0x0000011C) Byte address to read + unsigned int SEMI_AUTO_MODE_ADDR_REG; /*!< (@ 0x0000011C) Byte address to read the data from flash in semi auto mode. It is valid only semi auto mode enable bit is asserted */ union { - __IOM uint32_t SEMI_AUTO_MODE_CONFIG_REG; /*!< (@ 0x00000120) none */ + __IOM unsigned int SEMI_AUTO_MODE_CONFIG_REG; /*!< (@ 0x00000120) none */ struct { - __IOM uint32_t QSPI_SEMI_AUTO_BSIZE : 8; /*!< [7..0] This is burst size to read data + __IOM unsigned int QSPI_SEMI_AUTO_BSIZE : 8; /*!< [7..0] This is burst size to read data from flash in semi auto mode */ - __IOM uint32_t QSPI_SEMI_AUTO_HSIZE : 2; /*!< [9..8] Indicates number of bytes valid + __IOM unsigned int QSPI_SEMI_AUTO_HSIZE : 2; /*!< [9..8] Indicates number of bytes valid in each transaction */ - __IOM uint32_t RESERVED1 : 22; /*!< [31..10] reserved1 */ + __IOM unsigned int RESERVED1 : 22; /*!< [31..10] reserved1 */ } SEMI_AUTO_MODE_CONFIG_REG_b; }; union { - __IOM uint32_t SEMI_AUTO_MODE_CONFIG2_REG; /*!< (@ 0x00000124) none */ + __IOM unsigned int SEMI_AUTO_MODE_CONFIG2_REG; /*!< (@ 0x00000124) none */ struct { - __IOM uint32_t QSPI_SEMI_AUTO_RD_CNT : 12; /*!< [11..0] Total number of bytes to be + __IOM unsigned int QSPI_SEMI_AUTO_RD_CNT : 12; /*!< [11..0] Total number of bytes to be read flash continuously from the address given by SEMI_AUTO_MODE_ADDR_REG */ - __IOM uint32_t QSPI_SEMI_AUTO_MODE_EN : 1; /*!< [12..12] Enable for semi auto mode + __IOM unsigned int QSPI_SEMI_AUTO_MODE_EN : 1; /*!< [12..12] Enable for semi auto mode read operation. Make sure manual mode read/write operation is completed before asserting this bit */ - __IOM uint32_t QSPI_SEMI_AUTO_RD_BUSY : 1; /*!< [13..13] Indicates status of semi + __IOM unsigned int QSPI_SEMI_AUTO_RD_BUSY : 1; /*!< [13..13] Indicates status of semi auto mode read status. If it is high, semi auto mode read operation is progressing */ - __IOM uint32_t RESERVED1 : 18; /*!< [31..14] reserved1 */ + __IOM unsigned int RESERVED1 : 18; /*!< [31..14] reserved1 */ } SEMI_AUTO_MODE_CONFIG2_REG_b; }; union { - __IOM uint32_t QSPI_BUS_MODE2_REG; /*!< (@ 0x00000128) none */ + __IOM unsigned int QSPI_BUS_MODE2_REG; /*!< (@ 0x00000128) none */ struct { - __IOM uint32_t PREFETCH_ENBLD_MSTR_ID : 4; /*!< [3..0] Holds the programmable + __IOM unsigned int PREFETCH_ENBLD_MSTR_ID : 4; /*!< [3..0] Holds the programmable prefetch enabled AHB master ID. This is commonly used for enabling prefetch for icache master. */ - __IOM uint32_t PREFETCH_EN_FOR_ICACHE_MSTR : 1; /*!< [4..4] Prefetch enable for + __IOM unsigned int PREFETCH_EN_FOR_ICACHE_MSTR : 1; /*!< [4..4] Prefetch enable for icache AHB master. */ - __IOM uint32_t RESERVED1 : 3; /*!< [7..5] Reserved for future use */ + __IOM unsigned int RESERVED1 : 3; /*!< [7..5] Reserved for future use */ __IOM - uint32_t QSPI_PREFETCH_ENBLD_TRANS_BYTES : 8; /*!< [15..8] Programmable + unsigned int QSPI_PREFETCH_ENBLD_TRANS_BYTES : 8; /*!< [15..8] Programmable prefetch enabled AHB master transfer bytes. Assume this is used for icache and dma ahb master access in auto mode. */ - __IOM uint32_t RESERVED2 : 16; /*!< [31..16] Reserved for future use */ + __IOM unsigned int RESERVED2 : 16; /*!< [31..16] Reserved for future use */ } QSPI_BUS_MODE2_REG_b; }; union { - __IOM uint32_t QSPI_AES_SEC_KEY_FRM_KH_REG; /*!< (@ 0x0000012C) none */ + __IOM unsigned int QSPI_AES_SEC_KEY_FRM_KH_REG; /*!< (@ 0x0000012C) none */ struct { - __OM uint32_t START_LOADING_SEC_KEY_FRM_KH : 1; /*!< [0..0] Start Security key + __OM unsigned int START_LOADING_SEC_KEY_FRM_KH : 1; /*!< [0..0] Start Security key loading from KH. */ - __IM uint32_t LOADING_SEC_KEY_FRM_KH : 1; /*!< [1..1] Indicates security key loading + __IM unsigned int LOADING_SEC_KEY_FRM_KH : 1; /*!< [1..1] Indicates security key loading status from KH. */ - __IOM uint32_t SEC_KEY_READING_INTERVAL : 4; /*!< [5..2] Security key + __IOM unsigned int SEC_KEY_READING_INTERVAL : 4; /*!< [5..2] Security key reading interval */ - __IOM uint32_t RESERVED1 : 26; /*!< [31..6] Reserved for future use */ + __IOM unsigned int RESERVED1 : 26; /*!< [31..6] Reserved for future use */ } QSPI_AES_SEC_KEY_FRM_KH_REG_b; }; union { - __IOM uint32_t QSPI_AUTO_CONITNUE_FETCH_CTRL_REG; /*!< (@ 0x00000130) none */ + __IOM unsigned int QSPI_AUTO_CONITNUE_FETCH_CTRL_REG; /*!< (@ 0x00000130) none */ struct { - __IOM uint32_t CONTINUE_FETCH_WAIT_TIMEOUT_VALUE_FRM_REG : 12; /*!< [11..0] Maximum + __IOM unsigned int CONTINUE_FETCH_WAIT_TIMEOUT_VALUE_FRM_REG : 12; /*!< [11..0] Maximum Continue fetch wait time between two qspi auto reads. */ - __IOM uint32_t CONTINUE_FETCH_EN : 1; /*!< [12..12] Continue fetch feature + __IOM unsigned int CONTINUE_FETCH_EN : 1; /*!< [12..12] Continue fetch feature enable. */ - __IOM uint32_t RESERVED1 : 19; /*!< [31..13] Reserved for future use */ + __IOM unsigned int RESERVED1 : 19; /*!< [31..13] Reserved for future use */ } QSPI_AUTO_CONITNUE_FETCH_CTRL_REG_b; }; union { - __IOM uint32_t QSPI_AES_KEY1_0_3; /*!< (@ 0x00000134) QSPI_AES_KEY1_0_3 */ + __IOM unsigned int QSPI_AES_KEY1_0_3; /*!< (@ 0x00000134) QSPI_AES_KEY1_0_3 */ struct { - __IOM uint32_t QSPI_AES_KEY1_0_3 : 32; /*!< [31..0] To hold first 3-0 bytes of aes + __IOM unsigned int QSPI_AES_KEY1_0_3 : 32; /*!< [31..0] To hold first 3-0 bytes of aes key1 as 0 referred as lsb in the key */ } QSPI_AES_KEY1_0_3_b; }; union { - __IOM uint32_t QSPI_AES_KEY1_4_7; /*!< (@ 0x00000138) QSPI_AES_KEY1_4_7 */ + __IOM unsigned int QSPI_AES_KEY1_4_7; /*!< (@ 0x00000138) QSPI_AES_KEY1_4_7 */ struct { - __IOM uint32_t QSPI_AES_KEY1_4_7 : 32; /*!< [31..0] To hold first 7-4 bytes of aes + __IOM unsigned int QSPI_AES_KEY1_4_7 : 32; /*!< [31..0] To hold first 7-4 bytes of aes key1 as 0 referred as lsb */ } QSPI_AES_KEY1_4_7_b; }; union { - __IOM uint32_t QSPI_AES_KEY1_8_B; /*!< (@ 0x0000013C) QSPI_AES_KEY1_8_B */ + __IOM unsigned int QSPI_AES_KEY1_8_B; /*!< (@ 0x0000013C) QSPI_AES_KEY1_8_B */ struct { - __IOM uint32_t QSPI_AES_KEY1_8_B : 32; /*!< [31..0] To hold first 11-8 bytes of aes + __IOM unsigned int QSPI_AES_KEY1_8_B : 32; /*!< [31..0] To hold first 11-8 bytes of aes key1 as 0 referred as lsb */ } QSPI_AES_KEY1_8_B_b; }; union { - __IOM uint32_t QSPI_AES_KEY1_C_F; /*!< (@ 0x00000140) QSPI_AES_KEY1_C_F */ + __IOM unsigned int QSPI_AES_KEY1_C_F; /*!< (@ 0x00000140) QSPI_AES_KEY1_C_F */ struct { - __IOM uint32_t QSPI_AES_KEY1_C_F : 32; /*!< [31..0] To hold first 11-8 bytes of aes + __IOM unsigned int QSPI_AES_KEY1_C_F : 32; /*!< [31..0] To hold first 11-8 bytes of aes key1 as 0 referred as lsb */ } QSPI_AES_KEY1_C_F_b; }; - __IM uint32_t RESERVED7[4]; + __IM unsigned int RESERVED7[4]; union { - __IOM uint32_t QSPI_AES_KEY2_0_3; /*!< (@ 0x00000154) QSPI_AES_KEY2_0_3 */ + __IOM unsigned int QSPI_AES_KEY2_0_3; /*!< (@ 0x00000154) QSPI_AES_KEY2_0_3 */ struct { - __IOM uint32_t QSPI_AES_KEY2_0_3 : 32; /*!< [31..0] To hold first 3-0 bytes of aes + __IOM unsigned int QSPI_AES_KEY2_0_3 : 32; /*!< [31..0] To hold first 3-0 bytes of aes key2 as 0 referred as lsb in the key */ } QSPI_AES_KEY2_0_3_b; }; union { - __IOM uint32_t QSPI_AES_KEY2_4_7; /*!< (@ 0x00000158) QSPI_AES_KEY2_4_7 */ + __IOM unsigned int QSPI_AES_KEY2_4_7; /*!< (@ 0x00000158) QSPI_AES_KEY2_4_7 */ struct { - __IOM uint32_t QSPI_AES_KEY2_4_7 : 32; /*!< [31..0] To hold first 7-4 bytes of aes + __IOM unsigned int QSPI_AES_KEY2_4_7 : 32; /*!< [31..0] To hold first 7-4 bytes of aes key2 as 0 referred as lsb */ } QSPI_AES_KEY2_4_7_b; }; union { - __IOM uint32_t QSPI_AES_KEY2_8_B; /*!< (@ 0x0000015C) QSPI_AES_KEY2_8_B */ + __IOM unsigned int QSPI_AES_KEY2_8_B; /*!< (@ 0x0000015C) QSPI_AES_KEY2_8_B */ struct { - __IOM uint32_t QSPI_AES_KEY2_8_B : 32; /*!< [31..0] To hold first 11-8 bytes of aes + __IOM unsigned int QSPI_AES_KEY2_8_B : 32; /*!< [31..0] To hold first 11-8 bytes of aes key2 as 0 referred as lsb */ } QSPI_AES_KEY2_8_B_b; }; union { - __IOM uint32_t QSPI_AES_KEY2_C_F; /*!< (@ 0x00000160) QSPI_AES_KEY2_C_F */ + __IOM unsigned int QSPI_AES_KEY2_C_F; /*!< (@ 0x00000160) QSPI_AES_KEY2_C_F */ struct { - __IOM uint32_t QSPI_AES_KEY2_C_F : 32; /*!< [31..0] To hold first 15-12 bytes of aes + __IOM unsigned int QSPI_AES_KEY2_C_F : 32; /*!< [31..0] To hold first 15-12 bytes of aes key2 as 0 referred as lsb */ } QSPI_AES_KEY2_C_F_b; }; @@ -6641,46 +6641,46 @@ typedef struct { /*!< (@ 0x12000000) QSPI Structure */ typedef struct { /*!< (@ 0x45080000) CRC Structure */ union { - __IOM uint32_t CRC_GEN_CTRL_SET_REG; /*!< (@ 0x00000000) General control set + __IOM unsigned int CRC_GEN_CTRL_SET_REG; /*!< (@ 0x00000000) General control set register */ struct { - __IOM uint32_t SOFT_RST : 1; /*!< [0..0] Soft reset. This clears the FIFO and settles + __IOM unsigned int SOFT_RST : 1; /*!< [0..0] Soft reset. This clears the FIFO and settles all the state machines to their IDLE */ - __IOM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use. */ + __IOM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use. */ } CRC_GEN_CTRL_SET_REG_b; }; union { - __IOM uint32_t CRC_GEN_CTRL_RESET; /*!< (@ 0x00000004) General control reset + __IOM unsigned int CRC_GEN_CTRL_RESET; /*!< (@ 0x00000004) General control reset register */ struct { - __IOM uint32_t RESERVED1 : 32; /*!< [31..0] Reserved for future use. */ + __IOM unsigned int RESERVED1 : 32; /*!< [31..0] Reserved for future use. */ } CRC_GEN_CTRL_RESET_b; }; union { - __IM uint32_t CRC_GEN_STS; /*!< (@ 0x00000008) General status register */ + __IM unsigned int CRC_GEN_STS; /*!< (@ 0x00000008) General status register */ struct { - __IM uint32_t CALC_DONE : 1; /*!< [0..0] When the computation of final CRC + __IM unsigned int CALC_DONE : 1; /*!< [0..0] When the computation of final CRC with the data out of fifo, this will get set to 1 otherwise 0 */ - __IM uint32_t DIN_NUM_BYTES_DONE : 1; /*!< [1..1] When number of bytes requested for + __IM unsigned int DIN_NUM_BYTES_DONE : 1; /*!< [1..1] When number of bytes requested for computation of final CRC is read from fifo by internal FSM, this will get set to 1 otherwise 0. */ - __IM uint32_t RESERVED1 : 30; /*!< [31..2] Reserved for future use. */ + __IM unsigned int RESERVED1 : 30; /*!< [31..2] Reserved for future use. */ } CRC_GEN_STS_b; }; union { - __IOM uint32_t CRC_POLYNOMIAL; /*!< (@ 0x0000000C) This register holds the polynomial + __IOM unsigned int CRC_POLYNOMIAL; /*!< (@ 0x0000000C) This register holds the polynomial with which the final CRC is computed. */ struct { - __IOM uint32_t POLYNOMIAL : 32; /*!< [31..0] Polynomial register. This register holds + __IOM unsigned int POLYNOMIAL : 32; /*!< [31..0] Polynomial register. This register holds the polynomial with which the final CRC is computed.When write Polynomial will be updated.When read read polynomial. */ @@ -6688,11 +6688,11 @@ typedef struct { /*!< (@ 0x45080000) CRC Structure */ }; union { - __IOM uint32_t CRC_POLYNOMIAL_CTRL_SET; /*!< (@ 0x00000010) Polynomial + __IOM unsigned int CRC_POLYNOMIAL_CTRL_SET; /*!< (@ 0x00000010) Polynomial control set register */ struct { - __IOM uint32_t POLYNOMIAL_WIDTH_SET : 5; /*!< [4..0] Polynomial width set. Number of + __IOM unsigned int POLYNOMIAL_WIDTH_SET : 5; /*!< [4..0] Polynomial width set. Number of bits/width of the polynomial has to be written here for the computation of final CRC. If a new width has to be configured, @@ -6700,29 +6700,29 @@ typedef struct { /*!< (@ 0x45080000) CRC Structure */ writing 0x1f in polynomial_ctrl_reset register. When read, actual polynomial width is read. */ - __IOM uint32_t RESERVED1 : 27; /*!< [31..5] Reserved for future use. */ + __IOM unsigned int RESERVED1 : 27; /*!< [31..5] Reserved for future use. */ } CRC_POLYNOMIAL_CTRL_SET_b; }; union { - __IOM uint32_t CRC_POLYNOMIAL_CTRL_RESET; /*!< (@ 0x00000014) Polynomial + __IOM unsigned int CRC_POLYNOMIAL_CTRL_RESET; /*!< (@ 0x00000014) Polynomial control set register */ struct { - __IOM uint32_t POLYNOMIAL_WIDTH_SET : 5; /*!< [4..0] Polynomial width reset. If a new + __IOM unsigned int POLYNOMIAL_WIDTH_SET : 5; /*!< [4..0] Polynomial width reset. If a new width has to be configured, clear the existing length first by writing 0x1f. When read, actual polynomial width is read. */ - __IOM uint32_t RESERVED1 : 27; /*!< [31..5] Reserved for future use. */ + __IOM unsigned int RESERVED1 : 27; /*!< [31..5] Reserved for future use. */ } CRC_POLYNOMIAL_CTRL_RESET_b; }; union { - __IOM uint32_t CRC_LFSR_INIT_VAL; /*!< (@ 0x00000018) LFSR initial value */ + __IOM unsigned int CRC_LFSR_INIT_VAL; /*!< (@ 0x00000018) LFSR initial value */ struct { - __IOM uint32_t LFSR_INIT : 32; /*!< [31..0] This holds LFSR initialization value. + __IOM unsigned int LFSR_INIT : 32; /*!< [31..0] This holds LFSR initialization value. When ever LFSR needs to be initialized, this has to be updated with the init value and trigger init_lfsr in LFSR_INIT_CTRL_SET register. For @@ -6732,66 +6732,66 @@ typedef struct { /*!< (@ 0x45080000) CRC Structure */ }; union { - __IOM uint32_t CRC_LFSR_INIT_CTRL_SET; /*!< (@ 0x0000001C) LFSR state initialization + __IOM unsigned int CRC_LFSR_INIT_CTRL_SET; /*!< (@ 0x0000001C) LFSR state initialization control set register */ struct { - __IOM uint32_t CLEAR_LFSR : 1; /*!< [0..0] Clear LFSR state. When this is + __IOM unsigned int CLEAR_LFSR : 1; /*!< [0..0] Clear LFSR state. When this is set, LFSR state is cleared to 0 */ - __IOM uint32_t INIT_LFSR : 1; /*!< [1..1] Initialize LFSR state. When this + __IOM unsigned int INIT_LFSR : 1; /*!< [1..1] Initialize LFSR state. When this is set LFSR state will be initialized with LFSR_INIT_VAL/bit swapped LFSR_INIT_VAL in the next cycle */ - __IOM uint32_t USE_SWAPPED_INIT_VAL : 1; /*!< [2..2] Use bit swapped init value. If + __IOM unsigned int USE_SWAPPED_INIT_VAL : 1; /*!< [2..2] Use bit swapped init value. If this is set bit swapped version of LFSR init value will be loaded / initialized to LFSR state */ - __IOM uint32_t RESERVED1 : 29; /*!< [31..3] Reserved for future use. */ + __IOM unsigned int RESERVED1 : 29; /*!< [31..3] Reserved for future use. */ } CRC_LFSR_INIT_CTRL_SET_b; }; union { - __IOM uint32_t CRC_LFSR_INIT_CTRL_RESET; /*!< (@ 0x00000020) LFSR state initialization + __IOM unsigned int CRC_LFSR_INIT_CTRL_RESET; /*!< (@ 0x00000020) LFSR state initialization control reset register */ struct { - __IOM uint32_t RESERVED1 : 1; /*!< [0..0] Reserved for future use. */ - __IOM uint32_t RESERVED2 : 1; /*!< [1..1] Reserved for future use. */ - __IOM uint32_t USE_SWAPPED_INIT_VAL : 1; /*!< [2..2] Use bit swapped init value. If + __IOM unsigned int RESERVED1 : 1; /*!< [0..0] Reserved for future use. */ + __IOM unsigned int RESERVED2 : 1; /*!< [1..1] Reserved for future use. */ + __IOM unsigned int USE_SWAPPED_INIT_VAL : 1; /*!< [2..2] Use bit swapped init value. If this is set bit swapped version of LFSR init value will be loaded / initialized to LFSR state */ - __IOM uint32_t RESERVED3 : 29; /*!< [31..3] Reserved for future use. */ + __IOM unsigned int RESERVED3 : 29; /*!< [31..3] Reserved for future use. */ } CRC_LFSR_INIT_CTRL_RESET_b; }; union { - __OM uint32_t CRC_DIN_FIFO; /*!< (@ 0x00000024) Data input FIFO register */ + __OM unsigned int CRC_DIN_FIFO; /*!< (@ 0x00000024) Data input FIFO register */ struct { - __OM uint32_t DIN_FIFO : 32; /*!< [31..0] FIFO input port is mapped to this + __OM unsigned int DIN_FIFO : 32; /*!< [31..0] FIFO input port is mapped to this register. Data on which the final CRC has to be computed has to be loaded to this FIFO */ } CRC_DIN_FIFO_b; }; union { - __IOM uint32_t CRC_DIN_CTRL_SET; /*!< (@ 0x00000028) Input data control set + __IOM unsigned int CRC_DIN_CTRL_SET; /*!< (@ 0x00000028) Input data control set register */ struct { - __IOM uint32_t DIN_WIDTH_REG : 5; /*!< [4..0] Valid number of bits in the input data + __IOM unsigned int DIN_WIDTH_REG : 5; /*!< [4..0] Valid number of bits in the input data in din_width_from_reg set mode. Before writing a new value into this, din_ctrl_reset_reg has to be written with 0x1f to clear this field as these are set/clear bits. */ - __IOM uint32_t DIN_WIDTH_FROM_REG : 1; /*!< [5..5] Valid number of bits in the input + __IOM unsigned int DIN_WIDTH_FROM_REG : 1; /*!< [5..5] Valid number of bits in the input data. In default, number of valid bits in the input data is taken from ULI (uli_be). If this is set, whatever is the input size, only din_ctrl_reg[4:0] is taken as valid length/width for inout data. */ - __IOM uint32_t DIN_WIDTH_FROM_CNT : 1; /*!< [6..6] Valid number of bits in the input + __IOM unsigned int DIN_WIDTH_FROM_CNT : 1; /*!< [6..6] Valid number of bits in the input data. In default, number of valid bits in the input data is taken from ULI (uli_be). If this is set, a mix of ULI length @@ -6799,19 +6799,19 @@ typedef struct { /*!< (@ 0x45080000) CRC Structure */ valid bits (which ever is less that will be considered as valid bits). */ - __IOM uint32_t USE_SWAPPED_DIN : 1; /*!< [7..7] Use bit swapped input data. If this + __IOM unsigned int USE_SWAPPED_DIN : 1; /*!< [7..7] Use bit swapped input data. If this is set, input data will be swapped and filled in to FIFO. Whatever read out from FIFO will be directly fed to LFSR engine. */ - __IOM uint32_t RESET_FIFO_PTRS : 1; /*!< [8..8] Reset fifo pointer. This + __IOM unsigned int RESET_FIFO_PTRS : 1; /*!< [8..8] Reset fifo pointer. This clears the FIFO.When this is set, FIFO will be cleared. */ - __IOM uint32_t RESERVED1 : 15; /*!< [23..9] Reserved for future use. */ - __IOM uint32_t FIFO_AEMPTY_THRESHOLD : 4; /*!< [27..24] FIFO almost empty threshold + __IOM unsigned int RESERVED1 : 15; /*!< [23..9] Reserved for future use. */ + __IOM unsigned int FIFO_AEMPTY_THRESHOLD : 4; /*!< [27..24] FIFO almost empty threshold value. This has to be cleared by writing 0x0f000000 into din_ctrl_reset before updating any new value. */ - __IOM uint32_t FIFO_AFULL_THRESHOULD : 4; /*!< [31..28] FIFO almost full threshold + __IOM unsigned int FIFO_AFULL_THRESHOULD : 4; /*!< [31..28] FIFO almost full threshold value. This has to be cleared by writing 0xf0000000 into din_ctrl_reset before updating any new value */ @@ -6819,22 +6819,22 @@ typedef struct { /*!< (@ 0x45080000) CRC Structure */ }; union { - __IOM uint32_t CRC_DIN_CTRL_RESET_REG; /*!< (@ 0x0000002C) Input data + __IOM unsigned int CRC_DIN_CTRL_RESET_REG; /*!< (@ 0x0000002C) Input data control set register */ struct { - __IOM uint32_t DIN_WIDTH_REG : 5; /*!< [4..0] Valid number of bits in the input data + __IOM unsigned int DIN_WIDTH_REG : 5; /*!< [4..0] Valid number of bits in the input data in din_width_from_reg set mode. Before writing a new value into this, din_ctrl_reset_reg has to be written with 0x1f to clear this field as these are set/clear bits. */ - __IOM uint32_t DIN_WIDTH_FROM_REG : 1; /*!< [5..5] Valid number of bits in the input + __IOM unsigned int DIN_WIDTH_FROM_REG : 1; /*!< [5..5] Valid number of bits in the input data. In default, number of valid bits in the input data is taken from ULI (uli_be). If this is set, whatever is the input size, only din_ctrl_reg[4:0] is taken as valid length/width for inout data. */ - __IOM uint32_t DIN_WIDTH_FROM_CNT : 1; /*!< [6..6] Valid number of bits in the input + __IOM unsigned int DIN_WIDTH_FROM_CNT : 1; /*!< [6..6] Valid number of bits in the input data. In default, number of valid bits in the input data is taken from ULI (uli_be). If this is set, a mix of ULI length @@ -6842,17 +6842,17 @@ typedef struct { /*!< (@ 0x45080000) CRC Structure */ valid bits (which ever is less that will be considered as valid bits). */ - __IOM uint32_t USE_SWAPPED_DIN : 1; /*!< [7..7] Use bit swapped input data. If this + __IOM unsigned int USE_SWAPPED_DIN : 1; /*!< [7..7] Use bit swapped input data. If this is set input data will be swapped and filled in to FIFO. Whatever read out from FIFO will be directly fed to LFSR engine. */ - __IOM uint32_t RESERVED1 : 1; /*!< [8..8] Reserved for future use. */ - __IOM uint32_t RESERVED2 : 15; /*!< [23..9] Reserved for future use. */ - __IOM uint32_t FIFO_AEMPTY_THRESHOLD : 4; /*!< [27..24] FIFO almost empty threshold + __IOM unsigned int RESERVED1 : 1; /*!< [8..8] Reserved for future use. */ + __IOM unsigned int RESERVED2 : 15; /*!< [23..9] Reserved for future use. */ + __IOM unsigned int FIFO_AEMPTY_THRESHOLD : 4; /*!< [27..24] FIFO almost empty threshold value. This has to be cleared by writing 0x0f000000 into din_ctrl_reset before updating any new value. */ - __IOM uint32_t FIFO_AFULL_THRESHOULD : 4; /*!< [31..28] FIFO almost full threshold + __IOM unsigned int FIFO_AFULL_THRESHOULD : 4; /*!< [31..28] FIFO almost full threshold value. This has to be cleared by writing 0xf0000000 into din_ctrl_reset before updating any new value */ @@ -6860,31 +6860,31 @@ typedef struct { /*!< (@ 0x45080000) CRC Structure */ }; union { - __IOM uint32_t CRC_DIN_NUM_BYTES; /*!< (@ 0x00000030) Data input FIFO register */ + __IOM unsigned int CRC_DIN_NUM_BYTES; /*!< (@ 0x00000030) Data input FIFO register */ struct { - __IOM uint32_t DIN_NUM_BYTES : 32; /*!< [31..0] in out data number of bytes */ + __IOM unsigned int DIN_NUM_BYTES : 32; /*!< [31..0] in out data number of bytes */ } CRC_DIN_NUM_BYTES_b; }; union { - __IM uint32_t CRC_DIN_STS; /*!< (@ 0x00000034) Input data status register */ + __IM unsigned int CRC_DIN_STS; /*!< (@ 0x00000034) Input data status register */ struct { - __IM uint32_t FIFO_EMPTY : 1; /*!< [0..0] FIFO empty indication status */ - __IM uint32_t FIFO_AEMPTY : 1; /*!< [1..1] FIFO almost empty indication status. */ - __IM uint32_t FIFO_AFULL : 1; /*!< [2..2] FIFO almost full indication status */ - __IM uint32_t FIFO_FULL : 1; /*!< [3..3] FIFO full indication status */ - __IM uint32_t FIFO_OCC : 6; /*!< [9..4] FIFO occupancy */ - __IM uint32_t RESERVED1 : 22; /*!< [31..10] Reserved for future use. */ + __IM unsigned int FIFO_EMPTY : 1; /*!< [0..0] FIFO empty indication status */ + __IM unsigned int FIFO_AEMPTY : 1; /*!< [1..1] FIFO almost empty indication status. */ + __IM unsigned int FIFO_AFULL : 1; /*!< [2..2] FIFO almost full indication status */ + __IM unsigned int FIFO_FULL : 1; /*!< [3..3] FIFO full indication status */ + __IM unsigned int FIFO_OCC : 6; /*!< [9..4] FIFO occupancy */ + __IM unsigned int RESERVED1 : 22; /*!< [31..10] Reserved for future use. */ } CRC_DIN_STS_b; }; union { - __IOM uint32_t CRC_LFSR_STATE; /*!< (@ 0x00000038) LFSR state register */ + __IOM unsigned int CRC_LFSR_STATE; /*!< (@ 0x00000038) LFSR state register */ struct { - __IOM uint32_t LFSR_STATE : 32; /*!< [31..0] If LFSR dynamic loading is + __IOM unsigned int LFSR_STATE : 32; /*!< [31..0] If LFSR dynamic loading is required this can be used for writing the LFSR state directly. */ } CRC_LFSR_STATE_b; @@ -6906,135 +6906,135 @@ typedef struct { /*!< (@ 0x45080000) CRC Structure */ typedef struct { /*!< (@ 0x4600C000) EFUSE Structure */ union { - __IOM uint32_t EFUSE_DA_ADDR_REG; /*!< (@ 0x00000000) Direct Access Registers */ + __IOM unsigned int EFUSE_DA_ADDR_REG; /*!< (@ 0x00000000) Direct Access Registers */ struct { - __IOM uint32_t ADDR_BITS : 16; /*!< [15..0] These bits specifies the address to write + __IOM unsigned int ADDR_BITS : 16; /*!< [15..0] These bits specifies the address to write or read from EFUSE macro model */ - __IOM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ } EFUSE_DA_ADDR_REG_b; }; union { - __IOM uint32_t EFUSE_DA_CTRL_SET_REG; /*!< (@ 0x00000004) Direct Access Set + __IOM unsigned int EFUSE_DA_CTRL_SET_REG; /*!< (@ 0x00000004) Direct Access Set Registers */ struct { - __IOM uint32_t PGENB : 1; /*!< [0..0] Set Program enable */ - __IOM uint32_t CSB : 1; /*!< [1..1] Set Chip Enable */ - __IOM uint32_t STROBE : 1; /*!< [2..2] Set strobe enable */ - __IOM uint32_t LOAD : 1; /*!< [3..3] Set Load enable */ - __IOM uint32_t RESERVED1 : 12; /*!< [15..4] reserved1 */ - __IOM uint32_t RESERVED2 : 16; /*!< [31..16] reserved2 */ + __IOM unsigned int PGENB : 1; /*!< [0..0] Set Program enable */ + __IOM unsigned int CSB : 1; /*!< [1..1] Set Chip Enable */ + __IOM unsigned int STROBE : 1; /*!< [2..2] Set strobe enable */ + __IOM unsigned int LOAD : 1; /*!< [3..3] Set Load enable */ + __IOM unsigned int RESERVED1 : 12; /*!< [15..4] reserved1 */ + __IOM unsigned int RESERVED2 : 16; /*!< [31..16] reserved2 */ } EFUSE_DA_CTRL_SET_REG_b; }; union { - __IOM uint32_t EFUSE_DA_CTRL_CLEAR_REG; /*!< (@ 0x00000008) Direct Access + __IOM unsigned int EFUSE_DA_CTRL_CLEAR_REG; /*!< (@ 0x00000008) Direct Access Clear Registers */ struct { - __IOM uint32_t PGENB : 1; /*!< [0..0] Clear Program enable */ - __IOM uint32_t CSB : 1; /*!< [1..1] Clear Chip Enable */ - __IM uint32_t RESERVED1 : 1; /*!< [2..2] reserved1 */ - __IOM uint32_t LOAD : 1; /*!< [3..3] Clear Load enable */ - __IM uint32_t RESERVED2 : 12; /*!< [15..4] reserved2 */ - __IM uint32_t RESERVED3 : 16; /*!< [31..16] reserved3 */ + __IOM unsigned int PGENB : 1; /*!< [0..0] Clear Program enable */ + __IOM unsigned int CSB : 1; /*!< [1..1] Clear Chip Enable */ + __IM unsigned int RESERVED1 : 1; /*!< [2..2] reserved1 */ + __IOM unsigned int LOAD : 1; /*!< [3..3] Clear Load enable */ + __IM unsigned int RESERVED2 : 12; /*!< [15..4] reserved2 */ + __IM unsigned int RESERVED3 : 16; /*!< [31..16] reserved3 */ } EFUSE_DA_CTRL_CLEAR_REG_b; }; union { - __IOM uint32_t EFUSE_CTRL_REG; /*!< (@ 0x0000000C) Control Register */ + __IOM unsigned int EFUSE_CTRL_REG; /*!< (@ 0x0000000C) Control Register */ struct { - __IOM uint32_t EFUSE_ENABLE : 1; /*!< [0..0] This bit specifies whether the EFUSE + __IOM unsigned int EFUSE_ENABLE : 1; /*!< [0..0] This bit specifies whether the EFUSE module is enabled or not */ - __IOM uint32_t EFUSE_DIRECT_PATH_ENABLE : 1; /*!< [1..1] This bit specifies whether + __IOM unsigned int EFUSE_DIRECT_PATH_ENABLE : 1; /*!< [1..1] This bit specifies whether the EFUSE direct path is enabled or not for direct accessing of the EFUSE pins */ - __IOM uint32_t ENABLE_EFUSE_WRITE : 1; /*!< [2..2] Controls the switch on + __IOM unsigned int ENABLE_EFUSE_WRITE : 1; /*!< [2..2] Controls the switch on VDDIQ for eFuse read/write. */ - __IM uint32_t RESERVED1 : 13; /*!< [15..3] reserved1 */ - __IM uint32_t RESERVED2 : 16; /*!< [31..16] reserved2 */ + __IM unsigned int RESERVED1 : 13; /*!< [15..3] reserved1 */ + __IM unsigned int RESERVED2 : 16; /*!< [31..16] reserved2 */ } EFUSE_CTRL_REG_b; }; union { - __IOM uint32_t EFUSE_READ_ADDR_REG; /*!< (@ 0x00000010) Read address Register */ + __IOM unsigned int EFUSE_READ_ADDR_REG; /*!< (@ 0x00000010) Read address Register */ struct { - __IOM uint32_t READ_ADDR_BITS : 13; /*!< [12..0] These bits specifies the + __IOM unsigned int READ_ADDR_BITS : 13; /*!< [12..0] These bits specifies the address from which read operation has to be performed */ - __IM uint32_t RESERVED1 : 2; /*!< [14..13] reserved1 */ - __OM uint32_t DO_READ : 1; /*!< [15..15] Enables read FSM after EFUSE is + __IM unsigned int RESERVED1 : 2; /*!< [14..13] reserved1 */ + __OM unsigned int DO_READ : 1; /*!< [15..15] Enables read FSM after EFUSE is enabled */ - __IM uint32_t RESERVED2 : 16; /*!< [31..16] reserved2 */ + __IM unsigned int RESERVED2 : 16; /*!< [31..16] reserved2 */ } EFUSE_READ_ADDR_REG_b; }; union { - __IOM uint32_t EFUSE_READ_DATA_REG; /*!< (@ 0x00000014) Read address Register */ + __IOM unsigned int EFUSE_READ_DATA_REG; /*!< (@ 0x00000014) Read address Register */ struct { - __IOM uint32_t READ_DATA_BITS : 8; /*!< [7..0] These bits specifies the data bits + __IOM unsigned int READ_DATA_BITS : 8; /*!< [7..0] These bits specifies the data bits that are read from a given address specified in the EFUSE_READ_ADDRESS_REGISTER bits 8:0 */ - __IM uint32_t RESERVED1 : 7; /*!< [14..8] reserved1 */ - __IM uint32_t READ_FSM_DONE : 1; /*!< [15..15] Indicates read fsm is done. + __IM unsigned int RESERVED1 : 7; /*!< [14..8] reserved1 */ + __IM unsigned int READ_FSM_DONE : 1; /*!< [15..15] Indicates read fsm is done. After this read data is available in EFUSE_READ_DATA_REGISTER bits 7:0 */ - __IM uint32_t RESERVED2 : 16; /*!< [31..16] reserved2 */ + __IM unsigned int RESERVED2 : 16; /*!< [31..16] reserved2 */ } EFUSE_READ_DATA_REG_b; }; union { - __IM uint32_t EFUSE_STATUS_REG; /*!< (@ 0x00000018) Read address Register */ + __IM unsigned int EFUSE_STATUS_REG; /*!< (@ 0x00000018) Read address Register */ struct { - __IM uint32_t EFUSE_ENABLED : 1; /*!< [0..0] This bit specifies whether + __IM unsigned int EFUSE_ENABLED : 1; /*!< [0..0] This bit specifies whether the EFUSE is enabled or not */ - __IM uint32_t RESERVED1 : 1; /*!< [1..1] reserved1 */ - __IM uint32_t EFUSE_DOUT_SYNC : 8; /*!< [9..2] This bit specifies the 8-bit data + __IM unsigned int RESERVED1 : 1; /*!< [1..1] reserved1 */ + __IM unsigned int EFUSE_DOUT_SYNC : 8; /*!< [9..2] This bit specifies the 8-bit data read out from the EFUSE macro. This is synchronized with pclk */ - __IM uint32_t STROBE_CLEAR_BIT : 1; /*!< [10..10] This bit indicates STROBE signal + __IM unsigned int STROBE_CLEAR_BIT : 1; /*!< [10..10] This bit indicates STROBE signal goes low after strobe count value reached '0' */ - __IM uint32_t RESERVED2 : 5; /*!< [15..11] reserved2 */ - __IM uint32_t RESERVED3 : 16; /*!< [31..16] reserved3 */ + __IM unsigned int RESERVED2 : 5; /*!< [15..11] reserved2 */ + __IM unsigned int RESERVED3 : 16; /*!< [31..16] reserved3 */ } EFUSE_STATUS_REG_b; }; union { - __IOM uint32_t EFUSE_RD_TMNG_PARAM_REG; /*!< (@ 0x0000001C) none */ + __IOM unsigned int EFUSE_RD_TMNG_PARAM_REG; /*!< (@ 0x0000001C) none */ struct { - __IOM uint32_t TSUR_CS : 4; /*!< [3..0] CSB to STROBE setup time into read mode */ - __IOM uint32_t TSQ : 4; /*!< [7..4] Q7-Q0 access time from STROBE rising edge */ - __IOM uint32_t THRA : 4; /*!< [11..8] for 32x8 macro: A4 A0 to STROBE hold + __IOM unsigned int TSUR_CS : 4; /*!< [3..0] CSB to STROBE setup time into read mode */ + __IOM unsigned int TSQ : 4; /*!< [7..4] Q7-Q0 access time from STROBE rising edge */ + __IOM unsigned int THRA : 4; /*!< [11..8] for 32x8 macro: A4 A0 to STROBE hold time into Read mode 5122x8 macro: A8 A0 to STROBE hold time into Read mode */ - __IM uint32_t RESERVED1 : 4; /*!< [15..12] reserved1 */ - __IM uint32_t RESERVED2 : 16; /*!< [31..16] reserved2 */ + __IM unsigned int RESERVED1 : 4; /*!< [15..12] reserved1 */ + __IM unsigned int RESERVED2 : 16; /*!< [31..16] reserved2 */ } EFUSE_RD_TMNG_PARAM_REG_b; }; - __IM uint32_t RESERVED; + __IM unsigned int RESERVED; union { - __IOM uint32_t EFUSE_MEM_MAP_LENGTH_REG; /*!< (@ 0x00000024) none */ + __IOM unsigned int EFUSE_MEM_MAP_LENGTH_REG; /*!< (@ 0x00000024) none */ struct { - __IOM uint32_t EFUSE_MEM_MAP_LEN : 1; /*!< [0..0] 0: 8 bit read 1: 16 bit read */ - __IM uint32_t RESERVED1 : 15; /*!< [15..1] reserved1 */ - __IM uint32_t RESERVED2 : 16; /*!< [31..16] reserved2 */ + __IOM unsigned int EFUSE_MEM_MAP_LEN : 1; /*!< [0..0] 0: 8 bit read 1: 16 bit read */ + __IM unsigned int RESERVED1 : 15; /*!< [15..1] reserved1 */ + __IM unsigned int RESERVED2 : 16; /*!< [31..16] reserved2 */ } EFUSE_MEM_MAP_LENGTH_REG_b; }; union { __IOM - uint32_t EFUSE_READ_BLOCK_STARTING_LOCATION; /*!< (@ 0x00000028) Starting + unsigned int EFUSE_READ_BLOCK_STARTING_LOCATION; /*!< (@ 0x00000028) Starting address from which the read has to be blocked. Once the end address is written, it @@ -7042,62 +7042,62 @@ typedef struct { /*!< (@ 0x4600C000) EFUSE Structure */ on reset is given */ struct { - __IOM uint32_t EFUSE_READ_BLOCK_STARTING_LOCATION : 16; /*!< [15..0] Starting address + __IOM unsigned int EFUSE_READ_BLOCK_STARTING_LOCATION : 16; /*!< [15..0] Starting address from which the read has to be blocked. Once the end address is written, it cannot be changed till power on reset is given. */ - __IM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ } EFUSE_READ_BLOCK_STARTING_LOCATION_b; }; union { - __IOM uint32_t EFUSE_READ_BLOCK_END_LOCATION; /*!< (@ 0x0000002C) Starting address from + __IOM unsigned int EFUSE_READ_BLOCK_END_LOCATION; /*!< (@ 0x0000002C) Starting address from which the read has to be blocked. Once the end address is written, it cannot be changed till power on reset is given */ struct { - __IOM uint32_t EFUSE_READ_BLOCK_END_LOCATION : 16; /*!< [15..0] End address till + __IOM unsigned int EFUSE_READ_BLOCK_END_LOCATION : 16; /*!< [15..0] End address till which the read has to be blocked. Once the end address is written , it cannot be changed till power on reset is given. */ - __IM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ } EFUSE_READ_BLOCK_END_LOCATION_b; }; union { - __IOM uint32_t EFUSE_READ_BLOCK_ENABLE_REG; /*!< (@ 0x00000030) The Transmit Poll + __IOM unsigned int EFUSE_READ_BLOCK_ENABLE_REG; /*!< (@ 0x00000030) The Transmit Poll Demand register enables the Transmit DMA to check whether or not the current descriptor is owned by DMA */ struct { - __IOM uint32_t EFUSE_READ_BLOCK_ENABLE : 1; /*!< [0..0] Enable for blocking the read + __IOM unsigned int EFUSE_READ_BLOCK_ENABLE : 1; /*!< [0..0] Enable for blocking the read access from a programmable memory location */ - __IM uint32_t RESERVED1 : 15; /*!< [15..1] reserved1 */ - __IM uint32_t RESERVED2 : 16; /*!< [31..16] reserved2 */ + __IM unsigned int RESERVED1 : 15; /*!< [15..1] reserved1 */ + __IM unsigned int RESERVED2 : 16; /*!< [31..16] reserved2 */ } EFUSE_READ_BLOCK_ENABLE_REG_b; }; union { - __IOM uint32_t EFUSE_DA_CLR_STROBE_REG; /*!< (@ 0x00000034) none */ + __IOM unsigned int EFUSE_DA_CLR_STROBE_REG; /*!< (@ 0x00000034) none */ struct { - __IOM uint32_t EFUSE_STROBE_CLR_CNT : 9; /*!< [8..0] Strobe signal Clear count in + __IOM unsigned int EFUSE_STROBE_CLR_CNT : 9; /*!< [8..0] Strobe signal Clear count in direct access mode. value depends on APB clock frequency of eFuse controller */ - __IOM uint32_t EFUSE_STROBE_ENABLE : 1; /*!< [9..9] none */ - __IM uint32_t RESERVED1 : 6; /*!< [15..10] reserved1 */ - __IM uint32_t RESERVED2 : 16; /*!< [31..16] reserved2 */ + __IOM unsigned int EFUSE_STROBE_ENABLE : 1; /*!< [9..9] none */ + __IM unsigned int RESERVED1 : 6; /*!< [15..10] reserved1 */ + __IM unsigned int RESERVED2 : 16; /*!< [31..16] reserved2 */ } EFUSE_DA_CLR_STROBE_REG_b; }; } EFUSE_Type; /*!< Size = 56 (0x38) */ @@ -7117,192 +7117,192 @@ typedef struct { /*!< (@ 0x4600C000) EFUSE Structure */ typedef struct { /*!< (@ 0x47050000) I2S0 Structure */ union { - __IOM uint32_t I2S_IER; /*!< (@ 0x00000000) I2S Enable Register */ + __IOM unsigned int I2S_IER; /*!< (@ 0x00000000) I2S Enable Register */ struct { - __IOM uint32_t IEN : 1; /*!< [0..0] Inter Block Enable */ - __IOM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + __IOM unsigned int IEN : 1; /*!< [0..0] Inter Block Enable */ + __IOM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */ } I2S_IER_b; }; union { - __IOM uint32_t I2S_IRER; /*!< (@ 0x00000004) I2S Receiver Block Enable Register */ + __IOM unsigned int I2S_IRER; /*!< (@ 0x00000004) I2S Receiver Block Enable Register */ struct { - __IOM uint32_t RXEN : 1; /*!< [0..0] Receive Block Enable, Bit Overrides + __IOM unsigned int RXEN : 1; /*!< [0..0] Receive Block Enable, Bit Overrides any Individual Receive Channel Enables */ - __IOM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + __IOM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */ } I2S_IRER_b; }; union { - __IOM uint32_t I2S_ITER; /*!< (@ 0x00000008) Transmitter Block Enable */ + __IOM unsigned int I2S_ITER; /*!< (@ 0x00000008) Transmitter Block Enable */ struct { - __IOM uint32_t TXEN : 1; /*!< [0..0] Transmitter Block Enable, Bit Overrides any + __IOM unsigned int TXEN : 1; /*!< [0..0] Transmitter Block Enable, Bit Overrides any Individual Transmit Channel Enables */ - __IOM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + __IOM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */ } I2S_ITER_b; }; union { - __IOM uint32_t I2S_CER; /*!< (@ 0x0000000C) Clock Enable Register */ + __IOM unsigned int I2S_CER; /*!< (@ 0x0000000C) Clock Enable Register */ struct { - __IOM uint32_t CLKEN : 1; /*!< [0..0] Clock generation enable/disable */ - __IOM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + __IOM unsigned int CLKEN : 1; /*!< [0..0] Clock generation enable/disable */ + __IOM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */ } I2S_CER_b; }; union { - __IOM uint32_t I2S_CCR; /*!< (@ 0x00000010) Clock Configuration Register */ + __IOM unsigned int I2S_CCR; /*!< (@ 0x00000010) Clock Configuration Register */ struct { - __IOM uint32_t SCLKG : 3; /*!< [2..0] These bits are used to program the + __IOM unsigned int SCLKG : 3; /*!< [2..0] These bits are used to program the gating of sclk */ - __IOM uint32_t WSS : 2; /*!< [4..3] These bits are used to program the + __IOM unsigned int WSS : 2; /*!< [4..3] These bits are used to program the number of sclk cycles */ - __IOM uint32_t RESERVED1 : 27; /*!< [31..5] Reserved for future use */ + __IOM unsigned int RESERVED1 : 27; /*!< [31..5] Reserved for future use */ } I2S_CCR_b; }; union { - __OM uint32_t I2S_RXFFR; /*!< (@ 0x00000014) Receiver Block FIFO Reset Register */ + __OM unsigned int I2S_RXFFR; /*!< (@ 0x00000014) Receiver Block FIFO Reset Register */ struct { - __OM uint32_t RXFFR : 1; /*!< [0..0] Writing a 1 To This Register Flushes + __OM unsigned int RXFFR : 1; /*!< [0..0] Writing a 1 To This Register Flushes All The RX FIFO's Receiver Block Must be Disable Prior to Writing This Bit */ - __OM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + __OM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */ } I2S_RXFFR_b; }; union { - __OM uint32_t I2S_TXFFR; /*!< (@ 0x00000018) Transmitter Block FIFO Reset + __OM unsigned int I2S_TXFFR; /*!< (@ 0x00000018) Transmitter Block FIFO Reset Register */ struct { - __OM uint32_t TXFFR : 1; /*!< [0..0] Writing a 1 To This Register Flushes + __OM unsigned int TXFFR : 1; /*!< [0..0] Writing a 1 To This Register Flushes All The RX FIFO's Receiver Block Must be Disable Prior to Writing This Bit */ - __OM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + __OM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */ } I2S_TXFFR_b; }; - __IM uint32_t RESERVED; + __IM unsigned int RESERVED; __IOM I2S0_CHANNEL_CONFIG_Type CHANNEL_CONFIG[4]; /*!< (@ 0x00000020) [0..3] */ - __IM uint32_t RESERVED1[40]; + __IM unsigned int RESERVED1[40]; union { - __IM uint32_t I2S_RXDMA; /*!< (@ 0x000001C0) Receiver Block DMA Register */ + __IM unsigned int I2S_RXDMA; /*!< (@ 0x000001C0) Receiver Block DMA Register */ struct { - __IM uint32_t RXDMA : 32; /*!< [31..0] Used to cycle repeatedly through the enabled + __IM unsigned int RXDMA : 32; /*!< [31..0] Used to cycle repeatedly through the enabled receive channels Reading stereo data pairs */ } I2S_RXDMA_b; }; union { - __OM uint32_t I2S_RRXDMA; /*!< (@ 0x000001C4) Reset Receiver Block DMA Register */ + __OM unsigned int I2S_RRXDMA; /*!< (@ 0x000001C4) Reset Receiver Block DMA Register */ struct { - __OM uint32_t RRXDMA : 1; /*!< [0..0] Writing a 1 to this self-clearing + __OM unsigned int RRXDMA : 1; /*!< [0..0] Writing a 1 to this self-clearing register resets the RXDMA register */ - __OM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + __OM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */ } I2S_RRXDMA_b; }; union { - __OM uint32_t I2S_TXDMA; /*!< (@ 0x000001C8) Transmitter Block DMA Register */ + __OM unsigned int I2S_TXDMA; /*!< (@ 0x000001C8) Transmitter Block DMA Register */ struct { - __OM uint32_t TXDMA : 32; /*!< [31..0] Used to cycle repeatedly through + __OM unsigned int TXDMA : 32; /*!< [31..0] Used to cycle repeatedly through the enabled transmit channels allow to writing of stereo data pairs */ } I2S_TXDMA_b; }; union { - __OM uint32_t I2S_RTXDMA; /*!< (@ 0x000001CC) Reset Transmitter Block DMA + __OM unsigned int I2S_RTXDMA; /*!< (@ 0x000001CC) Reset Transmitter Block DMA Register */ struct { - __OM uint32_t RTXDMA : 1; /*!< [0..0] Writing a 1 to this self-clearing + __OM unsigned int RTXDMA : 1; /*!< [0..0] Writing a 1 to this self-clearing register resets the TXDMA register */ - __OM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved1 */ + __OM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved1 */ } I2S_RTXDMA_b; }; - __IM uint32_t RESERVED2[8]; + __IM unsigned int RESERVED2[8]; union { - __IM uint32_t I2S_COMP_PARAM_2; /*!< (@ 0x000001F0) Component Parameter 2 + __IM unsigned int I2S_COMP_PARAM_2; /*!< (@ 0x000001F0) Component Parameter 2 Register */ struct { - __IM uint32_t I2S_RX_WORDSIZE_0 : 3; /*!< [2..0] On Read returns the value + __IM unsigned int I2S_RX_WORDSIZE_0 : 3; /*!< [2..0] On Read returns the value of word size of receiver channel 0 */ - __IM uint32_t I2S_RX_WORDSIZE_1 : 3; /*!< [5..3] On Read returns the value + __IM unsigned int I2S_RX_WORDSIZE_1 : 3; /*!< [5..3] On Read returns the value of word size of receiver channel 1 */ - __IM uint32_t RESERVED1 : 1; /*!< [6..6] Reserved1 */ - __IM uint32_t I2S_RX_WORDSIZE_2 : 3; /*!< [9..7] On Read returns the value + __IM unsigned int RESERVED1 : 1; /*!< [6..6] Reserved1 */ + __IM unsigned int I2S_RX_WORDSIZE_2 : 3; /*!< [9..7] On Read returns the value of word size of receiver channel 2 */ - __IM uint32_t I2S_RX_WORDSIZE_3 : 3; /*!< [12..10] On Read returns the value of word + __IM unsigned int I2S_RX_WORDSIZE_3 : 3; /*!< [12..10] On Read returns the value of word size of receiver channel 3 */ - __IM uint32_t RESERVED2 : 19; /*!< [31..13] Reserved2 */ + __IM unsigned int RESERVED2 : 19; /*!< [31..13] Reserved2 */ } I2S_COMP_PARAM_2_b; }; union { - __IM uint32_t I2S_COMP_PARAM_1; /*!< (@ 0x000001F4) Component Parameter 1 + __IM unsigned int I2S_COMP_PARAM_1; /*!< (@ 0x000001F4) Component Parameter 1 Register */ struct { - __IM uint32_t APB_DATA_WIDTH : 2; /*!< [1..0] Width of APB data bus */ - __IM uint32_t I2S_FIFO_DEPTH_GLOBAL : 2; /*!< [3..2] Determines FIFO depth + __IM unsigned int APB_DATA_WIDTH : 2; /*!< [1..0] Width of APB data bus */ + __IM unsigned int I2S_FIFO_DEPTH_GLOBAL : 2; /*!< [3..2] Determines FIFO depth for all channels */ - __IM uint32_t I2S_FIFO_MODE_EN : 1; /*!< [4..4] Determines whether component act as + __IM unsigned int I2S_FIFO_MODE_EN : 1; /*!< [4..4] Determines whether component act as Master or Slave */ - __IM uint32_t I2S_TRANSMITTER_BLOCK : 1; /*!< [5..5] Shows the presence of + __IM unsigned int I2S_TRANSMITTER_BLOCK : 1; /*!< [5..5] Shows the presence of the transmitter block */ - __IM uint32_t I2S_RECEIVER_BLOCK : 1; /*!< [6..6] Shows the presence of + __IM unsigned int I2S_RECEIVER_BLOCK : 1; /*!< [6..6] Shows the presence of the receiver block */ - __IM uint32_t I2S_RX_CHANNELS : 2; /*!< [8..7] Returns the number of + __IM unsigned int I2S_RX_CHANNELS : 2; /*!< [8..7] Returns the number of receiver channels */ - __IM uint32_t I2S_TX_CHANNELS : 2; /*!< [10..9] Returns the number of + __IM unsigned int I2S_TX_CHANNELS : 2; /*!< [10..9] Returns the number of transmitter channels */ - __IM uint32_t RESERVED1 : 5; /*!< [15..11] Reserved1 */ - __IM uint32_t I2S_TX_WORDSIZE_0 : 3; /*!< [18..16] Returns the value of + __IM unsigned int RESERVED1 : 5; /*!< [15..11] Reserved1 */ + __IM unsigned int I2S_TX_WORDSIZE_0 : 3; /*!< [18..16] Returns the value of word size of transmitter channel 0 */ - __IM uint32_t I2S_TX_WORDSIZE_1 : 3; /*!< [21..19] Returns the value of + __IM unsigned int I2S_TX_WORDSIZE_1 : 3; /*!< [21..19] Returns the value of word size of transmitter channel 1 */ - __IM uint32_t I2S_TX_WORDSIZE_2 : 3; /*!< [24..22] Returns the value of + __IM unsigned int I2S_TX_WORDSIZE_2 : 3; /*!< [24..22] Returns the value of word size of transmitter channel 2 */ - __IM uint32_t I2S_TX_WORDSIZE_3 : 3; /*!< [27..25] Returns the value of + __IM unsigned int I2S_TX_WORDSIZE_3 : 3; /*!< [27..25] Returns the value of word size of transmitter channel 3 */ - __IM uint32_t RESERVED2 : 4; /*!< [31..28] Reserved2 */ + __IM unsigned int RESERVED2 : 4; /*!< [31..28] Reserved2 */ } I2S_COMP_PARAM_1_b; }; union { - __IM uint32_t I2S_COMP_VERSION_REG; /*!< (@ 0x000001F8) Component Version ID */ + __IM unsigned int I2S_COMP_VERSION_REG; /*!< (@ 0x000001F8) Component Version ID */ struct { - __IM uint32_t I2S_COMP_VERSION : 32; /*!< [31..0] Return the component + __IM unsigned int I2S_COMP_VERSION : 32; /*!< [31..0] Return the component version(1.02) */ } I2S_COMP_VERSION_REG_b; }; union { - __IM uint32_t I2S_COMP_TYPE_REG; /*!< (@ 0x000001FC) Component Type */ + __IM unsigned int I2S_COMP_TYPE_REG; /*!< (@ 0x000001FC) Component Type */ struct { - __IM uint32_t I2S_COMP_TYPE : 32; /*!< [31..0] Return the component type */ + __IM unsigned int I2S_COMP_TYPE : 32; /*!< [31..0] Return the component type */ } I2S_COMP_TYPE_REG_b; }; } I2S0_Type; /*!< Size = 512 (0x200) */ @@ -7322,138 +7322,138 @@ typedef struct { /*!< (@ 0x47050000) I2S0 Structure */ typedef struct { /*!< (@ 0x20480500) IID_AES Structure */ union { - __IOM uint32_t AES_KCR; /*!< (@ 0x00000000) AES Key Control register */ + __IOM unsigned int AES_KCR; /*!< (@ 0x00000000) AES Key Control register */ struct { - __IOM uint32_t AES_KEY_CHNG_REQ : 1; /*!< [0..0] Programming 1 clears the current key + __IOM unsigned int AES_KEY_CHNG_REQ : 1; /*!< [0..0] Programming 1 clears the current key and starts a request a for a new key Auto-reverts to 0 as soon as the request is accepted */ - __IOM uint32_t AES_KEY_SIZE : 1; /*!< [1..1] Size of the AES key 0: + __IOM unsigned int AES_KEY_SIZE : 1; /*!< [1..1] Size of the AES key 0: 128-bit 1: 256-bit */ - __IM uint32_t : 5; - __IOM uint32_t AES_KEY_SRC : 1; /*!< [7..7] Source of the AES key 0: + __IM unsigned int : 5; + __IOM unsigned int AES_KEY_SRC : 1; /*!< [7..7] Source of the AES key 0: Interface 1: Register */ - __IM uint32_t : 24; + __IM unsigned int : 24; } AES_KCR_b; }; union { - __IOM uint32_t AES_MODE_REG; /*!< (@ 0x00000004) AES Mode register */ + __IOM unsigned int AES_MODE_REG; /*!< (@ 0x00000004) AES Mode register */ struct { - __IOM uint32_t AES_MODE : 8; /*!< [7..0] The AES Mode register defines + __IOM unsigned int AES_MODE : 8; /*!< [7..0] The AES Mode register defines which mode of AES is used. */ - __IM uint32_t : 24; + __IM unsigned int : 24; } AES_MODE_REG_b; }; union { - __IOM uint32_t AES_ACT_REG; /*!< (@ 0x00000008) AES Action register */ + __IOM unsigned int AES_ACT_REG; /*!< (@ 0x00000008) AES Action register */ struct { - __IOM uint32_t AES_ACTION : 2; /*!< [1..0] The AES Mode register defines + __IOM unsigned int AES_ACTION : 2; /*!< [1..0] The AES Mode register defines which mode of AES is used. */ - __IM uint32_t : 30; + __IM unsigned int : 30; } AES_ACT_REG_b; }; - __IM uint32_t RESERVED[5]; + __IM unsigned int RESERVED[5]; union { - __IM uint32_t AES_SR_REG; /*!< (@ 0x00000020) AES Status register */ + __IM unsigned int AES_SR_REG; /*!< (@ 0x00000020) AES Status register */ struct { - __IM uint32_t AES_BUSY : 1; /*!< [0..0] Indicates that the AES core is + __IM unsigned int AES_BUSY : 1; /*!< [0..0] Indicates that the AES core is processing data */ - __IM uint32_t : 1; - __IM uint32_t AES_CLEAR_DONE : 1; /*!< [2..2] Indicates that the Clear + __IM unsigned int : 1; + __IM unsigned int AES_CLEAR_DONE : 1; /*!< [2..2] Indicates that the Clear action is finished */ - __IM uint32_t AES_KEY_PRESENT : 1; /*!< [3..3] Indicates that the Clear + __IM unsigned int AES_KEY_PRESENT : 1; /*!< [3..3] Indicates that the Clear action is finished */ - __IM uint32_t : 1; - __IM uint32_t AES_KEY_REQ : 1; /*!< [5..5] Indicates that a key must be + __IM unsigned int : 1; + __IM unsigned int AES_KEY_REQ : 1; /*!< [5..5] Indicates that a key must be provided */ - __IM uint32_t AES_DATA_REQ : 1; /*!< [6..6] Indicates that data must be + __IM unsigned int AES_DATA_REQ : 1; /*!< [6..6] Indicates that data must be provided */ - __IM uint32_t AES_DATA_AV : 1; /*!< [7..7] Indicates that data is available */ - __IM uint32_t : 24; + __IM unsigned int AES_DATA_AV : 1; /*!< [7..7] Indicates that data is available */ + __IM unsigned int : 24; } AES_SR_REG_b; }; - __IM uint32_t RESERVED1[7]; + __IM unsigned int RESERVED1[7]; union { - __OM uint32_t AES_KEY_REG; /*!< (@ 0x00000040) The AES Key register is used + __OM unsigned int AES_KEY_REG; /*!< (@ 0x00000040) The AES Key register is used to program a key into the AES module. */ struct { - __OM uint32_t AES_KEY : 32; /*!< [31..0] 4 writes of 32 bits make up the 128-bit key + __OM unsigned int AES_KEY : 32; /*!< [31..0] 4 writes of 32 bits make up the 128-bit key for AES, 8 writes make up the 256-bit key */ } AES_KEY_REG_b; }; union { - __OM uint32_t AES_DIN_REG; /*!< (@ 0x00000044) AES Data In register */ + __OM unsigned int AES_DIN_REG; /*!< (@ 0x00000044) AES Data In register */ struct { - __OM uint32_t AES_DIN : 32; /*!< [31..0] Data for encoding or decoding, 4 writes of + __OM unsigned int AES_DIN : 32; /*!< [31..0] Data for encoding or decoding, 4 writes of 32 bits make up a 128-bit data word */ } AES_DIN_REG_b; }; union { - __IM uint32_t AES_DOUT_REG; /*!< (@ 0x00000048) AES Data out register */ + __IM unsigned int AES_DOUT_REG; /*!< (@ 0x00000048) AES Data out register */ struct { - __IM uint32_t AES_DOUT : 32; /*!< [31..0] Result from encoding or decoding, 4 reads + __IM unsigned int AES_DOUT : 32; /*!< [31..0] Result from encoding or decoding, 4 reads of 32 bits make up a 128-bit data word */ } AES_DOUT_REG_b; }; - __IM uint32_t RESERVED2[36]; + __IM unsigned int RESERVED2[36]; union { - __OM uint32_t AES_IF_SR_C_REG; /*!< (@ 0x000000DC) AES Interface Status + __OM unsigned int AES_IF_SR_C_REG; /*!< (@ 0x000000DC) AES Interface Status Clear register */ struct { - __OM uint32_t IFB_ERROR : 1; /*!< [0..0] Clears the if_error bit */ - __IM uint32_t : 31; + __OM unsigned int IFB_ERROR : 1; /*!< [0..0] Clears the if_error bit */ + __IM unsigned int : 31; } AES_IF_SR_C_REG_b; }; union { - __IM uint32_t AES_IF_SR_REG; /*!< (@ 0x000000E0) AES Interface Status register */ + __IM unsigned int AES_IF_SR_REG; /*!< (@ 0x000000E0) AES Interface Status register */ struct { - __IM uint32_t IF_ERROR : 1; /*!< [0..0] Indicates that an interface error + __IM unsigned int IF_ERROR : 1; /*!< [0..0] Indicates that an interface error has occurred */ - __IM uint32_t : 31; + __IM unsigned int : 31; } AES_IF_SR_REG_b; }; union { - __IOM uint32_t AES_TEST_REG; /*!< (@ 0x000000E4) AES Test register */ + __IOM unsigned int AES_TEST_REG; /*!< (@ 0x000000E4) AES Test register */ struct { - __IOM uint32_t AES_BIST_ENABLE : 1; /*!< [0..0] Isolates the iid_aes + __IOM unsigned int AES_BIST_ENABLE : 1; /*!< [0..0] Isolates the iid_aes module and runs a BIST */ - __IM uint32_t : 3; - __IOM uint32_t AES_BIST_RUNNING : 1; /*!< [4..4] BIST is in progress or + __IM unsigned int : 3; + __IOM unsigned int AES_BIST_RUNNING : 1; /*!< [4..4] BIST is in progress or finishing up */ - __IOM uint32_t AES_BIST_ACTIVE : 1; /*!< [5..5] Indicates that the BIST is + __IOM unsigned int AES_BIST_ACTIVE : 1; /*!< [5..5] Indicates that the BIST is running */ - __IOM uint32_t AES_BIST_OK : 1; /*!< [6..6] Indicates that the BIST has passed */ - __IOM uint32_t AES_BIST_ERROR : 1; /*!< [7..7] Indicates that the BIST has + __IOM unsigned int AES_BIST_OK : 1; /*!< [6..6] Indicates that the BIST has passed */ + __IOM unsigned int AES_BIST_ERROR : 1; /*!< [7..7] Indicates that the BIST has failed */ - __IM uint32_t : 24; + __IM unsigned int : 24; } AES_TEST_REG_b; }; - __IM uint32_t RESERVED3[6]; + __IM unsigned int RESERVED3[6]; union { - __IM uint32_t AES_VER_REG; /*!< (@ 0x00000100) AES Version register */ + __IM unsigned int AES_VER_REG; /*!< (@ 0x00000100) AES Version register */ struct { - __IM uint32_t AES_VERSION : 32; /*!< [31..0] Version of iid_aes */ + __IM unsigned int AES_VERSION : 32; /*!< [31..0] Version of iid_aes */ } AES_VER_REG_b; }; } IID_AES_Type; /*!< Size = 260 (0x104) */ @@ -7473,182 +7473,182 @@ typedef struct { /*!< (@ 0x20480500) IID_AES Structure */ typedef struct { /*!< (@ 0x20480600) IID_QK Structure */ union { - __OM uint32_t QK_CR_REG; /*!< (@ 0x00000000) Quiddikey Control register.The + __OM unsigned int QK_CR_REG; /*!< (@ 0x00000000) Quiddikey Control register.The Quiddikey Control register defines which command must be executed next. */ struct { - __OM uint32_t QK_ZEROIZE : 1; /*!< [0..0] Begin Zeroize operation and go + __OM unsigned int QK_ZEROIZE : 1; /*!< [0..0] Begin Zeroize operation and go to Error state */ - __OM uint32_t QK_ENROLL : 1; /*!< [1..1] Begin Enroll operation */ - __OM uint32_t QK_START : 1; /*!< [2..2] Begin Start operation */ - __OM uint32_t QK_SET_IK : 1; /*!< [3..3] Begin Set Intrinsic Key operation */ - __OM uint32_t QK_SET_UK : 1; /*!< [4..4] Begin Set User Key operation */ - __OM uint32_t QK_SET_XK : 1; /*!< [5..5] Begin Set External Key operation */ - __OM uint32_t QK_GET_KEY : 1; /*!< [6..6] Begin Get Key operation */ - __IM uint32_t : 25; + __OM unsigned int QK_ENROLL : 1; /*!< [1..1] Begin Enroll operation */ + __OM unsigned int QK_START : 1; /*!< [2..2] Begin Start operation */ + __OM unsigned int QK_SET_IK : 1; /*!< [3..3] Begin Set Intrinsic Key operation */ + __OM unsigned int QK_SET_UK : 1; /*!< [4..4] Begin Set User Key operation */ + __OM unsigned int QK_SET_XK : 1; /*!< [5..5] Begin Set External Key operation */ + __OM unsigned int QK_GET_KEY : 1; /*!< [6..6] Begin Get Key operation */ + __IM unsigned int : 25; } QK_CR_REG_b; }; union { - __IOM uint32_t QK_KIDX_REG; /*!< (@ 0x00000004) The Quiddikey Key Index register + __IOM unsigned int QK_KIDX_REG; /*!< (@ 0x00000004) The Quiddikey Key Index register defines the key index for the next set_key command */ struct { - __IOM uint32_t QK_KEY_INDEX : 4; /*!< [3..0] Key index for Set Key operations */ - __IM uint32_t : 28; + __IOM unsigned int QK_KEY_INDEX : 4; /*!< [3..0] Key index for Set Key operations */ + __IM unsigned int : 28; } QK_KIDX_REG_b; }; union { - __IOM uint32_t QK_KSZ_REG; /*!< (@ 0x00000008) Quiddikey Key Size register */ + __IOM unsigned int QK_KSZ_REG; /*!< (@ 0x00000008) Quiddikey Key Size register */ struct { - __IOM uint32_t QK_KEY_SIZE : 6; /*!< [5..0] Key size for Set Key operations */ - __IM uint32_t : 26; + __IOM unsigned int QK_KEY_SIZE : 6; /*!< [5..0] Key size for Set Key operations */ + __IM unsigned int : 26; } QK_KSZ_REG_b; }; union { - __IOM uint32_t QK_KT_REG; /*!< (@ 0x0000000C) Quiddikey Key Size register */ + __IOM unsigned int QK_KT_REG; /*!< (@ 0x0000000C) Quiddikey Key Size register */ struct { - __IOM uint32_t QK_KEY_TARGET : 1; /*!< [0..0] Target of reconstructed key */ - __IM uint32_t : 31; + __IOM unsigned int QK_KEY_TARGET : 1; /*!< [0..0] Target of reconstructed key */ + __IM unsigned int : 31; } QK_KT_REG_b; }; - __IM uint32_t RESERVED[4]; + __IM unsigned int RESERVED[4]; union { - __IM uint32_t QK_SR_REG; /*!< (@ 0x00000020) Quiddikey Status register */ + __IM unsigned int QK_SR_REG; /*!< (@ 0x00000020) Quiddikey Status register */ struct { - __IM uint32_t QK_BUSY : 1; /*!< [0..0] Indicates that operation is in progress */ - __IM uint32_t QK_OK : 1; /*!< [1..1] Last operation was successful */ - __IM uint32_t QK_ERROR : 1; /*!< [2..2] Quiddikey is in the Error state + __IM unsigned int QK_BUSY : 1; /*!< [0..0] Indicates that operation is in progress */ + __IM unsigned int QK_OK : 1; /*!< [1..1] Last operation was successful */ + __IM unsigned int QK_ERROR : 1; /*!< [2..2] Quiddikey is in the Error state and no operations can be performed */ - __IM uint32_t QK_XO_AV : 1; /*!< [3..3] Next part of XKPD is available */ - __IM uint32_t QK_KI_REQ : 1; /*!< [4..4] Request for next part of key */ - __IM uint32_t QK_KO_AV : 1; /*!< [5..5] Next part of key is available */ - __IM uint32_t QK_CI_REQ : 1; /*!< [6..6] Request for next part of AC/KC */ - __IM uint32_t QK_CO_AV : 1; /*!< [7..7] Next part of AC/KC is available */ - __IM uint32_t : 24; + __IM unsigned int QK_XO_AV : 1; /*!< [3..3] Next part of XKPD is available */ + __IM unsigned int QK_KI_REQ : 1; /*!< [4..4] Request for next part of key */ + __IM unsigned int QK_KO_AV : 1; /*!< [5..5] Next part of key is available */ + __IM unsigned int QK_CI_REQ : 1; /*!< [6..6] Request for next part of AC/KC */ + __IM unsigned int QK_CO_AV : 1; /*!< [7..7] Next part of AC/KC is available */ + __IM unsigned int : 24; } QK_SR_REG_b; }; - __IM uint32_t RESERVED1; + __IM unsigned int RESERVED1; union { - __IM uint32_t QK_AR_REG; /*!< (@ 0x00000028) Quiddikey allow register */ + __IM unsigned int QK_AR_REG; /*!< (@ 0x00000028) Quiddikey allow register */ struct { - __IM uint32_t QK_ALLOW_ENROLL : 1; /*!< [0..0] Enroll operation is allowed */ - __IM uint32_t QK_ALLOW_START : 1; /*!< [1..1] Start operation is allowed */ - __IM uint32_t QK_ALLOW_SET_KEY : 1; /*!< [2..2] Set Key operations are allowed */ - __IM uint32_t QK_ALLOW_GET_KEY : 1; /*!< [3..3] Get Key operation is allowed */ - __IM uint32_t : 3; - __IM uint32_t QK_ALLOW_BIST : 1; /*!< [7..7] BIST is allowed to be started */ - __IM uint32_t : 24; + __IM unsigned int QK_ALLOW_ENROLL : 1; /*!< [0..0] Enroll operation is allowed */ + __IM unsigned int QK_ALLOW_START : 1; /*!< [1..1] Start operation is allowed */ + __IM unsigned int QK_ALLOW_SET_KEY : 1; /*!< [2..2] Set Key operations are allowed */ + __IM unsigned int QK_ALLOW_GET_KEY : 1; /*!< [3..3] Get Key operation is allowed */ + __IM unsigned int : 3; + __IM unsigned int QK_ALLOW_BIST : 1; /*!< [7..7] BIST is allowed to be started */ + __IM unsigned int : 24; } QK_AR_REG_b; }; - __IM uint32_t RESERVED2[5]; + __IM unsigned int RESERVED2[5]; union { - __IOM uint32_t QK_KI_REG; /*!< (@ 0x00000040) Quiddikey Key Input register */ + __IOM unsigned int QK_KI_REG; /*!< (@ 0x00000040) Quiddikey Key Input register */ struct { - __IOM uint32_t QK_KI : 32; /*!< [31..0] Key input data */ + __IOM unsigned int QK_KI : 32; /*!< [31..0] Key input data */ } QK_KI_REG_b; }; union { - __IOM uint32_t QK_CI_REG; /*!< (@ 0x00000044) Quiddikey Code Input register */ + __IOM unsigned int QK_CI_REG; /*!< (@ 0x00000044) Quiddikey Code Input register */ struct { - __IOM uint32_t QK_CI : 32; /*!< [31..0] AC/KC input data */ + __IOM unsigned int QK_CI : 32; /*!< [31..0] AC/KC input data */ } QK_CI_REG_b; }; union { - __IM uint32_t QK_CO_REG; /*!< (@ 0x00000048) Quiddikey Code Output register */ + __IM unsigned int QK_CO_REG; /*!< (@ 0x00000048) Quiddikey Code Output register */ struct { - __IM uint32_t QK_CO : 32; /*!< [31..0] AC/KC output data */ + __IM unsigned int QK_CO : 32; /*!< [31..0] AC/KC output data */ } QK_CO_REG_b; }; union { - __IM uint32_t QK_XO_REG; /*!< (@ 0x0000004C) Quiddikey XKPD Output register */ + __IM unsigned int QK_XO_REG; /*!< (@ 0x0000004C) Quiddikey XKPD Output register */ struct { - __IM uint32_t QK_XO : 32; /*!< [31..0] XKPD output data */ + __IM unsigned int QK_XO : 32; /*!< [31..0] XKPD output data */ } QK_XO_REG_b; }; - __IM uint32_t RESERVED3[4]; + __IM unsigned int RESERVED3[4]; union { - __IM uint32_t QK_KO_IDX_REG; /*!< (@ 0x00000060) Quiddikey Key Output Index + __IM unsigned int QK_KO_IDX_REG; /*!< (@ 0x00000060) Quiddikey Key Output Index register */ struct { - __IM uint32_t qk_ko_index : 4; /*!< [3..0] Key index for the key that is currently + __IM unsigned int qk_ko_index : 4; /*!< [3..0] Key index for the key that is currently output via the Key Output register */ - __IM uint32_t : 28; + __IM unsigned int : 28; } QK_KO_IDX_REG_b; }; union { - __IM uint32_t QK_KO_REG; /*!< (@ 0x00000064) Quiddikey Code Output register */ + __IM unsigned int QK_KO_REG; /*!< (@ 0x00000064) Quiddikey Code Output register */ struct { - __IM uint32_t QK_KO : 32; /*!< [31..0] Key output data */ + __IM unsigned int QK_KO : 32; /*!< [31..0] Key output data */ } QK_KO_REG_b; }; - __IM uint32_t RESERVED4[29]; + __IM unsigned int RESERVED4[29]; union { - __IM uint32_t QK_IF_SR_C_REG; /*!< (@ 0x000000DC) Quiddikey Interface Status + __IM unsigned int QK_IF_SR_C_REG; /*!< (@ 0x000000DC) Quiddikey Interface Status register */ struct { - __IM uint32_t IF_ERROR : 1; /*!< [0..0] Clears the if_error bit */ - __IM uint32_t : 31; + __IM unsigned int IF_ERROR : 1; /*!< [0..0] Clears the if_error bit */ + __IM unsigned int : 31; } QK_IF_SR_C_REG_b; }; union { - __IM uint32_t QK_IF_SR_REG; /*!< (@ 0x000000E0) Quiddikey Interface Status + __IM unsigned int QK_IF_SR_REG; /*!< (@ 0x000000E0) Quiddikey Interface Status register */ struct { - __IM uint32_t IF_ERROR : 1; /*!< [0..0] Indicates that an interface error + __IM unsigned int IF_ERROR : 1; /*!< [0..0] Indicates that an interface error has occurred */ - __IM uint32_t : 31; + __IM unsigned int : 31; } QK_IF_SR_REG_b; }; union { - __IOM uint32_t QK_TEST_REG; /*!< (@ 0x000000E4) QK Test register */ + __IOM unsigned int QK_TEST_REG; /*!< (@ 0x000000E4) QK Test register */ struct { - __IOM uint32_t QK_BIST_ENABLE : 1; /*!< [0..0] Isolates the iid_quiddikey + __IOM unsigned int QK_BIST_ENABLE : 1; /*!< [0..0] Isolates the iid_quiddikey module and runs a BIST */ - __IM uint32_t : 3; - __IOM uint32_t QK_BIST_RUNNING : 1; /*!< [4..4] BIST is in progress or + __IM unsigned int : 3; + __IOM unsigned int QK_BIST_RUNNING : 1; /*!< [4..4] BIST is in progress or finishing up */ - __IOM uint32_t QK_BIST_ACTIVE : 1; /*!< [5..5] Indicates that the BIST is + __IOM unsigned int QK_BIST_ACTIVE : 1; /*!< [5..5] Indicates that the BIST is running */ - __IOM uint32_t QK_BIST_OK : 1; /*!< [6..6] Indicates that the BIST has passed */ - __IOM uint32_t QK_BIST_ERROR : 1; /*!< [7..7] Indicates that the BIST has failed */ - __IM uint32_t : 24; + __IOM unsigned int QK_BIST_OK : 1; /*!< [6..6] Indicates that the BIST has passed */ + __IOM unsigned int QK_BIST_ERROR : 1; /*!< [7..7] Indicates that the BIST has failed */ + __IM unsigned int : 24; } QK_TEST_REG_b; }; - __IM uint32_t RESERVED5[6]; + __IM unsigned int RESERVED5[6]; union { - __IM uint32_t QK_VER_REG; /*!< (@ 0x00000100) QK Version register */ + __IM unsigned int QK_VER_REG; /*!< (@ 0x00000100) QK Version register */ struct { - __IM uint32_t QK_VERSION : 32; /*!< [31..0] Version of iid_qk */ + __IM unsigned int QK_VERSION : 32; /*!< [31..0] Version of iid_qk */ } QK_VER_REG_b; }; } IID_QK_Type; /*!< Size = 260 (0x104) */ @@ -7667,144 +7667,144 @@ typedef struct { /*!< (@ 0x20480600) IID_QK Structure */ typedef struct { /*!< (@ 0x20480400) IID_RPINE Structure */ union { - __IOM uint32_t IID_BIST_CTRL_REG; /*!< (@ 0x00000000) Quiddikey Control register.The + __IOM unsigned int IID_BIST_CTRL_REG; /*!< (@ 0x00000000) Quiddikey Control register.The Quiddikey Control register defines which command must be executed next. */ struct { - __IOM uint32_t QK_BIST_ENABLE : 1; /*!< [0..0] none */ - __IOM uint32_t AES_BIST_ENABLE : 1; /*!< [1..1] none */ - __IOM uint32_t KH_BIST_ENABLE : 1; /*!< [2..2] none */ - __IM uint32_t : 29; + __IOM unsigned int QK_BIST_ENABLE : 1; /*!< [0..0] none */ + __IOM unsigned int AES_BIST_ENABLE : 1; /*!< [1..1] none */ + __IOM unsigned int KH_BIST_ENABLE : 1; /*!< [2..2] none */ + __IM unsigned int : 29; } IID_BIST_CTRL_REG_b; }; union { - __IOM uint32_t IID_BIST_STATUS_REG; /*!< (@ 0x00000004) none */ + __IOM unsigned int IID_BIST_STATUS_REG; /*!< (@ 0x00000004) none */ struct { - __IOM uint32_t QK_BIST_ACTIVE : 1; /*!< [0..0] none */ - __IOM uint32_t QK_BIST_ERROR : 1; /*!< [1..1] Indicates that the BIST has failed */ - __IOM uint32_t QK_BIST_OK : 1; /*!< [2..2] Indicates that the BIST has passed */ - __IOM uint32_t QK_BIST_RUNNING : 1; /*!< [3..3] Indicates that the BIST is + __IOM unsigned int QK_BIST_ACTIVE : 1; /*!< [0..0] none */ + __IOM unsigned int QK_BIST_ERROR : 1; /*!< [1..1] Indicates that the BIST has failed */ + __IOM unsigned int QK_BIST_OK : 1; /*!< [2..2] Indicates that the BIST has passed */ + __IOM unsigned int QK_BIST_RUNNING : 1; /*!< [3..3] Indicates that the BIST is running */ - __IOM uint32_t AES_BIST_ACTIVE : 1; /*!< [4..4] none */ - __IOM uint32_t AES_BIST_ERROR : 1; /*!< [5..5] none */ - __IOM uint32_t AES_BIST_OK : 1; /*!< [6..6] Indicates that the BIST has passed */ - __IOM uint32_t AES_BIST_RUNNING : 1; /*!< [7..7] Indicates that the BIST + __IOM unsigned int AES_BIST_ACTIVE : 1; /*!< [4..4] none */ + __IOM unsigned int AES_BIST_ERROR : 1; /*!< [5..5] none */ + __IOM unsigned int AES_BIST_OK : 1; /*!< [6..6] Indicates that the BIST has passed */ + __IOM unsigned int AES_BIST_RUNNING : 1; /*!< [7..7] Indicates that the BIST is running */ - __IOM uint32_t KH_BIST_STATUS : 1; /*!< [8..8] none */ - __IM uint32_t : 23; + __IOM unsigned int KH_BIST_STATUS : 1; /*!< [8..8] none */ + __IM unsigned int : 23; } IID_BIST_STATUS_REG_b; }; union { - __IOM uint32_t IID_CTRL_REG; /*!< (@ 0x00000008) none */ + __IOM unsigned int IID_CTRL_REG; /*!< (@ 0x00000008) none */ struct { - __IOM uint32_t AES_MAX_KEY_SIZE : 1; /*!< [0..0] 1 256 bit key, 0 128 bit key */ - __IOM uint32_t SOURCE_KEY_KH : 1; /*!< [1..1] When set KH will source the key to AES + __IOM unsigned int AES_MAX_KEY_SIZE : 1; /*!< [0..0] 1 256 bit key, 0 128 bit key */ + __IOM unsigned int SOURCE_KEY_KH : 1; /*!< [1..1] When set KH will source the key to AES engine. When this is not QK key output is connected to AES key input */ - __IOM uint32_t LATCH_KEY_KH : 1; /*!< [2..2] When set KH will latch the key given by + __IOM unsigned int LATCH_KEY_KH : 1; /*!< [2..2] When set KH will latch the key given by QK. When this is not QK key output is connected to AES key input */ - __IOM uint32_t KH_RESET_N : 1; /*!< [3..3] 0 KH will be in reset 1 Out of reset */ - __IOM uint32_t KH_KEY_SIZE : 1; /*!< [4..4] 0 128 bit key 1 256 bit key + __IOM unsigned int KH_RESET_N : 1; /*!< [3..3] 0 KH will be in reset 1 Out of reset */ + __IOM unsigned int KH_KEY_SIZE : 1; /*!< [4..4] 0 128 bit key 1 256 bit key This is used by KH */ - __IOM uint32_t KH_CLOCK_RATIO : 3; /*!< [7..5] Indicates the division factor to be + __IOM unsigned int KH_CLOCK_RATIO : 3; /*!< [7..5] Indicates the division factor to be used for generating kh_clk. */ - __IM uint32_t : 24; + __IM unsigned int : 24; } IID_CTRL_REG_b; }; union { - __IOM uint32_t WKE_CTRL_REG; /*!< (@ 0x0000000C) none */ + __IOM unsigned int WKE_CTRL_REG; /*!< (@ 0x0000000C) none */ struct { - __IOM uint32_t ENABLE_WKE : 1; /*!< [0..0] When WKE will be enabled. This + __IOM unsigned int ENABLE_WKE : 1; /*!< [0..0] When WKE will be enabled. This is a self clearing bit. Once enabled WKE can not be disabled till process is done */ - __IOM uint32_t WKE_KEY_SIZE : 1; /*!< [1..1] 0 128 bit size 1 256 bit size */ - __IOM uint32_t WKE_FLUSH : 1; /*!< [2..2] When set, WKE will flush out the data from + __IOM unsigned int WKE_KEY_SIZE : 1; /*!< [1..1] 0 128 bit size 1 256 bit size */ + __IOM unsigned int WKE_FLUSH : 1; /*!< [2..2] When set, WKE will flush out the data from AES. When WEK is active, firmware reads to AES engine are masked. This gets cleared once four dwords are read from AES */ - __IOM uint32_t WKE_COMPARE : 1; /*!< [3..3] When set, WKE will compare the data from + __IOM unsigned int WKE_COMPARE : 1; /*!< [3..3] When set, WKE will compare the data from AES engine with the data provided by firmware */ - __IOM uint32_t WKE_SET_KEY : 1; /*!< [4..4] This has to be set after key + __IOM unsigned int WKE_SET_KEY : 1; /*!< [4..4] This has to be set after key available from AES */ - __IOM uint32_t KEY_CODE_DONE : 1; /*!< [5..5] This has to be set after + __IOM unsigned int KEY_CODE_DONE : 1; /*!< [5..5] This has to be set after reading key code */ - __IM uint32_t : 26; + __IM unsigned int : 26; } WKE_CTRL_REG_b; }; - __IM uint32_t RESERVED; + __IM unsigned int RESERVED; union { - __IOM uint32_t IID_AES_CTRL_REG; /*!< (@ 0x00000014) none */ + __IOM unsigned int IID_AES_CTRL_REG; /*!< (@ 0x00000014) none */ struct { - __IOM uint32_t KEY_REQ_IN_DMA_PATH : 1; /*!< [0..0] Include key req in dma path. With + __IOM unsigned int KEY_REQ_IN_DMA_PATH : 1; /*!< [0..0] Include key req in dma path. With this KEY Also can be loaded using DMA. */ - __IOM uint32_t AES_MAX_KEY_SIZE_FRM_REG : 1; /*!< [1..1] This is valid + __IOM unsigned int AES_MAX_KEY_SIZE_FRM_REG : 1; /*!< [1..1] This is valid only when aes_max_key_size_frm_reg_en is set. */ - __IOM uint32_t AES_MAX_KEY_SIZE_FRM_REG_EN : 1; /*!< [2..2] When set, WKE will flush + __IOM unsigned int AES_MAX_KEY_SIZE_FRM_REG_EN : 1; /*!< [2..2] When set, WKE will flush out the data from AES. When WEK is active, firmware reads to AES engine are masked. This gets cleared once four dwords are read from AES */ - __IOM uint32_t OTP_KEY_LOADING : 1; /*!< [3..3] When set, WKE will compare + __IOM unsigned int OTP_KEY_LOADING : 1; /*!< [3..3] When set, WKE will compare the data from AES engine with the data provided by firmware */ - __IM uint32_t : 28; + __IM unsigned int : 28; } IID_AES_CTRL_REG_b; }; union { - __IM uint32_t IID_AES_STS_REG; /*!< (@ 0x00000018) none */ + __IM unsigned int IID_AES_STS_REG; /*!< (@ 0x00000018) none */ struct { - __IM uint32_t DIN_FIFO_FULL : 1; /*!< [0..0] Input data fifo full indication */ - __IM uint32_t DOUT_FIFO_EMPTY : 1; /*!< [1..1] Output data fifo empty + __IM unsigned int DIN_FIFO_FULL : 1; /*!< [0..0] Input data fifo full indication */ + __IM unsigned int DOUT_FIFO_EMPTY : 1; /*!< [1..1] Output data fifo empty indication */ - __IM uint32_t : 30; + __IM unsigned int : 30; } IID_AES_STS_REG_b; }; - __IM uint32_t RESERVED1; + __IM unsigned int RESERVED1; union { - __IOM uint32_t WKE_STATUS_REG; /*!< (@ 0x00000020) none */ + __IOM unsigned int WKE_STATUS_REG; /*!< (@ 0x00000020) none */ struct { - __IOM uint32_t WKE_ACTIVE : 1; /*!< [0..0] Will be high when WKE is active */ - __IOM uint32_t WKE_KEY_FEED_IN_PROGRESS : 1; /*!< [1..1] Will be high when WKE is + __IOM unsigned int WKE_ACTIVE : 1; /*!< [0..0] Will be high when WKE is active */ + __IOM unsigned int WKE_KEY_FEED_IN_PROGRESS : 1; /*!< [1..1] Will be high when WKE is feeding key to AES engine */ - __IOM uint32_t WKE_FLUSH_IN_PROGRESS : 1; /*!< [2..2] Will be high when WKE flushing + __IOM unsigned int WKE_FLUSH_IN_PROGRESS : 1; /*!< [2..2] Will be high when WKE flushing out the data from AES */ - __IOM uint32_t WKE_COMPARE_IN_PROGRESS : 1; /*!< [3..3] Will be high when WKE is + __IOM unsigned int WKE_COMPARE_IN_PROGRESS : 1; /*!< [3..3] Will be high when WKE is comparing the data from AES */ - __IOM uint32_t WKE_SET_KEY_IN_PROGRESS : 1; /*!< [4..4] Will be high when WKE is + __IOM unsigned int WKE_SET_KEY_IN_PROGRESS : 1; /*!< [4..4] Will be high when WKE is doing set key operation with QK */ - __IOM uint32_t WKE_KEY_READY : 1; /*!< [5..5] Firmware has to load the + __IOM unsigned int WKE_KEY_READY : 1; /*!< [5..5] Firmware has to load the authentication, which will be compared with AES output, when this bit is low */ - __IOM uint32_t WKE_CMP_DATA_READY : 1; /*!< [6..6] Firmware has to load + __IOM unsigned int WKE_CMP_DATA_READY : 1; /*!< [6..6] Firmware has to load the authentication, which will be compared with AES output, when this bit is low */ - __IOM uint32_t WKE_COMPARE_FAIL : 1; /*!< [7..7] This bit will be set when + __IOM unsigned int WKE_COMPARE_FAIL : 1; /*!< [7..7] This bit will be set when authentication data comparison fails */ - __IM uint32_t : 24; + __IM unsigned int : 24; } WKE_STATUS_REG_b; }; - __IM uint32_t RESERVED2; - __IOM uint32_t WKE_DATA_REG; /*!< (@ 0x00000028) none */ -} IID_RPINE_Type; /*!< Size = 44 (0x2c) */ + __IM unsigned int RESERVED2; + __IOM unsigned int WKE_DATA_REG; /*!< (@ 0x00000028) none */ +} IID_RPINE_Type; /*!< Size = 44 (0x2c) */ /* =========================================================================================================================== */ @@ -7821,199 +7821,199 @@ typedef struct { /*!< (@ 0x20480400) IID_RPINE Structure */ typedef struct { /*!< (@ 0x45060000) CT0 Structure */ union { - __IOM uint32_t CT_GEN_CTRL_SET_REG; /*!< (@ 0x00000000) General control set + __IOM unsigned int CT_GEN_CTRL_SET_REG; /*!< (@ 0x00000000) General control set register */ struct { - __IOM uint32_t COUNTER_IN_32_BIT_MODE : 1; /*!< [0..0] Counter_1 and Counter_0 will + __IOM unsigned int COUNTER_IN_32_BIT_MODE : 1; /*!< [0..0] Counter_1 and Counter_0 will be merged and used as a single 32 bit counter */ - __IOM uint32_t SOFT_RESET_COUNTER_0_FRM_REG : 1; /*!< [1..1] This is applied to 32 + __IOM unsigned int SOFT_RESET_COUNTER_0_FRM_REG : 1; /*!< [1..1] This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter */ - __IOM uint32_t PERIODIC_EN_COUNTER_0_FRM_REG : 1; /*!< [2..2] This is applied to 32 + __IOM unsigned int PERIODIC_EN_COUNTER_0_FRM_REG : 1; /*!< [2..2] This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter */ - __IOM uint32_t COUNTER_0_TRIG_FRM_REG : 1; /*!< [3..3] This enables the + __IOM unsigned int COUNTER_0_TRIG_FRM_REG : 1; /*!< [3..3] This enables the counter to run/active */ - __IOM uint32_t COUNTER_0_UP_DOWN : 2; /*!< [5..4] This enables the counter to run in + __IOM unsigned int COUNTER_0_UP_DOWN : 2; /*!< [5..4] This enables the counter to run in up/down/up-down/down-up directions */ - __IOM uint32_t COUNTER_0_SYNC_TRIG : 1; /*!< [6..6] This is applied to 32 bits of + __IOM unsigned int COUNTER_0_SYNC_TRIG : 1; /*!< [6..6] This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter. This enables the counter to run/active when sync is found. */ - __IOM uint32_t BUF_REG_0_EN : 1; /*!< [7..7] Buffer register gets enabled + __IOM unsigned int BUF_REG_0_EN : 1; /*!< [7..7] Buffer register gets enabled for MATCH REG. MATCH_BUF_REG is always available and whenever this bit is set only, gets copied to MATCH REG. */ - __IOM uint32_t RESERVED1 : 9; /*!< [16..8] Reserved1 */ - __IOM uint32_t SOFT_RESET_COUNTER_1_FRM_REG : 1; /*!< [17..17] This resets the + __IOM unsigned int RESERVED1 : 9; /*!< [16..8] Reserved1 */ + __IOM unsigned int SOFT_RESET_COUNTER_1_FRM_REG : 1; /*!< [17..17] This resets the counter on the write */ - __IOM uint32_t PERIODIC_EN_COUNTER_1_FRM_REG : 1; /*!< [18..18] This resets the + __IOM unsigned int PERIODIC_EN_COUNTER_1_FRM_REG : 1; /*!< [18..18] This resets the counter on the write */ - __IOM uint32_t COUNTER_1_TRIG_FRM : 1; /*!< [19..19] This enables the + __IOM unsigned int COUNTER_1_TRIG_FRM : 1; /*!< [19..19] This enables the counter to run/active */ - __IOM uint32_t COUNTER_1_UP_DOWN : 2; /*!< [21..20] This enables the counter to run + __IOM unsigned int COUNTER_1_UP_DOWN : 2; /*!< [21..20] This enables the counter to run in upward direction */ - __IOM uint32_t COUNTER_1_SYNC_TRIG : 1; /*!< [22..22] This is applied to 32 bits of + __IOM unsigned int COUNTER_1_SYNC_TRIG : 1; /*!< [22..22] This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter. This enables the counter to run/active when sync is found. */ - __IOM uint32_t BUF_REG_1_EN : 1; /*!< [23..23] Buffer register gets enabled for MATCH + __IOM unsigned int BUF_REG_1_EN : 1; /*!< [23..23] Buffer register gets enabled for MATCH REG. MATCH_BUF_REG is always available and whenever this bit is set only, gets copied to MATCH REG. */ - __IOM uint32_t RESERVED2 : 8; /*!< [31..24] Reserved2 */ + __IOM unsigned int RESERVED2 : 8; /*!< [31..24] Reserved2 */ } CT_GEN_CTRL_SET_REG_b; }; union { - __IOM uint32_t CT_GEN_CTRL_RESET_REG; /*!< (@ 0x00000004) General control + __IOM unsigned int CT_GEN_CTRL_RESET_REG; /*!< (@ 0x00000004) General control reset register */ struct { - __IOM uint32_t COUNTER_IN_32_BIT_MODE : 1; /*!< [0..0] Counter_1 and Counter_0 will + __IOM unsigned int COUNTER_IN_32_BIT_MODE : 1; /*!< [0..0] Counter_1 and Counter_0 will be merged and used as a single 32 bit counter */ - __IM uint32_t RESERVED1 : 1; /*!< [1..1] Reserved1 */ - __IOM uint32_t PERIODIC_EN_COUNTER_0_FRM_REG : 1; /*!< [2..2] This is applied to 32 + __IM unsigned int RESERVED1 : 1; /*!< [1..1] Reserved1 */ + __IOM unsigned int PERIODIC_EN_COUNTER_0_FRM_REG : 1; /*!< [2..2] This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter */ - __IM uint32_t RESERVED2 : 1; /*!< [3..3] Reserved2 */ - __IOM uint32_t COUNTER_0_UP_DOWN : 2; /*!< [5..4] This enables the counter to run in + __IM unsigned int RESERVED2 : 1; /*!< [3..3] Reserved2 */ + __IOM unsigned int COUNTER_0_UP_DOWN : 2; /*!< [5..4] This enables the counter to run in up/down/up-down/down-up directions */ - __IM uint32_t RESERVED3 : 1; /*!< [6..6] Reserved3 */ - __IOM uint32_t BUF_REG_0_EN : 1; /*!< [7..7] Buffer register gets enabled + __IM unsigned int RESERVED3 : 1; /*!< [6..6] Reserved3 */ + __IOM unsigned int BUF_REG_0_EN : 1; /*!< [7..7] Buffer register gets enabled for MATCH REG. MATCH_BUF_REG is always available and whenever this bit is set only, gets copied to MATCH REG. */ - __IM uint32_t RESERVED4 : 9; /*!< [16..8] Reserved4 */ - __IM uint32_t RESERVED5 : 1; /*!< [17..17] Reserved5 */ - __IOM uint32_t PERIODIC_EN_COUNTER_1_FRM_REG : 1; /*!< [18..18] This resets the + __IM unsigned int RESERVED4 : 9; /*!< [16..8] Reserved4 */ + __IM unsigned int RESERVED5 : 1; /*!< [17..17] Reserved5 */ + __IOM unsigned int PERIODIC_EN_COUNTER_1_FRM_REG : 1; /*!< [18..18] This resets the counter on the write */ - __IM uint32_t RESERVED6 : 1; /*!< [19..19] Reserved6 */ - __IOM uint32_t COUNTER_1_UP_DOWN : 2; /*!< [21..20] This enables the counter to run + __IM unsigned int RESERVED6 : 1; /*!< [19..19] Reserved6 */ + __IOM unsigned int COUNTER_1_UP_DOWN : 2; /*!< [21..20] This enables the counter to run in upward direction */ - __IM uint32_t RESERVED7 : 1; /*!< [22..22] Reserved7 */ - __IOM uint32_t BUF_REG_1_EN : 1; /*!< [23..23] Buffer register gets enabled for MATCH + __IM unsigned int RESERVED7 : 1; /*!< [22..22] Reserved7 */ + __IOM unsigned int BUF_REG_1_EN : 1; /*!< [23..23] Buffer register gets enabled for MATCH REG. MATCH_BUF_REG is always available and whenever this bit is set only, gets copied to MATCH REG. */ - __IM uint32_t RESERVED8 : 8; /*!< [31..24] Reserved8 */ + __IM unsigned int RESERVED8 : 8; /*!< [31..24] Reserved8 */ } CT_GEN_CTRL_RESET_REG_b; }; union { - __IM uint32_t CT_INTR_STS; /*!< (@ 0x00000008) Interrupt status */ + __IM unsigned int CT_INTR_STS; /*!< (@ 0x00000008) Interrupt status */ struct { - __IM uint32_t INTR_0_L : 1; /*!< [0..0] Indicates the FIFO full signal of + __IM unsigned int INTR_0_L : 1; /*!< [0..0] Indicates the FIFO full signal of channel-0 */ - __IM uint32_t FIFO_0_FULL_L : 1; /*!< [1..1] Indicates the FIFO full + __IM unsigned int FIFO_0_FULL_L : 1; /*!< [1..1] Indicates the FIFO full signal of channel-0 */ - __IM uint32_t COUNTER_0_IS_ZERO_L : 1; /*!< [2..2] Counter 0 hit zero in + __IM unsigned int COUNTER_0_IS_ZERO_L : 1; /*!< [2..2] Counter 0 hit zero in active mode. */ - __IM uint32_t COUNTER_0_IS_PEAK_L : 1; /*!< [3..3] Counter 0 hit peak + __IM unsigned int COUNTER_0_IS_PEAK_L : 1; /*!< [3..3] Counter 0 hit peak (MATCH) in active mode. */ - __IM uint32_t RESERVED1 : 12; /*!< [15..4] Reserved1 */ - __IM uint32_t INTR_1_L : 1; /*!< [16..16] Indicates the FIFO full signal + __IM unsigned int RESERVED1 : 12; /*!< [15..4] Reserved1 */ + __IM unsigned int INTR_1_L : 1; /*!< [16..16] Indicates the FIFO full signal of channel-1 */ - __IM uint32_t FIFO_1_FULL_L : 1; /*!< [17..17] Indicates the FIFO full + __IM unsigned int FIFO_1_FULL_L : 1; /*!< [17..17] Indicates the FIFO full signal of channel-1 */ - __IM uint32_t COUNTER_1_IS_ZERO_L : 1; /*!< [18..18] Counter 1 hit zero in + __IM unsigned int COUNTER_1_IS_ZERO_L : 1; /*!< [18..18] Counter 1 hit zero in active mode. */ - __IM uint32_t COUNTER_1_IS_PEAK_L : 1; /*!< [19..19] Counter 1 hit peak + __IM unsigned int COUNTER_1_IS_PEAK_L : 1; /*!< [19..19] Counter 1 hit peak (MATCH) in active mode. */ - __IM uint32_t RESERVED2 : 12; /*!< [31..20] Reserved2 */ + __IM unsigned int RESERVED2 : 12; /*!< [31..20] Reserved2 */ } CT_INTR_STS_b; }; union { - __IOM uint32_t CT_INTR_MASK; /*!< (@ 0x0000000C) Interrupts mask */ + __IOM unsigned int CT_INTR_MASK; /*!< (@ 0x0000000C) Interrupts mask */ struct { - __IOM uint32_t INTR_0_L : 1; /*!< [0..0] Interrupt mask signal. */ - __IOM uint32_t FIFO_0_FULL_L : 1; /*!< [1..1] Interrupt mask signal. */ - __IOM uint32_t COUNTER_0_IS_ZERO_L : 1; /*!< [2..2] Interrupt mask signal. */ - __IOM uint32_t COUNTER_0_IS_PEAK_L : 1; /*!< [3..3] Interrupt mask signal. */ - __IOM uint32_t RESERVED1 : 12; /*!< [15..4] Reserved1 */ - __IOM uint32_t INTR_1_L : 1; /*!< [16..16] Interrupt mask signal. */ - __IOM uint32_t FIFO_1_FULL_L : 1; /*!< [17..17] Interrupt mask signal. */ - __IOM uint32_t COUNTER_1_IS_ZERO_L : 1; /*!< [18..18] Interrupt mask signal. */ - __IOM uint32_t COUNTER_1_IS_PEAK_L : 1; /*!< [19..19] Interrupt mask signal. */ - __IOM uint32_t RESERVED2 : 12; /*!< [31..20] Reserved2 */ + __IOM unsigned int INTR_0_L : 1; /*!< [0..0] Interrupt mask signal. */ + __IOM unsigned int FIFO_0_FULL_L : 1; /*!< [1..1] Interrupt mask signal. */ + __IOM unsigned int COUNTER_0_IS_ZERO_L : 1; /*!< [2..2] Interrupt mask signal. */ + __IOM unsigned int COUNTER_0_IS_PEAK_L : 1; /*!< [3..3] Interrupt mask signal. */ + __IOM unsigned int RESERVED1 : 12; /*!< [15..4] Reserved1 */ + __IOM unsigned int INTR_1_L : 1; /*!< [16..16] Interrupt mask signal. */ + __IOM unsigned int FIFO_1_FULL_L : 1; /*!< [17..17] Interrupt mask signal. */ + __IOM unsigned int COUNTER_1_IS_ZERO_L : 1; /*!< [18..18] Interrupt mask signal. */ + __IOM unsigned int COUNTER_1_IS_PEAK_L : 1; /*!< [19..19] Interrupt mask signal. */ + __IOM unsigned int RESERVED2 : 12; /*!< [31..20] Reserved2 */ } CT_INTR_MASK_b; }; union { - __IOM uint32_t CT_INTER_UNMASK; /*!< (@ 0x00000010) Interrupts unmask */ + __IOM unsigned int CT_INTER_UNMASK; /*!< (@ 0x00000010) Interrupts unmask */ struct { - __IOM uint32_t INTR_0_L : 1; /*!< [0..0] Interrupt unmask signal. */ - __IOM uint32_t FIFO_0_FULL_L : 1; /*!< [1..1] Interrupt unmask signal. */ - __IOM uint32_t COUNTER_0_IS_ZERO_L : 1; /*!< [2..2] Interrupt unmask signal. */ - __IOM uint32_t COUNTER_0_IS_PEAK_L : 1; /*!< [3..3] Interrupt unmask signal. */ - __IM uint32_t RESERVED1 : 12; /*!< [15..4] Reserved1 */ - __IOM uint32_t INTR_1_L : 1; /*!< [16..16] Interrupt unmask signal. */ - __IOM uint32_t FIFO_1_FULL_L : 1; /*!< [17..17] Interrupt unmask signal */ - __IOM uint32_t COUNTER_1_IS_ZERO_L : 1; /*!< [18..18] Interrupt unmask signal. */ - __IOM uint32_t COUNTER_1_IS_PEAK_L : 1; /*!< [19..19] Interrupt unmask signal. */ - __IM uint32_t RESERVED2 : 12; /*!< [31..20] Reserved2 */ + __IOM unsigned int INTR_0_L : 1; /*!< [0..0] Interrupt unmask signal. */ + __IOM unsigned int FIFO_0_FULL_L : 1; /*!< [1..1] Interrupt unmask signal. */ + __IOM unsigned int COUNTER_0_IS_ZERO_L : 1; /*!< [2..2] Interrupt unmask signal. */ + __IOM unsigned int COUNTER_0_IS_PEAK_L : 1; /*!< [3..3] Interrupt unmask signal. */ + __IM unsigned int RESERVED1 : 12; /*!< [15..4] Reserved1 */ + __IOM unsigned int INTR_1_L : 1; /*!< [16..16] Interrupt unmask signal. */ + __IOM unsigned int FIFO_1_FULL_L : 1; /*!< [17..17] Interrupt unmask signal */ + __IOM unsigned int COUNTER_1_IS_ZERO_L : 1; /*!< [18..18] Interrupt unmask signal. */ + __IOM unsigned int COUNTER_1_IS_PEAK_L : 1; /*!< [19..19] Interrupt unmask signal. */ + __IM unsigned int RESERVED2 : 12; /*!< [31..20] Reserved2 */ } CT_INTER_UNMASK_b; }; union { - __IOM uint32_t CT_INTR_ACK; /*!< (@ 0x00000014) Interrupt clear/ack register */ + __IOM unsigned int CT_INTR_ACK; /*!< (@ 0x00000014) Interrupt clear/ack register */ struct { - __IOM uint32_t INTR_0_L : 1; /*!< [0..0] Interrupt ack signal. */ - __IOM uint32_t FIFO_0_FULL_L : 1; /*!< [1..1] Interrupt ack signal. */ - __IOM uint32_t COUNTER_0_IS_ZERO_L : 1; /*!< [2..2] Interrupt ack signal. */ - __IOM uint32_t COUNTER_0_IS_PEAK_L : 1; /*!< [3..3] Interrupt ack signal. */ - __IM uint32_t RESERVED1 : 12; /*!< [15..4] Reserved1 */ - __IOM uint32_t INTR_1_L : 1; /*!< [16..16] Interrupt ack signal. */ - __IOM uint32_t FIFO_1_FULL_L : 1; /*!< [17..17] Interrupt ack signal. */ - __IOM uint32_t COUNTER_1_IS_ZERO_L : 1; /*!< [18..18] Interrupt ack signal. */ - __IOM uint32_t COUNTER_1_IS_PEAK_L : 1; /*!< [19..19] Interrupt ack signal. */ - __IOM uint32_t RESERVED2 : 12; /*!< [31..20] Reserved2 */ + __IOM unsigned int INTR_0_L : 1; /*!< [0..0] Interrupt ack signal. */ + __IOM unsigned int FIFO_0_FULL_L : 1; /*!< [1..1] Interrupt ack signal. */ + __IOM unsigned int COUNTER_0_IS_ZERO_L : 1; /*!< [2..2] Interrupt ack signal. */ + __IOM unsigned int COUNTER_0_IS_PEAK_L : 1; /*!< [3..3] Interrupt ack signal. */ + __IM unsigned int RESERVED1 : 12; /*!< [15..4] Reserved1 */ + __IOM unsigned int INTR_1_L : 1; /*!< [16..16] Interrupt ack signal. */ + __IOM unsigned int FIFO_1_FULL_L : 1; /*!< [17..17] Interrupt ack signal. */ + __IOM unsigned int COUNTER_1_IS_ZERO_L : 1; /*!< [18..18] Interrupt ack signal. */ + __IOM unsigned int COUNTER_1_IS_PEAK_L : 1; /*!< [19..19] Interrupt ack signal. */ + __IOM unsigned int RESERVED2 : 12; /*!< [31..20] Reserved2 */ } CT_INTR_ACK_b; }; union { - __IOM uint32_t CT_MATCH_REG; /*!< (@ 0x00000018) Match value register */ + __IOM unsigned int CT_MATCH_REG; /*!< (@ 0x00000018) Match value register */ struct { - __IOM uint32_t COUNTER_0_MATCH : 16; /*!< [15..0] This will be used as + __IOM unsigned int COUNTER_0_MATCH : 16; /*!< [15..0] This will be used as lower match */ - __IOM uint32_t COUNTER_1_MATCH : 16; /*!< [31..16] This will be used as + __IOM unsigned int COUNTER_1_MATCH : 16; /*!< [31..16] This will be used as upper match */ } CT_MATCH_REG_b; }; union { - __IOM uint32_t CT_MATCH_BUF_REG; /*!< (@ 0x0000001C) Match Buffer register */ + __IOM unsigned int CT_MATCH_BUF_REG; /*!< (@ 0x0000001C) Match Buffer register */ struct { - __IOM uint32_t COUNTER_0_MATCH_BUF : 16; /*!< [15..0] This gets copied to MATCH + __IOM unsigned int COUNTER_0_MATCH_BUF : 16; /*!< [15..0] This gets copied to MATCH register if bug_reg_0_en is set. Copying is done when counter 0 is active and hits 0. */ - __IOM uint32_t COUNTER_1_MATCH_BUF : 16; /*!< [31..16] This gets copied to MATCH + __IOM unsigned int COUNTER_1_MATCH_BUF : 16; /*!< [31..16] This gets copied to MATCH register if bug_reg_1_en is set. Copying is done when counter 1 is active and hits 0. */ @@ -8021,75 +8021,75 @@ typedef struct { /*!< (@ 0x45060000) CT0 Structure */ }; union { - __IM uint32_t CT_CAPTURE_REG; /*!< (@ 0x00000020) Capture Register */ + __IM unsigned int CT_CAPTURE_REG; /*!< (@ 0x00000020) Capture Register */ struct { - __IM uint32_t COUNTER_0_CAPTURE : 16; /*!< [15..0] This is a latched value of + __IM unsigned int COUNTER_0_CAPTURE : 16; /*!< [15..0] This is a latched value of counter lower part when the selected capture_event occurs */ - __IM uint32_t COUNTER_1_CAPTURE : 16; /*!< [31..16] This is a latched value of + __IM unsigned int COUNTER_1_CAPTURE : 16; /*!< [31..16] This is a latched value of counter upper part when the selected capture_event occurs */ } CT_CAPTURE_REG_b; }; union { - __IOM uint32_t CT_COUNTER_REG; /*!< (@ 0x00000024) Counter Register */ + __IOM unsigned int CT_COUNTER_REG; /*!< (@ 0x00000024) Counter Register */ struct { - __IM uint32_t COUNTER0 : 16; /*!< [15..0] This holds the value of counter-0 */ - __IM uint32_t COUNTER1 : 16; /*!< [31..16] This holds the value of counter-1 */ + __IM unsigned int COUNTER0 : 16; /*!< [15..0] This holds the value of counter-0 */ + __IM unsigned int COUNTER1 : 16; /*!< [31..16] This holds the value of counter-1 */ } CT_COUNTER_REG_b; }; union { - __IOM uint32_t CT_OCU_CTRL_REG; /*!< (@ 0x00000028) OCU control register */ + __IOM unsigned int CT_OCU_CTRL_REG; /*!< (@ 0x00000028) OCU control register */ struct { - __IOM uint32_t OUTPUT_IS_OCU_0 : 1; /*!< [0..0] Indicates whether the output is in + __IOM unsigned int OUTPUT_IS_OCU_0 : 1; /*!< [0..0] Indicates whether the output is in OCU mode or not for channel-0 */ - __IOM uint32_t SYNC_WITH_0 : 3; /*!< [3..1] Indicates whether the other channel is in + __IOM unsigned int SYNC_WITH_0 : 3; /*!< [3..1] Indicates whether the other channel is in sync with this channel */ - __IOM uint32_t OCU_0_DMA_MODE : 1; /*!< [4..4] Indicates whether the OCU DMA mode is + __IOM unsigned int OCU_0_DMA_MODE : 1; /*!< [4..4] Indicates whether the OCU DMA mode is active or not for channel 0 */ - __IOM uint32_t OCU_0_MODE_8_16 : 1; /*!< [5..5] Indicates whether entire 16 bits or + __IOM unsigned int OCU_0_MODE_8_16 : 1; /*!< [5..5] Indicates whether entire 16 bits or only 8-bits of the channel 0 are used in OCU mode */ - __IOM uint32_t MAKE_OUTPUT_0_HIGH_SEL : 3; /*!< [8..6] Check counter ocus for + __IOM unsigned int MAKE_OUTPUT_0_HIGH_SEL : 3; /*!< [8..6] Check counter ocus for possibilities. When this is hit output will be made high. */ - __IOM uint32_t MAKE_OUTPUT_0_LOW_SEL : 3; /*!< [11..9] Check counter ocus for + __IOM unsigned int MAKE_OUTPUT_0_LOW_SEL : 3; /*!< [11..9] Check counter ocus for possibilities. When this is hit output will be made low. */ - __IOM uint32_t RESERVED1 : 4; /*!< [15..12] Reserved1 */ - __IOM uint32_t OUTPUT_1_IS_OCU : 1; /*!< [16..16] Indicates whether the output is in + __IOM unsigned int RESERVED1 : 4; /*!< [15..12] Reserved1 */ + __IOM unsigned int OUTPUT_1_IS_OCU : 1; /*!< [16..16] Indicates whether the output is in OCU mode or not for channel 1 */ - __IOM uint32_t SYNC_WITH_1 : 3; /*!< [19..17] Indicates whether the other channel is + __IOM unsigned int SYNC_WITH_1 : 3; /*!< [19..17] Indicates whether the other channel is in sync with this channel */ - __IOM uint32_t OCU_1_DMA_MODE : 1; /*!< [20..20] Indicates whether the OCU DMA mode + __IOM unsigned int OCU_1_DMA_MODE : 1; /*!< [20..20] Indicates whether the OCU DMA mode is active or not for channel 1 */ - __IOM uint32_t OCU_1_MODE_8_16_MODE : 1; /*!< [21..21] Indicates whether entire 16 + __IOM unsigned int OCU_1_MODE_8_16_MODE : 1; /*!< [21..21] Indicates whether entire 16 bits or only 8-bits of the channel 1 are used in OCU mode */ - __IOM uint32_t MAKE_OUTPUT_1_HIGH_SEL : 3; /*!< [24..22] Check counter ocus for + __IOM unsigned int MAKE_OUTPUT_1_HIGH_SEL : 3; /*!< [24..22] Check counter ocus for possibilities. When this is hit output will be made high. */ - __IOM uint32_t MAKE_OUTPUT_1_LOW_SEL : 3; /*!< [27..25] Check counter ocus for + __IOM unsigned int MAKE_OUTPUT_1_LOW_SEL : 3; /*!< [27..25] Check counter ocus for possibilities. When this is hit output will be made low. */ - __IOM uint32_t RESERVED2 : 4; /*!< [31..28] Reserved2 */ + __IOM unsigned int RESERVED2 : 4; /*!< [31..28] Reserved2 */ } CT_OCU_CTRL_REG_b; }; union { - __IOM uint32_t CT_OCU_COMPARE_REG; /*!< (@ 0x0000002C) OCU Compare Register */ + __IOM unsigned int CT_OCU_COMPARE_REG; /*!< (@ 0x0000002C) OCU Compare Register */ struct { - __IOM uint32_t OCU_COMPARE_0_REG : 16; /*!< [15..0] Holds the threshold value of + __IOM unsigned int OCU_COMPARE_0_REG : 16; /*!< [15..0] Holds the threshold value of present OCU period which denotes the number of clock cycles for which the OCU output should be considered (counter 0) */ - __IOM uint32_t OCU_COMPARE_1_REG : 16; /*!< [31..16] Holds the threshold value of + __IOM unsigned int OCU_COMPARE_1_REG : 16; /*!< [31..16] Holds the threshold value of present OCU period which denotes the number of clock cycles for which the OCU output should be considered (counter 1) */ @@ -8097,16 +8097,16 @@ typedef struct { /*!< (@ 0x45060000) CT0 Structure */ }; union { - __IOM uint32_t CT_OCU_COMPARE2_REG; /*!< (@ 0x00000030) OCU Compare2 Register */ + __IOM unsigned int CT_OCU_COMPARE2_REG; /*!< (@ 0x00000030) OCU Compare2 Register */ struct { - __IOM uint32_t OCU_COMPARE2_0_REG : 16; /*!< [15..0] Holds the threshold + __IOM unsigned int OCU_COMPARE2_0_REG : 16; /*!< [15..0] Holds the threshold value of present OCU period2 which denotes the number of clock cycles for which the OCU output should be considered (counter 0) */ - __IOM uint32_t OCU_COMPARE2_1_REG : 16; /*!< [31..16] Holds the threshold + __IOM unsigned int OCU_COMPARE2_1_REG : 16; /*!< [31..16] Holds the threshold value of present OCU period2 which denotes the number of clock cycles for which the OCU @@ -8116,594 +8116,594 @@ typedef struct { /*!< (@ 0x45060000) CT0 Structure */ }; union { - __IOM uint32_t CT_OCU_SYNC_REG; /*!< (@ 0x00000034) OCU Synchronization Register */ + __IOM unsigned int CT_OCU_SYNC_REG; /*!< (@ 0x00000034) OCU Synchronization Register */ struct { - __IOM uint32_t OCU_SYNC_CHANNEL0_REG : 16; /*!< [15..0] Starting point of channel 0 + __IOM unsigned int OCU_SYNC_CHANNEL0_REG : 16; /*!< [15..0] Starting point of channel 0 for synchronization purpose */ - __IOM uint32_t OCU_SYNC_CHANNEL1_REG : 16; /*!< [31..16] Starting point of channel 1 + __IOM unsigned int OCU_SYNC_CHANNEL1_REG : 16; /*!< [31..16] Starting point of channel 1 for synchronization purpose */ } CT_OCU_SYNC_REG_b; }; union { - __IOM uint32_t CT_OCU_COMPARE_NXT_REG; /*!< (@ 0x00000038) PWM compare next + __IOM unsigned int CT_OCU_COMPARE_NXT_REG; /*!< (@ 0x00000038) PWM compare next register */ struct { - __IOM uint32_t OCU_COMPARE_NXT_COUNTER1 : 16; /*!< [15..0] OCU output should be high + __IOM unsigned int OCU_COMPARE_NXT_COUNTER1 : 16; /*!< [15..0] OCU output should be high for counter 1 */ - __IOM uint32_t OCU_COMPARE_NXT_COUNTER0 : 16; /*!< [31..16] PWM output should be high + __IOM unsigned int OCU_COMPARE_NXT_COUNTER0 : 16; /*!< [31..16] PWM output should be high for counter 0 */ } CT_OCU_COMPARE_NXT_REG_b; }; union { - __IOM uint32_t CT_WFG_CTRL_REG; /*!< (@ 0x0000003C) WFG control register */ + __IOM unsigned int CT_WFG_CTRL_REG; /*!< (@ 0x0000003C) WFG control register */ struct { - __IOM uint32_t MAKE_OUTPUT_0_TGL_0_SEL : 3; /*!< [2..0] Check the counter ocus + __IOM unsigned int MAKE_OUTPUT_0_TGL_0_SEL : 3; /*!< [2..0] Check the counter ocus possibilities for description for channel 0. */ - __IOM uint32_t MAKE_OUTPUT_0_TGL_1_SEL : 3; /*!< [5..3] Check the counter ocus + __IOM unsigned int MAKE_OUTPUT_0_TGL_1_SEL : 3; /*!< [5..3] Check the counter ocus possibilities for description for channel 0. */ - __IOM uint32_t RESERVED1 : 2; /*!< [7..6] Reserved1 */ - __IOM uint32_t WFG_TGL_CNT_0_PEAK : 8; /*!< [15..8] WFG mode output toggle + __IOM unsigned int RESERVED1 : 2; /*!< [7..6] Reserved1 */ + __IOM unsigned int WFG_TGL_CNT_0_PEAK : 8; /*!< [15..8] WFG mode output toggle count clock for channel 0. */ - __IOM uint32_t MAKE_OUTPUT_1_TGL_0_SEL : 3; /*!< [18..16] Check the counter ocus + __IOM unsigned int MAKE_OUTPUT_1_TGL_0_SEL : 3; /*!< [18..16] Check the counter ocus possibilities for description for channel 1. */ - __IOM uint32_t MAKE_OUTPUT_1_TGL_1_SEL : 3; /*!< [21..19] Check the counter ocus + __IOM unsigned int MAKE_OUTPUT_1_TGL_1_SEL : 3; /*!< [21..19] Check the counter ocus possibilities for description for channel 1. */ - __IOM uint32_t RESERVED2 : 2; /*!< [23..22] Reserved2 */ - __IOM uint32_t WFG_TGL_CNT_1_PEAK : 8; /*!< [31..24] WFG mode output toggle count + __IOM unsigned int RESERVED2 : 2; /*!< [23..22] Reserved2 */ + __IOM unsigned int WFG_TGL_CNT_1_PEAK : 8; /*!< [31..24] WFG mode output toggle count clock for channel 1 */ } CT_WFG_CTRL_REG_b; }; union { - __IOM uint32_t CT_OCU_COMPARE2_NXT_REG; /*!< (@ 0x00000040) PWM compare next + __IOM unsigned int CT_OCU_COMPARE2_NXT_REG; /*!< (@ 0x00000040) PWM compare next register */ struct { - __IOM uint32_t OCU_COMPARE2_NXT_COUNTER0 : 16; /*!< [15..0] OCU output should be high + __IOM unsigned int OCU_COMPARE2_NXT_COUNTER0 : 16; /*!< [15..0] OCU output should be high for counter 1 */ - __IOM uint32_t OCU_COMPARE2_NXT_COUNTER1 : 16; /*!< [31..16] PWM output should be + __IOM unsigned int OCU_COMPARE2_NXT_COUNTER1 : 16; /*!< [31..16] PWM output should be high for counter 0 */ } CT_OCU_COMPARE2_NXT_REG_b; }; - __IM uint32_t RESERVED[3]; + __IM unsigned int RESERVED[3]; union { - __IOM uint32_t CT_START_COUNTER_EVENT_SEL; /*!< (@ 0x00000050) Start counter + __IOM unsigned int CT_START_COUNTER_EVENT_SEL; /*!< (@ 0x00000050) Start counter event select register */ struct { - __IOM uint32_t START_COUNTER_0_EVENT_SEL : 6; /*!< [5..0] For two 16 bit counters + __IOM unsigned int START_COUNTER_0_EVENT_SEL : 6; /*!< [5..0] For two 16 bit counters mode: Event select for starting the Counter 0 For 32 bit counter mode: Event select for starting counter */ - __IOM uint32_t RESERVED1 : 10; /*!< [15..6] Reserved1 */ - __IOM uint32_t START_COUNTER_1_EVENT_SEL : 6; /*!< [21..16] For two 16 bit counters + __IOM unsigned int RESERVED1 : 10; /*!< [15..6] Reserved1 */ + __IOM unsigned int START_COUNTER_1_EVENT_SEL : 6; /*!< [21..16] For two 16 bit counters mode: Event select for starting the Counter 1. For 32 bit counter mode: Invalid. Please refer to events table for description */ - __IM uint32_t RESERVED2 : 10; /*!< [31..22] Reserved2 */ + __IM unsigned int RESERVED2 : 10; /*!< [31..22] Reserved2 */ } CT_START_COUNTER_EVENT_SEL_b; }; union { - __IOM uint32_t CT_START_COUNTER_AND_EVENT; /*!< (@ 0x00000054) Start counter + __IOM unsigned int CT_START_COUNTER_AND_EVENT; /*!< (@ 0x00000054) Start counter AND event register */ struct { - __IOM uint32_t START_COUNTER_0_AND_EVENT : 4; /*!< [3..0] For two 16 bit counter + __IOM unsigned int START_COUNTER_0_AND_EVENT : 4; /*!< [3..0] For two 16 bit counter mode: AND expression valids for AND event in start Counter 0 event For 32 bit counter mode AND expression valids for AND event in start counter event */ - __IOM uint32_t RESERVED1 : 4; /*!< [7..4] Reserved1 */ - __IOM uint32_t START_COUNTER_0_AND_VLD : 4; /*!< [11..8] none */ - __IM uint32_t RESERVED2 : 4; /*!< [15..12] Reserved2 */ - __IOM uint32_t START_COUNTER_1_AND_EVENT : 4; /*!< [19..16] For two 16 bit counters + __IOM unsigned int RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM unsigned int START_COUNTER_0_AND_VLD : 4; /*!< [11..8] none */ + __IM unsigned int RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM unsigned int START_COUNTER_1_AND_EVENT : 4; /*!< [19..16] For two 16 bit counters mode: AND expression valids for AND event in start counter event For 32 bit counter mode : Invalid */ - __IM uint32_t RESERVED3 : 4; /*!< [23..20] Reserved3 */ - __IOM uint32_t START_COUNTER_1_AND_VLD : 4; /*!< [27..24] none */ - __IM uint32_t RESERVED4 : 4; /*!< [31..28] Reserved4 */ + __IM unsigned int RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM unsigned int START_COUNTER_1_AND_VLD : 4; /*!< [27..24] none */ + __IM unsigned int RESERVED4 : 4; /*!< [31..28] Reserved4 */ } CT_START_COUNTER_AND_EVENT_b; }; union { - __IOM uint32_t CT_START_COUNTER_OR_EVENT; /*!< (@ 0x00000058) Start counter + __IOM unsigned int CT_START_COUNTER_OR_EVENT; /*!< (@ 0x00000058) Start counter OR event register */ struct { - __IOM uint32_t START_COUNTER_0_OR_EVENT : 4; /*!< [3..0] For two 16 bit counter mode: + __IOM unsigned int START_COUNTER_0_OR_EVENT : 4; /*!< [3..0] For two 16 bit counter mode: OR expression valids for OR event in start Counter 0 event For 32 bit counter mode OR expression valids for OR event in start counter event */ - __IOM uint32_t RESERVED1 : 4; /*!< [7..4] Reserved1 */ - __IOM uint32_t START_COUNTER_0_OR_VLD : 4; /*!< [11..8] none */ - __IOM uint32_t RESERVED2 : 4; /*!< [15..12] Reserved2 */ - __IOM uint32_t START_COUNTER_1_OR_EVENT : 4; /*!< [19..16] For two 16 bit counters + __IOM unsigned int RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM unsigned int START_COUNTER_0_OR_VLD : 4; /*!< [11..8] none */ + __IOM unsigned int RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM unsigned int START_COUNTER_1_OR_EVENT : 4; /*!< [19..16] For two 16 bit counters mode: OR expression valids for OR event in start counter event For 32 bit counter mode : Invalid. */ - __IM uint32_t RESERVED3 : 4; /*!< [23..20] Reserved3 */ - __IOM uint32_t START_COUNTER_1_OR_VLD : 4; /*!< [27..24] none */ - __IM uint32_t RESERVED4 : 4; /*!< [31..28] Reserved4 */ + __IM unsigned int RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM unsigned int START_COUNTER_1_OR_VLD : 4; /*!< [27..24] none */ + __IM unsigned int RESERVED4 : 4; /*!< [31..28] Reserved4 */ } CT_START_COUNTER_OR_EVENT_b; }; union { - __IOM uint32_t CT_CONTINUE_COUNTER_EVENT_SEL; /*!< (@ 0x0000005C) Continue counter + __IOM unsigned int CT_CONTINUE_COUNTER_EVENT_SEL; /*!< (@ 0x0000005C) Continue counter event select register */ struct { - __IOM uint32_t CONTINUE_COUNTER_0_EVENT_SEL : 6; /*!< [5..0] For two 16 bit counters + __IOM unsigned int CONTINUE_COUNTER_0_EVENT_SEL : 6; /*!< [5..0] For two 16 bit counters mode: Event select for continuing the Counter 0 For 32 bit counter mode: Event select for continuing counter */ - __IOM uint32_t RESERVED1 : 10; /*!< [15..6] Reserved1 */ - __IOM uint32_t CONTINUE_COUNTER_1_EVENT_SEL : 6; /*!< [21..16] For two 16 bit + __IOM unsigned int RESERVED1 : 10; /*!< [15..6] Reserved1 */ + __IOM unsigned int CONTINUE_COUNTER_1_EVENT_SEL : 6; /*!< [21..16] For two 16 bit counters mode: Event select for continuing the Counter 1 For 32 bit counter mode: Invalid. */ - __IM uint32_t RESERVED2 : 10; /*!< [31..22] Reserved2 */ + __IM unsigned int RESERVED2 : 10; /*!< [31..22] Reserved2 */ } CT_CONTINUE_COUNTER_EVENT_SEL_b; }; union { - __IOM uint32_t CT_CONTINUE_COUNTER_AND_EVENT; /*!< (@ 0x00000060) Continue counter AND + __IOM unsigned int CT_CONTINUE_COUNTER_AND_EVENT; /*!< (@ 0x00000060) Continue counter AND event register */ struct { - __IOM uint32_t CONTINUE_COUNTER_0_AND_EVENT : 4; /*!< [3..0] For two 16 bit counter + __IOM unsigned int CONTINUE_COUNTER_0_AND_EVENT : 4; /*!< [3..0] For two 16 bit counter mode: AND expression valids for AND event in continue Counter 0 event For 32 bit counter mode AND expression valids for AND event in continue counter event. */ - __IOM uint32_t RESERVED1 : 4; /*!< [7..4] Reserved1 */ - __IOM uint32_t CONTINUE_COUNTER_0_AND_VLD : 4; /*!< [11..8] none */ - __IOM uint32_t RESERVED2 : 4; /*!< [15..12] Reserved2 */ - __IOM uint32_t CONTINUE_COUNTER_1_AND_EVENT : 4; /*!< [19..16] For two 16 bit + __IOM unsigned int RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM unsigned int CONTINUE_COUNTER_0_AND_VLD : 4; /*!< [11..8] none */ + __IOM unsigned int RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM unsigned int CONTINUE_COUNTER_1_AND_EVENT : 4; /*!< [19..16] For two 16 bit counters mode: AND expression valids for AND event in continue counter event For 32 bit counter mode : Invalid */ - __IM uint32_t RESERVED3 : 4; /*!< [23..20] Reserved3 */ - __IOM uint32_t CONTINUE_COUNTER_1_AND_VLD : 4; /*!< [27..24] none */ - __IM uint32_t RESERVED4 : 4; /*!< [31..28] Reserved4 */ + __IM unsigned int RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM unsigned int CONTINUE_COUNTER_1_AND_VLD : 4; /*!< [27..24] none */ + __IM unsigned int RESERVED4 : 4; /*!< [31..28] Reserved4 */ } CT_CONTINUE_COUNTER_AND_EVENT_b; }; union { - __IOM uint32_t CT_CONTINUE_COUNTER_OR_EVENT; /*!< (@ 0x00000064) Continue counter OR + __IOM unsigned int CT_CONTINUE_COUNTER_OR_EVENT; /*!< (@ 0x00000064) Continue counter OR event register */ struct { - __IOM uint32_t CONTINUE_COUNTER_0_OR_EVENT : 4; /*!< [3..0] For two 16 bit counter + __IOM unsigned int CONTINUE_COUNTER_0_OR_EVENT : 4; /*!< [3..0] For two 16 bit counter mode: OR expression valids for OR event in continue Counter 0 event For 32 bit counter mode OR expression valids for OR event in continue counter event */ - __IOM uint32_t RESERVED1 : 4; /*!< [7..4] Reserved1 */ - __IOM uint32_t CONTINUE_COUNTER_0_OR_VLD : 4; /*!< [11..8] none */ - __IOM uint32_t RESERVED2 : 4; /*!< [15..12] Reserved2 */ - __IOM uint32_t CONTINUE_COUNTER_1_OR_EVENT : 4; /*!< [19..16] For two 16 bit counters + __IOM unsigned int RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM unsigned int CONTINUE_COUNTER_0_OR_VLD : 4; /*!< [11..8] none */ + __IOM unsigned int RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM unsigned int CONTINUE_COUNTER_1_OR_EVENT : 4; /*!< [19..16] For two 16 bit counters mode: OR expression valids for OR event in continue counter event For 32 bit counter mode : Invalid */ - __IM uint32_t RESERVED3 : 4; /*!< [23..20] Reserved3 */ - __IOM uint32_t CONTINUE_COUNTER_1_OR_VLD : 4; /*!< [27..24] none */ - __IM uint32_t RESERVED4 : 4; /*!< [31..28] Reserved4 */ + __IM unsigned int RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM unsigned int CONTINUE_COUNTER_1_OR_VLD : 4; /*!< [27..24] none */ + __IM unsigned int RESERVED4 : 4; /*!< [31..28] Reserved4 */ } CT_CONTINUE_COUNTER_OR_EVENT_b; }; union { - __IOM uint32_t CT_STOP_COUNTER_EVENT_SEL; /*!< (@ 0x00000068) Stop counter + __IOM unsigned int CT_STOP_COUNTER_EVENT_SEL; /*!< (@ 0x00000068) Stop counter event select register */ struct { - __IOM uint32_t STOP_COUNTER_0_EVENT_SEL : 6; /*!< [5..0] For two 16 bit counters + __IOM unsigned int STOP_COUNTER_0_EVENT_SEL : 6; /*!< [5..0] For two 16 bit counters mode: Event select for Stopping the Counter 0 For 32 bit counter mode: Event select for Stopping counter */ - __IOM uint32_t RESERVED1 : 10; /*!< [15..6] Reserved1 */ - __IOM uint32_t STOP_COUNTER_1_EVENT_SEL : 6; /*!< [21..16] For two 16 bit counters + __IOM unsigned int RESERVED1 : 10; /*!< [15..6] Reserved1 */ + __IOM unsigned int STOP_COUNTER_1_EVENT_SEL : 6; /*!< [21..16] For two 16 bit counters mode: Event select for Stopping the Counter 1 For 32 bit counter mode: Invalid */ - __IM uint32_t RESERVED2 : 10; /*!< [31..22] Reserved2 */ + __IM unsigned int RESERVED2 : 10; /*!< [31..22] Reserved2 */ } CT_STOP_COUNTER_EVENT_SEL_b; }; union { - __IOM uint32_t CT_STOP_COUNTER_AND_EVENT; /*!< (@ 0x0000006C) Stop counter + __IOM unsigned int CT_STOP_COUNTER_AND_EVENT; /*!< (@ 0x0000006C) Stop counter AND event register */ struct { - __IOM uint32_t STOP_COUNTER_0_AND_EVENT : 4; /*!< [3..0] For two 16 bit counter mode: + __IOM unsigned int STOP_COUNTER_0_AND_EVENT : 4; /*!< [3..0] For two 16 bit counter mode: AND expression valids for AND event in stop Counter 0 event For 32 bit counter mode AND expression valids for AND event in stop counter event */ - __IOM uint32_t RESERVED1 : 4; /*!< [7..4] Reserved1 */ - __IOM uint32_t STOP_COUNTER_0_AND_VLD : 4; /*!< [11..8] Indicates which + __IOM unsigned int RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM unsigned int STOP_COUNTER_0_AND_VLD : 4; /*!< [11..8] Indicates which bits in 3:0 are valid for considering AND event */ - __IOM uint32_t RESERVED2 : 4; /*!< [15..12] Reserved2 */ - __IOM uint32_t STOP_COUNTER_1_AND_EVENT : 4; /*!< [19..16] For two 16 bit counters + __IOM unsigned int RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM unsigned int STOP_COUNTER_1_AND_EVENT : 4; /*!< [19..16] For two 16 bit counters mode: AND expression valids for AND event in stop counter event For 32 bit counter mode : Invalid */ - __IM uint32_t RESERVED3 : 4; /*!< [23..20] Reserved3 */ - __IOM uint32_t STOP_COUNTER_1_AND_VLD : 4; /*!< [27..24] none */ - __IM uint32_t RESERVED4 : 4; /*!< [31..28] Reserved4 */ + __IM unsigned int RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM unsigned int STOP_COUNTER_1_AND_VLD : 4; /*!< [27..24] none */ + __IM unsigned int RESERVED4 : 4; /*!< [31..28] Reserved4 */ } CT_STOP_COUNTER_AND_EVENT_b; }; union { - __IOM uint32_t CT_STOP_COUNTER_OR_EVENT; /*!< (@ 0x00000070) Stop counter OR + __IOM unsigned int CT_STOP_COUNTER_OR_EVENT; /*!< (@ 0x00000070) Stop counter OR event register */ struct { - __IOM uint32_t STOP_COUNTER_0_OR_EVENT : 4; /*!< [3..0] For two 16 bit counter mode: + __IOM unsigned int STOP_COUNTER_0_OR_EVENT : 4; /*!< [3..0] For two 16 bit counter mode: OR expression valids for OR event in Stop Counter 0 event For 32 bit counter mode OR expression valids for OR event in Stop counter event */ - __IOM uint32_t RESERVED1 : 4; /*!< [7..4] Reserved1 */ - __IOM uint32_t STOP_COUNTER_0_OR_VLD : 4; /*!< [11..8] none */ - __IOM uint32_t RESERVED2 : 4; /*!< [15..12] Reserved2 */ - __IOM uint32_t STOP_COUNTER_1_OR_EVENT : 4; /*!< [19..16] For two 16 bit counters + __IOM unsigned int RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM unsigned int STOP_COUNTER_0_OR_VLD : 4; /*!< [11..8] none */ + __IOM unsigned int RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM unsigned int STOP_COUNTER_1_OR_EVENT : 4; /*!< [19..16] For two 16 bit counters mode: OR expression valids for OR event in Stop counter event For 32 bit counter mode : Invalid */ - __IM uint32_t RESERVED3 : 4; /*!< [23..20] Reserved3 */ - __IOM uint32_t STOP_COUNTER_1_OR_VLD : 4; /*!< [27..24] none */ - __IM uint32_t RESERVED4 : 4; /*!< [31..28] Reserved4 */ + __IM unsigned int RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM unsigned int STOP_COUNTER_1_OR_VLD : 4; /*!< [27..24] none */ + __IM unsigned int RESERVED4 : 4; /*!< [31..28] Reserved4 */ } CT_STOP_COUNTER_OR_EVENT_b; }; union { - __IOM uint32_t CT_HALT_COUNTER_EVENT_SEL; /*!< (@ 0x00000074) Halt counter + __IOM unsigned int CT_HALT_COUNTER_EVENT_SEL; /*!< (@ 0x00000074) Halt counter event select register */ struct { - __IOM uint32_t HALT_COUNTER_0_EVENT_SEL : 6; /*!< [5..0] For two 16 bit counters + __IOM unsigned int HALT_COUNTER_0_EVENT_SEL : 6; /*!< [5..0] For two 16 bit counters mode: Event select for Halting the Counter 0 For 32 bit counter mode: Event select for Halting counter */ - __OM uint32_t RESUME_FROM_HALT_COUNTER_0 : 1; /*!< [6..6] For two 16 bit counters + __OM unsigned int RESUME_FROM_HALT_COUNTER_0 : 1; /*!< [6..6] For two 16 bit counters mode: Event select for Halting the Counter 0 For 32 bit counter mode: Event select for Halting counter */ - __IM uint32_t RESERVED1 : 9; /*!< [15..7] Reserved1 */ - __IOM uint32_t HALT_COUNTER_1_EVENT_SEL : 6; /*!< [21..16] For two 16 bit counters + __IM unsigned int RESERVED1 : 9; /*!< [15..7] Reserved1 */ + __IOM unsigned int HALT_COUNTER_1_EVENT_SEL : 6; /*!< [21..16] For two 16 bit counters mode: Event select for Halting the Counter 1 For 32 bit counter mode: Invalid */ - __OM uint32_t RESUME_FROM_HALT_COUNTER_1 : 1; /*!< [22..22] For two 16 bit + __OM unsigned int RESUME_FROM_HALT_COUNTER_1 : 1; /*!< [22..22] For two 16 bit counters mode: Event select for Halting the Counter 0 For 32 bit counter mode: Event select for Halting counter */ - __IM uint32_t RESERVED2 : 9; /*!< [31..23] Reserved2 */ + __IM unsigned int RESERVED2 : 9; /*!< [31..23] Reserved2 */ } CT_HALT_COUNTER_EVENT_SEL_b; }; union { - __IOM uint32_t CT_HALT_COUNTER_AND_EVENT; /*!< (@ 0x00000078) Halt counter + __IOM unsigned int CT_HALT_COUNTER_AND_EVENT; /*!< (@ 0x00000078) Halt counter AND event register */ struct { - __IOM uint32_t HALT_COUNTER_0_AND_EVENT : 4; /*!< [3..0] For two 16 bit counter mode: + __IOM unsigned int HALT_COUNTER_0_AND_EVENT : 4; /*!< [3..0] For two 16 bit counter mode: AND expression valids for AND event in stop Counter 0 event For 32 bit counter mode AND expression valids for AND event in stop counter event */ - __IOM uint32_t RESERVED1 : 4; /*!< [7..4] Reserved1 */ - __IOM uint32_t HALT_COUNTER_0_AND_VLD : 4; /*!< [11..8] Indicates which + __IOM unsigned int RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM unsigned int HALT_COUNTER_0_AND_VLD : 4; /*!< [11..8] Indicates which bits in 3:0 are valid for considering AND event */ - __IM uint32_t RESERVED2 : 4; /*!< [15..12] Reserved2 */ - __IOM uint32_t HALT_COUNTER_1_AND_EVENT : 4; /*!< [19..16] For two 16 bit counters + __IM unsigned int RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM unsigned int HALT_COUNTER_1_AND_EVENT : 4; /*!< [19..16] For two 16 bit counters mode: AND expression valids for AND event in stop counter event For 32 bit counter mode : Invalid */ - __IM uint32_t RESERVED3 : 4; /*!< [23..20] Reserved3 */ - __IOM uint32_t HALT_COUNTER_1_AND_VLD : 4; /*!< [27..24] none */ - __IM uint32_t RESERVED4 : 4; /*!< [31..28] Reserved4 */ + __IM unsigned int RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM unsigned int HALT_COUNTER_1_AND_VLD : 4; /*!< [27..24] none */ + __IM unsigned int RESERVED4 : 4; /*!< [31..28] Reserved4 */ } CT_HALT_COUNTER_AND_EVENT_b; }; union { - __IOM uint32_t CT_HALT_COUNTER_OR_EVENT; /*!< (@ 0x0000007C) Halt counter OR + __IOM unsigned int CT_HALT_COUNTER_OR_EVENT; /*!< (@ 0x0000007C) Halt counter OR event register */ struct { - __IOM uint32_t HALT_COUNTER_0_OR_EVENT : 4; /*!< [3..0] For two 16 bit counter mode: + __IOM unsigned int HALT_COUNTER_0_OR_EVENT : 4; /*!< [3..0] For two 16 bit counter mode: OR expression valids for OR event in Halt Counter 0 event For 32 bit counter mode OR expression valids for OR event in Halt counter event */ - __IOM uint32_t RESERVED1 : 4; /*!< [7..4] Reserved1 */ - __IOM uint32_t HALT_COUNTER_0_OR_VLD : 4; /*!< [11..8] none */ - __IM uint32_t RESERVED2 : 4; /*!< [15..12] Reserved2 */ - __IOM uint32_t HALT_COUNTER_1_OR_EVENT : 4; /*!< [19..16] For two 16 bit counters + __IOM unsigned int RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM unsigned int HALT_COUNTER_0_OR_VLD : 4; /*!< [11..8] none */ + __IM unsigned int RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM unsigned int HALT_COUNTER_1_OR_EVENT : 4; /*!< [19..16] For two 16 bit counters mode: OR expression valids for OR event in Halt counter event For 32 bit counter mode : Invalid */ - __IM uint32_t RESERVED3 : 4; /*!< [23..20] Reserved3 */ - __IOM uint32_t HALT_COUNTER_1_OR_VLD : 4; /*!< [27..24] none */ - __IM uint32_t RESERVED4 : 4; /*!< [31..28] Reserved4 */ + __IM unsigned int RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM unsigned int HALT_COUNTER_1_OR_VLD : 4; /*!< [27..24] none */ + __IM unsigned int RESERVED4 : 4; /*!< [31..28] Reserved4 */ } CT_HALT_COUNTER_OR_EVENT_b; }; union { - __IOM uint32_t CT_INCREMENT_COUNTER_EVENT_SEL; /*!< (@ 0x00000080) Increment counter + __IOM unsigned int CT_INCREMENT_COUNTER_EVENT_SEL; /*!< (@ 0x00000080) Increment counter event select register */ struct { - __IOM uint32_t INCREMENT_COUNTER_0_EVENT_SEL : 6; /*!< [5..0] For two 16 bit counters + __IOM unsigned int INCREMENT_COUNTER_0_EVENT_SEL : 6; /*!< [5..0] For two 16 bit counters mode: Event select for Incrementing the Counter 0 For 32 bit counter mode: Event select for Incrementing counter */ - __IM uint32_t RESERVED1 : 10; /*!< [15..6] Reserved1 */ - __IOM uint32_t INCREMENT_COUNTER_1_EVENT_SEL : 6; /*!< [21..16] For two 16 + __IM unsigned int RESERVED1 : 10; /*!< [15..6] Reserved1 */ + __IOM unsigned int INCREMENT_COUNTER_1_EVENT_SEL : 6; /*!< [21..16] For two 16 bit counters mode: Event select for Incrementing the Counter 1 For 32 bit counter mode: Invalid */ - __IM uint32_t RESERVED2 : 10; /*!< [31..22] Reserved2 */ + __IM unsigned int RESERVED2 : 10; /*!< [31..22] Reserved2 */ } CT_INCREMENT_COUNTER_EVENT_SEL_b; }; union { - __IOM uint32_t CT_INCREMENT_COUNTER_AND_EVENT; /*!< (@ 0x00000084) Increment counter + __IOM unsigned int CT_INCREMENT_COUNTER_AND_EVENT; /*!< (@ 0x00000084) Increment counter AND event register */ struct { - __IOM uint32_t INCREMENT_COUNTER_0_AND_EVENT : 4; /*!< [3..0] For two 16 bit counter + __IOM unsigned int INCREMENT_COUNTER_0_AND_EVENT : 4; /*!< [3..0] For two 16 bit counter mode: AND expression valids for AND event in stop Counter 0 event For 32 bit counter mode AND expression valids for AND event in stop counter event */ - __IOM uint32_t RESERVED1 : 4; /*!< [7..4] Reserved1 */ - __IOM uint32_t INCREMENT_COUNTER_0_AND_VLD : 4; /*!< [11..8] none */ - __IM uint32_t RESERVED2 : 4; /*!< [15..12] Reserved2 */ - __IOM uint32_t INCREMENT_COUNTER_1_AND_EVENT : 4; /*!< [19..16] For two 16 bit + __IOM unsigned int RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM unsigned int INCREMENT_COUNTER_0_AND_VLD : 4; /*!< [11..8] none */ + __IM unsigned int RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM unsigned int INCREMENT_COUNTER_1_AND_EVENT : 4; /*!< [19..16] For two 16 bit counters mode: AND expression valids for AND event in stop counter event For 32 bit counter mode : Invalid */ - __IM uint32_t RESERVED3 : 4; /*!< [23..20] Reserved3 */ - __IOM uint32_t INCREMENT_COUNTER_1_AND_VLD : 4; /*!< [27..24] none */ - __IM uint32_t RESERVED4 : 4; /*!< [31..28] Reserved4 */ + __IM unsigned int RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM unsigned int INCREMENT_COUNTER_1_AND_VLD : 4; /*!< [27..24] none */ + __IM unsigned int RESERVED4 : 4; /*!< [31..28] Reserved4 */ } CT_INCREMENT_COUNTER_AND_EVENT_b; }; union { - __IOM uint32_t CT_INCREMENT_COUNTER_OR_EVENT; /*!< (@ 0x00000088) Increment counter OR + __IOM unsigned int CT_INCREMENT_COUNTER_OR_EVENT; /*!< (@ 0x00000088) Increment counter OR event register */ struct { - __IOM uint32_t INCREMENT_COUNTER_0_OR_EVENT : 4; /*!< [3..0] For two 16 bit counter + __IOM unsigned int INCREMENT_COUNTER_0_OR_EVENT : 4; /*!< [3..0] For two 16 bit counter mode: OR expression valids for OR event in Increment Counter 0 event For 32 bit counter mode OR expression valids for OR event in Increment counter event */ - __IOM uint32_t RESERVED1 : 4; /*!< [7..4] Reserved1 */ - __IOM uint32_t INCREMENT_COUNTER_0_OR_VLD : 4; /*!< [11..8] none */ - __IM uint32_t RESERVED2 : 4; /*!< [15..12] Reserved2 */ - __IOM uint32_t INCREMENT_COUNTER_1_OR_EVENT : 4; /*!< [19..16] For two 16 bit + __IOM unsigned int RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM unsigned int INCREMENT_COUNTER_0_OR_VLD : 4; /*!< [11..8] none */ + __IM unsigned int RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM unsigned int INCREMENT_COUNTER_1_OR_EVENT : 4; /*!< [19..16] For two 16 bit counters mode: OR expression valids for OR event in Increment counter event For 32 bit counter mode : Invalid */ - __IM uint32_t RESERVED4 : 4; /*!< [23..20] Reserved4 */ - __IOM uint32_t INCREMENT_COUNTER_1_OR_VLD : 4; /*!< [27..24] none */ - __IM uint32_t RESERVED5 : 4; /*!< [31..28] Reserved5 */ + __IM unsigned int RESERVED4 : 4; /*!< [23..20] Reserved4 */ + __IOM unsigned int INCREMENT_COUNTER_1_OR_VLD : 4; /*!< [27..24] none */ + __IM unsigned int RESERVED5 : 4; /*!< [31..28] Reserved5 */ } CT_INCREMENT_COUNTER_OR_EVENT_b; }; union { - __IOM uint32_t CT_CAPTURE_COUNTER_EVENT_SEL; /*!< (@ 0x0000008C) Capture counter event + __IOM unsigned int CT_CAPTURE_COUNTER_EVENT_SEL; /*!< (@ 0x0000008C) Capture counter event select register */ struct { - __IOM uint32_t CAPTURE_COUNTER_0_EVENT_SEL : 6; /*!< [5..0] For two 16 bit counters + __IOM unsigned int CAPTURE_COUNTER_0_EVENT_SEL : 6; /*!< [5..0] For two 16 bit counters mode: Event select for Capturing the Counter 0 For 32 bit counter mode: Event select for Capturing counter */ - __IM uint32_t RESERVED1 : 10; /*!< [15..6] Reserved1 */ - __IOM uint32_t CAPTURE_COUNTER_1_EVENT_SEL : 6; /*!< [21..16] For two 16 bit counters + __IM unsigned int RESERVED1 : 10; /*!< [15..6] Reserved1 */ + __IOM unsigned int CAPTURE_COUNTER_1_EVENT_SEL : 6; /*!< [21..16] For two 16 bit counters mode: Event select for Capturing the Counter 1 For 32 bit counter mode : Invalid */ - __IM uint32_t RESERVED2 : 10; /*!< [31..22] Reserved2 */ + __IM unsigned int RESERVED2 : 10; /*!< [31..22] Reserved2 */ } CT_CAPTURE_COUNTER_EVENT_SEL_b; }; union { - __IOM uint32_t CT_CAPTURE_COUNTER_AND_EVENT; /*!< (@ 0x00000090) Capture counter AND + __IOM unsigned int CT_CAPTURE_COUNTER_AND_EVENT; /*!< (@ 0x00000090) Capture counter AND event register */ struct { __IOM - uint32_t CAPTURE_COUNTER_0_AND_EVENT : 4; /*!< [3..0] For two 16 bit + unsigned int CAPTURE_COUNTER_0_AND_EVENT : 4; /*!< [3..0] For two 16 bit counter mode: AND expression valids for AND event in stop Counter 0 event For 32 bit counter mode AND expression valids for AND event in stop counter event */ - __IOM uint32_t RESERVED1 : 4; /*!< [7..4] Reserved1 */ - __IOM uint32_t CAPTURE_COUNTER_0_AND_VLD : 4; /*!< [11..8] none */ - __IM uint32_t RESERVED2 : 4; /*!< [15..12] Reserved2 */ - __IOM uint32_t CAPTURE_COUNTER_1_AND_EVENT : 4; /*!< [19..16] For two 16 bit counters + __IOM unsigned int RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM unsigned int CAPTURE_COUNTER_0_AND_VLD : 4; /*!< [11..8] none */ + __IM unsigned int RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM unsigned int CAPTURE_COUNTER_1_AND_EVENT : 4; /*!< [19..16] For two 16 bit counters mode: AND expression valids for AND event in stop counter event For 32 bit counter mode : Invalid */ - __IM uint32_t RESERVED3 : 4; /*!< [23..20] Reserved3 */ - __IOM uint32_t CAPTURE_COUNTER_1_AND_VLD : 4; /*!< [27..24] none */ - __IM uint32_t RESERVED4 : 4; /*!< [31..28] Reserved4 */ + __IM unsigned int RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM unsigned int CAPTURE_COUNTER_1_AND_VLD : 4; /*!< [27..24] none */ + __IM unsigned int RESERVED4 : 4; /*!< [31..28] Reserved4 */ } CT_CAPTURE_COUNTER_AND_EVENT_b; }; union { - __IOM uint32_t CT_CAPTURE_COUNTER_OR_EVENT; /*!< (@ 0x00000094) Capture counter OR + __IOM unsigned int CT_CAPTURE_COUNTER_OR_EVENT; /*!< (@ 0x00000094) Capture counter OR event register */ struct { - __IOM uint32_t CAPTURE_COUNTER_0_OR_EVENT : 4; /*!< [3..0] For two 16 bit counter + __IOM unsigned int CAPTURE_COUNTER_0_OR_EVENT : 4; /*!< [3..0] For two 16 bit counter mode: OR expression valids for OR event in Capture Counter 0 event For 32 bit counter mode OR expression valids for OR event in Capture counter event */ - __IOM uint32_t RESERVED1 : 4; /*!< [7..4] Reserved1 */ - __IOM uint32_t CAPTURE_COUNTER_0_OR_VLD : 4; /*!< [11..8] none */ - __IM uint32_t RESERVED2 : 4; /*!< [15..12] Reserved2 */ - __IOM uint32_t CAPTURE_COUNTER_1_OR_EVENT : 4; /*!< [19..16] For two 16 bit counters + __IOM unsigned int RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM unsigned int CAPTURE_COUNTER_0_OR_VLD : 4; /*!< [11..8] none */ + __IM unsigned int RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM unsigned int CAPTURE_COUNTER_1_OR_EVENT : 4; /*!< [19..16] For two 16 bit counters mode: OR expression valids for OR event in Capture counter event For 32 bit counter mode : Invalid */ - __IM uint32_t RESERVED3 : 4; /*!< [23..20] Reserved3 */ - __IOM uint32_t CAPTURE_COUNTER_1_OR_VLD : 4; /*!< [27..24] none */ - __IM uint32_t RESERVED4 : 4; /*!< [31..28] Reserved4 */ + __IM unsigned int RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM unsigned int CAPTURE_COUNTER_1_OR_VLD : 4; /*!< [27..24] none */ + __IM unsigned int RESERVED4 : 4; /*!< [31..28] Reserved4 */ } CT_CAPTURE_COUNTER_OR_EVENT_b; }; union { - __IOM uint32_t CT_OUTPUT_EVENT_SEL; /*!< (@ 0x00000098) Output event select + __IOM unsigned int CT_OUTPUT_EVENT_SEL; /*!< (@ 0x00000098) Output event select register */ struct { - __IOM uint32_t OUTPUT_EVENT_SEL_0 : 6; /*!< [5..0] For two 16 bit counters mode: + __IOM unsigned int OUTPUT_EVENT_SEL_0 : 6; /*!< [5..0] For two 16 bit counters mode: Event select for output event from Counter 0 For 32 bit counter mode: Event select for output event */ - __IM uint32_t RESERVED1 : 10; /*!< [15..6] Reserved1 */ - __IOM uint32_t OUTPUT_EVENT_SEL_1 : 6; /*!< [21..16] For two 16 bit counters mode: + __IM unsigned int RESERVED1 : 10; /*!< [15..6] Reserved1 */ + __IOM unsigned int OUTPUT_EVENT_SEL_1 : 6; /*!< [21..16] For two 16 bit counters mode: Event select for output event from counter 1 For 32 bit counter mode : Invalid */ - __IM uint32_t RESERVED2 : 10; /*!< [31..22] Reserved2 */ + __IM unsigned int RESERVED2 : 10; /*!< [31..22] Reserved2 */ } CT_OUTPUT_EVENT_SEL_b; }; union { - __IOM uint32_t CT_OUTPUT_AND_EVENT_REG; /*!< (@ 0x0000009C) Output AND event + __IOM unsigned int CT_OUTPUT_AND_EVENT_REG; /*!< (@ 0x0000009C) Output AND event Register */ struct { - __IOM uint32_t OUTPUT_0_AND_EVENT : 4; /*!< [3..0] AND expression for AND event in + __IOM unsigned int OUTPUT_0_AND_EVENT : 4; /*!< [3..0] AND expression for AND event in output Counter_0 event. */ - __IOM uint32_t RESERVED1 : 4; /*!< [7..4] Reserved1 */ - __IOM uint32_t OUTPUT_0_AND_VLD : 4; /*!< [11..8] AND expression for AND event in + __IOM unsigned int RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM unsigned int OUTPUT_0_AND_VLD : 4; /*!< [11..8] AND expression for AND event in output Counter_0 event. */ - __IM uint32_t RESERVED2 : 4; /*!< [15..12] Reserved2 */ - __IOM uint32_t OUTPUT_1_AND_EVENT : 4; /*!< [19..16] AND expression for AND event in + __IM unsigned int RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM unsigned int OUTPUT_1_AND_EVENT : 4; /*!< [19..16] AND expression for AND event in output Counter_1 event. */ - __IM uint32_t RESERVED3 : 4; /*!< [23..20] Reserved3 */ - __IOM uint32_t OUTPUT_1_AND_VLD : 4; /*!< [27..24] AND expression for AND event in + __IM unsigned int RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM unsigned int OUTPUT_1_AND_VLD : 4; /*!< [27..24] AND expression for AND event in output Counter_1 event. */ - __IM uint32_t RESERVED4 : 4; /*!< [31..28] Reserved4 */ + __IM unsigned int RESERVED4 : 4; /*!< [31..28] Reserved4 */ } CT_OUTPUT_AND_EVENT_REG_b; }; union { - __IOM uint32_t CT_OUTPUT_OR_EVENT; /*!< (@ 0x000000A0) Output OR event Register */ + __IOM unsigned int CT_OUTPUT_OR_EVENT; /*!< (@ 0x000000A0) Output OR event Register */ struct { - __IOM uint32_t OUTPUT_0_OR_EVENT : 4; /*!< [3..0] OR expression for OR event in + __IOM unsigned int OUTPUT_0_OR_EVENT : 4; /*!< [3..0] OR expression for OR event in output Counter_0 event */ - __IOM uint32_t RESERVED1 : 4; /*!< [7..4] Reserved1 */ - __IOM uint32_t OUTPUT_0_OR_VLD : 4; /*!< [11..8] Indicates which bits in 3:0 are + __IOM unsigned int RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM unsigned int OUTPUT_0_OR_VLD : 4; /*!< [11..8] Indicates which bits in 3:0 are valid for considering OR event */ - __IM uint32_t RESERVED2 : 4; /*!< [15..12] Reserved2 */ - __IOM uint32_t OUTPUT_1_OR_EVENT : 4; /*!< [19..16] OR expression for OR event in + __IM unsigned int RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM unsigned int OUTPUT_1_OR_EVENT : 4; /*!< [19..16] OR expression for OR event in output Counter_0 event */ - __IM uint32_t RESERVED3 : 4; /*!< [23..20] Reserved3 */ - __IOM uint32_t OUTPUT_1_OR_VLD : 4; /*!< [27..24] Indicates which bits in 3:0 are + __IM unsigned int RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM unsigned int OUTPUT_1_OR_VLD : 4; /*!< [27..24] Indicates which bits in 3:0 are valid for considering OR event */ - __IM uint32_t RESERVED4 : 4; /*!< [31..28] Reserved4 */ + __IM unsigned int RESERVED4 : 4; /*!< [31..28] Reserved4 */ } CT_OUTPUT_OR_EVENT_b; }; union { - __IOM uint32_t CT_INTR_EVENT_SEL; /*!< (@ 0x000000A4) Interrupt Event Select + __IOM unsigned int CT_INTR_EVENT_SEL; /*!< (@ 0x000000A4) Interrupt Event Select Register */ struct { - __IOM uint32_t INTR_EVENT_SEL_0 : 6; /*!< [5..0] For two 16 bit counters mode: Event + __IOM unsigned int INTR_EVENT_SEL_0 : 6; /*!< [5..0] For two 16 bit counters mode: Event select for interrupt event from Counter 0 For 32 bit counter mode: Event select for output event */ - __IM uint32_t RESERVED1 : 10; /*!< [15..6] Reserved1 */ - __IOM uint32_t INTR_EVENT_SEL_1 : 6; /*!< [21..16] For two 16 bit counters + __IM unsigned int RESERVED1 : 10; /*!< [15..6] Reserved1 */ + __IOM unsigned int INTR_EVENT_SEL_1 : 6; /*!< [21..16] For two 16 bit counters mode: Event select for interrupt event from counter 1 For 32 bit counter mode : Invalid */ - __IM uint32_t RESERVED2 : 10; /*!< [31..22] Reserved2 */ + __IM unsigned int RESERVED2 : 10; /*!< [31..22] Reserved2 */ } CT_INTR_EVENT_SEL_b; }; union { - __IOM uint32_t CT_INTR_AND_EVENT; /*!< (@ 0x000000A8) Interrupt AND Event Register */ + __IOM unsigned int CT_INTR_AND_EVENT; /*!< (@ 0x000000A8) Interrupt AND Event Register */ struct { - __IOM uint32_t INTR_0_AND_EVENT : 4; /*!< [3..0] None */ - __IOM uint32_t RESERVED1 : 4; /*!< [7..4] Reserved1 */ - __IOM uint32_t INTR_0_AND_VLD : 4; /*!< [11..8] None */ - __IM uint32_t RESERVED2 : 4; /*!< [15..12] Reserved2 */ - __IOM uint32_t INTR_1_AND_EVENT : 4; /*!< [19..16] None */ - __IM uint32_t RESERVED3 : 4; /*!< [23..20] Reserved3 */ - __IOM uint32_t INTR_1_AND_VLD : 4; /*!< [27..24] None */ - __IM uint32_t RESERVED4 : 4; /*!< [31..28] Reserved4 */ + __IOM unsigned int INTR_0_AND_EVENT : 4; /*!< [3..0] None */ + __IOM unsigned int RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM unsigned int INTR_0_AND_VLD : 4; /*!< [11..8] None */ + __IM unsigned int RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM unsigned int INTR_1_AND_EVENT : 4; /*!< [19..16] None */ + __IM unsigned int RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM unsigned int INTR_1_AND_VLD : 4; /*!< [27..24] None */ + __IM unsigned int RESERVED4 : 4; /*!< [31..28] Reserved4 */ } CT_INTR_AND_EVENT_b; }; union { - __IOM uint32_t CT_INTR_OR_EVENT_REG; /*!< (@ 0x000000AC) Interrupt OR Event + __IOM unsigned int CT_INTR_OR_EVENT_REG; /*!< (@ 0x000000AC) Interrupt OR Event Register */ struct { - __IOM uint32_t INTR_0_OR_EVENT : 4; /*!< [3..0] None */ - __IOM uint32_t RESERVED1 : 4; /*!< [7..4] Reserved1 */ - __IOM uint32_t INTR_0_OR_VLD : 4; /*!< [11..8] None */ - __IM uint32_t RESERVED2 : 4; /*!< [15..12] Reserved2 */ - __IOM uint32_t INTR_1_OR_EVENT : 4; /*!< [19..16] None */ - __IM uint32_t RESERVED3 : 4; /*!< [23..20] Reserved3 */ - __IOM uint32_t INTR_1_OR_VLD : 4; /*!< [27..24] None */ - __IM uint32_t RESERVED4 : 4; /*!< [31..28] Reserved4 */ + __IOM unsigned int INTR_0_OR_EVENT : 4; /*!< [3..0] None */ + __IOM unsigned int RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM unsigned int INTR_0_OR_VLD : 4; /*!< [11..8] None */ + __IM unsigned int RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM unsigned int INTR_1_OR_EVENT : 4; /*!< [19..16] None */ + __IM unsigned int RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM unsigned int INTR_1_OR_VLD : 4; /*!< [27..24] None */ + __IM unsigned int RESERVED4 : 4; /*!< [31..28] Reserved4 */ } CT_INTR_OR_EVENT_REG_b; }; } CT0_Type; /*!< Size = 176 (0xb0) */ @@ -8723,77 +8723,77 @@ typedef struct { /*!< (@ 0x45060000) CT0 Structure */ typedef struct { /*!< (@ 0x4506F000) CT_MUX_REG Structure */ union { - __IOM uint32_t CT_MUX_SEL_0_REG; /*!< (@ 0x00000000) MUX_SEL_0_REG Register */ + __IOM unsigned int CT_MUX_SEL_0_REG; /*!< (@ 0x00000000) MUX_SEL_0_REG Register */ struct { - __IOM uint32_t MUX_SEL_0 : 4; /*!< [3..0] Select value to select first output value + __IOM unsigned int MUX_SEL_0 : 4; /*!< [3..0] Select value to select first output value fifo_0_full[0] out of all the fifo_0_full_muxed signals of counter 0 */ - __IOM uint32_t RESERVED1 : 28; /*!< [31..4] Reserved1 */ + __IOM unsigned int RESERVED1 : 28; /*!< [31..4] Reserved1 */ } CT_MUX_SEL_0_REG_b; }; union { - __IOM uint32_t CT_MUX_SEL_1_REG; /*!< (@ 0x00000004) MUX_SEL_1_REG Register */ + __IOM unsigned int CT_MUX_SEL_1_REG; /*!< (@ 0x00000004) MUX_SEL_1_REG Register */ struct { - __IOM uint32_t MUX_SEL_1 : 4; /*!< [3..0] Select value to select first output value + __IOM unsigned int MUX_SEL_1 : 4; /*!< [3..0] Select value to select first output value fifo_0_full[1] out of all the fifo_0_full_muxed signals of counter 0 */ - __IOM uint32_t RESERVED1 : 28; /*!< [31..4] Reserved1 */ + __IOM unsigned int RESERVED1 : 28; /*!< [31..4] Reserved1 */ } CT_MUX_SEL_1_REG_b; }; union { - __IOM uint32_t CT_MUX_SEL_2_REG; /*!< (@ 0x00000008) MUX_SEL_2_REG Register */ + __IOM unsigned int CT_MUX_SEL_2_REG; /*!< (@ 0x00000008) MUX_SEL_2_REG Register */ struct { - __IOM uint32_t MUX_SEL_2 : 4; /*!< [3..0] Select value to select first output value + __IOM unsigned int MUX_SEL_2 : 4; /*!< [3..0] Select value to select first output value fifo_1_full[0] out of all the fifo_1_full_muxed signals of counter 1 */ - __IOM uint32_t RESERVED1 : 28; /*!< [31..4] Reserved1 */ + __IOM unsigned int RESERVED1 : 28; /*!< [31..4] Reserved1 */ } CT_MUX_SEL_2_REG_b; }; union { - __IOM uint32_t CT_MUX_SEL_3_REG; /*!< (@ 0x0000000C) MUX_SEL_3_REG Register */ + __IOM unsigned int CT_MUX_SEL_3_REG; /*!< (@ 0x0000000C) MUX_SEL_3_REG Register */ struct { - __IOM uint32_t MUX_SEL_3 : 4; /*!< [3..0] Select value to select first output value + __IOM unsigned int MUX_SEL_3 : 4; /*!< [3..0] Select value to select first output value fifo_1_full[1] out of all the fifo_1_full_muxed signals of counter 1 */ - __IOM uint32_t RESERVED1 : 28; /*!< [31..4] Reserved1 */ + __IOM unsigned int RESERVED1 : 28; /*!< [31..4] Reserved1 */ } CT_MUX_SEL_3_REG_b; }; - __IM uint32_t RESERVED[2]; + __IM unsigned int RESERVED[2]; union { - __IOM uint32_t CT_OUTPUT_EVENT1_ADC_SEL; /*!< (@ 0x00000018) OUTPUT_EVENT_ADC_SEL + __IOM unsigned int CT_OUTPUT_EVENT1_ADC_SEL; /*!< (@ 0x00000018) OUTPUT_EVENT_ADC_SEL Register */ struct { __IOM - uint32_t OUTPUT_EVENT_ADC_SEL : 4; /*!< [3..0] Select signals to select one + unsigned int OUTPUT_EVENT_ADC_SEL : 4; /*!< [3..0] Select signals to select one output event out of all the output events output_event_0 output_event_1, output_event_2, output_event_3 to enable ADC module */ - __IOM uint32_t RESERVED1 : 28; /*!< [31..4] Reserved1 */ + __IOM unsigned int RESERVED1 : 28; /*!< [31..4] Reserved1 */ } CT_OUTPUT_EVENT1_ADC_SEL_b; }; union { - __IOM uint32_t CT_OUTPUT_EVENT2_ADC_SEL; /*!< (@ 0x0000001C) OUTPUT_EVENT_ADC_SEL + __IOM unsigned int CT_OUTPUT_EVENT2_ADC_SEL; /*!< (@ 0x0000001C) OUTPUT_EVENT_ADC_SEL Register */ struct { __IOM - uint32_t OUTPUT_EVENT_ADC_SEL : 4; /*!< [3..0] Select signals to select one + unsigned int OUTPUT_EVENT_ADC_SEL : 4; /*!< [3..0] Select signals to select one output event out of all the output events output_event_0 output_event_1, output_event_2, output_event_3 to enable ADC module */ - __IOM uint32_t RESERVED1 : 28; /*!< [31..4] Reserved1 */ + __IOM unsigned int RESERVED1 : 28; /*!< [31..4] Reserved1 */ } CT_OUTPUT_EVENT2_ADC_SEL_b; }; } CT_MUX_REG_Type; /*!< Size = 32 (0x20) */ @@ -8811,9 +8811,9 @@ typedef struct { /*!< (@ 0x4506F000) CT_MUX_REG Structure */ typedef struct { /*!< (@ 0x46130000) EGPIO Structure */ __IOM EGPIO_PIN_CONFIG_Type PIN_CONFIG[80]; /*!< (@ 0x00000000) [0..79] */ - __IM uint32_t RESERVED[704]; + __IM unsigned int RESERVED[704]; __IOM EGPIO_PORT_CONFIG_Type PORT_CONFIG[6]; /*!< (@ 0x00001000) [0..5] */ - __IM uint32_t RESERVED1[80]; + __IM unsigned int RESERVED1[80]; __IOM EGPIO_INTR_Type INTR[8]; /*!< (@ 0x00001200) [0..7] */ __IOM EGPIO_GPIO_GRP_INTR_Type GPIO_GRP_INTR[4]; /*!< (@ 0x00001240) [0..3] */ } EGPIO_Type; /*!< Size = 4704 (0x1260) */ @@ -8834,755 +8834,755 @@ typedef struct { /*!< (@ 0x46130000) EGPIO Structur typedef struct { /*!< (@ 0x40000000) SDIO0 Structure */ union { - __IOM uint32_t SDIO_INTR_FN1_STATUS_CLEAR_REG; /*!< (@ 0x00000000) SDIO Function1 + __IOM unsigned int SDIO_INTR_FN1_STATUS_CLEAR_REG; /*!< (@ 0x00000000) SDIO Function1 Interrupt Enable Register */ struct { - __IOM uint32_t SDIO_WR_INT_CLR : 1; /*!< [0..0] This bit is used to enable + __IOM unsigned int SDIO_WR_INT_CLR : 1; /*!< [0..0] This bit is used to enable CMD53 write interrupt. =1 Interrupt is enabled =0 - Interrupt is disabled */ - __IOM uint32_t SDIO_RD_INT_CLR : 1; /*!< [1..1] This bit is used to enable + __IOM unsigned int SDIO_RD_INT_CLR : 1; /*!< [1..1] This bit is used to enable CMD53 read interrupt */ - __IOM uint32_t SDIO_CSA_INT_CLR : 1; /*!< [2..2] This bit is used to + __IOM unsigned int SDIO_CSA_INT_CLR : 1; /*!< [2..2] This bit is used to enable CMD53 CSA interrupt */ - __IOM uint32_t SDIO_CMD52_INT_CLR : 1; /*!< [3..3] This bit is used to + __IOM unsigned int SDIO_CMD52_INT_CLR : 1; /*!< [3..3] This bit is used to enable CMD52 interrupt */ - __IOM uint32_t SDIO_PWR_LEV_INT_CLR : 1; /*!< [4..4] This bit is used to enable power + __IOM unsigned int SDIO_PWR_LEV_INT_CLR : 1; /*!< [4..4] This bit is used to enable power level change interrupt */ - __IOM uint32_t SDIO_CRC_ERR_INT_CLR : 1; /*!< [5..5] This bit is used to enable CRC + __IOM unsigned int SDIO_CRC_ERR_INT_CLR : 1; /*!< [5..5] This bit is used to enable CRC error interrupt */ - __IOM uint32_t SDIO_ABORT_INT_CLR : 1; /*!< [6..6] This bit is used to + __IOM unsigned int SDIO_ABORT_INT_CLR : 1; /*!< [6..6] This bit is used to enable abort interrupt */ - __IOM uint32_t SDIO_TOUT_INT_CLR : 1; /*!< [7..7] This bit is used to enable ?read + __IOM unsigned int SDIO_TOUT_INT_CLR : 1; /*!< [7..7] This bit is used to enable ?read FIFO wait time over? interrupt */ - __IOM uint32_t SDIO_WR_RDZ : 1; /*!< [8..8] SDIO_WR_RDZ */ - __IOM uint32_t SDIO_CSA_ACCESS : 1; /*!< [9..9] csa_window_access When set, indicates + __IOM unsigned int SDIO_WR_RDZ : 1; /*!< [8..8] SDIO_WR_RDZ */ + __IOM unsigned int SDIO_CSA_ACCESS : 1; /*!< [9..9] csa_window_access When set, indicates that current request is for CSA window register. This is only status signal */ - __IOM uint32_t RES : 22; /*!< [31..10] reserved1 */ + __IOM unsigned int RES : 22; /*!< [31..10] reserved1 */ } SDIO_INTR_FN1_STATUS_CLEAR_REG_b; }; union { - __IOM uint32_t SDIO_INTR_FN1_ENABLE_REG; /*!< (@ 0x00000004) SDIO Function1 + __IOM unsigned int SDIO_INTR_FN1_ENABLE_REG; /*!< (@ 0x00000004) SDIO Function1 Interrupt Enable Register */ struct { - __IOM uint32_t SDIO_WR_INT_EN : 1; /*!< [0..0] This bit is used to enable + __IOM unsigned int SDIO_WR_INT_EN : 1; /*!< [0..0] This bit is used to enable CMD53 write interrupt. */ - __IOM uint32_t SDIO_RD_INT_EN : 1; /*!< [1..1] This bit is used to enable + __IOM unsigned int SDIO_RD_INT_EN : 1; /*!< [1..1] This bit is used to enable CMD53 read interrupt */ - __IOM uint32_t SDIO_CSA_INT_EN : 1; /*!< [2..2] This bit is used to enable + __IOM unsigned int SDIO_CSA_INT_EN : 1; /*!< [2..2] This bit is used to enable CMD53 CSA interrupt */ - __IOM uint32_t SDIO_CMD52_INT_EN : 1; /*!< [3..3] This bit is used to + __IOM unsigned int SDIO_CMD52_INT_EN : 1; /*!< [3..3] This bit is used to enable CMD52 interrupt */ - __IOM uint32_t SDIO_PWR_LEV_INT_EN : 1; /*!< [4..4] This bit is used to enable power + __IOM unsigned int SDIO_PWR_LEV_INT_EN : 1; /*!< [4..4] This bit is used to enable power level change interrupt */ - __IOM uint32_t SDIO_CRC_ERR_INT_EN : 1; /*!< [5..5] This bit is used to + __IOM unsigned int SDIO_CRC_ERR_INT_EN : 1; /*!< [5..5] This bit is used to enable CRC error interrupt */ - __IOM uint32_t SDIO_ABORT_INT_EN : 1; /*!< [6..6] This bit is used to + __IOM unsigned int SDIO_ABORT_INT_EN : 1; /*!< [6..6] This bit is used to enable abort interrupt */ - __IOM uint32_t SDIO_TOUT_INT_EN : 1; /*!< [7..7] This bit is used to enable ?read + __IOM unsigned int SDIO_TOUT_INT_EN : 1; /*!< [7..7] This bit is used to enable ?read FIFO wait time over? interrupt */ - __IOM uint32_t RES : 24; /*!< [31..8] reserved5 */ + __IOM unsigned int RES : 24; /*!< [31..8] reserved5 */ } SDIO_INTR_FN1_ENABLE_REG_b; }; union { - __IOM uint32_t SDIO_INTR_FN1_MASK_REG; /*!< (@ 0x00000008) SDIO Function1 + __IOM unsigned int SDIO_INTR_FN1_MASK_REG; /*!< (@ 0x00000008) SDIO Function1 Interrupt Mask Register */ struct { - __IOM uint32_t SDIO_WR_INT_MSK : 1; /*!< [0..0] This bit is used to mask + __IOM unsigned int SDIO_WR_INT_MSK : 1; /*!< [0..0] This bit is used to mask CMD53 write interrupt */ - __IOM uint32_t SDIO_RD_INT_MSK : 1; /*!< [1..1] This bit is used to mask + __IOM unsigned int SDIO_RD_INT_MSK : 1; /*!< [1..1] This bit is used to mask CMD53 read interrupt */ - __IOM uint32_t SDIO_CSA_MSK : 1; /*!< [2..2] This bit is used to mask CMD53 CSA + __IOM unsigned int SDIO_CSA_MSK : 1; /*!< [2..2] This bit is used to mask CMD53 CSA interrupt.Setting this bit will mask the interrupt Clearing this bit has no effect */ - __IOM uint32_t SDIO_CMD52_MSK : 1; /*!< [3..3] This bit is used to mask + __IOM unsigned int SDIO_CMD52_MSK : 1; /*!< [3..3] This bit is used to mask CMD52 interrupt */ - __IOM uint32_t SDIO_PWR_LEV_MSK : 1; /*!< [4..4] This bit is used to mask + __IOM unsigned int SDIO_PWR_LEV_MSK : 1; /*!< [4..4] This bit is used to mask power level change interrupt */ - __IOM uint32_t SDIO_CRC_ERR_MSK : 1; /*!< [5..5] This bit is used to mask + __IOM unsigned int SDIO_CRC_ERR_MSK : 1; /*!< [5..5] This bit is used to mask CRC error interrupt */ - __IOM uint32_t SDIO_ABORT_MSK : 1; /*!< [6..6] This bit is used to mask abort + __IOM unsigned int SDIO_ABORT_MSK : 1; /*!< [6..6] This bit is used to mask abort interrupt Setting this bit will mask the interrupt Clearing this bit has no effect */ - __IOM uint32_t SDIO_TOUT_MSK : 1; /*!< [7..7] This bit is used to mask read FIFO wait + __IOM unsigned int SDIO_TOUT_MSK : 1; /*!< [7..7] This bit is used to mask read FIFO wait time over interrupt */ - __IOM uint32_t RES : 24; /*!< [31..8] reserved5 */ + __IOM unsigned int RES : 24; /*!< [31..8] reserved5 */ } SDIO_INTR_FN1_MASK_REG_b; }; union { - __IOM uint32_t SDIO_INTR_FN1_UNMASK_REG; /*!< (@ 0x0000000C) SDIO Function1 + __IOM unsigned int SDIO_INTR_FN1_UNMASK_REG; /*!< (@ 0x0000000C) SDIO Function1 Interrupt UnMask Register */ struct { - __IOM uint32_t SDIO_WR_INT_UNMSK : 1; /*!< [0..0] This bit is used to + __IOM unsigned int SDIO_WR_INT_UNMSK : 1; /*!< [0..0] This bit is used to unmask CMD53 write interrupt */ - __IOM uint32_t SDIO_RD_INT_UNMSK : 1; /*!< [1..1] This bit is used to + __IOM unsigned int SDIO_RD_INT_UNMSK : 1; /*!< [1..1] This bit is used to unmask CMD53 read interrupt */ - __IOM uint32_t SDIO_CSA_UNMSK : 1; /*!< [2..2] This bit is used to unmask CMD53 CSA + __IOM unsigned int SDIO_CSA_UNMSK : 1; /*!< [2..2] This bit is used to unmask CMD53 CSA interrupt.Setting this bit will mask the interrupt Clearing this bit has no effect */ - __IOM uint32_t SDIO_CMD52_UNMSK : 1; /*!< [3..3] This bit is used to + __IOM unsigned int SDIO_CMD52_UNMSK : 1; /*!< [3..3] This bit is used to unmask CMD52 interrupt */ - __IOM uint32_t SDIO_PWR_LEV_UNMSK : 1; /*!< [4..4] This bit is used to unmask power + __IOM unsigned int SDIO_PWR_LEV_UNMSK : 1; /*!< [4..4] This bit is used to unmask power level change interrupt */ - __IOM uint32_t SDIO_CRC_ERR_UNMSK : 1; /*!< [5..5] This bit is used to + __IOM unsigned int SDIO_CRC_ERR_UNMSK : 1; /*!< [5..5] This bit is used to unmask CRC error interrupt */ __IOM - uint32_t SDIO_ABORT_UNMSK : 1; /*!< [6..6] This bit is used to unmask + unsigned int SDIO_ABORT_UNMSK : 1; /*!< [6..6] This bit is used to unmask abort interrupt Setting this bit will mask the interrupt Clearing this bit has no effect */ - __IOM uint32_t SDIO_TOUT_UNMSK : 1; /*!< [7..7] This bit is used to unmask read FIFO + __IOM unsigned int SDIO_TOUT_UNMSK : 1; /*!< [7..7] This bit is used to unmask read FIFO wait time over interrupt */ - __IOM uint32_t RES : 24; /*!< [31..8] reserved5 */ + __IOM unsigned int RES : 24; /*!< [31..8] reserved5 */ } SDIO_INTR_FN1_UNMASK_REG_b; }; union { - __IM uint32_t SDIO_BLK_LEN_REG; /*!< (@ 0x00000010) SDIO Block Length Register */ + __IM unsigned int SDIO_BLK_LEN_REG; /*!< (@ 0x00000010) SDIO Block Length Register */ struct { - __IM uint32_t SDIO_BLK_LEN : 12; /*!< [11..0] Length of each block for the + __IM unsigned int SDIO_BLK_LEN : 12; /*!< [11..0] Length of each block for the last received CMD53 */ - __IM uint32_t RES : 20; /*!< [31..12] reserved5 */ + __IM unsigned int RES : 20; /*!< [31..12] reserved5 */ } SDIO_BLK_LEN_REG_b; }; union { - __IM uint32_t SDIO_BLK_CNT_REG; /*!< (@ 0x00000014) SDIO Block Length Register */ + __IM unsigned int SDIO_BLK_CNT_REG; /*!< (@ 0x00000014) SDIO Block Length Register */ struct { - __IM uint32_t SDIO_BLK_CNT : 9; /*!< [8..0] Block count for the last + __IM unsigned int SDIO_BLK_CNT : 9; /*!< [8..0] Block count for the last received CMD53 */ - __IM uint32_t RES : 23; /*!< [31..9] reserved5 */ + __IM unsigned int RES : 23; /*!< [31..9] reserved5 */ } SDIO_BLK_CNT_REG_b; }; union { - __IM uint32_t SDIO_ADDRESS_REG; /*!< (@ 0x00000018) SDIO Address Register */ + __IM unsigned int SDIO_ADDRESS_REG; /*!< (@ 0x00000018) SDIO Address Register */ struct { - __IM uint32_t SDIO_ADDR : 16; /*!< [15..0] Lower 16-bits of the 17-bit address field + __IM unsigned int SDIO_ADDR : 16; /*!< [15..0] Lower 16-bits of the 17-bit address field in the last received CMD53 */ - __IM uint32_t RES : 16; /*!< [31..16] reserved5 */ + __IM unsigned int RES : 16; /*!< [31..16] reserved5 */ } SDIO_ADDRESS_REG_b; }; - __IOM uint32_t SDIO_CMD52_RDATA_REGISTER; /*!< (@ 0x0000001C) SDIO CMD52 RDATA + __IOM unsigned int SDIO_CMD52_RDATA_REGISTER; /*!< (@ 0x0000001C) SDIO CMD52 RDATA Register */ - __IOM uint32_t SDIO_CMD52_WDATA_REGISTER; /*!< (@ 0x00000020) SDIO CMD52 WDATA + __IOM unsigned int SDIO_CMD52_WDATA_REGISTER; /*!< (@ 0x00000020) SDIO CMD52 WDATA Register */ union { - __IM uint32_t SDIO_INTR_STATUS_REG; /*!< (@ 0x00000024) SDIO Interrupt + __IM unsigned int SDIO_INTR_STATUS_REG; /*!< (@ 0x00000024) SDIO Interrupt Status Register */ struct { - __IM uint32_t SDIO_INT_ERROR : 1; /*!< [0..0] Interrupt is pending because of error + __IM unsigned int SDIO_INT_ERROR : 1; /*!< [0..0] Interrupt is pending because of error condition from any of the functions */ - __IM uint32_t SDIO_INT_FN1 : 1; /*!< [1..1] Interrupt is pending for function1 */ - __IM uint32_t SDIO_INT_FN2 : 1; /*!< [2..2] Interrupt is pending for function2 */ - __IM uint32_t SDIO_INT_FN3 : 1; /*!< [3..3] Interrupt is pending for function3 */ - __IM uint32_t SDIO_INT_FN4 : 1; /*!< [4..4] Interrupt is pending for function4 */ - __IM uint32_t SDIO_INT_FN5 : 1; /*!< [5..5] Interrupt is pending for function5 */ - __IM uint32_t RES : 26; /*!< [31..6] reserved5 */ + __IM unsigned int SDIO_INT_FN1 : 1; /*!< [1..1] Interrupt is pending for function1 */ + __IM unsigned int SDIO_INT_FN2 : 1; /*!< [2..2] Interrupt is pending for function2 */ + __IM unsigned int SDIO_INT_FN3 : 1; /*!< [3..3] Interrupt is pending for function3 */ + __IM unsigned int SDIO_INT_FN4 : 1; /*!< [4..4] Interrupt is pending for function4 */ + __IM unsigned int SDIO_INT_FN5 : 1; /*!< [5..5] Interrupt is pending for function5 */ + __IM unsigned int RES : 26; /*!< [31..6] reserved5 */ } SDIO_INTR_STATUS_REG_b; }; union { - __IM uint32_t SDIO_INTR_FN_NUMBER_REG; /*!< (@ 0x00000028) SDIO Interrupt + __IM unsigned int SDIO_INTR_FN_NUMBER_REG; /*!< (@ 0x00000028) SDIO Interrupt Function Number Register */ struct { - __IM uint32_t SDIO_INTR_FN_NUM : 3; /*!< [2..0] Indicates the function number to + __IM unsigned int SDIO_INTR_FN_NUM : 3; /*!< [2..0] Indicates the function number to which interrupt is pending. */ - __IM uint32_t RES : 29; /*!< [31..3] reserved5 */ + __IM unsigned int RES : 29; /*!< [31..3] reserved5 */ } SDIO_INTR_FN_NUMBER_REG_b; }; union { - __IM uint32_t SDIO_FIFO_STATUS_REG; /*!< (@ 0x0000002C) SDIO FIFO Status Register */ + __IM unsigned int SDIO_FIFO_STATUS_REG; /*!< (@ 0x0000002C) SDIO FIFO Status Register */ struct { - __IM uint32_t SDIO_WFIFO_FULL : 1; /*!< [0..0] When set, indicates that + __IM unsigned int SDIO_WFIFO_FULL : 1; /*!< [0..0] When set, indicates that WFIFO is full WFIFO is used in SDIO reads from host for sending data from AHB to Host */ - __IM uint32_t SDIO_WFIFO_AFULL : 1; /*!< [1..1] When set, indicates that + __IM unsigned int SDIO_WFIFO_AFULL : 1; /*!< [1..1] When set, indicates that WFIFO is almost full */ - __IM uint32_t SDIO_RFIFO_EMPTY : 1; /*!< [2..2] When set, indicates that RFIFO is + __IM unsigned int SDIO_RFIFO_EMPTY : 1; /*!< [2..2] When set, indicates that RFIFO is empty RFIFO is used in SDIO writes from host for sending data from host to AHB */ - __IM uint32_t SDIO_RFIFO_AEMPTY : 1; /*!< [3..3] When set, indicates that + __IM unsigned int SDIO_RFIFO_AEMPTY : 1; /*!< [3..3] When set, indicates that RFIFO is almost empty */ - __IM uint32_t SDIO_CURRENT_FN_NUM : 3; /*!< [6..4] Indicates the function number of + __IM unsigned int SDIO_CURRENT_FN_NUM : 3; /*!< [6..4] Indicates the function number of the last received command */ - __IM uint32_t SDIO_BUS_CONTROL_STATE : 5; /*!< [11..7] Indicates the function number + __IM unsigned int SDIO_BUS_CONTROL_STATE : 5; /*!< [11..7] Indicates the function number of the last received command */ - __IM uint32_t RES : 20; /*!< [31..12] reserved5 */ + __IM unsigned int RES : 20; /*!< [31..12] reserved5 */ } SDIO_FIFO_STATUS_REG_b; }; union { - __IM uint32_t SDIO_FIFO_OCC_REG; /*!< (@ 0x00000030) SDIO FIFO Occupancy Register */ + __IM unsigned int SDIO_FIFO_OCC_REG; /*!< (@ 0x00000030) SDIO FIFO Occupancy Register */ struct { - __IM uint32_t SDIO_WFIFO_OCC : 8; /*!< [7..0] Indicates the occupancy + __IM unsigned int SDIO_WFIFO_OCC : 8; /*!< [7..0] Indicates the occupancy level of the write FIFO */ - __IM uint32_t SDIO_RFIFO_AVAIL : 8; /*!< [15..8] Indicates the available + __IM unsigned int SDIO_RFIFO_AVAIL : 8; /*!< [15..8] Indicates the available space in the read FIFO */ - __IM uint32_t RES : 16; /*!< [31..16] reserved5 */ + __IM unsigned int RES : 16; /*!< [31..16] reserved5 */ } SDIO_FIFO_OCC_REG_b; }; union { - __IOM uint32_t SDIO_HOST_INTR_SET_REG; /*!< (@ 0x00000034) SDIO Host + __IOM unsigned int SDIO_HOST_INTR_SET_REG; /*!< (@ 0x00000034) SDIO Host Interrupt Set Register */ struct { - __IOM uint32_t SDIO_INTSET_FN2 : 1; /*!< [0..0] This bit is used to raise an + __IOM unsigned int SDIO_INTSET_FN2 : 1; /*!< [0..0] This bit is used to raise an interrupt to host for function2. Setting this bit will raise the interrupt Clearing this bit has no effect */ - __IOM uint32_t SDIO_INTSET_FN3 : 1; /*!< [1..1] This bit is used to raise an + __IOM unsigned int SDIO_INTSET_FN3 : 1; /*!< [1..1] This bit is used to raise an interrupt to host for function3. Setting this bit will raise the interrupt Clearing this bit has no effect */ - __IOM uint32_t SDIO_INTSET_FN4 : 1; /*!< [2..2] This bit is used to raise an + __IOM unsigned int SDIO_INTSET_FN4 : 1; /*!< [2..2] This bit is used to raise an interrupt to host for function4. Setting this bit will raise the interrupt Clearing this bit has no effect */ - __IOM uint32_t SDIO_INTSET_FN5 : 1; /*!< [3..3] This bit is used to raise an + __IOM unsigned int SDIO_INTSET_FN5 : 1; /*!< [3..3] This bit is used to raise an interrupt to host for function5. Setting this bit will raise the interrupt Clearing this bit has no effect */ - __IOM uint32_t RES : 28; /*!< [31..4] reserved5 */ + __IOM unsigned int RES : 28; /*!< [31..4] reserved5 */ } SDIO_HOST_INTR_SET_REG_b; }; union { - __IOM uint32_t SDIO_HOST_INTR_CLEAR_REG; /*!< (@ 0x00000038) SDIO Host + __IOM unsigned int SDIO_HOST_INTR_CLEAR_REG; /*!< (@ 0x00000038) SDIO Host Interrupt Clear Register */ struct { - __IOM uint32_t SDIO_INTCLR_FN2 : 1; /*!< [0..0] This bit is used to clear the + __IOM unsigned int SDIO_INTCLR_FN2 : 1; /*!< [0..0] This bit is used to clear the interrupt to host for function2. Setting this bit will clear the interrupt Clearing this bit has no effect */ - __IOM uint32_t SDIO_INTCLR_FN3 : 1; /*!< [1..1] This bit is used to clear the + __IOM unsigned int SDIO_INTCLR_FN3 : 1; /*!< [1..1] This bit is used to clear the interrupt to host for function3. Setting this bit will clear the interrupt Clearing this bit has no effect */ - __IOM uint32_t SDIO_INTCLR_FN4 : 1; /*!< [2..2] This bit is used to clear the + __IOM unsigned int SDIO_INTCLR_FN4 : 1; /*!< [2..2] This bit is used to clear the interrupt to host for function4. Setting this bit will clear the interrupt Clearing this bit has no effectt */ - __IOM uint32_t SDIO_INTCLR_FN5 : 1; /*!< [3..3] This bit is used to clear the + __IOM unsigned int SDIO_INTCLR_FN5 : 1; /*!< [3..3] This bit is used to clear the interrupt to host for function5. Setting this bit will clear the interrupt Clearing this bit has no effect */ - __IOM uint32_t RES : 28; /*!< [31..4] reserved5 */ + __IOM unsigned int RES : 28; /*!< [31..4] reserved5 */ } SDIO_HOST_INTR_CLEAR_REG_b; }; - __IM uint32_t RESERVED; + __IM unsigned int RESERVED; union { - __OM uint32_t SDIO_RFIFO_DATA_REG[16]; /*!< (@ 0x00000040) SDIO Read FIFO + __OM unsigned int SDIO_RFIFO_DATA_REG[16]; /*!< (@ 0x00000040) SDIO Read FIFO Data Register */ struct { - __OM uint32_t SDIO_RFIFO : 32; /*!< [31..0] Data to be written into SDIO Read FIFO + __OM unsigned int SDIO_RFIFO : 32; /*!< [31..0] Data to be written into SDIO Read FIFO has to be written in this register. */ } SDIO_RFIFO_DATA_REG_b[16]; }; union { - __IM uint32_t SDIO_WFIFO_DATA_REG[16]; /*!< (@ 0x00000080) SDIO Write FIFO + __IM unsigned int SDIO_WFIFO_DATA_REG[16]; /*!< (@ 0x00000080) SDIO Write FIFO Data Register */ struct { - __IM uint32_t SDIO_WFIFO : 32; /*!< [31..0] SDIO Write FIFO data can be + __IM unsigned int SDIO_WFIFO : 32; /*!< [31..0] SDIO Write FIFO data can be read through this register. */ } SDIO_WFIFO_DATA_REG_b[16]; }; union { - __IOM uint32_t SDIO_INTR_FN2_STATUS_CLEAR_REG; /*!< (@ 0x000000C0) SDIO Function2 + __IOM unsigned int SDIO_INTR_FN2_STATUS_CLEAR_REG; /*!< (@ 0x000000C0) SDIO Function2 Status Clear Register */ struct { - __IOM uint32_t SDIO_WR_INT_CLR : 1; /*!< [0..0] This bit is used to enable + __IOM unsigned int SDIO_WR_INT_CLR : 1; /*!< [0..0] This bit is used to enable CMD53 write interrupt. =1 Interrupt is enabled =0 - Interrupt is disabled */ - __IOM uint32_t SDIO_RD_INT_CLR : 1; /*!< [1..1] This bit is used to enable + __IOM unsigned int SDIO_RD_INT_CLR : 1; /*!< [1..1] This bit is used to enable CMD53 read interrupt */ - __IOM uint32_t SDIO_CSA_INT_CLR : 1; /*!< [2..2] This bit is used to + __IOM unsigned int SDIO_CSA_INT_CLR : 1; /*!< [2..2] This bit is used to enable CMD53 CSA interrupt */ - __IOM uint32_t SDIO_CMD52_INT_CLR : 1; /*!< [3..3] This bit is used to + __IOM unsigned int SDIO_CMD52_INT_CLR : 1; /*!< [3..3] This bit is used to enable CMD52 interrupt */ - __IOM uint32_t SDIO_PWR_LEV_INT_CLR : 1; /*!< [4..4] This bit is used to enable power + __IOM unsigned int SDIO_PWR_LEV_INT_CLR : 1; /*!< [4..4] This bit is used to enable power level change interrupt */ - __IOM uint32_t SDIO_CRC_ERR_INT_CLR : 1; /*!< [5..5] This bit is used to enable CRC + __IOM unsigned int SDIO_CRC_ERR_INT_CLR : 1; /*!< [5..5] This bit is used to enable CRC error interrupt */ - __IOM uint32_t SDIO_ABORT_INT_CLR : 1; /*!< [6..6] This bit is used to + __IOM unsigned int SDIO_ABORT_INT_CLR : 1; /*!< [6..6] This bit is used to enable abort interrupt */ - __IOM uint32_t SDIO_TOUT_INT_CLR : 1; /*!< [7..7] This bit is used to enable ?read + __IOM unsigned int SDIO_TOUT_INT_CLR : 1; /*!< [7..7] This bit is used to enable ?read FIFO wait time over? interrupt */ - __IOM uint32_t RES : 24; /*!< [31..8] reserved5 */ + __IOM unsigned int RES : 24; /*!< [31..8] reserved5 */ } SDIO_INTR_FN2_STATUS_CLEAR_REG_b; }; union { - __IOM uint32_t SDIO_INTR_FN2_ENABLE_REG; /*!< (@ 0x000000C4) SDIO Function1 + __IOM unsigned int SDIO_INTR_FN2_ENABLE_REG; /*!< (@ 0x000000C4) SDIO Function1 Interrupt Enable Register */ struct { - __IOM uint32_t SDIO_WR_INT_EN : 1; /*!< [0..0] This bit is used to enable + __IOM unsigned int SDIO_WR_INT_EN : 1; /*!< [0..0] This bit is used to enable CMD53 write interrupt. */ - __IOM uint32_t SDIO_RD_INT_EN : 1; /*!< [1..1] This bit is used to enable + __IOM unsigned int SDIO_RD_INT_EN : 1; /*!< [1..1] This bit is used to enable CMD53 read interrupt */ - __IOM uint32_t SDIO_CSA_INT_EN : 1; /*!< [2..2] This bit is used to enable + __IOM unsigned int SDIO_CSA_INT_EN : 1; /*!< [2..2] This bit is used to enable CMD53 CSA interrupt */ - __IOM uint32_t SDIO_CMD52_INT_EN : 1; /*!< [3..3] This bit is used to + __IOM unsigned int SDIO_CMD52_INT_EN : 1; /*!< [3..3] This bit is used to enable CMD52 interrupt */ - __IOM uint32_t SDIO_PWR_LEV_INT_EN : 1; /*!< [4..4] This bit is used to enable power + __IOM unsigned int SDIO_PWR_LEV_INT_EN : 1; /*!< [4..4] This bit is used to enable power level change interrupt */ - __IOM uint32_t SDIO_CRC_ERR_INT_EN : 1; /*!< [5..5] This bit is used to + __IOM unsigned int SDIO_CRC_ERR_INT_EN : 1; /*!< [5..5] This bit is used to enable CRC error interrupt */ - __IOM uint32_t SDIO_ABORT_INT_EN : 1; /*!< [6..6] This bit is used to + __IOM unsigned int SDIO_ABORT_INT_EN : 1; /*!< [6..6] This bit is used to enable abort interrupt */ - __IOM uint32_t SDIO_TOUT_INT_EN : 1; /*!< [7..7] This bit is used to enable ?read + __IOM unsigned int SDIO_TOUT_INT_EN : 1; /*!< [7..7] This bit is used to enable ?read FIFO wait time over? interrupt */ - __IOM uint32_t RES : 24; /*!< [31..8] reserved5 */ + __IOM unsigned int RES : 24; /*!< [31..8] reserved5 */ } SDIO_INTR_FN2_ENABLE_REG_b; }; union { - __IOM uint32_t SDIO_INTR_FN2_MASK_REG; /*!< (@ 0x000000C8) SDIO Function2 + __IOM unsigned int SDIO_INTR_FN2_MASK_REG; /*!< (@ 0x000000C8) SDIO Function2 Interrupt Mask Register */ struct { - __IOM uint32_t SDIO_WR_INT_MSK : 1; /*!< [0..0] This bit is used to mask + __IOM unsigned int SDIO_WR_INT_MSK : 1; /*!< [0..0] This bit is used to mask CMD53 write interrupt */ - __IOM uint32_t SDIO_RD_INT_MSK : 1; /*!< [1..1] This bit is used to mask + __IOM unsigned int SDIO_RD_INT_MSK : 1; /*!< [1..1] This bit is used to mask CMD53 read interrupt */ - __IOM uint32_t SDIO_CSA_MSK : 1; /*!< [2..2] This bit is used to mask CMD53 CSA + __IOM unsigned int SDIO_CSA_MSK : 1; /*!< [2..2] This bit is used to mask CMD53 CSA interrupt.Setting this bit will mask the interrupt Clearing this bit has no effect */ - __IOM uint32_t SDIO_CMD52_MSK : 1; /*!< [3..3] This bit is used to mask + __IOM unsigned int SDIO_CMD52_MSK : 1; /*!< [3..3] This bit is used to mask CMD52 interrupt */ - __IOM uint32_t SDIO_PWR_LEV_MSK : 1; /*!< [4..4] This bit is used to mask + __IOM unsigned int SDIO_PWR_LEV_MSK : 1; /*!< [4..4] This bit is used to mask power level change interrupt */ - __IOM uint32_t SDIO_CRC_ERR_MSK : 1; /*!< [5..5] This bit is used to mask + __IOM unsigned int SDIO_CRC_ERR_MSK : 1; /*!< [5..5] This bit is used to mask CRC error interrupt */ - __IOM uint32_t SDIO_ABORT_MSK : 1; /*!< [6..6] This bit is used to mask abort + __IOM unsigned int SDIO_ABORT_MSK : 1; /*!< [6..6] This bit is used to mask abort interrupt Setting this bit will mask the interrupt Clearing this bit has no effect */ - __IOM uint32_t SDIO_TOUT_MSK : 1; /*!< [7..7] This bit is used to mask read FIFO wait + __IOM unsigned int SDIO_TOUT_MSK : 1; /*!< [7..7] This bit is used to mask read FIFO wait time over interrupt */ - __IOM uint32_t RES : 24; /*!< [31..8] reserved5 */ + __IOM unsigned int RES : 24; /*!< [31..8] reserved5 */ } SDIO_INTR_FN2_MASK_REG_b; }; union { - __IOM uint32_t SDIO_INTR_FN2_UNMASK_REG; /*!< (@ 0x000000CC) SDIO Function2 + __IOM unsigned int SDIO_INTR_FN2_UNMASK_REG; /*!< (@ 0x000000CC) SDIO Function2 Interrupt Mask Register */ struct { - __IOM uint32_t SDIO_WR_INT_UNMSK : 1; /*!< [0..0] This bit is used to + __IOM unsigned int SDIO_WR_INT_UNMSK : 1; /*!< [0..0] This bit is used to unmask CMD53 write interrupt */ - __IOM uint32_t SDIO_RD_INT_UNMSK : 1; /*!< [1..1] This bit is used to + __IOM unsigned int SDIO_RD_INT_UNMSK : 1; /*!< [1..1] This bit is used to unmask CMD53 read interrupt */ - __IOM uint32_t SDIO_CSA_UNMSK : 1; /*!< [2..2] This bit is used to unmask CMD53 CSA + __IOM unsigned int SDIO_CSA_UNMSK : 1; /*!< [2..2] This bit is used to unmask CMD53 CSA interrupt.Setting this bit will mask the interrupt Clearing this bit has no effect */ - __IOM uint32_t SDIO_CMD52_UNMSK : 1; /*!< [3..3] This bit is used to + __IOM unsigned int SDIO_CMD52_UNMSK : 1; /*!< [3..3] This bit is used to unmask CMD52 interrupt */ - __IOM uint32_t SDIO_PWR_LEV_UNMSK : 1; /*!< [4..4] This bit is used to unmask power + __IOM unsigned int SDIO_PWR_LEV_UNMSK : 1; /*!< [4..4] This bit is used to unmask power level change interrupt */ - __IOM uint32_t SDIO_CRC_ERR_UNMSK : 1; /*!< [5..5] This bit is used to + __IOM unsigned int SDIO_CRC_ERR_UNMSK : 1; /*!< [5..5] This bit is used to unmask CRC error interrupt */ __IOM - uint32_t SDIO_ABORT_UNMSK : 1; /*!< [6..6] This bit is used to unmask + unsigned int SDIO_ABORT_UNMSK : 1; /*!< [6..6] This bit is used to unmask abort interrupt Setting this bit will mask the interrupt Clearing this bit has no effect */ - __IOM uint32_t SDIO_TOUT_UNMSK : 1; /*!< [7..7] This bit is used to unmask read FIFO + __IOM unsigned int SDIO_TOUT_UNMSK : 1; /*!< [7..7] This bit is used to unmask read FIFO wait time over interrupt */ - __IOM uint32_t RES : 24; /*!< [31..8] reserved5 */ + __IOM unsigned int RES : 24; /*!< [31..8] reserved5 */ } SDIO_INTR_FN2_UNMASK_REG_b; }; union { - __IOM uint32_t SDIO_INTR_FN3_STATUS_CLEAR_REG; /*!< (@ 0x000000D0) SDIO Function3 + __IOM unsigned int SDIO_INTR_FN3_STATUS_CLEAR_REG; /*!< (@ 0x000000D0) SDIO Function3 Status Clear Register */ struct { - __IOM uint32_t SDIO_WR_INT_CLR : 1; /*!< [0..0] This bit is used to enable + __IOM unsigned int SDIO_WR_INT_CLR : 1; /*!< [0..0] This bit is used to enable CMD53 write interrupt. =1 Interrupt is enabled =0 - Interrupt is disabled */ - __IOM uint32_t SDIO_RD_INT_CLR : 1; /*!< [1..1] This bit is used to enable + __IOM unsigned int SDIO_RD_INT_CLR : 1; /*!< [1..1] This bit is used to enable CMD53 read interrupt */ - __IOM uint32_t SDIO_CSA_INT_CLR : 1; /*!< [2..2] This bit is used to + __IOM unsigned int SDIO_CSA_INT_CLR : 1; /*!< [2..2] This bit is used to enable CMD53 CSA interrupt */ - __IOM uint32_t SDIO_CMD52_INT_CLR : 1; /*!< [3..3] This bit is used to + __IOM unsigned int SDIO_CMD52_INT_CLR : 1; /*!< [3..3] This bit is used to enable CMD52 interrupt */ - __IOM uint32_t SDIO_PWR_LEV_INT_CLR : 1; /*!< [4..4] This bit is used to enable power + __IOM unsigned int SDIO_PWR_LEV_INT_CLR : 1; /*!< [4..4] This bit is used to enable power level change interrupt */ - __IOM uint32_t SDIO_CRC_ERR_INT_CLR : 1; /*!< [5..5] This bit is used to enable CRC + __IOM unsigned int SDIO_CRC_ERR_INT_CLR : 1; /*!< [5..5] This bit is used to enable CRC error interrupt */ - __IOM uint32_t SDIO_ABORT_INT_CLR : 1; /*!< [6..6] This bit is used to + __IOM unsigned int SDIO_ABORT_INT_CLR : 1; /*!< [6..6] This bit is used to enable abort interrupt */ - __IOM uint32_t SDIO_TOUT_INT_CLR : 1; /*!< [7..7] This bit is used to enable ?read + __IOM unsigned int SDIO_TOUT_INT_CLR : 1; /*!< [7..7] This bit is used to enable ?read FIFO wait time over? interrupt */ - __IOM uint32_t RES : 24; /*!< [31..8] reserved5 */ + __IOM unsigned int RES : 24; /*!< [31..8] reserved5 */ } SDIO_INTR_FN3_STATUS_CLEAR_REG_b; }; union { - __IOM uint32_t SDIO_INTR_FN3_ENABLE_REG; /*!< (@ 0x000000D4) SDIO Function3 + __IOM unsigned int SDIO_INTR_FN3_ENABLE_REG; /*!< (@ 0x000000D4) SDIO Function3 Interrupt Enable Register */ struct { - __IOM uint32_t SDIO_WR_INT_EN : 1; /*!< [0..0] This bit is used to enable + __IOM unsigned int SDIO_WR_INT_EN : 1; /*!< [0..0] This bit is used to enable CMD53 write interrupt. */ - __IOM uint32_t SDIO_RD_INT_EN : 1; /*!< [1..1] This bit is used to enable + __IOM unsigned int SDIO_RD_INT_EN : 1; /*!< [1..1] This bit is used to enable CMD53 read interrupt */ - __IOM uint32_t SDIO_CSA_INT_EN : 1; /*!< [2..2] This bit is used to enable + __IOM unsigned int SDIO_CSA_INT_EN : 1; /*!< [2..2] This bit is used to enable CMD53 CSA interrupt */ - __IOM uint32_t SDIO_CMD52_INT_EN : 1; /*!< [3..3] This bit is used to + __IOM unsigned int SDIO_CMD52_INT_EN : 1; /*!< [3..3] This bit is used to enable CMD52 interrupt */ - __IOM uint32_t SDIO_PWR_LEV_INT_EN : 1; /*!< [4..4] This bit is used to enable power + __IOM unsigned int SDIO_PWR_LEV_INT_EN : 1; /*!< [4..4] This bit is used to enable power level change interrupt */ - __IOM uint32_t SDIO_CRC_ERR_INT_EN : 1; /*!< [5..5] This bit is used to + __IOM unsigned int SDIO_CRC_ERR_INT_EN : 1; /*!< [5..5] This bit is used to enable CRC error interrupt */ - __IOM uint32_t SDIO_ABORT_INT_EN : 1; /*!< [6..6] This bit is used to + __IOM unsigned int SDIO_ABORT_INT_EN : 1; /*!< [6..6] This bit is used to enable abort interrupt */ - __IOM uint32_t SDIO_TOUT_INT_EN : 1; /*!< [7..7] This bit is used to enable ?read + __IOM unsigned int SDIO_TOUT_INT_EN : 1; /*!< [7..7] This bit is used to enable ?read FIFO wait time over? interrupt */ - __IOM uint32_t RES : 24; /*!< [31..8] reserved5 */ + __IOM unsigned int RES : 24; /*!< [31..8] reserved5 */ } SDIO_INTR_FN3_ENABLE_REG_b; }; union { - __IOM uint32_t SDIO_INTR_FN3_MASK_REG; /*!< (@ 0x000000D8) SDIO Function3 + __IOM unsigned int SDIO_INTR_FN3_MASK_REG; /*!< (@ 0x000000D8) SDIO Function3 Interrupt Mask Register */ struct { - __IOM uint32_t SDIO_WR_INT_MSK : 1; /*!< [0..0] This bit is used to mask + __IOM unsigned int SDIO_WR_INT_MSK : 1; /*!< [0..0] This bit is used to mask CMD53 write interrupt */ - __IOM uint32_t SDIO_RD_INT_MSK : 1; /*!< [1..1] This bit is used to mask + __IOM unsigned int SDIO_RD_INT_MSK : 1; /*!< [1..1] This bit is used to mask CMD53 read interrupt */ - __IOM uint32_t SDIO_CSA_MSK : 1; /*!< [2..2] This bit is used to mask CMD53 CSA + __IOM unsigned int SDIO_CSA_MSK : 1; /*!< [2..2] This bit is used to mask CMD53 CSA interrupt.Setting this bit will mask the interrupt Clearing this bit has no effect */ - __IOM uint32_t SDIO_CMD52_MSK : 1; /*!< [3..3] This bit is used to mask + __IOM unsigned int SDIO_CMD52_MSK : 1; /*!< [3..3] This bit is used to mask CMD52 interrupt */ - __IOM uint32_t SDIO_PWR_LEV_MSK : 1; /*!< [4..4] This bit is used to mask + __IOM unsigned int SDIO_PWR_LEV_MSK : 1; /*!< [4..4] This bit is used to mask power level change interrupt */ - __IOM uint32_t SDIO_CRC_ERR_MSK : 1; /*!< [5..5] This bit is used to mask + __IOM unsigned int SDIO_CRC_ERR_MSK : 1; /*!< [5..5] This bit is used to mask CRC error interrupt */ - __IOM uint32_t SDIO_ABORT_MSK : 1; /*!< [6..6] This bit is used to mask abort + __IOM unsigned int SDIO_ABORT_MSK : 1; /*!< [6..6] This bit is used to mask abort interrupt Setting this bit will mask the interrupt Clearing this bit has no effect */ - __IOM uint32_t SDIO_TOUT_MSK : 1; /*!< [7..7] This bit is used to mask read FIFO wait + __IOM unsigned int SDIO_TOUT_MSK : 1; /*!< [7..7] This bit is used to mask read FIFO wait time over interrupt */ - __IOM uint32_t RES : 24; /*!< [31..8] reserved5 */ + __IOM unsigned int RES : 24; /*!< [31..8] reserved5 */ } SDIO_INTR_FN3_MASK_REG_b; }; union { - __IOM uint32_t SDIO_INTR_FN3_UNMASK_REG; /*!< (@ 0x000000DC) SDIO Function3 + __IOM unsigned int SDIO_INTR_FN3_UNMASK_REG; /*!< (@ 0x000000DC) SDIO Function3 Interrupt Mask Register */ struct { - __IOM uint32_t SDIO_WR_INT_UNMSK : 1; /*!< [0..0] This bit is used to + __IOM unsigned int SDIO_WR_INT_UNMSK : 1; /*!< [0..0] This bit is used to unmask CMD53 write interrupt */ - __IOM uint32_t SDIO_RD_INT_UNMSK : 1; /*!< [1..1] This bit is used to + __IOM unsigned int SDIO_RD_INT_UNMSK : 1; /*!< [1..1] This bit is used to unmask CMD53 read interrupt */ - __IOM uint32_t SDIO_CSA_UNMSK : 1; /*!< [2..2] This bit is used to unmask CMD53 CSA + __IOM unsigned int SDIO_CSA_UNMSK : 1; /*!< [2..2] This bit is used to unmask CMD53 CSA interrupt.Setting this bit will mask the interrupt Clearing this bit has no effect */ - __IOM uint32_t SDIO_CMD52_UNMSK : 1; /*!< [3..3] This bit is used to + __IOM unsigned int SDIO_CMD52_UNMSK : 1; /*!< [3..3] This bit is used to unmask CMD52 interrupt */ - __IOM uint32_t SDIO_PWR_LEV_UNMSK : 1; /*!< [4..4] This bit is used to unmask power + __IOM unsigned int SDIO_PWR_LEV_UNMSK : 1; /*!< [4..4] This bit is used to unmask power level change interrupt */ - __IOM uint32_t SDIO_CRC_ERR_UNMSK : 1; /*!< [5..5] This bit is used to + __IOM unsigned int SDIO_CRC_ERR_UNMSK : 1; /*!< [5..5] This bit is used to unmask CRC error interrupt */ __IOM - uint32_t SDIO_ABORT_UNMSK : 1; /*!< [6..6] This bit is used to unmask + unsigned int SDIO_ABORT_UNMSK : 1; /*!< [6..6] This bit is used to unmask abort interrupt Setting this bit will mask the interrupt Clearing this bit has no effect */ - __IOM uint32_t SDIO_TOUT_UNMSK : 1; /*!< [7..7] This bit is used to unmask read FIFO + __IOM unsigned int SDIO_TOUT_UNMSK : 1; /*!< [7..7] This bit is used to unmask read FIFO wait time over interrupt */ - __IOM uint32_t RES : 24; /*!< [31..8] reserved5 */ + __IOM unsigned int RES : 24; /*!< [31..8] reserved5 */ } SDIO_INTR_FN3_UNMASK_REG_b; }; union { - __IOM uint32_t SDIO_INTR_FN4_STATUS_CLEAR_REG; /*!< (@ 0x000000E0) SDIO Function4 + __IOM unsigned int SDIO_INTR_FN4_STATUS_CLEAR_REG; /*!< (@ 0x000000E0) SDIO Function4 Status Clear Register */ struct { - __IOM uint32_t SDIO_WR_INT_CLR : 1; /*!< [0..0] This bit is used to enable + __IOM unsigned int SDIO_WR_INT_CLR : 1; /*!< [0..0] This bit is used to enable CMD53 write interrupt. =1 Interrupt is enabled =0 - Interrupt is disabled */ - __IOM uint32_t SDIO_RD_INT_CLR : 1; /*!< [1..1] This bit is used to enable + __IOM unsigned int SDIO_RD_INT_CLR : 1; /*!< [1..1] This bit is used to enable CMD53 read interrupt */ - __IOM uint32_t SDIO_CSA_INT_CLR : 1; /*!< [2..2] This bit is used to + __IOM unsigned int SDIO_CSA_INT_CLR : 1; /*!< [2..2] This bit is used to enable CMD53 CSA interrupt */ - __IOM uint32_t SDIO_CMD52_INT_CLR : 1; /*!< [3..3] This bit is used to + __IOM unsigned int SDIO_CMD52_INT_CLR : 1; /*!< [3..3] This bit is used to enable CMD52 interrupt */ - __IOM uint32_t SDIO_PWR_LEV_INT_CLR : 1; /*!< [4..4] This bit is used to enable power + __IOM unsigned int SDIO_PWR_LEV_INT_CLR : 1; /*!< [4..4] This bit is used to enable power level change interrupt */ - __IOM uint32_t SDIO_CRC_ERR_INT_CLR : 1; /*!< [5..5] This bit is used to enable CRC + __IOM unsigned int SDIO_CRC_ERR_INT_CLR : 1; /*!< [5..5] This bit is used to enable CRC error interrupt */ - __IOM uint32_t SDIO_ABORT_INT_CLR : 1; /*!< [6..6] This bit is used to + __IOM unsigned int SDIO_ABORT_INT_CLR : 1; /*!< [6..6] This bit is used to enable abort interrupt */ - __IOM uint32_t SDIO_TOUT_INT_CLR : 1; /*!< [7..7] This bit is used to enable ?read + __IOM unsigned int SDIO_TOUT_INT_CLR : 1; /*!< [7..7] This bit is used to enable ?read FIFO wait time over? interrupt */ - __IOM uint32_t RES : 24; /*!< [31..8] reserved5 */ + __IOM unsigned int RES : 24; /*!< [31..8] reserved5 */ } SDIO_INTR_FN4_STATUS_CLEAR_REG_b; }; union { - __IOM uint32_t SDIO_INTR_FN4_ENABLE_REG; /*!< (@ 0x000000E4) SDIO Function4 + __IOM unsigned int SDIO_INTR_FN4_ENABLE_REG; /*!< (@ 0x000000E4) SDIO Function4 Interrupt Enable Register */ struct { - __IOM uint32_t SDIO_WR_INT_EN : 1; /*!< [0..0] This bit is used to enable + __IOM unsigned int SDIO_WR_INT_EN : 1; /*!< [0..0] This bit is used to enable CMD53 write interrupt. */ - __IOM uint32_t SDIO_RD_INT_EN : 1; /*!< [1..1] This bit is used to enable + __IOM unsigned int SDIO_RD_INT_EN : 1; /*!< [1..1] This bit is used to enable CMD53 read interrupt */ - __IOM uint32_t SDIO_CSA_INT_EN : 1; /*!< [2..2] This bit is used to enable + __IOM unsigned int SDIO_CSA_INT_EN : 1; /*!< [2..2] This bit is used to enable CMD53 CSA interrupt */ - __IOM uint32_t SDIO_CMD52_INT_EN : 1; /*!< [3..3] This bit is used to + __IOM unsigned int SDIO_CMD52_INT_EN : 1; /*!< [3..3] This bit is used to enable CMD52 interrupt */ - __IOM uint32_t SDIO_PWR_LEV_INT_EN : 1; /*!< [4..4] This bit is used to enable power + __IOM unsigned int SDIO_PWR_LEV_INT_EN : 1; /*!< [4..4] This bit is used to enable power level change interrupt */ - __IOM uint32_t SDIO_CRC_ERR_INT_EN : 1; /*!< [5..5] This bit is used to + __IOM unsigned int SDIO_CRC_ERR_INT_EN : 1; /*!< [5..5] This bit is used to enable CRC error interrupt */ - __IOM uint32_t SDIO_ABORT_INT_EN : 1; /*!< [6..6] This bit is used to + __IOM unsigned int SDIO_ABORT_INT_EN : 1; /*!< [6..6] This bit is used to enable abort interrupt */ - __IOM uint32_t SDIO_TOUT_INT_EN : 1; /*!< [7..7] This bit is used to enable ?read + __IOM unsigned int SDIO_TOUT_INT_EN : 1; /*!< [7..7] This bit is used to enable ?read FIFO wait time over? interrupt */ - __IOM uint32_t RES : 24; /*!< [31..8] reserved5 */ + __IOM unsigned int RES : 24; /*!< [31..8] reserved5 */ } SDIO_INTR_FN4_ENABLE_REG_b; }; union { - __IOM uint32_t SDIO_INTR_FN4_MASK_REG; /*!< (@ 0x000000E8) SDIO Function4 + __IOM unsigned int SDIO_INTR_FN4_MASK_REG; /*!< (@ 0x000000E8) SDIO Function4 Interrupt Mask Register */ struct { - __IOM uint32_t SDIO_WR_INT_MSK : 1; /*!< [0..0] This bit is used to mask + __IOM unsigned int SDIO_WR_INT_MSK : 1; /*!< [0..0] This bit is used to mask CMD53 write interrupt */ - __IOM uint32_t SDIO_RD_INT_MSK : 1; /*!< [1..1] This bit is used to mask + __IOM unsigned int SDIO_RD_INT_MSK : 1; /*!< [1..1] This bit is used to mask CMD53 read interrupt */ - __IOM uint32_t SDIO_CSA_MSK : 1; /*!< [2..2] This bit is used to mask CMD53 CSA + __IOM unsigned int SDIO_CSA_MSK : 1; /*!< [2..2] This bit is used to mask CMD53 CSA interrupt.Setting this bit will mask the interrupt Clearing this bit has no effect */ - __IOM uint32_t SDIO_CMD52_MSK : 1; /*!< [3..3] This bit is used to mask + __IOM unsigned int SDIO_CMD52_MSK : 1; /*!< [3..3] This bit is used to mask CMD52 interrupt */ - __IOM uint32_t SDIO_PWR_LEV_MSK : 1; /*!< [4..4] This bit is used to mask + __IOM unsigned int SDIO_PWR_LEV_MSK : 1; /*!< [4..4] This bit is used to mask power level change interrupt */ - __IOM uint32_t SDIO_CRC_ERR_MSK : 1; /*!< [5..5] This bit is used to mask + __IOM unsigned int SDIO_CRC_ERR_MSK : 1; /*!< [5..5] This bit is used to mask CRC error interrupt */ - __IOM uint32_t SDIO_ABORT_MSK : 1; /*!< [6..6] This bit is used to mask abort + __IOM unsigned int SDIO_ABORT_MSK : 1; /*!< [6..6] This bit is used to mask abort interrupt Setting this bit will mask the interrupt Clearing this bit has no effect */ - __IOM uint32_t SDIO_TOUT_MSK : 1; /*!< [7..7] This bit is used to mask read FIFO wait + __IOM unsigned int SDIO_TOUT_MSK : 1; /*!< [7..7] This bit is used to mask read FIFO wait time over interrupt */ - __IOM uint32_t RES : 24; /*!< [31..8] reserved5 */ + __IOM unsigned int RES : 24; /*!< [31..8] reserved5 */ } SDIO_INTR_FN4_MASK_REG_b; }; union { - __IOM uint32_t SDIO_INTR_FN4_UNMASK_REG; /*!< (@ 0x000000EC) SDIO Function4 + __IOM unsigned int SDIO_INTR_FN4_UNMASK_REG; /*!< (@ 0x000000EC) SDIO Function4 Interrupt Mask Register */ struct { - __IOM uint32_t SDIO_WR_INT_UNMSK : 1; /*!< [0..0] This bit is used to + __IOM unsigned int SDIO_WR_INT_UNMSK : 1; /*!< [0..0] This bit is used to unmask CMD53 write interrupt */ - __IOM uint32_t SDIO_RD_INT_UNMSK : 1; /*!< [1..1] This bit is used to + __IOM unsigned int SDIO_RD_INT_UNMSK : 1; /*!< [1..1] This bit is used to unmask CMD53 read interrupt */ - __IOM uint32_t SDIO_CSA_UNMSK : 1; /*!< [2..2] This bit is used to unmask CMD53 CSA + __IOM unsigned int SDIO_CSA_UNMSK : 1; /*!< [2..2] This bit is used to unmask CMD53 CSA interrupt.Setting this bit will mask the interrupt Clearing this bit has no effect */ - __IOM uint32_t SDIO_CMD52_UNMSK : 1; /*!< [3..3] This bit is used to + __IOM unsigned int SDIO_CMD52_UNMSK : 1; /*!< [3..3] This bit is used to unmask CMD52 interrupt */ - __IOM uint32_t SDIO_PWR_LEV_UNMSK : 1; /*!< [4..4] This bit is used to unmask power + __IOM unsigned int SDIO_PWR_LEV_UNMSK : 1; /*!< [4..4] This bit is used to unmask power level change interrupt */ - __IOM uint32_t SDIO_CRC_ERR_UNMSK : 1; /*!< [5..5] This bit is used to + __IOM unsigned int SDIO_CRC_ERR_UNMSK : 1; /*!< [5..5] This bit is used to unmask CRC error interrupt */ __IOM - uint32_t SDIO_ABORT_UNMSK : 1; /*!< [6..6] This bit is used to unmask + unsigned int SDIO_ABORT_UNMSK : 1; /*!< [6..6] This bit is used to unmask abort interrupt Setting this bit will mask the interrupt Clearing this bit has no effect */ - __IOM uint32_t SDIO_TOUT_UNMSK : 1; /*!< [7..7] This bit is used to unmask read FIFO + __IOM unsigned int SDIO_TOUT_UNMSK : 1; /*!< [7..7] This bit is used to unmask read FIFO wait time over interrupt */ - __IOM uint32_t RES : 24; /*!< [31..8] reserved5 */ + __IOM unsigned int RES : 24; /*!< [31..8] reserved5 */ } SDIO_INTR_FN4_UNMASK_REG_b; }; union { - __IOM uint32_t SDIO_INTR_FN5_STATUS_CLEAR_REG; /*!< (@ 0x000000F0) SDIO Function5 + __IOM unsigned int SDIO_INTR_FN5_STATUS_CLEAR_REG; /*!< (@ 0x000000F0) SDIO Function5 Status Clear Register */ struct { - __IOM uint32_t SDIO_WR_INT_CLR : 1; /*!< [0..0] This bit is used to enable + __IOM unsigned int SDIO_WR_INT_CLR : 1; /*!< [0..0] This bit is used to enable CMD53 write interrupt. =1 Interrupt is enabled =0 - Interrupt is disabled */ - __IOM uint32_t SDIO_RD_INT_CLR : 1; /*!< [1..1] This bit is used to enable + __IOM unsigned int SDIO_RD_INT_CLR : 1; /*!< [1..1] This bit is used to enable CMD53 read interrupt */ - __IOM uint32_t SDIO_CSA_INT_CLR : 1; /*!< [2..2] This bit is used to + __IOM unsigned int SDIO_CSA_INT_CLR : 1; /*!< [2..2] This bit is used to enable CMD53 CSA interrupt */ - __IOM uint32_t SDIO_CMD52_INT_CLR : 1; /*!< [3..3] This bit is used to + __IOM unsigned int SDIO_CMD52_INT_CLR : 1; /*!< [3..3] This bit is used to enable CMD52 interrupt */ - __IOM uint32_t SDIO_PWR_LEV_INT_CLR : 1; /*!< [4..4] This bit is used to enable power + __IOM unsigned int SDIO_PWR_LEV_INT_CLR : 1; /*!< [4..4] This bit is used to enable power level change interrupt */ - __IOM uint32_t SDIO_CRC_ERR_INT_CLR : 1; /*!< [5..5] This bit is used to enable CRC + __IOM unsigned int SDIO_CRC_ERR_INT_CLR : 1; /*!< [5..5] This bit is used to enable CRC error interrupt */ - __IOM uint32_t SDIO_ABORT_INT_CLR : 1; /*!< [6..6] This bit is used to + __IOM unsigned int SDIO_ABORT_INT_CLR : 1; /*!< [6..6] This bit is used to enable abort interrupt */ - __IOM uint32_t SDIO_TOUT_INT_CLR : 1; /*!< [7..7] This bit is used to enable ?read + __IOM unsigned int SDIO_TOUT_INT_CLR : 1; /*!< [7..7] This bit is used to enable ?read FIFO wait time over? interrupt */ - __IOM uint32_t RES : 24; /*!< [31..8] reserved5 */ + __IOM unsigned int RES : 24; /*!< [31..8] reserved5 */ } SDIO_INTR_FN5_STATUS_CLEAR_REG_b; }; union { - __IOM uint32_t SDIO_INTR_FN5_ENABLE_REG; /*!< (@ 0x000000F4) SDIO Function5 + __IOM unsigned int SDIO_INTR_FN5_ENABLE_REG; /*!< (@ 0x000000F4) SDIO Function5 Interrupt Enable Register */ struct { - __IOM uint32_t SDIO_WR_INT_EN : 1; /*!< [0..0] This bit is used to enable + __IOM unsigned int SDIO_WR_INT_EN : 1; /*!< [0..0] This bit is used to enable CMD53 write interrupt. */ - __IOM uint32_t SDIO_RD_INT_EN : 1; /*!< [1..1] This bit is used to enable + __IOM unsigned int SDIO_RD_INT_EN : 1; /*!< [1..1] This bit is used to enable CMD53 read interrupt */ - __IOM uint32_t SDIO_CSA_INT_EN : 1; /*!< [2..2] This bit is used to enable + __IOM unsigned int SDIO_CSA_INT_EN : 1; /*!< [2..2] This bit is used to enable CMD53 CSA interrupt */ - __IOM uint32_t SDIO_CMD52_INT_EN : 1; /*!< [3..3] This bit is used to + __IOM unsigned int SDIO_CMD52_INT_EN : 1; /*!< [3..3] This bit is used to enable CMD52 interrupt */ - __IOM uint32_t SDIO_PWR_LEV_INT_EN : 1; /*!< [4..4] This bit is used to enable power + __IOM unsigned int SDIO_PWR_LEV_INT_EN : 1; /*!< [4..4] This bit is used to enable power level change interrupt */ - __IOM uint32_t SDIO_CRC_ERR_INT_EN : 1; /*!< [5..5] This bit is used to + __IOM unsigned int SDIO_CRC_ERR_INT_EN : 1; /*!< [5..5] This bit is used to enable CRC error interrupt */ - __IOM uint32_t SDIO_ABORT_INT_EN : 1; /*!< [6..6] This bit is used to + __IOM unsigned int SDIO_ABORT_INT_EN : 1; /*!< [6..6] This bit is used to enable abort interrupt */ - __IOM uint32_t SDIO_TOUT_INT_EN : 1; /*!< [7..7] This bit is used to enable ?read + __IOM unsigned int SDIO_TOUT_INT_EN : 1; /*!< [7..7] This bit is used to enable ?read FIFO wait time over? interrupt */ - __IOM uint32_t RES : 24; /*!< [31..8] reserved5 */ + __IOM unsigned int RES : 24; /*!< [31..8] reserved5 */ } SDIO_INTR_FN5_ENABLE_REG_b; }; union { - __IOM uint32_t SDIO_INTR_FN5_MASK_REG; /*!< (@ 0x000000F8) SDIO Function5 + __IOM unsigned int SDIO_INTR_FN5_MASK_REG; /*!< (@ 0x000000F8) SDIO Function5 Interrupt Mask Register */ struct { - __IOM uint32_t SDIO_WR_INT_MSK : 1; /*!< [0..0] This bit is used to mask + __IOM unsigned int SDIO_WR_INT_MSK : 1; /*!< [0..0] This bit is used to mask CMD53 write interrupt */ - __IOM uint32_t SDIO_RD_INT_MSK : 1; /*!< [1..1] This bit is used to mask + __IOM unsigned int SDIO_RD_INT_MSK : 1; /*!< [1..1] This bit is used to mask CMD53 read interrupt */ - __IOM uint32_t SDIO_CSA_MSK : 1; /*!< [2..2] This bit is used to mask CMD53 CSA + __IOM unsigned int SDIO_CSA_MSK : 1; /*!< [2..2] This bit is used to mask CMD53 CSA interrupt.Setting this bit will mask the interrupt Clearing this bit has no effect */ - __IOM uint32_t SDIO_CMD52_MSK : 1; /*!< [3..3] This bit is used to mask + __IOM unsigned int SDIO_CMD52_MSK : 1; /*!< [3..3] This bit is used to mask CMD52 interrupt */ - __IOM uint32_t SDIO_PWR_LEV_MSK : 1; /*!< [4..4] This bit is used to mask + __IOM unsigned int SDIO_PWR_LEV_MSK : 1; /*!< [4..4] This bit is used to mask power level change interrupt */ - __IOM uint32_t SDIO_CRC_ERR_MSK : 1; /*!< [5..5] This bit is used to mask + __IOM unsigned int SDIO_CRC_ERR_MSK : 1; /*!< [5..5] This bit is used to mask CRC error interrupt */ - __IOM uint32_t SDIO_ABORT_MSK : 1; /*!< [6..6] This bit is used to mask abort + __IOM unsigned int SDIO_ABORT_MSK : 1; /*!< [6..6] This bit is used to mask abort interrupt Setting this bit will mask the interrupt Clearing this bit has no effect */ - __IOM uint32_t SDIO_TOUT_MSK : 1; /*!< [7..7] This bit is used to mask read FIFO wait + __IOM unsigned int SDIO_TOUT_MSK : 1; /*!< [7..7] This bit is used to mask read FIFO wait time over interrupt */ - __IOM uint32_t RES : 24; /*!< [31..8] reserved5 */ + __IOM unsigned int RES : 24; /*!< [31..8] reserved5 */ } SDIO_INTR_FN5_MASK_REG_b; }; union { - __IOM uint32_t SDIO_INTR_FN5_UNMASK_REG; /*!< (@ 0x000000FC) SDIO Function5 + __IOM unsigned int SDIO_INTR_FN5_UNMASK_REG; /*!< (@ 0x000000FC) SDIO Function5 Interrupt Mask Register */ struct { - __IOM uint32_t SDIO_WR_INT_UNMSK : 1; /*!< [0..0] This bit is used to + __IOM unsigned int SDIO_WR_INT_UNMSK : 1; /*!< [0..0] This bit is used to unmask CMD53 write interrupt */ - __IOM uint32_t SDIO_RD_INT_UNMSK : 1; /*!< [1..1] This bit is used to + __IOM unsigned int SDIO_RD_INT_UNMSK : 1; /*!< [1..1] This bit is used to unmask CMD53 read interrupt */ - __IOM uint32_t SDIO_CSA_UNMSK : 1; /*!< [2..2] This bit is used to unmask CMD53 CSA + __IOM unsigned int SDIO_CSA_UNMSK : 1; /*!< [2..2] This bit is used to unmask CMD53 CSA interrupt.Setting this bit will mask the interrupt Clearing this bit has no effect */ - __IOM uint32_t SDIO_CMD52_UNMSK : 1; /*!< [3..3] This bit is used to + __IOM unsigned int SDIO_CMD52_UNMSK : 1; /*!< [3..3] This bit is used to unmask CMD52 interrupt */ - __IOM uint32_t SDIO_PWR_LEV_UNMSK : 1; /*!< [4..4] This bit is used to unmask power + __IOM unsigned int SDIO_PWR_LEV_UNMSK : 1; /*!< [4..4] This bit is used to unmask power level change interrupt */ - __IOM uint32_t SDIO_CRC_ERR_UNMSK : 1; /*!< [5..5] This bit is used to + __IOM unsigned int SDIO_CRC_ERR_UNMSK : 1; /*!< [5..5] This bit is used to unmask CRC error interrupt */ __IOM - uint32_t SDIO_ABORT_UNMSK : 1; /*!< [6..6] This bit is used to unmask + unsigned int SDIO_ABORT_UNMSK : 1; /*!< [6..6] This bit is used to unmask abort interrupt Setting this bit will mask the interrupt Clearing this bit has no effect */ - __IOM uint32_t SDIO_TOUT_UNMSK : 1; /*!< [7..7] This bit is used to unmask read FIFO + __IOM unsigned int SDIO_TOUT_UNMSK : 1; /*!< [7..7] This bit is used to unmask read FIFO wait time over interrupt */ - __IOM uint32_t RES : 24; /*!< [31..8] reserved5 */ + __IOM unsigned int RES : 24; /*!< [31..8] reserved5 */ } SDIO_INTR_FN5_UNMASK_REG_b; }; union { - __IOM uint32_t SDIO_ERROR_COND_CHK_ENABLE_REG; /*!< (@ 0x00000100) SDIO error condition + __IOM unsigned int SDIO_ERROR_COND_CHK_ENABLE_REG; /*!< (@ 0x00000100) SDIO error condition check enable register */ struct { - __IOM uint32_t SDIO_CRC_EN : 1; /*!< [0..0] When set, stops the DMA from doing data + __IOM unsigned int SDIO_CRC_EN : 1; /*!< [0..0] When set, stops the DMA from doing data accesses till CRC error interrupt is cleared */ - __IOM uint32_t SDIO_ABORT_EN : 1; /*!< [1..1] When set, stops the DMA from doing data + __IOM unsigned int SDIO_ABORT_EN : 1; /*!< [1..1] When set, stops the DMA from doing data accesses till ABORT interrupt is cleared */ - __IOM uint32_t SDIO_SPI_RD_DATA_ERROR_EN : 1; /*!< [2..2] When set, stops the DMA + __IOM unsigned int SDIO_SPI_RD_DATA_ERROR_EN : 1; /*!< [2..2] When set, stops the DMA from doing data accesses till read data error interrupt is cleared in SPI mode */ - __IOM uint32_t RES : 29; /*!< [31..3] reserved5 */ + __IOM unsigned int RES : 29; /*!< [31..3] reserved5 */ } SDIO_ERROR_COND_CHK_ENABLE_REG_b; }; union { - __IOM uint32_t SDIO_ERROR_COND_STATE_REG; /*!< (@ 0x00000104) SDIO error + __IOM unsigned int SDIO_ERROR_COND_STATE_REG; /*!< (@ 0x00000104) SDIO error condition state register */ struct { - __IOM uint32_t SDIO_ERROR_BYTE_CNT : 12; /*!< [11..0] Indicates byte count when one + __IOM unsigned int SDIO_ERROR_BYTE_CNT : 12; /*!< [11..0] Indicates byte count when one of the error condition occurred */ - __IOM uint32_t RESERVED1 : 4; /*!< [15..12] RESERVED1 */ - __IOM uint32_t SDIO_ERROR_BLK_CNT : 7; /*!< [22..16] Indicates block count when one + __IOM unsigned int RESERVED1 : 4; /*!< [15..12] RESERVED1 */ + __IOM unsigned int SDIO_ERROR_BLK_CNT : 7; /*!< [22..16] Indicates block count when one of error condition occurred */ - __IOM uint32_t RESERVED2 : 9; /*!< [31..23] RESERVED2 */ + __IOM unsigned int RESERVED2 : 9; /*!< [31..23] RESERVED2 */ } SDIO_ERROR_COND_STATE_REG_b; }; union { - __IM uint32_t SDIO_BOOT_CONFIG_VALS_0_REG; /*!< (@ 0x00000108) SDIO Boot + __IM unsigned int SDIO_BOOT_CONFIG_VALS_0_REG; /*!< (@ 0x00000108) SDIO Boot Config Values Register 0 */ struct { - __IM uint32_t OCR_R : 24; /*!< [23..0] Operating conditions. The value + __IM unsigned int OCR_R : 24; /*!< [23..0] Operating conditions. The value written by bootloader can be read here. */ - __IM uint32_t CSA_MSBYTE : 8; /*!< [31..24] MS byre of CSA address. Lower + __IM unsigned int CSA_MSBYTE : 8; /*!< [31..24] MS byre of CSA address. Lower 24 bits of CSA will come through SDIO CSA registers. Whenever CSA access is done, 32-bit address will @@ -9591,29 +9591,29 @@ typedef struct { /*!< (@ 0x40000000) SDIO0 Structure */ }; union { - __IM uint32_t SDIO_BOOT_CONFIG_VALS_1_REG; /*!< (@ 0x0000010C) SDIO Boot + __IM unsigned int SDIO_BOOT_CONFIG_VALS_1_REG; /*!< (@ 0x0000010C) SDIO Boot Config Values Register 1 */ struct { - __IM uint32_t NO_OF_IO_FUNCTIONS : 3; /*!< [2..0] Indicates number functions + __IM unsigned int NO_OF_IO_FUNCTIONS : 3; /*!< [2..0] Indicates number functions supported. The value written by bootloader can be read here. */ - __IM uint32_t COMBOCARD : 1; /*!< [3..3] When set, combo mode will be enabled. */ - __IM uint32_t SDMEM_IGNOTRE_SDMEM_PRESENT : 1; /*!< [4..4] When set, sdmem_present + __IM unsigned int COMBOCARD : 1; /*!< [3..3] When set, combo mode will be enabled. */ + __IM unsigned int SDMEM_IGNOTRE_SDMEM_PRESENT : 1; /*!< [4..4] When set, sdmem_present signal, coming from GPIO, will be ignored. */ - __IM uint32_t SDMEM_DRIVE_HIZ_MB_READ : 1; /*!< [5..5] When set, High will be driven + __IM unsigned int SDMEM_DRIVE_HIZ_MB_READ : 1; /*!< [5..5] When set, High will be driven in the second cycle of interrupt period during sd memory mb read transfer */ - __IM uint32_t SDMEM_DISABLE_INTERRUPT_MB_READ : 1; /*!< [6..6] When set, + __IM unsigned int SDMEM_DISABLE_INTERRUPT_MB_READ : 1; /*!< [6..6] When set, interrupt will be not be driven during sd memory mb read transfer */ - __IM uint32_t IGNORE_DISABLE_HS : 1; /*!< [7..7] if ignore_disable_hs is set, + __IM unsigned int IGNORE_DISABLE_HS : 1; /*!< [7..7] if ignore_disable_hs is set, sdmem_disable_high_speed_switching coming from combo mode module is ignored */ - __IM uint32_t RESERVED2 : 24; /*!< [31..8] RESERVED2 */ + __IM unsigned int RESERVED2 : 24; /*!< [31..8] RESERVED2 */ } SDIO_BOOT_CONFIG_VALS_1_REG_b; }; } SDIO0_Type; /*!< Size = 272 (0x110) */ @@ -9827,7 +9827,7 @@ typedef struct { /*!< (@ 0x20200000) SPI_SLAVE Structure */ } SPI_BC_STATE_b; }; __IM uint16_t RESERVED5; - __IM uint32_t RESERVED6[23]; + __IM unsigned int RESERVED6[23]; union { __IOM uint16_t SPI_SYS_RESET_REQ; /*!< (@ 0x0000007C) SPI SYS Reset Req Register */ @@ -9856,23 +9856,23 @@ typedef struct { /*!< (@ 0x20200000) SPI_SLAVE Structure */ __IOM uint16_t RESERVED1 : 14; /*!< [15..2] reserved1 */ } SPI_WAKE_UP_b; }; - __IM uint32_t RESERVED7[192]; + __IM unsigned int RESERVED7[192]; union { - __IM uint32_t SPI_RFIFO_DATA; /*!< (@ 0x00000380) SPI RFIFO Data Register */ + __IM unsigned int SPI_RFIFO_DATA; /*!< (@ 0x00000380) SPI RFIFO Data Register */ struct { - __IM uint32_t SPI_RFIFO : 32; /*!< [31..0] These bits store the data + __IM unsigned int SPI_RFIFO : 32; /*!< [31..0] These bits store the data received from the host */ } SPI_RFIFO_DATA_b; }; - __IM uint32_t RESERVED8[15]; + __IM unsigned int RESERVED8[15]; union { - __OM uint32_t SPI_WFIFO_DATA; /*!< (@ 0x000003C0) SPI WFIFO Data Register */ + __OM unsigned int SPI_WFIFO_DATA; /*!< (@ 0x000003C0) SPI WFIFO Data Register */ struct { - __OM uint32_t SPI_WFIFO : 32; /*!< [31..0] These bits are used to write, + __OM unsigned int SPI_WFIFO : 32; /*!< [31..0] These bits are used to write, the data to be sent to the host. */ } SPI_WFIFO_DATA_b; }; @@ -9894,65 +9894,65 @@ typedef struct { /*!< (@ 0x20200000) SPI_SLAVE Structure */ typedef struct { /*!< (@ 0x46000000) M4CLK Structure */ union { - __IOM uint32_t CLK_ENABLE_SET_REG1; /*!< (@ 0x00000000) Clock Enable Set + __IOM unsigned int CLK_ENABLE_SET_REG1; /*!< (@ 0x00000000) Clock Enable Set Register 1 */ struct { - __IOM uint32_t USART1_PCLK_ENABLE_b : 1; /*!< [0..0] Static Clock gating Enable for + __IOM unsigned int USART1_PCLK_ENABLE_b : 1; /*!< [0..0] Static Clock gating Enable for usart1 pclk1'b1 => Clock is enabled 1'b0 => Invalid */ - __IOM uint32_t USART1_SCLK_ENABLE_b : 1; /*!< [1..1] Static Clock gating Enable for + __IOM unsigned int USART1_SCLK_ENABLE_b : 1; /*!< [1..1] Static Clock gating Enable for usart1 sclk1'b1 => Clock is enabled 1'b0 => Invalid */ - __IOM uint32_t USART2_PCLK_ENABLE_b : 1; /*!< [2..2] Static Clock gating Enable for + __IOM unsigned int USART2_PCLK_ENABLE_b : 1; /*!< [2..2] Static Clock gating Enable for usart2 pclk1'b1 => Clock is enabled 1'b0 => Invalid */ - __IOM uint32_t USART2_SCLK_ENABLE_b : 1; /*!< [3..3] Static Clock gating Enable for + __IOM unsigned int USART2_SCLK_ENABLE_b : 1; /*!< [3..3] Static Clock gating Enable for usart2 sclk1'b1 => Clock is enabled 1'b0 => Invalid */ - __IOM uint32_t Reserved1 : 5; /*!< [8..4] It is recommended to write these + __IOM unsigned int Reserved1 : 5; /*!< [8..4] It is recommended to write these bits to 0. */ - __IOM uint32_t CT_CLK_ENABLE_b : 1; /*!< [9..9] Static Clock gating Enable + __IOM unsigned int CT_CLK_ENABLE_b : 1; /*!< [9..9] Static Clock gating Enable for sct clk1'b1 => Clock is enabled 1'b0 => Invalid. */ - __IOM uint32_t CT_PCLK_ENABLE_b : 1; /*!< [10..10] Static Clock gating + __IOM unsigned int CT_PCLK_ENABLE_b : 1; /*!< [10..10] Static Clock gating Enable for sct pclk1'b1 => Clock is enabled 1'b0 => Invalid. */ - __IOM uint32_t ICACHE_CLK_ENABLE_b : 1; /*!< [11..11] Static Clock gating Enable for + __IOM unsigned int ICACHE_CLK_ENABLE_b : 1; /*!< [11..11] Static Clock gating Enable for icache clk1'b1 => Clock is enabled 1'b0 => Invalid. */ - __IOM uint32_t ICACHE_CLK_2X_ENABLE_b : 1; /*!< [12..12] Static Clock gating Enable + __IOM unsigned int ICACHE_CLK_2X_ENABLE_b : 1; /*!< [12..12] Static Clock gating Enable for icache 2x clk1'b1 => Clock is enabled 1'b0 => Invalid. */ - __IOM uint32_t RPDMA_HCLK_ENABLE_b : 1; /*!< [13..13] Static Clock gating Enable for + __IOM unsigned int RPDMA_HCLK_ENABLE_b : 1; /*!< [13..13] Static Clock gating Enable for rpdma hclk1'b1 => Clock is enabled 1'b0 => Invalid. */ - __IOM uint32_t SOC_PLL_SPI_CLK_ENABLE_b : 1; /*!< [14..14] Static Clock gating Enable + __IOM unsigned int SOC_PLL_SPI_CLK_ENABLE_b : 1; /*!< [14..14] Static Clock gating Enable for soc pll spi clk1'b1 => Clock is enabled 1'b0 => Invalid. */ - __IOM uint32_t Reserved2 : 1; /*!< [15..15] It is recommended to write + __IOM unsigned int Reserved2 : 1; /*!< [15..15] It is recommended to write these bits to 0. */ - __IOM uint32_t IID_CLK_ENABLE_b : 1; /*!< [16..16] Static Clock gating + __IOM unsigned int IID_CLK_ENABLE_b : 1; /*!< [16..16] Static Clock gating Enable for iid clk1'b1 => Clock is enabled 1'b0 => Invalid. */ - __IOM uint32_t SDIO_SYS_HCLK_ENABLE_b : 1; /*!< [17..17] Static Clock gating Enable + __IOM unsigned int SDIO_SYS_HCLK_ENABLE_b : 1; /*!< [17..17] Static Clock gating Enable for sdio sys hclk1'b1 => Clock is enabled 1'b0 => Invalid */ - __IOM uint32_t CRC_CLK_ENABLE_b : 1; /*!< [18..18] Static Clock gating + __IOM unsigned int CRC_CLK_ENABLE_b : 1; /*!< [18..18] Static Clock gating Enable for crc clk1'b1 => Clock is enabled 1'b0 => Invalid */ - __IOM uint32_t Reserved3 : 3; /*!< [21..19] It is recommended to write + __IOM unsigned int Reserved3 : 3; /*!< [21..19] It is recommended to write these bits to 0. */ - __IOM uint32_t HWRNG_PCLK_ENABLE_b : 1; /*!< [22..22] Static Clock gating Enable for + __IOM unsigned int HWRNG_PCLK_ENABLE_b : 1; /*!< [22..22] Static Clock gating Enable for HWRNG pclk1'b1 => Clock is enabled 1'b0 => Invalid. */ - __IOM uint32_t GNSS_MEM_CLK_ENABLE_b : 1; /*!< [23..23] Static Clock gating Enable + __IOM unsigned int GNSS_MEM_CLK_ENABLE_b : 1; /*!< [23..23] Static Clock gating Enable for GNSS mem clk1'b1 => Clock is enabled 1'b0 => Invalid */ - __IOM uint32_t Reserved4 : 3; /*!< [26..24] It is recommended to write + __IOM unsigned int Reserved4 : 3; /*!< [26..24] It is recommended to write these bits to 0. */ - __IOM uint32_t MASK_HOST_CLK_WAIT_FIX_b : 1; /*!< [27..27] This bit decides whether + __IOM unsigned int MASK_HOST_CLK_WAIT_FIX_b : 1; /*!< [27..27] This bit decides whether to wait for a fixed number of xtal clock cycles(based on mask31_host_clk_cnt) or wait for a @@ -9963,7 +9963,7 @@ typedef struct { /*!< (@ 0x46000000) M4CLK Structure */ with mask_host_clk_available_fix and mask31_host_clk_cnt are to take care in case of any bugs. */ - __IOM uint32_t MASK31_HOST_CLK_CNT_b : 1; /*!< [28..28] When mask_host_clk_wait_fix + __IOM unsigned int MASK31_HOST_CLK_CNT_b : 1; /*!< [28..28] When mask_host_clk_wait_fix is 1'b1, this bit decides whether to count for 32 0r 16 xtal clock cycles to come out of WAIT state in host mux FSM @@ -9972,9 +9972,9 @@ typedef struct { /*!< (@ 0x46000000) M4CLK Structure */ mask_host_clk_available_fix and mask_host_clk_wait_fix are to take care in case of any bugs. */ - __IOM uint32_t Reserved5 : 1; /*!< [29..29] It is recommended to write + __IOM unsigned int Reserved5 : 1; /*!< [29..29] It is recommended to write these bits to 0. */ - __IOM uint32_t MASK_HOST_CLK_AVAILABLE_FIX_b : 1; /*!< [30..30] This bit decides + __IOM unsigned int MASK_HOST_CLK_AVAILABLE_FIX_b : 1; /*!< [30..30] This bit decides whether to consider negedge of host_clk_available in the generation of clock enable for @@ -9985,7 +9985,7 @@ typedef struct { /*!< (@ 0x46000000) M4CLK Structure */ mask31_host_clk_cnt are to take care in case of any bugs. */ - __IOM uint32_t ULPSS_CLK_ENABLE_b : 1; /*!< [31..31] Static Clock gating Enable for + __IOM unsigned int ULPSS_CLK_ENABLE_b : 1; /*!< [31..31] Static Clock gating Enable for m4 soc_clk to ulpss1'b1 => Clock is enabled 1'b0 => Invalid. */ @@ -9993,61 +9993,61 @@ typedef struct { /*!< (@ 0x46000000) M4CLK Structure */ }; union { - __IOM uint32_t CLK_ENABLE_CLEAR_REG1; /*!< (@ 0x00000004) Clock Enable Clear + __IOM unsigned int CLK_ENABLE_CLEAR_REG1; /*!< (@ 0x00000004) Clock Enable Clear Register 1 */ struct { - __IOM uint32_t USART1_PCLK_ENABLE_b : 1; /*!< [0..0] Static Clock Clear + __IOM unsigned int USART1_PCLK_ENABLE_b : 1; /*!< [0..0] Static Clock Clear for usart1 pclk1'b1 => Clock is Clear 1'b0 => Invalid */ - __IOM uint32_t USART1_SCLK_ENABLE_b : 1; /*!< [1..1] Static Clock Clear + __IOM unsigned int USART1_SCLK_ENABLE_b : 1; /*!< [1..1] Static Clock Clear for usart1 sclk1'b1 => Clock is Clear 1'b0 => Invalid */ - __IOM uint32_t USART2_PCLK_ENABLE_b : 1; /*!< [2..2] Static Clock Clear + __IOM unsigned int USART2_PCLK_ENABLE_b : 1; /*!< [2..2] Static Clock Clear for usart2 pclk 1'b1 => Clock is Clear 1'b0 => Invalid */ - __IOM uint32_t USART2_SCLK_ENABLE_b : 1; /*!< [3..3] Static Clock Clear + __IOM unsigned int USART2_SCLK_ENABLE_b : 1; /*!< [3..3] Static Clock Clear for usart2 sclk1'b1 => Clock is Clear 1'b0 => Invalid */ - __IOM uint32_t Reserved1 : 5; /*!< [8..4] It is recommended to write these + __IOM unsigned int Reserved1 : 5; /*!< [8..4] It is recommended to write these bits to 0. */ - __IOM uint32_t CT_CLK_ENABLE_b : 1; /*!< [9..9] Static Clock Clear for sct clk1'b1 => + __IOM unsigned int CT_CLK_ENABLE_b : 1; /*!< [9..9] Static Clock Clear for sct clk1'b1 => Clock is Clear 1'b0 => Invalid. */ - __IOM uint32_t CT_PCLK_ENABLE_b : 1; /*!< [10..10] Static Clock Clear for + __IOM unsigned int CT_PCLK_ENABLE_b : 1; /*!< [10..10] Static Clock Clear for sct pclk1'b1 => Clock is Clear 1'b0 => Invalid. */ - __IOM uint32_t ICACHE_CLK_ENABLE_b : 1; /*!< [11..11] Static Clock Clear + __IOM unsigned int ICACHE_CLK_ENABLE_b : 1; /*!< [11..11] Static Clock Clear for icache clk1'b1 => Clock is Clear 1'b0 => Invalid. */ - __IOM uint32_t ICACHE_CLK_2X_ENABLE_b : 1; /*!< [12..12] Static Clock Clear for + __IOM unsigned int ICACHE_CLK_2X_ENABLE_b : 1; /*!< [12..12] Static Clock Clear for icache 2x clk1'b1 => Clock is Clear 1'b0 => Invalid. */ - __IOM uint32_t RPDMA_HCLK_ENABLE_b : 1; /*!< [13..13] Static Clock Clear + __IOM unsigned int RPDMA_HCLK_ENABLE_b : 1; /*!< [13..13] Static Clock Clear for rpdma hclk1'b1 => Clock is Clear 1'b0 => Invalid. */ - __IOM uint32_t SOC_PLL_SPI_CLK_ENABLE_b : 1; /*!< [14..14] Static Clock Clear for soc + __IOM unsigned int SOC_PLL_SPI_CLK_ENABLE_b : 1; /*!< [14..14] Static Clock Clear for soc pll spi clk1'b1 => Clock is Clear 1'b0 => Invalid. */ - __IOM uint32_t Reserved2 : 1; /*!< [15..15] It is recommended to write + __IOM unsigned int Reserved2 : 1; /*!< [15..15] It is recommended to write these bits to 0. */ - __IOM uint32_t IID_CLK_ENABLE_b : 1; /*!< [16..16] Static Clock Clear for iid clk1'b1 + __IOM unsigned int IID_CLK_ENABLE_b : 1; /*!< [16..16] Static Clock Clear for iid clk1'b1 => Clock is Clear 1'b0 => Invalid. */ - __IOM uint32_t SDIO_SYS_HCLK_ENABLE_b : 1; /*!< [17..17] Static Clock Clear for sdio + __IOM unsigned int SDIO_SYS_HCLK_ENABLE_b : 1; /*!< [17..17] Static Clock Clear for sdio sys hclk1'b1 => Clock is Clear 1'b0 => Invalid */ - __IOM uint32_t CRC_CLK_ENABLE_b : 1; /*!< [18..18] Static Clock Clear for crc clk1'b1 + __IOM unsigned int CRC_CLK_ENABLE_b : 1; /*!< [18..18] Static Clock Clear for crc clk1'b1 => Clock is Clear 1'b0 => Invalid */ - __IOM uint32_t Reserved3 : 3; /*!< [21..19] It is recommended to write + __IOM unsigned int Reserved3 : 3; /*!< [21..19] It is recommended to write these bits to 0. */ - __IOM uint32_t HWRNG_PCLK_ENABLE_b : 1; /*!< [22..22] Static Clock Clear + __IOM unsigned int HWRNG_PCLK_ENABLE_b : 1; /*!< [22..22] Static Clock Clear for HWRNG pclk1'b1 => Clock is Clear 1'b0 => Invalid. */ - __IOM uint32_t GNSS_MEM_CLK_ENABLE_b : 1; /*!< [23..23] Static Clock Clear + __IOM unsigned int GNSS_MEM_CLK_ENABLE_b : 1; /*!< [23..23] Static Clock Clear for GNSS mem clk1'b1 => Clock is Clear 1'b0 => Invalid */ - __IOM uint32_t Reserved4 : 3; /*!< [26..24] It is recommended to write + __IOM unsigned int Reserved4 : 3; /*!< [26..24] It is recommended to write these bits to 0. */ - __IOM uint32_t MASK_HOST_CLK_WAIT_FIX_b : 1; /*!< [27..27] This bit decides whether + __IOM unsigned int MASK_HOST_CLK_WAIT_FIX_b : 1; /*!< [27..27] This bit decides whether to wait for a fixed number of xtal clock cycles(based on mask31_host_clk_cnt) or wait for a @@ -10058,7 +10058,7 @@ typedef struct { /*!< (@ 0x46000000) M4CLK Structure */ with mask_host_clk_available_fix and mask31_host_clk_cnt are to take care in case of any bugs. */ - __IOM uint32_t MASK31_HOST_CLK_CNT_b : 1; /*!< [28..28] When mask_host_clk_wait_fix + __IOM unsigned int MASK31_HOST_CLK_CNT_b : 1; /*!< [28..28] When mask_host_clk_wait_fix is 1'b1, this bit decides whether to count for 32 0r 16 xtal clock cycles to come out of WAIT state in host mux FSM @@ -10067,9 +10067,9 @@ typedef struct { /*!< (@ 0x46000000) M4CLK Structure */ mask_host_clk_available_fix and mask_host_clk_wait_fix are to take care in case of any bugs. */ - __IOM uint32_t Reserved5 : 1; /*!< [29..29] It is recommended to write + __IOM unsigned int Reserved5 : 1; /*!< [29..29] It is recommended to write these bits to 0. */ - __IOM uint32_t MASK_HOST_CLK_AVAILABLE_FIX_b : 1; /*!< [30..30] This bit decides + __IOM unsigned int MASK_HOST_CLK_AVAILABLE_FIX_b : 1; /*!< [30..30] This bit decides whether to consider negedge of host_clk_available in the generation of clock enable for @@ -10080,7 +10080,7 @@ typedef struct { /*!< (@ 0x46000000) M4CLK Structure */ mask31_host_clk_cnt are to take care in case of any bugs. */ - __IOM uint32_t ULPSS_CLK_ENABLE_b : 1; /*!< [31..31] Static Clock gating Enable for + __IOM unsigned int ULPSS_CLK_ENABLE_b : 1; /*!< [31..31] Static Clock gating Enable for m4 soc_clk to ulpss1'b1 => Clock is enabled 1'b0 => Invalid. */ @@ -10088,326 +10088,326 @@ typedef struct { /*!< (@ 0x46000000) M4CLK Structure */ }; union { - __IOM uint32_t CLK_ENABLE_SET_REG2; /*!< (@ 0x00000008) Clock Enable Set + __IOM unsigned int CLK_ENABLE_SET_REG2; /*!< (@ 0x00000008) Clock Enable Set Register 2 */ struct { - __IOM uint32_t GEN_SPI_MST1_HCLK_ENABLE_b : 1; /*!< [0..0] Static Clock gating Enable + __IOM unsigned int GEN_SPI_MST1_HCLK_ENABLE_b : 1; /*!< [0..0] Static Clock gating Enable for gen spi master1 hclk 1'b1 => Clock is enabled 1'b0 => Invalid */ - __IOM uint32_t Reserved1 : 5; /*!< [5..1] It is recommended to write these + __IOM unsigned int Reserved1 : 5; /*!< [5..1] It is recommended to write these bits to 0. */ - __IOM uint32_t UDMA_HCLK_ENABLE_b : 1; /*!< [6..6] Static Clock gating Enable for + __IOM unsigned int UDMA_HCLK_ENABLE_b : 1; /*!< [6..6] Static Clock gating Enable for udma hclk 1'b1 => Clock is enabled 1'b0 => Invalid. */ - __IOM uint32_t I2C_BUS_CLK_ENABLE_b : 1; /*!< [7..7] Static Clock gating Enable for + __IOM unsigned int I2C_BUS_CLK_ENABLE_b : 1; /*!< [7..7] Static Clock gating Enable for i2c-1 bus clk1'b1 => Clock is enabled 1'b0 => Invalid. */ - __IOM uint32_t I2C_2_BUS_CLK_ENABLE_b : 1; /*!< [8..8] Static Clock gating Enable for + __IOM unsigned int I2C_2_BUS_CLK_ENABLE_b : 1; /*!< [8..8] Static Clock gating Enable for i2c-2 bus clk 1'b1 => Clock is enabled 1'b0 => Invalid. */ - __IOM uint32_t SSI_SLV_PCLK_ENABLE_b : 1; /*!< [9..9] Static Clock gating Enable for + __IOM unsigned int SSI_SLV_PCLK_ENABLE_b : 1; /*!< [9..9] Static Clock gating Enable for ssi slave pclk 1'b1 => Clock is enabled 1'b0 => Invalid. */ __IOM - uint32_t SSI_SLV_SCLK_ENABLE_b : 1; /*!< [10..10] Static Clock gating + unsigned int SSI_SLV_SCLK_ENABLE_b : 1; /*!< [10..10] Static Clock gating Enable for ssi slave sclk 1'b1 => Clock is enabled 1'b0 => Invalid. */ - __IOM uint32_t QSPI_CLK_ENABLE_b : 1; /*!< [11..11] Static Clock gating + __IOM unsigned int QSPI_CLK_ENABLE_b : 1; /*!< [11..11] Static Clock gating Enable for qspi clk 1'b1 => Clock is enabled 1'b0 => Invalid. */ - __IOM uint32_t QSPI_HCLK_ENABLE_b : 1; /*!< [12..12] Static Clock gating Enable for + __IOM unsigned int QSPI_HCLK_ENABLE_b : 1; /*!< [12..12] Static Clock gating Enable for qspi hclk 1'b1 => Clock is enabled 1'b0 => Invalid. */ - __IOM uint32_t I2SM_SCLK_ENABLE_b : 1; /*!< [13..13] Static Clock gating Enable for + __IOM unsigned int I2SM_SCLK_ENABLE_b : 1; /*!< [13..13] Static Clock gating Enable for sclk of I2S at Root Clock generation 1'b1 => Clock is enabled 1'b0 => Invalid. */ - __IOM uint32_t I2SM_INTF_SCLK_ENABLE_b : 1; /*!< [14..14] Static Clock gating Enable + __IOM unsigned int I2SM_INTF_SCLK_ENABLE_b : 1; /*!< [14..14] Static Clock gating Enable for i2s interface sclk 1'b1 => Clock is enabled 1'b0 => Invalid. */ - __IOM uint32_t I2SM_PCLK_ENABLE_b : 1; /*!< [15..15] Static Clock gating Enable for + __IOM unsigned int I2SM_PCLK_ENABLE_b : 1; /*!< [15..15] Static Clock gating Enable for i2s master pclk 1'b1 => Clock is enabled 1'b0 => Invalid. */ - __IOM uint32_t Reserved2 : 1; /*!< [16..16] It is recommended to write + __IOM unsigned int Reserved2 : 1; /*!< [16..16] It is recommended to write these bits to 0. */ - __IOM uint32_t QE_PCLK_ENABLE_b : 1; /*!< [17..17] Static Clock gating Enable for qe + __IOM unsigned int QE_PCLK_ENABLE_b : 1; /*!< [17..17] Static Clock gating Enable for qe pclk 1'b1 => Clock is enabled 1'b0 => Invalid. */ - __IOM uint32_t MCPWM_PCLK_ENABLE_b : 1; /*!< [18..18] Static Clock gating Enable for + __IOM unsigned int MCPWM_PCLK_ENABLE_b : 1; /*!< [18..18] Static Clock gating Enable for mcpwm pclk 1'b1 => Clock is enabled 1'b0 => Invalid. */ - __IOM uint32_t Reserved3 : 1; /*!< [19..19] It is recommended to write + __IOM unsigned int Reserved3 : 1; /*!< [19..19] It is recommended to write these bits to 0. */ - __IOM uint32_t SGPIO_PCLK_ENABLE_b : 1; /*!< [20..20] Static Clock gating Enable for + __IOM unsigned int SGPIO_PCLK_ENABLE_b : 1; /*!< [20..20] Static Clock gating Enable for sgpio pclk 1'b1 => Clock is enabled 1'b0 => Invalid. */ - __IOM uint32_t EGPIO_PCLK_ENABLE_b : 1; /*!< [21..21] Static Clock gating Enable for + __IOM unsigned int EGPIO_PCLK_ENABLE_b : 1; /*!< [21..21] Static Clock gating Enable for egpio pclk 1'b1 => Clock is enabled 1'b0 => Invalid. */ - __IOM uint32_t ARM_CLK_ENABLE_b : 1; /*!< [22..22] Static Clock gating + __IOM unsigned int ARM_CLK_ENABLE_b : 1; /*!< [22..22] Static Clock gating Enable for arm clk 1'b1 => Clock is enabled 1'b0 => Invalid. */ - __IOM uint32_t SSI_MST_PCLK_ENABLE_b : 1; /*!< [23..23] Static Clock gating Enable + __IOM unsigned int SSI_MST_PCLK_ENABLE_b : 1; /*!< [23..23] Static Clock gating Enable for ssi master pclk 1'b1 => Clock is enabled 1'b0 => Invalid. */ - __IOM uint32_t SSI_MST_SCLK_ENABLE_b : 1; /*!< [24..24] Static Clock gating Enable + __IOM unsigned int SSI_MST_SCLK_ENABLE_b : 1; /*!< [24..24] Static Clock gating Enable for ssi master sclk 1'b1 => Clock is enabled 1'b0 => Invalid. */ - __IOM uint32_t Reserved4 : 1; /*!< [25..25] It is recommended to write + __IOM unsigned int Reserved4 : 1; /*!< [25..25] It is recommended to write these bits to 0. */ - __IOM uint32_t MEM_CLK_ULP_ENABLE_b : 1; /*!< [26..26] Static Clock gating Enable for + __IOM unsigned int MEM_CLK_ULP_ENABLE_b : 1; /*!< [26..26] Static Clock gating Enable for mem ulp clk 1'b1 => Clock is enabled 1'b0 => Invalid. */ - __IOM uint32_t ROM_CLK_ENABLE_b : 1; /*!< [27..27] Static Clock gating + __IOM unsigned int ROM_CLK_ENABLE_b : 1; /*!< [27..27] Static Clock gating Enable for rom clk 1'b1 => Clock is enabled 1'b0 => Invalid. */ - __IOM uint32_t PLL_INTF_CLK_ENABLE_b : 1; /*!< [28..28] Static Clock gating Enable + __IOM unsigned int PLL_INTF_CLK_ENABLE_b : 1; /*!< [28..28] Static Clock gating Enable for pll intf clk 1'b1 => Clock is enabled 1'b0 => Invalid. */ - __IOM uint32_t Reserved5 : 3; /*!< [31..29] It is recommended to write + __IOM unsigned int Reserved5 : 3; /*!< [31..29] It is recommended to write these bits to 0. */ } CLK_ENABLE_SET_REG2_b; }; union { - __IOM uint32_t CLK_ENABLE_CLEAR_REG2; /*!< (@ 0x0000000C) Clock Enable Clear + __IOM unsigned int CLK_ENABLE_CLEAR_REG2; /*!< (@ 0x0000000C) Clock Enable Clear Register 2 */ struct { - __IOM uint32_t GEN_SPI_MST1_HCLK_ENABLE_b : 1; /*!< [0..0] Static Clock Clear for gen + __IOM unsigned int GEN_SPI_MST1_HCLK_ENABLE_b : 1; /*!< [0..0] Static Clock Clear for gen spi master1 hclk 1'b1 => Clock is Clear 1'b0 => Invalid */ - __IOM uint32_t Reserved1 : 5; /*!< [5..1] It is recommended to write these + __IOM unsigned int Reserved1 : 5; /*!< [5..1] It is recommended to write these bits to 0. */ - __IOM uint32_t UDMA_HCLK_ENABLE_b : 1; /*!< [6..6] Static Clock Clear for + __IOM unsigned int UDMA_HCLK_ENABLE_b : 1; /*!< [6..6] Static Clock Clear for udma hclk 1'b1 => Clock is Clear 1'b0 => Invalid. */ - __IOM uint32_t I2C_BUS_CLK_ENABLE_b : 1; /*!< [7..7] Static Clock Clear + __IOM unsigned int I2C_BUS_CLK_ENABLE_b : 1; /*!< [7..7] Static Clock Clear for i2c-1 bus clk1'b1 => Clock is Clear 1'b0 => Invalid. */ - __IOM uint32_t I2C_2_BUS_CLK_ENABLE_b : 1; /*!< [8..8] Static Clock Clear for i2c-2 + __IOM unsigned int I2C_2_BUS_CLK_ENABLE_b : 1; /*!< [8..8] Static Clock Clear for i2c-2 bus clk 1'b1 => Clock is Clear 1'b0 => Invalid. */ - __IOM uint32_t SSI_SLV_PCLK_ENABLE_b : 1; /*!< [9..9] Static Clock Clear for ssi + __IOM unsigned int SSI_SLV_PCLK_ENABLE_b : 1; /*!< [9..9] Static Clock Clear for ssi slave pclk 1'b1 => Clock is Clear 1'b0 => Invalid. */ - __IOM uint32_t SSI_SLV_SCLK_ENABLE_b : 1; /*!< [10..10] Static Clock Clear for ssi + __IOM unsigned int SSI_SLV_SCLK_ENABLE_b : 1; /*!< [10..10] Static Clock Clear for ssi slave sclk 1'b1 => Clock is Clear 1'b0 => Invalid. */ - __IOM uint32_t QSPI_CLK_ENABLE_b : 1; /*!< [11..11] Static Clock Clear for qspi clk + __IOM unsigned int QSPI_CLK_ENABLE_b : 1; /*!< [11..11] Static Clock Clear for qspi clk 1'b1 => Clock is Clear 1'b0 => Invalid. */ - __IOM uint32_t QSPI_HCLK_ENABLE_b : 1; /*!< [12..12] Static Clock Clear + __IOM unsigned int QSPI_HCLK_ENABLE_b : 1; /*!< [12..12] Static Clock Clear for qspi hclk 1'b1 => Clock is Clear 1'b0 => Invalid. */ - __IOM uint32_t I2SM_SCLK_ENABLE_b : 1; /*!< [13..13] Static Clock Clear + __IOM unsigned int I2SM_SCLK_ENABLE_b : 1; /*!< [13..13] Static Clock Clear for sclk of I2S at Root Clock generation 1'b1 => Clock is Clear 1'b0 => Invalid. */ - __IOM uint32_t I2SM_INTF_SCLK_ENABLE_b : 1; /*!< [14..14] Static Clock Clear for i2s + __IOM unsigned int I2SM_INTF_SCLK_ENABLE_b : 1; /*!< [14..14] Static Clock Clear for i2s interface sclk 1'b1 => Clock is Clear 1'b0 => Invalid. */ - __IOM uint32_t I2SM_PCLK_ENABLE_b : 1; /*!< [15..15] Static Clock Clear for i2s + __IOM unsigned int I2SM_PCLK_ENABLE_b : 1; /*!< [15..15] Static Clock Clear for i2s master pclk 1'b1 => Clock is Clear 1'b0 => Invalid. */ - __IOM uint32_t Reserved2 : 1; /*!< [16..16] It is recommended to write + __IOM unsigned int Reserved2 : 1; /*!< [16..16] It is recommended to write these bits to 0. */ - __IOM uint32_t QE_PCLK_ENABLE_b : 1; /*!< [17..17] Static Clock Clear for qe pclk + __IOM unsigned int QE_PCLK_ENABLE_b : 1; /*!< [17..17] Static Clock Clear for qe pclk 1'b1 => Clock is Clear 1'b0 => Invalid. */ - __IOM uint32_t MCPWM_PCLK_ENABLE_b : 1; /*!< [18..18] Static Clock Clear + __IOM unsigned int MCPWM_PCLK_ENABLE_b : 1; /*!< [18..18] Static Clock Clear for mcpwm pclk 1'b1 => Clock is Clear 1'b0 => Invalid. */ - __IOM uint32_t Reserved3 : 1; /*!< [19..19] It is recommended to write + __IOM unsigned int Reserved3 : 1; /*!< [19..19] It is recommended to write these bits to 0. */ - __IOM uint32_t SGPIO_PCLK_ENABLE_b : 1; /*!< [20..20] Static Clock Clear + __IOM unsigned int SGPIO_PCLK_ENABLE_b : 1; /*!< [20..20] Static Clock Clear for sgpio pclk 1'b1 => Clock is Clear 1'b0 => Invalid. */ - __IOM uint32_t EGPIO_PCLK_ENABLE_b : 1; /*!< [21..21] Static Clock Clear + __IOM unsigned int EGPIO_PCLK_ENABLE_b : 1; /*!< [21..21] Static Clock Clear for egpio pclk 1'b1 => Clock is Clear 1'b0 => Invalid. */ - __IOM uint32_t ARM_CLK_ENABLE_b : 1; /*!< [22..22] Static Clock Clear for arm clk + __IOM unsigned int ARM_CLK_ENABLE_b : 1; /*!< [22..22] Static Clock Clear for arm clk 1'b1 => Clock is Clear 1'b0 => Invalid. */ - __IOM uint32_t SSI_MST_PCLK_ENABLE_b : 1; /*!< [23..23] Static Clock Clear for ssi + __IOM unsigned int SSI_MST_PCLK_ENABLE_b : 1; /*!< [23..23] Static Clock Clear for ssi master pclk 1'b1 => Clock is Clear 1'b0 => Invalid. */ - __IOM uint32_t SSI_MST_SCLK_ENABLE_b : 1; /*!< [24..24] Static Clock Clear for ssi + __IOM unsigned int SSI_MST_SCLK_ENABLE_b : 1; /*!< [24..24] Static Clock Clear for ssi master sclk 1'b1 => Clock is Clear 1'b0 => Invalid. */ - __IOM uint32_t Reserved4 : 1; /*!< [25..25] It is recommended to write + __IOM unsigned int Reserved4 : 1; /*!< [25..25] It is recommended to write these bits to 0. */ - __IOM uint32_t MEM_CLK_ULP_ENABLE_b : 1; /*!< [26..26] Static Clock Clear + __IOM unsigned int MEM_CLK_ULP_ENABLE_b : 1; /*!< [26..26] Static Clock Clear for mem ulp clk 1'b1 => Clock is Clear 1'b0 => Invalid. */ - __IOM uint32_t ROM_CLK_ENABLE_b : 1; /*!< [27..27] Static Clock Clear for rom clk + __IOM unsigned int ROM_CLK_ENABLE_b : 1; /*!< [27..27] Static Clock Clear for rom clk 1'b1 => Clock is Clear 1'b0 => Invalid. */ - __IOM uint32_t PLL_INTF_CLK_ENABLE_b : 1; /*!< [28..28] Static Clock Clear for pll + __IOM unsigned int PLL_INTF_CLK_ENABLE_b : 1; /*!< [28..28] Static Clock Clear for pll intf clk 1'b1 => Clock is Clear 1'b0 => Invalid. */ - __IOM uint32_t Reserved5 : 3; /*!< [31..29] It is recommended to write + __IOM unsigned int Reserved5 : 3; /*!< [31..29] It is recommended to write these bits to 0. */ } CLK_ENABLE_CLEAR_REG2_b; }; union { - __IOM uint32_t CLK_ENABLE_SET_REG3; /*!< (@ 0x00000010) Clock Enable Set + __IOM unsigned int CLK_ENABLE_SET_REG3; /*!< (@ 0x00000010) Clock Enable Set Register 3 */ struct { - __IOM uint32_t BUS_CLK_ENABLE_b : 1; /*!< [0..0] Static Clock gating + __IOM unsigned int BUS_CLK_ENABLE_b : 1; /*!< [0..0] Static Clock gating Enable for bus clk 1'b1 => Clock is enabled 1'b0 => Invalid */ - __IOM uint32_t M4_CORE_CLK_ENABLE_b : 1; /*!< [1..1] Static Clock gating Enable for + __IOM unsigned int M4_CORE_CLK_ENABLE_b : 1; /*!< [1..1] Static Clock gating Enable for M4 Core clk 1'b1 => Clock is enabled 1'b0 => Invalid. */ - __IOM uint32_t CM_BUS_CLK_ENABLE_b : 1; /*!< [2..2] Static Clock gating Enable for cm + __IOM unsigned int CM_BUS_CLK_ENABLE_b : 1; /*!< [2..2] Static Clock gating Enable for cm bus clk1'b1 => Clock is enabled1'b0 => Invalid. */ - __IOM uint32_t Reserved1 : 1; /*!< [3..3] It is recommended to write these + __IOM unsigned int Reserved1 : 1; /*!< [3..3] It is recommended to write these bits to 0. */ - __IOM uint32_t MISC_CONFIG_PCLK_ENABLE_b : 1; /*!< [4..4] Static Clock gating Enable + __IOM unsigned int MISC_CONFIG_PCLK_ENABLE_b : 1; /*!< [4..4] Static Clock gating Enable for misc config regs clk 1'b1 => Clock is enabled 1'b0 => Invalid. */ - __IOM uint32_t EFUSE_CLK_ENABLE_b : 1; /*!< [5..5] Static Clock gating Enable for + __IOM unsigned int EFUSE_CLK_ENABLE_b : 1; /*!< [5..5] Static Clock gating Enable for efuse clk 1'b1 => Clock is enabled 1'b0 => Invalid. */ - __IOM uint32_t ICM_CLK_ENABLE_b : 1; /*!< [6..6] Static Clock gating Enable for icm + __IOM unsigned int ICM_CLK_ENABLE_b : 1; /*!< [6..6] Static Clock gating Enable for icm clk 1'b1 => Clock is enabled 1'b0 => Invalid. */ - __IOM uint32_t Reserved2 : 6; /*!< [12..7] It is recommended to write + __IOM unsigned int Reserved2 : 6; /*!< [12..7] It is recommended to write these bits to 0. */ - __IOM uint32_t QSPI_CLK_ONEHOT_ENABLE_b : 1; /*!< [13..13] Static Clock gating Enable + __IOM unsigned int QSPI_CLK_ONEHOT_ENABLE_b : 1; /*!< [13..13] Static Clock gating Enable for QSPI clock generated from the dynamic mux 1b1 - Clock is enabled 1b0 - Invalid. */ - __IOM uint32_t QSPI_M4_SOC_SYNC_b : 1; /*!< [14..14] Specifies whether QSPI clock is + __IOM unsigned int QSPI_M4_SOC_SYNC_b : 1; /*!< [14..14] Specifies whether QSPI clock is in sync with Soc clock. Before enabling this make sure that qspi_clk_onehot_enable is 1b0 to enable glitch free switching 1b1 - QSPI clock is in sync with M4 clock 1b0 - Invalid. */ - __IOM uint32_t Reserved3 : 1; /*!< [15..15] It is recommended to write + __IOM unsigned int Reserved3 : 1; /*!< [15..15] It is recommended to write these bits to 0. */ - __IOM uint32_t EGPIO_CLK_ENABLE_b : 1; /*!< [16..16] Static Clock gating enable for + __IOM unsigned int EGPIO_CLK_ENABLE_b : 1; /*!< [16..16] Static Clock gating enable for Enhanced-GPIO 1b1 - Clock is enabled 1b0 - Invalid. */ - __IOM uint32_t I2C_CLK_ENABLE_b : 1; /*!< [17..17] Static Clock gating enable for + __IOM unsigned int I2C_CLK_ENABLE_b : 1; /*!< [17..17] Static Clock gating enable for I2C-1 Module 1b1 - Clock is enabled 1b0 - Invalid. */ - __IOM uint32_t I2C_2_CLK_ENABLE_b : 1; /*!< [18..18] Static Clock gating enable for + __IOM unsigned int I2C_2_CLK_ENABLE_b : 1; /*!< [18..18] Static Clock gating enable for I2C-2 Module 1b1 - Clock is enabled 1b0 - Invalid. */ - __IOM uint32_t EFUSE_PCLK_ENABLE_b : 1; /*!< [19..19] Static Clock gating + __IOM unsigned int EFUSE_PCLK_ENABLE_b : 1; /*!< [19..19] Static Clock gating enable for EFUSE APB Interface 1b1 - Clock is enabled 1b0 - Invalid. */ - __IOM uint32_t SGPIO_CLK_ENABLE_b : 1; /*!< [20..20] Static Clock gating enable for + __IOM unsigned int SGPIO_CLK_ENABLE_b : 1; /*!< [20..20] Static Clock gating enable for SIO Module 1b1 - Clock is enabled 1b0 - Invalid. */ - __IOM uint32_t TASS_M4SS_64K_SWITCH_CLK_ENABLE_b : 1; /*!< [21..21] Unused. */ - __IOM uint32_t TASS_M4SS_128K_SWITCH_CLK_ENABLE_b : 1; /*!< [22..22] Unused. */ - __IOM uint32_t TASS_M4SS_SDIO_SWITCH_CLK_ENABLE_b : 1; /*!< [23..23] Unused. */ - __IOM uint32_t Reserved4 : 1; /*!< [24..24] It is recommended to write + __IOM unsigned int TASS_M4SS_64K_SWITCH_CLK_ENABLE_b : 1; /*!< [21..21] Unused. */ + __IOM unsigned int TASS_M4SS_128K_SWITCH_CLK_ENABLE_b : 1; /*!< [22..22] Unused. */ + __IOM unsigned int TASS_M4SS_SDIO_SWITCH_CLK_ENABLE_b : 1; /*!< [23..23] Unused. */ + __IOM unsigned int Reserved4 : 1; /*!< [24..24] It is recommended to write these bits to 0. */ - __IOM uint32_t ROM_MISC_STATIC_ENABLE_b : 1; /*!< [25..25] Static Clock gating enable + __IOM unsigned int ROM_MISC_STATIC_ENABLE_b : 1; /*!< [25..25] Static Clock gating enable for rom ahb Clock 1b1 - Clock is enabled 1b0 - Invalid. */ - __IOM uint32_t M4_SOC_CLK_FOR_OTHER_ENABLE_b : 1; /*!< [26..26] Static Clock gating + __IOM unsigned int M4_SOC_CLK_FOR_OTHER_ENABLE_b : 1; /*!< [26..26] Static Clock gating enable for M4-SOC Other Clock 1b1 - Clock is enabled 1b0 - Invalid. */ - __IOM uint32_t ICACHE_ENABLE_b : 1; /*!< [27..27] Static Clock gating enable for + __IOM unsigned int ICACHE_ENABLE_b : 1; /*!< [27..27] Static Clock gating enable for Icache. This has to be enable for Icache operations. 1b1 - Clock is enabled 1b0 - Invalid. */ - __IOM uint32_t Reserved5 : 4; /*!< [31..28] It is recommended to write + __IOM unsigned int Reserved5 : 4; /*!< [31..28] It is recommended to write these bits to 0. */ } CLK_ENABLE_SET_REG3_b; }; union { - __IOM uint32_t CLK_ENABLE_CLEAR_REG3; /*!< (@ 0x00000014) Clock Enable Clear + __IOM unsigned int CLK_ENABLE_CLEAR_REG3; /*!< (@ 0x00000014) Clock Enable Clear Register 3 */ struct { - __IOM uint32_t BUS_CLK_ENABLE_b : 1; /*!< [0..0] Static Clock Clear for bus clk 1'b1 + __IOM unsigned int BUS_CLK_ENABLE_b : 1; /*!< [0..0] Static Clock Clear for bus clk 1'b1 => Clock is Clear 1'b0 => Invalid */ - __IOM uint32_t M4_CORE_CLK_ENABLE_b : 1; /*!< [1..1] Static Clock Clear + __IOM unsigned int M4_CORE_CLK_ENABLE_b : 1; /*!< [1..1] Static Clock Clear for M4 Core clk 1'b1 => Clock is Clear 1'b0 => Invalid. */ - __IOM uint32_t CM_BUS_CLK_ENABLE_b : 1; /*!< [2..2] Static Clock gating Enable for cm + __IOM unsigned int CM_BUS_CLK_ENABLE_b : 1; /*!< [2..2] Static Clock gating Enable for cm bus clk1'b1 => Clock is enabled1'b0 => Invalid. */ - __IOM uint32_t Reserved1 : 1; /*!< [3..3] It is recommended to write these + __IOM unsigned int Reserved1 : 1; /*!< [3..3] It is recommended to write these bits to 0. */ - __IOM uint32_t MISC_CONFIG_PCLK_ENABLE_b : 1; /*!< [4..4] Static Clock Clear for misc + __IOM unsigned int MISC_CONFIG_PCLK_ENABLE_b : 1; /*!< [4..4] Static Clock Clear for misc config regs clk 1'b1 => Clock is Clear 1'b0 => Invalid. */ - __IOM uint32_t EFUSE_CLK_ENABLE_b : 1; /*!< [5..5] Static Clock Clear for + __IOM unsigned int EFUSE_CLK_ENABLE_b : 1; /*!< [5..5] Static Clock Clear for efuse clk 1'b1 => Clock is Clear 1'b0 => Invalid. */ - __IOM uint32_t ICM_CLK_ENABLE_b : 1; /*!< [6..6] Static Clock Clear for icm clk 1'b1 + __IOM unsigned int ICM_CLK_ENABLE_b : 1; /*!< [6..6] Static Clock Clear for icm clk 1'b1 => Clock is Clear 1'b0 => Invalid. */ - __IOM uint32_t Reserved2 : 6; /*!< [12..7] It is recommended to write + __IOM unsigned int Reserved2 : 6; /*!< [12..7] It is recommended to write these bits to 0. */ - __IOM uint32_t QSPI_CLK_ONEHOT_ENABLE_b : 1; /*!< [13..13] Static Clock Clear for + __IOM unsigned int QSPI_CLK_ONEHOT_ENABLE_b : 1; /*!< [13..13] Static Clock Clear for QSPI clock generated from the dynamic mux 1b1 - Clock is Gated 1b0 - Invalid. */ - __IOM uint32_t QSPI_M4_SOC_SYNC_b : 1; /*!< [14..14] Specifies whether QSPI clock is + __IOM unsigned int QSPI_M4_SOC_SYNC_b : 1; /*!< [14..14] Specifies whether QSPI clock is in sync with Soc clock. Before enabling this make sure that qspi_clk_onehot_enable is 1b0 to enable glitch free switching 1b1 - QSPI clock is in sync with M4 clock 1b0 - Invalid. */ - __IOM uint32_t Reserved3 : 1; /*!< [15..15] It is recommended to write + __IOM unsigned int Reserved3 : 1; /*!< [15..15] It is recommended to write these bits to 0. */ - __IOM uint32_t EGPIO_CLK_ENABLE_b : 1; /*!< [16..16] Static Clock Disable for + __IOM unsigned int EGPIO_CLK_ENABLE_b : 1; /*!< [16..16] Static Clock Disable for Enhanced-GPIO 1b1 - Clock is Disable 1b0 - Invalid. */ - __IOM uint32_t I2C_CLK_ENABLE_b : 1; /*!< [17..17] Static Clock Disable + __IOM unsigned int I2C_CLK_ENABLE_b : 1; /*!< [17..17] Static Clock Disable for I2C-1 Module 1b1 - Clock is Disable 1b0 - Invalid. */ - __IOM uint32_t I2C_2_CLK_ENABLE_b : 1; /*!< [18..18] Static Clock Disable + __IOM unsigned int I2C_2_CLK_ENABLE_b : 1; /*!< [18..18] Static Clock Disable for I2C-2 Module 1b1 - Clock is Disable 1b0 - Invalid. */ - __IOM uint32_t EFUSE_PCLK_ENABLE_b : 1; /*!< [19..19] Static Clock Disable for EFUSE + __IOM unsigned int EFUSE_PCLK_ENABLE_b : 1; /*!< [19..19] Static Clock Disable for EFUSE APB Interface 1b1 - Clock is Disable 1b0 - Invalid. */ - __IOM uint32_t SGPIO_CLK_ENABLE_b : 1; /*!< [20..20] Static Clock gating enable for + __IOM unsigned int SGPIO_CLK_ENABLE_b : 1; /*!< [20..20] Static Clock gating enable for SIO Module 1b1 - Clock is enabled 1b0 - Invalid. */ - __IOM uint32_t TASS_M4SS_64K_SWITCH_CLK_ENABLE_b : 1; /*!< [21..21] Unused. */ - __IOM uint32_t TASS_M4SS_128K_SWITCH_CLK_ENABLE_b : 1; /*!< [22..22] Unused. */ - __IOM uint32_t TASS_M4SS_SDIO_SWITCH_CLK_ENABLE_b : 1; /*!< [23..23] Unused. */ - __IOM uint32_t Reserved4 : 1; /*!< [24..24] It is recommended to write + __IOM unsigned int TASS_M4SS_64K_SWITCH_CLK_ENABLE_b : 1; /*!< [21..21] Unused. */ + __IOM unsigned int TASS_M4SS_128K_SWITCH_CLK_ENABLE_b : 1; /*!< [22..22] Unused. */ + __IOM unsigned int TASS_M4SS_SDIO_SWITCH_CLK_ENABLE_b : 1; /*!< [23..23] Unused. */ + __IOM unsigned int Reserved4 : 1; /*!< [24..24] It is recommended to write these bits to 0. */ - __IOM uint32_t ROM_MISC_STATIC_ENABLE_b : 1; /*!< [25..25] Static Clock Disable for + __IOM unsigned int ROM_MISC_STATIC_ENABLE_b : 1; /*!< [25..25] Static Clock Disable for rom ahb Clock 1b1 - Clock is Disable 1b0 - Invalid. */ - __IOM uint32_t M4_SOC_CLK_FOR_OTHER_ENABLE_b : 1; /*!< [26..26] Static Clock Disable + __IOM unsigned int M4_SOC_CLK_FOR_OTHER_ENABLE_b : 1; /*!< [26..26] Static Clock Disable for M4-SOC Other Clock 1b1 - Clock is Disable 1b0 - Invalid. */ - __IOM uint32_t ICACHE_ENABLE_b : 1; /*!< [27..27] Static Clock Disable for Icache. + __IOM unsigned int ICACHE_ENABLE_b : 1; /*!< [27..27] Static Clock Disable for Icache. This has to be enable for Icache operations. 1b1 - Clock is Disable 1b0 - Invalid. */ - __IOM uint32_t Reserved5 : 4; /*!< [31..28] It is recommended to write + __IOM unsigned int Reserved5 : 4; /*!< [31..28] It is recommended to write these bits to 0. */ } CLK_ENABLE_CLEAR_REG3_b; }; union { - __IOM uint32_t CLK_CONFIG_REG1; /*!< (@ 0x00000018) Clock Config Register 1 */ + __IOM unsigned int CLK_CONFIG_REG1; /*!< (@ 0x00000018) Clock Config Register 1 */ struct { - __IOM uint32_t QSPI_CLK_SEL : 3; /*!< [2..0] Selects one of the following clocks for + __IOM unsigned int QSPI_CLK_SEL : 3; /*!< [2..0] Selects one of the following clocks for ssi master 000 - ULP Ref Clock(generated inside M4SS based on m4ss_ref_clk_sel from NPSS) 001 - Intf PLL Clock @@ -10417,7 +10417,7 @@ typedef struct { /*!< (@ 0x46000000) M4CLK Structure */ (program bypass_modem_pll_clk if the bypass clock has to be selected) 011 - SoC PLL Clock */ - __IOM uint32_t QSPI_CLK_DIV_FAC : 6; /*!< [8..3] Clock divison factor for QSPI. If + __IOM unsigned int QSPI_CLK_DIV_FAC : 6; /*!< [8..3] Clock divison factor for QSPI. If qspi_clk_enable is 1b0 clock is gated. Else 1)when qspi_clk_swallow_sel is 1b1 and qspi_odd_div_sel is 1b0 output clock is a @@ -10426,7 +10426,7 @@ typedef struct { /*!< (@ 0x46000000) M4CLK Structure */ clk_in/ qspi_clk_div_fac 2)when qspi_clk_swallow_sel is 1b0 */ __IOM - uint32_t QSPI_CLK_SWALLOW_SEL : 1; /*!< [9..9] Clock select for clock + unsigned int QSPI_CLK_SWALLOW_SEL : 1; /*!< [9..9] Clock select for clock swallow or clock divider for QSPI 1b0 => 50% divider is selected with division factor qspi_clk_div_fac 1b1 @@ -10434,17 +10434,17 @@ typedef struct { /*!< (@ 0x46000000) M4CLK Structure */ division factor qspi_clk_div_fac Before Changing this ensure that the input clocks are gated */ - __IOM uint32_t SLP_RF_CLK_SEL : 1; /*!< [10..10] clock select for + __IOM unsigned int SLP_RF_CLK_SEL : 1; /*!< [10..10] clock select for m4_soc_rf_ref_clk 0 - m4_soc_clk 1 - rf_ref_clk. */ - __IOM uint32_t SSI_MST_SCLK_DIV_FAC : 4; /*!< [14..11] Clock division factor for + __IOM unsigned int SSI_MST_SCLK_DIV_FAC : 4; /*!< [14..11] Clock division factor for ssi_mst_sclk. If ssi_mst_sclk_enable is 1b0 clock is gated. Else output clock is a swallowed clock with the following frequency. 4h0,4h1 => Divider is bypassed >4h1 => clk_out = clk_in/ ssi_mst_sclk_div_fac. */ - __IOM uint32_t SSI_MST_SCLK_SEL : 3; /*!< [17..15] Selects one of the following + __IOM unsigned int SSI_MST_SCLK_SEL : 3; /*!< [17..15] Selects one of the following clocks for ssi master 000 - ULP Ref Clock(generated inside M4SS based on m4ss_ref_clk_sel from NPSS) 001 - SoC PLL @@ -10455,26 +10455,26 @@ typedef struct { /*!< (@ 0x46000000) M4CLK Structure */ clock has to be selected) 011 - Intf PLL Clock(program bypass_intf_pll_clk if the */ - __IOM uint32_t PLL_INTF_CLK_SEL : 1; /*!< [18..18] Selects one of the following + __IOM unsigned int PLL_INTF_CLK_SEL : 1; /*!< [18..18] Selects one of the following clocks for pll intf clock 0 - Intf Pll Clock(program bypass_intf_pll_clk if the bypass clock has to be selected) 1 - SoC Pll Clock(program bypass_soc_pll_clk if the bypass clock has to be selected) */ - __IOM uint32_t PLL_INTF_CLK_DIV_FAC : 4; /*!< [22..19] Clock division factor for + __IOM unsigned int PLL_INTF_CLK_DIV_FAC : 4; /*!< [22..19] Clock division factor for pll_intf_clk. If pll_intf_clk_enable is 1b0 clock is gated. Else, when pll_intf_clk_swallow_sel is 1b1, output clock is a swallowed clock. when pll_intf_clk_swallow_sel is 1b0, output clock is a 50 Per duty cycle clock. */ - __IOM uint32_t PLL_INTF_CLK_SWALLOW_SEL : 1; /*!< [23..23] Clock select for clock + __IOM unsigned int PLL_INTF_CLK_SWALLOW_SEL : 1; /*!< [23..23] Clock select for clock swallow or clock divider for PLL INTF Clk 1b0 - 50% divider is selected with division factor 2; 1b1 - Swallowed clock is selected with division factor pll_intf_clk_div_fac */ - __IOM uint32_t GEN_SPI_MST1_SCLK_SEL : 3; /*!< [26..24] Selects one of the following + __IOM unsigned int GEN_SPI_MST1_SCLK_SEL : 3; /*!< [26..24] Selects one of the following clocks for USART1 clk 000 - m4_soc_clk_for_other_clocks 001 - ulp ref Clock(generated inside M4SS based on @@ -10484,16 +10484,16 @@ typedef struct { /*!< (@ 0x46000000) M4CLK Structure */ Modem PLL Clock2(Not Intended for the pragrammer) (program bypass_modem_pll_clk if the bypass clock has to be sele */ - __IOM uint32_t Reserved1 : 5; /*!< [31..27] It is recommended to write + __IOM unsigned int Reserved1 : 5; /*!< [31..27] It is recommended to write these bits to 0. */ } CLK_CONFIG_REG1_b; }; union { - __IOM uint32_t CLK_CONFIG_REG2; /*!< (@ 0x0000001C) Clock Config Register 1 */ + __IOM unsigned int CLK_CONFIG_REG2; /*!< (@ 0x0000001C) Clock Config Register 1 */ struct { - __IOM uint32_t USART1_SCLK_SEL : 3; /*!< [2..0] Selects one of the following clocks + __IOM unsigned int USART1_SCLK_SEL : 3; /*!< [2..0] Selects one of the following clocks for USART1 clk 000 - ulp ref Clock(generated inside M4SS based on m4ss_ref_clk_sel from NPSS) 001 - SoC @@ -10505,11 +10505,11 @@ typedef struct { /*!< (@ 0x46000000) M4CLK Structure */ Intf PLL Clock(program bypass_intf_pll_clk if the b */ - __IOM uint32_t USART1_SCLK_DIV_FAC : 4; /*!< [6..3] Clock division factor for USART1 + __IOM unsigned int USART1_SCLK_DIV_FAC : 4; /*!< [6..3] Clock division factor for USART1 Clock. If usart1_sclk_enable is 1b0 clock is gated. Else output clock is a swallowed clock. */ - __IOM uint32_t USART2_SCLK_SEL : 3; /*!< [9..7] Selects one of the following clocks + __IOM unsigned int USART2_SCLK_SEL : 3; /*!< [9..7] Selects one of the following clocks for USART2 clk 000 - ulp ref Clock(generated inside M4SS based on m4ss_ref_clk_sel from NPSS) 001 - SoC @@ -10521,13 +10521,13 @@ typedef struct { /*!< (@ 0x46000000) M4CLK Structure */ Intf PLL Clock(program bypass_intf_pll_clk if the b */ - __IOM uint32_t USART2_SCLK_DIV_FAC : 4; /*!< [13..10] Clock division factor for + __IOM unsigned int USART2_SCLK_DIV_FAC : 4; /*!< [13..10] Clock division factor for USART2 Clock. If usart2_sclk_enable is 1b0 clock is gated. Else output clock is a swallowed clock. */ - __IOM uint32_t Reserved1 : 14; /*!< [27..14] It is recommended to write + __IOM unsigned int Reserved1 : 14; /*!< [27..14] It is recommended to write these bits to 0. */ - __IOM uint32_t QSPI_ODD_DIV_SEL : 1; /*!< [28..28] Clock select for clock swallow or + __IOM unsigned int QSPI_ODD_DIV_SEL : 1; /*!< [28..28] Clock select for clock swallow or 50% even clock divider or 50% odd divider clock for QSPI 1b1 - 50% odd clock divider output is selected with division factor @@ -10535,15 +10535,15 @@ typedef struct { /*!< (@ 0x46000000) M4CLK Structure */ output or swallowed is selected with division factor qspi_clk_div_fac based on qspi_clk_swallow_sel. */ - __IOM uint32_t USART1_SCLK_FRAC_SEL : 1; /*!< [29..29] Selects the type of divider + __IOM unsigned int USART1_SCLK_FRAC_SEL : 1; /*!< [29..29] Selects the type of divider for uart1_clk 1b0 - Clock Swallow is selected 1b1 - Fractional Divider is selected. */ - __IOM uint32_t USART2_SCLK_FRAC_SEL : 1; /*!< [30..30] Selects the type of divider + __IOM unsigned int USART2_SCLK_FRAC_SEL : 1; /*!< [30..30] Selects the type of divider for uart2_clk 1b0 - Clock Swallow is selected 1b1 - Fractional Divider is selected. */ - __IOM uint32_t USART3_SCLK_FRAC_SEL : 1; /*!< [31..31] Selects the type of divider + __IOM unsigned int USART3_SCLK_FRAC_SEL : 1; /*!< [31..31] Selects the type of divider for uart3_clk 1b0 - Clock Swallow is selected 1b1 - Fractional Divider is selected. */ @@ -10551,98 +10551,98 @@ typedef struct { /*!< (@ 0x46000000) M4CLK Structure */ }; union { - __IOM uint32_t CLK_CONFIG_REG3; /*!< (@ 0x00000020) Clock Config Register 3 */ + __IOM unsigned int CLK_CONFIG_REG3; /*!< (@ 0x00000020) Clock Config Register 3 */ struct { - __IOM uint32_t Reserved1 : 8; /*!< [7..0] It is recommended to write these + __IOM unsigned int Reserved1 : 8; /*!< [7..0] It is recommended to write these bits to 0. */ - __IOM uint32_t MCU_CLKOUT_SEL : 4; /*!< [11..8] Clock Select for the clock + __IOM unsigned int MCU_CLKOUT_SEL : 4; /*!< [11..8] Clock Select for the clock on mcu_clkout (Mapped to GPIO) */ - __IOM uint32_t MCU_CLKOUT_DIV_FAC : 6; /*!< [17..12] Division factor for + __IOM unsigned int MCU_CLKOUT_DIV_FAC : 6; /*!< [17..12] Division factor for mcu_clkout (Mapped to GPIO) */ - __IOM uint32_t MCU_CLKOUT_ENABLE : 1; /*!< [18..18] Clock Enable for the clock on + __IOM unsigned int MCU_CLKOUT_ENABLE : 1; /*!< [18..18] Clock Enable for the clock on nwp_clkout (Mapped to GPIO) 1b0 - Clock is Gated 1b1 - Clock is Enabled */ - __IOM uint32_t Reserved2 : 13; /*!< [31..19] It is recommended to write + __IOM unsigned int Reserved2 : 13; /*!< [31..19] It is recommended to write these bits to 0. */ } CLK_CONFIG_REG3_b; }; union { - __IOM uint32_t CLK_CONFIG_REG4; /*!< (@ 0x00000024) Clock Config Register 4 */ + __IOM unsigned int CLK_CONFIG_REG4; /*!< (@ 0x00000024) Clock Config Register 4 */ struct { - __IOM uint32_t SOC_PLL_CLK_BYP_SEL : 2; /*!< [1..0] Selects one of the bypass clocks + __IOM unsigned int SOC_PLL_CLK_BYP_SEL : 2; /*!< [1..0] Selects one of the bypass clocks for SoC PLL Clock */ - __IOM uint32_t I2S_PLL_CLK_BYP_SEL : 2; /*!< [3..2] Selects one of the bypass clocks + __IOM unsigned int I2S_PLL_CLK_BYP_SEL : 2; /*!< [3..2] Selects one of the bypass clocks for I2S PLL Clock */ - __IOM uint32_t MODEM_PLL_CLK_BYP_SEL : 2; /*!< [5..4] Selects one of the bypass + __IOM unsigned int MODEM_PLL_CLK_BYP_SEL : 2; /*!< [5..4] Selects one of the bypass clocks for Modem PLL Clock */ - __IOM uint32_t INTF_PLL_CLK_BYP_SEL : 2; /*!< [7..6] Selects one of the bypass clocks + __IOM unsigned int INTF_PLL_CLK_BYP_SEL : 2; /*!< [7..6] Selects one of the bypass clocks for Intf PLL Clock */ - __IOM uint32_t SOC_INTF_PLL_BYPCLK_CLKCLNR_ON : 1; /*!< [8..8] Clock cleaner ON + __IOM unsigned int SOC_INTF_PLL_BYPCLK_CLKCLNR_ON : 1; /*!< [8..8] Clock cleaner ON Control for SoC PLL Bypass Clock */ - __IOM uint32_t SOC_INTF_PLL_BYPCLK_CLKCLNR_OFF : 1; /*!< [9..9] Clock cleaner OFF + __IOM unsigned int SOC_INTF_PLL_BYPCLK_CLKCLNR_OFF : 1; /*!< [9..9] Clock cleaner OFF Control for SoC PLL Bypass Clock */ - __IOM uint32_t Reserved1 : 2; /*!< [11..10] It is recommended to write + __IOM unsigned int Reserved1 : 2; /*!< [11..10] It is recommended to write these bits to 0. */ - __IOM uint32_t I2S_PLL_BYPCLK_CLKCLNR_ON : 1; /*!< [12..12] Clock cleaner ON Control + __IOM unsigned int I2S_PLL_BYPCLK_CLKCLNR_ON : 1; /*!< [12..12] Clock cleaner ON Control for I2S PLL Bypass Clock. */ - __IOM uint32_t I2S_PLL_BYPCLK_CLKCLNR_OFF : 1; /*!< [13..13] Clock cleaner + __IOM unsigned int I2S_PLL_BYPCLK_CLKCLNR_OFF : 1; /*!< [13..13] Clock cleaner OFF Control for I2S PLL Bypass Clock. */ - __IOM uint32_t MODEM_PLL_BYPCLK_CLKCLNR_ON : 1; /*!< [14..14] Clock cleaner ON + __IOM unsigned int MODEM_PLL_BYPCLK_CLKCLNR_ON : 1; /*!< [14..14] Clock cleaner ON Control for Modem PLL Bypass Clock. */ - __IOM uint32_t MODEM_PLL_BYPCLK_CLKCLNR_OFF : 1; /*!< [15..15] Clock cleaner OFF + __IOM unsigned int MODEM_PLL_BYPCLK_CLKCLNR_OFF : 1; /*!< [15..15] Clock cleaner OFF Control for Modem PLL Bypass Clock. */ - __IOM uint32_t BYPASS_SOC_PLL_CLK : 1; /*!< [16..16] Select to choose bypass clock or + __IOM unsigned int BYPASS_SOC_PLL_CLK : 1; /*!< [16..16] Select to choose bypass clock or PLL clock 1b0 - soc_pll_clk 1b1 - One of the bypass clocks based on soc_pll_clk_byp_sel. */ - __IOM uint32_t BYPASS_I2S_PLL_CLK : 1; /*!< [17..17] Select to choose bypass clock or + __IOM unsigned int BYPASS_I2S_PLL_CLK : 1; /*!< [17..17] Select to choose bypass clock or PLL clock 1b0 - i2s_pll_clk 1b1 - One of the bypass clocks based on soc_pll_clk_byp_sel. */ - __IOM uint32_t BYPASS_MODEM_PLL_CLK1 : 1; /*!< [18..18] Select to choose bypass clock + __IOM unsigned int BYPASS_MODEM_PLL_CLK1 : 1; /*!< [18..18] Select to choose bypass clock or PLL clock 1b0 - modem_pll_clk1 1b1 - One of the bypass clocks based on modem_pll_clk_byp_sel. */ - __IOM uint32_t BYPASS_MODEM_PLL_CLK2 : 1; /*!< [19..19] Select to choose bypass clock + __IOM unsigned int BYPASS_MODEM_PLL_CLK2 : 1; /*!< [19..19] Select to choose bypass clock or PLL clock 1b0 - modem_pll_clk2 1b1 - One of the bypass clocks based on modem_pll_clk_byp_sel. */ - __IOM uint32_t BYPASS_INTF_PLL_CLK : 1; /*!< [20..20] Select to choose bypass clock + __IOM unsigned int BYPASS_INTF_PLL_CLK : 1; /*!< [20..20] Select to choose bypass clock or PLL clock 1b0 - intf_pll_clk 1b1 - One of the bypass clocks based on soc_pll_clk_byp_sel. */ - __IOM uint32_t SLEEP_CLK_SEL : 2; /*!< [22..21] Select to choose sleep clk + __IOM unsigned int SLEEP_CLK_SEL : 2; /*!< [22..21] Select to choose sleep clk 00 - ulp_32khz_rc_clk 01 - ulp_32khz_xtal_clk 10 - Gated 11 - ulp_32khz_ro_clk. */ - __IOM uint32_t Reserved2 : 2; /*!< [24..23] It is recommended to write + __IOM unsigned int Reserved2 : 2; /*!< [24..23] It is recommended to write these bits to 0. */ - __IOM uint32_t ULPSS_CLK_DIV_FAC : 6; /*!< [30..25] Clock division factor for clock + __IOM unsigned int ULPSS_CLK_DIV_FAC : 6; /*!< [30..25] Clock division factor for clock to ULPSS. If ulpss_clk_enable is 1b0 clock is gated. Else output clock is a divided clock with the following frequency. 6h0 - Divider is bypassed > 6h0 - clk_out = clk_in/ 2* ulpss_clk_div_fac */ - __IOM uint32_t Reserved3 : 1; /*!< [31..31] It is recommended to write + __IOM unsigned int Reserved3 : 1; /*!< [31..31] It is recommended to write these bits to 0. */ } CLK_CONFIG_REG4_b; }; union { - __IOM uint32_t CLK_CONFIG_REG5; /*!< (@ 0x00000028) Clock Config Register 5 */ + __IOM unsigned int CLK_CONFIG_REG5; /*!< (@ 0x00000028) Clock Config Register 5 */ struct { - __IOM uint32_t M4_SOC_CLK_SEL : 4; /*!< [3..0] Selects one of the clock sources for + __IOM unsigned int M4_SOC_CLK_SEL : 4; /*!< [3..0] Selects one of the clock sources for M4 SoC clock. These clocks are selected for m4_soc_clk when 1)m4_soc_host_clk_sel is 1b0 or 2)when m4_soc_host_clk_sel is 1b1, xtal is @@ -10651,26 +10651,26 @@ typedef struct { /*!< (@ 0x46000000) M4CLK Structure */ 0000 - ULP Ref Clock (generated inside M4SS based on m4ss_ref_clk_sel from NPSS) 0001 - Reserved 0010 - */ - __IOM uint32_t M4_SOC_CLK_DIV_FAC : 6; /*!< [9..4] Clock divison factor for TA SoC + __IOM unsigned int M4_SOC_CLK_DIV_FAC : 6; /*!< [9..4] Clock divison factor for TA SoC Clock If ta_soc_clk_enable(from NPSS) is 1b0 clock is gated. Else output clock is a swallowed clock with the following frequency. 6h0,6h1 - Divider is bypassed >6h1 - clk_out = clk_in/ ta_soc_clk_div_fac */ - __IOM uint32_t I2S_CLK_SEL : 1; /*!< [10..10] Selects one of the following clocks for + __IOM unsigned int I2S_CLK_SEL : 1; /*!< [10..10] Selects one of the following clocks for config timer I2S interface 00/11 - I2S PLL Clock (program bypass_i2s_pll_clk if the bypass clock has to be selected) 01 - I2S PLL Clock_1 (program bypass_i2s_pll_clk_1 if the bypass clock has to be selected) 10 - m4_soc_clk_for_other_clocks */ - __IOM uint32_t I2S_CLK_DIV_FAC : 6; /*!< [16..11] Clock division factor for i2s_clk. + __IOM unsigned int I2S_CLK_DIV_FAC : 6; /*!< [16..11] Clock division factor for i2s_clk. Else output clock is a 50% divided clock with the following frequency. 6h0 - Divider is bypassed >6h0 - clk_out = clk_in/ 2*i2s_clk_div_fac */ - __IOM uint32_t CT_CLK_SEL : 3; /*!< [19..17] Selects one of the following clocks for + __IOM unsigned int CT_CLK_SEL : 3; /*!< [19..17] Selects one of the following clocks for config timer 000 - ulp ref Clock(generated inside M4SS based on m4ss_ref_clk_sel from NPSS) 001 - Intf PLL Clock(program bypass_intf_pll_clk if the @@ -10678,13 +10678,13 @@ typedef struct { /*!< (@ 0x46000000) M4CLK Structure */ Clock(program bypass_soc_pll_clk if the bypass clock has to be selected) 011 - m4_soc_clk_for_other_clocks 100,110 - Invalid */ - __IOM uint32_t CT_CLK_DIV_FAC : 6; /*!< [25..20] Clock division factor for sct_clk. + __IOM unsigned int CT_CLK_DIV_FAC : 6; /*!< [25..20] Clock division factor for sct_clk. If sct_clk_enable is 1b0 clock is gated. Else output clock is a 50% divided clock with the following frequency. 6h0 - Divider is bypassed >6h0 - clk_out = clk_in/ 2*sct_clk_div_fac */ - __IOM uint32_t M4_SOC_HOST_CLK_SEL : 1; /*!< [26..26] Selects the previous muxed + __IOM unsigned int M4_SOC_HOST_CLK_SEL : 1; /*!< [26..26] Selects the previous muxed output(xtal_clk) or host_clk as the clock source for M4 SoC clock based on the following combinations of {xtal_off(from @@ -10693,15 +10693,15 @@ typedef struct { /*!< (@ 0x46000000) M4CLK Structure */ 001 - After wait time based on mask_host_clk_wait_fix ; xtal_clk X11 - host_clk 101 - No Clock */ - __IOM uint32_t Reserved1 : 1; /*!< [27..27] It is recommended to write + __IOM unsigned int Reserved1 : 1; /*!< [27..27] It is recommended to write these bits to 0. */ - __IOM uint32_t ULPSS_ODD_DIV_SEL : 1; /*!< [28..28] Selects the type of divider for + __IOM unsigned int ULPSS_ODD_DIV_SEL : 1; /*!< [28..28] Selects the type of divider for m4_soc_clk_2ulpss 1b0 - Clock Divider(even) is selected 1b1 - Odd Divider is selected. */ - __IOM uint32_t Reserved2 : 2; /*!< [30..29] It is recommended to write + __IOM unsigned int Reserved2 : 2; /*!< [30..29] It is recommended to write these bits to 0. */ - __IOM uint32_t I2S_CLK_SEL_1 : 1; /*!< [31..31] Selects one of the following clocks + __IOM unsigned int I2S_CLK_SEL_1 : 1; /*!< [31..31] Selects one of the following clocks for config timer for I2S interface 00/11 - I2S PLL Clock (program bypass_i2s_pll_clk if the bypass clock has to be selected) 01 - I2S PLL @@ -10710,100 +10710,100 @@ typedef struct { /*!< (@ 0x46000000) M4CLK Structure */ m4_soc_clk_for_other_clocks */ } CLK_CONFIG_REG5_b; }; - __IM uint32_t RESERVED[6]; + __IM unsigned int RESERVED[6]; union { - __IOM uint32_t DYN_CLK_GATE_DISABLE_REG; /*!< (@ 0x00000044) Dynamic Clock + __IOM unsigned int DYN_CLK_GATE_DISABLE_REG; /*!< (@ 0x00000044) Dynamic Clock Gate Disable Register */ struct { - __IOM uint32_t SDIO_SYS_HCLK_DYN_CTRL_DISABLE_b : 1; /*!< [0..0] Dynamic clock gate + __IOM unsigned int SDIO_SYS_HCLK_DYN_CTRL_DISABLE_b : 1; /*!< [0..0] Dynamic clock gate disable control sdio sys clk1'b0 => Dynamic control of the clock is disbaled 1'b1 => Dynamic control of the clock is enabled */ - __IOM uint32_t BUS_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [1..1] Dynamic clock gate disable + __IOM unsigned int BUS_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [1..1] Dynamic clock gate disable control bus clk1'b0 => Dynamic control of the clock is disbaled 1'b1 => Dynamic control of the clock is enabled */ - __IOM uint32_t Reserved1 : 2; /*!< [3..2] It is recommended to write these + __IOM unsigned int Reserved1 : 2; /*!< [3..2] It is recommended to write these bits to 0. */ - __IOM uint32_t GPDMA_HCLK_DYN_CTRL_DISABLE_b : 1; /*!< [4..4] Dynamic clock gate + __IOM unsigned int GPDMA_HCLK_DYN_CTRL_DISABLE_b : 1; /*!< [4..4] Dynamic clock gate disable control gpdma clk1'b0 => Dynamic control of the clock is disbaled 1'b1 => Dynamic control of the clock is enabled */ - __IOM uint32_t EGPIO_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [5..5] Dynamic clock gate + __IOM unsigned int EGPIO_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [5..5] Dynamic clock gate disable control egpio clk1'b0 => Dynamic control of the clock is disbaled 1'b1 => Dynamic control of the clock is enabled */ - __IOM uint32_t SGPIO_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [6..6] Dynamic clock gate + __IOM unsigned int SGPIO_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [6..6] Dynamic clock gate disable control sgpio clk1'b0 => Dynamic control of the clock is disbaled 1'b1 => Dynamic control of the clock is enabled */ - __IOM uint32_t TOT_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [7..7] Dynamic clock gate disable + __IOM unsigned int TOT_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [7..7] Dynamic clock gate disable control tot clk1'b0 => Dynamic control of the clock is disbaled 1'b1 => Dynamic control of the clock is enabled */ - __IOM uint32_t Reserved2 : 1; /*!< [8..8] It is recommended to write these + __IOM unsigned int Reserved2 : 1; /*!< [8..8] It is recommended to write these bits to 0. */ - __IOM uint32_t USART1_SCLK_DYN_CTRL_DISABLE_b : 1; /*!< [9..9] Dynamic clock gate + __IOM unsigned int USART1_SCLK_DYN_CTRL_DISABLE_b : 1; /*!< [9..9] Dynamic clock gate disable control usart1 sclk1'b0 => Dynamic control of the clock is disbaled 1'b1 => Dynamic control of the clock is enabled. */ - __IOM uint32_t USART1_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [10..10] Dynamic clock gate + __IOM unsigned int USART1_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [10..10] Dynamic clock gate disable control usart1 pclk1'b0 => Dynamic control of the clock is disbaled 1'b1 => Dynamic control of the clock is enabled. */ - __IOM uint32_t USART2_SCLK_DYN_CTRL_DISABLE_b : 1; /*!< [11..11] Dynamic clock gate + __IOM unsigned int USART2_SCLK_DYN_CTRL_DISABLE_b : 1; /*!< [11..11] Dynamic clock gate disable control usart2 sclk1'b0 => Dynamic control of the clock is disbaled 1'b1 => Dynamic control of the clock is enabled. */ - __IOM uint32_t USART2_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [12..12] Dynamic clock gate + __IOM unsigned int USART2_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [12..12] Dynamic clock gate disable control usart2 pclk1'b0 => Dynamic control of the clock is disbaled 1'b1 => Dynamic control of the clock is enabled. */ - __IOM uint32_t Reserved3 : 2; /*!< [14..13] It is recommended to write + __IOM unsigned int Reserved3 : 2; /*!< [14..13] It is recommended to write these bits to 0. */ - __IOM uint32_t SSI_SLV_SCLK_DYN_CTRL_DISABLE_b : 1; /*!< [15..15] Dynamic clock gate + __IOM unsigned int SSI_SLV_SCLK_DYN_CTRL_DISABLE_b : 1; /*!< [15..15] Dynamic clock gate disable control ssi slave sclk1'b0 => Dynamic control of the clock is disbaled 1'b1 => Dynamic control of the clock is enabled */ - __IOM uint32_t SSI_SLV_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [16..16] Dynamic clock gate + __IOM unsigned int SSI_SLV_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [16..16] Dynamic clock gate disable control ssi slave pclk1'b0 => Dynamic control of the clock is disbaled 1'b1 => Dynamic control of the clock is enabled */ - __IOM uint32_t Reserved4 : 2; /*!< [18..17] It is recommended to write + __IOM unsigned int Reserved4 : 2; /*!< [18..17] It is recommended to write these bits to 0. */ - __IOM uint32_t SEMAPHORE_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [19..19] Dynamic clock gate + __IOM unsigned int SEMAPHORE_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [19..19] Dynamic clock gate disable control semaphore clk1'b0 => Dynamic control of the @@ -10811,45 +10811,45 @@ typedef struct { /*!< (@ 0x46000000) M4CLK Structure */ Dynamic control of the clock is enabled. */ - __IOM uint32_t ARM_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [20..20] Dynamic clock gate + __IOM unsigned int ARM_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [20..20] Dynamic clock gate disable control arm clk1'b0 => Dynamic control of the clock is disbaled 1'b1 => Dynamic control of the clock is enabled. */ - __IOM uint32_t SSI_MST_SCLK_DYN_CTRL_DISABLE_b : 1; /*!< [21..21] Dynamic clock gate + __IOM unsigned int SSI_MST_SCLK_DYN_CTRL_DISABLE_b : 1; /*!< [21..21] Dynamic clock gate disable control ssi mst sclk1'b0 => Dynamic control of the clock is disbaled 1'b1 => Dynamic control of the clock is enabled. */ - __IOM uint32_t Reserved5 : 2; /*!< [23..22] It is recommended to write + __IOM unsigned int Reserved5 : 2; /*!< [23..22] It is recommended to write these bits to 0. */ - __IOM uint32_t MEM_CLK_ULP_DYN_CTRL_DISABLE_b : 1; /*!< [24..24] Dynamic clock gate + __IOM unsigned int MEM_CLK_ULP_DYN_CTRL_DISABLE_b : 1; /*!< [24..24] Dynamic clock gate disable control mem clk1'b0 => Dynamic control of the clock is disbaled 1'b1 => Dynamic control of the clock is enabled. */ - __IOM uint32_t Reserved6 : 3; /*!< [27..25] It is recommended to write + __IOM unsigned int Reserved6 : 3; /*!< [27..25] It is recommended to write these bits to 0. */ - __IOM uint32_t SSI_MST_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [28..28] Dynamic clock gate + __IOM unsigned int SSI_MST_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [28..28] Dynamic clock gate disable control ssi mst pclk 1'b0 => Dynamic control of the clock is disbaled 1'b1 => Dynamic control of the clock is enabled */ - __IOM uint32_t ICACHE_DYN_GATING_DISABLE_b : 1; /*!< [29..29] Dynamic clock gate + __IOM unsigned int ICACHE_DYN_GATING_DISABLE_b : 1; /*!< [29..29] Dynamic clock gate disable control icache clk1'b0 => Dynamic control of the clock is disbaled 1'b1 => Dynamic control of the clock is enabled */ - __IOM uint32_t Reserved7 : 1; /*!< [30..30] It is recommended to write + __IOM unsigned int Reserved7 : 1; /*!< [30..30] It is recommended to write these bits to 0. */ - __IOM uint32_t MISC_CONFIG_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [31..31] Dynamic clock + __IOM unsigned int MISC_CONFIG_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [31..31] Dynamic clock gate disable control miscn config pclk 1'b0 => Dynamic control of the @@ -10858,229 +10858,229 @@ typedef struct { /*!< (@ 0x46000000) M4CLK Structure */ clock is enabled. */ } DYN_CLK_GATE_DISABLE_REG_b; }; - __IM uint32_t RESERVED1[2]; + __IM unsigned int RESERVED1[2]; union { - __IOM uint32_t PLL_ENABLE_SET_REG; /*!< (@ 0x00000050) PLL Enable Set Register */ + __IOM unsigned int PLL_ENABLE_SET_REG; /*!< (@ 0x00000050) PLL Enable Set Register */ struct { - __IOM uint32_t SOCPLL_SPI_SW_RESET : 1; /*!< [0..0] SPI soft reset for SoC PLL1'b1 => + __IOM unsigned int SOCPLL_SPI_SW_RESET : 1; /*!< [0..0] SPI soft reset for SoC PLL1'b1 => soft reset is enabled1'b0 => Invalid */ - __IOM uint32_t Reserved1 : 31; /*!< [31..1] It is recommended to write + __IOM unsigned int Reserved1 : 31; /*!< [31..1] It is recommended to write these bits to 0. */ } PLL_ENABLE_SET_REG_b; }; union { - __IOM uint32_t PLL_ENABLE_CLEAR_REG; /*!< (@ 0x00000054) PLL Enable Clear Register */ + __IOM unsigned int PLL_ENABLE_CLEAR_REG; /*!< (@ 0x00000054) PLL Enable Clear Register */ struct { - __IOM uint32_t SOCPLL_SPI_SW_RESET : 1; /*!< [0..0] SPI soft reset for SoC PLL1'b1 => + __IOM unsigned int SOCPLL_SPI_SW_RESET : 1; /*!< [0..0] SPI soft reset for SoC PLL1'b1 => soft reset is disabled1'b0 => Invalid */ - __IOM uint32_t Reserved1 : 31; /*!< [31..1] It is recommended to write + __IOM unsigned int Reserved1 : 31; /*!< [31..1] It is recommended to write these bits to 0. */ } PLL_ENABLE_CLEAR_REG_b; }; union { - __IM uint32_t PLL_STAT_REG; /*!< (@ 0x00000058) PLL Status Register */ + __IM unsigned int PLL_STAT_REG; /*!< (@ 0x00000058) PLL Status Register */ struct { - __IM uint32_t LCDPLL_LOCK : 1; /*!< [0..0] Lock Signal from LCD PLL */ - __IM uint32_t DDRPLL_LOCK : 1; /*!< [1..1] Lock Signal from DDR PLL */ - __IM uint32_t APPLL_LOCK : 1; /*!< [2..2] Lock Signal from AP PLL */ - __IM uint32_t INTFPLL_LOCK : 1; /*!< [3..3] Lock Signal from INTF PLL */ - __IM uint32_t I2SPLL_LOCK : 1; /*!< [4..4] Lock Signal from I2S PLL */ - __IM uint32_t SOCPLL_LOCK : 1; /*!< [5..5] Lock Signal from SoC PLL */ - __IM uint32_t MODEMPLL_LOCK : 1; /*!< [6..6] Lock Signal from Modem PLL */ - __IM uint32_t PLL_LOCK_DATA_TRIG : 1; /*!< [7..7] This is set to 1'b1 when the PLL + __IM unsigned int LCDPLL_LOCK : 1; /*!< [0..0] Lock Signal from LCD PLL */ + __IM unsigned int DDRPLL_LOCK : 1; /*!< [1..1] Lock Signal from DDR PLL */ + __IM unsigned int APPLL_LOCK : 1; /*!< [2..2] Lock Signal from AP PLL */ + __IM unsigned int INTFPLL_LOCK : 1; /*!< [3..3] Lock Signal from INTF PLL */ + __IM unsigned int I2SPLL_LOCK : 1; /*!< [4..4] Lock Signal from I2S PLL */ + __IM unsigned int SOCPLL_LOCK : 1; /*!< [5..5] Lock Signal from SoC PLL */ + __IM unsigned int MODEMPLL_LOCK : 1; /*!< [6..6] Lock Signal from Modem PLL */ + __IM unsigned int PLL_LOCK_DATA_TRIG : 1; /*!< [7..7] This is set to 1'b1 when the PLL Locks are equal to pll_lock_int_data_r g */ - __IM uint32_t M4_SOC_CLK_SWITCHED : 1; /*!< [8..8] Indication from M4 SoC + __IM unsigned int M4_SOC_CLK_SWITCHED : 1; /*!< [8..8] Indication from M4 SoC Clock Dynamic mux that the switching happened */ - __IM uint32_t QSPI_CLK_SWITCHED : 1; /*!< [9..9] Indication from QSPI Clock Dynamic + __IM unsigned int QSPI_CLK_SWITCHED : 1; /*!< [9..9] Indication from QSPI Clock Dynamic mux that the switching happened */ - __IM uint32_t USART1_SCLK_SWITCHED : 1; /*!< [10..10] Indication from + __IM unsigned int USART1_SCLK_SWITCHED : 1; /*!< [10..10] Indication from USART1 Clock Dynamic mux that the switching happened */ - __IM uint32_t USART2_SCLK_SWITCHED : 1; /*!< [11..11] Indication from + __IM unsigned int USART2_SCLK_SWITCHED : 1; /*!< [11..11] Indication from USART1 Clock Dynamic mux that the switching happened */ - __IM uint32_t GEN_SPI_MST1_SCLK_SWITCHED : 1; /*!< [12..12] Indication from USART2 + __IM unsigned int GEN_SPI_MST1_SCLK_SWITCHED : 1; /*!< [12..12] Indication from USART2 Clock Dynamic mux that the switching happened */ - __IM uint32_t SSI_MST_SCLK_SWITCHED : 1; /*!< [13..13] Indication from SSi + __IM unsigned int SSI_MST_SCLK_SWITCHED : 1; /*!< [13..13] Indication from SSi Master SClock Dynamic mux that the switching happened */ - __IM uint32_t Reserved1 : 1; /*!< [14..14] It is recommended to write + __IM unsigned int Reserved1 : 1; /*!< [14..14] It is recommended to write these bits to 0. */ - __IM uint32_t CT_CLK_SWITCHED : 1; /*!< [15..15] Indication from SCT Clock Dynamic + __IM unsigned int CT_CLK_SWITCHED : 1; /*!< [15..15] Indication from SCT Clock Dynamic mux that the switching happened */ - __IM uint32_t M4_TA_SOC_CLK_SWITCHED_SDIO : 1; /*!< [16..16] Indication + __IM unsigned int M4_TA_SOC_CLK_SWITCHED_SDIO : 1; /*!< [16..16] Indication from M4-TA Soc SDIO Clock Dynamic mux that the switching happened(TBD) */ - __IM uint32_t I2S_CLK_SWITCHED : 1; /*!< [17..17] Indication from I2S Clock Dynamic + __IM unsigned int I2S_CLK_SWITCHED : 1; /*!< [17..17] Indication from I2S Clock Dynamic mux that the switching happened */ - __IM uint32_t PLL_INTF_CLK_SWITCHED : 1; /*!< [18..18] Indication from Pll + __IM unsigned int PLL_INTF_CLK_SWITCHED : 1; /*!< [18..18] Indication from Pll Intf Clock Dynamic mux that the switching happened */ - __IM uint32_t Reserved2 : 2; /*!< [20..19] It is recommended to write + __IM unsigned int Reserved2 : 2; /*!< [20..19] It is recommended to write these bits to 0. */ - __IM uint32_t SLEEP_CLK_SWITCHED : 1; /*!< [21..21] Indication from Sleep + __IM unsigned int SLEEP_CLK_SWITCHED : 1; /*!< [21..21] Indication from Sleep clcok Dynamic mux that the switching happened */ - __IM uint32_t MCU_CLKOUT_SWITCHED : 1; /*!< [22..22] Indication from + __IM unsigned int MCU_CLKOUT_SWITCHED : 1; /*!< [22..22] Indication from mcu_clkout Dynamic mux that the switching happened */ - __IM uint32_t QSPI_2_CLK_SWITCHED : 1; /*!< [23..23] Indication from QSPI + __IM unsigned int QSPI_2_CLK_SWITCHED : 1; /*!< [23..23] Indication from QSPI Clock Dynamic mux that the switching happened */ - __IM uint32_t TASS_M4SS_64K_CLK_SWITCHED : 1; /*!< [24..24] Indication when TA + __IM unsigned int TASS_M4SS_64K_CLK_SWITCHED : 1; /*!< [24..24] Indication when TA accessing 2nd memory chunk of M4, clock to Dynamic mux switching happened */ - __IM uint32_t CC_CLOCK_MUX_SWITCHED : 1; /*!< [25..25] Indication from cc + __IM unsigned int CC_CLOCK_MUX_SWITCHED : 1; /*!< [25..25] Indication from cc clock Dynamic mux that the switching happened */ - __IM uint32_t TASS_M4SS_192K_CLK_SWITCHED : 1; /*!< [26..26] Indication when TA + __IM unsigned int TASS_M4SS_192K_CLK_SWITCHED : 1; /*!< [26..26] Indication when TA accessing 0th memory chunk of M4, clock to Dynamic mux switching happened */ - __IM uint32_t USART1_CLK_SWITCHED : 1; /*!< [27..27] Indication from + __IM unsigned int USART1_CLK_SWITCHED : 1; /*!< [27..27] Indication from usart1 sclk or pclk Dynamic mux that the switching happened */ - __IM uint32_t USART2_CLK_SWITCHED : 1; /*!< [28..28] Indication from + __IM unsigned int USART2_CLK_SWITCHED : 1; /*!< [28..28] Indication from usart2 sclk or pclk Dynamic mux that the switching happened */ - __IM uint32_t TASS_M4SS_64K0_CLK_SWITCHED : 1; /*!< [29..29] Indication when TA + __IM unsigned int TASS_M4SS_64K0_CLK_SWITCHED : 1; /*!< [29..29] Indication when TA accessing 1st memory chunk of M4, clock to Dynamic mux switching happened */ - __IM uint32_t CLK_FREE_OR_SLP_SWITCHED : 1; /*!< [30..30] Indication from + __IM unsigned int CLK_FREE_OR_SLP_SWITCHED : 1; /*!< [30..30] Indication from clk_free_or_slp Dynamic mux that the switching happened */ - __IM uint32_t ULP_REF_CLK_SWITCHED : 1; /*!< [31..31] Indication from + __IM unsigned int ULP_REF_CLK_SWITCHED : 1; /*!< [31..31] Indication from ulp_ref_clk Dynamic mux that the switching happened */ } PLL_STAT_REG_b; }; union { - __IOM uint32_t PLL_LOCK_INT_MASK_REG; /*!< (@ 0x0000005C) PLL Lock Interrupt + __IOM unsigned int PLL_LOCK_INT_MASK_REG; /*!< (@ 0x0000005C) PLL Lock Interrupt Mask Register */ struct { - __IOM uint32_t LCD_PLL_LOCK_MASK_BIT_OF_RISING_EDGE : 1; /*!< [0..0] 1'b1 => + __IOM unsigned int LCD_PLL_LOCK_MASK_BIT_OF_RISING_EDGE : 1; /*!< [0..0] 1'b1 => Masked;1'b0 => Not Masked */ - __IOM uint32_t DDR_PLL_LOCK_MASK_BIT_OF_RISING_EDGE : 1; /*!< [1..1] 1'b1 => + __IOM unsigned int DDR_PLL_LOCK_MASK_BIT_OF_RISING_EDGE : 1; /*!< [1..1] 1'b1 => Masked;1'b0 => Not Masked */ - __IOM uint32_t AP_PLL_LOCK_MASK_BIT_OF_RISING_EDGE : 1; /*!< [2..2] 1'b1 => + __IOM unsigned int AP_PLL_LOCK_MASK_BIT_OF_RISING_EDGE : 1; /*!< [2..2] 1'b1 => Masked;1'b0 => Not Masked */ - __IOM uint32_t INTF_PLL_LOCK_MASK_BIT_OF_RISING_EDGE : 1; /*!< [3..3] 1'b1 => + __IOM unsigned int INTF_PLL_LOCK_MASK_BIT_OF_RISING_EDGE : 1; /*!< [3..3] 1'b1 => Masked;1'b0 => Not Masked */ - __IOM uint32_t I2S_PLL_LOCK_MASK_BIT_OF_RISING_EDGE : 1; /*!< [4..4] 1'b1 => + __IOM unsigned int I2S_PLL_LOCK_MASK_BIT_OF_RISING_EDGE : 1; /*!< [4..4] 1'b1 => Masked;1'b0 => Not Masked */ - __IOM uint32_t SOC_PLL_LOCK_MASK_BIT_OF_RISING_EDGE : 1; /*!< [5..5] 1'b1 => + __IOM unsigned int SOC_PLL_LOCK_MASK_BIT_OF_RISING_EDGE : 1; /*!< [5..5] 1'b1 => Masked;1'b0 => Not Masked */ - __IOM uint32_t MODEM_PLL_LOCK_MASK_BIT_OF_RISING_EDGE : 1; /*!< [6..6] 1'b1 => + __IOM unsigned int MODEM_PLL_LOCK_MASK_BIT_OF_RISING_EDGE : 1; /*!< [6..6] 1'b1 => Masked;1'b0 => Not Masked */ - __IOM uint32_t PLL_LOCK_DATA_TRIGGER_MASK_BIT_OF_RISING_EDGE : 1; /*!< [7..7] 1'b1 => + __IOM unsigned int PLL_LOCK_DATA_TRIGGER_MASK_BIT_OF_RISING_EDGE : 1; /*!< [7..7] 1'b1 => Masked;1'b0 => Not Masked */ - __IOM uint32_t LCD_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE : 1; /*!< [8..8] 1'b1 => + __IOM unsigned int LCD_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE : 1; /*!< [8..8] 1'b1 => Masked;1'b0 => Not Masked */ - __IOM uint32_t DDR_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE : 1; /*!< [9..9] 1'b1 => + __IOM unsigned int DDR_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE : 1; /*!< [9..9] 1'b1 => Masked;1'b0 => Not Masked */ - __IOM uint32_t AP_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE : 1; /*!< [10..10] 1'b1 => + __IOM unsigned int AP_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE : 1; /*!< [10..10] 1'b1 => Masked;1'b0 => Not Masked */ - __IOM uint32_t INTF_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE : 1; /*!< [11..11] 1'b1 => + __IOM unsigned int INTF_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE : 1; /*!< [11..11] 1'b1 => Masked;1'b0 => Not Masked */ - __IOM uint32_t I2S_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE : 1; /*!< [12..12] 1'b1 => + __IOM unsigned int I2S_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE : 1; /*!< [12..12] 1'b1 => Masked;1'b0 => Not Masked */ - __IOM uint32_t SOC_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE : 1; /*!< [13..13] 1'b1 => + __IOM unsigned int SOC_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE : 1; /*!< [13..13] 1'b1 => Masked;1'b0 => Not Masked */ - __IOM uint32_t MODEM_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE : 1; /*!< [14..14] 1'b1 => + __IOM unsigned int MODEM_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE : 1; /*!< [14..14] 1'b1 => Masked;1'b0 => Not Masked */ - __IOM uint32_t PLL_LOCK_DATA_TRIGGER_MASK_BIT_OF_FALLING_EDGE : 1; /*!< [15..15] 1'b1 + __IOM unsigned int PLL_LOCK_DATA_TRIGGER_MASK_BIT_OF_FALLING_EDGE : 1; /*!< [15..15] 1'b1 => Masked;1'b0 => Not Masked */ - __IOM uint32_t Reserved1 : 16; /*!< [31..16] It is recommended to write + __IOM unsigned int Reserved1 : 16; /*!< [31..16] It is recommended to write these bits to 0. */ } PLL_LOCK_INT_MASK_REG_b; }; union { - __IOM uint32_t PLL_LOCK_INT_CLR_REG; /*!< (@ 0x00000060) PLL Lock Interrupt + __IOM unsigned int PLL_LOCK_INT_CLR_REG; /*!< (@ 0x00000060) PLL Lock Interrupt Clear Register */ struct { - __IOM uint32_t LCD_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE : 1; /*!< [0..0] 1'b0 => Not + __IOM unsigned int LCD_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE : 1; /*!< [0..0] 1'b0 => Not Cleared 1'b1 => Cleared */ - __IOM uint32_t DDR_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE : 1; /*!< [1..1] 1'b0 => Not + __IOM unsigned int DDR_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE : 1; /*!< [1..1] 1'b0 => Not Cleared 1'b1 => Cleared */ - __IOM uint32_t AP_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE : 1; /*!< [2..2] 1'b0 => Not + __IOM unsigned int AP_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE : 1; /*!< [2..2] 1'b0 => Not Cleared 1'b1 => Cleared */ - __IOM uint32_t INTF_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE : 1; /*!< [3..3] 1'b0 => Not + __IOM unsigned int INTF_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE : 1; /*!< [3..3] 1'b0 => Not Cleared 1'b1 => Cleared */ - __IOM uint32_t I2S_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE : 1; /*!< [4..4] 1'b0 => Not + __IOM unsigned int I2S_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE : 1; /*!< [4..4] 1'b0 => Not Cleared 1'b1 => Cleared */ - __IOM uint32_t SOC_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE : 1; /*!< [5..5] 1'b0 => Not + __IOM unsigned int SOC_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE : 1; /*!< [5..5] 1'b0 => Not Cleared 1'b1 => Cleared */ - __IOM uint32_t MODEM_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE : 1; /*!< [6..6] 1'b0 => Not + __IOM unsigned int MODEM_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE : 1; /*!< [6..6] 1'b0 => Not Cleared 1'b1 => Cleared */ - __IOM uint32_t PLL_LOCK_DATA_TRIGGER_CLEAR_BIT_OF_RISING_EDGE : 1; /*!< [7..7] 1'b0 + __IOM unsigned int PLL_LOCK_DATA_TRIGGER_CLEAR_BIT_OF_RISING_EDGE : 1; /*!< [7..7] 1'b0 => Not Cleared 1'b1 => Cleared */ - __IOM uint32_t LCD_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE : 1; /*!< [8..8] 1'b0 => Not + __IOM unsigned int LCD_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE : 1; /*!< [8..8] 1'b0 => Not Cleared 1'b1 => Cleared */ - __IOM uint32_t DDR_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE : 1; /*!< [9..9] 1'b0 => Not + __IOM unsigned int DDR_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE : 1; /*!< [9..9] 1'b0 => Not Cleared 1'b1 => Cleared */ - __IOM uint32_t AP_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE : 1; /*!< [10..10] 1'b0 => Not + __IOM unsigned int AP_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE : 1; /*!< [10..10] 1'b0 => Not Cleared 1'b1 => Cleared */ - __IOM uint32_t INTF_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE : 1; /*!< [11..11] 1'b0 => Not + __IOM unsigned int INTF_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE : 1; /*!< [11..11] 1'b0 => Not Cleared 1'b1 => Cleared */ - __IOM uint32_t I2S_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE : 1; /*!< [12..12] 1'b0 => Not + __IOM unsigned int I2S_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE : 1; /*!< [12..12] 1'b0 => Not Cleared 1'b1 => Cleared */ - __IOM uint32_t SOC_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE : 1; /*!< [13..13] 1'b0 => Not + __IOM unsigned int SOC_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE : 1; /*!< [13..13] 1'b0 => Not Cleared 1'b1 => Cleared */ - __IOM uint32_t MODEM_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE : 1; /*!< [14..14] 1'b0 => + __IOM unsigned int MODEM_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE : 1; /*!< [14..14] 1'b0 => Not Cleared 1'b1 => Cleared */ - __IOM uint32_t PLL_LOCK_DATA_TRIGGER_CLEAR_BIT_OF_FALLING_EDGE : 1; /*!< + __IOM unsigned int PLL_LOCK_DATA_TRIGGER_CLEAR_BIT_OF_FALLING_EDGE : 1; /*!< [15..15] 1'b0 => @@ -11090,58 +11090,58 @@ typedef struct { /*!< (@ 0x46000000) M4CLK Structure */ => Cleared */ - __IOM uint32_t Reserved1 : 16; /*!< [31..16] It is recommended to write + __IOM unsigned int Reserved1 : 16; /*!< [31..16] It is recommended to write these bits to 0. */ } PLL_LOCK_INT_CLR_REG_b; }; union { - __IOM uint32_t PLL_LOCK_INT_DATA_REG; /*!< (@ 0x00000064) PLL Lock Interrupt + __IOM unsigned int PLL_LOCK_INT_DATA_REG; /*!< (@ 0x00000064) PLL Lock Interrupt DATA Register */ struct { - __IOM uint32_t LCD_PLL_LOCK : 1; /*!< [0..0] 1'b1 => LCD PLL Lock has to be used as + __IOM unsigned int LCD_PLL_LOCK : 1; /*!< [0..0] 1'b1 => LCD PLL Lock has to be used as trigger1'b0 => LCD PLL Lock not to be used as trigger */ - __IOM uint32_t DDR_PLL_LOCK : 1; /*!< [1..1] 1'b1 => DDR PLL Lock has to be used as + __IOM unsigned int DDR_PLL_LOCK : 1; /*!< [1..1] 1'b1 => DDR PLL Lock has to be used as trigger1'b0 => DDR PLL Lock not to be used as trigger */ - __IOM uint32_t AP_PLL_LOCK : 1; /*!< [2..2] 1'b1 => AP PLL Lock has to be used as + __IOM unsigned int AP_PLL_LOCK : 1; /*!< [2..2] 1'b1 => AP PLL Lock has to be used as trigger1'b0 => Ap PLL Lock not to be used as trigger */ - __IOM uint32_t INTF_PLL_LOCK : 1; /*!< [3..3] 1'b1 => INTF PLL Lock has to + __IOM unsigned int INTF_PLL_LOCK : 1; /*!< [3..3] 1'b1 => INTF PLL Lock has to be used as trigger1'b0 => INTF PLL Lock not to be used as trigger */ - __IOM uint32_t I2S_PLL_LOCK : 1; /*!< [4..4] 1'b1 => I2S PLL Lock has to be used as + __IOM unsigned int I2S_PLL_LOCK : 1; /*!< [4..4] 1'b1 => I2S PLL Lock has to be used as trigger1'b0 => I2S PLL Lock not to be used as trigger */ - __IOM uint32_t SOC_PLL_LOCK : 1; /*!< [5..5] 1'b1 => SoC PLL Lock has to be used as + __IOM unsigned int SOC_PLL_LOCK : 1; /*!< [5..5] 1'b1 => SoC PLL Lock has to be used as trigger1'b0 => SoC PLL Lock not to be used as trigger */ - __IOM uint32_t MODEM_PLL_LOCK : 1; /*!< [6..6] 1'b1 => Modem PLL Lock has + __IOM unsigned int MODEM_PLL_LOCK : 1; /*!< [6..6] 1'b1 => Modem PLL Lock has to be used as trigger1'b0 => Modem PLL Lock not to be used as trigger */ - __IOM uint32_t Reserved1 : 25; /*!< [31..7] It is recommended to write + __IOM unsigned int Reserved1 : 25; /*!< [31..7] It is recommended to write these bits to 0. */ } PLL_LOCK_INT_DATA_REG_b; }; union { - __IOM uint32_t SLEEP_CALIB_REG; /*!< (@ 0x00000068) Sleep Calib Register */ + __IOM unsigned int SLEEP_CALIB_REG; /*!< (@ 0x00000068) Sleep Calib Register */ struct { - __IOM uint32_t SLP_CALIB_START_b : 1; /*!< [0..0] This bit is used to start the + __IOM unsigned int SLP_CALIB_START_b : 1; /*!< [0..0] This bit is used to start the calibration. 1b1 - Start calibration. slp_calib_duration should be loaded before this bit is set. This bit is self-clearing. When read, if high indicates the completion of calibration process. */ - __IOM uint32_t SLP_CALIB_CYCLES : 2; /*!< [2..1] These bits are used to program the + __IOM unsigned int SLP_CALIB_CYCLES : 2; /*!< [2..1] These bits are used to program the number of clock cycles over which clock calibration is to be done. */ - __IOM uint32_t SLP_CALIB_DURATION_b : 16; /*!< [18..3] Duration of the sleep clock in + __IOM unsigned int SLP_CALIB_DURATION_b : 16; /*!< [18..3] Duration of the sleep clock in terms of processor clocks. This has to be divided with number of calibration cycles to get number of clock @@ -11150,84 +11150,84 @@ typedef struct { /*!< (@ 0x46000000) M4CLK Structure */ used as trigger1b0 - Ap PLL Lock not to be used as trigger */ - __IOM uint32_t SLP_CALIB_DONE_b : 1; /*!< [19..19] Indicates the end of + __IOM unsigned int SLP_CALIB_DONE_b : 1; /*!< [19..19] Indicates the end of calibration */ - __IOM uint32_t Reserved1 : 12; /*!< [31..20] It is recommended to write + __IOM unsigned int Reserved1 : 12; /*!< [31..20] It is recommended to write these bits to 0. */ } SLEEP_CALIB_REG_b; }; union { - __IOM uint32_t CLK_CALIB_CTRL_REG1; /*!< (@ 0x0000006C) Clock Calib Control + __IOM unsigned int CLK_CALIB_CTRL_REG1; /*!< (@ 0x0000006C) Clock Calib Control Register1 */ struct { - __IOM uint32_t CC_SOFT_RST_b : 1; /*!< [0..0] Soft Reset for clock + __IOM unsigned int CC_SOFT_RST_b : 1; /*!< [0..0] Soft Reset for clock calibrator 1b1 - reset enabled 1b0 - reset disabled. */ - __IOM uint32_t CC_START_b : 1; /*!< [1..1] start clk calibration 1b1 - start */ - __IOM uint32_t CC_CHANGE_TEST_CLK_b : 1; /*!< [2..2] change test clk. Set + __IOM unsigned int CC_START_b : 1; /*!< [1..1] start clk calibration 1b1 - start */ + __IOM unsigned int CC_CHANGE_TEST_CLK_b : 1; /*!< [2..2] change test clk. Set this bit to 1'b1 only when test_clk is being changed, else this should be 1'b0. */ - __IOM uint32_t CC_CLKIN_SEL_b : 4; /*!< [6..3] select the clock to be calibrated 4d0 + __IOM unsigned int CC_CLKIN_SEL_b : 4; /*!< [6..3] select the clock to be calibrated 4d0 - ulp_ref_clk 4d1 - mems_ref_clk 4d2 - ulp_20mhz_ringosc_clk 4d3 - modem_pll_clk1 4d4 - modem_pll_clk2 4d5 - intf_pll_clk 4d6 - soc_pll_clk 4d7 - i2s_pll_clk 4d8 - sleep_clk 4d9 - bus_clkby2_ap */ - __IOM uint32_t Reserved1 : 25; /*!< [31..7] It is recommended to write + __IOM unsigned int Reserved1 : 25; /*!< [31..7] It is recommended to write these bits to 0. */ } CLK_CALIB_CTRL_REG1_b; }; union { - __IOM uint32_t CLK_CALIB_CTRL_REG2; /*!< (@ 0x00000070) Clock Calib Control + __IOM unsigned int CLK_CALIB_CTRL_REG2; /*!< (@ 0x00000070) Clock Calib Control Register2 */ struct { - __IOM uint32_t CC_NUM_REF_CLKS : 32; /*!< [31..0] number of ref_clk cycles to be + __IOM unsigned int CC_NUM_REF_CLKS : 32; /*!< [31..0] number of ref_clk cycles to be considered for calibrating. */ } CLK_CALIB_CTRL_REG2_b; }; union { - __IOM uint32_t CLK_CALIB_STS_REG1; /*!< (@ 0x00000074) Clock Calib Status + __IOM unsigned int CLK_CALIB_STS_REG1; /*!< (@ 0x00000074) Clock Calib Status Register1 */ struct { - __IOM uint32_t CC_DONE_b : 1; /*!< [0..0] indicates clock calibratioon + __IOM unsigned int CC_DONE_b : 1; /*!< [0..0] indicates clock calibratioon done1'b1 => done1'b0 => none */ - __IOM uint32_t CC_ERROR_b : 1; /*!< [1..1] indicates clock calibration + __IOM unsigned int CC_ERROR_b : 1; /*!< [1..1] indicates clock calibration error1'b1 => error1'b0 => none */ - __IOM uint32_t Reserved1 : 30; /*!< [31..2] It is recommended to write + __IOM unsigned int Reserved1 : 30; /*!< [31..2] It is recommended to write these bits to 0. */ } CLK_CALIB_STS_REG1_b; }; union { - __IOM uint32_t CLK_CALIB_STS_REG2; /*!< (@ 0x00000078) Clock Calib Status + __IOM unsigned int CLK_CALIB_STS_REG2; /*!< (@ 0x00000078) Clock Calib Status Register2 */ struct { - __IOM uint32_t CC_NUM_TEST_CLKS : 32; /*!< [31..0] number of test clk cycles occurred + __IOM unsigned int CC_NUM_TEST_CLKS : 32; /*!< [31..0] number of test clk cycles occurred for the specified number of ref_clk cycles */ } CLK_CALIB_STS_REG2_b; }; union { - __IOM uint32_t CLK_CONFIG_REG6; /*!< (@ 0x0000007C) Clock Config Register6 */ + __IOM unsigned int CLK_CONFIG_REG6; /*!< (@ 0x0000007C) Clock Config Register6 */ struct { - __IOM uint32_t IID_KH_CLK_DIV_FAC : 3; /*!< [2..0] Clock division factor + __IOM unsigned int IID_KH_CLK_DIV_FAC : 3; /*!< [2..0] Clock division factor for iid_clk. */ - __IOM uint32_t Reserved1 : 2; /*!< [4..3] It is recommended to write these + __IOM unsigned int Reserved1 : 2; /*!< [4..3] It is recommended to write these bits to 0. */ - __IOM uint32_t PADCFG_PCLK_DIV_FAC : 4; /*!< [8..5] Clock division factor + __IOM unsigned int PADCFG_PCLK_DIV_FAC : 4; /*!< [8..5] Clock division factor for pclk_pad_config_m4ss */ - __IOM uint32_t QSPI_2_CLK_SEL : 3; /*!< [11..9] Selects one of the following clocks + __IOM unsigned int QSPI_2_CLK_SEL : 3; /*!< [11..9] Selects one of the following clocks for ssi master 000 - ULP Ref Clock(generated inside M4SS based on m4ss_ref_clk_sel from NPSS) 001 - Intf PLL @@ -11237,7 +11237,7 @@ typedef struct { /*!< (@ 0x46000000) M4CLK Structure */ (program bypass_modem_pll_clk if the bypass clock has to be selected) 011 - SoC PLL Clock */ - __IOM uint32_t QSPI_2_CLK_DIV_FAC : 6; /*!< [17..12] Clock divison factor for QSPI. + __IOM unsigned int QSPI_2_CLK_DIV_FAC : 6; /*!< [17..12] Clock divison factor for QSPI. If qspi_clk_enable is 1b0 clock is gated. Else 1)when qspi_clk_swallow_sel is 1b1 and qspi_odd_div_sel is 1b0 output clock is a @@ -11245,7 +11245,7 @@ typedef struct { /*!< (@ 0x46000000) M4CLK Structure */ frequency. 6h0,6h1 => clk_out = clk_in >6h1 => clk_out = clk_in/ qspi_clk_div_fac 2)when qspi_clk_swallow_sel is 1b0 */ - __IOM uint32_t QSPI_2_CLK_SWALLOW_SEL : 1; /*!< [18..18] Clock select for clock + __IOM unsigned int QSPI_2_CLK_SWALLOW_SEL : 1; /*!< [18..18] Clock select for clock swallow or clock divider for QSPI 1b0 => 50% divider is selected with division factor qspi_clk_div_fac 1b1 => @@ -11253,7 +11253,7 @@ typedef struct { /*!< (@ 0x46000000) M4CLK Structure */ division factor qspi_clk_div_fac Before Changing this ensure that the input clocks are gated */ - __IOM uint32_t QSPI_2_ODD_DIV_SEL : 1; /*!< [19..19] Clock select for clock swallow + __IOM unsigned int QSPI_2_ODD_DIV_SEL : 1; /*!< [19..19] Clock select for clock swallow or 50% even clock divider or 50% odd divider clock for QSPI 1b1 - 50% odd clock divider output is selected with division @@ -11262,101 +11262,101 @@ typedef struct { /*!< (@ 0x46000000) M4CLK Structure */ selected with division factor qspi_clk_div_fac based on qspi_clk_swallow_sel. */ - __IOM uint32_t Reserved2 : 12; /*!< [31..20] It is recommended to write + __IOM unsigned int Reserved2 : 12; /*!< [31..20] It is recommended to write these bits to 0. */ } CLK_CONFIG_REG6_b; }; union { - __IOM uint32_t DYN_CLK_GATE_DISABLE_REG2; /*!< (@ 0x00000080) Dynamic Clock + __IOM unsigned int DYN_CLK_GATE_DISABLE_REG2; /*!< (@ 0x00000080) Dynamic Clock Gate Disable Register2 */ struct { - __IOM uint32_t SOC_PLL_SPI_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [0..0] Dynamic clock gate + __IOM unsigned int SOC_PLL_SPI_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [0..0] Dynamic clock gate disable control soc pll spi clk 1b1 - Dynamic control of the clock is disbaled 1b0 - Dynamic control of the clock is enabled */ - __IOM uint32_t Reserved1 : 2; /*!< [2..1] It is recommended to write these + __IOM unsigned int Reserved1 : 2; /*!< [2..1] It is recommended to write these bits to 0. */ - __IOM uint32_t CT_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [3..3] Dynamic clock gate disable + __IOM unsigned int CT_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [3..3] Dynamic clock gate disable control SCT pclk 1b1 - Dynamic control of the clock is disbaled 1b0 - Dynamic control of the clock is enabled */ - __IOM uint32_t Reserved2 : 2; /*!< [5..4] It is recommended to write these + __IOM unsigned int Reserved2 : 2; /*!< [5..4] It is recommended to write these bits to 0. */ - __IOM uint32_t EFUSE_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [6..6] Dynamic clock gate + __IOM unsigned int EFUSE_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [6..6] Dynamic clock gate disable control efuse clk 1b1 - Dynamic control of the clock is disbaled 1b0 - Dynamic control of the clock is enabled */ - __IOM uint32_t EFUSE_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [7..7] Dynamic clock gate + __IOM unsigned int EFUSE_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [7..7] Dynamic clock gate disable control efuse pclk 1b1 - Dynamic control of the clock is disbaled 1b0 - Dynamic control of the clock is enabled */ - __IOM uint32_t Reserved3 : 24; /*!< [31..8] It is recommended to write + __IOM unsigned int Reserved3 : 24; /*!< [31..8] It is recommended to write these bits to 0. */ } DYN_CLK_GATE_DISABLE_REG2_b; }; union { - __IOM uint32_t PLL_LOCK_INT_STATUS_REG; /*!< (@ 0x00000084) PLL Lock + __IOM unsigned int PLL_LOCK_INT_STATUS_REG; /*!< (@ 0x00000084) PLL Lock Interrupt Status Register */ struct { - __IOM uint32_t LCD_PLL_LOCK_OF_RISING_EDGE : 1; /*!< [0..0] 1b0 - No Interrupt; 1b1 - + __IOM unsigned int LCD_PLL_LOCK_OF_RISING_EDGE : 1; /*!< [0..0] 1b0 - No Interrupt; 1b1 - Interrupt encountered. */ - __IOM uint32_t DDR_PLL_LOCK_OF_RISING_EDGE : 1; /*!< [1..1] 1'b0 => No Interrupt;1'b1 + __IOM unsigned int DDR_PLL_LOCK_OF_RISING_EDGE : 1; /*!< [1..1] 1'b0 => No Interrupt;1'b1 => Interrupt encountered. */ - __IOM uint32_t AP_PLL_LOCK_OF_RISING_EDGE : 1; /*!< [2..2] 1'b0 => No Interrupt;1'b1 + __IOM unsigned int AP_PLL_LOCK_OF_RISING_EDGE : 1; /*!< [2..2] 1'b0 => No Interrupt;1'b1 => Interrupt encountered. */ - __IOM uint32_t INTF_PLL_LOCK_OF_RISING_EDGE : 1; /*!< [3..3] 1'b0 => No + __IOM unsigned int INTF_PLL_LOCK_OF_RISING_EDGE : 1; /*!< [3..3] 1'b0 => No Interrupt;1'b1 => Interrupt encountered. */ - __IOM uint32_t I2S_PLL_LOCK_OF_RISING_EDGE : 1; /*!< [4..4] 1'b0 => No Interrupt;1'b1 + __IOM unsigned int I2S_PLL_LOCK_OF_RISING_EDGE : 1; /*!< [4..4] 1'b0 => No Interrupt;1'b1 => Interrupt encountered. */ - __IOM uint32_t SOC_PLL_LOCK_OF_RISING_EDGE : 1; /*!< [5..5] 1'b0 => No Interrupt;1'b1 + __IOM unsigned int SOC_PLL_LOCK_OF_RISING_EDGE : 1; /*!< [5..5] 1'b0 => No Interrupt;1'b1 => Interrupt encountered. */ - __IOM uint32_t MODEM_PLL_LOCK_OF_RISING_EDGE : 1; /*!< [6..6] 1'b0 => No + __IOM unsigned int MODEM_PLL_LOCK_OF_RISING_EDGE : 1; /*!< [6..6] 1'b0 => No Interrupt;1'b1 => Interrupt encountered. */ - __IOM uint32_t PLL_LOCK_DATA_TRIGGER_INTR_OF_RISING_EDGE : 1; /*!< [7..7] 1'b0 => No + __IOM unsigned int PLL_LOCK_DATA_TRIGGER_INTR_OF_RISING_EDGE : 1; /*!< [7..7] 1'b0 => No Interrupt;1'b1 => Interrupt encountered. */ - __IOM uint32_t LCD_PLL_LOCK_OF_FALLING_EDGE : 1; /*!< [8..8] 1'b0 => No + __IOM unsigned int LCD_PLL_LOCK_OF_FALLING_EDGE : 1; /*!< [8..8] 1'b0 => No Interrupt;1'b1 => Interrupt encountered. */ - __IOM uint32_t DDR_PLL_LOCK_OF_FALLING_EDGE : 1; /*!< [9..9] 1'b0 => No + __IOM unsigned int DDR_PLL_LOCK_OF_FALLING_EDGE : 1; /*!< [9..9] 1'b0 => No Interrupt;1'b1 => Interrupt encountered. */ - __IOM uint32_t AP_PLL_LOCK_OF_FALLING_EDGE : 1; /*!< [10..10] 1'b0 => No + __IOM unsigned int AP_PLL_LOCK_OF_FALLING_EDGE : 1; /*!< [10..10] 1'b0 => No Interrupt;1'b1 => Interrupt encountered. */ - __IOM uint32_t INTF_PLL_LOCK_OF_FALLING_EDGE : 1; /*!< [11..11] 1'b0 => No + __IOM unsigned int INTF_PLL_LOCK_OF_FALLING_EDGE : 1; /*!< [11..11] 1'b0 => No Interrupt;1'b1 => Interrupt encountered. */ - __IOM uint32_t I2S_PLL_LOCK_OF_FALLING_EDGE : 1; /*!< [12..12] 1'b0 => No + __IOM unsigned int I2S_PLL_LOCK_OF_FALLING_EDGE : 1; /*!< [12..12] 1'b0 => No Interrupt;1'b1 => Interrupt encountered. */ - __IOM uint32_t SOC_PLL_LOCK_OF_FALLING_EDGE : 1; /*!< [13..13] 1'b0 => No + __IOM unsigned int SOC_PLL_LOCK_OF_FALLING_EDGE : 1; /*!< [13..13] 1'b0 => No Interrupt;1'b1 => Interrupt encountered. */ - __IOM uint32_t MODEM_PLL_LOCK_OF_FALLING_EDGE : 1; /*!< [14..14] 1'b0 => No + __IOM unsigned int MODEM_PLL_LOCK_OF_FALLING_EDGE : 1; /*!< [14..14] 1'b0 => No Interrupt;1'b1 => Interrupt encountered. */ - __IOM uint32_t PLL_LOCK_DATA_TRIGGER_INTR_OF_FALLING_EDGE : 1; /*!< [15..15] 1'b0 => + __IOM unsigned int PLL_LOCK_DATA_TRIGGER_INTR_OF_FALLING_EDGE : 1; /*!< [15..15] 1'b0 => No Interrupt;1'b1 => Interrupt encountered. */ - __IOM uint32_t Reserved1 : 16; /*!< [31..16] It is recommended to write + __IOM unsigned int Reserved1 : 16; /*!< [31..16] It is recommended to write these bits to 0. */ } PLL_LOCK_INT_STATUS_REG_b; }; @@ -11377,24 +11377,24 @@ typedef struct { /*!< (@ 0x46000000) M4CLK Structure */ typedef struct { /*!< (@ 0x24048200) TIME_PERIOD Structure */ union { - __IOM uint32_t MCU_CAL_RO_TIMEPERIOD_READ; /*!< (@ 0x00000000) RO timeperiod + __IOM unsigned int MCU_CAL_RO_TIMEPERIOD_READ; /*!< (@ 0x00000000) RO timeperiod read register */ struct { - __IM uint32_t TIMEPERIOD_RO : 25; /*!< [24..0] Calibrated RO timeperiod */ - __IM uint32_t RESERVED1 : 7; /*!< [31..25] reser */ + __IM unsigned int TIMEPERIOD_RO : 25; /*!< [24..0] Calibrated RO timeperiod */ + __IM unsigned int RESERVED1 : 7; /*!< [31..25] reser */ } MCU_CAL_RO_TIMEPERIOD_READ_b; }; union { - __IOM uint32_t MCU_CAL_TIMER_CLOCK_PERIOD; /*!< (@ 0x00000004) MCU calender timer clock + __IOM unsigned int MCU_CAL_TIMER_CLOCK_PERIOD; /*!< (@ 0x00000004) MCU calender timer clock period register */ struct { - __IOM uint32_t RTC_TIMER_CLK_PERIOD : 25; /*!< [24..0] RTC timer clock + __IOM unsigned int RTC_TIMER_CLK_PERIOD : 25; /*!< [24..0] RTC timer clock period programmed by SOC */ - __IM uint32_t RESERVED1 : 6; /*!< [30..25] reser */ - __IM uint32_t SPI_RTC_TIMER_CLK_PERIOD_APPLIED_b : 1; /*!< [31..31] Indicated SOC + __IM unsigned int RESERVED1 : 6; /*!< [30..25] reser */ + __IM unsigned int SPI_RTC_TIMER_CLK_PERIOD_APPLIED_b : 1; /*!< [31..31] Indicated SOC programmed rtc_timer clock period is applied at KHz clock domain */ @@ -11402,94 +11402,94 @@ typedef struct { /*!< (@ 0x24048200) TIME_PERIOD Structure */ }; union { - __IOM uint32_t MCU_CAL_TEMP_PROG_REG; /*!< (@ 0x00000008) temprature program + __IOM unsigned int MCU_CAL_TEMP_PROG_REG; /*!< (@ 0x00000008) temprature program register */ struct { - __IOM uint32_t BYPASS_CALIB_PG : 1; /*!< [0..0] To bypass power gating and + __IOM unsigned int BYPASS_CALIB_PG : 1; /*!< [0..0] To bypass power gating and keep all the blocks always on */ - __IM uint32_t RESERVED1 : 15; /*!< [15..1] reser */ - __IOM uint32_t MAX_TEMP_CHANGE : 5; /*!< [20..16] maximum temperature change after + __IM unsigned int RESERVED1 : 15; /*!< [15..1] reser */ + __IOM unsigned int MAX_TEMP_CHANGE : 5; /*!< [20..16] maximum temperature change after which rc calibration must be trigger */ - __IOM uint32_t TEMP_TRIGGER_TIME_SEL : 2; /*!< [22..21] temperature + __IOM unsigned int TEMP_TRIGGER_TIME_SEL : 2; /*!< [22..21] temperature trigger time select */ - __IOM uint32_t PERIODIC_TEMP_CALIB_EN : 1; /*!< [23..23] Enable periodic + __IOM unsigned int PERIODIC_TEMP_CALIB_EN : 1; /*!< [23..23] Enable periodic checking of temperature */ - __IOM uint32_t RTC_TIMER_PERIOD_MUX_SEL : 1; /*!< [24..24] rtc timer + __IOM unsigned int RTC_TIMER_PERIOD_MUX_SEL : 1; /*!< [24..24] rtc timer period mux select */ - __IM uint32_t RESERVED2 : 7; /*!< [31..25] reser */ + __IM unsigned int RESERVED2 : 7; /*!< [31..25] reser */ } MCU_CAL_TEMP_PROG_REG_b; }; union { - __IOM uint32_t MCU_CAL_START_REG; /*!< (@ 0x0000000C) mcu cal start register */ + __IOM unsigned int MCU_CAL_START_REG; /*!< (@ 0x0000000C) mcu cal start register */ struct { - __IOM uint32_t ALPHA_RO : 3; /*!< [2..0] alpha = 1/2^alpha_ro , averaging factor of + __IOM unsigned int ALPHA_RO : 3; /*!< [2..0] alpha = 1/2^alpha_ro , averaging factor of RO timeperiod T = alpha(t_inst) + (1- alpha )t_prev */ - __IOM uint32_t ALPHA_RC : 3; /*!< [5..3] alpha = 1/2^alpha_rc , averaging factor of + __IOM unsigned int ALPHA_RC : 3; /*!< [5..3] alpha = 1/2^alpha_rc , averaging factor of RC timeperiod T = alpha(t_inst) + (1- alpha )t_prev */ - __IOM uint32_t NO_OF_RO_CLKS : 4; /*!< [9..6] 2^no_of_ro_clks no of clocks + __IOM unsigned int NO_OF_RO_CLKS : 4; /*!< [9..6] 2^no_of_ro_clks no of clocks of ro clock counts for no of rc clocks in that time to measure timeperiod */ - __IOM uint32_t NO_OF_RC_CLKS : 3; /*!< [12..10] 2^no_of_rc_clocks = no of + __IOM unsigned int NO_OF_RC_CLKS : 3; /*!< [12..10] 2^no_of_rc_clocks = no of rc clocks used in calibration */ - __IOM uint32_t RC_SETTLE_TIME : 3; /*!< [15..13] no of clocks of RO for the RC clk to + __IOM unsigned int RC_SETTLE_TIME : 3; /*!< [15..13] no of clocks of RO for the RC clk to settle when enabled */ - __IOM uint32_t RO_TRIGGER_TIME_SEL : 2; /*!< [17..16] ro trigger time select */ - __IOM uint32_t RC_TRIGGER_TIME_SEL : 3; /*!< [20..18] rc trigger time select */ - __IOM uint32_t PERIODIC_RO_CALIB_EN : 1; /*!< [21..21] periodically calibrate RO + __IOM unsigned int RO_TRIGGER_TIME_SEL : 2; /*!< [17..16] ro trigger time select */ + __IOM unsigned int RC_TRIGGER_TIME_SEL : 3; /*!< [20..18] rc trigger time select */ + __IOM unsigned int PERIODIC_RO_CALIB_EN : 1; /*!< [21..21] periodically calibrate RO timeperiod based ro trigger time sel */ - __IOM uint32_t PERIODIC_RC_CALIB_EN : 1; /*!< [22..22] periodically calibrate RC + __IOM unsigned int PERIODIC_RC_CALIB_EN : 1; /*!< [22..22] periodically calibrate RC timeperiod based rc trigger time sel */ - __OM uint32_t START_CALIB_RO : 1; /*!< [23..23] to initiate RO calibration */ - __OM uint32_t START_CALIB_RC : 1; /*!< [24..24] to initiate RC calibration */ - __IOM uint32_t RC_XTAL_MUX_SEL : 1; /*!< [25..25] xtal mux select */ - __IOM uint32_t LOW_POWER_TRIGGER_SEL : 1; /*!< [26..26] power trigger select */ - __IOM uint32_t VBATT_TRIGGER_TIME_SEL : 3; /*!< [29..27] trigger to ipmu block for + __OM unsigned int START_CALIB_RO : 1; /*!< [23..23] to initiate RO calibration */ + __OM unsigned int START_CALIB_RC : 1; /*!< [24..24] to initiate RC calibration */ + __IOM unsigned int RC_XTAL_MUX_SEL : 1; /*!< [25..25] xtal mux select */ + __IOM unsigned int LOW_POWER_TRIGGER_SEL : 1; /*!< [26..26] power trigger select */ + __IOM unsigned int VBATT_TRIGGER_TIME_SEL : 3; /*!< [29..27] trigger to ipmu block for checking vbatt status periodicaly */ - __IM uint32_t RESERVED1 : 2; /*!< [31..30] reser */ + __IM unsigned int RESERVED1 : 2; /*!< [31..30] reser */ } MCU_CAL_START_REG_b; }; union { - __IOM uint32_t MCU_CAL_REF_CLK_SETTLE_REG; /*!< (@ 0x00000010) reference + __IOM unsigned int MCU_CAL_REF_CLK_SETTLE_REG; /*!< (@ 0x00000010) reference clock settle register */ struct { - __IOM uint32_t XTAL_SETTLE : 7; /*!< [6..0] no of 32khz clocks for xtal + __IOM unsigned int XTAL_SETTLE : 7; /*!< [6..0] no of 32khz clocks for xtal 40mhz clk to settle */ - __IM uint32_t RESERVED1 : 9; /*!< [15..7] reser */ - __IM uint32_t VALID_RC_TIMEPERIOD : 1; /*!< [16..16] Valid signal for reading RC + __IM unsigned int RESERVED1 : 9; /*!< [15..7] reser */ + __IM unsigned int VALID_RC_TIMEPERIOD : 1; /*!< [16..16] Valid signal for reading RC timeperiod calibrated */ - __IM uint32_t VALID_RO_TIMEPERIOD : 1; /*!< [17..17] Valid signal for + __IM unsigned int VALID_RO_TIMEPERIOD : 1; /*!< [17..17] Valid signal for reading RO timeperiod */ - __IM uint32_t RESERVED2 : 14; /*!< [31..18] reser */ + __IM unsigned int RESERVED2 : 14; /*!< [31..18] reser */ } MCU_CAL_REF_CLK_SETTLE_REG_b; }; union { - __IOM uint32_t MCU_CAL_RC_TIMEPERIOD_READ; /*!< (@ 0x00000014) rc timeperiod + __IOM unsigned int MCU_CAL_RC_TIMEPERIOD_READ; /*!< (@ 0x00000014) rc timeperiod read register */ struct { - __IM uint32_t TIMEPERIOD_RC : 25; /*!< [24..0] Calibrated RC timeperiod */ - __IM uint32_t RESERVED1 : 7; /*!< [31..25] reser */ + __IM unsigned int TIMEPERIOD_RC : 25; /*!< [24..0] Calibrated RC timeperiod */ + __IM unsigned int RESERVED1 : 7; /*!< [31..25] reser */ } MCU_CAL_RC_TIMEPERIOD_READ_b; }; union { - __IOM uint32_t MCU_CAL_REF_CLK_TIEMPERIOD_REG; /*!< (@ 0x00000018) reference clock + __IOM unsigned int MCU_CAL_REF_CLK_TIEMPERIOD_REG; /*!< (@ 0x00000018) reference clock timeperiod register */ struct { - __IOM uint32_t TIMEPERIOD_REF_CLK : 24; /*!< [23..0] timeperiod of reference clk with + __IOM unsigned int TIMEPERIOD_REF_CLK : 24; /*!< [23..0] timeperiod of reference clk with each bit corresponding to granularity of 2^27 = 1us */ - __IM uint32_t RESERVED1 : 8; /*!< [31..24] reser */ + __IM unsigned int RESERVED1 : 8; /*!< [31..24] reser */ } MCU_CAL_REF_CLK_TIEMPERIOD_REG_b; }; } TIME_PERIOD_Type; /*!< Size = 28 (0x1c) */ @@ -11508,72 +11508,72 @@ typedef struct { /*!< (@ 0x24048200) TIME_PERIOD Structure */ typedef struct { /*!< (@ 0x24048300) MCU_WDT Structure */ union { - __IOM uint32_t MCU_WWD_INTERRUPT_TIMER; /*!< (@ 0x00000000) WATCHDOG + __IOM unsigned int MCU_WWD_INTERRUPT_TIMER; /*!< (@ 0x00000000) WATCHDOG interrupt timer register */ struct { - __IOM uint32_t WWD_INTERRUPT_TIMER : 5; /*!< [4..0] Watchdog Timer + __IOM unsigned int WWD_INTERRUPT_TIMER : 5; /*!< [4..0] Watchdog Timer programming values */ - __IM uint32_t RESERVED1 : 27; /*!< [31..5] reser */ + __IM unsigned int RESERVED1 : 27; /*!< [31..5] reser */ } MCU_WWD_INTERRUPT_TIMER_b; }; union { - __IOM uint32_t MCU_WWD_SYSTEM_RESET_TIMER; /*!< (@ 0x00000004) MCU watchdog + __IOM unsigned int MCU_WWD_SYSTEM_RESET_TIMER; /*!< (@ 0x00000004) MCU watchdog system reset register */ struct { - __IOM uint32_t WWD_SYSTEM_RESET_TIMER : 5; /*!< [4..0] Watch dog soc reset delay + __IOM unsigned int WWD_SYSTEM_RESET_TIMER : 5; /*!< [4..0] Watch dog soc reset delay timer programming values */ - __IM uint32_t RESERVED1 : 27; /*!< [31..5] reser */ + __IM unsigned int RESERVED1 : 27; /*!< [31..5] reser */ } MCU_WWD_SYSTEM_RESET_TIMER_b; }; union { - __IOM uint32_t MCU_WWD_WINDOW_TIMER; /*!< (@ 0x00000008) watchdog window + __IOM unsigned int MCU_WWD_WINDOW_TIMER; /*!< (@ 0x00000008) watchdog window timer register */ struct { - __IOM uint32_t WINDOW_TIMER : 4; /*!< [3..0] watchdog window timer */ - __IM uint32_t RESERVED1 : 28; /*!< [31..4] reser */ + __IOM unsigned int WINDOW_TIMER : 4; /*!< [3..0] watchdog window timer */ + __IM unsigned int RESERVED1 : 28; /*!< [31..4] reser */ } MCU_WWD_WINDOW_TIMER_b; }; union { - __IOM uint32_t MCU_WWD_ARM_STUCK_EN; /*!< (@ 0x0000000C) watchdog arm stuck + __IOM unsigned int MCU_WWD_ARM_STUCK_EN; /*!< (@ 0x0000000C) watchdog arm stuck enable register */ struct { - __IM uint32_t RESERVED1 : 16; /*!< [15..0] reser */ - __OM uint32_t PROCESSOR_STUCK_RESET_EN : 1; /*!< [16..16] Enable to reset M4 core on + __IM unsigned int RESERVED1 : 16; /*!< [15..0] reser */ + __OM unsigned int PROCESSOR_STUCK_RESET_EN : 1; /*!< [16..16] Enable to reset M4 core on seeing LOCKUP signal */ - __IM uint32_t RESERVED2 : 7; /*!< [23..17] reser */ - __IM uint32_t PROCESSOR_STUCK_RESET_EN_ : 1; /*!< [24..24] Read signal for processor + __IM unsigned int RESERVED2 : 7; /*!< [23..17] reser */ + __IM unsigned int PROCESSOR_STUCK_RESET_EN_ : 1; /*!< [24..24] Read signal for processor stuck reset enable */ - __IM uint32_t RESERVED3 : 7; /*!< [31..25] reser */ + __IM unsigned int RESERVED3 : 7; /*!< [31..25] reser */ } MCU_WWD_ARM_STUCK_EN_b; }; union { - __IOM uint32_t MCU_WWD_MODE_AND_RSTART; /*!< (@ 0x00000010) WATCHDOG mode + __IOM unsigned int MCU_WWD_MODE_AND_RSTART; /*!< (@ 0x00000010) WATCHDOG mode and restart register */ struct { - __IOM uint32_t WWD_MODE_RSTART : 1; /*!< [0..0] restart pulse to restart + __IOM unsigned int WWD_MODE_RSTART : 1; /*!< [0..0] restart pulse to restart watchdog timer */ - __IM uint32_t RESERVED1 : 15; /*!< [15..1] reser */ - __IOM uint32_t WWD_MODE_EN_STATUS : 8; /*!< [23..16] Watchdog timer mode */ - __IM uint32_t RESERVED2 : 8; /*!< [31..24] reser */ + __IM unsigned int RESERVED1 : 15; /*!< [15..1] reser */ + __IOM unsigned int WWD_MODE_EN_STATUS : 8; /*!< [23..16] Watchdog timer mode */ + __IM unsigned int RESERVED2 : 8; /*!< [31..24] reser */ } MCU_WWD_MODE_AND_RSTART_b; }; - __IM uint32_t RESERVED; + __IM unsigned int RESERVED; union { - __IOM uint32_t MCU_WWD_KEY_ENABLE; /*!< (@ 0x00000018) watchdog key enable + __IOM unsigned int MCU_WWD_KEY_ENABLE; /*!< (@ 0x00000018) watchdog key enable register */ struct { - __OM uint32_t WWD_KEY_ENABLE : 32; /*!< [31..0] enable access to program + __OM unsigned int WWD_KEY_ENABLE : 32; /*!< [31..0] enable access to program Watch dog registers */ } MCU_WWD_KEY_ENABLE_b; }; @@ -11594,148 +11594,148 @@ typedef struct { /*!< (@ 0x24048300) MCU_WDT Structure */ typedef struct { /*!< (@ 0x2404821C) RTC Structure */ union { - __IOM uint32_t MCU_CAL_ALARM_PROG_1; /*!< (@ 0x00000000) MCU calender alarm + __IOM unsigned int MCU_CAL_ALARM_PROG_1; /*!< (@ 0x00000000) MCU calender alarm prog register 1 */ struct { - __IOM uint32_t PROG_ALARM_MSEC : 10; /*!< [9..0] milli seconds value of + __IOM unsigned int PROG_ALARM_MSEC : 10; /*!< [9..0] milli seconds value of alarm time */ - __IOM uint32_t PROG_ALARM_SEC : 6; /*!< [15..10] seconds value of alarm time */ - __IOM uint32_t PROG_ALARM_MIN : 6; /*!< [21..16] mins value of alarm time */ - __IOM uint32_t PROG_ALARM_HOUR : 5; /*!< [26..22] hours value of alarm time */ - __IM uint32_t RESERVED1 : 5; /*!< [31..27] reser */ + __IOM unsigned int PROG_ALARM_SEC : 6; /*!< [15..10] seconds value of alarm time */ + __IOM unsigned int PROG_ALARM_MIN : 6; /*!< [21..16] mins value of alarm time */ + __IOM unsigned int PROG_ALARM_HOUR : 5; /*!< [26..22] hours value of alarm time */ + __IM unsigned int RESERVED1 : 5; /*!< [31..27] reser */ } MCU_CAL_ALARM_PROG_1_b; }; union { - __IOM uint32_t MCU_CAL_ALARM_PROG_2; /*!< (@ 0x00000004) MCU calender alarm + __IOM unsigned int MCU_CAL_ALARM_PROG_2; /*!< (@ 0x00000004) MCU calender alarm prog register 2 */ struct { - __IOM uint32_t PROG_ALARM_DAY : 5; /*!< [4..0] day count in alarm time 1-31 */ - __IM uint32_t RESERVED1 : 3; /*!< [7..5] reser */ - __IOM uint32_t PROG_ALARM_MONTH : 4; /*!< [11..8] month count in alarm time */ - __IM uint32_t RESERVED2 : 4; /*!< [15..12] reser */ - __IOM uint32_t PROG_ALARM_YEAR : 7; /*!< [22..16] year count in alarm time + __IOM unsigned int PROG_ALARM_DAY : 5; /*!< [4..0] day count in alarm time 1-31 */ + __IM unsigned int RESERVED1 : 3; /*!< [7..5] reser */ + __IOM unsigned int PROG_ALARM_MONTH : 4; /*!< [11..8] month count in alarm time */ + __IM unsigned int RESERVED2 : 4; /*!< [15..12] reser */ + __IOM unsigned int PROG_ALARM_YEAR : 7; /*!< [22..16] year count in alarm time 0 - 99 */ - __IOM uint32_t PROG_ALARM_CENTURY : 2; /*!< [24..23] century count in alarm time */ - __IM uint32_t RESERVED3 : 6; /*!< [30..25] reser */ - __IOM uint32_t ALARM_EN : 1; /*!< [31..31] alarm function enable for calendar */ + __IOM unsigned int PROG_ALARM_CENTURY : 2; /*!< [24..23] century count in alarm time */ + __IM unsigned int RESERVED3 : 6; /*!< [30..25] reser */ + __IOM unsigned int ALARM_EN : 1; /*!< [31..31] alarm function enable for calendar */ } MCU_CAL_ALARM_PROG_2_b; }; union { - __IOM uint32_t MCU_CAL_POWERGATE_REG; /*!< (@ 0x00000008) MCU calender + __IOM unsigned int MCU_CAL_POWERGATE_REG; /*!< (@ 0x00000008) MCU calender powergate register */ struct { - __IOM uint32_t PG_EN_CALENDER : 1; /*!< [0..0] Start calender block */ - __IOM uint32_t ENABLE_CALENDER_COMBI : 1; /*!< [1..1] Enable calender + __IOM unsigned int PG_EN_CALENDER : 1; /*!< [0..0] Start calender block */ + __IOM unsigned int ENABLE_CALENDER_COMBI : 1; /*!< [1..1] Enable calender combitional logic block */ - __IOM uint32_t DISABLE_COMBI_DYN_PWRGATE_EN : 1; /*!< [2..2] Disable option for + __IOM unsigned int DISABLE_COMBI_DYN_PWRGATE_EN : 1; /*!< [2..2] Disable option for dynamic combo RTC power gate */ - __IOM uint32_t STATIC_COMBI_RTC_PG_EN : 1; /*!< [3..3] Enable static combo + __IOM unsigned int STATIC_COMBI_RTC_PG_EN : 1; /*!< [3..3] Enable static combo RTC power gate */ - __IM uint32_t RESERVED1 : 28; /*!< [31..4] RESERVED1 */ + __IM unsigned int RESERVED1 : 28; /*!< [31..4] RESERVED1 */ } MCU_CAL_POWERGATE_REG_b; }; union { - __IOM uint32_t MCU_CAL_PROG_TIME_1; /*!< (@ 0x0000000C) MCU calendar prog + __IOM unsigned int MCU_CAL_PROG_TIME_1; /*!< (@ 0x0000000C) MCU calendar prog time 1 register */ struct { - __IOM uint32_t PROG_MSEC : 10; /*!< [9..0] Milli seconds value to be programmed to + __IOM unsigned int PROG_MSEC : 10; /*!< [9..0] Milli seconds value to be programmed to real time in calendar when pro_time_trig is 1 */ - __IOM uint32_t PROG_SEC : 6; /*!< [15..10] seconds value to be programmed to real + __IOM unsigned int PROG_SEC : 6; /*!< [15..10] seconds value to be programmed to real time in calendar when pro_time_trig is 1 */ - __IOM uint32_t PROG_MIN : 6; /*!< [21..16] minutes value to be programmed to real + __IOM unsigned int PROG_MIN : 6; /*!< [21..16] minutes value to be programmed to real time in calendar when pro_time_trig is 1 */ - __IOM uint32_t PROG_HOUR : 5; /*!< [26..22] hours value to be programmed to real time + __IOM unsigned int PROG_HOUR : 5; /*!< [26..22] hours value to be programmed to real time in calendar when pro_time_trig is 1 */ - __IM uint32_t RESERVED2 : 5; /*!< [31..27] reser */ + __IM unsigned int RESERVED2 : 5; /*!< [31..27] reser */ } MCU_CAL_PROG_TIME_1_b; }; union { - __IOM uint32_t MCU_CAL_PROG_TIME_2; /*!< (@ 0x00000010) MCU calendar prog + __IOM unsigned int MCU_CAL_PROG_TIME_2; /*!< (@ 0x00000010) MCU calendar prog time 2 register */ struct { - __IOM uint32_t PROG_DAY : 5; /*!< [4..0] day count value to be programmed to real + __IOM unsigned int PROG_DAY : 5; /*!< [4..0] day count value to be programmed to real time in calendar when pro_time_trig is 1 */ - __IOM uint32_t PROG_WEEK_DAY : 3; /*!< [7..5] program which week day it is */ - __IOM uint32_t PROG_MONTH : 4; /*!< [11..8] month value to be programmed to real time + __IOM unsigned int PROG_WEEK_DAY : 3; /*!< [7..5] program which week day it is */ + __IOM unsigned int PROG_MONTH : 4; /*!< [11..8] month value to be programmed to real time in calendar when pro_time_trig is 1 */ - __IM uint32_t RES : 4; /*!< [15..12] reser */ - __IOM uint32_t PROG_YEAR : 7; /*!< [22..16] year value to be programmed to real time + __IM unsigned int RES : 4; /*!< [15..12] reser */ + __IOM unsigned int PROG_YEAR : 7; /*!< [22..16] year value to be programmed to real time in calendar when pro_time_trig is 1 */ - __IOM uint32_t PROG_CENTURY : 2; /*!< [24..23] century value to be programmed to real + __IOM unsigned int PROG_CENTURY : 2; /*!< [24..23] century value to be programmed to real time in calendar when pro_time_trig is 1 */ - __IM uint32_t RESERVED1 : 6; /*!< [30..25] reser */ - __OM uint32_t PROG_TIME_TRIG : 1; /*!< [31..31] load the programmed to the + __IM unsigned int RESERVED1 : 6; /*!< [30..25] reser */ + __OM unsigned int PROG_TIME_TRIG : 1; /*!< [31..31] load the programmed to the real time in calendar block */ } MCU_CAL_PROG_TIME_2_b; }; union { - __IM uint32_t MCU_CAL_READ_TIME_MSB; /*!< (@ 0x00000014) MCU calendar read + __IM unsigned int MCU_CAL_READ_TIME_MSB; /*!< (@ 0x00000014) MCU calendar read time msb */ struct { - __IM uint32_t WEEK_DAY : 3; /*!< [2..0] week day */ - __IM uint32_t MONTHS_COUNT : 4; /*!< [6..3] months count */ - __IM uint32_t YEAR_COUNT : 7; /*!< [13..7] years count */ - __IM uint32_t CENTURY_COUNT : 2; /*!< [15..14] century count */ - __IM uint32_t RESERVED1 : 16; /*!< [31..16] reser */ + __IM unsigned int WEEK_DAY : 3; /*!< [2..0] week day */ + __IM unsigned int MONTHS_COUNT : 4; /*!< [6..3] months count */ + __IM unsigned int YEAR_COUNT : 7; /*!< [13..7] years count */ + __IM unsigned int CENTURY_COUNT : 2; /*!< [15..14] century count */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] reser */ } MCU_CAL_READ_TIME_MSB_b; }; union { - __IM uint32_t MCU_CAL_READ_TIME_LSB; /*!< (@ 0x00000018) MCU calendar read + __IM unsigned int MCU_CAL_READ_TIME_LSB; /*!< (@ 0x00000018) MCU calendar read time lsb */ struct { - __IM uint32_t MILLISECONDS_COUNT : 10; /*!< [9..0] milliseconds count */ - __IM uint32_t SECONDS_COUNT : 6; /*!< [15..10] seconds count */ - __IM uint32_t MINS_COUNT : 6; /*!< [21..16] mins count */ - __IM uint32_t HOURS_COUNT : 5; /*!< [26..22] hours count */ - __IM uint32_t DAYS_COUNT : 5; /*!< [31..27] days count */ + __IM unsigned int MILLISECONDS_COUNT : 10; /*!< [9..0] milliseconds count */ + __IM unsigned int SECONDS_COUNT : 6; /*!< [15..10] seconds count */ + __IM unsigned int MINS_COUNT : 6; /*!< [21..16] mins count */ + __IM unsigned int HOURS_COUNT : 5; /*!< [26..22] hours count */ + __IM unsigned int DAYS_COUNT : 5; /*!< [31..27] days count */ } MCU_CAL_READ_TIME_LSB_b; }; union { - __IM uint32_t MCU_CAL_READ_COUNT_TIMER; /*!< (@ 0x0000001C) MCU calendar + __IM unsigned int MCU_CAL_READ_COUNT_TIMER; /*!< (@ 0x0000001C) MCU calendar read count timer */ struct { - __IM uint32_t READ_COUNT_TIMER : 27; /*!< [26..0] Read timer which increments by + __IM unsigned int READ_COUNT_TIMER : 27; /*!< [26..0] Read timer which increments by time period value to reach to count milliseconds */ - __IM uint32_t RESERVED1 : 5; /*!< [31..27] reser */ + __IM unsigned int RESERVED1 : 5; /*!< [31..27] reser */ } MCU_CAL_READ_COUNT_TIMER_b; }; union { - __IM uint32_t MCU_CAL_SLEEP_CLK_COUNTERS; /*!< (@ 0x00000020) MCU calendar + __IM unsigned int MCU_CAL_SLEEP_CLK_COUNTERS; /*!< (@ 0x00000020) MCU calendar sleep clock counter */ struct { - __IM uint32_t SLEEP_CLK_DURATION : 12; /*!< [11..0] No of sleep clks with respect to + __IM unsigned int SLEEP_CLK_DURATION : 12; /*!< [11..0] No of sleep clks with respect to APB clock so far from the posedge of sleep clk */ - __IM uint32_t RESERVED1 : 4; /*!< [15..12] reser */ - __IM uint32_t PCLK_COUNT_WRT_SLEEP_CLK : 12; /*!< [27..16] no. of APB clks in 1 + __IM unsigned int RESERVED1 : 4; /*!< [15..12] reser */ + __IM unsigned int PCLK_COUNT_WRT_SLEEP_CLK : 12; /*!< [27..16] no. of APB clks in 1 sleep clock duration */ - __IM uint32_t RESERVED2 : 4; /*!< [31..28] reser */ + __IM unsigned int RESERVED2 : 4; /*!< [31..28] reser */ } MCU_CAL_SLEEP_CLK_COUNTERS_b; }; union { - __OM uint32_t MCU_CAL_KEY_EANBLE; /*!< (@ 0x00000024) MCU calendar key enable */ + __OM unsigned int MCU_CAL_KEY_EANBLE; /*!< (@ 0x00000024) MCU calendar key enable */ struct { - __OM uint32_t RTC_KEY : 32; /*!< [31..0] enable access to program Watch + __OM unsigned int RTC_KEY : 32; /*!< [31..0] enable access to program Watch dog registers */ } MCU_CAL_KEY_EANBLE_b; }; @@ -11756,627 +11756,627 @@ typedef struct { /*!< (@ 0x2404821C) RTC Structure */ typedef struct { /*!< (@ 0x24048400) BATT_FF Structure */ union { - __IOM uint32_t M4SS_BYPASS_PWRCTRL_REG1; /*!< (@ 0x00000000) M4ss bypass + __IOM unsigned int M4SS_BYPASS_PWRCTRL_REG1; /*!< (@ 0x00000000) M4ss bypass power control register 1 */ struct { - __IM uint32_t RES : 3; /*!< [2..0] reserved1 */ - __IOM uint32_t BYPASS_M4SS_PWRCTL_ULP_M4_ULP_AON_b : 1; /*!< [3..3] Enables software + __IM unsigned int RES : 3; /*!< [2..0] reserved1 */ + __IOM unsigned int BYPASS_M4SS_PWRCTL_ULP_M4_ULP_AON_b : 1; /*!< [3..3] Enables software based control of isolation and reset for ULP AON M4ss */ - __IOM uint32_t BYPASS_M4SS_PWRCTL_ULP_EFUSE_b : 1; /*!< [4..4] Enables software based + __IOM unsigned int BYPASS_M4SS_PWRCTL_ULP_EFUSE_b : 1; /*!< [4..4] Enables software based control of isolation and reset for ULP EFUSE */ - __IOM uint32_t RESERVED2 : 4; /*!< [8..5] reserved2 */ - __IOM uint32_t BYPASS_M4SS_PWRCTL_ULP_RPDMA_b : 1; /*!< [9..9] Enables software based + __IOM unsigned int RESERVED2 : 4; /*!< [8..5] reserved2 */ + __IOM unsigned int BYPASS_M4SS_PWRCTL_ULP_RPDMA_b : 1; /*!< [9..9] Enables software based control of isolation and reset for RPDMA */ - __IOM uint32_t RESERVED3 : 1; /*!< [10..10] reserved3 */ - __IOM uint32_t BYPASS_M4SS_PWRCTL_ULP_HIF_SDIO_SPI_b : 1; /*!< [11..11] Enables + __IOM unsigned int RESERVED3 : 1; /*!< [10..10] reserved3 */ + __IOM unsigned int BYPASS_M4SS_PWRCTL_ULP_HIF_SDIO_SPI_b : 1; /*!< [11..11] Enables software based control of isolation and reset for HIF SDIO SPI */ - __IOM uint32_t RESERVED4 : 1; /*!< [12..12] reserved4 */ - __IOM uint32_t BYPASS_M4SS_PWRCTL_ULP_QSPI_ICACHE_b : 1; /*!< [13..13] Enables + __IOM unsigned int RESERVED4 : 1; /*!< [12..12] reserved4 */ + __IOM unsigned int BYPASS_M4SS_PWRCTL_ULP_QSPI_ICACHE_b : 1; /*!< [13..13] Enables software based control of isolation and reset for ULP quad SPI and ICACHE */ - __IOM uint32_t BYPASS_M4SS_PWRCTL_ULP_IID_b : 1; /*!< [14..14] Enables software based + __IOM unsigned int BYPASS_M4SS_PWRCTL_ULP_IID_b : 1; /*!< [14..14] Enables software based control of isolation and reset for ULP IID */ - __IOM uint32_t RESERVED5 : 2; /*!< [16..15] reserved5 */ + __IOM unsigned int RESERVED5 : 2; /*!< [16..15] reserved5 */ __IOM - uint32_t BYPASS_M4SS_PWRCTL_ULP_M4_DEBUG_b : 1; /*!< [17..17] Enables + unsigned int BYPASS_M4SS_PWRCTL_ULP_M4_DEBUG_b : 1; /*!< [17..17] Enables software based control of isolation and reset for M4ss DEBUG */ - __IOM uint32_t BYPASS_M4SS_PWRCTL_ULP_M4_CORE_b : 1; /*!< [18..18] Enables software + __IOM unsigned int BYPASS_M4SS_PWRCTL_ULP_M4_CORE_b : 1; /*!< [18..18] Enables software based control of isolation and reset for M4ss CORE */ - __IOM uint32_t BYPASS_M4SS_PWRCTL_ULP_AON_b : 1; /*!< [19..19] Enables software based + __IOM unsigned int BYPASS_M4SS_PWRCTL_ULP_AON_b : 1; /*!< [19..19] Enables software based control of isolation and reset for ULP AON */ - __IM uint32_t RESERVED6 : 2; /*!< [21..20] reserved6 */ - __IOM uint32_t BYPASS_M4SS_PWRCTL_ULP_ROM_b : 1; /*!< [22..22] Enables software based + __IM unsigned int RESERVED6 : 2; /*!< [21..20] reserved6 */ + __IOM unsigned int BYPASS_M4SS_PWRCTL_ULP_ROM_b : 1; /*!< [22..22] Enables software based control of isolation and reset for M4ss ROM */ - __IM uint32_t RESERVED7 : 9; /*!< [31..23] reserved7 */ + __IM unsigned int RESERVED7 : 9; /*!< [31..23] reserved7 */ } M4SS_BYPASS_PWRCTRL_REG1_b; }; union { - __IOM uint32_t M4SS_BYPASS_PWRCTRL_REG2; /*!< (@ 0x00000004) M4SS bypass + __IOM unsigned int M4SS_BYPASS_PWRCTRL_REG2; /*!< (@ 0x00000004) M4SS bypass power control register 2 */ struct { - __IOM uint32_t BYPASS_M4SS_PWRCTL_ULP_SRAM_1 : 10; /*!< [9..0] Enables software based + __IOM unsigned int BYPASS_M4SS_PWRCTL_ULP_SRAM_1 : 10; /*!< [9..0] Enables software based control of isolation and reset for M4ss SRAM 1 */ - __IM uint32_t RESERVED1 : 6; /*!< [15..10] reserved1 */ - __IOM uint32_t BYPASS_M4SS_PWRCTL_ULP_SRAM_2 : 4; /*!< [19..16] Enables software + __IM unsigned int RESERVED1 : 6; /*!< [15..10] reserved1 */ + __IOM unsigned int BYPASS_M4SS_PWRCTL_ULP_SRAM_2 : 4; /*!< [19..16] Enables software based control of isolation and reset for M4ss SRAM 2 */ - __IM uint32_t RESERVED2 : 12; /*!< [31..20] reserved1 */ + __IM unsigned int RESERVED2 : 12; /*!< [31..20] reserved1 */ } M4SS_BYPASS_PWRCTRL_REG2_b; }; union { - __IOM uint32_t M4SS_PWRCTRL_SET_REG; /*!< (@ 0x00000008) M4SS power control + __IOM unsigned int M4SS_PWRCTRL_SET_REG; /*!< (@ 0x00000008) M4SS power control set register */ struct { - __IM uint32_t RES : 4; /*!< [3..0] reserved1 */ - __IOM uint32_t M4SS_PWRGATE_EN_N_ULP_EFUSE_b : 1; /*!< [4..4] Power Gate control for + __IM unsigned int RES : 4; /*!< [3..0] reserved1 */ + __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_EFUSE_b : 1; /*!< [4..4] Power Gate control for EFUSE */ - __IM uint32_t RESERVED2 : 4; /*!< [8..5] reserved2 */ - __IOM uint32_t M4SS_PWRGATE_EN_N_ULP_RPDMA_b : 1; /*!< [9..9] Power Gate control for + __IM unsigned int RESERVED2 : 4; /*!< [8..5] reserved2 */ + __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_RPDMA_b : 1; /*!< [9..9] Power Gate control for RPDMA */ - __IM uint32_t RESERVED3 : 1; /*!< [10..10] reserved3 */ - __IOM uint32_t M4SS_PWRGATE_EN_N_ULP_HIF_SDIO_SPI_b : 1; /*!< [11..11] Power Gate + __IM unsigned int RESERVED3 : 1; /*!< [10..10] reserved3 */ + __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_HIF_SDIO_SPI_b : 1; /*!< [11..11] Power Gate control for HIF SDIO SPI */ - __IM uint32_t RESERVED4 : 1; /*!< [12..12] reserved4 */ - __IOM uint32_t M4SS_PWRGATE_EN_N_ULP_QSPI_ICACHE_b : 1; /*!< [13..13] Power Gate + __IM unsigned int RESERVED4 : 1; /*!< [12..12] reserved4 */ + __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_QSPI_ICACHE_b : 1; /*!< [13..13] Power Gate control for QSPI and ICACHE */ - __IOM uint32_t M4SS_PWRGATE_EN_N_ULP_IID_b : 1; /*!< [14..14] Power Gate control for + __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_IID_b : 1; /*!< [14..14] Power Gate control for IID Block.If set, powered ON Clearing this bit has no effect */ - __IM uint32_t RESERVED5 : 2; /*!< [16..15] reserved5 */ - __IOM uint32_t M4SS_PWRGATE_EN_N_ULP_M4_DEBUG_b : 1; /*!< [17..17] Power Gate control + __IM unsigned int RESERVED5 : 2; /*!< [16..15] reserved5 */ + __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_M4_DEBUG_b : 1; /*!< [17..17] Power Gate control for M4 DEBUG */ - __IOM uint32_t M4SS_PWRGATE_EN_N_ULP_M4_CORE_b : 1; /*!< [18..18] Power Gate control + __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_M4_CORE_b : 1; /*!< [18..18] Power Gate control for M4 CORE */ - __IM uint32_t RESERVED6 : 3; /*!< [21..19] reserved6 */ - __IOM uint32_t M4SS_EXT_PWRGATE_EN_N_ULP_ROM_b : 1; /*!< [22..22] External power gate + __IM unsigned int RESERVED6 : 3; /*!< [21..19] reserved6 */ + __IOM unsigned int M4SS_EXT_PWRGATE_EN_N_ULP_ROM_b : 1; /*!< [22..22] External power gate enable signal for ROM */ - __IM uint32_t RESERVED7 : 9; /*!< [31..23] reserved7 */ + __IM unsigned int RESERVED7 : 9; /*!< [31..23] reserved7 */ } M4SS_PWRCTRL_SET_REG_b; }; union { - __IOM uint32_t M4SS_PWRCTRL_CLEAR_REG; /*!< (@ 0x0000000C) M4SS power + __IOM unsigned int M4SS_PWRCTRL_CLEAR_REG; /*!< (@ 0x0000000C) M4SS power control clear register */ struct { - __IM uint32_t RES : 4; /*!< [3..0] reserved1 */ - __IOM uint32_t M4SS_PWRGATE_EN_N_ULP_EFUSE_b : 1; /*!< [4..4] Power Gate control for + __IM unsigned int RES : 4; /*!< [3..0] reserved1 */ + __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_EFUSE_b : 1; /*!< [4..4] Power Gate control for EFUSE */ - __IM uint32_t RESERVED2 : 4; /*!< [8..5] reserved2 */ - __IOM uint32_t M4SS_PWRGATE_EN_N_ULP_RPDMA_b : 1; /*!< [9..9] Power Gate control for + __IM unsigned int RESERVED2 : 4; /*!< [8..5] reserved2 */ + __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_RPDMA_b : 1; /*!< [9..9] Power Gate control for RPDMA */ - __IM uint32_t RESERVED3 : 1; /*!< [10..10] reserved3 */ - __IOM uint32_t M4SS_PWRGATE_EN_N_ULP_HIF_SDIO_SPI_b : 1; /*!< [11..11] Power Gate + __IM unsigned int RESERVED3 : 1; /*!< [10..10] reserved3 */ + __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_HIF_SDIO_SPI_b : 1; /*!< [11..11] Power Gate control for HIF SDIO SPI */ - __IM uint32_t RESERVED4 : 1; /*!< [12..12] reserved4 */ - __IOM uint32_t M4SS_PWRGATE_EN_N_ULP_QSPI_ICACHE_b : 1; /*!< [13..13] Power Gate + __IM unsigned int RESERVED4 : 1; /*!< [12..12] reserved4 */ + __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_QSPI_ICACHE_b : 1; /*!< [13..13] Power Gate control for QSPI and ICACHE */ - __IOM uint32_t M4SS_PWRGATE_EN_N_ULP_IID_b : 1; /*!< [14..14] Power Gate control for + __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_IID_b : 1; /*!< [14..14] Power Gate control for IID Block.If set, powered ON Clearing this bit has no effect */ - __IM uint32_t RESERVED5 : 2; /*!< [16..15] reserved5 */ - __IOM uint32_t M4SS_PWRGATE_EN_N_ULP_M4_DEBUG_b : 1; /*!< [17..17] Power Gate control + __IM unsigned int RESERVED5 : 2; /*!< [16..15] reserved5 */ + __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_M4_DEBUG_b : 1; /*!< [17..17] Power Gate control for M4 DEBUG */ - __IOM uint32_t M4SS_PWRGATE_EN_N_ULP_M4_CORE_b : 1; /*!< [18..18] Power Gate control + __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_M4_CORE_b : 1; /*!< [18..18] Power Gate control for M4 CORE */ - __IM uint32_t RESERVED6 : 3; /*!< [21..19] reserved6 */ - __IOM uint32_t M4SS_EXT_PWRGATE_EN_N_ULP_ROM_b : 1; /*!< [22..22] External power gate + __IM unsigned int RESERVED6 : 3; /*!< [21..19] reserved6 */ + __IOM unsigned int M4SS_EXT_PWRGATE_EN_N_ULP_ROM_b : 1; /*!< [22..22] External power gate enable signal for ROM */ - __IM uint32_t RESERVED7 : 9; /*!< [31..23] reserved7 */ + __IM unsigned int RESERVED7 : 9; /*!< [31..23] reserved7 */ } M4SS_PWRCTRL_CLEAR_REG_b; }; union { - __IOM uint32_t M4_SRAM_PWRCTRL_SET_REG1; /*!< (@ 0x00000010) M4SS power + __IOM unsigned int M4_SRAM_PWRCTRL_SET_REG1; /*!< (@ 0x00000010) M4SS power control set register 1 */ struct { - __IOM uint32_t M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_1 : 10; /*!< [9..0] Functional Control + __IOM unsigned int M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_1 : 10; /*!< [9..0] Functional Control signal for M4SS SRAM */ - __IM uint32_t RESERVED1 : 6; /*!< [15..10] reserved1 */ - __IOM uint32_t M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_2 : 4; /*!< [19..16] Functional Control + __IM unsigned int RESERVED1 : 6; /*!< [15..10] reserved1 */ + __IOM unsigned int M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_2 : 4; /*!< [19..16] Functional Control signal for TASS SRAM shared with M4SS */ - __IOM uint32_t RESERVED2 : 12; /*!< [31..20] reserved1 */ + __IOM unsigned int RESERVED2 : 12; /*!< [31..20] reserved1 */ } M4_SRAM_PWRCTRL_SET_REG1_b; }; union { - __IOM uint32_t M4_SRAM_PWRCTRL_CLEAR_REG1; /*!< (@ 0x00000014) M4SS power + __IOM unsigned int M4_SRAM_PWRCTRL_CLEAR_REG1; /*!< (@ 0x00000014) M4SS power control clear register 1 */ struct { - __IOM uint32_t M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_1 : 10; /*!< [9..0] Functional Control + __IOM unsigned int M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_1 : 10; /*!< [9..0] Functional Control signal for M4SS SRAM */ - __IOM uint32_t RESERVED1 : 6; /*!< [15..10] reserved1 */ - __IOM uint32_t M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_2 : 4; /*!< [19..16] Functional Control + __IOM unsigned int RESERVED1 : 6; /*!< [15..10] reserved1 */ + __IOM unsigned int M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_2 : 4; /*!< [19..16] Functional Control signal for TASS SRAM shared with M4SS */ - __IOM uint32_t RESERVED2 : 12; /*!< [31..20] reserved1 */ + __IOM unsigned int RESERVED2 : 12; /*!< [31..20] reserved1 */ } M4_SRAM_PWRCTRL_CLEAR_REG1_b; }; union { - __IOM uint32_t M4_SRAM_PWRCTRL_SET_REG2; /*!< (@ 0x00000018) M4SS power + __IOM unsigned int M4_SRAM_PWRCTRL_SET_REG2; /*!< (@ 0x00000018) M4SS power control set register 2 */ struct { - __IOM uint32_t M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_PERI_1 : 10; /*!< [9..0] Functional + __IOM unsigned int M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_PERI_1 : 10; /*!< [9..0] Functional Control signal for M4SS SRAM Dual Rail pins */ - __IOM uint32_t RESERVED1 : 6; /*!< [15..10] reserved1 */ - __IOM uint32_t M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_PERI_2 : 4; /*!< [19..16] Functional + __IOM unsigned int RESERVED1 : 6; /*!< [15..10] reserved1 */ + __IOM unsigned int M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_PERI_2 : 4; /*!< [19..16] Functional Control signal for TASS SRAM Dual Rail pins shared with M4SS */ - __IOM uint32_t RESERVED2 : 12; /*!< [31..20] reserved1 */ + __IOM unsigned int RESERVED2 : 12; /*!< [31..20] reserved1 */ } M4_SRAM_PWRCTRL_SET_REG2_b; }; union { - __IOM uint32_t M4_SRAM_PWRCTRL_CLEAR_REG2; /*!< (@ 0x0000001C) M4SS power + __IOM unsigned int M4_SRAM_PWRCTRL_CLEAR_REG2; /*!< (@ 0x0000001C) M4SS power control clear register 2 */ struct { - __IOM uint32_t M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_PERI_1 : 10; /*!< [9..0] Functional + __IOM unsigned int M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_PERI_1 : 10; /*!< [9..0] Functional Control signal for M4SS SRAM Dual Rail pins */ - __IOM uint32_t RESERVED1 : 6; /*!< [15..10] reserved1 */ - __IOM uint32_t M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_PERI_2 : 4; /*!< [19..16] Functional + __IOM unsigned int RESERVED1 : 6; /*!< [15..10] reserved1 */ + __IOM unsigned int M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_PERI_2 : 4; /*!< [19..16] Functional Control signal for TASS SRAM Dual Rail pins shared with M4SS */ - __IOM uint32_t RESERVED2 : 12; /*!< [31..20] reserved1 */ + __IOM unsigned int RESERVED2 : 12; /*!< [31..20] reserved1 */ } M4_SRAM_PWRCTRL_CLEAR_REG2_b; }; union { - __IOM uint32_t M4_SRAM_PWRCTRL_SET_REG3; /*!< (@ 0x00000020) M4SS power + __IOM unsigned int M4_SRAM_PWRCTRL_SET_REG3; /*!< (@ 0x00000020) M4SS power control set register 3 */ struct { - __IOM uint32_t M4SS_SRAM_INPUT_DISABLE_ISOLATION_ULP_1 : 10; /*!< [9..0] Input + __IOM unsigned int M4SS_SRAM_INPUT_DISABLE_ISOLATION_ULP_1 : 10; /*!< [9..0] Input isolation control for M4SS SRAM */ - __IOM uint32_t RESERVED1 : 6; /*!< [15..10] reserved1 */ - __IOM uint32_t M4SS_SRAM_INPUT_DISABLE_ISOLATION_ULP_2 : 4; /*!< [19..16] Input + __IOM unsigned int RESERVED1 : 6; /*!< [15..10] reserved1 */ + __IOM unsigned int M4SS_SRAM_INPUT_DISABLE_ISOLATION_ULP_2 : 4; /*!< [19..16] Input isolation control for TASS SRAM shared with M4SS */ - __IOM uint32_t RESERVED2 : 12; /*!< [31..20] reserved1 */ + __IOM unsigned int RESERVED2 : 12; /*!< [31..20] reserved1 */ } M4_SRAM_PWRCTRL_SET_REG3_b; }; union { - __IOM uint32_t M4_SRAM_PWRCTRL_CLEAR_REG3; /*!< (@ 0x00000024) M4SS power + __IOM unsigned int M4_SRAM_PWRCTRL_CLEAR_REG3; /*!< (@ 0x00000024) M4SS power control clear register 3 */ struct { - __IOM uint32_t M4SS_SRAM_INPUT_DISABLE_ISOLATION_ULP_1 : 10; /*!< [9..0] Input + __IOM unsigned int M4SS_SRAM_INPUT_DISABLE_ISOLATION_ULP_1 : 10; /*!< [9..0] Input isolation control for M4SS SRAM */ - __IOM uint32_t RESERVED1 : 6; /*!< [15..10] reserved1 */ - __IOM uint32_t M4SS_SRAM_INPUT_DISABLE_ISOLATION_ULP_2 : 4; /*!< [19..16] Input + __IOM unsigned int RESERVED1 : 6; /*!< [15..10] reserved1 */ + __IOM unsigned int M4SS_SRAM_INPUT_DISABLE_ISOLATION_ULP_2 : 4; /*!< [19..16] Input isolation control for TASS SRAM shared with M4SS */ - __IOM uint32_t RESERVED2 : 12; /*!< [31..20] reserved1 */ + __IOM unsigned int RESERVED2 : 12; /*!< [31..20] reserved1 */ } M4_SRAM_PWRCTRL_CLEAR_REG3_b; }; union { - __IOM uint32_t M4_SRAM_PWRCTRL_SET_REG4; /*!< (@ 0x00000028) M4SS power + __IOM unsigned int M4_SRAM_PWRCTRL_SET_REG4; /*!< (@ 0x00000028) M4SS power control set register 4 */ struct { - __IOM uint32_t M4SS_SRAM_DS_1 : 24; /*!< [23..0] Deep-Sleep control for + __IOM unsigned int M4SS_SRAM_DS_1 : 24; /*!< [23..0] Deep-Sleep control for M4SS SRAM */ - __IOM uint32_t RESERVED1 : 8; /*!< [31..24] reserved1 */ + __IOM unsigned int RESERVED1 : 8; /*!< [31..24] reserved1 */ } M4_SRAM_PWRCTRL_SET_REG4_b; }; union { - __IOM uint32_t M4_SRAM_PWRCTRL_CLEAR_REG4; /*!< (@ 0x0000002C) M4SS power + __IOM unsigned int M4_SRAM_PWRCTRL_CLEAR_REG4; /*!< (@ 0x0000002C) M4SS power control clear register 4 */ struct { - __IOM uint32_t M4SS_SRAM_DS_1 : 24; /*!< [23..0] Deep-Sleep control for + __IOM unsigned int M4SS_SRAM_DS_1 : 24; /*!< [23..0] Deep-Sleep control for M4SS SRAM */ - __IOM uint32_t RESERVED1 : 8; /*!< [31..24] reserved1 */ + __IOM unsigned int RESERVED1 : 8; /*!< [31..24] reserved1 */ } M4_SRAM_PWRCTRL_CLEAR_REG4_b; }; - __IM uint32_t RESERVED; + __IM unsigned int RESERVED; union { - __IOM uint32_t M4SS_TASS_CTRL_SET_REG; /*!< (@ 0x00000034) M4SS_TASS control + __IOM unsigned int M4SS_TASS_CTRL_SET_REG; /*!< (@ 0x00000034) M4SS_TASS control set register */ struct { - __IOM uint32_t M4SS_CTRL_TASS_AON_PWRGATE_EN : 1; /*!< [0..0] M4SS controlling Power + __IOM unsigned int M4SS_CTRL_TASS_AON_PWRGATE_EN : 1; /*!< [0..0] M4SS controlling Power supply for TASS AON domain */ - __IOM uint32_t M4SS_CTRL_TASS_AON_DISABLE_ISOLATION_BYPASS : 1; /*!< [1..1] M4SS + __IOM unsigned int M4SS_CTRL_TASS_AON_DISABLE_ISOLATION_BYPASS : 1; /*!< [1..1] M4SS controlling Power supply for TASS AON domains isolation enable in bypass mode */ - __IOM uint32_t M4SS_CTRL_TASS_AON_PWR_DMN_RST_BYPASS : 1; /*!< [2..2] M4SS + __IOM unsigned int M4SS_CTRL_TASS_AON_PWR_DMN_RST_BYPASS : 1; /*!< [2..2] M4SS controlling Power supply for TASS AON domains reset pin in bypass mode */ - __IOM uint32_t RESERVED1 : 29; /*!< [31..3] reserved1 */ + __IOM unsigned int RESERVED1 : 29; /*!< [31..3] reserved1 */ } M4SS_TASS_CTRL_SET_REG_b; }; union { - __IOM uint32_t M4SS_TASS_CTRL_CLEAR_REG; /*!< (@ 0x00000038) M4SS_TASS + __IOM unsigned int M4SS_TASS_CTRL_CLEAR_REG; /*!< (@ 0x00000038) M4SS_TASS control CLEAR register */ struct { - __IOM uint32_t M4SS_CTRL_TASS_AON_PWRGATE_EN : 1; /*!< [0..0] M4SS controlling Power + __IOM unsigned int M4SS_CTRL_TASS_AON_PWRGATE_EN : 1; /*!< [0..0] M4SS controlling Power supply for TASS AON domain */ - __IOM uint32_t M4SS_CTRL_TASS_AON_DISABLE_ISOLATION_BYPASS : 1; /*!< [1..1] M4SS + __IOM unsigned int M4SS_CTRL_TASS_AON_DISABLE_ISOLATION_BYPASS : 1; /*!< [1..1] M4SS controlling Power supply for TASS AON domains isolation enable in bypass mode */ - __IOM uint32_t M4SS_CTRL_TASS_AON_PWR_DMN_RST_BYPASS : 1; /*!< [2..2] M4SS + __IOM unsigned int M4SS_CTRL_TASS_AON_PWR_DMN_RST_BYPASS : 1; /*!< [2..2] M4SS controlling Power supply for TASS AON domains reset pin in bypass mode */ - __IOM uint32_t RESERVED1 : 29; /*!< [31..3] reserved1 */ + __IOM unsigned int RESERVED1 : 29; /*!< [31..3] reserved1 */ } M4SS_TASS_CTRL_CLEAR_REG_b; }; union { - __IOM uint32_t M4_ULP_MODE_CONFIG; /*!< (@ 0x0000003C) m4 ulp mode config register */ + __IOM unsigned int M4_ULP_MODE_CONFIG; /*!< (@ 0x0000003C) m4 ulp mode config register */ struct { - __IOM uint32_t ULPMODE_ISOLATION_CTRL_ULPSS : 1; /*!< [0..0] Isolation Control for + __IOM unsigned int ULPMODE_ISOLATION_CTRL_ULPSS : 1; /*!< [0..0] Isolation Control for ULP-Mode non-functional paths for ULPSS */ - __IOM uint32_t ULPMODE_ISOLATION_CTRL_M4SS_AON : 1; /*!< [1..1] Isolation Control for + __IOM unsigned int ULPMODE_ISOLATION_CTRL_M4SS_AON : 1; /*!< [1..1] Isolation Control for ULP-Mode non-functional paths for M4SS-AON */ - __IOM uint32_t ULPMODE_ISOLATION_CTRL_M4_ULP : 1; /*!< [2..2] Isolation Control for + __IOM unsigned int ULPMODE_ISOLATION_CTRL_M4_ULP : 1; /*!< [2..2] Isolation Control for ULP-Mode non-functional paths for M4ULP_AON */ - __IOM uint32_t ULPMODE_ISOLATION_CTRL_M4_CORE : 1; /*!< [3..3] Isolation Control for + __IOM unsigned int ULPMODE_ISOLATION_CTRL_M4_CORE : 1; /*!< [3..3] Isolation Control for ULP-Mode non-functional paths for M4_CORE */ - __IOM uint32_t ULPMODE_ISOLATION_CTRL_M4_DEBUG_FPU : 1; /*!< [4..4] Isolation Control + __IOM unsigned int ULPMODE_ISOLATION_CTRL_M4_DEBUG_FPU : 1; /*!< [4..4] Isolation Control for ULP-Mode non-functional paths for M4_DEBUG */ - __IOM uint32_t ULPMODE_ISOLATION_CTRL_M4_ROM : 1; /*!< [5..5] Isolation Control for + __IOM unsigned int ULPMODE_ISOLATION_CTRL_M4_ROM : 1; /*!< [5..5] Isolation Control for ULP-Mode non-functional paths for ROM */ - __IOM uint32_t RES : 26; /*!< [31..6] reserved1 */ + __IOM unsigned int RES : 26; /*!< [31..6] reserved1 */ } M4_ULP_MODE_CONFIG_b; }; union { - __IOM uint32_t ULPSS_BYPASS_PWRCTRL_REG; /*!< (@ 0x00000040) ULPSS bypass + __IOM unsigned int ULPSS_BYPASS_PWRCTRL_REG; /*!< (@ 0x00000040) ULPSS bypass power control register */ struct { - __IOM uint32_t RES : 2; /*!< [1..0] reserved1 */ - __IOM uint32_t BYPASS_ULPTASS_PWRCTL_ULP_AON : 1; /*!< [2..2] Enables software based + __IOM unsigned int RES : 2; /*!< [1..0] reserved1 */ + __IOM unsigned int BYPASS_ULPTASS_PWRCTL_ULP_AON : 1; /*!< [2..2] Enables software based control of output isolation for ULPTASS AON */ __IOM - uint32_t BYPASS_ULPSDCSS_PWRCTRL_ULP_AON : 1; /*!< [3..3] Enables software + unsigned int BYPASS_ULPSDCSS_PWRCTRL_ULP_AON : 1; /*!< [3..3] Enables software based control of output isolation for ULPSDCSS AON */ - __IOM uint32_t RESERVED2 : 1; /*!< [4..4] reser */ - __IOM uint32_t BYPASS_ULPTASS_PWRCTL_ULP_MISC : 1; /*!< [5..5] Enables software based + __IOM unsigned int RESERVED2 : 1; /*!< [4..4] reser */ + __IOM unsigned int BYPASS_ULPTASS_PWRCTL_ULP_MISC : 1; /*!< [5..5] Enables software based control of output isolation for ULP MISC */ - __IOM uint32_t BYPASS_ULPTASS_PWRCTL_ULP_CAP : 1; /*!< [6..6] Enables software based + __IOM unsigned int BYPASS_ULPTASS_PWRCTL_ULP_CAP : 1; /*!< [6..6] Enables software based control of output isolation for ULP CAP */ - __IOM uint32_t BYPASS_ULPTASS_PWRCTL_ULP_VAD : 1; /*!< [7..7] Enables software based + __IOM unsigned int BYPASS_ULPTASS_PWRCTL_ULP_VAD : 1; /*!< [7..7] Enables software based control of output isolation for ULP VAD */ - __IOM uint32_t BYPASS_ULPTASS_PWRCTL_ULP_UART : 1; /*!< [8..8] Enables software based + __IOM unsigned int BYPASS_ULPTASS_PWRCTL_ULP_UART : 1; /*!< [8..8] Enables software based control of output isolation for ULP UART */ - __IOM uint32_t BYPASS_ULPTASS_PWRCTL_ULP_SSI : 1; /*!< [9..9] Enables software based + __IOM unsigned int BYPASS_ULPTASS_PWRCTL_ULP_SSI : 1; /*!< [9..9] Enables software based control of output isolation for ULP SSI */ - __IOM uint32_t BYPASS_ULPTASS_PWRCTL_ULP_I2S : 1; /*!< [10..10] Enables software + __IOM unsigned int BYPASS_ULPTASS_PWRCTL_ULP_I2S : 1; /*!< [10..10] Enables software based control of output isolation for ULP I2S */ - __IOM uint32_t BYPASS_ULPTASS_PWRCTL_ULP_I2C : 1; /*!< [11..11] Enables software + __IOM unsigned int BYPASS_ULPTASS_PWRCTL_ULP_I2C : 1; /*!< [11..11] Enables software based control of output isolation for ULP I2C */ - __IOM uint32_t BYPASS_ULPTASS_PWRCTL_ULP_AUX : 1; /*!< [12..12] Enables software + __IOM unsigned int BYPASS_ULPTASS_PWRCTL_ULP_AUX : 1; /*!< [12..12] Enables software based control of output isolation for ULP AUX */ - __IOM uint32_t BYPASS_ULPTASS_PWRCTL_ULP_IR : 1; /*!< [13..13] Enables software based + __IOM unsigned int BYPASS_ULPTASS_PWRCTL_ULP_IR : 1; /*!< [13..13] Enables software based control of output isolation for ULP IR */ - __IOM uint32_t BYPASS_ULPTASS_PWRCTL_ULP_UDMA : 1; /*!< [14..14] Enables software + __IOM unsigned int BYPASS_ULPTASS_PWRCTL_ULP_UDMA : 1; /*!< [14..14] Enables software based control of output isolation for ULP UDMA */ - __IOM uint32_t BYPASS_ULPTASS_PWRCTL_ULP_FIM : 1; /*!< [15..15] Enables software + __IOM unsigned int BYPASS_ULPTASS_PWRCTL_ULP_FIM : 1; /*!< [15..15] Enables software based control of output isolation for ULP FIM */ - __IOM uint32_t RESERVED3 : 3; /*!< [18..16] reserved1 */ - __IOM uint32_t BYPASS_ULPTASS_PWRCTL_ULP_SRAM : 4; /*!< [22..19] Enables software + __IOM unsigned int RESERVED3 : 3; /*!< [18..16] reserved1 */ + __IOM unsigned int BYPASS_ULPTASS_PWRCTL_ULP_SRAM : 4; /*!< [22..19] Enables software based control of output isolation for ULPTASS SRAM */ - __IOM uint32_t RESERVED4 : 9; /*!< [31..23] reserved1 */ + __IOM unsigned int RESERVED4 : 9; /*!< [31..23] reserved1 */ } ULPSS_BYPASS_PWRCTRL_REG_b; }; union { - __IOM uint32_t ULPSS_PWRCTRL_SET_REG; /*!< (@ 0x00000044) ULPSS power + __IOM unsigned int ULPSS_PWRCTRL_SET_REG; /*!< (@ 0x00000044) ULPSS power control set register */ struct { - __IOM uint32_t RES : 18; /*!< [17..0] reserved1 */ - __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_MISC : 1; /*!< [18..18] Functional + __IOM unsigned int RES : 18; /*!< [17..0] reserved1 */ + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_MISC : 1; /*!< [18..18] Functional Control signal for ULPTASS MISC */ - __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_CAP : 1; /*!< [19..19] Functional Control + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_CAP : 1; /*!< [19..19] Functional Control signal for ULPTASS CAP */ - __IOM uint32_t RESERVED2 : 1; /*!< [20..20] reserved2 */ - __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_UART : 1; /*!< [21..21] Functional + __IOM unsigned int RESERVED2 : 1; /*!< [20..20] reserved2 */ + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_UART : 1; /*!< [21..21] Functional Control signal for ULPTASS UART */ - __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_SSI : 1; /*!< [22..22] Functional Control + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_SSI : 1; /*!< [22..22] Functional Control signal for ULPTASS SSI */ - __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_I2S : 1; /*!< [23..23] Functional Control + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_I2S : 1; /*!< [23..23] Functional Control signal for ULPTASS I2S */ - __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_I2C : 1; /*!< [24..24] Functional Control + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_I2C : 1; /*!< [24..24] Functional Control signal for ULPTASS I2C */ - __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_AUX : 1; /*!< [25..25] Functional Control + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_AUX : 1; /*!< [25..25] Functional Control signal for ULPTASS AUX */ - __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_IR : 1; /*!< [26..26] Functional Control + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_IR : 1; /*!< [26..26] Functional Control signal for ULPTASS IR */ - __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_UDMA : 1; /*!< [27..27] Functional + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_UDMA : 1; /*!< [27..27] Functional Control signal for ULPTASS UDMA */ - __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_FIM : 1; /*!< [28..28] Functional Control + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_FIM : 1; /*!< [28..28] Functional Control signal for ULPTASS FIM */ - __IOM uint32_t RESERVED3 : 3; /*!< [31..29] RESERVED3 */ + __IOM unsigned int RESERVED3 : 3; /*!< [31..29] RESERVED3 */ } ULPSS_PWRCTRL_SET_REG_b; }; union { - __IOM uint32_t ULPSS_PWRCTRL_CLEAR_REG; /*!< (@ 0x00000048) ULPSS power + __IOM unsigned int ULPSS_PWRCTRL_CLEAR_REG; /*!< (@ 0x00000048) ULPSS power control clear register */ struct { - __IOM uint32_t RESERVED1 : 18; /*!< [17..0] reserved1 */ - __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_MISC : 1; /*!< [18..18] Functional + __IOM unsigned int RESERVED1 : 18; /*!< [17..0] reserved1 */ + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_MISC : 1; /*!< [18..18] Functional Control signal for ULPTASS MISC */ - __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_CAP : 1; /*!< [19..19] Functional Control + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_CAP : 1; /*!< [19..19] Functional Control signal for ULPTASS CAP */ - __IOM uint32_t RESERVED2 : 1; /*!< [20..20] reserved2 */ - __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_UART : 1; /*!< [21..21] Functional + __IOM unsigned int RESERVED2 : 1; /*!< [20..20] reserved2 */ + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_UART : 1; /*!< [21..21] Functional Control signal for ULPTASS UART */ - __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_SSI : 1; /*!< [22..22] Functional Control + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_SSI : 1; /*!< [22..22] Functional Control signal for ULPTASS SSI */ - __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_I2S : 1; /*!< [23..23] Functional Control + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_I2S : 1; /*!< [23..23] Functional Control signal for ULPTASS I2S */ - __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_I2C : 1; /*!< [24..24] Functional Control + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_I2C : 1; /*!< [24..24] Functional Control signal for ULPTASS I2C */ - __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_AUX : 1; /*!< [25..25] Functional Control + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_AUX : 1; /*!< [25..25] Functional Control signal for ULPTASS AUX */ - __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_IR : 1; /*!< [26..26] Functional Control + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_IR : 1; /*!< [26..26] Functional Control signal for ULPTASS IR */ - __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_UDMA : 1; /*!< [27..27] Functional + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_UDMA : 1; /*!< [27..27] Functional Control signal for ULPTASS UDMA */ - __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_FIM : 1; /*!< [28..28] Functional Control + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_FIM : 1; /*!< [28..28] Functional Control signal for ULPTASS FIM */ - __IOM uint32_t RESERVED3 : 3; /*!< [31..29] RESERVED3 */ + __IOM unsigned int RESERVED3 : 3; /*!< [31..29] RESERVED3 */ } ULPSS_PWRCTRL_CLEAR_REG_b; }; union { - __IOM uint32_t ULPSS_RAM_PWRCTRL_SET_REG1; /*!< (@ 0x0000004C) ULPSS ram power control + __IOM unsigned int ULPSS_RAM_PWRCTRL_SET_REG1; /*!< (@ 0x0000004C) ULPSS ram power control set register1 */ struct { - __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_SRAM : 4; /*!< [3..0] Functional Control + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_SRAM : 4; /*!< [3..0] Functional Control signal for ULPSS SRAM pins */ - __IOM uint32_t RESERVED1 : 28; /*!< [31..4] reserved1 */ + __IOM unsigned int RESERVED1 : 28; /*!< [31..4] reserved1 */ } ULPSS_RAM_PWRCTRL_SET_REG1_b; }; union { - __IOM uint32_t ULPSS_RAM_PWRCTRL_CLEAR_REG1; /*!< (@ 0x00000050) ULPSS ram power + __IOM unsigned int ULPSS_RAM_PWRCTRL_CLEAR_REG1; /*!< (@ 0x00000050) ULPSS ram power control clear register1 */ struct { - __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_SRAM : 4; /*!< [3..0] Functional Control + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_SRAM : 4; /*!< [3..0] Functional Control signal for ULPSS SRAM pins */ - __IOM uint32_t RESERVED1 : 28; /*!< [31..4] reserved1 */ + __IOM unsigned int RESERVED1 : 28; /*!< [31..4] reserved1 */ } ULPSS_RAM_PWRCTRL_CLEAR_REG1_b; }; union { - __IOM uint32_t ULPSS_RAM_PWRCTRL_SET_REG2; /*!< (@ 0x00000054) ULPSS ram power control + __IOM unsigned int ULPSS_RAM_PWRCTRL_SET_REG2; /*!< (@ 0x00000054) ULPSS ram power control set register2 */ struct { - __IOM uint32_t ULPTASS_SRAM_INPUT_DISABLE_ISOLATION_ULP : 4; /*!< [3..0] Input + __IOM unsigned int ULPTASS_SRAM_INPUT_DISABLE_ISOLATION_ULP : 4; /*!< [3..0] Input isolation control for ULPTASS SRAM */ - __IOM uint32_t RESERVED1 : 12; /*!< [15..4] reserved1 */ - __IOM uint32_t SRAM_DS_ULP_PROC_1 : 4; /*!< [19..16] Deep-Sleep control + __IOM unsigned int RESERVED1 : 12; /*!< [15..4] reserved1 */ + __IOM unsigned int SRAM_DS_ULP_PROC_1 : 4; /*!< [19..16] Deep-Sleep control for ULPTASS SRAM */ - __IOM uint32_t RESERVED2 : 12; /*!< [31..20] reserved1 */ + __IOM unsigned int RESERVED2 : 12; /*!< [31..20] reserved1 */ } ULPSS_RAM_PWRCTRL_SET_REG2_b; }; union { - __IOM uint32_t ULPSS_RAM_PWRCTRL_CLEAR_REG2; /*!< (@ 0x00000058) ULPSS ram power + __IOM unsigned int ULPSS_RAM_PWRCTRL_CLEAR_REG2; /*!< (@ 0x00000058) ULPSS ram power control clear register2 */ struct { - __IOM uint32_t ULPTASS_SRAM_INPUT_DISABLE_ISOLATION_ULP : 4; /*!< [3..0] Input + __IOM unsigned int ULPTASS_SRAM_INPUT_DISABLE_ISOLATION_ULP : 4; /*!< [3..0] Input isolation control for ULPTASS SRAM */ - __IOM uint32_t RESERVED1 : 12; /*!< [15..4] reserved1 */ - __IOM uint32_t SRAM_DS_ULP_PROC_1 : 4; /*!< [19..16] Deep-Sleep control + __IOM unsigned int RESERVED1 : 12; /*!< [15..4] reserved1 */ + __IOM unsigned int SRAM_DS_ULP_PROC_1 : 4; /*!< [19..16] Deep-Sleep control for ULPTASS SRAM */ - __IOM uint32_t RESERVED2 : 12; /*!< [31..20] reserved1 */ + __IOM unsigned int RESERVED2 : 12; /*!< [31..20] reserved1 */ } ULPSS_RAM_PWRCTRL_CLEAR_REG2_b; }; union { - __IOM uint32_t ULPSS_RAM_PWRCTRL_SET_REG3; /*!< (@ 0x0000005C) ULPSS ram power control + __IOM unsigned int ULPSS_RAM_PWRCTRL_SET_REG3; /*!< (@ 0x0000005C) ULPSS ram power control set register3 */ struct { - __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_SRAM_PERI_1 : 4; /*!< [3..0] Functional + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_SRAM_PERI_1 : 4; /*!< [3..0] Functional Control signal for ULPTASS SRAM Dual Rail pins */ - __IOM uint32_t RES : 28; /*!< [31..4] reserved1 */ + __IOM unsigned int RES : 28; /*!< [31..4] reserved1 */ } ULPSS_RAM_PWRCTRL_SET_REG3_b; }; union { - __IOM uint32_t ULPSS_RAM_PWRCTRL_CLEAR_REG3; /*!< (@ 0x00000060) ULPSS ram power + __IOM unsigned int ULPSS_RAM_PWRCTRL_CLEAR_REG3; /*!< (@ 0x00000060) ULPSS ram power control clear register3 */ struct { - __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_SRAM_PERI_1 : 4; /*!< [3..0] Functional + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_SRAM_PERI_1 : 4; /*!< [3..0] Functional Control signal for ULPTASS SRAM Dual Rail pins */ - __IOM uint32_t RES : 28; /*!< [31..4] reserved1 */ + __IOM unsigned int RES : 28; /*!< [31..4] reserved1 */ } ULPSS_RAM_PWRCTRL_CLEAR_REG3_b; }; union { - __IOM uint32_t MCU_FSM_CTRL_BYPASS; /*!< (@ 0x00000064) MCU FSM control + __IOM unsigned int MCU_FSM_CTRL_BYPASS; /*!< (@ 0x00000064) MCU FSM control bypass register */ struct { - __IOM uint32_t MCU_XTAL_EN_40MHZ_BYPASS_CTRL : 1; /*!< [0..0] Xtal 40mhz enable + __IOM unsigned int MCU_XTAL_EN_40MHZ_BYPASS_CTRL : 1; /*!< [0..0] Xtal 40mhz enable bypass from MCU */ - __IOM uint32_t MCU_XTAL_EN_40MHZ_BYPASS : 1; /*!< [1..1] Value of Xtal + __IOM unsigned int MCU_XTAL_EN_40MHZ_BYPASS : 1; /*!< [1..1] Value of Xtal Enable in bypass mode */ - __IOM uint32_t MCU_PMU_SHUT_DOWN_BYPASS_CTRL : 1; /*!< [2..2] Enable bypass mode to + __IOM unsigned int MCU_PMU_SHUT_DOWN_BYPASS_CTRL : 1; /*!< [2..2] Enable bypass mode to Control pmu shut down */ - __IOM uint32_t MCU_PMU_SHUT_DOWN_BYPASS : 1; /*!< [3..3] Value of pmu shutdown in + __IOM unsigned int MCU_PMU_SHUT_DOWN_BYPASS : 1; /*!< [3..3] Value of pmu shutdown in bypass mode */ - __IOM uint32_t MCU_BUCK_BOOST_ENABLE_BYPASS_CTRL : 1; /*!< [4..4] Enable software + __IOM unsigned int MCU_BUCK_BOOST_ENABLE_BYPASS_CTRL : 1; /*!< [4..4] Enable software control for buck boost enable */ - __IOM uint32_t MCU_BUCK_BOOST_ENABLE_BYPASS : 1; /*!< [5..5] Value for MCU BuckBoost + __IOM unsigned int MCU_BUCK_BOOST_ENABLE_BYPASS : 1; /*!< [5..5] Value for MCU BuckBoost Enable in bypass mode */ - __IOM uint32_t RES : 26; /*!< [31..6] reserved1 */ + __IOM unsigned int RES : 26; /*!< [31..6] reserved1 */ } MCU_FSM_CTRL_BYPASS_b; }; union { - __IOM uint32_t MCU_PMU_LDO_CTRL_SET; /*!< (@ 0x00000068) MCU PMU LD0 control + __IOM unsigned int MCU_PMU_LDO_CTRL_SET; /*!< (@ 0x00000068) MCU PMU LD0 control set register */ struct { - __IOM uint32_t MCU_FLASH_LDO_EN : 1; /*!< [0..0] Enable Flash LDO from M4SS */ - __IOM uint32_t MCU_SCO_LDO_EN : 1; /*!< [1..1] Enable SoC LDO from M4SS */ - __IOM uint32_t MCU_DCDC_EN : 1; /*!< [2..2] Enable PMU DCDC from M4SS */ - __IOM uint32_t RESER : 14; /*!< [16..3] reserved1 */ - __IOM uint32_t MCU_SOC_LDO_LVL : 1; /*!< [17..17] PMU SOC LDO High and Low + __IOM unsigned int MCU_FLASH_LDO_EN : 1; /*!< [0..0] Enable Flash LDO from M4SS */ + __IOM unsigned int MCU_SCO_LDO_EN : 1; /*!< [1..1] Enable SoC LDO from M4SS */ + __IOM unsigned int MCU_DCDC_EN : 1; /*!< [2..2] Enable PMU DCDC from M4SS */ + __IOM unsigned int RESER : 14; /*!< [16..3] reserved1 */ + __IOM unsigned int MCU_SOC_LDO_LVL : 1; /*!< [17..17] PMU SOC LDO High and Low Voltage selection */ - __IOM uint32_t MCU_DCDC_LVL : 1; /*!< [18..18] PMU DCDC High and Low + __IOM unsigned int MCU_DCDC_LVL : 1; /*!< [18..18] PMU DCDC High and Low Voltage selection */ - __IOM uint32_t RES : 13; /*!< [31..19] reserved1 */ + __IOM unsigned int RES : 13; /*!< [31..19] reserved1 */ } MCU_PMU_LDO_CTRL_SET_b; }; union { - __IOM uint32_t MCU_PMU_LDO_CTRL_CLEAR; /*!< (@ 0x0000006C) MCU PMU LD0 + __IOM unsigned int MCU_PMU_LDO_CTRL_CLEAR; /*!< (@ 0x0000006C) MCU PMU LD0 control clear register */ struct { - __IOM uint32_t MCU_FLASH_LDO_EN : 1; /*!< [0..0] Enable Flash LDO from M4SS */ - __IOM uint32_t MCU_SOC_LDO_EN : 1; /*!< [1..1] Enable SoC LDO from M4SS */ - __IOM uint32_t MCU_DCDC_EN : 1; /*!< [2..2] Enable PMU DCDC from M4SS */ - __IOM uint32_t RESER : 14; /*!< [16..3] reserved1 */ - __IOM uint32_t MCU_SOC_LDO_LVL : 1; /*!< [17..17] PMU SOC LDO High and Low + __IOM unsigned int MCU_FLASH_LDO_EN : 1; /*!< [0..0] Enable Flash LDO from M4SS */ + __IOM unsigned int MCU_SOC_LDO_EN : 1; /*!< [1..1] Enable SoC LDO from M4SS */ + __IOM unsigned int MCU_DCDC_EN : 1; /*!< [2..2] Enable PMU DCDC from M4SS */ + __IOM unsigned int RESER : 14; /*!< [16..3] reserved1 */ + __IOM unsigned int MCU_SOC_LDO_LVL : 1; /*!< [17..17] PMU SOC LDO High and Low Voltage selection */ - __IOM uint32_t MCU_DCDC_LVL : 1; /*!< [18..18] PMU DCDC High and Low + __IOM unsigned int MCU_DCDC_LVL : 1; /*!< [18..18] PMU DCDC High and Low Voltage selection */ - __IOM uint32_t RES : 13; /*!< [31..19] reserved1 */ + __IOM unsigned int RES : 13; /*!< [31..19] reserved1 */ } MCU_PMU_LDO_CTRL_CLEAR_b; }; - __IM uint32_t RESERVED1[4]; + __IM unsigned int RESERVED1[4]; union { - __IOM uint32_t PLLCCI_PWRCTRL_REG; /*!< (@ 0x00000080) PLL CCI power control + __IOM unsigned int PLLCCI_PWRCTRL_REG; /*!< (@ 0x00000080) PLL CCI power control register */ struct { - __IOM uint32_t I2SPLL_ISO_EN : 1; /*!< [0..0] Enables software based control of + __IOM unsigned int I2SPLL_ISO_EN : 1; /*!< [0..0] Enables software based control of isolation and reset for I2SPLL */ - __IOM uint32_t I2SPLL_BYPASS_ISO_GEN : 1; /*!< [1..1] Isolation value */ - __IOM uint32_t INTFPLL_ISO_EN : 1; /*!< [2..2] Enables software based control of + __IOM unsigned int I2SPLL_BYPASS_ISO_GEN : 1; /*!< [1..1] Isolation value */ + __IOM unsigned int INTFPLL_ISO_EN : 1; /*!< [2..2] Enables software based control of isolation and reset for INTF PLL */ - __IOM uint32_t INTFPLL_BYPASS_ISO_GEN : 1; /*!< [3..3] Isolation value */ - __IOM uint32_t SOCPLL_ISO_ENABLE : 1; /*!< [4..4] Enables software based control of + __IOM unsigned int INTFPLL_BYPASS_ISO_GEN : 1; /*!< [3..3] Isolation value */ + __IOM unsigned int SOCPLL_ISO_ENABLE : 1; /*!< [4..4] Enables software based control of isolation and reset for SOCPLL */ - __IOM uint32_t SOCPLL_BYPASS_ISO_GEN : 1; /*!< [5..5] Isolation value */ - __IOM uint32_t SOCPLL_SPI_PG_EN : 1; /*!< [6..6] SOCPLL SPI Power Control */ - __IOM uint32_t SOCPLL_VDD13_ISO_EN : 1; /*!< [7..7] SOCPLL MACRO POC Control */ - __IOM uint32_t RES : 24; /*!< [31..8] reserved1 */ + __IOM unsigned int SOCPLL_BYPASS_ISO_GEN : 1; /*!< [5..5] Isolation value */ + __IOM unsigned int SOCPLL_SPI_PG_EN : 1; /*!< [6..6] SOCPLL SPI Power Control */ + __IOM unsigned int SOCPLL_VDD13_ISO_EN : 1; /*!< [7..7] SOCPLL MACRO POC Control */ + __IOM unsigned int RES : 24; /*!< [31..8] reserved1 */ } PLLCCI_PWRCTRL_REG_b; }; union { - __IOM uint32_t DLL_PWRCTRL_REG; /*!< (@ 0x00000084) DLL power control register */ + __IOM unsigned int DLL_PWRCTRL_REG; /*!< (@ 0x00000084) DLL power control register */ struct { - __IOM uint32_t QSPI_DLL_RX_ISO_ENABLE : 1; /*!< [0..0] Enables software based control + __IOM unsigned int QSPI_DLL_RX_ISO_ENABLE : 1; /*!< [0..0] Enables software based control of isolation and reset for QSPI_DLL_TX */ - __IOM uint32_t QSPI_DLL_RX_BYPASS_ISO_GEN : 1; /*!< [1..1] Isolation value */ - __IOM uint32_t QSPI_DLL_RX_PG_EN_N : 1; /*!< [2..2] QPSI DLL RX Power Control */ - __IOM uint32_t RESER : 1; /*!< [3..3] reserved1 */ - __IOM uint32_t QSPI_DLL_TX_ISO_ENABLE : 1; /*!< [4..4] Enables software based control + __IOM unsigned int QSPI_DLL_RX_BYPASS_ISO_GEN : 1; /*!< [1..1] Isolation value */ + __IOM unsigned int QSPI_DLL_RX_PG_EN_N : 1; /*!< [2..2] QPSI DLL RX Power Control */ + __IOM unsigned int RESER : 1; /*!< [3..3] reserved1 */ + __IOM unsigned int QSPI_DLL_TX_ISO_ENABLE : 1; /*!< [4..4] Enables software based control of isolation and reset for QSPI_DLL_TX */ - __IOM uint32_t QSPI_DLL_TX_BYPASS_ISO_GEN : 1; /*!< [5..5] Isolation value */ - __IOM uint32_t QSPI_DLL_TX_PG_EN_N : 1; /*!< [6..6] QPSI DLL TX Power Control */ - __IOM uint32_t RESERVED1 : 25; /*!< [31..7] reserved1 */ + __IOM unsigned int QSPI_DLL_TX_BYPASS_ISO_GEN : 1; /*!< [5..5] Isolation value */ + __IOM unsigned int QSPI_DLL_TX_PG_EN_N : 1; /*!< [6..6] QPSI DLL TX Power Control */ + __IOM unsigned int RESERVED1 : 25; /*!< [31..7] reserved1 */ } DLL_PWRCTRL_REG_b; }; } BATT_FF_Type; /*!< Size = 136 (0x88) */ @@ -12395,130 +12395,130 @@ typedef struct { /*!< (@ 0x24048400) BATT_FF Structure */ typedef struct { /*!< (@ 0x24048100) MCU_FSM Structure */ union { - __IOM uint32_t MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE; /*!< (@ 0x00000000) Sleep Control + __IOM unsigned int MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE; /*!< (@ 0x00000000) Sleep Control Signals and Wakeup source selection */ struct { - __IOM uint32_t MCUFSM_SHUTDOWN_ENABLE : 1; /*!< [0..0] shutdown enable pulse. */ - __IOM uint32_t Reserved1 : 1; /*!< [1..1] It is recommended to write these + __IOM unsigned int MCUFSM_SHUTDOWN_ENABLE : 1; /*!< [0..0] shutdown enable pulse. */ + __IOM unsigned int Reserved1 : 1; /*!< [1..1] It is recommended to write these bits to 0. */ - __IOM uint32_t LP_SLEEP_MODE_b : 1; /*!< [2..2] setting this bit enables retention of + __IOM unsigned int LP_SLEEP_MODE_b : 1; /*!< [2..2] setting this bit enables retention of TASS-RAM, M4SS-RAM in PS2 Active/Sleep state */ - __IOM uint32_t M4SS_RAM_RETENTION_MODE_EN : 1; /*!< [3..3] shutdown enable + __IOM unsigned int M4SS_RAM_RETENTION_MODE_EN : 1; /*!< [3..3] shutdown enable pulse. */ - __IOM uint32_t M4ULP_RAM_RETENTION_MODE_EN_b : 1; /*!< [4..4] RAM retention enable + __IOM unsigned int M4ULP_RAM_RETENTION_MODE_EN_b : 1; /*!< [4..4] RAM retention enable for ULP M4 ram during deep sleep */ - __IOM uint32_t TA_RAM_RETENTION_MODE_EN : 1; /*!< [5..5] RAM retention enable for ta + __IOM unsigned int TA_RAM_RETENTION_MODE_EN : 1; /*!< [5..5] RAM retention enable for ta ram during deep sleep */ - __IOM uint32_t ULPSS_RAM_RETENTION_MODE_EN : 1; /*!< [6..6] RAM retention enable for + __IOM unsigned int ULPSS_RAM_RETENTION_MODE_EN : 1; /*!< [6..6] RAM retention enable for ulpss ram during deep sleep */ - __IOM uint32_t M4ULP_RAM16K_RETENTION_MODE_EN : 1; /*!< [7..7] To enable retention + __IOM unsigned int M4ULP_RAM16K_RETENTION_MODE_EN : 1; /*!< [7..7] To enable retention mode for m4ulp 16k RAM */ - __IOM uint32_t LDO_SOC_ON_b : 1; /*!< [8..8] ON ldo soc during deep sleep */ - __IOM uint32_t LDO_FLASH_ON_b : 1; /*!< [9..9] ON flash ldo during deep sleep */ - __IOM uint32_t PMU_DCDC_ON_b : 1; /*!< [10..10] 1: PMU DCDC(BUCK) ON,0: + __IOM unsigned int LDO_SOC_ON_b : 1; /*!< [8..8] ON ldo soc during deep sleep */ + __IOM unsigned int LDO_FLASH_ON_b : 1; /*!< [9..9] ON flash ldo during deep sleep */ + __IOM unsigned int PMU_DCDC_ON_b : 1; /*!< [10..10] 1: PMU DCDC(BUCK) ON,0: PMU DCDC(BUCK) OFF. */ - __IOM uint32_t SKIP_XTAL_WAIT_TIME : 1; /*!< [11..11] 1 : Skips Xtal Good + __IOM unsigned int SKIP_XTAL_WAIT_TIME : 1; /*!< [11..11] 1 : Skips Xtal Good Delay wait time. */ - __IOM uint32_t Reserved2 : 2; /*!< [13..12] It is recommended to write + __IOM unsigned int Reserved2 : 2; /*!< [13..12] It is recommended to write these bits to 0. */ - __IOM uint32_t MCUFSM_WAKEUP_NWPFSM : 1; /*!< [14..14] When Set, mcufsm wakeup enable + __IOM unsigned int MCUFSM_WAKEUP_NWPFSM : 1; /*!< [14..14] When Set, mcufsm wakeup enable will wakeup both NWP FSM and MCU FSM.Clear this BIT if this feature is not required.. */ - __IOM uint32_t SLEEP_WAKEUP : 1; /*!< [15..15] Wakeup indication from Processor */ - __IOM uint32_t TIMER_BASED_WAKEUP_b : 1; /*!< [16..16] wakeup enable after deep sleep + __IOM unsigned int SLEEP_WAKEUP : 1; /*!< [15..15] Wakeup indication from Processor */ + __IOM unsigned int TIMER_BASED_WAKEUP_b : 1; /*!< [16..16] wakeup enable after deep sleep counter elapses */ - __IOM uint32_t HOST_BASED_WAKEUP_b : 1; /*!< [17..17] host based wakeup enable */ - __IOM uint32_t WIRELESS_BASED_WAKEUP_b : 1; /*!< [18..18] wireless based + __IOM unsigned int HOST_BASED_WAKEUP_b : 1; /*!< [17..17] host based wakeup enable */ + __IOM unsigned int WIRELESS_BASED_WAKEUP_b : 1; /*!< [18..18] wireless based wakeup enable */ - __IOM uint32_t M4_PROC_BASED_WAKEUP_b : 1; /*!< [19..19] wakeup based on + __IOM unsigned int M4_PROC_BASED_WAKEUP_b : 1; /*!< [19..19] wakeup based on m4 processor enable */ - __IOM uint32_t GPIO_BASED_WAKEUP_b : 1; /*!< [20..20] wakeup on gpio interrupt enable + __IOM unsigned int GPIO_BASED_WAKEUP_b : 1; /*!< [20..20] wakeup on gpio interrupt enable based in configuration in GPIO WAKEUP REGISTER */ - __IOM uint32_t COMPR_BASED_WAKEUP_b : 1; /*!< [21..21] compartor based + __IOM unsigned int COMPR_BASED_WAKEUP_b : 1; /*!< [21..21] compartor based wakeup enable, either of any 6 comparator interrupts */ #ifdef SLI_SI917B0 - __IOM uint32_t SYSRTC_BASED_WAKEUP_b : 1; /*!< [22..22] SYSRTC Based Wakeup */ + __IOM unsigned int SYSRTC_BASED_WAKEUP_b : 1; /*!< [22..22] SYSRTC Based Wakeup */ #else - __IOM uint32_t Reserved3 : 1; /*!< [22..22] It is recommended to write + __IOM unsigned int Reserved3 : 1; /*!< [22..22] It is recommended to write these bits to 0. */ #endif - __IOM uint32_t WIC_BASED_WAKEUP_b : 1; /*!< [23..23] WIC based wakeup mask */ - __IOM uint32_t ULPSS_BASED_WAKEUP_b : 1; /*!< [24..24] ULPSS peripheral + __IOM unsigned int WIC_BASED_WAKEUP_b : 1; /*!< [23..23] WIC based wakeup mask */ + __IOM unsigned int ULPSS_BASED_WAKEUP_b : 1; /*!< [24..24] ULPSS peripheral based wakeup */ - __IOM uint32_t SDCSS_BASED_WAKEUP_b : 1; /*!< [25..25] Sensor Data + __IOM unsigned int SDCSS_BASED_WAKEUP_b : 1; /*!< [25..25] Sensor Data collector based wakeup */ - __IOM uint32_t ALARM_BASED_WAKEUP_b : 1; /*!< [26..26] Alarm Based wakeup */ - __IOM uint32_t SEC_BASED_WAKEUP_b : 1; /*!< [27..27] Second Pulse Based wakeup */ - __IOM uint32_t MSEC_BASED_WAKEUP_b : 1; /*!< [28..28] Millisecond Pulse + __IOM unsigned int ALARM_BASED_WAKEUP_b : 1; /*!< [26..26] Alarm Based wakeup */ + __IOM unsigned int SEC_BASED_WAKEUP_b : 1; /*!< [27..27] Second Pulse Based wakeup */ + __IOM unsigned int MSEC_BASED_WAKEUP_b : 1; /*!< [28..28] Millisecond Pulse Based wakeup */ - __IOM uint32_t WDT_INTR_BASED_WAKEUP_b : 1; /*!< [29..29] Millisecond + __IOM unsigned int WDT_INTR_BASED_WAKEUP_b : 1; /*!< [29..29] Millisecond Pulse Based wakeup */ - __IOM uint32_t ULPSS_BASED_SLEEP : 1; /*!< [30..30] ULPSS initiated DeepSleep. */ - __IOM uint32_t SDCSS_BASED_SLEEP : 1; /*!< [31..31] SDCSS initiated DeepSleep. */ + __IOM unsigned int ULPSS_BASED_SLEEP : 1; /*!< [30..30] ULPSS initiated DeepSleep. */ + __IOM unsigned int SDCSS_BASED_SLEEP : 1; /*!< [31..31] SDCSS initiated DeepSleep. */ } MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE_b; }; union { - __IOM uint32_t MCU_FSM_PERI_CONFIG_REG; /*!< (@ 0x00000004) Configuration + __IOM unsigned int MCU_FSM_PERI_CONFIG_REG; /*!< (@ 0x00000004) Configuration for Ultra Low-Power Mode of the processor (PS2 State) */ struct { - __IOM uint32_t ULP_MCU_MODE_EN : 1; /*!< [0..0] Enables voltage switching + __IOM unsigned int ULP_MCU_MODE_EN : 1; /*!< [0..0] Enables voltage switching for PS2-PS4/PS3 and PS4/PS3-PS2 state transitions. */ - __IOM uint32_t M4SS_CONTEXT_SWITCH_TOP_ULP_MODE : 2; /*!< [2..1] Enable functional + __IOM unsigned int M4SS_CONTEXT_SWITCH_TOP_ULP_MODE : 2; /*!< [2..1] Enable functional switching for PS2-PS4/PS3 and PS4/PS3-PS2 state transitions */ - __IOM uint32_t WICENREQ : 1; /*!< [3..3] Its enable or disable maximum of 32KB of + __IOM unsigned int WICENREQ : 1; /*!< [3..3] Its enable or disable maximum of 32KB of LP-SRAM for operation in PS2 state */ - __IOM uint32_t Reserved1 : 12; /*!< [15..4] It is recommended to write + __IOM unsigned int Reserved1 : 12; /*!< [15..4] It is recommended to write these bits to 0. */ - __IOM uint32_t BGPMU_SAMPLING_EN_R : 1; /*!< [16..16] Controls the mode of Band-Gap + __IOM unsigned int BGPMU_SAMPLING_EN_R : 1; /*!< [16..16] Controls the mode of Band-Gap for DC-DC 1.35 during PS2 state. */ - __IOM uint32_t Reserved2 : 15; /*!< [31..17] It is recommended to write + __IOM unsigned int Reserved2 : 15; /*!< [31..17] It is recommended to write these bits to 0. */ } MCU_FSM_PERI_CONFIG_REG_b; }; union { - __IOM uint32_t GPIO_WAKEUP_REGISTER; /*!< (@ 0x00000008) GPIO Wakeup Register */ + __IOM unsigned int GPIO_WAKEUP_REGISTER; /*!< (@ 0x00000008) GPIO Wakeup Register */ struct { - __IOM uint32_t GPIO_0_WAKEUP : 1; /*!< [0..0] Enable gpio 0 based wakeup. */ - __IOM uint32_t GPIO_1_WAKEUP : 1; /*!< [1..1] Enable gpio 1 based wakeup */ - __IOM uint32_t GPIO_2_WAKEUP : 1; /*!< [2..2] Enable gpio 2 based wakeup */ - __IOM uint32_t GPIO_3_WAKEUP : 1; /*!< [3..3] Enable gpio 3 based wakeup */ - __IOM uint32_t GPIO_4_WAKEUP : 1; /*!< [4..4] Enable gpio 3 based wakeup */ - __IOM uint32_t Reserved1 : 11; /*!< [15..5] It is recommended to write + __IOM unsigned int GPIO_0_WAKEUP : 1; /*!< [0..0] Enable gpio 0 based wakeup. */ + __IOM unsigned int GPIO_1_WAKEUP : 1; /*!< [1..1] Enable gpio 1 based wakeup */ + __IOM unsigned int GPIO_2_WAKEUP : 1; /*!< [2..2] Enable gpio 2 based wakeup */ + __IOM unsigned int GPIO_3_WAKEUP : 1; /*!< [3..3] Enable gpio 3 based wakeup */ + __IOM unsigned int GPIO_4_WAKEUP : 1; /*!< [4..4] Enable gpio 3 based wakeup */ + __IOM unsigned int Reserved1 : 11; /*!< [15..5] It is recommended to write these bits to 0. */ - __IOM uint32_t CONTINIOUS_START : 1; /*!< [16..16] Trigger Deep sleep + __IOM unsigned int CONTINIOUS_START : 1; /*!< [16..16] Trigger Deep sleep timer to start counting. */ - __IOM uint32_t CONTINIOUS_TIMER_ENABLE : 1; /*!< [17..17] Enable Deep sleep timer + __IOM unsigned int CONTINIOUS_TIMER_ENABLE : 1; /*!< [17..17] Enable Deep sleep timer mode continuous. */ - __IOM uint32_t DS_TIMER_SOFT_RESET : 1; /*!< [18..18] Enable Deep sleep + __IOM unsigned int DS_TIMER_SOFT_RESET : 1; /*!< [18..18] Enable Deep sleep timer mode continuous. */ - __IOM uint32_t Reserved2 : 13; /*!< [31..19] It is recommended to write + __IOM unsigned int Reserved2 : 13; /*!< [31..19] It is recommended to write these bits to 0. */ } GPIO_WAKEUP_REGISTER_b; }; union { - __IOM uint32_t MCU_FSM_DEEP_SLEEP_DURATION_LSB_REG; /*!< (@ 0x0000000C) MCU FSM DEEP + __IOM unsigned int MCU_FSM_DEEP_SLEEP_DURATION_LSB_REG; /*!< (@ 0x0000000C) MCU FSM DEEP SLEEP DURATION LSB Register */ struct { __IOM - uint32_t MCUFSM_DEEPSLEEP_DURATION_COUNT : 32; /*!< [31..0] LSB bits of + unsigned int MCUFSM_DEEPSLEEP_DURATION_COUNT : 32; /*!< [31..0] LSB bits of deep sleep duration counter after which system wakes up is @@ -12528,425 +12528,425 @@ typedef struct { /*!< (@ 0x24048100) MCU_FSM Structure */ }; union { - __IOM uint32_t MCU_FSM_XTAL_AND_PMU_GOOD_COUNT_REG; /*!< (@ 0x00000010) MCU FSM XTAL + __IOM unsigned int MCU_FSM_XTAL_AND_PMU_GOOD_COUNT_REG; /*!< (@ 0x00000010) MCU FSM XTAL AND PMU GOOD COUNT Register */ struct { - __IOM uint32_t MCUFSM_PMU_POWERGOOD_DURATION_COUNT : 7; /*!< [6..0] Wait Delay for + __IOM unsigned int MCUFSM_PMU_POWERGOOD_DURATION_COUNT : 7; /*!< [6..0] Wait Delay for PMU POWER GOOD 0 - 5us 1 - 10us 2 - 12.5us 3 - 25us 4 - 50us 5 - 75us. */ - __IOM uint32_t Reserved1 : 9; /*!< [15..7] It is recommended to write + __IOM unsigned int Reserved1 : 9; /*!< [15..7] It is recommended to write these bits to 0. */ - __IOM uint32_t MCUFSM_XTAL_GOODTIME_DURATION_COUNT : 7; /*!< [22..16] Wait Delay for + __IOM unsigned int MCUFSM_XTAL_GOODTIME_DURATION_COUNT : 7; /*!< [22..16] Wait Delay for XTAL GOOD Time 0 - 5us 1 - 10us. */ - __IOM uint32_t Reserved2 : 9; /*!< [31..23] It is recommended to write + __IOM unsigned int Reserved2 : 9; /*!< [31..23] It is recommended to write these bits to 0. */ } MCU_FSM_XTAL_AND_PMU_GOOD_COUNT_REG_b; }; union { - __IOM uint32_t MCU_FSM_POWER_CTRL_AND_DELAY; /*!< (@ 0x00000014) Power Control and + __IOM unsigned int MCU_FSM_POWER_CTRL_AND_DELAY; /*!< (@ 0x00000014) Power Control and Delay Configuration for Ultra Low-Power Mode of the processor (PS2 State) */ struct { - __IOM uint32_t PS2_PMU_LDO_OFF_DELAY : 5; /*!< [4..0] PMU BUCK And LDO + __IOM unsigned int PS2_PMU_LDO_OFF_DELAY : 5; /*!< [4..0] PMU BUCK And LDO Turn-OFF Delay. */ - __IOM uint32_t Reserved1 : 3; /*!< [7..5] It is recommended to write these + __IOM unsigned int Reserved1 : 3; /*!< [7..5] It is recommended to write these bits to 0. */ - __IOM uint32_t PS4_SOCLDO_ON_DELAY : 4; /*!< [11..8] PMU SOCLDO Turn-ON Delay. */ - __IOM uint32_t PG4_BUCK_ON_DELAY : 4; /*!< [15..12] PMU Buck Turn-ON Delay. */ - __IOM uint32_t FSM_PERI_SOC_LDO_EN : 1; /*!< [16..16] Enable SOCLDO in + __IOM unsigned int PS4_SOCLDO_ON_DELAY : 4; /*!< [11..8] PMU SOCLDO Turn-ON Delay. */ + __IOM unsigned int PG4_BUCK_ON_DELAY : 4; /*!< [15..12] PMU Buck Turn-ON Delay. */ + __IOM unsigned int FSM_PERI_SOC_LDO_EN : 1; /*!< [16..16] Enable SOCLDO in Peri mode. */ - __IOM uint32_t FSM_PERI_DCDC_EN : 1; /*!< [17..17] Enable DCDC in Peri mode. */ - __IOM uint32_t Reserved2 : 1; /*!< [18..18] It is recommended to write + __IOM unsigned int FSM_PERI_DCDC_EN : 1; /*!< [17..17] Enable DCDC in Peri mode. */ + __IOM unsigned int Reserved2 : 1; /*!< [18..18] It is recommended to write these bits to 0. */ - __IOM uint32_t POWER_MUX_SEL_ULPSS : 1; /*!< [19..19] Select value for + __IOM unsigned int POWER_MUX_SEL_ULPSS : 1; /*!< [19..19] Select value for ULPSS(Peripherals) Power Mux */ - __IOM uint32_t POWER_MUX_SEL_M4_ULP : 2; /*!< [21..20] Select value for M4 + __IOM unsigned int POWER_MUX_SEL_M4_ULP : 2; /*!< [21..20] Select value for M4 ULP (Peripherals + Cortex Core )Power Mux. */ - __IOM uint32_t POWER_MUX_SEL_M4_ULP_RAM_16K : 2; /*!< [23..22] Select value for M4 + __IOM unsigned int POWER_MUX_SEL_M4_ULP_RAM_16K : 2; /*!< [23..22] Select value for M4 ULP RAM 16K Power Mux */ - __IOM uint32_t POWER_MUX_SEL_M4_ULP_RAM : 2; /*!< [25..24] Select value for M4 ULP + __IOM unsigned int POWER_MUX_SEL_M4_ULP_RAM : 2; /*!< [25..24] Select value for M4 ULP RAM Power Mux. */ - __IOM uint32_t POWER_MUX_SEL_ULPSS_RAM : 2; /*!< [27..26] Select value for + __IOM unsigned int POWER_MUX_SEL_ULPSS_RAM : 2; /*!< [27..26] Select value for ULPSS RAM Power Mux. */ - __IOM uint32_t Reserved3 : 4; /*!< [31..28] It is recommended to write + __IOM unsigned int Reserved3 : 4; /*!< [31..28] It is recommended to write these bits to 0. */ } MCU_FSM_POWER_CTRL_AND_DELAY_b; }; union { - __IOM uint32_t MCU_FSM_CLKS_REG; /*!< (@ 0x00000018) MCU FSM Clocks Register */ + __IOM unsigned int MCU_FSM_CLKS_REG; /*!< (@ 0x00000018) MCU FSM Clocks Register */ struct { - __IOM uint32_t Reserved1 : 2; /*!< [1..0] It is recommended to write these + __IOM unsigned int Reserved1 : 2; /*!< [1..0] It is recommended to write these bits to 0. */ - __IOM uint32_t HF_FSM_CLK_SELECT : 3; /*!< [4..2] Disable signal for m4ss + __IOM unsigned int HF_FSM_CLK_SELECT : 3; /*!< [4..2] Disable signal for m4ss reference clock. */ - __IOM uint32_t Reserved2 : 10; /*!< [14..5] It is recommended to write + __IOM unsigned int Reserved2 : 10; /*!< [14..5] It is recommended to write these bits to 0. */ - __IOM uint32_t HF_FSM_CLK_SWITCHED_SYNC : 1; /*!< [15..15] If high freq fsm clock + __IOM unsigned int HF_FSM_CLK_SWITCHED_SYNC : 1; /*!< [15..15] If high freq fsm clock select is modified. */ - __IOM uint32_t HF_FSM_CLK_FREQ : 6; /*!< [21..16] High Frequency Source + __IOM unsigned int HF_FSM_CLK_FREQ : 6; /*!< [21..16] High Frequency Source Clock value in MHz. */ - __IOM uint32_t US_DIV_COUNT : 2; /*!< [23..22] One Micro second division factor. + __IOM unsigned int US_DIV_COUNT : 2; /*!< [23..22] One Micro second division factor. Program value to 3. If hf_fsm_gen_2mhz is 0 Program value to 1. If hf_fsm_gen_2mhz is 1. */ - __IOM uint32_t HF_FSM_GEN_2MHZ : 1; /*!< [24..24] Enable 2Mhz clock for FSM 1 -Enable + __IOM unsigned int HF_FSM_GEN_2MHZ : 1; /*!< [24..24] Enable 2Mhz clock for FSM 1 -Enable 2Mhz option 0- Enable 4MHz option. */ - __IOM uint32_t HF_FSM_CLK_EN : 1; /*!< [25..25] high frequency mcu fsm + __IOM unsigned int HF_FSM_CLK_EN : 1; /*!< [25..25] high frequency mcu fsm clock enable. */ - __IOM uint32_t Reserved3 : 6; /*!< [31..26] It is recommended to write + __IOM unsigned int Reserved3 : 6; /*!< [31..26] It is recommended to write these bits to 0. */ } MCU_FSM_CLKS_REG_b; }; union { - __IOM uint32_t MCU_FSM_REF_CLK_REG; /*!< (@ 0x0000001C) MCU FSM Clocks Register */ + __IOM unsigned int MCU_FSM_REF_CLK_REG; /*!< (@ 0x0000001C) MCU FSM Clocks Register */ struct { - __IOM uint32_t M4SS_REF_CLK_SEL : 3; /*!< [2..0] Dynamic Reference Clock Mux select + __IOM unsigned int M4SS_REF_CLK_SEL : 3; /*!< [2..0] Dynamic Reference Clock Mux select of M4SS 0 - Clock will be gated at dynamic mux output of M4SS 1 - ulp_32mhz_rc_byp_clk 2 - ulp_32mhz_rc_clk 3 - rf_ref_clk 4 - mems_ref_clk 5 - ulp_20mhz_ringosc_clk 6 - ulp_doubler_clk 7 - ref_byp_clk to TASS. */ - __IOM uint32_t Reserved1 : 4; /*!< [6..3] It is recommended to write these + __IOM unsigned int Reserved1 : 4; /*!< [6..3] It is recommended to write these bits to 0. */ - __IOM uint32_t M4SS_REF_CLK_CLEANER_OFF_b : 1; /*!< [7..7] Disable signal for m4ss + __IOM unsigned int M4SS_REF_CLK_CLEANER_OFF_b : 1; /*!< [7..7] Disable signal for m4ss reference clock. */ - __IOM uint32_t M4SS_REF_CLK_CLEANER_ON_b : 1; /*!< [8..8] Enable clk cleaner for m4ss + __IOM unsigned int M4SS_REF_CLK_CLEANER_ON_b : 1; /*!< [8..8] Enable clk cleaner for m4ss reference clock. */ - __IOM uint32_t Reserved2 : 3; /*!< [11..9] It is recommended to write + __IOM unsigned int Reserved2 : 3; /*!< [11..9] It is recommended to write these bits to 0. */ - __IOM uint32_t TASS_REF_CLK_SEL : 3; /*!< [14..12] Dynamic Reference Clock Mux select + __IOM unsigned int TASS_REF_CLK_SEL : 3; /*!< [14..12] Dynamic Reference Clock Mux select of TASS controlled by M4. 0 : Clock will be gated at dynamic mux output of TASS 1 : ulp_32mhz_rc_byp_clk 2 : ulp_32mhz_rc_clk 3 : rf_ref_clk 4 : mems_ref_clk 5 : ulp_20mhz_ringosc_clk 6 : ref_byp_clk to TASS. */ - __IOM uint32_t Reserved3 : 1; /*!< [15..15] It is recommended to write + __IOM unsigned int Reserved3 : 1; /*!< [15..15] It is recommended to write these bits to 0. */ - __IOM uint32_t ULPSS_REF_CLK_SEL_b : 3; /*!< [18..16] Dynamic Reference Clock Mux + __IOM unsigned int ULPSS_REF_CLK_SEL_b : 3; /*!< [18..16] Dynamic Reference Clock Mux select of TASS controlled by M4. 0 : Clock will be gated at dynamic mux output of TASS 1 : ulp_32mhz_rc_byp_clk 2 : ulp_32mhz_rc_clk 3 : rf_ref_clk 4 : mems_ref_clk 5 : ulp_20mhz_ringosc_clk 6 : ref_byp_clk to TASS. */ - __IOM uint32_t Reserved4 : 4; /*!< [22..19] It is recommended to write + __IOM unsigned int Reserved4 : 4; /*!< [22..19] It is recommended to write these bits to 0. */ - __IOM uint32_t ULPSS_REF_CLK_CLEANER_OFF_b : 1; /*!< [23..23] Clock cleaner Off + __IOM unsigned int ULPSS_REF_CLK_CLEANER_OFF_b : 1; /*!< [23..23] Clock cleaner Off signal for ulpss ref clock. */ - __IOM uint32_t ULPSS_REF_CLK_CLEANER_ON_b : 1; /*!< [24..24] Clock cleaner Off signal + __IOM unsigned int ULPSS_REF_CLK_CLEANER_ON_b : 1; /*!< [24..24] Clock cleaner Off signal for ulpss ref clock. */ - __IOM uint32_t Reserved5 : 3; /*!< [27..25] It is recommended to write + __IOM unsigned int Reserved5 : 3; /*!< [27..25] It is recommended to write these bits to 0. */ - __IOM uint32_t SDCSS_CLK_SEL_b : 2; /*!< [29..28] select between RC / RO + __IOM unsigned int SDCSS_CLK_SEL_b : 2; /*!< [29..28] select between RC / RO 32KHz clk in sdcss 01 - 32MHz RC Clock 10- 20MHz RO Clock. */ - __IOM uint32_t SDCSS_CLK_EN_b : 1; /*!< [30..30] To enable dynamic clock + __IOM unsigned int SDCSS_CLK_EN_b : 1; /*!< [30..30] To enable dynamic clock for sdcss */ - __IOM uint32_t SDCSS_STATIC_CLK_EN_b : 1; /*!< [31..31] To enable static clk for + __IOM unsigned int SDCSS_STATIC_CLK_EN_b : 1; /*!< [31..31] To enable static clk for sensor data collector subsystem */ } MCU_FSM_REF_CLK_REG_b; }; union { - __IOM uint32_t MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP; /*!< (@ 0x00000020) MCU FSM + __IOM unsigned int MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP; /*!< (@ 0x00000020) MCU FSM And First Bootup */ struct { - __IOM uint32_t FIRST_BOOTUP_MCU_N_b : 1; /*!< [0..0] Indication for S/W to + __IOM unsigned int FIRST_BOOTUP_MCU_N_b : 1; /*!< [0..0] Indication for S/W to distinguish b/w First Power or ULP wakeup.S/W need to set this Bit after first power .. */ - __IM uint32_t RAM_RETENTION_STATUS_M4SS_b : 1; /*!< [1..1] Indicates to S/W that + __IM unsigned int RAM_RETENTION_STATUS_M4SS_b : 1; /*!< [1..1] Indicates to S/W that RAM's were in retention mode during Sleep time. 1 - RAM are in retention mode during sleep. 0 - RAM are not in retention mode during sleep.Domain is OFF.. */ - __IOM uint32_t RETENTION_DOMAIN_ON_b : 1; /*!< [2..2] Indicates to S/W that Retention + __IOM unsigned int RETENTION_DOMAIN_ON_b : 1; /*!< [2..2] Indicates to S/W that Retention domain is ON. 1 - Domain is ON. 0 - Domain is OFF.. */ - __IOM uint32_t CHIP_MODE_VALID_b : 1; /*!< [3..3] Indicates to S/W that ChipMode + __IOM unsigned int CHIP_MODE_VALID_b : 1; /*!< [3..3] Indicates to S/W that ChipMode programming are valid and need not read EFUSE. 1 - ChipMode are Valid. 0 - ChipModes are invalid. */ - __IOM uint32_t STORAGE_DOMAIN_ON_b : 1; /*!< [4..4] Indicates to S/W that + __IOM unsigned int STORAGE_DOMAIN_ON_b : 1; /*!< [4..4] Indicates to S/W that MCU Data Storage 1 domain is ON. 1 - Domain is ON. 0 - Domain is OFF.. */ #ifndef SLI_SI917B0 - __IOM uint32_t Reserved1 : 10; /*!< [14..5] It is recommended to write + __IOM unsigned int Reserved1 : 10; /*!< [14..5] It is recommended to write these bits to 0. */ #else - __IOM uint32_t Reserved1 : 9; /*!< [13..5] It is recommended to write + __IOM unsigned int Reserved1 : 9; /*!< [13..5] It is recommended to write these bits to 0. */ - __IOM uint32_t MCU_ULP_1KHZ_RC_CLK_EN_b : 1; /*!< [14..14] Enables ULP 1KHz Rc Clock + __IOM unsigned int MCU_ULP_1KHZ_RC_CLK_EN_b : 1; /*!< [14..14] Enables ULP 1KHz Rc Clock (For SYSRTC and MCU WWD). */ #endif - __IOM uint32_t MCU_FSM_RESET_N_SYNC_b : 1; /*!< [15..15] Indicated MCU FSM is out of + __IOM unsigned int MCU_FSM_RESET_N_SYNC_b : 1; /*!< [15..15] Indicated MCU FSM is out of reset. 1 : Indicated MCU FSM is out of reset 0 : Indicated MCU FSM is in reset. */ - __IOM uint32_t MCU_ULP_32KHZ_RC_CLK_EN_b : 1; /*!< [16..16] Enables ULP + __IOM unsigned int MCU_ULP_32KHZ_RC_CLK_EN_b : 1; /*!< [16..16] Enables ULP 32KHz Rc Clock. */ - __IOM uint32_t MCU_ULP_32KHZ_RO_CLK_EN_b : 1; /*!< [17..17] Enables ULP + __IOM unsigned int MCU_ULP_32KHZ_RO_CLK_EN_b : 1; /*!< [17..17] Enables ULP 32KHz RO Clock. */ - __IOM uint32_t MCU_ULP_32KHZ_XTAL_CLK_EN_b : 1; /*!< [18..18] Enables ULP + __IOM unsigned int MCU_ULP_32KHZ_XTAL_CLK_EN_b : 1; /*!< [18..18] Enables ULP 32KHz Xtal Clock. */ - __IOM uint32_t MCU_ULP_32MHZ_RC_CLK_EN_b : 1; /*!< [19..19] Enables ULP + __IOM unsigned int MCU_ULP_32MHZ_RC_CLK_EN_b : 1; /*!< [19..19] Enables ULP 32MHz RC Clock. */ - __IOM uint32_t MCU_ULP_20MHZ_RING_OSC_CLK_EN_b : 1; /*!< [20..20] Enables ULP 20mhz + __IOM unsigned int MCU_ULP_20MHZ_RING_OSC_CLK_EN_b : 1; /*!< [20..20] Enables ULP 20mhz RO Clock. */ - __IOM uint32_t MCU_ULP_DOUBLER_CLK_EN_b : 1; /*!< [21..21] Enables ULP + __IOM unsigned int MCU_ULP_DOUBLER_CLK_EN_b : 1; /*!< [21..21] Enables ULP Doubler Clock. */ - __IOM uint32_t MCU_ULP_40MHZ_CLK_EN_b : 1; /*!< [22..22] Enables 40MHz + __IOM unsigned int MCU_ULP_40MHZ_CLK_EN_b : 1; /*!< [22..22] Enables 40MHz XTAL clock. */ - __IOM uint32_t Reserved2 : 9; /*!< [31..23] It is recommended to write + __IOM unsigned int Reserved2 : 9; /*!< [31..23] It is recommended to write these bits to 0. */ } MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b; }; union { - __IOM uint32_t MCU_FSM_CRTL_PDM_AND_ENABLES; /*!< (@ 0x00000024) Power Domains + __IOM unsigned int MCU_FSM_CRTL_PDM_AND_ENABLES; /*!< (@ 0x00000024) Power Domains Controlled by Sleep FSM. */ struct { - __IOM uint32_t ENABLE_WDT_IN_SLEEP_b : 1; /*!< [0..0] Its enable or disable WDT + __IOM unsigned int ENABLE_WDT_IN_SLEEP_b : 1; /*!< [0..0] Its enable or disable WDT during Sleep/Shutdown states. */ - __IOM uint32_t ENABLE_WURX_DETECTION_b : 1; /*!< [1..1] Its enable or disable + __IOM unsigned int ENABLE_WURX_DETECTION_b : 1; /*!< [1..1] Its enable or disable detection of On-Air Pattern using Wake-Fi Rx. */ - __IOM uint32_t RESET_MCU_BBF_DM_EN_b : 1; /*!< [2..2] Its enable or disable reset of + __IOM unsigned int RESET_MCU_BBF_DM_EN_b : 1; /*!< [2..2] Its enable or disable reset of Power Domain Control Battery FF's on wakeup. */ - __IOM uint32_t DISABLE_TURNOFF_SRAM_PERI_b : 1; /*!< [3..3] Enable MCU SRAM periphery + __IOM unsigned int DISABLE_TURNOFF_SRAM_PERI_b : 1; /*!< [3..3] Enable MCU SRAM periphery during Deepsleep 1 - Enable SRAM periphery during Deepsleep 0 - Disable SRAM periphery during Deepsleep. */ - __IOM uint32_t ENABLE_SRAM_DS_CRTL_b : 1; /*!< [4..4] Enable signal for controlling + __IOM unsigned int ENABLE_SRAM_DS_CRTL_b : 1; /*!< [4..4] Enable signal for controlling Deepsleep signal of all SRAM used by M4 1- Enable SRAM Deepsleep Signal 0- Disable SRAM Deepsleep Signal. */ - __IOM uint32_t Reserved1 : 11; /*!< [15..5] It is recommended to write + __IOM unsigned int Reserved1 : 11; /*!< [15..5] It is recommended to write these bits to 0. */ - __IOM uint32_t POWER_ENABLE_FSM_PERI_b : 1; /*!< [16..16] Its enable or disable Power + __IOM unsigned int POWER_ENABLE_FSM_PERI_b : 1; /*!< [16..16] Its enable or disable Power to Low-Power FSM. */ - __IOM uint32_t POWER_ENABLE_TIMESTAMPING_b : 1; /*!< [17..17] Its enable or disable + __IOM unsigned int POWER_ENABLE_TIMESTAMPING_b : 1; /*!< [17..17] Its enable or disable Power to TIMESTAMP. */ - __IOM uint32_t POWER_ENABLE_DEEPSLEEP_TIMER_b : 1; /*!< [18..18] Its enable or + __IOM unsigned int POWER_ENABLE_DEEPSLEEP_TIMER_b : 1; /*!< [18..18] Its enable or disable Power to DEEP SLEEP Timer. */ - __IOM uint32_t POWER_ENABLE_RETENTION_DM_b : 1; /*!< [19..19] Its enable or disable + __IOM unsigned int POWER_ENABLE_RETENTION_DM_b : 1; /*!< [19..19] Its enable or disable Power to Retention Flops during SHIP state.These Flops are used for storing Chip Configuration. */ - __IOM uint32_t Reserved2 : 12; /*!< [31..20] It is recommended to write + __IOM unsigned int Reserved2 : 12; /*!< [31..20] It is recommended to write these bits to 0. */ } MCU_FSM_CRTL_PDM_AND_ENABLES_b; }; union { - __IOM uint32_t MCU_GPIO_TIMESTAMPING_CONFIG; /*!< (@ 0x00000028) MCU GPIO + __IOM unsigned int MCU_GPIO_TIMESTAMPING_CONFIG; /*!< (@ 0x00000028) MCU GPIO TIMESTAMPING CONFIG. */ struct { - __IOM uint32_t ENABLE_GPIO_TIMESTAMPING_b : 1; /*!< [0..0] Enable GPIO time stamping + __IOM unsigned int ENABLE_GPIO_TIMESTAMPING_b : 1; /*!< [0..0] Enable GPIO time stamping Feature.. */ - __IOM uint32_t TIMESTAMPING_ON_GPIO0_b : 1; /*!< [1..1] Enable GPIO time + __IOM unsigned int TIMESTAMPING_ON_GPIO0_b : 1; /*!< [1..1] Enable GPIO time stamping on GPIO0. */ - __IOM uint32_t TIMESTAMPING_ON_GPIO1_b : 1; /*!< [2..2] Enable GPIO time + __IOM unsigned int TIMESTAMPING_ON_GPIO1_b : 1; /*!< [2..2] Enable GPIO time stamping on GPIO1. */ - __IOM uint32_t TIMESTAMPING_ON_GPIO2_b : 1; /*!< [3..3] Enable GPIO time + __IOM unsigned int TIMESTAMPING_ON_GPIO2_b : 1; /*!< [3..3] Enable GPIO time stamping on GPIO2. */ - __IOM uint32_t TIMESTAMPING_ON_GPIO3_b : 1; /*!< [4..4] Enable GPIO time + __IOM unsigned int TIMESTAMPING_ON_GPIO3_b : 1; /*!< [4..4] Enable GPIO time stamping on GPIO3. */ - __IOM uint32_t TIMESTAMPING_ON_GPIO4_b : 1; /*!< [5..5] Enable GPIO time + __IOM unsigned int TIMESTAMPING_ON_GPIO4_b : 1; /*!< [5..5] Enable GPIO time stamping on GPIO4. */ - __IOM uint32_t Reserved1 : 26; /*!< [31..6] It is recommended to write + __IOM unsigned int Reserved1 : 26; /*!< [31..6] It is recommended to write these bits to 0. */ } MCU_GPIO_TIMESTAMPING_CONFIG_b; }; union { - __IM uint32_t MCU_GPIO_TIMESTAMP_READ; /*!< (@ 0x0000002C) MCU GPIO + __IM unsigned int MCU_GPIO_TIMESTAMP_READ; /*!< (@ 0x0000002C) MCU GPIO TIMESTAMPING READ. */ struct { - __IM uint32_t GPIO_EVENT_COUNT_PARTIAL : 11; /*!< [10..0] Counter value indicating + __IM unsigned int GPIO_EVENT_COUNT_PARTIAL : 11; /*!< [10..0] Counter value indicating the duration from GPIO going high to first Sleep clock( MCU FSM Clock) posedge from GPIO going high with respect to 32MHz clock. */ - __IM uint32_t Reserved1 : 5; /*!< [15..11] It is recommended to write + __IM unsigned int Reserved1 : 5; /*!< [15..11] It is recommended to write these bits to 0. */ - __IM uint32_t GPIO_EVENT_COUNT_FULL : 11; /*!< [26..16] Counter value indicating + __IM unsigned int GPIO_EVENT_COUNT_FULL : 11; /*!< [26..16] Counter value indicating number for 32MHz clock present in 1 Sleep clock (MCU FSM Clock). */ - __IM uint32_t Reserved2 : 5; /*!< [31..27] It is recommended to write + __IM unsigned int Reserved2 : 5; /*!< [31..27] It is recommended to write these bits to 0. */ } MCU_GPIO_TIMESTAMP_READ_b; }; union { - __IOM uint32_t MCU_SLEEPHOLD_REQ; /*!< (@ 0x00000030) MCU SLEEP HOLD REQ. */ + __IOM unsigned int MCU_SLEEPHOLD_REQ; /*!< (@ 0x00000030) MCU SLEEP HOLD REQ. */ struct { - __IOM uint32_t SLEEPHOLDREQn : 1; /*!< [0..0] Sleepholdreq when enable + __IOM unsigned int SLEEPHOLDREQn : 1; /*!< [0..0] Sleepholdreq when enable will gate the clock to M4. 1 - Sleepholdreq is Disabled. 0 - Sleepholdreq is Enabled. */ - __IM uint32_t SLEEPHOLDACKn : 1; /*!< [1..1] SLEEPHOLDACK response to + __IM unsigned int SLEEPHOLDACKn : 1; /*!< [1..1] SLEEPHOLDACK response to SLEEPHOLDREQ. */ - __IOM uint32_t Reserved1 : 14; /*!< [15..2] It is recommended to write + __IOM unsigned int Reserved1 : 14; /*!< [15..2] It is recommended to write these bits to 0. */ - __IOM uint32_t SELECT_FSM_MODE : 1; /*!< [16..16] Enable for selecting secondary FSM. + __IOM unsigned int SELECT_FSM_MODE : 1; /*!< [16..16] Enable for selecting secondary FSM. 1 - Select Secondary FSM 0 - Select Primary FSM. */ - __IOM uint32_t Reserved2 : 15; /*!< [31..17] It is recommended to write + __IOM unsigned int Reserved2 : 15; /*!< [31..17] It is recommended to write these bits to 0. */ } MCU_SLEEPHOLD_REQ_b; }; - __IM uint32_t RESERVED; + __IM unsigned int RESERVED; union { - __IOM uint32_t MCU_FSM_WAKEUP_STATUS_REG; /*!< (@ 0x00000038) MCU FSM Wakeup + __IOM unsigned int MCU_FSM_WAKEUP_STATUS_REG; /*!< (@ 0x00000038) MCU FSM Wakeup Status Register. */ struct { - __IOM uint32_t WAKEUP_STATUS : 11; /*!< [10..0] To know the wakeup source. */ - __IOM uint32_t Reserved1 : 5; /*!< [15..11] It is recommended to write + __IOM unsigned int WAKEUP_STATUS : 11; /*!< [10..0] To know the wakeup source. */ + __IOM unsigned int Reserved1 : 5; /*!< [15..11] It is recommended to write these bits to 0. */ - __IOM uint32_t MCU_FIRST_POWERUP_POR : 1; /*!< [16..16] Indication to Processor that + __IOM unsigned int MCU_FIRST_POWERUP_POR : 1; /*!< [16..16] Indication to Processor that system came out first power up. */ - __IOM uint32_t MCU_FIRST_POWERUP_RESET_N : 1; /*!< [17..17] Indication to Processor + __IOM unsigned int MCU_FIRST_POWERUP_RESET_N : 1; /*!< [17..17] Indication to Processor that system came out of Reset. */ - __IOM uint32_t Reserve2 : 14; /*!< [31..18] It is recommended to write + __IOM unsigned int Reserve2 : 14; /*!< [31..18] It is recommended to write these bits to 0. */ } MCU_FSM_WAKEUP_STATUS_REG_b; }; union { - __IOM uint32_t MCU_FSM_WAKEUP_STATUS_CLEAR; /*!< (@ 0x0000003C) MCU FSM + __IOM unsigned int MCU_FSM_WAKEUP_STATUS_CLEAR; /*!< (@ 0x0000003C) MCU FSM Wakeup Status Clear. */ struct { - __IOM uint32_t WWD_INTERRUPT_STATUS_CLEAR_b : 1; /*!< [0..0] To Clear WatchDog + __IOM unsigned int WWD_INTERRUPT_STATUS_CLEAR_b : 1; /*!< [0..0] To Clear WatchDog Interrupt status indication. */ - __IOM uint32_t MILLI_SEC_BASED_STATUS_CLEAR_b : 1; /*!< [1..1] To Clear Milli-Second + __IOM unsigned int MILLI_SEC_BASED_STATUS_CLEAR_b : 1; /*!< [1..1] To Clear Milli-Second Wakeup status indication. */ - __IOM uint32_t RTC_SEC_BASED_STATUS_CLEAR_b : 1; /*!< [2..2] To Clear Second Tick + __IOM unsigned int RTC_SEC_BASED_STATUS_CLEAR_b : 1; /*!< [2..2] To Clear Second Tick wakeup status indication. */ - __IOM uint32_t RTC_ALARM_BASED_WAKEUP_STATUS_CLEAR_b : 1; /*!< [3..3] To Clear RTC + __IOM unsigned int RTC_ALARM_BASED_WAKEUP_STATUS_CLEAR_b : 1; /*!< [3..3] To Clear RTC Alarm wakeup status indicaition. */ - __IOM uint32_t COMP1_BASED_WAKEUP_STATUS_CLEAR_b : 1; /*!< [4..4] To Clear comp1 + __IOM unsigned int COMP1_BASED_WAKEUP_STATUS_CLEAR_b : 1; /*!< [4..4] To Clear comp1 wakeup (Analog IP1 and Analog IP2) status indication. */ - __IOM uint32_t COMP2_BASED_WAKEUP_STATUS_CLEAR_b : 1; /*!< [5..5] To Clear comp2 + __IOM unsigned int COMP2_BASED_WAKEUP_STATUS_CLEAR_b : 1; /*!< [5..5] To Clear comp2 wakeup (Analog IP1 and BandGap Scale) status indication. */ __IOM - uint32_t COMP3_BASED_WAKEUP_STATUS_CLEAR_b : 1; /*!< [6..6] To Clear comp3 + unsigned int COMP3_BASED_WAKEUP_STATUS_CLEAR_b : 1; /*!< [6..6] To Clear comp3 wakeup (Analog IP1 and VBatt Scale) status indication. */ __IOM - uint32_t COMP4_BASED_WAKEUP_STATUS_CLEAR_b : 1; /*!< [7..7] To Clear Comp4 + unsigned int COMP4_BASED_WAKEUP_STATUS_CLEAR_b : 1; /*!< [7..7] To Clear Comp4 wakeup (Bandgap En and VBatt Scale) status indication. */ - __IOM uint32_t COMP5_BASED_WAKEUP_STATUS_CLEAR_b : 1; /*!< [8..8] To Clear BOD Wakeup + __IOM unsigned int COMP5_BASED_WAKEUP_STATUS_CLEAR_b : 1; /*!< [8..8] To Clear BOD Wakeup status indication. */ - __IOM uint32_t COMP6_BASED_WAKEUP_STATUS_CLEAR_b : 1; /*!< [9..9] To Clear + __IOM unsigned int COMP6_BASED_WAKEUP_STATUS_CLEAR_b : 1; /*!< [9..9] To Clear Button-wake status indication. */ #ifndef SLI_SI917B0 - __IOM uint32_t RF_WAKEUP_CLEAR_b : 1; /*!< [10..10] To Clear WuRX status + __IOM unsigned int RF_WAKEUP_CLEAR_b : 1; /*!< [10..10] To Clear WuRX status indication. */ #else - __IOM uint32_t SYSRTC_WAKEUP_CLEAR_b : 1; /*!< [10..10] To Clear SYSRTC Wakeup status + __IOM unsigned int SYSRTC_WAKEUP_CLEAR_b : 1; /*!< [10..10] To Clear SYSRTC Wakeup status indication. */ #endif - __IOM uint32_t Reserved1 : 21; /*!< [31..11] It is recommended to write + __IOM unsigned int Reserved1 : 21; /*!< [31..11] It is recommended to write these bits to 0. */ } MCU_FSM_WAKEUP_STATUS_CLEAR_b; }; union { - __IOM uint32_t MCU_FSM_PMU_STATUS_REG; /*!< (@ 0x00000040) MCU FSM PMU + __IOM unsigned int MCU_FSM_PMU_STATUS_REG; /*!< (@ 0x00000040) MCU FSM PMU Status Register. */ struct { - __IOM uint32_t SCDCDC_LP_MODE_EN : 1; /*!< [0..0] SCDC in LP mode. */ - __IOM uint32_t BGPMU_SLEEP_EN_R_b : 1; /*!< [1..1] Sleep en for BG PMU. */ - __IOM uint32_t Reserved1 : 15; /*!< [16..2] It is recommended to write + __IOM unsigned int SCDCDC_LP_MODE_EN : 1; /*!< [0..0] SCDC in LP mode. */ + __IOM unsigned int BGPMU_SLEEP_EN_R_b : 1; /*!< [1..1] Sleep en for BG PMU. */ + __IOM unsigned int Reserved1 : 15; /*!< [16..2] It is recommended to write these bits to 0. */ - __IOM uint32_t STANDBY_LDORF_R : 1; /*!< [17..17] Standby state for LDO RF. */ - __IOM uint32_t STANDBY_LDOSOC_R : 1; /*!< [18..18] Standby state for LDO soc. */ - __IOM uint32_t STANDBY_DC1P3_R : 1; /*!< [19..19] Standby state for DC1p3. */ - __IM uint32_t POWERGOOD_LDOSOC : 1; /*!< [20..20] Powergood signal from ldosoc. */ - __IM uint32_t LEVEL_OK_DC1P3 : 1; /*!< [21..21] Powergood signal from LDORF. */ - __IM uint32_t CL_FLAG_DC1P3 : 1; /*!< [22..22] Powergood signal read for + __IOM unsigned int STANDBY_LDORF_R : 1; /*!< [17..17] Standby state for LDO RF. */ + __IOM unsigned int STANDBY_LDOSOC_R : 1; /*!< [18..18] Standby state for LDO soc. */ + __IOM unsigned int STANDBY_DC1P3_R : 1; /*!< [19..19] Standby state for DC1p3. */ + __IM unsigned int POWERGOOD_LDOSOC : 1; /*!< [20..20] Powergood signal from ldosoc. */ + __IM unsigned int LEVEL_OK_DC1P3 : 1; /*!< [21..21] Powergood signal from LDORF. */ + __IM unsigned int CL_FLAG_DC1P3 : 1; /*!< [22..22] Powergood signal read for DC 1.3V. */ - __IOM uint32_t Reserved2 : 9; /*!< [31..23] It is recommended to write + __IOM unsigned int Reserved2 : 9; /*!< [31..23] It is recommended to write these bits to 0. */ } MCU_FSM_PMU_STATUS_REG_b; }; union { - __IOM uint32_t MCU_FSM_PMUX_CTRLS_RET; /*!< (@ 0x00000044) MCU FSM PMUX + __IOM unsigned int MCU_FSM_PMUX_CTRLS_RET; /*!< (@ 0x00000044) MCU FSM PMUX Controls Retention. */ struct { - __IOM uint32_t POWER_SW_CTRL_TASS_RAM_IN_RETAIN : 1; /*!< [0..0] Select value for + __IOM unsigned int POWER_SW_CTRL_TASS_RAM_IN_RETAIN : 1; /*!< [0..0] Select value for TASS RAM Power Mux In Retention mode */ - __IOM uint32_t POWER_SW_CTRL_M4SS_RAM_IN_RETAIN : 1; /*!< [1..1] Select value for + __IOM unsigned int POWER_SW_CTRL_M4SS_RAM_IN_RETAIN : 1; /*!< [1..1] Select value for M4SS RAM Power Mux In Retention mode */ - __IOM uint32_t POWER_SW_CTRL_M4ULP_RAM_IN_RETAIN : 2; /*!< [3..2] Select value for + __IOM unsigned int POWER_SW_CTRL_M4ULP_RAM_IN_RETAIN : 2; /*!< [3..2] Select value for M4ULP RAM Power Mux In Retention mode */ - __IOM uint32_t POWER_SW_CTRL_M4ULP_RAM16K_IN_RETAIN : 2; /*!< [5..4] Select value for + __IOM unsigned int POWER_SW_CTRL_M4ULP_RAM16K_IN_RETAIN : 2; /*!< [5..4] Select value for M4ULP 16K RAM Power Mux In Retention mode */ - __IOM uint32_t POWER_SW_CTRL_ULPSS_RAM_IN_RETAIN : 2; /*!< [7..6] Select value for + __IOM unsigned int POWER_SW_CTRL_ULPSS_RAM_IN_RETAIN : 2; /*!< [7..6] Select value for ULPSS RAM Power Mux In Retention mode */ - __IOM uint32_t Reserved1 : 24; /*!< [31..8] It is recommended to write + __IOM unsigned int Reserved1 : 24; /*!< [31..8] It is recommended to write these bits to 0. */ } MCU_FSM_PMUX_CTRLS_RET_b; }; union { - __IOM uint32_t MCU_FSM_TOGGLE_COUNT; /*!< (@ 0x00000048) MCU FSM Toggle Count. */ + __IOM unsigned int MCU_FSM_TOGGLE_COUNT; /*!< (@ 0x00000048) MCU FSM Toggle Count. */ struct { - __OM uint32_t TOGGLE_COUNT_RSTART : 1; /*!< [0..0] Start counting GIPO Toggles. */ - __IOM uint32_t Reserved1 : 14; /*!< [14..1] It is recommended to write + __OM unsigned int TOGGLE_COUNT_RSTART : 1; /*!< [0..0] Start counting GIPO Toggles. */ + __IOM unsigned int Reserved1 : 14; /*!< [14..1] It is recommended to write these bits to 0. */ - __OM uint32_t LATCH_TOGGLE_DATA : 1; /*!< [15..15] Trigger indication to + __OM unsigned int LATCH_TOGGLE_DATA : 1; /*!< [15..15] Trigger indication to read GPIO toggle data. */ - __IM uint32_t GPIO_TOGGLE_COUNT : 12; /*!< [27..16] GPIO toogle data count. */ - __IOM uint32_t Reserved2 : 3; /*!< [30..28] It is recommended to write + __IM unsigned int GPIO_TOGGLE_COUNT : 12; /*!< [27..16] GPIO toogle data count. */ + __IOM unsigned int Reserved2 : 3; /*!< [30..28] It is recommended to write these bits to 0. */ - __IM uint32_t TOGGLE_DATA_READY : 1; /*!< [31..31] GPIO toogle data count. */ + __IM unsigned int TOGGLE_DATA_READY : 1; /*!< [31..31] GPIO toogle data count. */ } MCU_FSM_TOGGLE_COUNT_b; }; } MCU_FSM_Type; /*!< Size = 76 (0x4c) */ @@ -12967,28 +12967,28 @@ typedef struct { /*!< (@ 0x24048100) MCU_FSM Structure */ typedef struct { /*!< (@ 0x24048540) MCU_ProcessSensor Structure */ union { - __IOM uint32_t PROCESS_SENSOR_ENABLE_AND_READ; /*!< (@ 0x00000000) Process sensor + __IOM unsigned int PROCESS_SENSOR_ENABLE_AND_READ; /*!< (@ 0x00000000) Process sensor enable and read for operation */ struct { - __IOM uint32_t PROCESS_SENSOR_EN : 1; /*!< [0..0] enable or on the process sensor,if + __IOM unsigned int PROCESS_SENSOR_EN : 1; /*!< [0..0] enable or on the process sensor,if this bit is set the sensor enable else sensor is disable. */ - __IOM uint32_t PS_RING_CLK_START : 1; /*!< [1..1] Start Ring-Oscillator clock for + __IOM unsigned int PS_RING_CLK_START : 1; /*!< [1..1] Start Ring-Oscillator clock for estimating process corner. */ - __IOM uint32_t PS_CLK_SW_ON : 1; /*!< [2..2] Clock cleaner on signal to clock cleaner + __IOM unsigned int PS_CLK_SW_ON : 1; /*!< [2..2] Clock cleaner on signal to clock cleaner block on clock generated by delay chain. */ - __IOM uint32_t PS_CLK_SW_OFF : 1; /*!< [3..3] Clock cleaner off signal to clock + __IOM unsigned int PS_CLK_SW_OFF : 1; /*!< [3..3] Clock cleaner off signal to clock cleaner block on clock generated by delay chain. */ - __IOM uint32_t NUM_CYCLES : 2; /*!< [5..4] Number of MCU FSM clock(32KHz)for which + __IOM unsigned int NUM_CYCLES : 2; /*!< [5..4] Number of MCU FSM clock(32KHz)for which measurement need to be done.if bits is 1 then 1 clock, 2 then 2 clocks,3 then 3 clocks,4 then 4 clocks. */ - __IM uint32_t PS_MEAS_DONE_SYNC : 1; /*!< [6..6] Processor sensor + __IM unsigned int PS_MEAS_DONE_SYNC : 1; /*!< [6..6] Processor sensor measurement done. */ - __IOM uint32_t RESERVED1 : 9; /*!< [15..7] Reserved1 */ - __IM uint32_t PS_COUNT : 16; /*!< [31..16] Processor sensor read back */ + __IOM unsigned int RESERVED1 : 9; /*!< [15..7] Reserved1 */ + __IM unsigned int PS_COUNT : 16; /*!< [31..16] Processor sensor read back */ } PROCESS_SENSOR_ENABLE_AND_READ_b; }; } MCU_ProcessSensor_Type; /*!< Size = 4 (0x4) */ @@ -13009,84 +13009,84 @@ typedef struct { /*!< (@ 0x24048540) MCU_ProcessSensor Structure */ typedef struct { /*!< (@ 0x24048600) MCU_RET Structure */ union { - __IOM uint32_t MCURET_QSPI_WR_OP_DIS; /*!< (@ 0x00000000) MCURET QSPI WR OP DIS */ + __IOM unsigned int MCURET_QSPI_WR_OP_DIS; /*!< (@ 0x00000000) MCURET QSPI WR OP DIS */ struct { - __IOM uint32_t M4SS_QSPI_WRSR_WR_OP_DISABLE : 1; /*!< [0..0] M4SS Write operation + __IOM unsigned int M4SS_QSPI_WRSR_WR_OP_DISABLE : 1; /*!< [0..0] M4SS Write operation disable to Flash. 1 - Write Operation to Flash is not allowed. 0 - Write Operation to Flash is allowed. */ - __IM uint32_t TASS_QSPI_WRSR_WR_OP_DISABLE : 1; /*!< [1..1] TASS Write operation + __IM unsigned int TASS_QSPI_WRSR_WR_OP_DISABLE : 1; /*!< [1..1] TASS Write operation disable to Flash. 1 - Write Operation to Flash is not allowed. 0 - Write Operation to Flash is allowed. */ - __IOM uint32_t RESERVED1 : 30; /*!< [31..2] Reserved1 */ + __IOM unsigned int RESERVED1 : 30; /*!< [31..2] Reserved1 */ } MCURET_QSPI_WR_OP_DIS_b; }; union { - __IM uint32_t MCURET_BOOTSTATUS; /*!< (@ 0x00000004) MCURET BOOT Status */ + __IM unsigned int MCURET_BOOTSTATUS; /*!< (@ 0x00000004) MCURET BOOT Status */ struct { - __IM uint32_t BOOT_STATUS : 1; /*!< [0..0] Boot Status/Configuration + __IM unsigned int BOOT_STATUS : 1; /*!< [0..0] Boot Status/Configuration information to MCU */ - __IM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved1 */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved1 */ } MCURET_BOOTSTATUS_b; }; - __IM uint32_t RESERVED; + __IM unsigned int RESERVED; union { - __IM uint32_t CHIP_CONFIG_MCU_READ; /*!< (@ 0x0000000C) MCURET BOOT Status */ + __IM unsigned int CHIP_CONFIG_MCU_READ; /*!< (@ 0x0000000C) MCURET BOOT Status */ struct { - __IM uint32_t DISABLE_M4 : 1; /*!< [0..0] When set, disables the M4 by + __IM unsigned int DISABLE_M4 : 1; /*!< [0..0] When set, disables the M4 by clock gating and putting M4 in reset */ - __IM uint32_t LIMIT_M4_FREQ_110MHZ_b : 1; /*!< [1..1] When set, limits the M4SS SoC + __IM unsigned int LIMIT_M4_FREQ_110MHZ_b : 1; /*!< [1..1] When set, limits the M4SS SoC clock to Max clock/2 */ - __IM uint32_t DISABLE_M4_ULP_MODE : 1; /*!< [2..2] When set, limits the M4SS SoC + __IM unsigned int DISABLE_M4_ULP_MODE : 1; /*!< [2..2] When set, limits the M4SS SoC clock to Max clock/2 */ - __IM uint32_t RESERVED1 : 7; /*!< [9..3] Reserved1 */ - __IM uint32_t M4_FLASH_SIZE : 3; /*!< [12..10] 0xx - Unrestricted 100 - Auto mode + __IM unsigned int RESERVED1 : 7; /*!< [9..3] Reserved1 */ + __IM unsigned int M4_FLASH_SIZE : 3; /*!< [12..10] 0xx - Unrestricted 100 - Auto mode accesses to flash are restricted to 4 MBit 101 - Auto mode accesses to flash are restricted to 8 MBit 110 - Auto mode accesses to flash are restricted to 16 MBit 111 - Auto mode accesses to flash are restricted to 32 MBit */ - __IM uint32_t DISABLE_FIM_COP : 1; /*!< [13..13] When set, disable FIMV */ - __IM uint32_t DISABLE_VAP : 1; /*!< [14..14] When set, disables VAD */ - __IM uint32_t DISABLE_TOUCH : 1; /*!< [15..15] When set, disables touch + __IM unsigned int DISABLE_FIM_COP : 1; /*!< [13..13] When set, disable FIMV */ + __IM unsigned int DISABLE_VAP : 1; /*!< [14..14] When set, disables VAD */ + __IM unsigned int DISABLE_TOUCH : 1; /*!< [15..15] When set, disables touch interface */ - __IM uint32_t RESERVED2 : 1; /*!< [16..16] Reserved2 */ - __IM uint32_t DISABLE_ANALOG_PERIPH : 1; /*!< [17..17] When set, disables + __IM unsigned int RESERVED2 : 1; /*!< [16..16] Reserved2 */ + __IM unsigned int DISABLE_ANALOG_PERIPH : 1; /*!< [17..17] When set, disables analog peripherals */ - __IM uint32_t DISABLE_JTAG : 1; /*!< [18..18] When set, disable JTAG + __IM unsigned int DISABLE_JTAG : 1; /*!< [18..18] When set, disable JTAG interface(both M4 and TA) */ - __IM uint32_t DISABLE_M4SS_KH_ACCESS : 1; /*!< [19..19] When set, disables + __IM unsigned int DISABLE_M4SS_KH_ACCESS : 1; /*!< [19..19] When set, disables access to key in the key holder from M4SS QSPI */ - __IM uint32_t DISABLE_M4SS_ACCESS_FRM_TASS_SEC : 1; /*!< [20..20] When set, M4 can + __IM unsigned int DISABLE_M4SS_ACCESS_FRM_TASS_SEC : 1; /*!< [20..20] When set, M4 can not access TASS memory or registers except for host communication registers */ - __IM uint32_t RESERVED3 : 11; /*!< [31..21] Reserved3 */ + __IM unsigned int RESERVED3 : 11; /*!< [31..21] Reserved3 */ } CHIP_CONFIG_MCU_READ_b; }; union { - __IOM uint32_t MCUAON_CTRL_REG4; /*!< (@ 0x00000010) MCURET Control Register4 */ + __IOM unsigned int MCUAON_CTRL_REG4; /*!< (@ 0x00000010) MCURET Control Register4 */ struct { - __IOM uint32_t RESERVED1 : 16; /*!< [15..0] Reserved1 */ - __IOM uint32_t ULP_GPIO_2_TEST_MODE_OUT_SEL : 4; /*!< [19..16] NPSS Test modes */ - __IOM uint32_t ULP_GPIO_1_TEST_MODE_OUT_SEL : 4; /*!< [23..20] NPSS Test modes */ - __IOM uint32_t ULP_GPIO_0_TEST_MODE_OUT_SEL : 4; /*!< [27..24] NPSS Test modes */ - __IOM uint32_t ULP_GPIOS_IN_TEST_MODE : 1; /*!< [28..28] NPSS Test modes */ - __IOM uint32_t RESERVED2 : 3; /*!< [31..29] Reserved2 */ + __IOM unsigned int RESERVED1 : 16; /*!< [15..0] Reserved1 */ + __IOM unsigned int ULP_GPIO_2_TEST_MODE_OUT_SEL : 4; /*!< [19..16] NPSS Test modes */ + __IOM unsigned int ULP_GPIO_1_TEST_MODE_OUT_SEL : 4; /*!< [23..20] NPSS Test modes */ + __IOM unsigned int ULP_GPIO_0_TEST_MODE_OUT_SEL : 4; /*!< [27..24] NPSS Test modes */ + __IOM unsigned int ULP_GPIOS_IN_TEST_MODE : 1; /*!< [28..28] NPSS Test modes */ + __IOM unsigned int RESERVED2 : 3; /*!< [31..29] Reserved2 */ } MCUAON_CTRL_REG4_b; }; - __IM uint32_t RESERVED1[2]; + __IM unsigned int RESERVED1[2]; __IOM MCU_RET_NPSS_GPIO_CNTRL_Type NPSS_GPIO_CNTRL[5]; /*!< (@ 0x0000001C) [0..4] */ } MCU_RET_Type; /*!< Size = 48 (0x30) */ @@ -13105,75 +13105,75 @@ typedef struct { /*!< (@ 0x24048600) MCU_RET Structure */ typedef struct { /*!< (@ 0x24048500) MCU_TEMP Structure */ union { - __IOM uint32_t TS_ENABLE_AND_TEMPERATURE_DONE; /*!< (@ 0x00000000) Temperature sensor + __IOM unsigned int TS_ENABLE_AND_TEMPERATURE_DONE; /*!< (@ 0x00000000) Temperature sensor enable and measurement calculation done indication register */ struct { - __OM uint32_t TEMP_SENS_EN : 1; /*!< [0..0] Temperature sensing + __OM unsigned int TEMP_SENS_EN : 1; /*!< [0..0] Temperature sensing enable,self clearing register */ - __IOM uint32_t REF_CLK_SEL : 1; /*!< [1..1] if this bit is zero then reference RO + __IOM unsigned int REF_CLK_SEL : 1; /*!< [1..1] if this bit is zero then reference RO clock from analog,else this bit is one then MCU FSM clock */ - __IOM uint32_t CONT_COUNT_FREEZE : 10; /*!< [11..2] Count of reference clock on which + __IOM unsigned int CONT_COUNT_FREEZE : 10; /*!< [11..2] Count of reference clock on which ptat clock counts */ - __IM uint32_t TEMP_MEASUREMENT_DONE : 1; /*!< [12..12] temperature measurement done + __IM unsigned int TEMP_MEASUREMENT_DONE : 1; /*!< [12..12] temperature measurement done indication. */ - __IOM uint32_t RESERVED1 : 19; /*!< [31..13] reserved1 */ + __IOM unsigned int RESERVED1 : 19; /*!< [31..13] reserved1 */ } TS_ENABLE_AND_TEMPERATURE_DONE_b; }; union { - __IOM uint32_t TS_SLOPE_SET; /*!< (@ 0x00000004) temperature sensor slope set(slope + __IOM unsigned int TS_SLOPE_SET; /*!< (@ 0x00000004) temperature sensor slope set(slope will be change with respect to temperature change) */ struct { - __IOM uint32_t SLOPE : 10; /*!< [9..0] This is one time measurement for one package + __IOM unsigned int SLOPE : 10; /*!< [9..0] This is one time measurement for one package after chip arrives from fab,this is signed bit. */ - __IOM uint32_t RESERVED1 : 6; /*!< [15..10] Reserved1 */ - __IOM uint32_t TEMPERATURE_SPI : 11; /*!< [26..16] temperature known */ - __OM uint32_t TEMP_UPDATED : 1; /*!< [27..27] temperature updated signal for the reg + __IOM unsigned int RESERVED1 : 6; /*!< [15..10] Reserved1 */ + __IOM unsigned int TEMPERATURE_SPI : 11; /*!< [26..16] temperature known */ + __OM unsigned int TEMP_UPDATED : 1; /*!< [27..27] temperature updated signal for the reg to capture this temperature. */ - __IOM uint32_t BJT_BASED_TEMP : 1; /*!< [28..28] Temperature is updated through which + __IOM unsigned int BJT_BASED_TEMP : 1; /*!< [28..28] Temperature is updated through which is calculated using bjt based if bit is high(1) through spi and bit is low(0) then through calculation RO based */ - __IOM uint32_t RESERVED2 : 3; /*!< [31..29] Reserved2 */ + __IOM unsigned int RESERVED2 : 3; /*!< [31..29] Reserved2 */ } TS_SLOPE_SET_b; }; union { - __IOM uint32_t TS_FE_COUNTS_NOMINAL_SETTINGS; /*!< (@ 0x00000008) determine + __IOM unsigned int TS_FE_COUNTS_NOMINAL_SETTINGS; /*!< (@ 0x00000008) determine calibrated temperature */ struct { - __IOM uint32_t F2_NOMINAL : 10; /*!< [9..0] ptat clock count during calibration,This + __IOM unsigned int F2_NOMINAL : 10; /*!< [9..0] ptat clock count during calibration,This will vary with chip to chip. */ - __IOM uint32_t RESERVED1 : 6; /*!< [15..10] Reserved1 */ - __IOM uint32_t NOMINAL_TEMPERATURE : 7; /*!< [22..16] calibrated temperature */ - __IOM uint32_t RESERVED2 : 9; /*!< [31..23] Reserved2 */ + __IOM unsigned int RESERVED1 : 6; /*!< [15..10] Reserved1 */ + __IOM unsigned int NOMINAL_TEMPERATURE : 7; /*!< [22..16] calibrated temperature */ + __IOM unsigned int RESERVED2 : 9; /*!< [31..23] Reserved2 */ } TS_FE_COUNTS_NOMINAL_SETTINGS_b; }; union { - __IM uint32_t TS_COUNTS_READ; /*!< (@ 0x0000000C) temperature sensor count read. */ + __IM unsigned int TS_COUNTS_READ; /*!< (@ 0x0000000C) temperature sensor count read. */ struct { - __IM uint32_t COUNT_F2 : 10; /*!< [9..0] COUNT_F2 */ - __IM uint32_t RESERVED1 : 6; /*!< [15..10] Reserved1 */ - __IM uint32_t COUNT_F1 : 10; /*!< [25..16] COUNT_F1 */ - __IM uint32_t RESERVED2 : 6; /*!< [31..26] Reserved2 */ + __IM unsigned int COUNT_F2 : 10; /*!< [9..0] COUNT_F2 */ + __IM unsigned int RESERVED1 : 6; /*!< [15..10] Reserved1 */ + __IM unsigned int COUNT_F1 : 10; /*!< [25..16] COUNT_F1 */ + __IM unsigned int RESERVED2 : 6; /*!< [31..26] Reserved2 */ } TS_COUNTS_READ_b; }; union { - __IOM uint32_t TEMPERATURE_READ; /*!< (@ 0x00000010) read the temperature */ + __IOM unsigned int TEMPERATURE_READ; /*!< (@ 0x00000010) read the temperature */ struct { - __IM uint32_t TEMPERATURE_RD : 11; /*!< [10..0] Temperature value for read + __IM unsigned int TEMPERATURE_RD : 11; /*!< [10..0] Temperature value for read in signed format */ - __IOM uint32_t RES10 : 21; /*!< [31..11] reserved10 */ + __IOM unsigned int RES10 : 21; /*!< [31..11] reserved10 */ } TEMPERATURE_READ_b; }; } MCU_TEMP_Type; /*!< Size = 20 (0x14) */ @@ -13194,277 +13194,277 @@ typedef struct { /*!< (@ 0x24048500) MCU_TEMP Structure */ typedef struct { /*!< (@ 0x24048000) MCU_AON Structure */ union { - __IOM uint32_t MCUAON_NPSS_PWRCTRL_SET_REG; /*!< (@ 0x00000000) This register used for + __IOM unsigned int MCUAON_NPSS_PWRCTRL_SET_REG; /*!< (@ 0x00000000) This register used for NPSS power control set register. */ struct { - __IOM uint32_t RES : 1; /*!< [0..0] bit is reserved */ - __IOM uint32_t SLPSS_PWRGATE_EN_N_ULP_MCUBFFS : 1; /*!< [1..1] MCU domain battery + __IOM unsigned int RES : 1; /*!< [0..0] bit is reserved */ + __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUBFFS : 1; /*!< [1..1] MCU domain battery FF's power gate enable.If set,Power Supply is On clearing this bit has no effect. */ - __IOM uint32_t SLPSS_PWRGATE_EN_N_ULP_MCUFSM : 1; /*!< [2..2] MCU FSM power gate + __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUFSM : 1; /*!< [2..2] MCU FSM power gate enable,If set power supply is on clearing this bit has no effect. */ - __IOM uint32_t SLPSS_PWRGATE_EN_N_ULP_MCURTC : 1; /*!< [3..3] MCU RTC power gate + __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCURTC : 1; /*!< [3..3] MCU RTC power gate enable if set,power supply is on clearing this bit has no effect. */ __IOM - uint32_t SLPSS_PWRGATE_EN_N_ULP_MCUWDT : 1; /*!< [4..4] MCU WDT power + unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUWDT : 1; /*!< [4..4] MCU WDT power gate enable if set,power supply is on clearing this bit has no effect */ __IOM - uint32_t SLPSS_PWRGATE_EN_N_ULP_MCUPS : 1; /*!< [5..5] MCU PS power gate + unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUPS : 1; /*!< [5..5] MCU PS power gate enable.if set,power supply is on clearing this bit has no effect. */ - __IOM uint32_t SLPSS_PWRGATE_EN_N_ULP_MCUTS : 1; /*!< [6..6] MCU temperature sensor + __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUTS : 1; /*!< [6..6] MCU temperature sensor power gate enable if set,power supply is on.clearing this bit has no effect */ - __IOM uint32_t SLPSS_PWRGATE_EN_N_ULP_MCUSTORE1 : 1; /*!< [7..7] MCU Storage 1 power + __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUSTORE1 : 1; /*!< [7..7] MCU Storage 1 power gate enable for 64-bit.if set,power supply is on,clearing this bit has no effect. */ - __IOM uint32_t SLPSS_PWRGATE_EN_N_ULP_MCUSTORE2 : 1; /*!< [8..8] MCU Storage 2 power + __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUSTORE2 : 1; /*!< [8..8] MCU Storage 2 power gate enable for 64-bit.if set,power supply is on,clearing this bit has no effect. */ - __IOM uint32_t SLPSS_PWRGATE_EN_N_ULP_MCUSTORE3 : 1; /*!< [9..9] MCU Storage 3 power + __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUSTORE3 : 1; /*!< [9..9] MCU Storage 3 power gate enable for 64-bit.if set,power supply is on,clearing this bit has no effect. */ - __IOM uint32_t SLPSS_PWRGATE_EN_N_ULP_TIMEPERIOD : 1; /*!< [10..10] TIMEPERIOD power + __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_TIMEPERIOD : 1; /*!< [10..10] TIMEPERIOD power gate enable. */ - __IOM uint32_t RESERVED1 : 5; /*!< [15..11] reserved1 */ - __IOM uint32_t SLPSS_PWRGATE_EN_N_ULP_NWPAPB_MCU_CTRL : 1; /*!< [16..16] NWPAPB MCU + __IOM unsigned int RESERVED1 : 5; /*!< [15..11] reserved1 */ + __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_NWPAPB_MCU_CTRL : 1; /*!< [16..16] NWPAPB MCU control power gate enable */ - __IOM uint32_t RESERVED2 : 15; /*!< [31..17] reserved2 */ + __IOM unsigned int RESERVED2 : 15; /*!< [31..17] reserved2 */ } MCUAON_NPSS_PWRCTRL_SET_REG_b; }; union { - __IOM uint32_t MCUAON_NPSS_PWRCTRL_CLEAR_REG; /*!< (@ 0x00000004) This register used + __IOM unsigned int MCUAON_NPSS_PWRCTRL_CLEAR_REG; /*!< (@ 0x00000004) This register used for NPSS power control clear register. */ struct { - __IOM uint32_t RES : 1; /*!< [0..0] bit is reserved */ - __IOM uint32_t SLPSS_PWRGATE_EN_N_ULP_MCUBFFS : 1; /*!< [1..1] MCU domain battery + __IOM unsigned int RES : 1; /*!< [0..0] bit is reserved */ + __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUBFFS : 1; /*!< [1..1] MCU domain battery FF's power gate enable.If set,Power Supply is OFF clearing this bit has no effect. */ - __IOM uint32_t SLPSS_PWRGATE_EN_N_ULP_MCUFSM : 1; /*!< [2..2] MCU FSM power gate + __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUFSM : 1; /*!< [2..2] MCU FSM power gate enable,If set power supply is OFF clearing this bit has no effect. */ - __IOM uint32_t SLPSS_PWRGATE_EN_N_ULP_MCURTC : 1; /*!< [3..3] MCU RTC power gate + __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCURTC : 1; /*!< [3..3] MCU RTC power gate enable if set,power supply is OFF clearing this bit has no effect. */ - __IOM uint32_t SLPSS_PWRGATE_EN_N_ULP_MCUWDT : 1; /*!< [4..4] MCU WDT power gate + __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUWDT : 1; /*!< [4..4] MCU WDT power gate enable if set,power supply is OFF clearing this bit has no effect */ - __IOM uint32_t SLPSS_PWRGATE_EN_N_ULP_MCUPS : 1; /*!< [5..5] MCU PS power gate + __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUPS : 1; /*!< [5..5] MCU PS power gate enable.if set,power supply is OFF clearing this bit has no effect. */ - __IOM uint32_t SLPSS_PWRGATE_EN_N_ULP_MCUTS : 1; /*!< [6..6] MCU temperature sensor + __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUTS : 1; /*!< [6..6] MCU temperature sensor power gate enable if set,power supply is OFF.clearing this bit has no effect */ - __IOM uint32_t SLPSS_PWRGATE_EN_N_ULP_MCUSTORE1 : 1; /*!< [7..7] MCU Storage 1 power + __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUSTORE1 : 1; /*!< [7..7] MCU Storage 1 power gate enable for 64-bit.if set,power supply is OFF,clearing this bit has no effect. */ - __IOM uint32_t SLPSS_PWRGATE_EN_N_ULP_MCUSTORE2 : 1; /*!< [8..8] MCU Storage 2 power + __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUSTORE2 : 1; /*!< [8..8] MCU Storage 2 power gate enable for 64-bit.if set,power supply is OFF,clearing this bit has no effect. */ - __IOM uint32_t SLPSS_PWRGATE_EN_N_ULP_MCUSTORE3 : 1; /*!< [9..9] MCU Storage 3 power + __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUSTORE3 : 1; /*!< [9..9] MCU Storage 3 power gate enable for 64-bit.if set,power supply is OFF,clearing this bit has no effect. */ - __IOM uint32_t SLPSS_PWRGATE_EN_N_ULP_TIMEPERIOD : 1; /*!< [10..10] TIMEPERIOD power + __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_TIMEPERIOD : 1; /*!< [10..10] TIMEPERIOD power gate enable. */ - __IOM uint32_t RESERVED1 : 5; /*!< [15..11] reserved1 */ - __IOM uint32_t SLPSS_PWRGATE_EN_N_ULP_NWPAPB_MCU_CTRL : 1; /*!< [16..16] NWPAPB MCU + __IOM unsigned int RESERVED1 : 5; /*!< [15..11] reserved1 */ + __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_NWPAPB_MCU_CTRL : 1; /*!< [16..16] NWPAPB MCU control power gate enable */ - __IOM uint32_t RESERVED2 : 15; /*!< [31..17] reserved2 */ + __IOM unsigned int RESERVED2 : 15; /*!< [31..17] reserved2 */ } MCUAON_NPSS_PWRCTRL_CLEAR_REG_b; }; - __IM uint32_t RESERVED; + __IM unsigned int RESERVED; union { - __IOM uint32_t MCUAON_IPMU_RESET_CTRL; /*!< (@ 0x0000000C) This register used for ipmu + __IOM unsigned int MCUAON_IPMU_RESET_CTRL; /*!< (@ 0x0000000C) This register used for ipmu reset control register */ struct { - __IOM uint32_t ULP_ANALOG_SPI_RESET_N : 1; /*!< [0..0] ULP Analog SPI Reset Signal, + __IOM unsigned int ULP_ANALOG_SPI_RESET_N : 1; /*!< [0..0] ULP Analog SPI Reset Signal, if bit is 1 then outoff reset,else in reset */ - __IOM uint32_t IPMU_SPI_RESET_N : 1; /*!< [1..1] IPMU SPI Reset Signal,if bit is 1 + __IOM unsigned int IPMU_SPI_RESET_N : 1; /*!< [1..1] IPMU SPI Reset Signal,if bit is 1 then outoff reset,else in reset */ - __IOM uint32_t RESERVED1 : 30; /*!< [31..2] reserved1 */ + __IOM unsigned int RESERVED1 : 30; /*!< [31..2] reserved1 */ } MCUAON_IPMU_RESET_CTRL_b; }; union { - __IOM uint32_t MCUAON_SHELF_MODE; /*!< (@ 0x00000010) This register used for + __IOM unsigned int MCUAON_SHELF_MODE; /*!< (@ 0x00000010) This register used for control shelf mode. */ struct { - __OM uint32_t ENTER_SHELF_MODE : 16; /*!< [15..0] Program 0xAAAA for + __OM unsigned int ENTER_SHELF_MODE : 16; /*!< [15..0] Program 0xAAAA for entering shelf mode. */ - __IOM uint32_t SHUTDOWN_WAKEUP_MODE : 2; /*!< [17..16] GPIO based wakeup + __IOM unsigned int SHUTDOWN_WAKEUP_MODE : 2; /*!< [17..16] GPIO based wakeup mode configuration. */ - __IOM uint32_t SHELF_MODE_GPIOBASED : 1; /*!< [18..18] GPIO based shelf mode + __IOM unsigned int SHELF_MODE_GPIOBASED : 1; /*!< [18..18] GPIO based shelf mode entering,If set 1 by processor, On Falling edge of GPIO (Based on the option used in shutdown_wakeup_mode register) chip will enter Shelf mode. */ - __IOM uint32_t SHELF_MODE_WAKEUP_DELAY : 3; /*!< [21..19] Programmable delay for + __IOM unsigned int SHELF_MODE_WAKEUP_DELAY : 3; /*!< [21..19] Programmable delay for resetting Chip during exit phase of shelf mode. */ - __IOM uint32_t RESERVED1 : 10; /*!< [31..22] reserved1 */ + __IOM unsigned int RESERVED1 : 10; /*!< [31..22] reserved1 */ } MCUAON_SHELF_MODE_b; }; union { - __IOM uint32_t MCUAON_GEN_CTRLS; /*!< (@ 0x00000014) This register used for + __IOM unsigned int MCUAON_GEN_CTRLS; /*!< (@ 0x00000014) This register used for MCUON gen control mode. */ struct { - __IOM uint32_t XTAL_CLK_FROM_GPIO : 1; /*!< [0..0] Select external 32KHz clock from + __IOM unsigned int XTAL_CLK_FROM_GPIO : 1; /*!< [0..0] Select external 32KHz clock from NPSS GPIO's,if bit is 1 then select XTAL clock from GPIO Pins. Please refer to NPSS GPIO Pin muxing for configuration.else select XTAL clock from IPMU clock sources. */ - __IOM uint32_t ULP_ANALOG_WAKEUP_ACCESS : 1; /*!< [1..1] ULP analog wakeup Source + __IOM unsigned int ULP_ANALOG_WAKEUP_ACCESS : 1; /*!< [1..1] ULP analog wakeup Source Access,if bit is 1 then TASS else bit is 0 then M4SS. */ - __IOM uint32_t RES : 14; /*!< [15..2] reser */ - __IOM uint32_t ENABLE_PDO : 1; /*!< [16..16] Enable turning Off POD power + __IOM unsigned int RES : 14; /*!< [15..2] reser */ + __IOM unsigned int ENABLE_PDO : 1; /*!< [16..16] Enable turning Off POD power domain when SOC_LDO EN is low,When Set to 1, Up on SoC LDO Enable going low, IO supply (3.3v)to SOC Pads will be tuned-off. */ - __IOM uint32_t NPSS_SUPPLY_0P9 : 1; /*!< [17..17] keep npss supply always at 0.9V,if + __IOM unsigned int NPSS_SUPPLY_0P9 : 1; /*!< [17..17] keep npss supply always at 0.9V,if bit is 1 then npss supply always at 0.9V else bit is zero then npss supply will switch from 0.6V to 0.9V based on high frequency enables. */ - __IOM uint32_t RESERVED1 : 14; /*!< [31..18] reser */ + __IOM unsigned int RESERVED1 : 14; /*!< [31..18] reser */ } MCUAON_GEN_CTRLS_b; }; union { - __IOM uint32_t MCUAON_PDO_CTRLS; /*!< (@ 0x00000018) This register used for + __IOM unsigned int MCUAON_PDO_CTRLS; /*!< (@ 0x00000018) This register used for MCUON PDO control mode. */ struct { __IOM - uint32_t SOC_B_IO_DOMAIN_EN_B : 1; /*!< [0..0] Turn-Off IO supply of SOC + unsigned int SOC_B_IO_DOMAIN_EN_B : 1; /*!< [0..0] Turn-Off IO supply of SOC domain on bottom side,if bit is 1 then turn-off and 0 then turn on */ - __IOM uint32_t SOC_L_IO_DOMAIN_EN_B : 1; /*!< [1..1] Turn-Off IO supply of SOC domain + __IOM unsigned int SOC_L_IO_DOMAIN_EN_B : 1; /*!< [1..1] Turn-Off IO supply of SOC domain on left side,if bit is 1 then turn-off and 0 then turn on */ - __IOM uint32_t SOC_T_IO_DOMAIN_EN_B : 1; /*!< [2..2] Turn-Off IO supply of SOC domain + __IOM unsigned int SOC_T_IO_DOMAIN_EN_B : 1; /*!< [2..2] Turn-Off IO supply of SOC domain on top side,if bit is 1 then turn-off and 0 then turn on */ - __IOM uint32_t QSPI_IO_DOMAIN_EN_B : 1; /*!< [3..3] Turn-Off IO supply of QSPI + __IOM unsigned int QSPI_IO_DOMAIN_EN_B : 1; /*!< [3..3] Turn-Off IO supply of QSPI domain,if bit is 1 then turn-off and 0 then turn on */ - __IOM uint32_t SDIO_IO_DOMAIN_EN_B : 1; /*!< [4..4] Turn-Off IO supply of SDIO + __IOM unsigned int SDIO_IO_DOMAIN_EN_B : 1; /*!< [4..4] Turn-Off IO supply of SDIO domain.,if bit is 1 then turn-off and 0 then turn on */ - __IOM uint32_t RES : 27; /*!< [31..5] reser */ + __IOM unsigned int RES : 27; /*!< [31..5] reser */ } MCUAON_PDO_CTRLS_b; }; union { - __IOM uint32_t MCUAON_WDT_CHIP_RST; /*!< (@ 0x0000001C) This register used + __IOM unsigned int MCUAON_WDT_CHIP_RST; /*!< (@ 0x0000001C) This register used for wdt chip reset purpose. */ struct { - __IOM uint32_t MCU_WDT_BASED_CHIP_RESET : 1; /*!< [0..0] When cleared, Up on host + __IOM unsigned int MCU_WDT_BASED_CHIP_RESET : 1; /*!< [0..0] When cleared, Up on host reset request.Power-On Reset (POR) will be generated */ - __IOM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + __IOM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ } MCUAON_WDT_CHIP_RST_b; }; union { - __IOM uint32_t MCUAON_KHZ_CLK_SEL_POR_RESET_STATUS; /*!< (@ 0x00000020) This register + __IOM unsigned int MCUAON_KHZ_CLK_SEL_POR_RESET_STATUS; /*!< (@ 0x00000020) This register used for khz clock select and reset status */ struct { - __IOM uint32_t AON_KHZ_CLK_SEL : 3; /*!< [2..0] NPSS AON KHz clock selection,if 001 + __IOM unsigned int AON_KHZ_CLK_SEL : 3; /*!< [2..0] NPSS AON KHz clock selection,if 001 Khz RO clock select,else if 010 - Khz RC clock select,else 100 Khz Xtal clock select */ - __IM uint32_t AON_KHZ_CLK_SEL_CLOCK_SWITCHED : 1; /*!< [3..3] If Khz clock mux + __IM unsigned int AON_KHZ_CLK_SEL_CLOCK_SWITCHED : 1; /*!< [3..3] If Khz clock mux select is modified,please poll this bit and wait till it becomes one. */ #ifdef SLI_SI917B0 - __IOM uint32_t AON_KHZ_CLK_SEL_WWD : 4; /* [4 .. 7] NPSS AON KHz clock + __IOM unsigned int AON_KHZ_CLK_SEL_WWD : 4; /* [4 .. 7] NPSS AON KHz clock selection for WWD */ - __IM uint32_t AON_KHZ_CLK_SEL_CLOCK_SWITCHED_WWD : 1; /*!< [8..8] If Khz clock mux + __IM unsigned int AON_KHZ_CLK_SEL_CLOCK_SWITCHED_WWD : 1; /*!< [8..8] If Khz clock mux select is modified for wwd,please poll this bit and wait till it becomes one. */ - __IOM uint32_t AON_KHZ_CLK_SEL_SYSRTC : 4; /* [9 .. 12] NPSS AON KHz clock + __IOM unsigned int AON_KHZ_CLK_SEL_SYSRTC : 4; /* [9 .. 12] NPSS AON KHz clock selection for SYSRTC */ - __IM uint32_t AON_KHZ_CLK_SEL_CLOCK_SWITCHED_SYSRTC : 1; /*!< [13..13] If Khz clock + __IM unsigned int AON_KHZ_CLK_SEL_CLOCK_SWITCHED_SYSRTC : 1; /*!< [13..13] If Khz clock mux select is modified for sysrtc,please poll this bit and wait till it becomes one. */ - __IOM uint32_t RES : 2; /*!< [14..15] reserved */ + __IOM unsigned int RES : 2; /*!< [14..15] reserved */ #else - __IOM uint32_t RES : 12; /*!< [15..4] reser */ + __IOM unsigned int RES : 12; /*!< [15..4] reser */ #endif - __IOM uint32_t MCU_FIRST_POWERUP_POR : 1; /*!< [16..16] Program this bit to '1' upon + __IOM unsigned int MCU_FIRST_POWERUP_POR : 1; /*!< [16..16] Program this bit to '1' upon power_up.It will be clear when Vbatt power is removed */ - __IOM uint32_t MCU_FIRST_POWERUP_RESET_N : 1; /*!< [17..17] Program this bit to '1' + __IOM unsigned int MCU_FIRST_POWERUP_RESET_N : 1; /*!< [17..17] Program this bit to '1' upon power_up,It will be clear when reset pin is pulled low. */ #ifdef SLI_SI917B0 - __IOM uint32_t SYSRTC_32KHZ_RC_CLK_DIV_FACTOR : 6; /* [18..23] Clock division factor + __IOM unsigned int SYSRTC_32KHZ_RC_CLK_DIV_FACTOR : 6; /* [18..23] Clock division factor for 32Khz_rc_clk (Used in SYSRTC and MCU WWD) */ - __IOM uint32_t RESERVED1 : 8; /*!< [24..31] reserved1 */ + __IOM unsigned int RESERVED1 : 8; /*!< [24..31] reserved1 */ #else - __IOM uint32_t RESERVED1 : 14; /*!< [31..18] reserved1 */ + __IOM unsigned int RESERVED1 : 14; /*!< [31..18] reserved1 */ #endif } MCUAON_KHZ_CLK_SEL_POR_RESET_STATUS_b; }; @@ -13485,689 +13485,689 @@ typedef struct { /*!< (@ 0x24048000) MCU_AON Structure */ typedef struct { /*!< (@ 0x24041400) ULPCLK Structure */ union { - __IOM uint32_t ULP_MISC_SOFT_SET_REG; /*!< (@ 0x00000000) ULP MISC soft + __IOM unsigned int ULP_MISC_SOFT_SET_REG; /*!< (@ 0x00000000) ULP MISC soft register set. */ struct { - __IOM uint32_t PCM_ENABLE_b : 1; /*!< [0..0] Used in pcm */ - __IOM uint32_t PCM_FSYNC_START_b : 1; /*!< [1..1] Used in pcm */ - __IOM uint32_t BIT_RES : 2; /*!< [3..2] Used in pcm */ - __IOM uint32_t IR_PCLK_EN_b : 1; /*!< [4..4] Static clock enable for IR + __IOM unsigned int PCM_ENABLE_b : 1; /*!< [0..0] Used in pcm */ + __IOM unsigned int PCM_FSYNC_START_b : 1; /*!< [1..1] Used in pcm */ + __IOM unsigned int BIT_RES : 2; /*!< [3..2] Used in pcm */ + __IOM unsigned int IR_PCLK_EN_b : 1; /*!< [4..4] Static clock enable for IR APB Interface */ - __IOM uint32_t PCLK_ENABLE_I2C_b : 1; /*!< [5..5] This bit is used as Static enable + __IOM unsigned int PCLK_ENABLE_I2C_b : 1; /*!< [5..5] This bit is used as Static enable for APB clock to I2C module,if bit is zero then clock is disabled else bit is one then clock is enabled. */ - __IOM uint32_t CLK_ENABLE_I2S_b : 1; /*!< [6..6] This bit is used to enable clock to + __IOM unsigned int CLK_ENABLE_I2S_b : 1; /*!< [6..6] This bit is used to enable clock to I2S module if bit is set(1)then clock is enabled is bit is zero then clock disabled. */ - __IOM uint32_t PCLK_ENABLE_SSI_MASTER_b : 1; /*!< [7..7] This bit is used to enable + __IOM unsigned int PCLK_ENABLE_SSI_MASTER_b : 1; /*!< [7..7] This bit is used to enable APB bus clock to SSI master,if bit is zero clock will be available only when the request from the module is present.else bit is one then clock is enabled. */ - __IOM uint32_t SCLK_ENABLE_SSI_MASTER_b : 1; /*!< [8..8] This bit is used to enable + __IOM unsigned int SCLK_ENABLE_SSI_MASTER_b : 1; /*!< [8..8] This bit is used to enable clock serial clock to SSI master,if bit is zero clock will be available only when the request from the module is present.else bit is one then clock is enabled. */ - __IOM uint32_t PCLK_ENABLE_UART_b : 1; /*!< [9..9] This bit is used to enable + __IOM unsigned int PCLK_ENABLE_UART_b : 1; /*!< [9..9] This bit is used to enable peripheral bus clock to UART4,if bit zero then clock will be available only when the request from the module is present or a transaction is pending on the APB bus,else bit is one then clock is enabled. */ - __IOM uint32_t SCLK_ENABLE_UART_b : 1; /*!< [10..10] This bit is used to enable + __IOM unsigned int SCLK_ENABLE_UART_b : 1; /*!< [10..10] This bit is used to enable asynchronous serial clock to UART4,if bit is zero clock will be available only when the request from the module is present.else bit is one then clock is enabled. */ - __IOM uint32_t FIM_PCLK_ENABLE_b : 1; /*!< [11..11] This bit is used to enable clock + __IOM unsigned int FIM_PCLK_ENABLE_b : 1; /*!< [11..11] This bit is used to enable clock to FIM reg file,if this bit is zero then clock will be available only when the request from the module is present else bit is set(1)then clock is enabled. */ - __IOM uint32_t VAD_PCLK_ENABLE_b : 1; /*!< [12..12] This bit is used to enable clock + __IOM unsigned int VAD_PCLK_ENABLE_b : 1; /*!< [12..12] This bit is used to enable clock to FIM reg file,if this bit is zero then clock will be available only when the request from the module is present else bit is set(1)then clock is enabled. */ - __IOM uint32_t CLK_ENABLE_TIMER_b : 1; /*!< [13..13] This bit is used to enable clock + __IOM unsigned int CLK_ENABLE_TIMER_b : 1; /*!< [13..13] This bit is used to enable clock to Timer,if this bit is zero then clock will be available only when the request from the module is present else bit is set(1)then clock is enabled. */ - __IOM uint32_t EGPIO_CLK_EN_b : 1; /*!< [14..14] This bit is used to enable clock to + __IOM unsigned int EGPIO_CLK_EN_b : 1; /*!< [14..14] This bit is used to enable clock to gpio,if this bit is zero then clock will be available only when the request from the module is present else bit is set(1)then clock is enabled. */ - __IOM uint32_t REG_ACCESS_SPI_CLK_EN_b : 1; /*!< [15..15] This bit is used to enable + __IOM unsigned int REG_ACCESS_SPI_CLK_EN_b : 1; /*!< [15..15] This bit is used to enable clock to register access spi,if this bit is zero then clock will be available only when the request from the module is present else bit is set(1)then clock is enabled. */ - __IOM uint32_t FIM_CLK_EN_b : 1; /*!< [16..16] This bit is used to enable clock to + __IOM unsigned int FIM_CLK_EN_b : 1; /*!< [16..16] This bit is used to enable clock to FIM module,if this bit is zero then clock will be gated,else bit is one then clock is enabled. */ - __IOM uint32_t VAD_CLK_EN_b : 1; /*!< [17..17] This bit is used to enable clock to + __IOM unsigned int VAD_CLK_EN_b : 1; /*!< [17..17] This bit is used to enable clock to vad module,if this bit is zero then clock will be gated,else bit is one then clock is enabled. */ - __IOM uint32_t CLK_ENABLE_ULP_MEMORIES_b : 1; /*!< [18..18] This bit is used to + __IOM unsigned int CLK_ENABLE_ULP_MEMORIES_b : 1; /*!< [18..18] This bit is used to enable clock to memories,if this bit is zero then clock will be available only when the request from the module is present else bit is set(1)then clock is enabled. */ - __IOM uint32_t EGPIO_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [19..19] This bit is used to + __IOM unsigned int EGPIO_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [19..19] This bit is used to disable dynamic clock gating on APB clock to egpio */ - __IOM uint32_t EGPIO_PCLK_ENABLE_b : 1; /*!< [20..20] This bit is used to enable + __IOM unsigned int EGPIO_PCLK_ENABLE_b : 1; /*!< [20..20] This bit is used to enable static clock to egpio APB interface */ - __IOM uint32_t TIMER_PCLK_EN_b : 1; /*!< [21..21] This bit is used to enable static + __IOM unsigned int TIMER_PCLK_EN_b : 1; /*!< [21..21] This bit is used to enable static clock to Timer APB Interface */ - __IOM uint32_t AUX_ULP_EXT_TRIG_1_SEL_b : 1; /*!< [22..22] aux adc dac controller + __IOM unsigned int AUX_ULP_EXT_TRIG_1_SEL_b : 1; /*!< [22..22] aux adc dac controller external trigger2 mux select, to choose between ulp gpio aux ext trigger2 and timer interrupt. */ - __IOM uint32_t AUX_ULP_EXT_TRIG_2_SEL_b : 1; /*!< [23..23] aux adc dac controller + __IOM unsigned int AUX_ULP_EXT_TRIG_2_SEL_b : 1; /*!< [23..23] aux adc dac controller external trigger2 mux select, to choose between ulp gpio aux ext trigger2 and timer interrupt. */ - __IOM uint32_t AUX_SOC_EXT_TRIG_1_SEL_b : 1; /*!< [24..24] aux adc dac controller + __IOM unsigned int AUX_SOC_EXT_TRIG_1_SEL_b : 1; /*!< [24..24] aux adc dac controller external trigger3 mux select, to choose between soc aux ext trigger1and soc aux ext trigger3. */ - __IOM uint32_t AUX_SOC_EXT_TRIG_2_SEL_b : 1; /*!< [25..25] aux adc dac controller + __IOM unsigned int AUX_SOC_EXT_TRIG_2_SEL_b : 1; /*!< [25..25] aux adc dac controller external trigger4 mux select, to choose between soc aux ext trigger2and soc aux ext trigger4. */ - __IOM uint32_t ULPSS_M4SS_SLV_SEL_b : 1; /*!< [26..26] select slave */ - __IOM uint32_t ULPSS_TASS_QUASI_SYNC_b : 1; /*!< [27..27] TASS quasi sync */ - __IOM uint32_t RESERVED1 : 2; /*!< [29..28] reserved1 */ - __IOM uint32_t FIM_AHB_CLK_ENABLE_b : 1; /*!< [30..30] static clock enable + __IOM unsigned int ULPSS_M4SS_SLV_SEL_b : 1; /*!< [26..26] select slave */ + __IOM unsigned int ULPSS_TASS_QUASI_SYNC_b : 1; /*!< [27..27] TASS quasi sync */ + __IOM unsigned int RESERVED1 : 2; /*!< [29..28] reserved1 */ + __IOM unsigned int FIM_AHB_CLK_ENABLE_b : 1; /*!< [30..30] static clock enable for FIM AHB interface */ - __IOM uint32_t TOUCH_SENSOR_PCLK_ENABLE_b : 1; /*!< [31..31] Static clock enable for + __IOM unsigned int TOUCH_SENSOR_PCLK_ENABLE_b : 1; /*!< [31..31] Static clock enable for touch APB interface */ } ULP_MISC_SOFT_SET_REG_b; }; union { - __IOM uint32_t ULP_TA_PERI_ISO_REG; /*!< (@ 0x00000004) ULP TA isolation register. */ + __IOM unsigned int ULP_TA_PERI_ISO_REG; /*!< (@ 0x00000004) ULP TA isolation register. */ struct { - __IOM uint32_t UDMA_ISO_CNTRL_b : 1; /*!< [0..0] UDMA module isolation enable,if bit + __IOM unsigned int UDMA_ISO_CNTRL_b : 1; /*!< [0..0] UDMA module isolation enable,if bit is set(1) then enable else bit is zero then disable. */ - __IOM uint32_t IR_ISO_CNTRL_b : 1; /*!< [1..1] IR module isolation enable,if bit is + __IOM unsigned int IR_ISO_CNTRL_b : 1; /*!< [1..1] IR module isolation enable,if bit is set(1) then enable else bit is zero then disable. */ - __IOM uint32_t I2C_ISO_CNTRL_b : 1; /*!< [2..2] I2C module isolation enable,if bit is + __IOM unsigned int I2C_ISO_CNTRL_b : 1; /*!< [2..2] I2C module isolation enable,if bit is set(1) then enable else bit is zero then disable. */ - __IOM uint32_t I2S_ISO_CNTRL_b : 1; /*!< [3..3] I2S module isolation enable,if bit is + __IOM unsigned int I2S_ISO_CNTRL_b : 1; /*!< [3..3] I2S module isolation enable,if bit is set(1) then enable else bit is zero then disable. */ - __IOM uint32_t SSI_ISO_CNTRL_b : 1; /*!< [4..4] SSI module isolation enable ,if bit + __IOM unsigned int SSI_ISO_CNTRL_b : 1; /*!< [4..4] SSI module isolation enable ,if bit is set(1) then enable else bit is zero then disable. */ - __IOM uint32_t UART_ISO_CNTRL_b : 1; /*!< [5..5] UART module isolation enable,if bit + __IOM unsigned int UART_ISO_CNTRL_b : 1; /*!< [5..5] UART module isolation enable,if bit is set(1) then enable else bit is zero then disable. */ - __IOM uint32_t AUX_A2D_ISO_CNTRL_b : 1; /*!< [6..6] AUX a2d module isolation + __IOM unsigned int AUX_A2D_ISO_CNTRL_b : 1; /*!< [6..6] AUX a2d module isolation enable,if bit is set(1) then enable else bit is zero then disable. */ - __IOM uint32_t VAD_ISO_CNTRL_b : 1; /*!< [7..7] VAD module isolation enable,if bit is + __IOM unsigned int VAD_ISO_CNTRL_b : 1; /*!< [7..7] VAD module isolation enable,if bit is set(1) then enable else bit is zero then disable. */ - __IOM uint32_t TOUCH_ISO_CNTRL_b : 1; /*!< [8..8] CAP sensor module isolation + __IOM unsigned int TOUCH_ISO_CNTRL_b : 1; /*!< [8..8] CAP sensor module isolation enable,if bit is set(1) then enable else bit is zero then disable. */ - __IOM uint32_t PROC_MISC_ISO_CNTRL_b : 1; /*!< [9..9] mis top(TOT, semaphore, + __IOM unsigned int PROC_MISC_ISO_CNTRL_b : 1; /*!< [9..9] mis top(TOT, semaphore, interrupt cntrl, Timer) module isolation enable ,if bit is set(1) then enable else bit is zero then disable. */ - __IOM uint32_t RESERVED0 : 1; /*!< [10..10] reserved0 */ - __IOM uint32_t RESERVED1 : 1; /*!< [11..11] reserved1 */ - __IOM uint32_t RESERVED2 : 1; /*!< [12..12] reserved2 */ - __IOM uint32_t RESERVED3 : 1; /*!< [13..13] reserved3 */ - __IOM uint32_t FIM_ISO_CNTRL_b : 1; /*!< [14..14] FIM module isolation enable ,if bit + __IOM unsigned int RESERVED0 : 1; /*!< [10..10] reserved0 */ + __IOM unsigned int RESERVED1 : 1; /*!< [11..11] reserved1 */ + __IOM unsigned int RESERVED2 : 1; /*!< [12..12] reserved2 */ + __IOM unsigned int RESERVED3 : 1; /*!< [13..13] reserved3 */ + __IOM unsigned int FIM_ISO_CNTRL_b : 1; /*!< [14..14] FIM module isolation enable ,if bit is set(1) then enable else bit is zero then disable. */ - __IOM uint32_t MEM_2K_1_ISO_CNTRL_b : 1; /*!< [15..15] 2k SRAM memory isolation + __IOM unsigned int MEM_2K_1_ISO_CNTRL_b : 1; /*!< [15..15] 2k SRAM memory isolation enable ,if bit is set(1) then enable else bit is zero then disable. */ - __IOM uint32_t MEM_2K_2_ISO_CNTRL_b : 1; /*!< [16..16] 2k SRAM memory isolation + __IOM unsigned int MEM_2K_2_ISO_CNTRL_b : 1; /*!< [16..16] 2k SRAM memory isolation enable ,if bit is set(1) then enable else bit is zero then disable. */ - __IOM uint32_t MEM_2K_3_ISO_CNTRL_b : 1; /*!< [17..17] 2k SRAM memory isolation + __IOM unsigned int MEM_2K_3_ISO_CNTRL_b : 1; /*!< [17..17] 2k SRAM memory isolation enable ,if bit is set(1) then enable else bit is zero then disable. */ - __IOM uint32_t MEM_2K_4_ISO_CNTRL_b : 1; /*!< [18..18] 2k SRAM memory isolation + __IOM unsigned int MEM_2K_4_ISO_CNTRL_b : 1; /*!< [18..18] 2k SRAM memory isolation enable ,if bit is set(1) then enable else bit is zero then disable. */ - __IOM uint32_t RESERVED4 : 13; /*!< [31..19] reserved4 */ + __IOM unsigned int RESERVED4 : 13; /*!< [31..19] reserved4 */ } ULP_TA_PERI_ISO_REG_b; }; union { - __IOM uint32_t ULP_TA_PERI_RESET_REG; /*!< (@ 0x00000008) ULP TA peri reset + __IOM unsigned int ULP_TA_PERI_RESET_REG; /*!< (@ 0x00000008) ULP TA peri reset register. */ struct { - __IOM uint32_t UDMA_SOFT_RESET_CNTRL_b : 1; /*!< [0..0] UDMA module soft reset + __IOM unsigned int UDMA_SOFT_RESET_CNTRL_b : 1; /*!< [0..0] UDMA module soft reset enable,if bit is set(1) then out of soft reset else bit is zero then in reset. */ - __IOM uint32_t IR_SOFT_RESET_CNTRL_b : 1; /*!< [1..1] IR module soft reset enable,if + __IOM unsigned int IR_SOFT_RESET_CNTRL_b : 1; /*!< [1..1] IR module soft reset enable,if bit is set(1) then out of soft reset else bit is zero then in reset. */ - __IOM uint32_t I2C_SOFT_RESET_CNTRL_b : 1; /*!< [2..2] I2C module soft reset enable + __IOM unsigned int I2C_SOFT_RESET_CNTRL_b : 1; /*!< [2..2] I2C module soft reset enable ,if bit is set(1) then out of soft reset else bit is zero then in reset. */ - __IOM uint32_t I2S_SOFT_RESET_CNTRL_b : 1; /*!< [3..3] I2S module soft reset enable + __IOM unsigned int I2S_SOFT_RESET_CNTRL_b : 1; /*!< [3..3] I2S module soft reset enable ,if bit is set(1) then out of soft reset else bit is zero then in reset. */ - __IOM uint32_t SSI_SOFT_RESET_CNTRL_b : 1; /*!< [4..4] SSI module soft reset enable + __IOM unsigned int SSI_SOFT_RESET_CNTRL_b : 1; /*!< [4..4] SSI module soft reset enable ,if bit is set(1) then out of soft reset else bit is zero then in reset. */ - __IOM uint32_t UART_SOFT_RESET_CNTRL_b : 1; /*!< [5..5] UART module soft reset enable + __IOM unsigned int UART_SOFT_RESET_CNTRL_b : 1; /*!< [5..5] UART module soft reset enable ,if bit is set(1) then out of soft reset else bit is zero then in reset. */ - __IOM uint32_t AUX_A2D_SOFT_RESET_CNTRL_b : 1; /*!< [6..6] AUX a2d module soft reset + __IOM unsigned int AUX_A2D_SOFT_RESET_CNTRL_b : 1; /*!< [6..6] AUX a2d module soft reset enable,if bit is set(1) then out of soft reset else bit is zero then in reset. */ - __IOM uint32_t VAD_SOFT_RESET_CNTRL_b : 1; /*!< [7..7] VAD module soft reset + __IOM unsigned int VAD_SOFT_RESET_CNTRL_b : 1; /*!< [7..7] VAD module soft reset enable,if bit is set(1) then out of soft reset else bit is zero then in reset. */ - __IOM uint32_t TOUCH_SOFT_RESET_CNTRL_b : 1; /*!< [8..8] CAP Sensor module soft reset + __IOM unsigned int TOUCH_SOFT_RESET_CNTRL_b : 1; /*!< [8..8] CAP Sensor module soft reset enable,if bit is set(1) then out of soft reset else bit is zero then in reset. */ - __IOM uint32_t PROC_MISC_SOFT_RESET_CNTRL_b : 1; /*!< [9..9] mis top(TOT, semaphore, + __IOM unsigned int PROC_MISC_SOFT_RESET_CNTRL_b : 1; /*!< [9..9] mis top(TOT, semaphore, interrupt control, Timer) module soft reset enable,if bit is set(1) then out of soft reset else bit is zero then in reset */ - __IOM uint32_t COMP1_OUTPUT_CNTRL_b : 1; /*!< [10..10] This is ULP comparator1 + __IOM unsigned int COMP1_OUTPUT_CNTRL_b : 1; /*!< [10..10] This is ULP comparator1 interrupt unmasking signal. 0 means comparator1 interrupt is masked and 1 means unmasking. It is masked at power-on time. */ - __IOM uint32_t COMP2_OUTPUT_CNTRL_b : 1; /*!< [11..11] This is ULP comparator2 + __IOM unsigned int COMP2_OUTPUT_CNTRL_b : 1; /*!< [11..11] This is ULP comparator2 interrupt unmasking signal. 0 means comparator2 interrupt is masked and 1 means unmasking. It is masked at power-on time. */ - __IOM uint32_t RESERVED1 : 2; /*!< [13..12] reserved1 */ - __IOM uint32_t FIM_SOFT_RESET_CNTRL_b : 1; /*!< [14..14] FIM module soft reset + __IOM unsigned int RESERVED1 : 2; /*!< [13..12] reserved1 */ + __IOM unsigned int FIM_SOFT_RESET_CNTRL_b : 1; /*!< [14..14] FIM module soft reset enable,if bit is set(1) then out of soft reset else bit is zero then in reset */ - __IOM uint32_t RESERVED2 : 17; /*!< [31..15] reserved2 */ + __IOM unsigned int RESERVED2 : 17; /*!< [31..15] reserved2 */ } ULP_TA_PERI_RESET_REG_b; }; - __IM uint32_t RESERVED[2]; + __IM unsigned int RESERVED[2]; union { - __IOM uint32_t ULP_TA_CLK_GEN_REG; /*!< (@ 0x00000014) ULP TA clock + __IOM unsigned int ULP_TA_CLK_GEN_REG; /*!< (@ 0x00000014) ULP TA clock generation register. */ struct { - __IOM uint32_t ULP2M4_A2A_BRDG_CLK_EN_b : 1; /*!< [0..0] Clock enable for ULP-M4SS + __IOM unsigned int ULP2M4_A2A_BRDG_CLK_EN_b : 1; /*!< [0..0] Clock enable for ULP-M4SS AHB-AHB bridge,if bit is set(1) then enable else bit is zero then in disable */ - __IOM uint32_t ULP_PROC_CLK_SEL : 4; /*!< [4..1] ulp bus clock select. */ - __IOM uint32_t ULP_PROC_CLK_DIV_FACTOR : 8; /*!< [12..5] ulp bus clock + __IOM unsigned int ULP_PROC_CLK_SEL : 4; /*!< [4..1] ulp bus clock select. */ + __IOM unsigned int ULP_PROC_CLK_DIV_FACTOR : 8; /*!< [12..5] ulp bus clock division factor */ - __IOM uint32_t RES : 19; /*!< [31..13] reserved1 */ + __IOM unsigned int RES : 19; /*!< [31..13] reserved1 */ } ULP_TA_CLK_GEN_REG_b; }; union { - __IOM uint32_t ULP_I2C_SSI_CLK_GEN_REG; /*!< (@ 0x00000018) ULP I2C SSI + __IOM unsigned int ULP_I2C_SSI_CLK_GEN_REG; /*!< (@ 0x00000018) ULP I2C SSI clock generation register. */ struct { - __IOM uint32_t ULP_I2C_CLK_EN_b : 1; /*!< [0..0] ulp i2c clock enable,if bit is + __IOM unsigned int ULP_I2C_CLK_EN_b : 1; /*!< [0..0] ulp i2c clock enable,if bit is set(1) then enable else bit is zero then in disable */ - __IOM uint32_t RESERVED1 : 4; /*!< [4..1] reserved1 */ - __IOM uint32_t RESERVED2 : 8; /*!< [12..5] reserved2 */ - __IOM uint32_t RESERVED3 : 3; /*!< [15..13] reserved3 */ - __IOM uint32_t ULP_SSI_CLK_EN_b : 1; /*!< [16..16] ssi clk enable if set(1) then + __IOM unsigned int RESERVED1 : 4; /*!< [4..1] reserved1 */ + __IOM unsigned int RESERVED2 : 8; /*!< [12..5] reserved2 */ + __IOM unsigned int RESERVED3 : 3; /*!< [15..13] reserved3 */ + __IOM unsigned int ULP_SSI_CLK_EN_b : 1; /*!< [16..16] ssi clk enable if set(1) then enable else bit is zero then disable */ - __IOM uint32_t ULP_SSI_CLK_DIV_FACTOR : 7; /*!< [23..17] ssi clk enable if + __IOM unsigned int ULP_SSI_CLK_DIV_FACTOR : 7; /*!< [23..17] ssi clk enable if set(1) then enable else bit is zero then disable */ - __IOM uint32_t RESERVED4 : 4; /*!< [27..24] reserved4 */ - __IOM uint32_t ULP_SSI_CLK_SEL : 4; /*!< [31..28] Ulp ssi clock select. */ + __IOM unsigned int RESERVED4 : 4; /*!< [27..24] reserved4 */ + __IOM unsigned int ULP_SSI_CLK_SEL : 4; /*!< [31..28] Ulp ssi clock select. */ } ULP_I2C_SSI_CLK_GEN_REG_b; }; union { - __IOM uint32_t ULP_I2S_CLK_GEN_REG; /*!< (@ 0x0000001C) ULP I2S clock + __IOM unsigned int ULP_I2S_CLK_GEN_REG; /*!< (@ 0x0000001C) ULP I2S clock generation register. */ struct { - __IOM uint32_t ULP_I2S_CLK_EN_b : 1; /*!< [0..0] ulp i2s clk enable,if bit is set(1) + __IOM unsigned int ULP_I2S_CLK_EN_b : 1; /*!< [0..0] ulp i2s clk enable,if bit is set(1) then enable else bit is zero then in disable */ - __IOM uint32_t ULP_I2S_CLK_SEL_b : 4; /*!< [4..1] ulp i2s clock select. */ - __IOM uint32_t ULP_I2S_CLKDIV_FACTOR : 8; /*!< [12..5] ulp i2s clock + __IOM unsigned int ULP_I2S_CLK_SEL_b : 4; /*!< [4..1] ulp i2s clock select. */ + __IOM unsigned int ULP_I2S_CLKDIV_FACTOR : 8; /*!< [12..5] ulp i2s clock division factor. */ - __IOM uint32_t ULP_I2S_MASTER_SLAVE_MODE_b : 1; /*!< [13..13] i2s master slave mode + __IOM unsigned int ULP_I2S_MASTER_SLAVE_MODE_b : 1; /*!< [13..13] i2s master slave mode decide field. */ - __IOM uint32_t ULP_I2S_SCLK_DYN_CTRL_DISABLE_b : 1; /*!< [14..14] Disable dynamic + __IOM unsigned int ULP_I2S_SCLK_DYN_CTRL_DISABLE_b : 1; /*!< [14..14] Disable dynamic clock gating of System clock in I2S */ - __IOM uint32_t RESERVED1 : 1; /*!< [15..15] reserved1 */ - __IOM uint32_t ULP_I2S_LOOP_BACK_MODE_b : 1; /*!< [16..16] Enables loop + __IOM unsigned int RESERVED1 : 1; /*!< [15..15] reserved1 */ + __IOM unsigned int ULP_I2S_LOOP_BACK_MODE_b : 1; /*!< [16..16] Enables loop back mode in I2S. */ - __IOM uint32_t ULP_I2S_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [17..17] Disable dynamic + __IOM unsigned int ULP_I2S_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [17..17] Disable dynamic clock gating of APB clock in I2S */ - __IOM uint32_t ULP_I2S_PCLK_EN_b : 1; /*!< [18..18] Static clock enable + __IOM unsigned int ULP_I2S_PCLK_EN_b : 1; /*!< [18..18] Static clock enable for APB clock in I2S */ - __IOM uint32_t RESERVED2 : 13; /*!< [31..19] reserved2 */ + __IOM unsigned int RESERVED2 : 13; /*!< [31..19] reserved2 */ } ULP_I2S_CLK_GEN_REG_b; }; union { - __IOM uint32_t ULP_UART_CLK_GEN_REG; /*!< (@ 0x00000020) ulp uart clock + __IOM unsigned int ULP_UART_CLK_GEN_REG; /*!< (@ 0x00000020) ulp uart clock generation register. */ struct { - __IOM uint32_t ULP_UART_FRAC_CLK_SEL_b : 1; /*!< [0..0] ulp uart clk selection,if bit + __IOM unsigned int ULP_UART_FRAC_CLK_SEL_b : 1; /*!< [0..0] ulp uart clk selection,if bit is set(1) then fractional divider output is selected else swallow divider output is selected */ - __IOM uint32_t ULP_UART_CLK_SEL : 4; /*!< [4..1] ulp uart clock select. */ - __IOM uint32_t ULP_UART_CLKDIV_FACTOR : 3; /*!< [7..5] ulp uart clock + __IOM unsigned int ULP_UART_CLK_SEL : 4; /*!< [4..1] ulp uart clock select. */ + __IOM unsigned int ULP_UART_CLKDIV_FACTOR : 3; /*!< [7..5] ulp uart clock division factor */ - __IOM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + __IOM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ } ULP_UART_CLK_GEN_REG_b; }; union { - __IOM uint32_t M4LP_CTRL_REG; /*!< (@ 0x00000024) m4 ulp control register */ + __IOM unsigned int M4LP_CTRL_REG; /*!< (@ 0x00000024) m4 ulp control register */ struct { - __IOM uint32_t RESERVED0 : 2; /*!< [1..0] reserved0 */ - __IOM uint32_t ULP_M4_CORE_CLK_ENABLE_b : 1; /*!< [2..2] Static clock + __IOM unsigned int RESERVED0 : 2; /*!< [1..0] reserved0 */ + __IOM unsigned int ULP_M4_CORE_CLK_ENABLE_b : 1; /*!< [2..2] Static clock enable m4 core in ULP mode,if bit is set(1) then clock enable else clock is disable */ - __IOM uint32_t ULP_MEM_CLK_ULP_ENABLE_b : 1; /*!< [3..3] Static clock enable for M4 + __IOM unsigned int ULP_MEM_CLK_ULP_ENABLE_b : 1; /*!< [3..3] Static clock enable for M4 memories in ULP mode,if bit is set(1) then clock enable else dynamic control */ - __IOM uint32_t ULP_MEM_CLK_ULP_DYN_CTRL_DISABLE_b : 1; /*!< [4..4] Disable the + __IOM unsigned int ULP_MEM_CLK_ULP_DYN_CTRL_DISABLE_b : 1; /*!< [4..4] Disable the dynamic clock gating for M4 memories in ULP mode,if bit is set(1) then dynamic control disabled else dynamic control enabled. */ - __IOM uint32_t RESERVED1 : 27; /*!< [31..5] reserved1 */ + __IOM unsigned int RESERVED1 : 27; /*!< [31..5] reserved1 */ } M4LP_CTRL_REG_b; }; union { - __IOM uint32_t CLOCK_STAUS_REG; /*!< (@ 0x00000028) read clock status register */ + __IOM unsigned int CLOCK_STAUS_REG; /*!< (@ 0x00000028) read clock status register */ struct { - __IM uint32_t CLOCK_SWITCHED_UART_CLK_b : 1; /*!< [0..0] status of clock mux for + __IM unsigned int CLOCK_SWITCHED_UART_CLK_b : 1; /*!< [0..0] status of clock mux for uart,if bit is set(1) then clock is switched,else bit is zero then clock not switched. */ - __IM uint32_t CLOCK_SWITCHED_I2S_CLK_b : 1; /*!< [1..1] Status of clock mux for + __IM unsigned int CLOCK_SWITCHED_I2S_CLK_b : 1; /*!< [1..1] Status of clock mux for i2s,if bit is set(1) then clock is switched,else bit is zero then clock not switched. */ - __IM uint32_t CLOCK_SWITCHED_CORTEX_SLEEP_CLK_b : 1; /*!< [2..2] Status of clock mux + __IM unsigned int CLOCK_SWITCHED_CORTEX_SLEEP_CLK_b : 1; /*!< [2..2] Status of clock mux for m4 sleep clk,if bit is set(1) then clock is switched,else bit is zero then clock not switched. */ - __IM uint32_t CLOCK_SWITCHED_PROC_CLK_b : 1; /*!< [3..3] Status of clock mux for + __IM unsigned int CLOCK_SWITCHED_PROC_CLK_b : 1; /*!< [3..3] Status of clock mux for pclk,if bit is set(1) then clock is switched,else bit is zero then clock not switched. */ - __IM uint32_t CLOCK_SWITCHED_I2C_b : 1; /*!< [4..4] Status of clock mux for i2c,if + __IM unsigned int CLOCK_SWITCHED_I2C_b : 1; /*!< [4..4] Status of clock mux for i2c,if bit is set(1) then clock is switched,else bit is zero then clock not switched. */ - __IM uint32_t CLOCK_SWITCHED_SSI_b : 1; /*!< [5..5] Status of clock mux for ssi,if + __IM unsigned int CLOCK_SWITCHED_SSI_b : 1; /*!< [5..5] Status of clock mux for ssi,if bit is set(1) then clock is switched,else bit is zero then clock not switched. */ - __IM uint32_t CLOCK_SWITCHED_VAD_b : 1; /*!< [6..6] Status of clock mux for vad,if + __IM unsigned int CLOCK_SWITCHED_VAD_b : 1; /*!< [6..6] Status of clock mux for vad,if bit is set(1) then clock is switched,else bit is zero then clock not switched. */ - __IM uint32_t CLOCK_SWITCHED_AUXADC_b : 1; /*!< [7..7] Status of clock mux for aux + __IM unsigned int CLOCK_SWITCHED_AUXADC_b : 1; /*!< [7..7] Status of clock mux for aux adc dac clock,if bit is set(1) then clock is switched,else bit is zero then clock not switched. */ - __IM uint32_t CLOCK_SWITCHED_TIMER_b : 1; /*!< [8..8] Status of clock mux for async + __IM unsigned int CLOCK_SWITCHED_TIMER_b : 1; /*!< [8..8] Status of clock mux for async timers,if bit is set(1) then clock is switched,else bit is zero then clock not switched. */ - __IM uint32_t CLOCK_SWITCHED_TOUCH_SENSOR_b : 1; /*!< [9..9] Status of clock mux for + __IM unsigned int CLOCK_SWITCHED_TOUCH_SENSOR_b : 1; /*!< [9..9] Status of clock mux for touch sensor,if bit is set(1) then clock is switched,else bit is zero then clock not switched. */ - __IM uint32_t CLOCK_SWITCHED_FCLK_VAD_b : 1; /*!< [10..10] Status of clock mux for + __IM unsigned int CLOCK_SWITCHED_FCLK_VAD_b : 1; /*!< [10..10] Status of clock mux for vad fast clock,if bit is set(1) then clock is switched,else bit is zero then clock not switched. */ - __IM uint32_t CLOCK_SWITCHED_SCLK_VAD_b : 1; /*!< [11..11] Status of clock mux for + __IM unsigned int CLOCK_SWITCHED_SCLK_VAD_b : 1; /*!< [11..11] Status of clock mux for vad slow clock,if bit is set(1) then clock is switched,else bit is zero then clock not switched. */ - __IM uint32_t CLOCK_SWITCHED_SYSTICK_b : 1; /*!< [12..12] Status of clock mux for + __IM unsigned int CLOCK_SWITCHED_SYSTICK_b : 1; /*!< [12..12] Status of clock mux for systick clock,if bit is set(1) then clock is switched,else bit is zero then clock not switched. */ - __IOM uint32_t RESERVED1 : 19; /*!< [31..13] reserved1 */ + __IOM unsigned int RESERVED1 : 19; /*!< [31..13] reserved1 */ } CLOCK_STAUS_REG_b; }; union { - __IOM uint32_t ULP_TOUCH_CLK_GEN_REG; /*!< (@ 0x0000002C) ULP touch clock + __IOM unsigned int ULP_TOUCH_CLK_GEN_REG; /*!< (@ 0x0000002C) ULP touch clock generation register */ struct { - __IOM uint32_t ULP_TOUCH_CLK_EN_b : 1; /*!< [0..0] ulp touch clk enable,if bit is + __IOM unsigned int ULP_TOUCH_CLK_EN_b : 1; /*!< [0..0] ulp touch clk enable,if bit is set(1) then enable,else bit is zero then disable. */ - __IOM uint32_t ULP_TOUCH_CLK_SEL : 4; /*!< [4..1] ulp touch clock select. */ - __IOM uint32_t ULP_TOUCH_CLKDIV_FACTOR : 8; /*!< [12..5] ulp touch clock + __IOM unsigned int ULP_TOUCH_CLK_SEL : 4; /*!< [4..1] ulp touch clock select. */ + __IOM unsigned int ULP_TOUCH_CLKDIV_FACTOR : 8; /*!< [12..5] ulp touch clock division factor. */ - __IOM uint32_t RESERVED1 : 19; /*!< [31..13] reserved1 */ + __IOM unsigned int RESERVED1 : 19; /*!< [31..13] reserved1 */ } ULP_TOUCH_CLK_GEN_REG_b; }; union { - __IOM uint32_t ULP_TIMER_CLK_GEN_REG; /*!< (@ 0x00000030) ULP clock + __IOM unsigned int ULP_TIMER_CLK_GEN_REG; /*!< (@ 0x00000030) ULP clock generation for timer */ struct { - __IOM uint32_t RESERVED1 : 1; /*!< [0..0] reserved1 */ - __IOM uint32_t ULP_TIMER_CLK_SEL : 4; /*!< [4..1] ulp timer clock select. */ - __IOM uint32_t RESERVED2 : 8; /*!< [12..5] reserved2 */ - __IOM uint32_t ULP_TIMER_IN_SYNC_b : 1; /*!< [13..13] Ulp timer in synchronous mode + __IOM unsigned int RESERVED1 : 1; /*!< [0..0] reserved1 */ + __IOM unsigned int ULP_TIMER_CLK_SEL : 4; /*!< [4..1] ulp timer clock select. */ + __IOM unsigned int RESERVED2 : 8; /*!< [12..5] reserved2 */ + __IOM unsigned int ULP_TIMER_IN_SYNC_b : 1; /*!< [13..13] Ulp timer in synchronous mode to ULPSS pclk */ - __IOM uint32_t RESERVED3 : 18; /*!< [31..14] reserved3 */ + __IOM unsigned int RESERVED3 : 18; /*!< [31..14] reserved3 */ } ULP_TIMER_CLK_GEN_REG_b; }; union { - __IOM uint32_t ULP_AUXADC_CLK_GEN_REG; /*!< (@ 0x00000034) ULP AUX clock + __IOM unsigned int ULP_AUXADC_CLK_GEN_REG; /*!< (@ 0x00000034) ULP AUX clock generation register */ struct { - __IOM uint32_t ULP_AUX_CLK_EN_b : 1; /*!< [0..0] ulp aux clk enable,if bit is one + __IOM unsigned int ULP_AUX_CLK_EN_b : 1; /*!< [0..0] ulp aux clk enable,if bit is one then clock enable else bit is zero then clock disable. */ - __IOM uint32_t ULP_AUX_CLK_SEL : 4; /*!< [4..1] ulp aux clock select. */ - __IOM uint32_t RESERVED1 : 27; /*!< [31..5] reserved1 */ + __IOM unsigned int ULP_AUX_CLK_SEL : 4; /*!< [4..1] ulp aux clock select. */ + __IOM unsigned int RESERVED1 : 27; /*!< [31..5] reserved1 */ } ULP_AUXADC_CLK_GEN_REG_b; }; union { - __IOM uint32_t ULP_VAD_CLK_GEN_REG; /*!< (@ 0x00000038) ULP vad clock + __IOM unsigned int ULP_VAD_CLK_GEN_REG; /*!< (@ 0x00000038) ULP vad clock generation register */ struct { - __IOM uint32_t ULP_VAD_CLK_EN_b : 1; /*!< [0..0] ulp vad clk enable ,if bit is one + __IOM unsigned int ULP_VAD_CLK_EN_b : 1; /*!< [0..0] ulp vad clk enable ,if bit is one then clock enable else bit is zero then clock disable. */ - __IOM uint32_t ULP_VAD_CLK_SEL : 3; /*!< [3..1] ulp vad clock select. */ - __IOM uint32_t ULP_VAD_FCLK_EN : 1; /*!< [4..4] Enables Fast clock to VAD. */ - __IOM uint32_t ULP_VAD_FCLK_SEL : 4; /*!< [8..5] ulp vad Fast clock select. */ - __IOM uint32_t ULP_VAD_CLKDIV_FACTOR : 8; /*!< [16..9] ulp vad clock + __IOM unsigned int ULP_VAD_CLK_SEL : 3; /*!< [3..1] ulp vad clock select. */ + __IOM unsigned int ULP_VAD_FCLK_EN : 1; /*!< [4..4] Enables Fast clock to VAD. */ + __IOM unsigned int ULP_VAD_FCLK_SEL : 4; /*!< [8..5] ulp vad Fast clock select. */ + __IOM unsigned int ULP_VAD_CLKDIV_FACTOR : 8; /*!< [16..9] ulp vad clock division factor */ - __IOM uint32_t RESERVED1 : 15; /*!< [31..17] reserved1 */ + __IOM unsigned int RESERVED1 : 15; /*!< [31..17] reserved1 */ } ULP_VAD_CLK_GEN_REG_b; }; union { - __IOM uint32_t BYPASS_I2S_CLK_REG; /*!< (@ 0x0000003C) bypass i2s clock register */ + __IOM unsigned int BYPASS_I2S_CLK_REG; /*!< (@ 0x0000003C) bypass i2s clock register */ struct { - __IOM uint32_t BYPASS_I2S_PLL_SEL : 1; /*!< [0..0] Bypass_I2S PLL clock,if + __IOM unsigned int BYPASS_I2S_PLL_SEL : 1; /*!< [0..0] Bypass_I2S PLL clock,if bit is one bypass clock is used else bit is zero then I2S Clock is used. */ - __IOM uint32_t BYPASS_I2S_PLL_CLK_CLN_ON : 1; /*!< [1..1] I2S PLL Bypass + __IOM unsigned int BYPASS_I2S_PLL_CLK_CLN_ON : 1; /*!< [1..1] I2S PLL Bypass clock cleaner ON */ - __IOM uint32_t BYPASS_I2S_PLL_CLK_CLN_OFF : 1; /*!< [2..2] I2S PLL Bypass + __IOM unsigned int BYPASS_I2S_PLL_CLK_CLN_OFF : 1; /*!< [2..2] I2S PLL Bypass clock cleaner OFF */ - __IOM uint32_t RESERVED3 : 29; /*!< [31..3] reserved3 */ + __IOM unsigned int RESERVED3 : 29; /*!< [31..3] reserved3 */ } BYPASS_I2S_CLK_REG_b; }; - __IM uint32_t RESERVED1; + __IM unsigned int RESERVED1; union { - __IOM uint32_t ULP_RM_RME_REG; /*!< (@ 0x00000044) ulp rm rem register */ + __IOM unsigned int ULP_RM_RME_REG; /*!< (@ 0x00000044) ulp rm rem register */ struct { - __IOM uint32_t ULP_MEM_RME_b : 1; /*!< [0..0] RM enable signal for memories internal + __IOM unsigned int ULP_MEM_RME_b : 1; /*!< [0..0] RM enable signal for memories internal tp peripherals. This needs to be programmed when the peripheral memories are not active. */ - __IOM uint32_t ULP_MEM_RM : 2; /*!< [2..1] RM ports for memories internal to + __IOM unsigned int ULP_MEM_RM : 2; /*!< [2..1] RM ports for memories internal to peripheral. This needs to be programmed when the peripheral memories are not active. */ - __IM uint32_t RESERVED1 : 1; /*!< [3..3] reserved1 */ - __IOM uint32_t ULP_MEM_RME_SRAM_b : 1; /*!< [4..4] RM enable signal for + __IM unsigned int RESERVED1 : 1; /*!< [3..3] reserved1 */ + __IOM unsigned int ULP_MEM_RME_SRAM_b : 1; /*!< [4..4] RM enable signal for sram memories. This needs to be programmed when the SRAM is not active. */ - __IOM uint32_t ULP_MEM_RM_SRAM : 2; /*!< [6..5] RM ports for sram memories. This + __IOM unsigned int ULP_MEM_RM_SRAM : 2; /*!< [6..5] RM ports for sram memories. This needs to be programmed when the SRAM is not active */ - __IOM uint32_t RESERVED2 : 25; /*!< [31..7] reserved2 */ + __IOM unsigned int RESERVED2 : 25; /*!< [31..7] reserved2 */ } ULP_RM_RME_REG_b; }; union { - __IOM uint32_t ULP_CLK_ENABLE_REG; /*!< (@ 0x00000048) ulp clock enable register. */ + __IOM unsigned int ULP_CLK_ENABLE_REG; /*!< (@ 0x00000048) ulp clock enable register. */ struct { - __IOM uint32_t ULP_32KHZ_RO_CLK_EN_PROG_b : 1; /*!< [0..0] Static Clock enable to + __IOM unsigned int ULP_32KHZ_RO_CLK_EN_PROG_b : 1; /*!< [0..0] Static Clock enable to iPMU for 32KHz RO Clock,if bit is one(set) then clock enable else not enable. */ - __IOM uint32_t ULP_32KHZ_RC_CLK_EN_PROG_b : 1; /*!< [1..1] Static Clock enable to + __IOM unsigned int ULP_32KHZ_RC_CLK_EN_PROG_b : 1; /*!< [1..1] Static Clock enable to iPMU for 32KHz RC Clock,if bit is one(set) then clock enable else not enable. */ - __IOM uint32_t ULP_32KHZ_XTAL_CLK_EN_PROG_b : 1; /*!< [2..2] Static Clock enable to + __IOM unsigned int ULP_32KHZ_XTAL_CLK_EN_PROG_b : 1; /*!< [2..2] Static Clock enable to iPMU for 32KHz XTAL Clock,if bit is one(set) then clock enable else not enable. */ - __IOM uint32_t ULP_DOUBLER_CLK_EN_PROG_b : 1; /*!< [3..3] Static Clock + __IOM unsigned int ULP_DOUBLER_CLK_EN_PROG_b : 1; /*!< [3..3] Static Clock enable to iPMU for Doubler Clock,if bit is one(set) then clock enable else not enable. */ - __IOM uint32_t ULP_20MHZ_RO_CLK_EN_PROG_b : 1; /*!< [4..4] Static Clock enable to + __IOM unsigned int ULP_20MHZ_RO_CLK_EN_PROG_b : 1; /*!< [4..4] Static Clock enable to iPMU for 20MHz RO clock,if bit is one(set) then clock enable else not enable. */ - __IOM uint32_t ULP_32MHZ_RC_CLK_EN_PROG_b : 1; /*!< [5..5] Static Clock enable to + __IOM unsigned int ULP_32MHZ_RC_CLK_EN_PROG_b : 1; /*!< [5..5] Static Clock enable to iPMU for 32MHz RC Clock,if bit is one(set) then clock enable else not enable. */ - __IOM uint32_t SOC_CLK_EN_PROG_b : 1; /*!< [6..6] Static Clock enable to iPMU for + __IOM unsigned int SOC_CLK_EN_PROG_b : 1; /*!< [6..6] Static Clock enable to iPMU for PLL-500 Clock,if bit is one(set) then clock enable else not enable. */ - __IOM uint32_t I2S_PLLCLK_EN_PROG_b : 1; /*!< [7..7] Static clock enable + __IOM unsigned int I2S_PLLCLK_EN_PROG_b : 1; /*!< [7..7] Static clock enable to iPMU for I2S-PLL Clock,if bit is one(set) then clock enable else not enable. */ - __IOM uint32_t REF_CLK_EN_IPS_PROG_b : 1; /*!< [8..8] Static Clock enable to iPMU for + __IOM unsigned int REF_CLK_EN_IPS_PROG_b : 1; /*!< [8..8] Static Clock enable to iPMU for REF Clock,if bit is one(set) then clock enable else not enable. */ - __IOM uint32_t RESERVED1 : 23; /*!< [31..9] reserved1 */ + __IOM unsigned int RESERVED1 : 23; /*!< [31..9] reserved1 */ } ULP_CLK_ENABLE_REG_b; }; - __IM uint32_t RESERVED2; + __IM unsigned int RESERVED2; union { - __IOM uint32_t SYSTICK_CLK_GEN_REG; /*!< (@ 0x00000050) sys tick clock + __IOM unsigned int SYSTICK_CLK_GEN_REG; /*!< (@ 0x00000050) sys tick clock generation register. */ struct { - __IOM uint32_t SYSTICK_CLK_EN_b : 1; /*!< [0..0] sys tick clock enable ,if bit is + __IOM unsigned int SYSTICK_CLK_EN_b : 1; /*!< [0..0] sys tick clock enable ,if bit is one(set) then clock enable else not enable. */ - __IOM uint32_t SYSTICK_CLK_SEL : 4; /*!< [4..1] sys tick clock select */ - __IOM uint32_t SYSTICK_CLKDIV_FACTOR : 8; /*!< [12..5] sys tick clock + __IOM unsigned int SYSTICK_CLK_SEL : 4; /*!< [4..1] sys tick clock select */ + __IOM unsigned int SYSTICK_CLKDIV_FACTOR : 8; /*!< [12..5] sys tick clock division factor */ - __IOM uint32_t RESERVED1 : 19; /*!< [31..13] reserved1 */ + __IOM unsigned int RESERVED1 : 19; /*!< [31..13] reserved1 */ } SYSTICK_CLK_GEN_REG_b; }; - __IM uint32_t RESERVED3[3]; + __IM unsigned int RESERVED3[3]; __IOM ULPCLK_ULP_SOC_GPIO_MODE_REG_Type ULP_SOC_GPIO_MODE_REG[16]; /*!< (@ 0x00000060) [0..15] */ union { - __IOM uint32_t ULP_DYN_CLK_CTRL_DISABLE; /*!< (@ 0x000000A0) this register used for ULP + __IOM unsigned int ULP_DYN_CLK_CTRL_DISABLE; /*!< (@ 0x000000A0) this register used for ULP dynamic clock control disable. */ struct { - __IOM uint32_t I2C_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [0..0] Dynamic clock control + __IOM unsigned int I2C_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [0..0] Dynamic clock control disable for APB interface in i2c module,if bit is one(set) then dynamic control disabled else bit is zero then Dynamic control enabled. */ - __IOM uint32_t I2S_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [1..1] Dynamic clock control + __IOM unsigned int I2S_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [1..1] Dynamic clock control disable for i2s module,if bit is one(set) then dynamic control disabled else bit is zero then Dynamic control enabled. */ - __IOM uint32_t SSI_MST_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [2..2] Dynamic clock control + __IOM unsigned int SSI_MST_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [2..2] Dynamic clock control disable for pclk ssi module,if bit is one(set) then dynamic control disabled else bit is zero then Dynamic control enabled. */ - __IOM uint32_t SSI_MST_SCLK_DYN_CTRL_DISABLE_b : 1; /*!< [3..3] Dynamic clock control + __IOM unsigned int SSI_MST_SCLK_DYN_CTRL_DISABLE_b : 1; /*!< [3..3] Dynamic clock control disable for ssi module,if bit is one(set) then dynamic control disabled else bit is zero then Dynamic control enabled. */ - __IOM uint32_t UART_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [4..4] Dynamic clock control + __IOM unsigned int UART_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [4..4] Dynamic clock control disable for pclk uart module ,if bit is one(set) then dynamic control disabled else bit is zero then Dynamic control enabled. */ - __IOM uint32_t UART_SCLK_DYN_CTRL_DISABLE_b : 1; /*!< [5..5] Dynamic clock + __IOM unsigned int UART_SCLK_DYN_CTRL_DISABLE_b : 1; /*!< [5..5] Dynamic clock control disable for uart module,if bit is one(set) then dynamic control disabled else bit is zero then Dynamic control enabled. */ - __IOM uint32_t TIMER_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [6..6] Dynamic clock control + __IOM unsigned int TIMER_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [6..6] Dynamic clock control disable for timer pclk module,if bit is one(set) then dynamic control disabled else bit is zero then Dynamic control enabled. */ - __IOM uint32_t TIMER_SCLK_DYN_CTRL_DISABLE_b : 1; /*!< [7..7] Dynamic clock control + __IOM unsigned int TIMER_SCLK_DYN_CTRL_DISABLE_b : 1; /*!< [7..7] Dynamic clock control disable for timer sclk module,if bit is one(set) then dynamic control disabled else bit is zero then Dynamic control enabled. */ - __IOM uint32_t REG_ACCESS_SPI_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [8..8] Dynamic clock + __IOM unsigned int REG_ACCESS_SPI_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [8..8] Dynamic clock control disable for reg access spi module,if bit is one(set) then dynamic control disabled else bit is zero then Dynamic control enabled. */ - __IOM uint32_t FIM_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [9..9] Dynamic clock control + __IOM unsigned int FIM_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [9..9] Dynamic clock control disable for fim module,if bit is one(set) then dynamic control disabled else bit is zero then Dynamic control enabled. */ - __IOM uint32_t VAD_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [10..10] Dynamic clock + __IOM unsigned int VAD_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [10..10] Dynamic clock control disable for vad module,if bit is one(set) then dynamic control disabled else bit is zero then Dynamic control enabled. */ - __IOM uint32_t AUX_PCLK_EN_b : 1; /*!< [11..11] Static Enable for Aux adc pclk. */ - __IOM uint32_t AUX_CLK_EN_b : 1; /*!< [12..12] Static Enable for Aux adc clk. */ - __IOM uint32_t AUX_MEM_EN_b : 1; /*!< [13..13] Static Enable for Aux adc mem. */ - __IOM uint32_t AUX_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [14..14] Dynamic clock control + __IOM unsigned int AUX_PCLK_EN_b : 1; /*!< [11..11] Static Enable for Aux adc pclk. */ + __IOM unsigned int AUX_CLK_EN_b : 1; /*!< [12..12] Static Enable for Aux adc clk. */ + __IOM unsigned int AUX_MEM_EN_b : 1; /*!< [13..13] Static Enable for Aux adc mem. */ + __IOM unsigned int AUX_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [14..14] Dynamic clock control disable for aux adc module,if bit is one(set) then dynamic control disabled else bit is zero then Dynamic control enabled. */ - __IOM uint32_t AUX_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [15..15] Dynamic clock control + __IOM unsigned int AUX_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [15..15] Dynamic clock control disable for aux adc module,if bit is one(set) then dynamic control disabled else bit is zero then Dynamic control enabled. */ - __IOM uint32_t AUX_CLK_MEM_DYN_CTRL_DISABLE_b : 1; /*!< [16..16] Dynamic clock + __IOM unsigned int AUX_CLK_MEM_DYN_CTRL_DISABLE_b : 1; /*!< [16..16] Dynamic clock control disable for aux adc mem,if bit is one(set) then dynamic control disabled else bit is zero then Dynamic control enabled. */ - __IOM uint32_t UDMA_CLK_ENABLE_b : 1; /*!< [17..17] Static Enable for UDMA. */ - __IOM uint32_t IR_CLK_ENABLE_b : 1; /*!< [18..18] Static Enable for IR. */ + __IOM unsigned int UDMA_CLK_ENABLE_b : 1; /*!< [17..17] Static Enable for UDMA. */ + __IOM unsigned int IR_CLK_ENABLE_b : 1; /*!< [18..18] Static Enable for IR. */ __IOM - uint32_t IR_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [19..19] Dynamic clock control + unsigned int IR_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [19..19] Dynamic clock control disable for ir module ,if bit is one(set) then dynamic control disabled else bit is zero then Dynamic control enabled. */ - __IOM uint32_t RESERVED1 : 12; /*!< [31..20] reserved1 */ + __IOM unsigned int RESERVED1 : 12; /*!< [31..20] reserved1 */ } ULP_DYN_CLK_CTRL_DISABLE_b; }; union { - __IOM uint32_t SLP_SENSOR_CLK_REG; /*!< (@ 0x000000A4) this register used + __IOM unsigned int SLP_SENSOR_CLK_REG; /*!< (@ 0x000000A4) this register used for SLP sensor clock register. */ struct { - __IOM uint32_t DIVISON_FACTOR : 8; /*!< [7..0] Division factor for apb interface + __IOM unsigned int DIVISON_FACTOR : 8; /*!< [7..0] Division factor for apb interface clock to sleep sensor subsystem. */ - __IOM uint32_t ENABLE_b : 1; /*!< [8..8] Enable for APB clock to SLPSS */ - __IOM uint32_t RESERVED1 : 23; /*!< [31..9] reserved1 */ + __IOM unsigned int ENABLE_b : 1; /*!< [8..8] Enable for APB clock to SLPSS */ + __IOM unsigned int RESERVED1 : 23; /*!< [31..9] reserved1 */ } SLP_SENSOR_CLK_REG_b; }; } ULPCLK_Type; /*!< Size = 168 (0xa8) */ @@ -14187,120 +14187,120 @@ typedef struct { /*!< (@ 0x24041400) ULPCLK Structure */ typedef struct { /*!< (@ 0x24070000) FIM Structure */ union { - __IOM uint32_t FIM_MODE_INTERRUPT; /*!< (@ 0x00000000) Configuration for FIM Operation + __IOM unsigned int FIM_MODE_INTERRUPT; /*!< (@ 0x00000000) Configuration for FIM Operation Mode and Interrupt Control */ struct { - __IOM uint32_t LATCH_MODE : 1; /*!< [0..0] Enable latch mode */ - __IOM uint32_t OPER_MODE : 8; /*!< [8..1] Indicates the Mode of Operation + __IOM unsigned int LATCH_MODE : 1; /*!< [0..0] Enable latch mode */ + __IOM unsigned int OPER_MODE : 8; /*!< [8..1] Indicates the Mode of Operation to be performed. */ - __IM uint32_t RESERVED1 : 1; /*!< [9..9] reserved1 */ - __OM uint32_t INTR_CLEAR : 1; /*!< [10..10] Writing 1 to this bit clears + __IM unsigned int RESERVED1 : 1; /*!< [9..9] reserved1 */ + __OM unsigned int INTR_CLEAR : 1; /*!< [10..10] Writing 1 to this bit clears the interrupt */ - __IM uint32_t RESERVED2 : 21; /*!< [31..11] reserved2 */ + __IM unsigned int RESERVED2 : 21; /*!< [31..11] reserved2 */ } FIM_MODE_INTERRUPT_b; }; union { - __IOM uint32_t FIM_INP1_ADDR; /*!< (@ 0x00000004) This register used for COP + __IOM unsigned int FIM_INP1_ADDR; /*!< (@ 0x00000004) This register used for COP input address for 0 register. */ struct { - __IOM uint32_t INP1_ADDR : 32; /*!< [31..0] Indicates the Start Address of + __IOM unsigned int INP1_ADDR : 32; /*!< [31..0] Indicates the Start Address of 1st Input Data for FIM Operations */ } FIM_INP1_ADDR_b; }; union { - __IOM uint32_t FIM_INP2_ADDR; /*!< (@ 0x00000008) This register used for COP + __IOM unsigned int FIM_INP2_ADDR; /*!< (@ 0x00000008) This register used for COP input address for 1 register */ struct { - __IOM uint32_t INP2_ADDR : 32; /*!< [31..0] Indicates the Start Address of + __IOM unsigned int INP2_ADDR : 32; /*!< [31..0] Indicates the Start Address of 2nd Input Data for FIM Operations */ } FIM_INP2_ADDR_b; }; union { - __IOM uint32_t FIM_OUT_ADDR; /*!< (@ 0x0000000C) Memory Offset Address for + __IOM unsigned int FIM_OUT_ADDR; /*!< (@ 0x0000000C) Memory Offset Address for Output from FIM Operations */ struct { - __IOM uint32_t OUT_ADDR : 32; /*!< [31..0] Indicates the Start Address of + __IOM unsigned int OUT_ADDR : 32; /*!< [31..0] Indicates the Start Address of Output Data for FIM Operations */ } FIM_OUT_ADDR_b; }; union { - __IOM uint32_t FIM_SCALAR_POLE_DATA1; /*!< (@ 0x00000010) Indicates the Input Scalar + __IOM unsigned int FIM_SCALAR_POLE_DATA1; /*!< (@ 0x00000010) Indicates the Input Scalar Data for Scalar Operations indicates the feedback coefficient for IIR Operations */ struct { - __IOM uint32_t SCALAR_POLE_DATA1 : 32; /*!< [31..0] Pole 0/Scalar Value */ + __IOM unsigned int SCALAR_POLE_DATA1 : 32; /*!< [31..0] Pole 0/Scalar Value */ } FIM_SCALAR_POLE_DATA1_b; }; union { - __IOM uint32_t FIM_POLE_DATA2; /*!< (@ 0x00000014) Feedback coefficient for + __IOM unsigned int FIM_POLE_DATA2; /*!< (@ 0x00000014) Feedback coefficient for IIR filter operation */ struct { - __IOM uint32_t POLE_DATA2 : 32; /*!< [31..0] Indicates the feedback + __IOM unsigned int POLE_DATA2 : 32; /*!< [31..0] Indicates the feedback coefficient for IIR Operations */ } FIM_POLE_DATA2_b; }; union { - __IOM uint32_t FIM_SAT_SHIFT; /*!< (@ 0x00000018) Configuration for precision of Output + __IOM unsigned int FIM_SAT_SHIFT; /*!< (@ 0x00000018) Configuration for precision of Output Data for FIM Operations */ struct { - __IOM uint32_t SAT_VAL : 5; /*!< [4..0] Indicates the number of MSB's to + __IOM unsigned int SAT_VAL : 5; /*!< [4..0] Indicates the number of MSB's to be saturated for Output Data */ - __IOM uint32_t TRUNCATE : 5; /*!< [9..5] Truncate */ - __IOM uint32_t SHIFT_VAL : 6; /*!< [15..10] Indicates the number of bits + __IOM unsigned int TRUNCATE : 5; /*!< [9..5] Truncate */ + __IOM unsigned int SHIFT_VAL : 6; /*!< [15..10] Indicates the number of bits to be right-shifted for Output Data */ - __IOM uint32_t ROUND : 2; /*!< [17..16] Round */ - __IOM uint32_t SAT_EN : 1; /*!< [18..18] Saturation enable bit */ - __IM uint32_t RESERVED2 : 13; /*!< [31..19] reserved2 */ + __IOM unsigned int ROUND : 2; /*!< [17..16] Round */ + __IOM unsigned int SAT_EN : 1; /*!< [18..18] Saturation enable bit */ + __IM unsigned int RESERVED2 : 13; /*!< [31..19] reserved2 */ } FIM_SAT_SHIFT_b; }; union { - __IOM uint32_t FIM_CONFIG_REG1; /*!< (@ 0x0000001C) Configuration Register + __IOM unsigned int FIM_CONFIG_REG1; /*!< (@ 0x0000001C) Configuration Register for FIM Operations. */ struct { - __IOM uint32_t MAT_LEN : 6; /*!< [5..0] Indicates the number of columns in 1st input + __IOM unsigned int MAT_LEN : 6; /*!< [5..0] Indicates the number of columns in 1st input for Matrix Multiplication. This is same as number of rows in 2nd input for Matrix Multiplication. */ - __IOM uint32_t INP1_LEN : 10; /*!< [15..6] Indicates the length of 1st input for FIM + __IOM unsigned int INP1_LEN : 10; /*!< [15..6] Indicates the length of 1st input for FIM Operations other than filtering (FIR, IIR) and Interpolation */ - __IOM uint32_t INP2_LEN : 10; /*!< [25..16] Indicates the length of 2nd input for FIM + __IOM unsigned int INP2_LEN : 10; /*!< [25..16] Indicates the length of 2nd input for FIM Operations other than filtering (FIR, IIR) and Interpolation. */ - __IOM uint32_t DECIM_FAC : 6; /*!< [31..26] Decimation Factor */ + __IOM unsigned int DECIM_FAC : 6; /*!< [31..26] Decimation Factor */ } FIM_CONFIG_REG1_b; }; union { - __IOM uint32_t FIM_CONFIG_REG2; /*!< (@ 0x00000020) Configuration Register + __IOM unsigned int FIM_CONFIG_REG2; /*!< (@ 0x00000020) Configuration Register for FIM Operations */ struct { - __OM uint32_t START_OPER : 1; /*!< [0..0] Start trigger for the FIM operations,this + __OM unsigned int START_OPER : 1; /*!< [0..0] Start trigger for the FIM operations,this is reset upon write register */ - __IOM uint32_t INSTR_BUFF_ENABLE : 1; /*!< [1..1] Instruction buffer enable */ - __IM uint32_t RES : 6; /*!< [7..2] reserved5 */ - __IOM uint32_t CPLX_FLAG : 2; /*!< [9..8] Complex Flag,not valid in matrix mode */ - __IOM uint32_t COL_M2 : 6; /*!< [15..10] Indicates the number of columns + __IOM unsigned int INSTR_BUFF_ENABLE : 1; /*!< [1..1] Instruction buffer enable */ + __IM unsigned int RES : 6; /*!< [7..2] reserved5 */ + __IOM unsigned int CPLX_FLAG : 2; /*!< [9..8] Complex Flag,not valid in matrix mode */ + __IOM unsigned int COL_M2 : 6; /*!< [15..10] Indicates the number of columns in 2nd input for Matrix Multiplication */ - __IOM uint32_t ROW_M1 : 6; /*!< [21..16] Indicates the number of rows in + __IOM unsigned int ROW_M1 : 6; /*!< [21..16] Indicates the number of rows in 1st input for Matrix Multiplication */ - __IOM uint32_t INTRP_FAC : 6; /*!< [27..22] Indicates the Interpolation Factor */ - __IM uint32_t RESERVED1 : 4; /*!< [31..28] reserved1 */ + __IOM unsigned int INTRP_FAC : 6; /*!< [27..22] Indicates the Interpolation Factor */ + __IM unsigned int RESERVED1 : 4; /*!< [31..28] reserved1 */ } FIM_CONFIG_REG2_b; }; } FIM_Type; /*!< Size = 36 (0x24) */ @@ -14319,20 +14319,20 @@ typedef struct { /*!< (@ 0x24070000) FIM Structure */ typedef struct { /*!< (@ 0x41300110) NWP_FSM Structure */ union { - __IOM uint32_t TASS_REF_CLOCK_SELECT; /*!< (@ 0x00000000) TASS REF CLOCK SELECT */ + __IOM unsigned int TASS_REF_CLOCK_SELECT; /*!< (@ 0x00000000) TASS REF CLOCK SELECT */ struct { - __IOM uint32_t M4SS_REF_CLK_SEL_NWP : 3; /*!< [2..0] M4SS REF CLK SEL NWP */ - __IOM uint32_t RESERVED1 : 1; /*!< [3..3] reserved1 */ - __IOM uint32_t ULPSS_REF_CLK_SEL_NWP : 3; /*!< [6..4] ULPSS REF CLK SEL NWP */ - __IOM uint32_t RESERVED2 : 9; /*!< [15..7] reserved2 */ - __IOM uint32_t TASS_REF_CLK_SEL_NWP : 3; /*!< [18..16] TASS REF CLK SEL NWP */ - __IOM uint32_t RESERVED3 : 3; /*!< [21..19] reserved3 */ - __IOM uint32_t TASS_REF_CLK_CLEANER_OFF_NWP : 1; /*!< [22..22] TASS REF CLK CLEANER + __IOM unsigned int M4SS_REF_CLK_SEL_NWP : 3; /*!< [2..0] M4SS REF CLK SEL NWP */ + __IOM unsigned int RESERVED1 : 1; /*!< [3..3] reserved1 */ + __IOM unsigned int ULPSS_REF_CLK_SEL_NWP : 3; /*!< [6..4] ULPSS REF CLK SEL NWP */ + __IOM unsigned int RESERVED2 : 9; /*!< [15..7] reserved2 */ + __IOM unsigned int TASS_REF_CLK_SEL_NWP : 3; /*!< [18..16] TASS REF CLK SEL NWP */ + __IOM unsigned int RESERVED3 : 3; /*!< [21..19] reserved3 */ + __IOM unsigned int TASS_REF_CLK_CLEANER_OFF_NWP : 1; /*!< [22..22] TASS REF CLK CLEANER OFF NWP */ - __IOM uint32_t TASS_REF_CLK_CLEANER_ON_NWP : 1; /*!< [23..23] TASS REF CLK + __IOM unsigned int TASS_REF_CLK_CLEANER_ON_NWP : 1; /*!< [23..23] TASS REF CLK CLEANER ON NWP */ - __IOM uint32_t RESERVED4 : 8; /*!< [31..24] reserved4 */ + __IOM unsigned int RESERVED4 : 8; /*!< [31..24] reserved4 */ } TASS_REF_CLOCK_SELECT_b; }; } NWP_FSM_Type; /*!< Size = 4 (0x4) */ @@ -14352,83 +14352,83 @@ typedef struct { /*!< (@ 0x41300110) NWP_FSM Structure */ typedef struct { /*!< (@ 0x24043A14) OPAMP Structure */ union { - __IOM uint32_t OPAMP_1; /*!< (@ 0x00000000) Programs opamp1 */ + __IOM unsigned int OPAMP_1; /*!< (@ 0x00000000) Programs opamp1 */ struct { - __IOM uint32_t OPAMP1_ENABLE : 1; /*!< [0..0] To enable opamp 1 */ - __IOM uint32_t OPAMP1_LP_MODE : 1; /*!< [1..1] Enable or disable low power mode */ - __IOM uint32_t OPAMP1_R1_SEL : 2; /*!< [3..2] Programmability to select + __IOM unsigned int OPAMP1_ENABLE : 1; /*!< [0..0] To enable opamp 1 */ + __IOM unsigned int OPAMP1_LP_MODE : 1; /*!< [1..1] Enable or disable low power mode */ + __IOM unsigned int OPAMP1_R1_SEL : 2; /*!< [3..2] Programmability to select resister bank R1 */ - __IOM uint32_t OPAMP1_R2_SEL : 3; /*!< [6..4] Programmability to select + __IOM unsigned int OPAMP1_R2_SEL : 3; /*!< [6..4] Programmability to select resister bank R2 */ - __IOM uint32_t OPAMP1_EN_RES_BANK : 1; /*!< [7..7] enables the resistor bank 1 for + __IOM unsigned int OPAMP1_EN_RES_BANK : 1; /*!< [7..7] enables the resistor bank 1 for enable 0 for disable */ - __IOM uint32_t OPAMP1_RES_MUX_SEL : 3; /*!< [10..8] selecting input for + __IOM unsigned int OPAMP1_RES_MUX_SEL : 3; /*!< [10..8] selecting input for registor bank */ - __IOM uint32_t OPAMP1_RES_TO_OUT_VDD : 1; /*!< [11..11] connect resistor bank to out + __IOM unsigned int OPAMP1_RES_TO_OUT_VDD : 1; /*!< [11..11] connect resistor bank to out or vdd i.e 0-out and 1-vdd */ - __IOM uint32_t OPAMP1_OUT_MUX_EN : 1; /*!< [12..12] out mux enable */ - __IOM uint32_t OPAMP1_INN_SEL : 3; /*!< [15..13] selecting -ve input of opamp */ - __IOM uint32_t OPAMP1_INP_SEL : 4; /*!< [19..16] selecting +ve input of opamp */ - __IOM uint32_t OPAMP1_OUT_MUX_SEL : 1; /*!< [20..20] to connect opamp1 + __IOM unsigned int OPAMP1_OUT_MUX_EN : 1; /*!< [12..12] out mux enable */ + __IOM unsigned int OPAMP1_INN_SEL : 3; /*!< [15..13] selecting -ve input of opamp */ + __IOM unsigned int OPAMP1_INP_SEL : 4; /*!< [19..16] selecting +ve input of opamp */ + __IOM unsigned int OPAMP1_OUT_MUX_SEL : 1; /*!< [20..20] to connect opamp1 output to pad */ - __IOM uint32_t MEMS_RES_BANK_EN : 1; /*!< [21..21] enables mems res bank */ - __IOM uint32_t VREF_MUX_EN : 4; /*!< [25..22] vref mux enable */ - __IOM uint32_t MUX_EN : 1; /*!< [26..26] Mux Enable */ - __IOM uint32_t VREF_MUX_SEL : 4; /*!< [30..27] vref mux enable */ - __IOM uint32_t OPAMP1_DYN_EN : 1; /*!< [31..31] dynamic enable for opamp1 */ + __IOM unsigned int MEMS_RES_BANK_EN : 1; /*!< [21..21] enables mems res bank */ + __IOM unsigned int VREF_MUX_EN : 4; /*!< [25..22] vref mux enable */ + __IOM unsigned int MUX_EN : 1; /*!< [26..26] Mux Enable */ + __IOM unsigned int VREF_MUX_SEL : 4; /*!< [30..27] vref mux enable */ + __IOM unsigned int OPAMP1_DYN_EN : 1; /*!< [31..31] dynamic enable for opamp1 */ } OPAMP_1_b; }; union { - __IOM uint32_t OPAMP_2; /*!< (@ 0x00000004) Programs opamp2 */ + __IOM unsigned int OPAMP_2; /*!< (@ 0x00000004) Programs opamp2 */ struct { - __IOM uint32_t OPAMP2_ENABLE : 1; /*!< [0..0] enables the opamp2 */ - __IOM uint32_t OPAMP2_LP_MODE : 1; /*!< [1..1] select the power mode 0-normal mode + __IOM unsigned int OPAMP2_ENABLE : 1; /*!< [0..0] enables the opamp2 */ + __IOM unsigned int OPAMP2_LP_MODE : 1; /*!< [1..1] select the power mode 0-normal mode and 1-low power mode */ - __IOM uint32_t OPAMP2_R1_SEL : 2; /*!< [3..2] Programmability to select + __IOM unsigned int OPAMP2_R1_SEL : 2; /*!< [3..2] Programmability to select resister bank R1 */ - __IOM uint32_t OPAMP2_R2_SEL : 3; /*!< [6..4] Programmability to select + __IOM unsigned int OPAMP2_R2_SEL : 3; /*!< [6..4] Programmability to select resister bank R2 */ - __IOM uint32_t OPAMP2_EN_RES_BANK : 1; /*!< [7..7] enables the resistor bank 1 for + __IOM unsigned int OPAMP2_EN_RES_BANK : 1; /*!< [7..7] enables the resistor bank 1 for enable 0 for disable */ - __IOM uint32_t OPAMP2_RES_MUX_SEL : 3; /*!< [10..8] selecting input for + __IOM unsigned int OPAMP2_RES_MUX_SEL : 3; /*!< [10..8] selecting input for registor bank */ - __IOM uint32_t OPAMP2_RES_TO_OUT_VDD : 2; /*!< [12..11] connect resistor bank to out + __IOM unsigned int OPAMP2_RES_TO_OUT_VDD : 2; /*!< [12..11] connect resistor bank to out or vdd or gnd or DAC i.e 0-out and 1-vdd 2-DAC 3-gnd */ - __IOM uint32_t OPAMP2_OUT_MUX_EN : 1; /*!< [13..13] out mux enable */ - __IOM uint32_t OPAMP2_INN_SEL : 2; /*!< [15..14] selecting -ve input of opamp */ - __IOM uint32_t OPAMP2_INP_SEL : 3; /*!< [18..16] selecting +ve input of opamp2 */ - __IOM uint32_t OPAMP2_DYN_EN : 1; /*!< [19..19] dynamic enable for opamp2 */ - __IOM uint32_t RESERVED1 : 12; /*!< [31..20] res */ + __IOM unsigned int OPAMP2_OUT_MUX_EN : 1; /*!< [13..13] out mux enable */ + __IOM unsigned int OPAMP2_INN_SEL : 2; /*!< [15..14] selecting -ve input of opamp */ + __IOM unsigned int OPAMP2_INP_SEL : 3; /*!< [18..16] selecting +ve input of opamp2 */ + __IOM unsigned int OPAMP2_DYN_EN : 1; /*!< [19..19] dynamic enable for opamp2 */ + __IOM unsigned int RESERVED1 : 12; /*!< [31..20] res */ } OPAMP_2_b; }; union { - __IOM uint32_t OPAMP_3; /*!< (@ 0x00000008) Programs opamp3 */ + __IOM unsigned int OPAMP_3; /*!< (@ 0x00000008) Programs opamp3 */ struct { - __IOM uint32_t OPAMP3_ENABLE : 1; /*!< [0..0] enables the opamp3 1 for + __IOM unsigned int OPAMP3_ENABLE : 1; /*!< [0..0] enables the opamp3 1 for enable 0 for disable */ - __IOM uint32_t OPAMP3_LP_MODE : 1; /*!< [1..1] select the power mode 0-normal mode + __IOM unsigned int OPAMP3_LP_MODE : 1; /*!< [1..1] select the power mode 0-normal mode and 1-low power mode */ - __IOM uint32_t OPAMP3_R1_SEL : 2; /*!< [3..2] Programmability to select + __IOM unsigned int OPAMP3_R1_SEL : 2; /*!< [3..2] Programmability to select resister bank R1 */ - __IOM uint32_t OPAMP3_R2_SEL : 3; /*!< [6..4] Programmability to select + __IOM unsigned int OPAMP3_R2_SEL : 3; /*!< [6..4] Programmability to select resister bank R2 */ - __IOM uint32_t OPAMP3_EN_RES_BANK : 1; /*!< [7..7] enables the resistor bank 1 for + __IOM unsigned int OPAMP3_EN_RES_BANK : 1; /*!< [7..7] enables the resistor bank 1 for enable 0 for disable */ - __IOM uint32_t OPAMP3_RES_MUX_SEL : 3; /*!< [10..8] selecting input for + __IOM unsigned int OPAMP3_RES_MUX_SEL : 3; /*!< [10..8] selecting input for registor bank */ - __IOM uint32_t OPAMP3_RES_TO_OUT_VDD : 1; /*!< [11..11] connect resistor bank to out + __IOM unsigned int OPAMP3_RES_TO_OUT_VDD : 1; /*!< [11..11] connect resistor bank to out or vdd i.e 0-out and 1-vdd */ - __IOM uint32_t OPAMP3_OUT_MUX_EN : 1; /*!< [12..12] out mux enable */ - __IOM uint32_t OPAMP3_INN_SEL : 2; /*!< [14..13] selecting -ve input of opamp */ - __IOM uint32_t OPAMP3_INP_SEL : 3; /*!< [17..15] selecting +ve input of opamp */ - __IOM uint32_t OPAMP3_DYN_EN : 1; /*!< [18..18] dynamic enable for opamp2 */ - __IOM uint32_t RESERVED1 : 13; /*!< [31..19] res */ + __IOM unsigned int OPAMP3_OUT_MUX_EN : 1; /*!< [12..12] out mux enable */ + __IOM unsigned int OPAMP3_INN_SEL : 2; /*!< [14..13] selecting -ve input of opamp */ + __IOM unsigned int OPAMP3_INP_SEL : 3; /*!< [17..15] selecting +ve input of opamp */ + __IOM unsigned int OPAMP3_DYN_EN : 1; /*!< [18..18] dynamic enable for opamp2 */ + __IOM unsigned int RESERVED1 : 13; /*!< [31..19] res */ } OPAMP_3_b; }; } OPAMP_Type; /*!< Size = 12 (0xc) */ @@ -14450,461 +14450,461 @@ typedef struct { /*!< (@ 0x24043A14) OPAMP Structure */ typedef struct { /*!< (@ 0x24043800) AUX_ADC_DAC_COMP Structure */ union { - __IOM uint32_t AUXDAC_CTRL_1; /*!< (@ 0x00000000) Control register1 for DAC */ + __IOM unsigned int AUXDAC_CTRL_1; /*!< (@ 0x00000000) Control register1 for DAC */ struct { - __IOM uint32_t ENDAC_FIFO_CONFIG : 1; /*!< [0..0] This bit activates the + __IOM unsigned int ENDAC_FIFO_CONFIG : 1; /*!< [0..0] This bit activates the DAC path in Aux ADC-DAC controller. Data samples will be played on DAC only when this bit is set. */ - __IOM uint32_t DAC_STATIC_MODE : 1; /*!< [1..1] This bit is used to select + __IOM unsigned int DAC_STATIC_MODE : 1; /*!< [1..1] This bit is used to select non-FIFO mode in DAC. */ - __IOM uint32_t DAC_FIFO_FLUSH : 1; /*!< [2..2] This bit is used to flush + __IOM unsigned int DAC_FIFO_FLUSH : 1; /*!< [2..2] This bit is used to flush the DAC FIFO. */ - __IOM uint32_t DAC_FIFO_THRESHOLD : 3; /*!< [5..3] These bits control the DAC FIFO + __IOM unsigned int DAC_FIFO_THRESHOLD : 3; /*!< [5..3] These bits control the DAC FIFO threshold. When used by DMA, this will act as almost full threshold. For TA, it acts as almost empty threshold */ - __IOM uint32_t DAC_ENABLE_F : 1; /*!< [6..6] This bit is used to enable + __IOM unsigned int DAC_ENABLE_F : 1; /*!< [6..6] This bit is used to enable AUX DAC controller ,valid only when DAC enable is happpen */ - __IOM uint32_t DAC_WORD_MODE : 1; /*!< [7..7] This bit is used to select + __IOM unsigned int DAC_WORD_MODE : 1; /*!< [7..7] This bit is used to select the data size valid on the APB */ - __IOM uint32_t AUX_DAC_MAC_MUX_SEL : 1; /*!< [8..8] It is recommended to + __IOM unsigned int AUX_DAC_MAC_MUX_SEL : 1; /*!< [8..8] It is recommended to write these bits to 0 */ - __IOM uint32_t DAC_FIFO_AEMPTY_THRESHOLD : 4; /*!< [12..9] It is recommended to write + __IOM unsigned int DAC_FIFO_AEMPTY_THRESHOLD : 4; /*!< [12..9] It is recommended to write these bits to 0 */ - __IOM uint32_t DAC_FIFO_AFULL_THRESHOLD : 4; /*!< [16..13] It is recommended to write + __IOM unsigned int DAC_FIFO_AFULL_THRESHOLD : 4; /*!< [16..13] It is recommended to write these bits to 0 */ - __IOM uint32_t RESERVED1 : 15; /*!< [31..9] Reserved1 */ + __IOM unsigned int RESERVED1 : 15; /*!< [31..9] Reserved1 */ } AUXDAC_CTRL_1_b; }; union { - __IOM uint32_t AUXADC_CTRL_1; /*!< (@ 0x00000004) Control register1 for ADC */ + __IOM unsigned int AUXADC_CTRL_1; /*!< (@ 0x00000004) Control register1 for ADC */ struct { - __IOM uint32_t ADC_ENABLE : 1; /*!< [0..0] This bits activates the ADC + __IOM unsigned int ADC_ENABLE : 1; /*!< [0..0] This bits activates the ADC path in Aux ADC-DAC controller. */ - __IOM uint32_t ADC_STATIC_MODE : 1; /*!< [1..1] This bit is used to select + __IOM unsigned int ADC_STATIC_MODE : 1; /*!< [1..1] This bit is used to select non-FIFO mode in ADC. */ - __IOM uint32_t ADC_FIFO_FLUSH : 1; /*!< [2..2] This bit is used to flush + __IOM unsigned int ADC_FIFO_FLUSH : 1; /*!< [2..2] This bit is used to flush the ADC FIFO */ - __IOM uint32_t RESERVED1 : 3; /*!< [5..3] RESERVED1 */ - __IOM uint32_t ADC_MULTIPLE_CHAN_ACTIVE : 1; /*!< [6..6] This bit is used to control + __IOM unsigned int RESERVED1 : 3; /*!< [5..3] RESERVED1 */ + __IOM unsigned int ADC_MULTIPLE_CHAN_ACTIVE : 1; /*!< [6..6] This bit is used to control the auxadc sel signal going to the Aux ADC. */ - __IOM uint32_t ADC_CH_SEL_MSB : 2; /*!< [8..7] It is recommended to write + __IOM unsigned int ADC_CH_SEL_MSB : 2; /*!< [8..7] It is recommended to write these bits to 0 */ - __IOM uint32_t BYPASS_NOISE_AVG : 1; /*!< [9..9] ADC in Bypass noise avg mode. */ - __IOM uint32_t EN_ADC_CLK : 1; /*!< [10..10] Enable AUX ADC Divider output clock */ - __IOM uint32_t ENDIFF : 1; /*!< [11..11] Control to the Aux ADC TODO */ - __IOM uint32_t ADC_CH_SEL_LS : 2; /*!< [13..12] Aux ADC channel number from which the + __IOM unsigned int BYPASS_NOISE_AVG : 1; /*!< [9..9] ADC in Bypass noise avg mode. */ + __IOM unsigned int EN_ADC_CLK : 1; /*!< [10..10] Enable AUX ADC Divider output clock */ + __IOM unsigned int ENDIFF : 1; /*!< [11..11] Control to the Aux ADC TODO */ + __IOM unsigned int ADC_CH_SEL_LS : 2; /*!< [13..12] Aux ADC channel number from which the data has to be sampled This is valid only when adc multiple channel active is zero. When channel number is greater than three, upper bits should also be programmed ADC CHANNEL SELECT MS to bits in this register */ - __IOM uint32_t ADC_WORD_MODE : 1; /*!< [14..14] This bit is used to select the read + __IOM unsigned int ADC_WORD_MODE : 1; /*!< [14..14] This bit is used to select the read data size valid on the APB */ - __IOM uint32_t AUX_ADC_MAC_MUX_SEK : 1; /*!< [15..15] When set, AUX-ADC control is + __IOM unsigned int AUX_ADC_MAC_MUX_SEK : 1; /*!< [15..15] When set, AUX-ADC control is handed over to Aux ADC-ADC controller. By default, AUX-ADC is under the control of baseband. */ __IOM - uint32_t OVERRUN_DMA : 1; /*!< [16..16] overrun bit in dma mode to + unsigned int OVERRUN_DMA : 1; /*!< [16..16] overrun bit in dma mode to enable the over-writing of buffer from beginning when buffer is full. */ - __IOM uint32_t RESERVED2 : 4; /*!< [20..17] Reserved2 */ - __IOM uint32_t ADC_WAKE_UP_TIME : 5; /*!< [25..21] overrun bit in dma mode to enable + __IOM unsigned int RESERVED2 : 4; /*!< [20..17] Reserved2 */ + __IOM unsigned int ADC_WAKE_UP_TIME : 5; /*!< [25..21] overrun bit in dma mode to enable the over-writing of buffer from beginning when buffer is wake up time (number of clock cycles) , dependant upon AUX ADC latency. */ - __IOM uint32_t EN_ADC_TRUN_OFF : 1; /*!< [26..26] Enable power save mode to turn off + __IOM unsigned int EN_ADC_TRUN_OFF : 1; /*!< [26..26] Enable power save mode to turn off AUX ADC when sampling clock is idle and enable it before sampling event, programmed by adc_wake_up_time */ - __IOM uint32_t ADC_NUM_PHASE : 1; /*!< [27..27] ADC number of phase */ - __IOM uint32_t RESERVED3 : 4; /*!< [31..28] Reserved3 */ + __IOM unsigned int ADC_NUM_PHASE : 1; /*!< [27..27] ADC number of phase */ + __IOM unsigned int RESERVED3 : 4; /*!< [31..28] Reserved3 */ } AUXADC_CTRL_1_b; }; union { - __IOM uint32_t AUXDAC_CLK_DIV_FAC; /*!< (@ 0x00000008) DAC clock division register */ + __IOM unsigned int AUXDAC_CLK_DIV_FAC; /*!< (@ 0x00000008) DAC clock division register */ struct { - __IOM uint32_t DAC_CLK_DIV_FAC : 10; /*!< [9..0] These bits control the + __IOM unsigned int DAC_CLK_DIV_FAC : 10; /*!< [9..0] These bits control the DAC clock division factor */ - __IOM uint32_t RESERVED1 : 22; /*!< [31..10] Reserved1 */ + __IOM unsigned int RESERVED1 : 22; /*!< [31..10] Reserved1 */ } AUXDAC_CLK_DIV_FAC_b; }; union { - __IOM uint32_t AUXADC_CLK_DIV_FAC; /*!< (@ 0x0000000C) ADC clock division register */ + __IOM unsigned int AUXADC_CLK_DIV_FAC; /*!< (@ 0x0000000C) ADC clock division register */ struct { - __IOM uint32_t ADC_CLK_DIV_FAC : 10; /*!< [9..0] These bits control the + __IOM unsigned int ADC_CLK_DIV_FAC : 10; /*!< [9..0] These bits control the Total-Duration of the ADC clock */ - __IOM uint32_t RESERVED1 : 6; /*!< [15..10] Reserved1 */ - __IOM uint32_t ADC_CLK_ON_DUR : 9; /*!< [24..16] These bits control the + __IOM unsigned int RESERVED1 : 6; /*!< [15..10] Reserved1 */ + __IOM unsigned int ADC_CLK_ON_DUR : 9; /*!< [24..16] These bits control the On-Duration of the ADC clock */ - __IOM uint32_t RESERVED2 : 7; /*!< [31..25] Reserved2 */ + __IOM unsigned int RESERVED2 : 7; /*!< [31..25] Reserved2 */ } AUXADC_CLK_DIV_FAC_b; }; union { - __IOM uint32_t AUXDAC_DATA_REG; /*!< (@ 0x00000010) Writing to this register will fill + __IOM unsigned int AUXDAC_DATA_REG; /*!< (@ 0x00000010) Writing to this register will fill DAC FIFO for streaming Data to DAC */ struct { - __IOM uint32_t AUXDAC_DATA : 10; /*!< [9..0] Writing to this register will fill DAC + __IOM unsigned int AUXDAC_DATA : 10; /*!< [9..0] Writing to this register will fill DAC FIFO for streaming Data to DAC */ - __IOM uint32_t RESERVED1 : 22; /*!< [31..10] Reserved1 */ + __IOM unsigned int RESERVED1 : 22; /*!< [31..10] Reserved1 */ } AUXDAC_DATA_REG_b; }; union { - __IOM uint32_t AUXADC_DATA; /*!< (@ 0x00000014) AUXADC Data Read through Register. */ + __IOM unsigned int AUXADC_DATA; /*!< (@ 0x00000014) AUXADC Data Read through Register. */ struct { - __IM uint32_t AUXADC_DATA : 12; /*!< [11..0] AUXADC Data Read through Register */ - __IM uint32_t AUXADC_CH_ID : 4; /*!< [15..12] AUXADC Channel ID */ - __IOM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved1 */ + __IM unsigned int AUXADC_DATA : 12; /*!< [11..0] AUXADC Data Read through Register */ + __IM unsigned int AUXADC_CH_ID : 4; /*!< [15..12] AUXADC Channel ID */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved1 */ } AUXADC_DATA_b; }; union { - __IOM uint32_t ADC_DET_THR_CTRL_0; /*!< (@ 0x00000018) ADC detection + __IOM unsigned int ADC_DET_THR_CTRL_0; /*!< (@ 0x00000018) ADC detection threshold control 0 */ struct { - __IOM uint32_t ADC_INPUT_DETECTION_THRESHOLD_0 : 8; /*!< [7..0] The value against + __IOM unsigned int ADC_INPUT_DETECTION_THRESHOLD_0 : 8; /*!< [7..0] The value against which the ADC output has to be compared is to be programmed in this register */ - __IOM uint32_t COMP_LESS_THAN_EN : 1; /*!< [8..8] When set, Aux ADC-DAC controller + __IOM unsigned int COMP_LESS_THAN_EN : 1; /*!< [8..8] When set, Aux ADC-DAC controller raises an interrupt to processor when the Aux ADC output falls below the programmed Aux ADC detection threshold. */ __IOM - uint32_t COMP_GRTR_THAN_EN : 1; /*!< [9..9] When set, Aux ADC-DAC + unsigned int COMP_GRTR_THAN_EN : 1; /*!< [9..9] When set, Aux ADC-DAC controller raises an interrupt to processor when the Aux ADC output is greater than the programmed Aux ADC detection threshold.. */ - __IOM uint32_t COMP_EQ_EN : 1; /*!< [10..10] When set, Aux ADC-DAC controller raises + __IOM unsigned int COMP_EQ_EN : 1; /*!< [10..10] When set, Aux ADC-DAC controller raises an interrupt to processor when the Aux ADC output is equal to the programmed Aux ADC detection threshold */ - __IOM uint32_t RANGE_COMPARISON_ENABLE : 1; /*!< [11..11] When set, Aux ADC-DAC + __IOM unsigned int RANGE_COMPARISON_ENABLE : 1; /*!< [11..11] When set, Aux ADC-DAC controller raises an interrupt to processor when the Aux ADC output falls within the range specified in AUX ADC Detection threshold0 and AUX ADC Detection threshold1 */ - __IOM uint32_t ADC_INPUT_DETECTION_THRESHOLD_1 : 4; /*!< [15..12] Carries upper four + __IOM unsigned int ADC_INPUT_DETECTION_THRESHOLD_1 : 4; /*!< [15..12] Carries upper four bits of ADC detection threshold */ - __IOM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved1 */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved1 */ } ADC_DET_THR_CTRL_0_b; }; union { - __IOM uint32_t ADC_DET_THR_CTRL_1; /*!< (@ 0x0000001C) ADC detection + __IOM unsigned int ADC_DET_THR_CTRL_1; /*!< (@ 0x0000001C) ADC detection threshold control 1 */ struct { - __IOM uint32_t ADC_INPUT_DETECTION_THRESHOLD_2 : 8; /*!< [7..0] The value against + __IOM unsigned int ADC_INPUT_DETECTION_THRESHOLD_2 : 8; /*!< [7..0] The value against which the ADC output has to be compared is to be programmed in this register. */ - __IOM uint32_t COMP_LESS_THAN_EN : 1; /*!< [8..8] When set, Aux ADC-DAC controller + __IOM unsigned int COMP_LESS_THAN_EN : 1; /*!< [8..8] When set, Aux ADC-DAC controller raises an interrupt to TA when the Aux ADC output falls below the programmed Aux ADC detection threshold. */ - __IOM uint32_t COMP_GRTR_THAN_EN : 1; /*!< [9..9] When set, Aux ADC-DAC controller + __IOM unsigned int COMP_GRTR_THAN_EN : 1; /*!< [9..9] When set, Aux ADC-DAC controller raises an interrupt to TA when the Aux ADC output is greater than the programmed Aux ADC detection threshold. */ - __IOM uint32_t COMP_EQ_EN : 1; /*!< [10..10] When set, Aux ADC-DAC controller raises + __IOM unsigned int COMP_EQ_EN : 1; /*!< [10..10] When set, Aux ADC-DAC controller raises an interrupt to TA when the Aux ADC output is equal to the programmed Aux ADC detection threshold. */ - __IOM uint32_t ADC_DETECTION_THRESHOLD_4_UPPER_BITS : 4; /*!< [14..11] Upper 4 bits + __IOM unsigned int ADC_DETECTION_THRESHOLD_4_UPPER_BITS : 4; /*!< [14..11] Upper 4 bits of ADC detection threshold 2 for ADC */ - __IOM uint32_t RESERVED1 : 17; /*!< [31..15] Reserved1 */ + __IOM unsigned int RESERVED1 : 17; /*!< [31..15] Reserved1 */ } ADC_DET_THR_CTRL_1_b; }; union { - __IOM uint32_t INTR_CLEAR_REG; /*!< (@ 0x00000020) ADC detection threshold + __IOM unsigned int INTR_CLEAR_REG; /*!< (@ 0x00000020) ADC detection threshold control 1 */ struct { - __IOM uint32_t CLR_INTR : 1; /*!< [0..0] This bit is used to clear + __IOM unsigned int CLR_INTR : 1; /*!< [0..0] This bit is used to clear threshold detection interrupt */ - __IOM uint32_t RESERVED1 : 7; /*!< [7..1] Reserved1 */ - __IOM uint32_t INTR_CLEAR_REG : 16; /*!< [23..8] If enabled, corresponding + __IOM unsigned int RESERVED1 : 7; /*!< [7..1] Reserved1 */ + __IOM unsigned int INTR_CLEAR_REG : 16; /*!< [23..8] If enabled, corresponding first_mem_switch_intr bits will be cleared. */ - __IOM uint32_t RESERVED2 : 8; /*!< [31..24] Reserved2 */ + __IOM unsigned int RESERVED2 : 8; /*!< [31..24] Reserved2 */ } INTR_CLEAR_REG_b; }; union { - __IOM uint32_t INTR_MASK_REG; /*!< (@ 0x00000024) Mask interrupt register */ + __IOM unsigned int INTR_MASK_REG; /*!< (@ 0x00000024) Mask interrupt register */ struct { - __IOM uint32_t THRESHOLD_DETECTION_INTR_EN : 1; /*!< [0..0] When Cleared, threshold + __IOM unsigned int THRESHOLD_DETECTION_INTR_EN : 1; /*!< [0..0] When Cleared, threshold detection interrupt will be unmasked */ - __IOM uint32_t DAC_FIFO_EMPTY_INTR_MASK : 1; /*!< [1..1] When Cleared, dac_FIFO_empty + __IOM unsigned int DAC_FIFO_EMPTY_INTR_MASK : 1; /*!< [1..1] When Cleared, dac_FIFO_empty interrupt will be unmasked */ - __IOM uint32_t DAC_FIFO_AEMPTY_INTR_MASK : 1; /*!< [2..2] When Cleared, adc FIFO full + __IOM unsigned int DAC_FIFO_AEMPTY_INTR_MASK : 1; /*!< [2..2] When Cleared, adc FIFO full interrupt will be unmasked */ - __IOM uint32_t ADC_FIFO_FULL_INTR_MASK : 1; /*!< [3..3] When Cleared, adc FIFO full + __IOM unsigned int ADC_FIFO_FULL_INTR_MASK : 1; /*!< [3..3] When Cleared, adc FIFO full interrupt will be unmasked */ - __IOM uint32_t ADC_FIFO_AFULL_INTR_MASK : 1; /*!< [4..4] When Cleared, adc FIFO afull + __IOM unsigned int ADC_FIFO_AFULL_INTR_MASK : 1; /*!< [4..4] When Cleared, adc FIFO afull interrupt will be unmasked */ - __IOM uint32_t ADC_FIFO_OVERFLOW_INTR_MASK : 1; /*!< [5..5] When Cleared, dac FIFO + __IOM unsigned int ADC_FIFO_OVERFLOW_INTR_MASK : 1; /*!< [5..5] When Cleared, dac FIFO underrun interrupt will be unmasked */ - __IOM uint32_t DAC_FIFO_UNDERRUN_INTR_MASK : 1; /*!< [6..6] When Cleared, dac FIFO + __IOM unsigned int DAC_FIFO_UNDERRUN_INTR_MASK : 1; /*!< [6..6] When Cleared, dac FIFO underrun interrupt will be unmasked */ - __IOM uint32_t FIRST_MEM_SWITCH_INTR_MASK : 16; /*!< [22..7] When Cleared, + __IOM unsigned int FIRST_MEM_SWITCH_INTR_MASK : 16; /*!< [22..7] When Cleared, first_mem_switch_intr will be unmasked */ - __IOM uint32_t ADC_STATIC_MODE_DATA_INTR_MASK : 1; /*!< [23..23] When Cleared, adc + __IOM unsigned int ADC_STATIC_MODE_DATA_INTR_MASK : 1; /*!< [23..23] When Cleared, adc static_mode_data_intr will be unmasked */ - __IOM uint32_t DAC_STATIC_MODE_DATA_INTR_MASK : 1; /*!< [24..24] When Cleared, dac + __IOM unsigned int DAC_STATIC_MODE_DATA_INTR_MASK : 1; /*!< [24..24] When Cleared, dac static_mode_data_intr will be unmasked */ - __IOM uint32_t RESERVED1 : 7; /*!< [31..25] Reserved1 */ + __IOM unsigned int RESERVED1 : 7; /*!< [31..25] Reserved1 */ } INTR_MASK_REG_b; }; union { - __IM uint32_t INTR_STATUS_REG; /*!< (@ 0x00000028) Status interrupt register */ + __IM unsigned int INTR_STATUS_REG; /*!< (@ 0x00000028) Status interrupt register */ struct { - __IM uint32_t ADC_THRESHOLD_DETECTION_INTR : 1; /*!< [0..0] This bit is set when ADC + __IM unsigned int ADC_THRESHOLD_DETECTION_INTR : 1; /*!< [0..0] This bit is set when ADC threshold matches with the programmed conditions This will be be cleared as soon as this interrupt is acknowledged by processor */ - __IM uint32_t DAC_FIFO_EMPTY : 1; /*!< [1..1] Set when DAC FIFO is empty. This bit + __IM unsigned int DAC_FIFO_EMPTY : 1; /*!< [1..1] Set when DAC FIFO is empty. This bit gets cleared when the DAC FIFO at least a single sample is available in DAC FIFO */ - __IM uint32_t DAC_FIFO_AEMPTY : 1; /*!< [2..2] Set when the FIFO occupancy grater + __IM unsigned int DAC_FIFO_AEMPTY : 1; /*!< [2..2] Set when the FIFO occupancy grater than or equal to DAC FIFO threshold. */ - __IM uint32_t ADC_FIFO_FULL : 1; /*!< [3..3] Set when ADC FIFO is full,This bit gets + __IM unsigned int ADC_FIFO_FULL : 1; /*!< [3..3] Set when ADC FIFO is full,This bit gets cleared when data is read from the FIFO */ - __IM uint32_t ADC_FIFO_AFULL : 1; /*!< [4..4] Set when ADC FIFO occupancy less than + __IM unsigned int ADC_FIFO_AFULL : 1; /*!< [4..4] Set when ADC FIFO occupancy less than or equal to ADC FIFO threshold */ - __IM uint32_t ADC_FIFO_OVERFLOW : 1; /*!< [5..5] Set when a write attempt is made to + __IM unsigned int ADC_FIFO_OVERFLOW : 1; /*!< [5..5] Set when a write attempt is made to ADC FIFO when the FIFO is already full */ - __IM uint32_t DAC_FIFO_UNDERRUN : 1; /*!< [6..6] Set when a read is done on DAC FIFO + __IM unsigned int DAC_FIFO_UNDERRUN : 1; /*!< [6..6] Set when a read is done on DAC FIFO when the FIFO is empty */ - __IM uint32_t FIRST_MEM_SWITCH_INTR : 16; /*!< [22..7] Interrupt + __IM unsigned int FIRST_MEM_SWITCH_INTR : 16; /*!< [22..7] Interrupt indicating the first memory has been filled and the DMA write is being shifted to second memory chunk for ping-pong operation */ - __IM uint32_t ADC_STATIC_MODE_DATA_INTR : 1; /*!< [23..23] Set when a proper data + __IM unsigned int ADC_STATIC_MODE_DATA_INTR : 1; /*!< [23..23] Set when a proper data packet is ready to read in static mode for ADC */ - __IM uint32_t DAC_STATIC_MODE_DATA_INTR : 1; /*!< [24..24] Set when a proper data + __IM unsigned int DAC_STATIC_MODE_DATA_INTR : 1; /*!< [24..24] Set when a proper data packet is ready to read in static mode for DAC */ - __IM uint32_t RESERVED1 : 7; /*!< [31..25] Reserved1 */ + __IM unsigned int RESERVED1 : 7; /*!< [31..25] Reserved1 */ } INTR_STATUS_REG_b; }; union { - __IM uint32_t INTR_MASKED_STATUS_REG; /*!< (@ 0x0000002C) Interrupt masked + __IM unsigned int INTR_MASKED_STATUS_REG; /*!< (@ 0x0000002C) Interrupt masked status register */ struct { - __IM uint32_t ADC_THRESHOLD_DETECTION_INTR_MASKED : 1; /*!< [0..0] Masked Interrupt. + __IM unsigned int ADC_THRESHOLD_DETECTION_INTR_MASKED : 1; /*!< [0..0] Masked Interrupt. This bit is set when ADC threshold matches with the programmed conditions */ - __IM uint32_t DAC_FIFO_EMPTY_MASKED : 1; /*!< [1..1] Masked Interrupt.Set + __IM unsigned int DAC_FIFO_EMPTY_MASKED : 1; /*!< [1..1] Masked Interrupt.Set when DAC FIFO is empty */ - __IM uint32_t DAC_FIFO_AEMPTY_MASKED : 1; /*!< [2..2] Masked Interrupt. Set when the + __IM unsigned int DAC_FIFO_AEMPTY_MASKED : 1; /*!< [2..2] Masked Interrupt. Set when the FIFO occupancy less than equal to DAC FIFO threshold. */ - __IM uint32_t ADC_FIFO_FULL_MASKED : 1; /*!< [3..3] Masked Interrupt. Set + __IM unsigned int ADC_FIFO_FULL_MASKED : 1; /*!< [3..3] Masked Interrupt. Set when ADC FIFO is full. */ - __IM uint32_t ADC_FIFO_AFULL_MASKED : 1; /*!< [4..4] Masked Interrupt. Set when ADC + __IM unsigned int ADC_FIFO_AFULL_MASKED : 1; /*!< [4..4] Masked Interrupt. Set when ADC FIFO occupancy greater than ADC FIFO threshold */ - __IM uint32_t ADC_FIFO_OVERFLOW_MASKED : 1; /*!< [5..5] Masked Interrupt. Set when a + __IM unsigned int ADC_FIFO_OVERFLOW_MASKED : 1; /*!< [5..5] Masked Interrupt. Set when a write attempt is made to ADC FIFO when the FIFO is already full. */ - __IM uint32_t DAC_FIFO_UNDERRUN_MASKED : 1; /*!< [6..6] Masked Interrupt. Set when a + __IM unsigned int DAC_FIFO_UNDERRUN_MASKED : 1; /*!< [6..6] Masked Interrupt. Set when a read is done on DAC FIFO when the FIFO is empty. */ - __IM uint32_t FIRST_MEM_SWITCH_INTR_MASKED : 16; /*!< [22..7] Masked Interrupt + __IM unsigned int FIRST_MEM_SWITCH_INTR_MASKED : 16; /*!< [22..7] Masked Interrupt status indicating the first memory has been filled and the DMA write is being shifted to second memory chunk for ping-pong operation */ - __IM uint32_t ADC_STATIC_MODE_DATA_INTR_MASKED : 1; /*!< [23..23] Masked Interrupt. + __IM unsigned int ADC_STATIC_MODE_DATA_INTR_MASKED : 1; /*!< [23..23] Masked Interrupt. Set when a proper data packet is ready to read in static mode for ADC */ - __IM uint32_t DAC_STATIC_MODE_DATA_INTR_MASKED : 1; /*!< [24..24] Masked Interrupt. + __IM unsigned int DAC_STATIC_MODE_DATA_INTR_MASKED : 1; /*!< [24..24] Masked Interrupt. Set when a proper data packet is ready to read in static mode for DAC */ - __IM uint32_t RESERVED1 : 7; /*!< [31..25] Reserved1 */ + __IM unsigned int RESERVED1 : 7; /*!< [31..25] Reserved1 */ } INTR_MASKED_STATUS_REG_b; }; union { - __IM uint32_t FIFO_STATUS_REG; /*!< (@ 0x00000030) Interrupt masked status + __IM unsigned int FIFO_STATUS_REG; /*!< (@ 0x00000030) Interrupt masked status register */ struct { - __IM uint32_t DAC_FIFO_FULL : 1; /*!< [0..0] Set when DAC FIFO is full. In + __IM unsigned int DAC_FIFO_FULL : 1; /*!< [0..0] Set when DAC FIFO is full. In word mode, FIFO will be shown as full unless there is space for 16-bits. */ - __IM uint32_t DAC_FIFO_AFULL : 1; /*!< [1..1] Set when DAC FIFO occupancy + __IM unsigned int DAC_FIFO_AFULL : 1; /*!< [1..1] Set when DAC FIFO occupancy greater than FIFO threshold */ - __IM uint32_t ADC_FIFO_EMPTY : 1; /*!< [2..2] Set when FIFO is empty. This bit gets + __IM unsigned int ADC_FIFO_EMPTY : 1; /*!< [2..2] Set when FIFO is empty. This bit gets cleared when the ADC FIFO is not empty. */ - __IM uint32_t ADC_FIFO_AEMPTY : 1; /*!< [3..3] Set when the FIFO occupancy + __IM unsigned int ADC_FIFO_AEMPTY : 1; /*!< [3..3] Set when the FIFO occupancy less than ADC FIFO threshold */ - __IM uint32_t DAC_FIFO_EMPTY : 1; /*!< [4..4] Set when FIFO is empty. This bit gets + __IM unsigned int DAC_FIFO_EMPTY : 1; /*!< [4..4] Set when FIFO is empty. This bit gets cleared when the DAC FIFO is not empty. */ - __IM uint32_t DAC_FIFO_AEMPTY : 1; /*!< [5..5] Set when the FIFO occupancy + __IM unsigned int DAC_FIFO_AEMPTY : 1; /*!< [5..5] Set when the FIFO occupancy less than DAC FIFO threshold */ - __IM uint32_t ADC_FIFO_FULL : 1; /*!< [6..6] Set when ADC FIFO is full. + __IM unsigned int ADC_FIFO_FULL : 1; /*!< [6..6] Set when ADC FIFO is full. This bit gets cleared when data is read from the FIFO. */ - __IM uint32_t ADC_FIFO_AFULL : 1; /*!< [7..7] Set when ADC FIFO occupancy + __IM unsigned int ADC_FIFO_AFULL : 1; /*!< [7..7] Set when ADC FIFO occupancy greater than ADC FIFO threshold. */ - __IM uint32_t RESERVED1 : 24; /*!< [31..8] Reserved1 */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] Reserved1 */ } FIFO_STATUS_REG_b; }; union { - __IOM uint32_t ADC_CTRL_REG_2; /*!< (@ 0x00000034) ADC Control register2 */ + __IOM unsigned int ADC_CTRL_REG_2; /*!< (@ 0x00000034) ADC Control register2 */ struct { - __IOM uint32_t EXT_TRIG_DETECT_1 : 2; /*!< [1..0] Condition to detect event on + __IOM unsigned int EXT_TRIG_DETECT_1 : 2; /*!< [1..0] Condition to detect event on external trigger 1 00: None (trigger disabled) 01: Positive edge 10: Negative edge 11: Positive or negative edge. */ - __IOM uint32_t EXT_TRIG_DETECT_2 : 2; /*!< [3..2] Condition to detect event on + __IOM unsigned int EXT_TRIG_DETECT_2 : 2; /*!< [3..2] Condition to detect event on external trigger 2 00: None (trigger disabled) 01: Positive edge 10: Negative edge 11: Positive or negative edge. */ - __IOM uint32_t EXT_TRIG_DETECT_3 : 2; /*!< [5..4] Condition to detect event on + __IOM unsigned int EXT_TRIG_DETECT_3 : 2; /*!< [5..4] Condition to detect event on external trigger 3 00: None (trigger disabled) 01: Positive edge 10: Negative edge 11: Positive or negative edge. */ - __IOM uint32_t EXT_TRIG_DETECT_4 : 2; /*!< [7..6] Condition to detect event on + __IOM unsigned int EXT_TRIG_DETECT_4 : 2; /*!< [7..6] Condition to detect event on external trigger 4 00: None (trigger disabled) 01: Positive edge 10: Negative edge 11: Positive or negative edge. */ - __IOM uint32_t EXT_TRIGGER_SEL_4 : 4; /*!< [11..8] 4-bit Channel ID corresponding to + __IOM unsigned int EXT_TRIGGER_SEL_4 : 4; /*!< [11..8] 4-bit Channel ID corresponding to external trigger 4. */ - __IOM uint32_t EXT_TRIGGER_SEL_3 : 4; /*!< [15..12] 4-bit Channel ID corresponding to + __IOM unsigned int EXT_TRIGGER_SEL_3 : 4; /*!< [15..12] 4-bit Channel ID corresponding to external trigger 3. */ - __IOM uint32_t EXT_TRIGGER_SEL_2 : 4; /*!< [19..16] Enable bit corresponding to + __IOM unsigned int EXT_TRIGGER_SEL_2 : 4; /*!< [19..16] Enable bit corresponding to channel id selected for trigger 2. */ - __IOM uint32_t EXT_TRIGGER_SEL_1 : 4; /*!< [23..20] 4-bit Channel ID corresponding to + __IOM unsigned int EXT_TRIGGER_SEL_1 : 4; /*!< [23..20] 4-bit Channel ID corresponding to external trigger 1. */ - __IOM uint32_t TRIG_1_MATCH : 1; /*!< [24..24] indicating trigger 1 is matched. Write + __IOM unsigned int TRIG_1_MATCH : 1; /*!< [24..24] indicating trigger 1 is matched. Write 1 to clear this bit. */ - __IOM uint32_t TRIG_2_MATCH : 1; /*!< [25..25] indicating trigger 2 is matched. Write + __IOM unsigned int TRIG_2_MATCH : 1; /*!< [25..25] indicating trigger 2 is matched. Write 1 to clear this bit. */ - __IOM uint32_t TRIG_3_MATCH : 1; /*!< [26..26] indicating trigger 3 is matched. Write + __IOM unsigned int TRIG_3_MATCH : 1; /*!< [26..26] indicating trigger 3 is matched. Write 1 to clear this bit. */ - __IOM uint32_t TRIG_4_MATCH : 1; /*!< [27..27] indicating trigger 4 is matched. Write + __IOM unsigned int TRIG_4_MATCH : 1; /*!< [27..27] indicating trigger 4 is matched. Write 1 to clear this bit. */ - __IOM uint32_t RESERVED1 : 4; /*!< [31..28] Reserved1 */ + __IOM unsigned int RESERVED1 : 4; /*!< [31..28] Reserved1 */ } ADC_CTRL_REG_2_b; }; __IOM AUX_ADC_DAC_COMP_ADC_CH_BIT_MAP_CONFIG_Type ADC_CH_BIT_MAP_CONFIG[16]; /*!< (@ 0x00000038) [0..15] */ union { - __IOM uint32_t ADC_CH_OFFSET[16]; /*!< (@ 0x00000138) This Register specifies initial + __IOM unsigned int ADC_CH_OFFSET[16]; /*!< (@ 0x00000138) This Register specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled. */ struct { - __IOM uint32_t CH_OFFSET : 16; /*!< [15..0] This Register field specifies initial + __IOM unsigned int CH_OFFSET : 16; /*!< [15..0] This Register field specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled. */ - __IOM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved1 */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved1 */ } ADC_CH_OFFSET_b[16]; }; union { - __IOM uint32_t ADC_CH_FREQ[16]; /*!< (@ 0x00000178) This register specifies Sampling + __IOM unsigned int ADC_CH_FREQ[16]; /*!< (@ 0x00000178) This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel(1 to 16 ) */ struct { - __IOM uint32_t CH_FREQ_VALUE : 16; /*!< [15..0] This register specifies Sampling + __IOM unsigned int CH_FREQ_VALUE : 16; /*!< [15..0] This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel all respective channel (1-16) */ - __IOM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved1 */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved1 */ } ADC_CH_FREQ_b[16]; }; union { - __IOM uint32_t ADC_CH_PHASE_1; /*!< (@ 0x000001B8) ADC Channel Phase 1 */ + __IOM unsigned int ADC_CH_PHASE_1; /*!< (@ 0x000001B8) ADC Channel Phase 1 */ struct { - __IOM uint32_t CH1_PHASE : 4; /*!< [3..0] Phase corresponding to channel-1 */ - __IOM uint32_t CH2_PHASE : 4; /*!< [7..4] Phase corresponding to channel-2 */ - __IOM uint32_t CH3_PHASE : 4; /*!< [11..8] Phase corresponding to channel-3 */ - __IOM uint32_t CH4_PHASE : 4; /*!< [15..12] Phase corresponding to channel-4 */ - __IOM uint32_t CH5_PHASE : 4; /*!< [19..16] Phase corresponding to channel-5 */ - __IOM uint32_t CH6_PHASE : 4; /*!< [23..20] Phase corresponding to channel-6 */ - __IOM uint32_t CH7_PHASE : 4; /*!< [27..24] Phase corresponding to channel-7 */ - __IOM uint32_t CH8_PHASE : 4; /*!< [31..28] Phase corresponding to channel-8 */ + __IOM unsigned int CH1_PHASE : 4; /*!< [3..0] Phase corresponding to channel-1 */ + __IOM unsigned int CH2_PHASE : 4; /*!< [7..4] Phase corresponding to channel-2 */ + __IOM unsigned int CH3_PHASE : 4; /*!< [11..8] Phase corresponding to channel-3 */ + __IOM unsigned int CH4_PHASE : 4; /*!< [15..12] Phase corresponding to channel-4 */ + __IOM unsigned int CH5_PHASE : 4; /*!< [19..16] Phase corresponding to channel-5 */ + __IOM unsigned int CH6_PHASE : 4; /*!< [23..20] Phase corresponding to channel-6 */ + __IOM unsigned int CH7_PHASE : 4; /*!< [27..24] Phase corresponding to channel-7 */ + __IOM unsigned int CH8_PHASE : 4; /*!< [31..28] Phase corresponding to channel-8 */ } ADC_CH_PHASE_1_b; }; union { - __IOM uint32_t ADC_CH_PHASE_2; /*!< (@ 0x000001BC) ADC Channel Phase 2 */ + __IOM unsigned int ADC_CH_PHASE_2; /*!< (@ 0x000001BC) ADC Channel Phase 2 */ struct { - __IOM uint32_t CH9_PHASE : 4; /*!< [3..0] Phase corresponding to channel-9 */ - __IOM uint32_t CH10_PHASE : 4; /*!< [7..4] Phase corresponding to channel-10 */ - __IOM uint32_t CH11_PHASE : 4; /*!< [11..8] Phase corresponding to channel-11 */ - __IOM uint32_t CH12_PHASE : 4; /*!< [15..12] Phase corresponding to channel-12 */ - __IOM uint32_t CH13_PHASE : 4; /*!< [19..16] Phase corresponding to channel-13 */ - __IOM uint32_t CH14_PHASE : 4; /*!< [23..20] Phase corresponding to channel-14 */ - __IOM uint32_t CH15_PHASE : 4; /*!< [27..24] Phase corresponding to channel-15 */ - __IOM uint32_t CH16_PHASE : 4; /*!< [31..28] Phase corresponding to channel-16 */ + __IOM unsigned int CH9_PHASE : 4; /*!< [3..0] Phase corresponding to channel-9 */ + __IOM unsigned int CH10_PHASE : 4; /*!< [7..4] Phase corresponding to channel-10 */ + __IOM unsigned int CH11_PHASE : 4; /*!< [11..8] Phase corresponding to channel-11 */ + __IOM unsigned int CH12_PHASE : 4; /*!< [15..12] Phase corresponding to channel-12 */ + __IOM unsigned int CH13_PHASE : 4; /*!< [19..16] Phase corresponding to channel-13 */ + __IOM unsigned int CH14_PHASE : 4; /*!< [23..20] Phase corresponding to channel-14 */ + __IOM unsigned int CH15_PHASE : 4; /*!< [27..24] Phase corresponding to channel-15 */ + __IOM unsigned int CH16_PHASE : 4; /*!< [31..28] Phase corresponding to channel-16 */ } ADC_CH_PHASE_2_b; }; - __IM uint32_t RESERVED; + __IM unsigned int RESERVED; union { - __IOM uint32_t ADC_SINGLE_CH_CTRL_1; /*!< (@ 0x000001C4) ADC SINGLE Channel + __IOM unsigned int ADC_SINGLE_CH_CTRL_1; /*!< (@ 0x000001C4) ADC SINGLE Channel Configuration */ struct { - __IOM uint32_t ADC_CH_INDEX_SINGLE_CHAN_1 : 32; /*!< [31..0] [31:0]out of total 48 + __IOM unsigned int ADC_CH_INDEX_SINGLE_CHAN_1 : 32; /*!< [31..0] [31:0]out of total 48 bits of bit map for single channel mode of a particular channel. */ @@ -14912,45 +14912,45 @@ typedef struct { /*!< (@ 0x24043800) AUX_ADC_DAC_COMP Structure */ }; union { - __IOM uint32_t ADC_SINGLE_CH_CTRL_2; /*!< (@ 0x000001C8) ADC SINGLE Channel + __IOM unsigned int ADC_SINGLE_CH_CTRL_2; /*!< (@ 0x000001C8) ADC SINGLE Channel Configuration */ struct { - __IOM uint32_t ADC_CH_INDEX_SINGLE_CHAN_2 : 16; /*!< [15..0] [47:32] out of total 48 + __IOM unsigned int ADC_CH_INDEX_SINGLE_CHAN_2 : 16; /*!< [15..0] [47:32] out of total 48 bits of bit map for single channel mode of a particular channel. */ - __IOM uint32_t ADC_INTERPOL_SINGLE_CHAN : 2; /*!< [17..16] Interpolation angle for + __IOM unsigned int ADC_INTERPOL_SINGLE_CHAN : 2; /*!< [17..16] Interpolation angle for the particular channel in single channel mode whose bit sequence has been written to adc_ch_index_single_c an. */ - __IOM uint32_t RESERVED1 : 14; /*!< [31..18] Reserved1 */ + __IOM unsigned int RESERVED1 : 14; /*!< [31..18] Reserved1 */ } ADC_SINGLE_CH_CTRL_2_b; }; union { - __IOM uint32_t ADC_SEQ_CTRL; /*!< (@ 0x000001CC) This register explain + __IOM unsigned int ADC_SEQ_CTRL; /*!< (@ 0x000001CC) This register explain configuration parameter for AUXADC */ struct { - __IOM uint32_t ADC_SEQ_CTRL_PING_PONG : 16; /*!< [15..0] To enable/disable per + __IOM unsigned int ADC_SEQ_CTRL_PING_PONG : 16; /*!< [15..0] To enable/disable per channel DAM mode (One-hot coding) */ - __IOM uint32_t ADC_SEQ_CTRL_DMA_MODE : 16; /*!< [31..16] To enable/disable per + __IOM unsigned int ADC_SEQ_CTRL_DMA_MODE : 16; /*!< [31..16] To enable/disable per channel ping-pong operation (One-hot coding). */ } ADC_SEQ_CTRL_b; }; union { - __IOM uint32_t VAD_BBP_ID; /*!< (@ 0x000001D0) This register explain VDD BBP ID */ + __IOM unsigned int VAD_BBP_ID; /*!< (@ 0x000001D0) This register explain VDD BBP ID */ struct { - __IOM uint32_t BPP_ID : 4; /*!< [3..0] Channel id for bbp samples. */ - __IOM uint32_t BPP_EN : 1; /*!< [4..4] Enables Aux-ADC samples to BBP */ - __IOM uint32_t AUX_ADC_BPP_EN : 1; /*!< [5..5] Enable Indication for BBP */ - __IOM uint32_t RESERVED1 : 10; /*!< [15..6] RESERVED1 */ - __IOM uint32_t DISCONNET_MODE : 16; /*!< [31..16] Per channel discontinuous mode + __IOM unsigned int BPP_ID : 4; /*!< [3..0] Channel id for bbp samples. */ + __IOM unsigned int BPP_EN : 1; /*!< [4..4] Enables Aux-ADC samples to BBP */ + __IOM unsigned int AUX_ADC_BPP_EN : 1; /*!< [5..5] Enable Indication for BBP */ + __IOM unsigned int RESERVED1 : 10; /*!< [15..6] RESERVED1 */ + __IOM unsigned int DISCONNET_MODE : 16; /*!< [31..16] Per channel discontinuous mode enable signal. When discontinuous mode is enabled, data is sampled only once from that channel and the enable bit is reset to 0. */ @@ -14958,12 +14958,12 @@ typedef struct { /*!< (@ 0x24043800) AUX_ADC_DAC_COMP Structure */ }; union { - __IOM uint32_t ADC_INT_MEM_1; /*!< (@ 0x000001D4) This register explain start address + __IOM unsigned int ADC_INT_MEM_1; /*!< (@ 0x000001D4) This register explain start address of first/second buffer corresponding to the channel location ADC INT MEM 2 */ struct { - __IOM uint32_t PROG_WR_DATA : 32; /*!< [31..0] These 32-bits specifies the + __IOM unsigned int PROG_WR_DATA : 32; /*!< [31..0] These 32-bits specifies the start address of first/second buffer corresponding to the channel location ADC INT MEM */ @@ -14971,33 +14971,33 @@ typedef struct { /*!< (@ 0x24043800) AUX_ADC_DAC_COMP Structure */ }; union { - __IOM uint32_t ADC_INT_MEM_2; /*!< (@ 0x000001D8) This register explain ADC + __IOM unsigned int ADC_INT_MEM_2; /*!< (@ 0x000001D8) This register explain ADC INT MEM2. */ struct { - __IOM uint32_t PROG_WR_DATA : 10; /*!< [9..0] These 10-bits specify the buffer length + __IOM unsigned int PROG_WR_DATA : 10; /*!< [9..0] These 10-bits specify the buffer length of first/second buffer corresponding to the channel location ADC INT MEM2 */ - __IOM uint32_t PROG_WR_ADDR : 5; /*!< [14..10] These bits correspond to + __IOM unsigned int PROG_WR_ADDR : 5; /*!< [14..10] These bits correspond to the address of the internal memory basing on the channel number, whose information we want to program */ - __IOM uint32_t PROG_WR_DATA1 : 1; /*!< [15..15] Valid bit for first/second buffers + __IOM unsigned int PROG_WR_DATA1 : 1; /*!< [15..15] Valid bit for first/second buffers corresponding to ADC INT MEM2 */ - __IOM uint32_t RESERVED3 : 16; /*!< [31..16] Reserved3 */ + __IOM unsigned int RESERVED3 : 16; /*!< [31..16] Reserved3 */ } ADC_INT_MEM_2_b; }; union { - __IOM uint32_t INTERNAL_DMA_CH_ENABLE; /*!< (@ 0x000001DC) This register is + __IOM unsigned int INTERNAL_DMA_CH_ENABLE; /*!< (@ 0x000001DC) This register is internal channel enable */ struct { - __IOM uint32_t PER_CHANNEL_ENABLE : 16; /*!< [15..0] Enable bit for Each + __IOM unsigned int PER_CHANNEL_ENABLE : 16; /*!< [15..0] Enable bit for Each channel,like channel0 for bit0 to channel15 for bit15 etc */ - __IOM uint32_t RESERVED3 : 15; /*!< [30..16] Reserved3 */ - __IOM uint32_t INTERNAL_DMA_ENABLE : 1; /*!< [31..31] When Set, Internal DMA will be + __IOM unsigned int RESERVED3 : 15; /*!< [30..16] Reserved3 */ + __IOM unsigned int INTERNAL_DMA_ENABLE : 1; /*!< [31..31] When Set, Internal DMA will be used for reading ADC samples from ADC FIFO and writing them to ULP SRAM Memories. */ @@ -15005,114 +15005,114 @@ typedef struct { /*!< (@ 0x24043800) AUX_ADC_DAC_COMP Structure */ }; union { - __IOM uint32_t TS_PTAT_ENABLE; /*!< (@ 0x000001E0) This register is enable + __IOM unsigned int TS_PTAT_ENABLE; /*!< (@ 0x000001E0) This register is enable PTAT for temperature sensor */ struct { - __IOM uint32_t TS_PTAT_EN : 1; /*!< [0..0] BJT based Temperature sensor */ - __IOM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved1 */ + __IOM unsigned int TS_PTAT_EN : 1; /*!< [0..0] BJT based Temperature sensor */ + __IOM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved1 */ } TS_PTAT_ENABLE_b; }; union { - __OM uint32_t ADC_FIFO_THRESHOLD; /*!< (@ 0x000001E4) Configured FIFO to ADC */ + __OM unsigned int ADC_FIFO_THRESHOLD; /*!< (@ 0x000001E4) Configured FIFO to ADC */ struct { - __OM uint32_t ADC_FIFO_AEMPTY_THRESHOLD : 4; /*!< [3..0] FIFO almost empty + __OM unsigned int ADC_FIFO_AEMPTY_THRESHOLD : 4; /*!< [3..0] FIFO almost empty threshold for ADC */ - __OM uint32_t ADC_FIFO_AFULL_THRESHOLD : 4; /*!< [7..4] FIFO almost full + __OM unsigned int ADC_FIFO_AFULL_THRESHOLD : 4; /*!< [7..4] FIFO almost full threshold for ADC */ - __OM uint32_t RESERVED1 : 24; /*!< [31..8] Reserved1 */ + __OM unsigned int RESERVED1 : 24; /*!< [31..8] Reserved1 */ } ADC_FIFO_THRESHOLD_b; }; - __IM uint32_t RESERVED1[6]; + __IM unsigned int RESERVED1[6]; union { - __IOM uint32_t BOD; /*!< (@ 0x00000200) Programs resistor bank, reference + __IOM unsigned int BOD; /*!< (@ 0x00000200) Programs resistor bank, reference buffer and scaler */ struct { - __IOM uint32_t EN_BOD_TEST_MUX : 1; /*!< [0..0] 1 - To enable test mux */ - __IOM uint32_t BOD_TEST_SEL : 2; /*!< [2..1] Select bits for test mux */ - __IOM uint32_t REFBUF_EN : 1; /*!< [3..3] Reference buffer configuration 1 + __IOM unsigned int EN_BOD_TEST_MUX : 1; /*!< [0..0] 1 - To enable test mux */ + __IOM unsigned int BOD_TEST_SEL : 2; /*!< [2..1] Select bits for test mux */ + __IOM unsigned int REFBUF_EN : 1; /*!< [3..3] Reference buffer configuration 1 for enable 0 for disable */ - __IOM uint32_t REFBUF_VOLT_SEL : 4; /*!< [7..4] selection of voltage of + __IOM unsigned int REFBUF_VOLT_SEL : 4; /*!< [7..4] selection of voltage of reference buffer */ - __IOM uint32_t BOD_RES_EN : 1; /*!< [8..8] configuration of register bank + __IOM unsigned int BOD_RES_EN : 1; /*!< [8..8] configuration of register bank 1 for enable and 0 for disable */ - __IOM uint32_t BOD_THRSH : 5; /*!< [13..9] Programmability for resistor bank */ - __IOM uint32_t RESERVED2 : 18; /*!< [31..14] Reserved2 */ + __IOM unsigned int BOD_THRSH : 5; /*!< [13..9] Programmability for resistor bank */ + __IOM unsigned int RESERVED2 : 18; /*!< [31..14] Reserved2 */ } BOD_b; }; union { - __IOM uint32_t COMPARATOR1; /*!< (@ 0x00000204) Programs comparators1 and + __IOM unsigned int COMPARATOR1; /*!< (@ 0x00000204) Programs comparators1 and comparators2 */ struct { - __IOM uint32_t CMP1_EN : 1; /*!< [0..0] To enable comparator1 */ - __IOM uint32_t CMP1_EN_FILTER : 1; /*!< [1..1] To enable filter for comparator 1 */ - __IOM uint32_t CMP1_HYST : 2; /*!< [3..2] Programmability to control + __IOM unsigned int CMP1_EN : 1; /*!< [0..0] To enable comparator1 */ + __IOM unsigned int CMP1_EN_FILTER : 1; /*!< [1..1] To enable filter for comparator 1 */ + __IOM unsigned int CMP1_HYST : 2; /*!< [3..2] Programmability to control hysteresis of comparator1 */ - __IOM uint32_t CMP1_MUX_SEL_P : 4; /*!< [7..4] Select for positive input + __IOM unsigned int CMP1_MUX_SEL_P : 4; /*!< [7..4] Select for positive input of comparator_1 */ - __IOM uint32_t CMP1_MUX_SEL_N : 4; /*!< [11..8] Select for negative input + __IOM unsigned int CMP1_MUX_SEL_N : 4; /*!< [11..8] Select for negative input of comparator_1 */ - __IOM uint32_t CMP2_EN : 1; /*!< [12..12] To enable comparator 2 */ - __IOM uint32_t CMP2_EN_FILTER : 1; /*!< [13..13] To enable filter for + __IOM unsigned int CMP2_EN : 1; /*!< [12..12] To enable comparator 2 */ + __IOM unsigned int CMP2_EN_FILTER : 1; /*!< [13..13] To enable filter for comparator 2 */ - __IOM uint32_t CMP2_HYST : 2; /*!< [15..14] Programmability to control + __IOM unsigned int CMP2_HYST : 2; /*!< [15..14] Programmability to control hysteresis of comparator2 */ - __IOM uint32_t CMP2_MUX_SEL_P : 4; /*!< [19..16] Select for positive input + __IOM unsigned int CMP2_MUX_SEL_P : 4; /*!< [19..16] Select for positive input of comparator_2 */ - __IOM uint32_t CMP2_MUX_SEL_N : 4; /*!< [23..20] Select for negative input + __IOM unsigned int CMP2_MUX_SEL_N : 4; /*!< [23..20] Select for negative input of comparator_2 */ - __IOM uint32_t COM_DYN_EN : 1; /*!< [24..24] Dynamic enable for registers */ - __IOM uint32_t RESERVED1 : 7; /*!< [31..25] Reserved1 */ + __IOM unsigned int COM_DYN_EN : 1; /*!< [24..24] Dynamic enable for registers */ + __IOM unsigned int RESERVED1 : 7; /*!< [31..25] Reserved1 */ } COMPARATOR1_b; }; union { - __IOM uint32_t AUXADC_CONFIG_2; /*!< (@ 0x00000208) This register is AUX-ADC + __IOM unsigned int AUXADC_CONFIG_2; /*!< (@ 0x00000208) This register is AUX-ADC config2 */ struct { - __IOM uint32_t AUXADC_INP_SEL : 5; /*!< [4..0] Mux select for positive + __IOM unsigned int AUXADC_INP_SEL : 5; /*!< [4..0] Mux select for positive input of adc */ - __IOM uint32_t AUXADC_INN_SEL : 4; /*!< [8..5] Mux select for negetive + __IOM unsigned int AUXADC_INN_SEL : 4; /*!< [8..5] Mux select for negetive input of adc */ - __IOM uint32_t AUXADC_DIFF_MODE : 1; /*!< [9..9] AUX ADC Differential Mode */ - __IOM uint32_t AUXADC_ENABLE : 1; /*!< [10..10] Static Enable */ - __IOM uint32_t AUXADC_DYN_ENABLE : 1; /*!< [11..11] Aux ADC Configuration Enable */ - __IOM uint32_t RESERVED2 : 20; /*!< [31..12] Reserved2 */ + __IOM unsigned int AUXADC_DIFF_MODE : 1; /*!< [9..9] AUX ADC Differential Mode */ + __IOM unsigned int AUXADC_ENABLE : 1; /*!< [10..10] Static Enable */ + __IOM unsigned int AUXADC_DYN_ENABLE : 1; /*!< [11..11] Aux ADC Configuration Enable */ + __IOM unsigned int RESERVED2 : 20; /*!< [31..12] Reserved2 */ } AUXADC_CONFIG_2_b; }; union { - __IOM uint32_t AUXDAC_CONIG_1; /*!< (@ 0x0000020C) This register is AUX-DAC + __IOM unsigned int AUXDAC_CONIG_1; /*!< (@ 0x0000020C) This register is AUX-DAC config1 */ struct { - __IOM uint32_t AUXDAC_EN_S : 1; /*!< [0..0] Enable signal DAC */ - __IOM uint32_t AUXDAC_OUT_MUX_EN : 1; /*!< [1..1] Aux OUT mux Enable */ - __IOM uint32_t AUXDAC_OUT_MUX_SEL : 1; /*!< [2..2] AUXDAC OUT MUX SELECT Enable */ - __IOM uint32_t RESERVED1 : 1; /*!< [3..3] Reserved1 */ - __IOM uint32_t AUXDAC_DATA_S : 10; /*!< [13..4] Satatic AUX Dac Data */ - __IOM uint32_t AUXDAC_DYN_EN : 1; /*!< [14..14] Satatic AUX Dac Data */ - __IOM uint32_t RESERVED2 : 17; /*!< [31..15] RESERVED2 */ + __IOM unsigned int AUXDAC_EN_S : 1; /*!< [0..0] Enable signal DAC */ + __IOM unsigned int AUXDAC_OUT_MUX_EN : 1; /*!< [1..1] Aux OUT mux Enable */ + __IOM unsigned int AUXDAC_OUT_MUX_SEL : 1; /*!< [2..2] AUXDAC OUT MUX SELECT Enable */ + __IOM unsigned int RESERVED1 : 1; /*!< [3..3] Reserved1 */ + __IOM unsigned int AUXDAC_DATA_S : 10; /*!< [13..4] Satatic AUX Dac Data */ + __IOM unsigned int AUXDAC_DYN_EN : 1; /*!< [14..14] Satatic AUX Dac Data */ + __IOM unsigned int RESERVED2 : 17; /*!< [31..15] RESERVED2 */ } AUXDAC_CONIG_1_b; }; union { - __IOM uint32_t AUX_LDO; /*!< (@ 0x00000210) This register is AUX-LDO configuration */ + __IOM unsigned int AUX_LDO; /*!< (@ 0x00000210) This register is AUX-LDO configuration */ struct { - __IOM uint32_t LDO_CTRL : 4; /*!< [3..0] Enable ldo control field */ - __IOM uint32_t LDO_DEFAULT_MODE : 1; /*!< [4..4] ldo default mode enable */ - __IOM uint32_t BYPASS_LDO : 1; /*!< [5..5] bypass the LDO */ - __IOM uint32_t ENABLE_LDO : 1; /*!< [6..6] Turn LDO */ - __IOM uint32_t DYN_EN : 1; /*!< [7..7] Dynamic Enable */ - __IOM uint32_t RESERVED1 : 24; /*!< [31..8] It is recommended to write + __IOM unsigned int LDO_CTRL : 4; /*!< [3..0] Enable ldo control field */ + __IOM unsigned int LDO_DEFAULT_MODE : 1; /*!< [4..4] ldo default mode enable */ + __IOM unsigned int BYPASS_LDO : 1; /*!< [5..5] bypass the LDO */ + __IOM unsigned int ENABLE_LDO : 1; /*!< [6..6] Turn LDO */ + __IOM unsigned int DYN_EN : 1; /*!< [7..7] Dynamic Enable */ + __IOM unsigned int RESERVED1 : 24; /*!< [31..8] It is recommended to write these bits to 0. */ } AUX_LDO_b; }; @@ -15133,106 +15133,106 @@ typedef struct { /*!< (@ 0x24043800) AUX_ADC_DAC_COMP Structure */ typedef struct { /*!< (@ 0x24040C00) IR Structure */ union { - __IOM uint32_t IR_OFF_TIME_DURATION; /*!< (@ 0x00000000) This register used for IR + __IOM unsigned int IR_OFF_TIME_DURATION; /*!< (@ 0x00000000) This register used for IR sleep duration timer value. */ struct { - __IOM uint32_t IR_OFF_TIME_DURATION : 17; /*!< [16..0] This field define + __IOM unsigned int IR_OFF_TIME_DURATION : 17; /*!< [16..0] This field define ir off time */ - __IM uint32_t RES : 15; /*!< [31..17] reserved5 */ + __IM unsigned int RES : 15; /*!< [31..17] reserved5 */ } IR_OFF_TIME_DURATION_b; }; union { - __IOM uint32_t IR_ON_TIME_DURATION; /*!< (@ 0x00000004) This register used for IR + __IOM unsigned int IR_ON_TIME_DURATION; /*!< (@ 0x00000004) This register used for IR Detection duration timer value. */ struct { - __IOM uint32_t IR_ON_TIME_DURATION : 12; /*!< [11..0] This field define ir on time + __IOM unsigned int IR_ON_TIME_DURATION : 12; /*!< [11..0] This field define ir on time for ir detection on */ - __IM uint32_t RES : 20; /*!< [31..12] reserved5 */ + __IM unsigned int RES : 20; /*!< [31..12] reserved5 */ } IR_ON_TIME_DURATION_b; }; union { - __IOM uint32_t IR_FRAME_DONE_THRESHOLD; /*!< (@ 0x00000008) This register used count + __IOM unsigned int IR_FRAME_DONE_THRESHOLD; /*!< (@ 0x00000008) This register used count with respect to 32KHz clock after not more toggle are expected to a given pattern. */ struct { - __IOM uint32_t IR_FRAME_DONE_THRESHOLD : 15; /*!< [14..0] count with respect to 32KHz + __IOM unsigned int IR_FRAME_DONE_THRESHOLD : 15; /*!< [14..0] count with respect to 32KHz clock after not more toggle are expected to a given pattern */ - __IM uint32_t RES : 17; /*!< [31..15] reserved5 */ + __IM unsigned int RES : 17; /*!< [31..15] reserved5 */ } IR_FRAME_DONE_THRESHOLD_b; }; union { - __IOM uint32_t IR_DET_THRESHOLD; /*!< (@ 0x0000000C) This register used Minimum Number + __IOM unsigned int IR_DET_THRESHOLD; /*!< (@ 0x0000000C) This register used Minimum Number of edges to detected during on-time failing which IR detection is re-stated. */ struct { - __IOM uint32_t IR_DET_THRESHOLD : 7; /*!< [6..0] Minimum Number of edges to detected + __IOM unsigned int IR_DET_THRESHOLD : 7; /*!< [6..0] Minimum Number of edges to detected during on-time failing which IR detection is re-stated. */ - __IM uint32_t RES : 25; /*!< [31..7] reserved5 */ + __IM unsigned int RES : 25; /*!< [31..7] reserved5 */ } IR_DET_THRESHOLD_b; }; union { - __IOM uint32_t IR_CONFIG; /*!< (@ 0x00000010) This register used to configure the ir + __IOM unsigned int IR_CONFIG; /*!< (@ 0x00000010) This register used to configure the ir structure for application purpose. */ struct { - __IOM uint32_t EN_IR_DET : 1; /*!< [0..0] Enable IR detection logic bit if bit 1 then + __IOM unsigned int EN_IR_DET : 1; /*!< [0..0] Enable IR detection logic bit if bit 1 then detection enable if 0 then not enable. */ - __IOM uint32_t IR_DET_RSTART : 1; /*!< [1..1] Enable IR detection re-start logic bit + __IOM unsigned int IR_DET_RSTART : 1; /*!< [1..1] Enable IR detection re-start logic bit if bit 1 then re-start. */ - __IOM uint32_t EN_CLK_IR_CORE : 1; /*!< [2..2] Enable 32KHz clock to IR Core bit ,if + __IOM unsigned int EN_CLK_IR_CORE : 1; /*!< [2..2] Enable 32KHz clock to IR Core bit ,if bit 1 then clock gating disable and bit is 0 then clock gating Enable */ - __IM uint32_t RES : 5; /*!< [7..3] reserved5 */ - __IOM uint32_t EN_CONT_IR_DET : 1; /*!< [8..8] This bit is Enable continues IR + __IM unsigned int RES : 5; /*!< [7..3] reserved5 */ + __IOM unsigned int EN_CONT_IR_DET : 1; /*!< [8..8] This bit is Enable continues IR detection,When enabled there will be no power cycling on External IR Sensor. */ - __IM uint32_t RES1 : 7; /*!< [15..9] reserved6 */ - __IOM uint32_t SREST_IR_CORE : 1; /*!< [16..16] This bit is used soft + __IM unsigned int RES1 : 7; /*!< [15..9] reserved6 */ + __IOM unsigned int SREST_IR_CORE : 1; /*!< [16..16] This bit is used soft reset IR core block */ - __IM uint32_t RES2 : 15; /*!< [31..17] reserved7 */ + __IM unsigned int RES2 : 15; /*!< [31..17] reserved7 */ } IR_CONFIG_b; }; union { - __IOM uint32_t IR_MEM_ADDR_ACCESS; /*!< (@ 0x00000014) This register used to access + __IOM unsigned int IR_MEM_ADDR_ACCESS; /*!< (@ 0x00000014) This register used to access memory address for application purpose. */ struct { - __IOM uint32_t IR_MEM_ADDR : 7; /*!< [6..0] This field is used to IR read + __IOM unsigned int IR_MEM_ADDR : 7; /*!< [6..0] This field is used to IR read address. */ - __IOM uint32_t RES : 1; /*!< [7..7] reserved5 */ - __IOM uint32_t IR_MEM_WR_EN : 1; /*!< [8..8] IR memory write enable. */ - __IOM uint32_t IR_MEM_RD_EN : 1; /*!< [9..9] This field used to IR memory + __IOM unsigned int RES : 1; /*!< [7..7] reserved5 */ + __IOM unsigned int IR_MEM_WR_EN : 1; /*!< [8..8] IR memory write enable. */ + __IOM unsigned int IR_MEM_RD_EN : 1; /*!< [9..9] This field used to IR memory read enable. */ - __IOM uint32_t RES1 : 6; /*!< [15..10] reserved1 */ - __IOM uint32_t IR_MEM_WR_TEST_MODE : 1; /*!< [16..16] IR memory write + __IOM unsigned int RES1 : 6; /*!< [15..10] reserved1 */ + __IOM unsigned int IR_MEM_WR_TEST_MODE : 1; /*!< [16..16] IR memory write enable in test mode.. */ - __IOM uint32_t RES2 : 15; /*!< [31..17] reserved2 */ + __IOM unsigned int RES2 : 15; /*!< [31..17] reserved2 */ } IR_MEM_ADDR_ACCESS_b; }; union { - __IM uint32_t IR_MEM_READ; /*!< (@ 0x00000018) This register used to IR Read + __IM unsigned int IR_MEM_READ; /*!< (@ 0x00000018) This register used to IR Read data from memory. */ struct { - __IM uint32_t IR_MEM_DATA_OUT : 16; /*!< [15..0] This field is used to IR + __IM unsigned int IR_MEM_DATA_OUT : 16; /*!< [15..0] This field is used to IR Read data from memory. */ - __IM uint32_t RES : 8; /*!< [23..16] reserved5 */ - __IM uint32_t IR_DATA_MEM_DEPTH : 7; /*!< [30..24] This field used to indicated + __IM unsigned int RES : 8; /*!< [23..16] reserved5 */ + __IM unsigned int IR_DATA_MEM_DEPTH : 7; /*!< [30..24] This field used to indicated valid number of IR Address in the memory to be read. */ - __IM uint32_t RES1 : 1; /*!< [31..31] reserved6 */ + __IM unsigned int RES1 : 1; /*!< [31..31] reserved6 */ } IR_MEM_READ_b; }; } IR_Type; /*!< Size = 28 (0x1c) */ @@ -15252,140 +15252,140 @@ typedef struct { /*!< (@ 0x24040C00) IR Structure */ typedef struct { /*!< (@ 0x24042C00) CTS Structure */ union { - __IOM uint32_t CTS_CONFIG_REG_0_0; /*!< (@ 0x00000000) Configuration Register 0_0 */ + __IOM unsigned int CTS_CONFIG_REG_0_0; /*!< (@ 0x00000000) Configuration Register 0_0 */ struct { - __IOM uint32_t CLK_SEL1 : 2; /*!< [1..0] Mux select for clock_mux_1 */ - __IOM uint32_t PRE_SCALAR_1 : 8; /*!< [9..2] Division factor for clock divider */ - __IOM uint32_t PRE_SCALAR_2 : 4; /*!< [13..10] Division factor for clock divider */ - __IOM uint32_t CLK_SEL2 : 1; /*!< [14..14] Mux select for clock_mux_2 */ - __IOM uint32_t CTS_STATIC_CLK_EN : 1; /*!< [15..15] Enable static for + __IOM unsigned int CLK_SEL1 : 2; /*!< [1..0] Mux select for clock_mux_1 */ + __IOM unsigned int PRE_SCALAR_1 : 8; /*!< [9..2] Division factor for clock divider */ + __IOM unsigned int PRE_SCALAR_2 : 4; /*!< [13..10] Division factor for clock divider */ + __IOM unsigned int CLK_SEL2 : 1; /*!< [14..14] Mux select for clock_mux_2 */ + __IOM unsigned int CTS_STATIC_CLK_EN : 1; /*!< [15..15] Enable static for capacitive touch sensor */ - __IOM uint32_t FIFO_AFULL_THRLD : 6; /*!< [21..16] Threshold for fifo afull */ - __IOM uint32_t FIFO_AEMPTY_THRLD : 6; /*!< [27..22] Threshold for fifo aempty */ - __IM uint32_t FIFO_EMPTY : 1; /*!< [28..28] FIFO empty status bit */ - __IM uint32_t RESERVED1 : 3; /*!< [31..29] Reserved1 */ + __IOM unsigned int FIFO_AFULL_THRLD : 6; /*!< [21..16] Threshold for fifo afull */ + __IOM unsigned int FIFO_AEMPTY_THRLD : 6; /*!< [27..22] Threshold for fifo aempty */ + __IM unsigned int FIFO_EMPTY : 1; /*!< [28..28] FIFO empty status bit */ + __IM unsigned int RESERVED1 : 3; /*!< [31..29] Reserved1 */ } CTS_CONFIG_REG_0_0_b; }; union { - __IOM uint32_t CTS_FIFO_ADDRESS; /*!< (@ 0x00000004) FIFO Address Register */ + __IOM unsigned int CTS_FIFO_ADDRESS; /*!< (@ 0x00000004) FIFO Address Register */ struct { - __IOM uint32_t FIFO : 32; /*!< [31..0] Used for FIFO reads and write operations */ + __IOM unsigned int FIFO : 32; /*!< [31..0] Used for FIFO reads and write operations */ } CTS_FIFO_ADDRESS_b; }; - __IM uint32_t RESERVED[62]; + __IM unsigned int RESERVED[62]; union { - __IOM uint32_t CTS_CONFIG_REG_1_1; /*!< (@ 0x00000100) Configuration Register 1_1 */ + __IOM unsigned int CTS_CONFIG_REG_1_1; /*!< (@ 0x00000100) Configuration Register 1_1 */ struct { - __IOM uint32_t POLYNOMIAL_LEN : 2; /*!< [1..0] Length of polynomial */ - __IOM uint32_t SEED_LOAD : 1; /*!< [2..2] Seed of polynomial */ - __IOM uint32_t BUFFER_DELAY : 5; /*!< [7..3] Delay of buffer. Delay programmed will + __IOM unsigned int POLYNOMIAL_LEN : 2; /*!< [1..0] Length of polynomial */ + __IOM unsigned int SEED_LOAD : 1; /*!< [2..2] Seed of polynomial */ + __IOM unsigned int BUFFER_DELAY : 5; /*!< [7..3] Delay of buffer. Delay programmed will be equal to delay in nano seconds. Max delay value is 32.Default delay should be programmed before using Capacitive touch sensor module. */ - __IOM uint32_t WAKE_UP_ACK : 1; /*!< [8..8] Ack for wake up interrupt. This is a + __IOM unsigned int WAKE_UP_ACK : 1; /*!< [8..8] Ack for wake up interrupt. This is a level signal. To acknowledge wake up , set this bit to one and reset it . */ - __IOM uint32_t ENABLE1 : 1; /*!< [9..9] Enable signal */ - __IOM uint32_t SOFT_RESET_2 : 1; /*!< [10..10] Reset the FIFO write and + __IOM unsigned int ENABLE1 : 1; /*!< [9..9] Enable signal */ + __IOM unsigned int SOFT_RESET_2 : 1; /*!< [10..10] Reset the FIFO write and FIFO read occupancy pointers */ - __IOM uint32_t CNT_ONEHOT_MODE : 1; /*!< [11..11] Continuous or One hot mode */ - __IOM uint32_t SAMPLE_MODE : 2; /*!< [13..12] Select bits for FIFO write + __IOM unsigned int CNT_ONEHOT_MODE : 1; /*!< [11..11] Continuous or One hot mode */ + __IOM unsigned int SAMPLE_MODE : 2; /*!< [13..12] Select bits for FIFO write and FIFO average */ - __IOM uint32_t RESET_WR_FIFO : 1; /*!< [14..14] Resets the signal fifo_wr_int */ - __OM uint32_t BYPASS : 1; /*!< [15..15] Bypass signal */ - __IOM uint32_t BIT_SEL : 2; /*!< [17..16] Selects different set of 12 bits + __IOM unsigned int RESET_WR_FIFO : 1; /*!< [14..14] Resets the signal fifo_wr_int */ + __OM unsigned int BYPASS : 1; /*!< [15..15] Bypass signal */ + __IOM unsigned int BIT_SEL : 2; /*!< [17..16] Selects different set of 12 bits to be stored in FIFO */ - __IOM uint32_t EXT_TRIG_SEL : 1; /*!< [18..18] Select bit for NPSS clock + __IOM unsigned int EXT_TRIG_SEL : 1; /*!< [18..18] Select bit for NPSS clock or Enable */ - __IOM uint32_t EXT_TRIG_EN : 1; /*!< [19..19] Select bit for NPSS clock or + __IOM unsigned int EXT_TRIG_EN : 1; /*!< [19..19] Select bit for NPSS clock or Enable */ - __IOM uint32_t RESERVED2 : 12; /*!< [31..20] Reserved2 */ + __IOM unsigned int RESERVED2 : 12; /*!< [31..20] Reserved2 */ } CTS_CONFIG_REG_1_1_b; }; union { - __IOM uint32_t CTS_CONFIG_REG_1_2; /*!< (@ 0x00000104) Configuration Register 1_2 */ + __IOM unsigned int CTS_CONFIG_REG_1_2; /*!< (@ 0x00000104) Configuration Register 1_2 */ struct { - __IOM uint32_t PWM_ON_PERIOD : 16; /*!< [15..0] PWM ON period */ - __IOM uint32_t PWM_OFF_PERIOD : 16; /*!< [31..16] PWM OFF period */ + __IOM unsigned int PWM_ON_PERIOD : 16; /*!< [15..0] PWM ON period */ + __IOM unsigned int PWM_OFF_PERIOD : 16; /*!< [31..16] PWM OFF period */ } CTS_CONFIG_REG_1_2_b; }; union { - __IOM uint32_t CTS_CONFIG_REG_1_3; /*!< (@ 0x00000108) Configuration Register 1_3 */ + __IOM unsigned int CTS_CONFIG_REG_1_3; /*!< (@ 0x00000108) Configuration Register 1_3 */ struct { - __IOM uint32_t PRS_SEED : 32; /*!< [31..0] Pseudo random generator (PRS) + __IOM unsigned int PRS_SEED : 32; /*!< [31..0] Pseudo random generator (PRS) seed value */ } CTS_CONFIG_REG_1_3_b; }; union { - __IOM uint32_t CTS_CONFIG_REG_1_4; /*!< (@ 0x0000010C) Configuration Register 1_4 */ + __IOM unsigned int CTS_CONFIG_REG_1_4; /*!< (@ 0x0000010C) Configuration Register 1_4 */ struct { - __IOM uint32_t PRS_POLY : 32; /*!< [31..0] Polynomial programming register + __IOM unsigned int PRS_POLY : 32; /*!< [31..0] Polynomial programming register for PRS generator */ } CTS_CONFIG_REG_1_4_b; }; union { - __IOM uint32_t CTS_CONFIG_REG_1_5; /*!< (@ 0x00000110) Configuration Register 1_5 */ + __IOM unsigned int CTS_CONFIG_REG_1_5; /*!< (@ 0x00000110) Configuration Register 1_5 */ struct { - __IOM uint32_t INTER_SENSOR_DELAY : 16; /*!< [15..0] Inter-sensor scan + __IOM unsigned int INTER_SENSOR_DELAY : 16; /*!< [15..0] Inter-sensor scan delay value */ - __IOM uint32_t N_SAMPLE_COUNT : 16; /*!< [31..16] Number of repetitions of + __IOM unsigned int N_SAMPLE_COUNT : 16; /*!< [31..16] Number of repetitions of sensor scan */ } CTS_CONFIG_REG_1_5_b; }; union { - __IOM uint32_t CTS_CONFIG_REG_1_6; /*!< (@ 0x00000114) Configuration Register 1_6 */ + __IOM unsigned int CTS_CONFIG_REG_1_6; /*!< (@ 0x00000114) Configuration Register 1_6 */ struct { - __IOM uint32_t SENSOR_CFG : 32; /*!< [31..0] Register of scan controller + __IOM unsigned int SENSOR_CFG : 32; /*!< [31..0] Register of scan controller containing the programmed bit map */ } CTS_CONFIG_REG_1_6_b; }; union { - __IOM uint32_t CTS_CONFIG_REG_1_7; /*!< (@ 0x00000118) Configuration Register 1_7 */ + __IOM unsigned int CTS_CONFIG_REG_1_7; /*!< (@ 0x00000118) Configuration Register 1_7 */ struct { - __IOM uint32_t VALID_SENSORS : 4; /*!< [3..0] Value of number of sensors + __IOM unsigned int VALID_SENSORS : 4; /*!< [3..0] Value of number of sensors valid in the bit map */ - __IOM uint32_t RESERVED1 : 2; /*!< [5..4] Reserved1 */ - __IOM uint32_t REF_VOLT_CONFIG : 9; /*!< [14..6] This is given as an input voltage to + __IOM unsigned int RESERVED1 : 2; /*!< [5..4] Reserved1 */ + __IOM unsigned int REF_VOLT_CONFIG : 9; /*!< [14..6] This is given as an input voltage to analog model as comparator reference voltage. */ - __IOM uint32_t WAKEUP_MODE : 1; /*!< [15..15] Select bit for high/low mode. */ - __IOM uint32_t WAKE_UP_THRESHOLD : 16; /*!< [31..16] Wakeup threshold. */ + __IOM unsigned int WAKEUP_MODE : 1; /*!< [15..15] Select bit for high/low mode. */ + __IOM unsigned int WAKE_UP_THRESHOLD : 16; /*!< [31..16] Wakeup threshold. */ } CTS_CONFIG_REG_1_7_b; }; union { - __IM uint32_t CTS_CONFIG_REG_1_8; /*!< (@ 0x0000011C) Configuration Register 1_8 */ + __IM unsigned int CTS_CONFIG_REG_1_8; /*!< (@ 0x0000011C) Configuration Register 1_8 */ struct { - __IM uint32_t PRS_STATE : 32; /*!< [31..0] Current state of PRS */ + __IM unsigned int PRS_STATE : 32; /*!< [31..0] Current state of PRS */ } CTS_CONFIG_REG_1_8_b; }; union { - __IOM uint32_t CTS_CONFIG_REG_1_9; /*!< (@ 0x00000120) Configuration Register 1_9 */ + __IOM unsigned int CTS_CONFIG_REG_1_9; /*!< (@ 0x00000120) Configuration Register 1_9 */ struct { - __IOM uint32_t TRIG_DIV : 10; /*!< [9..0] Allows one pulse for every 'trig_div' no. + __IOM unsigned int TRIG_DIV : 10; /*!< [9..0] Allows one pulse for every 'trig_div' no. of pulses of 1 ms clock */ - __IOM uint32_t RESERVED1 : 22; /*!< [31..10] Reserved1 */ + __IOM unsigned int RESERVED1 : 22; /*!< [31..10] Reserved1 */ } CTS_CONFIG_REG_1_9_b; }; } CTS_Type; /*!< Size = 292 (0x124) */ @@ -15404,14 +15404,14 @@ typedef struct { /*!< (@ 0x24042C00) CTS Structure */ typedef struct { /*!< (@ 0x46008000) MISC_CONFIG Structure */ union { - __IOM uint32_t MISC_CFG_HOST_INTR_MASK; /*!< (@ 0x00000000) MISC CFG HOST + __IOM unsigned int MISC_CFG_HOST_INTR_MASK; /*!< (@ 0x00000000) MISC CFG HOST INTR MASK */ struct { - __IOM uint32_t HOST_INTR_MSK : 8; /*!< [7..0] Writing 1 in any bit masks + __IOM unsigned int HOST_INTR_MSK : 8; /*!< [7..0] Writing 1 in any bit masks the corresponding interrupt in HOST_INTR_STATUS. */ - __IOM uint32_t HOST_SPI_INTR_OPEN_DRAIN_MODE : 1; /*!< [8..8] Writing 1 to this bit + __IOM unsigned int HOST_SPI_INTR_OPEN_DRAIN_MODE : 1; /*!< [8..8] Writing 1 to this bit configures the host SPI interrupt in open drain mode. When open drain mode is enabled @@ -15420,12 +15420,12 @@ typedef struct { /*!< (@ 0x46008000) MISC_CONFIG Structure */ PULLDOWN has to be used on the board. */ __IOM - uint32_t HOST_SPI_INTR_ACTIVE_LOW_MODE : 1; /*!< [9..9] Writing 1 to this + unsigned int HOST_SPI_INTR_ACTIVE_LOW_MODE : 1; /*!< [9..9] Writing 1 to this bit configures the host SPI interrupt in active low mode. By default, it will be active high. */ - __IOM uint32_t RESERVED1 : 22; /*!< [31..10] reserved1 */ + __IOM unsigned int RESERVED1 : 22; /*!< [31..10] reserved1 */ } MISC_CFG_HOST_INTR_MASK_b; }; } MISC_CONFIG_Type; /*!< Size = 4 (0x4) */ @@ -15439,123 +15439,123 @@ typedef struct { /*!< (@ 0x46008000) MISC_CONFIG Structure */ /** SYSRTC Register Declaration. */ typedef struct { - __IM uint32_t IPVERSION; /**< IP VERSION */ - __IOM uint32_t EN; /**< Module Enable Register */ - __IOM uint32_t SWRST; /**< Software Reset Register */ - __IOM uint32_t CFG; /**< Configuration Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IM uint32_t STATUS; /**< Status register */ - __IOM uint32_t CNT; /**< Counter Value Register */ - __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK; /**< Configuration Lock Register */ - uint32_t RESERVED0[3U]; /**< Reserved for future use */ - __IOM uint32_t FAILDETCTRL; /**< Failure Detection */ - __IOM uint32_t FAILDETLOCK; /**< FAILDET Lock Register */ - uint32_t RESERVED1[2U]; /**< Reserved for future use */ - __IOM uint32_t GRP0_IF; /**< Group Interrupt Flags */ - __IOM uint32_t GRP0_IEN; /**< Group Interrupt Enables */ - __IOM uint32_t GRP0_CTRL; /**< Group Control Register */ - __IOM uint32_t GRP0_CMP0VALUE; /**< Compare 0 Value Register */ - __IOM uint32_t GRP0_CMP1VALUE; /**< Compare 1 Value Register */ - __IM uint32_t GRP0_CAP0VALUE; /**< Capture 0 Value Register */ - __IM uint32_t GRP0_SYNCBUSY; /**< Synchronization busy Register */ - uint32_t RESERVED2[1U]; /**< Reserved for future use */ - __IOM uint32_t GRP1_IF; /**< Group Interrupt Flags */ - __IOM uint32_t GRP1_IEN; /**< Group Interrupt Enables */ - __IOM uint32_t GRP1_CTRL; /**< Group Control Register */ - __IOM uint32_t GRP1_CMP0VALUE; /**< Compare 0 Value Register */ - __IOM uint32_t GRP1_CMP1VALUE; /**< Compare 1 Value Register */ - __IM uint32_t GRP1_CAP0VALUE; /**< Capture 0 Value Register */ - __IM uint32_t GRP1_SYNCBUSY; /**< Synchronization busy Register */ - uint32_t RESERVED3[33U]; /**< GRP2 - GRP7,Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP VERSION */ - __IOM uint32_t EN_SET; /**< Module Enable Register */ - __IOM uint32_t SWRST_SET; /**< Software Reset Register */ - __IOM uint32_t CFG_SET; /**< Configuration Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IM uint32_t STATUS_SET; /**< Status register */ - __IOM uint32_t CNT_SET; /**< Counter Value Register */ - __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ - uint32_t RESERVED4[3U]; /**< Reserved for future use */ - __IOM uint32_t FAILDETCTRL_SET; /**< Failure Detection */ - __IOM uint32_t FAILDETLOCK_SET; /**< FAILDET Lock Register */ - uint32_t RESERVED5[2U]; /**< Reserved for future use */ - __IOM uint32_t GRP0_IF_SET; /**< Group Interrupt Flags */ - __IOM uint32_t GRP0_IEN_SET; /**< Group Interrupt Enables */ - __IOM uint32_t GRP0_CTRL_SET; /**< Group Control Register */ - __IOM uint32_t GRP0_CMP0VALUE_SET; /**< Compare 0 Value Register */ - __IOM uint32_t GRP0_CMP1VALUE_SET; /**< Compare 1 Value Register */ - __IM uint32_t GRP0_CAP0VALUE_SET; /**< Capture 0 Value Register */ - __IM uint32_t GRP0_SYNCBUSY_SET; /**< Synchronization busy Register */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - __IOM uint32_t GRP1_IF_SET; /**< Group Interrupt Flags */ - __IOM uint32_t GRP1_IEN_SET; /**< Group Interrupt Enables */ - __IOM uint32_t GRP1_CTRL_SET; /**< Group Control Register */ - __IOM uint32_t GRP1_CMP0VALUE_SET; /**< Compare 0 Value Register */ - __IOM uint32_t GRP1_CMP1VALUE_SET; /**< Compare 1 Value Register */ - __IM uint32_t GRP1_CAP0VALUE_SET; /**< Capture 0 Value Register */ - __IM uint32_t GRP1_SYNCBUSY_SET; /**< Synchronization busy Register */ - uint32_t RESERVED7[33U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP VERSION */ - __IOM uint32_t EN_CLR; /**< Module Enable Register */ - __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ - __IOM uint32_t CFG_CLR; /**< Configuration Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IM uint32_t STATUS_CLR; /**< Status register */ - __IOM uint32_t CNT_CLR; /**< Counter Value Register */ - __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ - uint32_t RESERVED8[3U]; /**< Reserved for future use */ - __IOM uint32_t FAILDETCTRL_CLR; /**< Failure Detection */ - __IOM uint32_t FAILDETLOCK_CLR; /**< FAILDET Lock Register */ - uint32_t RESERVED9[2U]; /**< Reserved for future use */ - __IOM uint32_t GRP0_IF_CLR; /**< Group Interrupt Flags */ - __IOM uint32_t GRP0_IEN_CLR; /**< Group Interrupt Enables */ - __IOM uint32_t GRP0_CTRL_CLR; /**< Group Control Register */ - __IOM uint32_t GRP0_CMP0VALUE_CLR; /**< Compare 0 Value Register */ - __IOM uint32_t GRP0_CMP1VALUE_CLR; /**< Compare 1 Value Register */ - __IM uint32_t GRP0_CAP0VALUE_CLR; /**< Capture 0 Value Register */ - __IM uint32_t GRP0_SYNCBUSY_CLR; /**< Synchronization busy Register */ - uint32_t RESERVED10[1U]; /**< Reserved for future use */ - __IOM uint32_t GRP1_IF_CLR; /**< Group Interrupt Flags */ - __IOM uint32_t GRP1_IEN_CLR; /**< Group Interrupt Enables */ - __IOM uint32_t GRP1_CTRL_CLR; /**< Group Control Register */ - __IOM uint32_t GRP1_CMP0VALUE_CLR; /**< Compare 0 Value Register */ - __IOM uint32_t GRP1_CMP1VALUE_CLR; /**< Compare 1 Value Register */ - __IM uint32_t GRP1_CAP0VALUE_CLR; /**< Capture 0 Value Register */ - __IM uint32_t GRP1_SYNCBUSY_CLR; /**< Synchronization busy Register */ - uint32_t RESERVED11[33U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP VERSION */ - __IOM uint32_t EN_TGL; /**< Module Enable Register */ - __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ - __IOM uint32_t CFG_TGL; /**< Configuration Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IM uint32_t STATUS_TGL; /**< Status register */ - __IOM uint32_t CNT_TGL; /**< Counter Value Register */ - __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ - uint32_t RESERVED12[3U]; /**< Reserved for future use */ - __IOM uint32_t FAILDETCTRL_TGL; /**< Failure Detection */ - __IOM uint32_t FAILDETLOCK_TGL; /**< FAILDET Lock Register */ - uint32_t RESERVED13[2U]; /**< Reserved for future use */ - __IOM uint32_t GRP0_IF_TGL; /**< Group Interrupt Flags */ - __IOM uint32_t GRP0_IEN_TGL; /**< Group Interrupt Enables */ - __IOM uint32_t GRP0_CTRL_TGL; /**< Group Control Register */ - __IOM uint32_t GRP0_CMP0VALUE_TGL; /**< Compare 0 Value Register */ - __IOM uint32_t GRP0_CMP1VALUE_TGL; /**< Compare 1 Value Register */ - __IM uint32_t GRP0_CAP0VALUE_TGL; /**< Capture 0 Value Register */ - __IM uint32_t GRP0_SYNCBUSY_TGL; /**< Synchronization busy Register */ - uint32_t RESERVED14[1U]; /**< Reserved for future use */ - __IOM uint32_t GRP1_IF_TGL; /**< Group Interrupt Flags */ - __IOM uint32_t GRP1_IEN_TGL; /**< Group Interrupt Enables */ - __IOM uint32_t GRP1_CTRL_TGL; /**< Group Control Register */ - __IOM uint32_t GRP1_CMP0VALUE_TGL; /**< Compare 0 Value Register */ - __IOM uint32_t GRP1_CMP1VALUE_TGL; /**< Compare 1 Value Register */ - __IM uint32_t GRP1_CAP0VALUE_TGL; /**< Capture 0 Value Register */ - __IM uint32_t GRP1_SYNCBUSY_TGL; /**< Synchronization busy Register */ - uint32_t RESERVED15[32U]; /**< Reserved for future use */ - __IOM uint32_t MCUSYSRTC_REG1; /**< input and output configuration */ + __IM unsigned int IPVERSION; /**< IP VERSION */ + __IOM unsigned int EN; /**< Module Enable Register */ + __IOM unsigned int SWRST; /**< Software Reset Register */ + __IOM unsigned int CFG; /**< Configuration Register */ + __IOM unsigned int CMD; /**< Command Register */ + __IM unsigned int STATUS; /**< Status register */ + __IOM unsigned int CNT; /**< Counter Value Register */ + __IM unsigned int SYNCBUSY; /**< Synchronization Busy Register */ + __IOM unsigned int LOCK; /**< Configuration Lock Register */ + unsigned int RESERVED0[3U]; /**< Reserved for future use */ + __IOM unsigned int FAILDETCTRL; /**< Failure Detection */ + __IOM unsigned int FAILDETLOCK; /**< FAILDET Lock Register */ + unsigned int RESERVED1[2U]; /**< Reserved for future use */ + __IOM unsigned int GRP0_IF; /**< Group Interrupt Flags */ + __IOM unsigned int GRP0_IEN; /**< Group Interrupt Enables */ + __IOM unsigned int GRP0_CTRL; /**< Group Control Register */ + __IOM unsigned int GRP0_CMP0VALUE; /**< Compare 0 Value Register */ + __IOM unsigned int GRP0_CMP1VALUE; /**< Compare 1 Value Register */ + __IM unsigned int GRP0_CAP0VALUE; /**< Capture 0 Value Register */ + __IM unsigned int GRP0_SYNCBUSY; /**< Synchronization busy Register */ + unsigned int RESERVED2[1U]; /**< Reserved for future use */ + __IOM unsigned int GRP1_IF; /**< Group Interrupt Flags */ + __IOM unsigned int GRP1_IEN; /**< Group Interrupt Enables */ + __IOM unsigned int GRP1_CTRL; /**< Group Control Register */ + __IOM unsigned int GRP1_CMP0VALUE; /**< Compare 0 Value Register */ + __IOM unsigned int GRP1_CMP1VALUE; /**< Compare 1 Value Register */ + __IM unsigned int GRP1_CAP0VALUE; /**< Capture 0 Value Register */ + __IM unsigned int GRP1_SYNCBUSY; /**< Synchronization busy Register */ + unsigned int RESERVED3[33U]; /**< GRP2 - GRP7,Reserved for future use */ + __IM unsigned int IPVERSION_SET; /**< IP VERSION */ + __IOM unsigned int EN_SET; /**< Module Enable Register */ + __IOM unsigned int SWRST_SET; /**< Software Reset Register */ + __IOM unsigned int CFG_SET; /**< Configuration Register */ + __IOM unsigned int CMD_SET; /**< Command Register */ + __IM unsigned int STATUS_SET; /**< Status register */ + __IOM unsigned int CNT_SET; /**< Counter Value Register */ + __IM unsigned int SYNCBUSY_SET; /**< Synchronization Busy Register */ + __IOM unsigned int LOCK_SET; /**< Configuration Lock Register */ + unsigned int RESERVED4[3U]; /**< Reserved for future use */ + __IOM unsigned int FAILDETCTRL_SET; /**< Failure Detection */ + __IOM unsigned int FAILDETLOCK_SET; /**< FAILDET Lock Register */ + unsigned int RESERVED5[2U]; /**< Reserved for future use */ + __IOM unsigned int GRP0_IF_SET; /**< Group Interrupt Flags */ + __IOM unsigned int GRP0_IEN_SET; /**< Group Interrupt Enables */ + __IOM unsigned int GRP0_CTRL_SET; /**< Group Control Register */ + __IOM unsigned int GRP0_CMP0VALUE_SET; /**< Compare 0 Value Register */ + __IOM unsigned int GRP0_CMP1VALUE_SET; /**< Compare 1 Value Register */ + __IM unsigned int GRP0_CAP0VALUE_SET; /**< Capture 0 Value Register */ + __IM unsigned int GRP0_SYNCBUSY_SET; /**< Synchronization busy Register */ + unsigned int RESERVED6[1U]; /**< Reserved for future use */ + __IOM unsigned int GRP1_IF_SET; /**< Group Interrupt Flags */ + __IOM unsigned int GRP1_IEN_SET; /**< Group Interrupt Enables */ + __IOM unsigned int GRP1_CTRL_SET; /**< Group Control Register */ + __IOM unsigned int GRP1_CMP0VALUE_SET; /**< Compare 0 Value Register */ + __IOM unsigned int GRP1_CMP1VALUE_SET; /**< Compare 1 Value Register */ + __IM unsigned int GRP1_CAP0VALUE_SET; /**< Capture 0 Value Register */ + __IM unsigned int GRP1_SYNCBUSY_SET; /**< Synchronization busy Register */ + unsigned int RESERVED7[33U]; /**< Reserved for future use */ + __IM unsigned int IPVERSION_CLR; /**< IP VERSION */ + __IOM unsigned int EN_CLR; /**< Module Enable Register */ + __IOM unsigned int SWRST_CLR; /**< Software Reset Register */ + __IOM unsigned int CFG_CLR; /**< Configuration Register */ + __IOM unsigned int CMD_CLR; /**< Command Register */ + __IM unsigned int STATUS_CLR; /**< Status register */ + __IOM unsigned int CNT_CLR; /**< Counter Value Register */ + __IM unsigned int SYNCBUSY_CLR; /**< Synchronization Busy Register */ + __IOM unsigned int LOCK_CLR; /**< Configuration Lock Register */ + unsigned int RESERVED8[3U]; /**< Reserved for future use */ + __IOM unsigned int FAILDETCTRL_CLR; /**< Failure Detection */ + __IOM unsigned int FAILDETLOCK_CLR; /**< FAILDET Lock Register */ + unsigned int RESERVED9[2U]; /**< Reserved for future use */ + __IOM unsigned int GRP0_IF_CLR; /**< Group Interrupt Flags */ + __IOM unsigned int GRP0_IEN_CLR; /**< Group Interrupt Enables */ + __IOM unsigned int GRP0_CTRL_CLR; /**< Group Control Register */ + __IOM unsigned int GRP0_CMP0VALUE_CLR; /**< Compare 0 Value Register */ + __IOM unsigned int GRP0_CMP1VALUE_CLR; /**< Compare 1 Value Register */ + __IM unsigned int GRP0_CAP0VALUE_CLR; /**< Capture 0 Value Register */ + __IM unsigned int GRP0_SYNCBUSY_CLR; /**< Synchronization busy Register */ + unsigned int RESERVED10[1U]; /**< Reserved for future use */ + __IOM unsigned int GRP1_IF_CLR; /**< Group Interrupt Flags */ + __IOM unsigned int GRP1_IEN_CLR; /**< Group Interrupt Enables */ + __IOM unsigned int GRP1_CTRL_CLR; /**< Group Control Register */ + __IOM unsigned int GRP1_CMP0VALUE_CLR; /**< Compare 0 Value Register */ + __IOM unsigned int GRP1_CMP1VALUE_CLR; /**< Compare 1 Value Register */ + __IM unsigned int GRP1_CAP0VALUE_CLR; /**< Capture 0 Value Register */ + __IM unsigned int GRP1_SYNCBUSY_CLR; /**< Synchronization busy Register */ + unsigned int RESERVED11[33U]; /**< Reserved for future use */ + __IM unsigned int IPVERSION_TGL; /**< IP VERSION */ + __IOM unsigned int EN_TGL; /**< Module Enable Register */ + __IOM unsigned int SWRST_TGL; /**< Software Reset Register */ + __IOM unsigned int CFG_TGL; /**< Configuration Register */ + __IOM unsigned int CMD_TGL; /**< Command Register */ + __IM unsigned int STATUS_TGL; /**< Status register */ + __IOM unsigned int CNT_TGL; /**< Counter Value Register */ + __IM unsigned int SYNCBUSY_TGL; /**< Synchronization Busy Register */ + __IOM unsigned int LOCK_TGL; /**< Configuration Lock Register */ + unsigned int RESERVED12[3U]; /**< Reserved for future use */ + __IOM unsigned int FAILDETCTRL_TGL; /**< Failure Detection */ + __IOM unsigned int FAILDETLOCK_TGL; /**< FAILDET Lock Register */ + unsigned int RESERVED13[2U]; /**< Reserved for future use */ + __IOM unsigned int GRP0_IF_TGL; /**< Group Interrupt Flags */ + __IOM unsigned int GRP0_IEN_TGL; /**< Group Interrupt Enables */ + __IOM unsigned int GRP0_CTRL_TGL; /**< Group Control Register */ + __IOM unsigned int GRP0_CMP0VALUE_TGL; /**< Compare 0 Value Register */ + __IOM unsigned int GRP0_CMP1VALUE_TGL; /**< Compare 1 Value Register */ + __IM unsigned int GRP0_CAP0VALUE_TGL; /**< Capture 0 Value Register */ + __IM unsigned int GRP0_SYNCBUSY_TGL; /**< Synchronization busy Register */ + unsigned int RESERVED14[1U]; /**< Reserved for future use */ + __IOM unsigned int GRP1_IF_TGL; /**< Group Interrupt Flags */ + __IOM unsigned int GRP1_IEN_TGL; /**< Group Interrupt Enables */ + __IOM unsigned int GRP1_CTRL_TGL; /**< Group Control Register */ + __IOM unsigned int GRP1_CMP0VALUE_TGL; /**< Compare 0 Value Register */ + __IOM unsigned int GRP1_CMP1VALUE_TGL; /**< Compare 1 Value Register */ + __IM unsigned int GRP1_CAP0VALUE_TGL; /**< Capture 0 Value Register */ + __IM unsigned int GRP1_SYNCBUSY_TGL; /**< Synchronization busy Register */ + unsigned int RESERVED15[32U]; /**< Reserved for future use */ + __IOM unsigned int MCUSYSRTC_REG1; /**< input and output configuration */ } SYSRTC_TypeDef; @@ -15568,13 +15568,14 @@ typedef struct { */ typedef struct { union { - __IM uint32_t DATA_REG; /*!< (@ 0x00000000) SDC Data register */ + __IM unsigned int DATA_REG; /*!< (@ 0x00000000) SDC Data register */ struct { - __IM uint32_t - SDC_DATA_SAMPLE : 12; /*!< [11..0] Sample 0 collected from Sensor through Aux ADC. */ - __IM uint32_t SMP_ID_CH : 2; /*!< [13..12] Channel iD for sample */ - __IM uint32_t RESERVED1 : 18; /*!< [31..14] reserved1 */ + __IM unsigned int + SDC_DATA_SAMPLE : 12; /*!< [11..0] Sample 0 collected from Sensor through Aux ADC. */ + __IM unsigned int SMP_ID_CH : 2; /*!< [13..12] Channel iD for sample */ + __IM unsigned int + RESERVED1 : 18; /*!< [31..14] reserved1 */ } DATA_REG_b; }; } SDC_SDC_DATA_REG_Type; @@ -15586,222 +15587,250 @@ typedef struct { typedef struct { /*!< (@ 0x24042400) SDC Structure */ union { - __IOM uint32_t SDC_GEN_CONFIG_0; /*!< (@ 0x00000000) SDC general configuration 0 */ + __IOM unsigned int + SDC_GEN_CONFIG_0; /*!< (@ 0x00000000) SDC general configuration 0 */ struct { - __IOM uint32_t INTR_STATUS_CLEAR : 1; /*!< [0..0] Writing 1 clears interrupt, reading gives SDC Interrupt + __IOM unsigned int INTR_STATUS_CLEAR : 1; /*!< [0..0] Writing 1 clears interrupt, reading gives SDC Interrupt status */ - __IOM uint32_t RESERVED1 : 31; /*!< [31..1] Reserevd */ + __IOM unsigned int + RESERVED1 : 31; /*!< [31..1] Reserevd */ } SDC_GEN_CONFIG_0_b; }; union { - __IOM uint32_t SDC_GEN_CONFIG_1; /*!< (@ 0x00000004) SDC general configuration 1 */ + __IOM unsigned int + SDC_GEN_CONFIG_1; /*!< (@ 0x00000004) SDC general configuration 1 */ struct { - __IOM uint32_t RST_WRT_PTR : 1; /*!< [0..0] Writing 1 will resets the write pointer so that new samples + __IOM unsigned int RST_WRT_PTR : 1; /*!< [0..0] Writing 1 will resets the write pointer so that new samples can be filled in Buffer. */ - __IM uint32_t WRT_PTR : 4; /*!< [4..1] Write pointer Value */ - __IOM uint32_t SAMP_THRESH : 4; /*!< [8..5] Number of data sampled to be collected from Aux-ADC and + __IM unsigned int WRT_PTR : 4; /*!< [4..1] Write pointer Value */ + __IOM unsigned int SAMP_THRESH : 4; /*!< [8..5] Number of data sampled to be collected from Aux-ADC and stored in Buffer before interrupt is raised/wakeup is initialed */ - __IOM uint32_t RESERVED1 : 23; /*!< [31..9] Reserevd */ + __IOM unsigned int + RESERVED1 : 23; /*!< [31..9] Reserevd */ } SDC_GEN_CONFIG_1_b; }; union { - __IOM uint32_t SDC_GEN_CONFIG_2; /*!< (@ 0x00000008) SDC general configuration 2 */ + __IOM unsigned int + SDC_GEN_CONFIG_2; /*!< (@ 0x00000008) SDC general configuration 2 */ struct { - __IOM uint32_t SDC_SAMP_EN : 1; /*!< [0..0] SDC Data Sampling mode */ - __IOM uint32_t NUM_CH_SEL : 3; /*!< [3..1] Number of Channels to be used */ - __IOM uint32_t RESERVED1 : 28; /*!< [31..4] Reserevd */ + __IOM unsigned int + SDC_SAMP_EN : 1; /*!< [0..0] SDC Data Sampling mode */ + __IOM unsigned int + NUM_CH_SEL : 3; /*!< [3..1] Number of Channels to be used */ + __IOM unsigned int + RESERVED1 : 28; /*!< [31..4] Reserevd */ } SDC_GEN_CONFIG_2_b; }; union { - __IOM uint32_t SDC_GEN_CONFIG_3; /*!< (@ 0x00000014) SDC general configuration 3 */ + __IOM unsigned int + SDC_GEN_CONFIG_3; /*!< (@ 0x00000014) SDC general configuration 3 */ struct { - __IOM uint32_t + __IOM unsigned int SAMP_TRIG_SEL : 1; /*!< [0..0] select the trigger event on which AUX-ADC Data is sampled */ - __IOM uint32_t - CNT_TRIG_EVNT : 10; /*!< [10..1] which trigger event AUX-ADC Data will sampled */ - __IOM uint32_t SDC_CLK_DIV : 10; /*!< [20..11] SDCSS clock division factor */ - __IOM uint32_t RESERVED1 : 11; /*!< [31..21] Reserevd */ + __IOM unsigned int + CNT_TRIG_EVNT : 10; /*!< [10..1] which trigger event AUX-ADC Data will sampled */ + __IOM unsigned int + SDC_CLK_DIV : 10; /*!< [20..11] SDCSS clock division factor */ + __IOM unsigned int + RESERVED1 : 11; /*!< [31..21] Reserevd */ } SDC_GEN_CONFIG_3_b; }; - __IM uint32_t RESERVED[2]; + __IM unsigned int RESERVED[2]; union { - __IOM uint32_t + __IOM unsigned int SDC_AUXADC_CONFIG_1; /*!< (@ 0x00000018) SDC AUX ADC configuration 1 */ struct { - __IOM uint32_t + __IOM unsigned int SDC_AUXADC_INPUT_P_SEL_CH1 : 5; /*!< [4..0] AUXADC's Positive Input Mux Select for Channel-1 */ - __IOM uint32_t + __IOM unsigned int SDC_AUXADC_INPUT_N_SEL_CH1 : 4; /*!< [8..5] AUXADC's Negative Input Mux Select for Channel-1 */ - __IOM uint32_t + __IOM unsigned int SDC_AUXADC_DIFF_MODE_CH1 : 1; /*!< [9..9] Enable Differential Mode in AUX ADC for Channel -1 */ - __IOM uint32_t + __IOM unsigned int SDC_AUXADC_EN : 1; /*!< [10..10] AUXADC Enable from SDC Block */ - __IOM uint32_t SDC_ADC_CONFIG_EN : 1; /*!< [11..11] On Enabling this register, SDC ADC Configuration will + __IOM unsigned int SDC_ADC_CONFIG_EN : 1; /*!< [11..11] On Enabling this register, SDC ADC Configuration will be Applied. */ - __IOM uint32_t RESERVED1 : 20; /*!< [31..12] Reserevd */ + __IOM unsigned int + RESERVED1 : 20; /*!< [31..12] Reserevd */ } SDC_AUXADC_CONFIG_1_b; }; union { - __IOM uint32_t + __IOM unsigned int SDC_AUXDAC_CONFIG_1; /*!< (@ 0x0000001C) SDC AUX DAC configuration 1 */ struct { - __IOM uint32_t SDC_DAC_EN : 1; /*!< [0..0] Enable signal DAC */ - __IOM uint32_t + __IOM unsigned int + SDC_DAC_EN : 1; /*!< [0..0] Enable signal DAC */ + __IOM unsigned int SDC_DAC_OUT_MUX_EN : 1; /*!< [1..1] Enable signal for Connecting DAC Output to GPIO */ - __IOM uint32_t SDC_DAC_OUT_MUX_SEL : 1; /*!< [2..2] Programming register for choosing GPIO in which DAC Output + __IOM unsigned int SDC_DAC_OUT_MUX_SEL : 1; /*!< [2..2] Programming register for choosing GPIO in which DAC Output is connected */ - __IOM uint32_t RESERVED1 : 1; /*!< [3..3] Reserved */ - __IOM uint32_t + __IOM unsigned int + RESERVED1 : 1; /*!< [3..3] Reserved */ + __IOM unsigned int SDC_DAC_DATA : 10; /*!< [13..4] SDC Aux DAC Data */ - __IOM uint32_t SDC_DAC_CONFIG_EN : 1; /*!< [14..14] On Enabling this register, SDC DAC Configuration will + __IOM unsigned int SDC_DAC_CONFIG_EN : 1; /*!< [14..14] On Enabling this register, SDC DAC Configuration will be Applied. */ - __IOM uint32_t RESERVED2 : 17; /*!< [31..15] Reserevd */ + __IOM unsigned int + RESERVED2 : 17; /*!< [31..15] Reserevd */ } SDC_AUXDAC_CONFIG_1_b; }; union { - __IOM uint32_t SDC_AUXLDO_CONFIG; /*!< (@ 0x00000020) SDC AUX LDO configuration */ + __IOM unsigned int + SDC_AUXLDO_CONFIG; /*!< (@ 0x00000020) SDC AUX LDO configuration */ struct { - __IOM uint32_t - SDC_AUXLDO_VOLT_CTRL : 4; /*!< [3..0] SDC AUX LDO Voltage Control Selection */ - __IOM uint32_t RESERVED1 : 1; /*!< [4..4] RESERVED */ - __IOM uint32_t SDC_AUXLDO_BYP_EB : 1; /*!< [5..5] Configure AUXLDO in Buypass mode.When Enabled, Ouput + __IOM unsigned int + SDC_AUXLDO_VOLT_CTRL : 4; /*!< [3..0] SDC AUX LDO Voltage Control Selection */ + __IOM unsigned int + RESERVED1 : 1; /*!< [4..4] RESERVED */ + __IOM unsigned int SDC_AUXLDO_BYP_EB : 1; /*!< [5..5] Configure AUXLDO in Buypass mode.When Enabled, Ouput supply of LDO will be same as Input supply. */ - __IOM uint32_t + __IOM unsigned int SDC_AUXLDO_EN : 1; /*!< [6..6] Turn-On AUX LDO */ - __IOM uint32_t - SDC_AUXLDO_CONFIG_EN : 1; /*!< [7..7] SDC Aux LDO Configuration Control Enable */ - __IOM uint32_t RESERVED2 : 24; /*!< [31..8] Reserved */ + __IOM unsigned int + SDC_AUXLDO_CONFIG_EN : 1; /*!< [7..7] SDC Aux LDO Configuration Control Enable */ + __IOM unsigned int + RESERVED2 : 24; /*!< [31..8] Reserved */ } SDC_AUXLDO_CONFIG_b; }; union { - __IOM uint32_t + __IOM unsigned int SDC_AUXOPAMP_CONFIG_1; /*!< (@ 0x00000024) SDC AUX OPAMP configuration 1 */ struct { - __IOM uint32_t SDC_OPAMP_EN_CH1 : 1; /*!< [0..0] Enable signal for turning OPAMP to used for Channel-1 + __IOM unsigned int SDC_OPAMP_EN_CH1 : 1; /*!< [0..0] Enable signal for turning OPAMP to used for Channel-1 Operation */ - __IOM uint32_t + __IOM unsigned int SDC_OPAMP_LP_MODE : 1; /*!< [1..1] Configuration of OPAMP1 Operation mode */ - __IOM uint32_t SDC_OPAMP_R1_SEL : 2; /*!< [3..2] Configuration for Resistor Ladder R1 of OPAMP1 for controlling + __IOM unsigned int + SDC_OPAMP_R1_SEL : 2; /*!< [3..2] Configuration for Resistor Ladder R1 of OPAMP1 for controlling it gain. */ - __IOM uint32_t SDC_OPAMP_R2_SEL : 3; /*!< [6..4] Configuration for Resistor Ladder R2 of OPAMP1 for controlling + __IOM unsigned int + SDC_OPAMP_R2_SEL : 3; /*!< [6..4] Configuration for Resistor Ladder R2 of OPAMP1 for controlling it gain. */ - __IOM uint32_t SDC_OPAMP_RES_BACK_EN : 1; /*!< [7..7] Configuration register for controlling Resistor Bank + __IOM unsigned int SDC_OPAMP_RES_BACK_EN : 1; /*!< [7..7] Configuration register for controlling Resistor Bank of OPAMP */ - __IOM uint32_t SDC_OPAMP_RES_MUX_SEL : 3; /*!< [10..8] Configuration register for Connecting R1 Resistor Ladder + __IOM unsigned int + SDC_OPAMP_RES_MUX_SEL : 3; /*!< [10..8] Configuration register for Connecting R1 Resistor Ladder input */ - __IOM uint32_t - SDC_OPAMP_RES_TO_OUT_VDD : 1; /*!< [11..11] Configuration register for Connecting R2 Resistor Ladder + __IOM unsigned int + SDC_OPAMP_RES_TO_OUT_VDD : 1; /*!< [11..11] Configuration register for Connecting R2 Resistor Ladder input */ - __IOM uint32_t SDC_OPAMP_OUT_MUX_EN : 1; /*!< [12..12] Configur this register to OPAMP1 Output will be connected + __IOM unsigned int + SDC_OPAMP_OUT_MUX_EN : 1; /*!< [12..12] Configur this register to OPAMP1 Output will be connected to GPIO */ - __IOM uint32_t + __IOM unsigned int SDC_OPAMP_IN_N_SEL : 3; /*!< [15..13] Configuration register for selecting N Input of OPAMP1. */ - __IOM uint32_t + __IOM unsigned int SDC_OPAMP_IN_P_SEL_CH1 : 4; /*!< [19..16] Configuration register for selecting P Input of OPAMP1.,for CH1 */ - __IOM uint32_t SDC_OPAMP_OUT_MUX_SEL : 1; /*!< [20..20] Configuration register for connecting OPAMP1 output + __IOM unsigned int SDC_OPAMP_OUT_MUX_SEL : 1; /*!< [20..20] Configuration register for connecting OPAMP1 output to GPIO */ - __IM uint32_t RESERVED1 : 1; /*!< [21..21] Reserved */ - __IOM uint32_t SDC_VREF_MUX_1_EN : 1; /*!< [22..22] Connect Low Drive Strength voltage reference for ULP + __IM unsigned int RESERVED1 : 1; /*!< [21..21] Reserved */ + __IOM unsigned int SDC_VREF_MUX_1_EN : 1; /*!< [22..22] Connect Low Drive Strength voltage reference for ULP GPIO 1 For external use */ - __IOM uint32_t SDC_VREF_MUX_2_EN : 1; /*!< [23..23] Connect Low Drive Strength voltage reference for ULP + __IOM unsigned int SDC_VREF_MUX_2_EN : 1; /*!< [23..23] Connect Low Drive Strength voltage reference for ULP GPIO 3 For external use */ - __IOM uint32_t SDC_VREF_MUX_3_EN : 1; /*!< [24..24] Connect Low Drive Strength voltage reference for ULP + __IOM unsigned int SDC_VREF_MUX_3_EN : 1; /*!< [24..24] Connect Low Drive Strength voltage reference for ULP GPIO 4 For external use */ - __IOM uint32_t SDC_VREF_MUX_4_EN : 1; /*!< [25..25] Connect Low Drive Strength voltage reference for ULP + __IOM unsigned int SDC_VREF_MUX_4_EN : 1; /*!< [25..25] Connect Low Drive Strength voltage reference for ULP GPIO 15 For external use */ - __IOM uint32_t RESERVED2 : 1; /*!< [26..26] Reserved */ - __IOM uint32_t SDC_VREF_MUX_1_SEL : 1; /*!< [27..27] Selection register for choosing Voltage reference to + __IOM unsigned int + RESERVED2 : 1; /*!< [26..26] Reserved */ + __IOM unsigned int SDC_VREF_MUX_1_SEL : 1; /*!< [27..27] Selection register for choosing Voltage reference to external use on ULP_GPIO_1 */ - __IOM uint32_t SDC_VREF_MUX_2_SEL : 1; /*!< [28..28] Selection register for choosing Voltage reference to + __IOM unsigned int SDC_VREF_MUX_2_SEL : 1; /*!< [28..28] Selection register for choosing Voltage reference to external use on ULP_GPIO_3 */ - __IOM uint32_t SDC_VREF_MUX_3_SEL : 1; /*!< [29..29] Selection register for choosing Voltage reference to + __IOM unsigned int SDC_VREF_MUX_3_SEL : 1; /*!< [29..29] Selection register for choosing Voltage reference to external use on ULP_GPIO_4 */ - __IOM uint32_t SDC_VREF_MUX_4_SEL : 1; /*!< [30..30] Selection register for choosing Voltage reference to + __IOM unsigned int SDC_VREF_MUX_4_SEL : 1; /*!< [30..30] Selection register for choosing Voltage reference to external use on ULP_GPIO_15 */ - __IOM uint32_t SDC_OPAMP_CONFIG_EN : 1; /*!< [31..31] On Enabling this register, SDC OPAMP Configuration + __IOM unsigned int SDC_OPAMP_CONFIG_EN : 1; /*!< [31..31] On Enabling this register, SDC OPAMP Configuration will be Applied. */ } SDC_AUXOPAMP_CONFIG_1_b; }; union { - __IOM uint32_t + __IOM unsigned int SDC_AUXADC_CONFIG_2; /*!< (@ 0x00000028) SDC AUX ADC configuration 2 */ struct { - __IOM uint32_t + __IOM unsigned int SDC_AUXADC_INPUT_P_SEL_CH2 : 5; /*!< [4..0] AUXADC's Positive Input Mux Select for Channel-2 */ - __IOM uint32_t + __IOM unsigned int SDC_AUXADC_INPUT_N_SEL_CH2 : 4; /*!< [8..5] AUXADC's Negative Input Mux Select for Channel-2 */ - __IOM uint32_t + __IOM unsigned int SDC_AUXADC_DIFF_MODE_CH2 : 1; /*!< [9..9] 1-AUX ADC Differencial mode, 0 - Single Ended Mode */ - __IOM uint32_t RESERVED1 : 22; /*!< [31..10] Reserevd */ + __IOM unsigned int + RESERVED1 : 22; /*!< [31..10] Reserevd */ } SDC_AUXADC_CONFIG_2_b; }; union { - __IOM uint32_t + __IOM unsigned int SDC_AUXADC_CONFIG_3; /*!< (@ 0x0000002C) SDC AUX ADC configuration 3 */ struct { - __IOM uint32_t + __IOM unsigned int SDC_AUXADC_INPUT_P_SEL_CH3 : 5; /*!< [4..0] AUXADC's Positive Input Mux Select for Channel-3 */ - __IOM uint32_t + __IOM unsigned int SDC_AUXADC_INPUT_N_SEL_CH3 : 4; /*!< [8..5] AUXADC's Negative Input Mux Select for Channel-3 */ - __IOM uint32_t + __IOM unsigned int SDC_AUXADC_DIFF_MODE_CH3 : 1; /*!< [9..9] 1-AUX ADC Differencial mode, 0 - Single Ended Mode */ - __IOM uint32_t RESERVED1 : 22; /*!< [31..10] Reserved */ + __IOM unsigned int + RESERVED1 : 22; /*!< [31..10] Reserved */ } SDC_AUXADC_CONFIG_3_b; }; union { - __IOM uint32_t + __IOM unsigned int SDC_AUXADC_CONFIG_4; /*!< (@ 0x00000030) SDC AUX ADC configuration 4 */ struct { - __IOM uint32_t + __IOM unsigned int SDC_AUXADC_INPUT_P_SEL_CH4 : 5; /*!< [4..0] AUXADC's Positive Input Mux Select for Channel-4 */ - __IOM uint32_t + __IOM unsigned int SDC_AUXADC_INPUT_N_SEL_CH4 : 4; /*!< [8..5] AUXADC's Negative Input Mux Select for Channel-4 */ - __IOM uint32_t + __IOM unsigned int SDC_AUXADC_DIFF_MODE_CH4 : 1; /*!< [9..9] 1-AUX ADC Differencial mode, 0 - Single Ended Mode */ - __IOM uint32_t RESERVED1 : 22; /*!< [31..10] Reserved */ + __IOM unsigned int + RESERVED1 : 22; /*!< [31..10] Reserved */ } SDC_AUXADC_CONFIG_4_b; }; union { - __IOM uint32_t + __IOM unsigned int SDC_AUXOPAMP_CONFIG_2; /*!< (@ 0x00000034) SDC AUX OPAMP Configuration 2 */ struct { - __IOM uint32_t SDC_OPAMP_EN_CH2 : 1; /*!< [0..0] Enable signal for turning OPAMP to used for Channel-2 + __IOM unsigned int SDC_OPAMP_EN_CH2 : 1; /*!< [0..0] Enable signal for turning OPAMP to used for Channel-2 Operation */ - __IOM uint32_t SDC_OPAMP_IN_P_SEL_CH2 : 4; /*!< [4..1] Configuration register for selecting P Input of OPAMP1 + __IOM unsigned int SDC_OPAMP_IN_P_SEL_CH2 : 4; /*!< [4..1] Configuration register for selecting P Input of OPAMP1 for Channel-2 */ - __IOM uint32_t SDC_OPAMP_EN_CH3 : 1; /*!< [5..5] Enable signal for turning OPAMP to used for Channel-4 + __IOM unsigned int SDC_OPAMP_EN_CH3 : 1; /*!< [5..5] Enable signal for turning OPAMP to used for Channel-4 Operation */ - __IOM uint32_t SDC_OPAMP_IN_P_SEL_CH3 : 4; /*!< [9..6] Configuration register for selecting P Input of OPAMP1 + __IOM unsigned int SDC_OPAMP_IN_P_SEL_CH3 : 4; /*!< [9..6] Configuration register for selecting P Input of OPAMP1 for Channel-3 */ - __IOM uint32_t SDC_OPAMP_EN_CH4 : 1; /*!< [10..10] Enable signal for turning OPAMP to used for Channel-4 + __IOM unsigned int SDC_OPAMP_EN_CH4 : 1; /*!< [10..10] Enable signal for turning OPAMP to used for Channel-4 Operation */ - __IOM uint32_t SDC_OPAMP_IN_P_SEL_CH4 : 1; /*!< [11..11] Configuration register for selecting P Input of OPAMP1 + __IOM unsigned int + SDC_OPAMP_IN_P_SEL_CH4 : 1; /*!< [11..11] Configuration register for selecting P Input of OPAMP1 for Channel-4 */ - uint32_t : 3; - __IOM uint32_t RESERVED1 : 17; /*!< [31..15] Reserved */ + unsigned int : 3; + __IOM unsigned int + RESERVED1 : 17; /*!< [31..15] Reserved */ } SDC_AUXOPAMP_CONFIG_2_b; }; __IOM SDC_SDC_DATA_REG_Type @@ -15983,7 +16012,7 @@ typedef struct { /*!< (@ 0x24042400) SDC Structure #if defined(__CC_ARM) #pragma pop #elif defined(__ICCARM__) - /* leave anonymous unions enabled */ + /* leave anonymous unions enabled */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #elif defined(__GNUC__) @@ -16004,4 +16033,4 @@ typedef struct { /*!< (@ 0x24042400) SDC Structure /** @} */ /* End of group RS1xxxx */ -/** @} */ /* End of group Silicon Lab Inc. */ +/** @} */ /* End of group Silicon Lab Inc. */ \ No newline at end of file diff --git a/components/device/silabs/si91x/mcu/core/chip/inc/system_si91x.h b/components/device/silabs/si91x/mcu/core/chip/inc/system_si91x.h index ea20cb7a2..c923ee74e 100644 --- a/components/device/silabs/si91x/mcu/core/chip/inc/system_si91x.h +++ b/components/device/silabs/si91x/mcu/core/chip/inc/system_si91x.h @@ -56,8 +56,8 @@ typedef enum SLEEP_TYPE { #define HF_MHZ_RO 3 #define BG_SLEEP_TIMER_REG_OFFSET 0x125 /*System default clocks*/ -#define DEFAULT_SOC_PLL_CLOCK 80000000 -#define DEFAULT_INTF_PLL_CLOCK 80000000 +#define DEFAULT_SOC_PLL_CLOCK 0 +#define DEFAULT_INTF_PLL_CLOCK 0 #define DEFAULT_MODEM_PLL_CLOCK 80000000 #define DEFAULT_32MHZ_RC_CLOCK 32000000 #define DEFAULT_20MHZ_RO_CLOCK 20000000 @@ -68,12 +68,16 @@ typedef enum SLEEP_TYPE { #define DEFAULT_RF_REF_CLOCK 40000000 #define DEFAULT_MEMS_REF_CLOCK 40000000 #define DEFAULT_BYP_RC_CLOCK 32000000 -#define DEFAULT_I2S_PLL_CLOCK 6144000 +#define DEFAULT_I2S_PLL_CLOCK 0 #define DEFAULT_REF_CLOCK 2 /* Selecting the PLL reference clock */ /* 0 - XTAL_CLK, 1 - Reserved, 2 - RC_32MHZ_CLK, 3 - Reserved */ #define PLL_REF_CLK_CONFIG_REG (*(volatile uint32_t *)(0x46180000UL + 0x00008000 + 0x04)) +#define RC_32MHZ_CLK_FREQ 32000000UL +#define SELECT_RC_MHZ_CLOCK BIT(15) +#define SELECT_XTAL_MHZ_CLOCK ~(BIT(14) | BIT(15)) +#define XTAL_CLK_FREQ 40000000UL #define M4SS_P2P_INT_BASE_ADDRESS 0x46008000 #ifdef SLI_SI91X_MCU_COMMON_FLASH_MODE @@ -129,6 +133,10 @@ typedef enum SLEEP_TYPE { /* Board capabilities */ #define SLI_CRYPTOACC_PRESENT_SI91X +/*XTAL bypass from MCU macros */ +#define XTAL_IS_IN_SW_CTRL_FROM_M4 0 +#define XTAL_DISABLE_FROM_M4 0 + /* system clock source look up table*/ typedef struct SYSTEM_CLOCK_SOURCE_FREQUENCIES { uint32_t m4ss_ref_clk; diff --git a/components/device/silabs/si91x/mcu/core/chip/src/iPMU_prog/iPMU_dotc/ipmu_apis.c b/components/device/silabs/si91x/mcu/core/chip/src/iPMU_prog/iPMU_dotc/ipmu_apis.c index e15a96f8b..3c2b2e540 100644 --- a/components/device/silabs/si91x/mcu/core/chip/src/iPMU_prog/iPMU_dotc/ipmu_apis.c +++ b/components/device/silabs/si91x/mcu/core/chip/src/iPMU_prog/iPMU_dotc/ipmu_apis.c @@ -77,7 +77,7 @@ typedef uint8_t uint8; #include "bb_rf_calib.h" #include "wrappers_common.h" #endif -void program_ipmu_data(uint32_t *src); +void program_ipmu_data(const uint32_t *src); #ifndef BT_LE_ONLY_MODE #ifdef SLI_SI91X_MCU_INTERFACE void ipmu_init_mcu(void); @@ -199,8 +199,8 @@ uint16 scdc_sleep; * @param void * @return void */ -void update_ipmu_calib_data(efuse_ipmu_t *ipmu_calib_data) __attribute__((section(".common_tcm_code"))); -void update_ipmu_calib_data(efuse_ipmu_t *ipmu_calib_data) +void update_ipmu_calib_data(const efuse_ipmu_t *ipmu_calib_data) __attribute__((section(".common_tcm_code"))); +void update_ipmu_calib_data(const efuse_ipmu_t *ipmu_calib_data) { uint32_t data; uint32_t mask; @@ -418,16 +418,22 @@ uint32_t init_ipmu_calib_data(uint32_t m4_present) #endif #ifdef IPMU_DOTC_PROG #ifdef SLI_SI91X_MCU_INTERFACE -void program_ipmu_data(uint32_t *src); +void program_ipmu_data(const uint32_t *src); #else -void program_ipmu_data(uint32_t *src) __attribute__((section(".common_non_tcm_code"))); +void program_ipmu_data(const uint32_t *src) __attribute__((section(".common_non_tcm_code"))); #endif -void program_ipmu_data(uint32_t *src) +void program_ipmu_data(const uint32_t *src) { - uint32_t write_data, num_of_reg, mask = 0, read_data; + uint32_t write_data; + uint32_t num_of_reg; + uint32_t mask = 0; + uint32_t read_data; uint32_t addr; - uint32_t ls_shift, ms_shift, mask_bits, inx = 0; - num_of_reg = src[inx]; + uint32_t ls_shift; + uint32_t ms_shift; + uint32_t mask_bits; + uint32_t inx = 0; + num_of_reg = src[inx]; inx++; //Dummy Read @@ -556,7 +562,8 @@ void ipmu_init(void) #ifndef IPMU_DOTC_PROG uint32_t pmu_1p3_ctrl_data; #endif - uint32_t pmu_1p2_ctrl_word, bypass_curr_ctrl_data; + uint32_t pmu_1p2_ctrl_word; + uint32_t bypass_curr_ctrl_data; retention_boot_status_word_t *retention_reg = (retention_boot_status_word_t *)MCURET_BOOTSTATUS; //! If M4 present and host interface with M4(M4 master) case, total IPMU and MCU FSM registers has to be initialised in M4. diff --git a/components/device/silabs/si91x/mcu/core/chip/src/rsi_deepsleep_soc.c b/components/device/silabs/si91x/mcu/core/chip/src/rsi_deepsleep_soc.c index b54375dcd..ba868e255 100644 --- a/components/device/silabs/si91x/mcu/core/chip/src/rsi_deepsleep_soc.c +++ b/components/device/silabs/si91x/mcu/core/chip/src/rsi_deepsleep_soc.c @@ -21,6 +21,7 @@ #include "rsi_ccp_common.h" #include "rsi_power_save.h" #include "rsi_temp_sensor.h" +#include "rsi_retention.h" #ifdef DEBUG_UART #include "rsi_debug.h" #endif @@ -31,9 +32,10 @@ void fpuInit(void); #define M4SS_TASS_CTRL_SET_REG (*(volatile uint32_t *)(0x24048400 + 0x34)) #define M4SS_TASS_CTRL_CLEAR_REG (*(volatile uint32_t *)(0x24048400 + 0x38)) #define M4SS_TASS_CTRL_CLR_REG (*(volatile uint32_t *)(0x24048400 + 0x38)) -#define MAX_NVIC_REGS 4 // Max Interrupts register -#define MAX_IPS 240 // Max Interrupt Priority registers -#define MAX_SHP 12 //Max System Handlers Priority registers +#define MAX_NVIC_REGS 4 // Max Interrupts register +#define MAX_IPS 240 // Max Interrupt Priority registers +#define MAX_SHP 12 // Max System Handlers Priority registers +#define NPSS_GPIO_CLR_VALUE 0x3E // NPSS GPIO rising edge interrupt clear value #ifdef SLI_SI91X_MCU_4MB_LITE_IMAGE #define MBR_MAGIC_WORD (*(volatile uint32_t *)(0x8160000)) @@ -63,7 +65,10 @@ extern sl_psram_return_type_t sl_si91x_psram_wakeup(void); uint32_t nvic_enable[MAX_NVIC_REGS] = { 0 }; uint8_t nvic_ip_reg[MAX_IPS] = { 0 }; uint8_t scs_shp_reg[MAX_SHP] = { 0 }; -volatile uint32_t msp_value, psp_value, control_reg_val; +volatile uint32_t msp_value; +volatile uint32_t psp_value; +volatile uint32_t control_reg_val; +uint32_t npss_gpio_config = 0; volatile uint32_t sl_magic_word_value = 0; @@ -272,7 +277,6 @@ void RSI_PS_RestoreCpuContext(void) */ void RSI_Set_Cntrls_To_M4(void) { - volatile uint8_t delay; #ifdef SLI_SI917B0 //!take TASS ref clock control to M4 MCUAON_CONTROL_REG4 &= ~(MCU_TASS_REF_CLK_SEL_MUX_CTRL); @@ -286,7 +290,7 @@ void RSI_Set_Cntrls_To_M4(void) BATT_FF->M4SS_TASS_CTRL_SET_REG_b.M4SS_CTRL_TASS_AON_DISABLE_ISOLATION_BYPASS = ENABLE; /* M4SS controlling Power supply for TASS AON domains reset pin in bypass mode. */ M4SS_TASS_CTRL_CLR_REG = M4SS_CTRL_TASS_AON_PWR_DMN_RST_BYPASS_BIT; - for (delay = 0; delay < 10; delay++) { + for (volatile uint8_t delay = 0; delay < 10; delay++) { __ASM("NOP"); } } @@ -321,10 +325,16 @@ void RSI_Set_Cntrls_To_TA(void) */ rsi_error_t RSI_PS_EnterDeepSleep(SLEEP_TYPE_T sleepType, uint8_t lf_clk_mode) { - volatile int var = 0, enable_sdcss_based_wakeup = 0, enable_m4ulp_retention = 0, Temp; - uint32_t ipmuDummyRead = 0, m4ulp_ram_core_status = 0, m4ulp_ram_peri_status = 0, disable_pads_ctrl = 0, - ulp_proc_clk = 0; - volatile uint8_t in_ps2_state = 0, x = 0; + volatile int var = 0; + volatile int enable_sdcss_based_wakeup = 0; + volatile int enable_m4ulp_retention = 0; + volatile int Temp; + uint32_t ipmuDummyRead = 0; + uint32_t m4ulp_ram_core_status = 0; + uint32_t m4ulp_ram_peri_status = 0; + uint32_t disable_pads_ctrl = 0; + uint32_t ulp_proc_clk = 0; + volatile uint8_t in_ps2_state = 0; sl_p2p_intr_status_bkp_t p2p_intr_status_bkp; /*Save the NVIC registers */ @@ -341,6 +351,8 @@ rsi_error_t RSI_PS_EnterDeepSleep(SLEEP_TYPE_T sleepType, uint8_t lf_clk_mode) } /*store the NPSS interrupt mask clear status*/ npssIntrState = NPSS_INTR_MASK_CLR_REG; + // Stores the NPSS GPIO interrupt configurations + npss_gpio_config = NPSS_GPIO_CONFIG_REG; /*Clear AUX and DAC pg enables */ if (!((MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE_b.SDCSS_BASED_WAKEUP_b) @@ -561,11 +573,11 @@ rsi_error_t RSI_PS_EnterDeepSleep(SLEEP_TYPE_T sleepType, uint8_t lf_clk_mode) #endif #ifndef SL_SI91X_NPSS_GPIO_BTN_HANDLER - //NPSS GPIO-2(Button) interrupt clr reg(GPIO_NPSS_INTERRUPT_CLEAR_REG) - (*(volatile uint32_t *)(0x12080000UL + 0x08)) = 0x08; + // Clearing NPSS GPIO rise edge interrupts to avoid false triggering after wakeup + NPSS_GPIO_CONFIG_CLR_REG = NPSS_GPIO_CLR_VALUE; - //NPSS GPIO-2(Button) low-level interrupt enable(GPIO_NPSS_GPIO_CONFIG_REG) - (*(volatile uint32_t *)(0x12080000UL + 0x10)) = BIT(18); + // Restoring the NPSS GPIO interrupt configurations after wakeup + NPSS_GPIO_CONFIG_REG = npss_gpio_config; #endif /* After wake-up, Set the SCDC voltage to the actual value*/ /* As this function is located in flash accessing this fucntion only after getting controls*/ @@ -651,9 +663,6 @@ rsi_error_t RSI_PS_EnterDeepSleep(SLEEP_TYPE_T sleepType, uint8_t lf_clk_mode) ULP_SPI_MEM_MAP(0x141) |= (BIT(11)); // ULP PADS PDO ON disable_pads_ctrl = 0; } - for (x = 0; x < 200; x++) { - __ASM("NOP"); - } /* powerup FPU domain*/ RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_M4_DEBUG_FPU); diff --git a/components/device/silabs/si91x/mcu/core/chip/src/startup_si91x.c b/components/device/silabs/si91x/mcu/core/chip/src/startup_si91x.c index 036c63e9c..a07278a48 100644 --- a/components/device/silabs/si91x/mcu/core/chip/src/startup_si91x.c +++ b/components/device/silabs/si91x/mcu/core/chip/src/startup_si91x.c @@ -57,13 +57,16 @@ extern unsigned long _sidata; /*!< Start address for the initialization values of the .data section. */ extern unsigned long _sdata; /*!< Start address for the .data section */ extern unsigned long _edata; /*!< End address for the .data section */ -extern unsigned long _slpcode; /*!< Start address for the initialization - values of the .sleep_psram_driver section. */ -extern unsigned long _scode; /*!< Start address for the .sleep_psram_driver section */ -extern unsigned long _ecode; /*!< End address for the .sleep_psram_driver section */ extern unsigned long __bss_start__; /*!< Start address for the .bss section */ extern unsigned long __bss_end__; /*!< End address for the .bss section */ +#if defined(NO_DATA_SEGMENT_IN_PSRAM) && (SLI_SI91X_MCU_ENABLE_PSRAM_SECTION_FEATURE == ENABLE) +extern unsigned long _slpcode; /*!< Start address for the initialization + values of the .sleep_psram_driver section. */ +extern unsigned long _scode; /*!< Start address for the .sleep_psram_driver section */ +extern unsigned long _ecode; /*!< End address for the .sleep_psram_driver section */ +#endif + /*--------------------------------------------------------------------------- * Internal References *---------------------------------------------------------------------------*/ @@ -200,13 +203,14 @@ void Default_Reset_Handler(void) void Copy_Table(void) { /* Initialize data and bss */ - volatile unsigned long *pulSrc, *pulDest; + volatile unsigned long *pulSrc; + volatile unsigned long *pulDest; pulSrc = &_sidata; /* Copy the data segment initializers from flash to SRAM */ for (pulDest = &_sdata; pulDest < &_edata;) { *(pulDest++) = *(pulSrc++); } -#if defined(SLI_SI91X_MCU_ENABLE_PSRAM_FEATURE) && (SLI_SI91X_MCU_ENABLE_PSRAM_FEATURE == ENABLE) +#if defined(NO_DATA_SEGMENT_IN_PSRAM) && (SLI_SI91X_MCU_ENABLE_PSRAM_SECTION_FEATURE == ENABLE) /* Copy the sleep PSRAM driver segment to SRAM */ pulSrc = &_slpcode; for (pulDest = &_scode; pulDest < &_ecode;) { diff --git a/components/device/silabs/si91x/mcu/core/chip/src/system_si91x.c b/components/device/silabs/si91x/mcu/core/chip/src/system_si91x.c index 134b7ae73..f5ee90918 100644 --- a/components/device/silabs/si91x/mcu/core/chip/src/system_si91x.c +++ b/components/device/silabs/si91x/mcu/core/chip/src/system_si91x.c @@ -30,6 +30,9 @@ #include "rsi_ulpss_clk.h" #include "rsi_rom_ulpss_clk.h" #include "rsi_rom_clks.h" +#if defined(NO_DATA_SEGMENT_IN_PSRAM) && (SLI_SI91X_MCU_ENABLE_PSRAM_SECTION_FEATURE == ENABLE) +#include "rsi_d_cache.h" +#endif /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ @@ -91,7 +94,9 @@ void SystemCoreClockUpdate(void) /* Get Core Clock Frequency */ SiliconRev = SILICON_REV_WMCU; package_type = PACKAGE_TYPE_WMCU; } - +#endif +#if defined(NO_DATA_SEGMENT_IN_PSRAM) && (SLI_SI91X_MCU_ENABLE_PSRAM_SECTION_FEATURE == ENABLE) + rsi_d_cache_invalidate_all(); #endif /*Initialize IPMU and MCU FSM blocks */ RSI_Ipmu_Init(); @@ -108,13 +113,23 @@ void SystemCoreClockUpdate(void) /* Get Core Clock Frequency */ MCU_FSM->MCU_FSM_REF_CLK_REG_b.TASS_REF_CLK_SEL = ULP_32MHZ_RC_CLK; /* Changing NPSS GPIO 0 mode to 0, to disable buck-boost enable mode*/ MCU_RET->NPSS_GPIO_CNTRL[0].NPSS_GPIO_CTRLS_b.NPSS_GPIO_MODE = 0; - /* Configuring RO-32KHz Clock for BG_PMU */ - RSI_IPMU_ClockMuxSel(1); - /* Configuring XTAL 32KHz Clock for LF-FSM */ + /* Configuring MCU FSM clock for BG_PMU */ + RSI_IPMU_ClockMuxSel(2); + +#if defined(SL_SI91X_MODULE_BOARD) + /* Configuring RC 32KHz Clock for LF-FSM*/ + RSI_PS_FsmLfClkSel(KHZ_RC_CLK_SEL); +#else + /* Configuring XTAL 32.768kHz Clock for LF-FSM */ RSI_PS_FsmLfClkSel(KHZ_XTAL_CLK_SEL); +#endif // SL_SI91X_MODULE_BOARD + /* Configuring RC-32MHz Clock for HF-FSM */ RSI_PS_FsmHfClkSel(FSM_32MHZ_RC); + /* XTAL control pointed to Software and XTAL is Turned-Off from M4 */ + RSI_ConfigXtal(XTAL_DISABLE_FROM_M4, XTAL_IS_IN_SW_CTRL_FROM_M4); + #if ((defined SLI_SI91X_MCU_COMMON_FLASH_MODE) && (!(defined(RAM_COMPILATION)))) /* Before TA is going to power save mode ,set m4ss_ref_clk_mux_ctrl , tass_ref_clk_mux_ctrl, AON domain power supply controls form TA to M4 */ diff --git a/components/device/silabs/si91x/mcu/core/common/freertos_config/FreeRTOSConfig.h b/components/device/silabs/si91x/mcu/core/common/freertos_config/FreeRTOSConfig.h index 12c346e5d..9bc371008 100644 --- a/components/device/silabs/si91x/mcu/core/common/freertos_config/FreeRTOSConfig.h +++ b/components/device/silabs/si91x/mcu/core/common/freertos_config/FreeRTOSConfig.h @@ -115,7 +115,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. // Define the following macro to set xExpectedIdleTime to 0 // if the application prevents the device Sleep -#define configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING(x) sl_si91x_pre_supress_ticks_and_sleep(&x) +#define configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING(x) // Activate SiWx917 MCU specific low power functionality #define configPRE_SLEEP_PROCESSING(x) diff --git a/components/device/silabs/si91x/mcu/core/common/inc/rsi_debug.h b/components/device/silabs/si91x/mcu/core/common/inc/rsi_debug.h index ff694b79a..30eeccf7c 100644 --- a/components/device/silabs/si91x/mcu/core/common/inc/rsi_debug.h +++ b/components/device/silabs/si91x/mcu/core/common/inc/rsi_debug.h @@ -28,7 +28,7 @@ extern "C" { /*Sample print prototype*/ void Board_Debug_Init(void); -void Board_UARTPutSTR(uint8_t *ptr); +void Board_UARTPutSTR(const uint8_t *ptr); uint8_t Board_UARTGetChar(void); void Board_UARTPutChar(uint8_t ch); diff --git a/components/device/silabs/si91x/mcu/core/common/inc/syscalls.h b/components/device/silabs/si91x/mcu/core/common/inc/syscalls.h index 61d30d511..3424fbb4b 100644 --- a/components/device/silabs/si91x/mcu/core/common/inc/syscalls.h +++ b/components/device/silabs/si91x/mcu/core/common/inc/syscalls.h @@ -41,14 +41,14 @@ void *_sbrk(int incr); int _isatty(int file); int _lseek(int file, int ptr, int dir); int _read(char *fmt_ptr, ...); -int _open(char *path, int flags, ...); -int _wait(int *status); -int _unlink(char *name); -int _link(char *old_link, char *new_link); +int _open(const char *path, int flags, ...); +int _wait(const int *status); +int _unlink(const char *name); +int _link(const char *old_link, const char *new_link); int _fork(void); -int _execve(char *name, char **argv, char **env); -int _stat(char *file, struct stat *st); -int _times(struct tms *buff); +int _execve(const char *name, char **argv, char **env); +int _stat(const char *file, struct stat *st); +int _times(const struct tms *buff); int _fstat(int file, struct stat *st); SL_WEAK void _putchar(char character); diff --git a/components/device/silabs/si91x/mcu/core/common/src/rsi_debug.c b/components/device/silabs/si91x/mcu/core/common/src/rsi_debug.c index 70c648e71..d5c6375d4 100644 --- a/components/device/silabs/si91x/mcu/core/common/src/rsi_debug.c +++ b/components/device/silabs/si91x/mcu/core/common/src/rsi_debug.c @@ -58,7 +58,8 @@ static ARM_DRIVER_USART *UARTdrv = &Driver_ULP_UART; ARM_USART_CAPABILITIES drv_ulp_capabilities; -volatile uint32_t send_done = 0, recv_done = 0; +volatile uint32_t send_done = 0; +volatile uint32_t recv_done = 0; #ifdef SLI_SI91X_MCU_INTR_BASED_RX_ON_UART // Add this macro to receive data in interrupt based uint8_t rx_char; #endif @@ -172,10 +173,12 @@ void Board_Debug_Init(void) #endif /* defined(DEBUG_ENABLE) */ #if !defined(DEBUG_SEMIHOSTING) -int WRITEFUNC(int iFileHandle, char *pcBuffer, int iLength); -int WRITEFUNC(int iFileHandle, char *pcBuffer, int iLength) +int WRITEFUNC(int iFileHandle, const char *pcBuffer, int iLength); +int WRITEFUNC(int iFileHandle, const char *pcBuffer, int iLength) { (void)iFileHandle; + (void)pcBuffer; // Explicitly mark pcBuffer as unused to avoid warnings + #if defined(DEBUG_ENABLE) int i; for (i = 0; i < iLength; i++) { @@ -291,15 +294,14 @@ int ferror(FILE *f) * @{ */ /** - * @fn void Board_UARTPutSTR(uint8_t *ptr) + * @fn void Board_UARTPutSTR(const uint8_t *ptr) * @brief Prints a string to the UART. * @param[in] ptr : Terminated string to output * @return none */ -void Board_UARTPutSTR(uint8_t *ptr) +void Board_UARTPutSTR(const uint8_t *ptr) { - int i; - for (i = 0; ptr[i] != '\0'; i++) { + for (int i = 0; ptr[i] != '\0'; i++) { send_done = 0; UARTdrv->Send(&ptr[i], 1); while (send_done == 0) diff --git a/components/device/silabs/si91x/mcu/core/common/src/syscalls.c b/components/device/silabs/si91x/mcu/core/common/src/syscalls.c index 3b047b13a..4d9835f7f 100644 --- a/components/device/silabs/si91x/mcu/core/common/src/syscalls.c +++ b/components/device/silabs/si91x/mcu/core/common/src/syscalls.c @@ -46,9 +46,12 @@ #define IO_MAXLINE 20U //maximun read length typedef int (*PUTCHAR_FUNC)(int a); char *stack_ptr __asm("sp"); -extern void Serial_send(uint8_t ch); extern char __HeapBase[]; extern char __HeapLimit[]; +#ifdef DEBUG_SERIAL +extern void Serial_send(uint8_t ch); +extern char Serial_receive(void); +#endif // DEBUG_SERIAL char *__env[1] = { 0 }; char **environ = __env; @@ -110,7 +113,6 @@ int _write(int file, char *ptr, int len) #else Board_UARTPutChar(*ptr++); - (void)Serial_send; #endif } @@ -473,7 +475,7 @@ int _read(char *fmt_ptr, ...) return result; } -int _open(char *path, int flags, ...) +int _open(const char *path, int flags, ...) { (void)path; (void)flags; @@ -481,34 +483,34 @@ int _open(char *path, int flags, ...) return -1; } -int _wait(int *status) +int _wait(const int *status) { (void)status; errno = ECHILD; return -1; } -int _unlink(char *name) +int _unlink(const char *name) { (void)name; errno = ENOENT; return -1; } -int _times(struct tms *buff) +int _times(const struct tms *buff) { (void)buff; return -1; } -int _stat(char *file, struct stat *st) +int _stat(const char *file, struct stat *st) { (void)file; st->st_mode = S_IFCHR; return 0; } -int _link(char *old_link, char *new_link) +int _link(const char *old_link, const char *new_link) { (void)old_link; //This statement is added only to resolve compilation warning, value is unchanged (void)new_link; //This statement is added only to resolve compilation warning, value is unchanged @@ -522,7 +524,7 @@ int _fork(void) return -1; } -int _execve(char *name, char **argv, char **env) +int _execve(const char *name, char **argv, char **env) { (void)name; (void)argv; diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_USART.h b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_USART.h index 5b3b519f2..462185ff1 100644 --- a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_USART.h +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_USART.h @@ -315,7 +315,7 @@ typedef struct _ARM_DRIVER_USART { int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_USART_Uninitialize : De-initialize USART Interface. int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_USART_PowerControl : Control USART Interface Power. int32_t (*Send) (const void *data, uint32_t num); ///< Pointer to \ref ARM_USART_Send : Start sending data to USART transmitter. - int32_t (*Receive) ( void *data, uint32_t num); ///< Pointer to \ref ARM_USART_Receive : Start receiving data from USART receiver. + int32_t (*Receive) (const void *data, uint32_t num); ///< Pointer to \ref ARM_USART_Receive : Start receiving data from USART receiver. int32_t (*Transfer) (const void *data_out, void *data_in, uint32_t num); ///< Pointer to \ref ARM_USART_Transfer : Start sending/receiving data to/from USART. diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/GSPI.c b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/GSPI.c index 26521ac2d..4dd437f68 100644 --- a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/GSPI.c +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/GSPI.c @@ -45,6 +45,7 @@ extern RSI_UDMA_HANDLE_T udmaHandle0; //check extern uint32_t dma_rom_buff0[30]; //we can keep wrapeers #define CONTROL_STRUCT0 (UDMA_NUMBER_OF_CHANNELS * 2) +#define MAX_FRAME_LENGTH 16 /* IAR support */ #if defined(__ICCARM__) @@ -358,7 +359,11 @@ ARM_DRIVER_SPI Driver_GSPI_MASTER = { // To get the Frame length uint32_t GSPI_GetFrameLength(void) { - return GSPI_MASTER_Resources.reg->GSPI_WRITE_DATA2_b.GSPI_MANUAL_WRITE_DATA2; + uint32_t frame_length = GSPI_MASTER_Resources.reg->GSPI_WRITE_DATA2_b.GSPI_MANUAL_WRITE_DATA2; + if (!frame_length) { + frame_length = MAX_FRAME_LENGTH; + } + return frame_length; } // To enable/disable the swapping of byte for read and write operation @@ -371,14 +376,14 @@ int32_t GSPI_SwapReadWriteByte(boolean_t read, boolean_t write) return ARM_DRIVER_ERROR_BUSY; } if (read) { - GSPI_MASTER_Resources.reg->GSPI_CONFIG2 &= ~BIT(4); + GSPI_MASTER_Resources.reg->GSPI_CONFIG2_b.GSPI_RD_DATA_SWAP_MNL_CSN0 = ENABLE; } else { - GSPI_MASTER_Resources.reg->GSPI_CONFIG2 |= BIT(4); + GSPI_MASTER_Resources.reg->GSPI_CONFIG2_b.GSPI_RD_DATA_SWAP_MNL_CSN0 = DISABLE; } if (write) { - GSPI_MASTER_Resources.reg->GSPI_CONFIG2 &= ~BIT(0); + GSPI_MASTER_Resources.reg->GSPI_CONFIG2_b.GSPI_WR_DATA_SWAP_MNL_CSN0 = ENABLE; } else { - GSPI_MASTER_Resources.reg->GSPI_CONFIG2 |= BIT(0); + GSPI_MASTER_Resources.reg->GSPI_CONFIG2_b.GSPI_WR_DATA_SWAP_MNL_CSN0 = DISABLE; } return ARM_DRIVER_OK; } diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/SPI.h b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/SPI.h index c511ba8d9..3a557dbe4 100644 --- a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/SPI.h +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/SPI.h @@ -51,6 +51,11 @@ #define SPI_MASTER_MODE 1U #define SPI_SLAVE_MODE 2U #define SPI_ULP_MASTER_MODE 3U +#define SSI_INSTANCE_BIT 30 // SSI Instance validation bits +#define SSI_INSTANCE_MASK 0x3FFFFFFF // Mask value for SSI instance +#define SSI_MASTER_INSTANCE 0 // SSI Master Instance +#define SSI_SLAVE_INSTANCE 1 // SSI Slave Instance +#define SSI_ULP_MASTER_INSTANCE 2 // SSI ULP Master Instance #define SPI_ISR_TX_FIFO_EMPTY BIT(0) #define SPI_ISR_TX_FIFO_OVERFLOW BIT(1) diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/UDMA.c b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/UDMA.c index 9ac9ae36d..a7039f180 100644 --- a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/UDMA.c +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/UDMA.c @@ -37,8 +37,10 @@ extern dac_config_t dac_callback_fun; #include "rsi_udma_wrapper.h" //UDMA Defines//// -RSI_UDMA_HANDLE_T udmaHandle0,udmaHandle1; -uint32_t dma_rom_buff0[30], dma_rom_buff1[30]; +RSI_UDMA_HANDLE_T udmaHandle0; +RSI_UDMA_HANDLE_T udmaHandle1; +uint32_t dma_rom_buff0[30]; +uint32_t dma_rom_buff1[30]; #if ((UDMA0_SRAM_BASE & (~0x3FF)) != UDMA0_SRAM_BASE) @@ -98,8 +100,12 @@ UDMA_RESOURCES UDMA1_Resources = { */ void uDMAx_IRQHandler(UDMA_RESOURCES *udma, RSI_UDMA_DESC_T *UDMA_Table, UDMA_Channel_Info *chnl_info) { - volatile uint32_t ch = 0, size = 0; - volatile uint32_t intr = 0, src_inc = 0, dst_inc = 0, dma_len = 0; + volatile uint32_t ch = 0; + volatile uint32_t size = 0; + volatile uint32_t intr = 0; + volatile uint32_t src_inc = 0; + volatile uint32_t dst_inc = 0; + volatile uint32_t dma_len = 0; for (ch = 0; ch < UDMA_NUMBER_OF_CHANNELS; ch++) { intr = udma->reg->UDMA_DONE_STATUS_REG; if (intr & (1U << ch)) { @@ -268,7 +274,6 @@ void IRQ033_Handler(void) void IRQ010_Handler (void) { NVIC_DisableIRQ(UDMA1_IRQn); - do { #if defined(DAC_FIFO_MODE_EN) || defined(ADC_MULTICHANNEL_WITH_EXT_DMA) volatile uint32_t intr = 0; intr = UDMA1_Resources.reg->UDMA_DONE_STATUS_REG; @@ -289,7 +294,8 @@ void IRQ010_Handler (void) adc_commn_config.call_back_event(ADC_CHNL0_INTR , EXTERNAL_DMA_RECONFIG); #endif } - break; + NVIC_EnableIRQ(UDMA1_IRQn); + return; } #endif #if defined(A11_ROM) && defined(UDMA_ROMDRIVER_PRESENT) @@ -318,6 +324,5 @@ void IRQ010_Handler (void) #else uDMAx_IRQHandler (&UDMA1_Resources,UDMA1_Table,udma1_chnl_info); #endif - } while(false); NVIC_EnableIRQ(UDMA1_IRQn); -} +} \ No newline at end of file diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/USART.c b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/USART.c index cc81bfd8f..ba67cb115 100644 --- a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/USART.c +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/USART.c @@ -47,8 +47,10 @@ #endif #define ARM_USART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,10) /* driver version */ -extern RSI_UDMA_HANDLE_T udmaHandle0,udmaHandle1; //check -extern uint32_t dma_rom_buff0[30], dma_rom_buff1[30]; //we can keep wrapeers +extern RSI_UDMA_HANDLE_T udmaHandle0; +extern RSI_UDMA_HANDLE_T udmaHandle1; //check +extern uint32_t dma_rom_buff0[30]; +extern uint32_t dma_rom_buff1[30]; //we can keep wrapeers #define CONTROL_STRUCT0 (UDMA_NUMBER_OF_CHANNELS * 2) #define CONTROL_STRUCT1 (ULP_UDMA_NUMBER_OF_CHANNELS * 2) @@ -451,12 +453,12 @@ ARM_DRIVER_VERSION ARM_USARTx_GetVersion(void) return UsartDriverVersion; } /** - @fn ARM_USART_CAPABILITIES USART_GetCapabilities (USART_RESOURCES *usart) + @fn ARM_USART_CAPABILITIES USART_GetCapabilities (const USART_RESOURCES *usart) @brief Gets driver capabilities @param[in] usart Pointer to USART resources @return \ref ARM_USART_CAPABILITIES */ -ARM_USART_CAPABILITIES USART_GetCapabilities (USART_RESOURCES *usart) +ARM_USART_CAPABILITIES USART_GetCapabilities (const USART_RESOURCES *usart) { return usart->capabilities; } @@ -509,7 +511,7 @@ static int32_t ARM_USART0_Send (const void *data, uint32_t num) #endif } -static int32_t ARM_USART0_Receive (void *data, uint32_t num) +static int32_t ARM_USART0_Receive (const void *data, uint32_t num) { if(num < RTE_USART0_DMA_RX_LEN_PER_DES) { USART0_Resources.dma_rx->control.totalNumOfDMATrans=(unsigned int)((num-1) & 0x03FF); @@ -714,7 +716,7 @@ static int32_t ARM_UART1_Send (const void *data, uint32_t num) #endif } -static int32_t ARM_UART1_Receive (void *data, uint32_t num) +static int32_t ARM_UART1_Receive (const void *data, uint32_t num) { if(num < RTE_UART1_DMA_RX_LEN_PER_DES) { UART1_Resources.dma_rx->control.totalNumOfDMATrans = (unsigned int)((num-1) & 0x03FF); @@ -913,7 +915,7 @@ static int32_t ARM_ULP_UART_Send (const void *data, uint32_t num) #endif } -static int32_t ARM_ULP_UART_Receive (void *data, uint32_t num) +static int32_t ARM_ULP_UART_Receive (const void *data, uint32_t num) { if(num < RTE_ULP_UART_DMA_RX_LEN_PER_DES) { ULP_UART_Resources.dma_rx->control.totalNumOfDMATrans = (unsigned int)((num-1) & 0x03FF); diff --git a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/USART.h b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/USART.h index db1fe9e54..c2ae389ad 100644 --- a/components/device/silabs/si91x/mcu/drivers/cmsis_driver/USART.h +++ b/components/device/silabs/si91x/mcu/drivers/cmsis_driver/USART.h @@ -130,7 +130,6 @@ typedef struct _USART0_DMA #define USART_RX_DATA_AVAILABLE (0x01 << 2) /*!< Received Data Available */ #define USART_RX_LINE_STATUS (0x03 << 1) /*!< Receiver line status */ #define USART_BUSY_DETECT (0x07 << 0) /*!< USART busy detect */ -#define USART_RX_CHAR_TIMEOUT (0x03 << 2) /*!< Receive character timeout */ #define USART_IIR_FIFO_ENABLE (0x03 << 6) /*!< IIR FIFO enabled */ /*!< USART (Modem status registers)*/ @@ -261,7 +260,7 @@ typedef struct USART_CLOCK clock; USART_SYNC_MODE sync_mode; } USART_RESOURCES; -ARM_USART_CAPABILITIES USART_GetCapabilities (USART_RESOURCES *usart); +ARM_USART_CAPABILITIES USART_GetCapabilities (const USART_RESOURCES *usart); ARM_DRIVER_VERSION ARM_USARTx_GetVersion(void); void IRQ038_Handler(void); void IRQ039_Handler(void); diff --git a/components/device/silabs/si91x/mcu/drivers/hardware_drivers/button/src/sl_si91x_button.c b/components/device/silabs/si91x/mcu/drivers/hardware_drivers/button/src/sl_si91x_button.c index 5abe70c4a..0cddf718c 100644 --- a/components/device/silabs/si91x/mcu/drivers/hardware_drivers/button/src/sl_si91x_button.c +++ b/components/device/silabs/si91x/mcu/drivers/hardware_drivers/button/src/sl_si91x_button.c @@ -34,7 +34,7 @@ /******************************************************************************* ******************************* DEFINES *********************************** ******************************************************************************/ -#define BUTTON_M4_INTR 7 // M4 Pin interrupt number +#define BUTTON_M4_INTR 6 // M4 Pin interrupt number #define BUTTON_UULP_INTR 2 // UULP GPIO pin interrupt 2 #define AVL_INTR_NO 0 // available interrupt number #define SL_SI91x_MAX_BUTTON_COUNT SL_SI91x_BUTTON_COUNT @@ -88,7 +88,7 @@ void sl_si91x_button_init(const sl_button_t *handle) if (handle->button_number == 0U) { /*GPIO clock is enabled*/ - sl_si91x_gpio_enable_clock((sl_si91x_gpio_select_clock_t)ULPCLK_GPIO); + sl_si91x_gpio_driver_enable_clock((sl_si91x_gpio_select_clock_t)ULPCLK_GPIO); /*UULP gpio is selected*/ sl_si91x_gpio_select_uulp_npss_receiver(handle->pin, 1); @@ -126,7 +126,10 @@ void sl_si91x_button_init(const sl_button_t *handle) sl_si91x_gpio_driver_set_pin_direction(handle->port, handle->pin, (sl_si91x_gpio_direction_t)GPIO_INPUT); /*REN enable */ - sl_si91x_gpio_driver_enable_pad_receiver(handle->pin); + sl_si91x_gpio_driver_enable_pad_receiver((handle->port * MAX_GPIO_PORT_PIN) + handle->pin); + + /* Set pin mode */ + sl_gpio_set_pin_mode(handle->port, handle->pin, (sl_gpio_mode_t)SL_GPIO_MODE_0, SET); status = sl_gpio_driver_configure_interrupt(&gpio_port_pin, BUTTON_M4_INTR, @@ -139,7 +142,7 @@ void sl_si91x_button_init(const sl_button_t *handle) } #elif SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER /*GPIO clock is enabled*/ - sl_si91x_gpio_enable_clock((sl_si91x_gpio_select_clock_t)ULPCLK_GPIO); + sl_si91x_gpio_driver_enable_clock((sl_si91x_gpio_select_clock_t)ULPCLK_GPIO); /*UULP gpio is selected*/ sl_si91x_gpio_select_uulp_npss_receiver(handle->pin, 1); @@ -221,11 +224,7 @@ int8_t sl_si91x_button_pin_state(uint8_t pin) * DEBOUNCE operation is based upon the theory that when multiple reads in a row * return the same value, we have passed any debounce created by the mechanical * action of a button. The define "DEBOUNCE" says how many reads in a row -* should return the same value. The value '5', below, is the recommended value -* since this should require the signal to have stabalized for approximately -* 100us which should be much longer than any debounce action. -* Uncomment the following line to enable software debounce operation: -* #define DEBOUNCE 5 +* should return the same value. * ******************************************************************************/ @@ -233,7 +232,7 @@ int8_t sl_si91x_button_pin_state(uint8_t pin) //which will cause the preprocessor to strip out the debounce code and save //flash space. #ifndef DEBOUNCE -#define DEBOUNCE 0 +#define DEBOUNCE 500 #endif //DEBOUNCE #if (SL_SI91x_BUTTON_COUNT > 0) diff --git a/components/device/silabs/si91x/mcu/drivers/hardware_drivers/icm40627/inc/sl_si91x_icm40627.h b/components/device/silabs/si91x/mcu/drivers/hardware_drivers/icm40627/inc/sl_si91x_icm40627.h index 9bceb76d9..a267bd820 100644 --- a/components/device/silabs/si91x/mcu/drivers/hardware_drivers/icm40627/inc/sl_si91x_icm40627.h +++ b/components/device/silabs/si91x/mcu/drivers/hardware_drivers/icm40627/inc/sl_si91x_icm40627.h @@ -206,7 +206,7 @@ extern "C" { #define SL_ICM40627_MASK_ACCEL_BW (0x39) -#define SL_ICM40627_ACCEL_BW_8000HZ (0x01) /**< Accel Bandwidth = 8 kHz */ +#define SL_ICM40627_ACCEL_BW_8000HZ (0x03) /**< Accel Bandwidth = 8 kHz */ #define SL_ICM40627_ACCEL_BW_200HZ (0x07) /**< Accel Bandwidth = 200 Hz */ #define SL_ICM40627_ACCEL_BW_50HZ (0x09) /**< Accel Bandwidth = 50 Hz */ #define SL_ICM40627_ACCEL_BW_25HZ (0x0A) /**< Accel Bandwidth = 25 Hz */ @@ -297,29 +297,29 @@ sl_status_t sl_si91x_icm40627_software_reset(sl_ssi_handle_t ssi_driver_handle); * @brief * Set the bandwidth of the gyroscope. * - * @param[in] gyroBw - * The desired bandwidth value. Use the ICM40627_GYRO_BW_xHZ macros, which + * @param[in] gyro_ODR + * The desired ODR value. Use the ICM40627_GYRO_BW_xHZ macros, which * are defined in the icm40627.h file. The value of x can be * 6, 12, 24, 51, 120, 150, 200, 360 or 12100. * * @return * Returns zero on OK, non-zero otherwise ******************************************************************************/ -sl_status_t sl_si91x_icm40627_set_gyro_bandwidth(sl_ssi_handle_t ssi_driver_handle, uint8_t gyroBw); +sl_status_t sl_si91x_icm40627_set_gyro_bandwidth(sl_ssi_handle_t ssi_driver_handle, uint8_t gyro_ODR); /***************************************************************************/ /** * @brief * Set the bandwidth of the accelerometer. * - * @param[in] accelBw - * The desired bandwidth value. Use the ICM40627_ACCEL_BW_yHZ macros, which + * @param[in] accel_ODR + * The desired ODR value. Use the ICM40627_ACCEL_BW_yHZ macros, which * are defined in the icm40627.h file. The value of y can be * 6, 12, 24, 50, 111, 246, 470 or 1210. * * @return * Returns zero on OK, non-zero otherwise ******************************************************************************/ -sl_status_t sl_si91x_icm40627_set_accel_bandwidth(sl_ssi_handle_t ssi_driver_handle, uint8_t accelBw); +sl_status_t sl_si91x_icm40627_set_accel_bandwidth(sl_ssi_handle_t ssi_driver_handle, uint8_t accel_ODR); /***************************************************************************/ /** * @brief diff --git a/components/device/silabs/si91x/mcu/drivers/hardware_drivers/icm40627/src/sl_si91x_icm40627.c b/components/device/silabs/si91x/mcu/drivers/hardware_drivers/icm40627/src/sl_si91x_icm40627.c index 51772be75..a1c0d7646 100644 --- a/components/device/silabs/si91x/mcu/drivers/hardware_drivers/icm40627/src/sl_si91x_icm40627.c +++ b/components/device/silabs/si91x/mcu/drivers/hardware_drivers/icm40627/src/sl_si91x_icm40627.c @@ -486,19 +486,19 @@ sl_status_t sl_si91x_icm40627_enable_sensor(sl_ssi_handle_t ssi_driver_handle, b /***************************************************************************/ /** * Sets the bandwidth of the gyroscope ******************************************************************************/ -sl_status_t sl_si91x_icm40627_set_gyro_bandwidth(sl_ssi_handle_t ssi_driver_handle, uint8_t gyroBw) +sl_status_t sl_si91x_icm40627_set_gyro_bandwidth(sl_ssi_handle_t ssi_driver_handle, uint8_t gyro_ODR) { uint32_t ssi_data_length = 2; uint8_t ssi_data[ssi_data_length]; uint8_t temp; /* Read the GYRO_CONFIG_1 register */ - icm40627_read_register(ssi_driver_handle, SL_ICM40627_REG_GYRO_ACCEL_CONFIG0, ssi_data, ssi_data_length); + icm40627_read_register(ssi_driver_handle, SL_ICM40627_REG_GYRO_CONFIG0, ssi_data, ssi_data_length); /* Write the new bandwidth value to the gyro config register */ - temp = gyroBw | ssi_data[ssi_data_length - 1]; + temp = gyro_ODR | ssi_data[ssi_data_length - 1]; - icm40627_write_register(ssi_driver_handle, SL_ICM40627_REG_GYRO_ACCEL_CONFIG0, &temp, ssi_data_length - 1); + icm40627_write_register(ssi_driver_handle, SL_ICM40627_REG_GYRO_CONFIG0, &temp, ssi_data_length - 1); return SL_STATUS_OK; } @@ -506,19 +506,19 @@ sl_status_t sl_si91x_icm40627_set_gyro_bandwidth(sl_ssi_handle_t ssi_driver_hand /***************************************************************************/ /** * Sets the bandwidth of the accelerometer ******************************************************************************/ -sl_status_t sl_si91x_icm40627_set_accel_bandwidth(sl_ssi_handle_t ssi_driver_handle, uint8_t accelBw) +sl_status_t sl_si91x_icm40627_set_accel_bandwidth(sl_ssi_handle_t ssi_driver_handle, uint8_t accel_ODR) { uint32_t ssi_data_length = 2; uint8_t ssi_data[ssi_data_length]; uint8_t temp; /* Read the GYRO_CONFIG_1 register */ - icm40627_read_register(ssi_driver_handle, SL_ICM40627_REG_GYRO_ACCEL_CONFIG0, ssi_data, ssi_data_length); + icm40627_read_register(ssi_driver_handle, SL_ICM40627_REG_ACCEL_CONFIG0, ssi_data, ssi_data_length); /* Write the new bandwidth value to the accel config register */ - temp = accelBw | ssi_data[ssi_data_length - 1]; + temp = accel_ODR | ssi_data[ssi_data_length - 1]; - icm40627_write_register(ssi_driver_handle, SL_ICM40627_REG_GYRO_ACCEL_CONFIG0, &temp, ssi_data_length - 1); + icm40627_write_register(ssi_driver_handle, SL_ICM40627_REG_ACCEL_CONFIG0, &temp, ssi_data_length - 1); return SL_STATUS_OK; } diff --git a/components/device/silabs/si91x/mcu/drivers/hardware_drivers/led/component/sl_si91x_led_917.slcc b/components/device/silabs/si91x/mcu/drivers/hardware_drivers/led/component/sl_si91x_led_917.slcc index 188a7ce9f..aeb5a51bf 100644 --- a/components/device/silabs/si91x/mcu/drivers/hardware_drivers/led/component/sl_si91x_led_917.slcc +++ b/components/device/silabs/si91x/mcu/drivers/hardware_drivers/led/component/sl_si91x_led_917.slcc @@ -21,7 +21,7 @@ include: source: - path: src/sl_si91x_led.c requires: - - name: rsilib_egpio + - name: sl_gpio provides: - name: sl_si91x_led_917 template_file: diff --git a/components/device/silabs/si91x/mcu/drivers/hardware_drivers/led/config/sl_si91x_led_config.h b/components/device/silabs/si91x/mcu/drivers/hardware_drivers/led/config/sl_si91x_led_config.h index d4cd8f3b0..8f1427463 100644 --- a/components/device/silabs/si91x/mcu/drivers/hardware_drivers/led/config/sl_si91x_led_config.h +++ b/components/device/silabs/si91x/mcu/drivers/hardware_drivers/led/config/sl_si91x_led_config.h @@ -13,6 +13,8 @@ #define SL_SI91x_LED_COUNT 2 +#ifndef SI917_DEVKIT + #define SL_LED_LED0_PIN RTE_LED0_PIN #define SL_LED_LED0_PORT RTE_LED0_PORT #define SL_LED_LED0_NUMBER RTE_LED0_NUMBER @@ -22,4 +24,13 @@ #define SL_LED_LED1_NUMBER RTE_LED1_NUMBER #define SL_LED_LED1_PAD RTE_LED1_PAD +#else + +#define SL_LED_LEDB_PIN RTE_LEDB_PIN +#define SL_LED_LEDB_PORT RTE_LEDB_PORT +#define SL_LED_LEDB_NUMBER RTE_LEDB_NUMBER +#define SL_LED_LEDB_PAD RTE_LEDB_PAD + +#endif + #endif // SL_SI91X_LED_CONFIG_H diff --git a/components/device/silabs/si91x/mcu/drivers/hardware_drivers/led/inc/sl_si91x_led.h b/components/device/silabs/si91x/mcu/drivers/hardware_drivers/led/inc/sl_si91x_led.h index 27f273756..fd89fbada 100644 --- a/components/device/silabs/si91x/mcu/drivers/hardware_drivers/led/inc/sl_si91x_led.h +++ b/components/device/silabs/si91x/mcu/drivers/hardware_drivers/led/inc/sl_si91x_led.h @@ -49,7 +49,7 @@ void sl_si91x_led_init(const sl_led_t *handle); * Atomically wraps an XOR or a similar operation for a * single GPIO pin connected to an LED to toggle the LED. * - * @param[in] pin LED pin for the LED to be toggled. + * @param[in] pin GPIO pin connected to the LED to be toggled. * * @return none * @@ -59,7 +59,7 @@ void sl_si91x_led_toggle(uint8_t pin); /***************************************************************************/ /** * Sets a GPIO pin connected to an LED to turn the LED on. * - * @param[in] pin LED pin for the LED to turn on. + * @param[in] pin GPIO pin connected to the LED to be set. * * @return none * @@ -69,7 +69,7 @@ void sl_si91x_led_set(uint8_t pin); /***************************************************************************/ /** * Clears a GPIO pin connected to an LED to turn the LED off. * - * @param[in] pin LED pin for the LED to turn off. + * @param[in] pin GPIO pin connected to the LED to be cleared. * * @return none * diff --git a/components/device/silabs/si91x/mcu/drivers/hardware_drivers/led/src/sl_si91x_led.c b/components/device/silabs/si91x/mcu/drivers/hardware_drivers/led/src/sl_si91x_led.c index c6e7b451a..fd5ac2559 100644 --- a/components/device/silabs/si91x/mcu/drivers/hardware_drivers/led/src/sl_si91x_led.c +++ b/components/device/silabs/si91x/mcu/drivers/hardware_drivers/led/src/sl_si91x_led.c @@ -16,80 +16,73 @@ ******************************************************************************/ #include "sl_si91x_led.h" #include "si91x_device.h" -#include "rsi_rom_egpio.h" +#include "sl_driver_gpio.h" +#include "sl_si91x_driver_gpio.h" void sl_si91x_led_init(const sl_led_t *handle) { -#if ((defined(SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER)) && (defined(SLI_SI91X_MCU_CONFIG_RADIO_BOARD_VER2))) +#ifndef SI917_DEVKIT if (handle->led_number == 0U) { - /*Set the GPIO pin MUX */ - RSI_EGPIO_SetPinMux(EGPIO1, handle->port, handle->pin, 0); - /*Set GPIO direction*/ - RSI_EGPIO_SetDir(EGPIO1, handle->port, handle->pin, 0); + /*Enable clock*/ + sl_si91x_gpio_driver_enable_clock((sl_si91x_gpio_select_clock_t)ULPCLK_GPIO); } else { - RSI_EGPIO_PadSelectionEnable(5); - /*Set the GPIO pin MUX */ - RSI_EGPIO_SetPinMux(EGPIO, handle->port, handle->pin, 0); - /*Set GPIO direction*/ - RSI_EGPIO_SetDir(EGPIO, handle->port, handle->pin, 0); - } -#elif SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER - if (handle->led_number == 0U) { - RSI_EGPIO_PadSelectionEnable(5); - /*Set the GPIO pin MUX */ - RSI_EGPIO_SetPinMux(EGPIO, handle->port, handle->pin, 0); - /*Set GPIO direction*/ - RSI_EGPIO_SetDir(EGPIO, handle->port, handle->pin, 0); - } else { - /*Set the GPIO pin MUX */ - RSI_EGPIO_SetPinMux(EGPIO1, handle->port, handle->pin, 0); - /*Set GPIO direction*/ - RSI_EGPIO_SetDir(EGPIO1, handle->port, handle->pin, 0); + /*Enable clock*/ + sl_si91x_gpio_driver_enable_clock((sl_si91x_gpio_select_clock_t)M4CLK_GPIO); } +#else + /*Enable clock*/ + sl_si91x_gpio_driver_enable_clock((sl_si91x_gpio_select_clock_t)M4CLK_GPIO); #endif + sl_si91x_gpio_pin_config_t sl_gpio_pin_config = { { handle->port, handle->pin }, GPIO_OUTPUT }; + sl_gpio_set_configuration(sl_gpio_pin_config); } void sl_si91x_led_set(uint8_t pin) { -#if ((SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER) && (SLI_SI91X_MCU_CONFIG_RADIO_BOARD_VER2)) - if (pin == SL_LED_LED0_PIN) - RSI_EGPIO_SetPin(EGPIO1, SL_LED_LED0_PORT, pin, 1); - else - RSI_EGPIO_SetPin(EGPIO, SL_LED_LED1_PORT, pin, 1); -#elif SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER - if (pin == SL_LED_LED0_PIN) - RSI_EGPIO_SetPin(EGPIO, SL_LED_LED0_PORT, pin, 1); - else - RSI_EGPIO_SetPin(EGPIO1, SL_LED_LED1_PORT, pin, 1); + sl_gpio_t led_gpio_port_pin; + led_gpio_port_pin.pin = pin; +#ifndef SI917_DEVKIT + if (pin == SL_LED_LED0_PIN) { + led_gpio_port_pin.port = SL_LED_LED0_PORT; + } else { + led_gpio_port_pin.port = SL_LED_LED1_PORT; + } + sl_gpio_driver_set_pin(&led_gpio_port_pin); +#else + led_gpio_port_pin.port = SL_LED_LEDB_PORT; + sl_gpio_driver_clear_pin(&led_gpio_port_pin); #endif } void sl_si91x_led_clear(uint8_t pin) { -#if ((SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER) && (SLI_SI91X_MCU_CONFIG_RADIO_BOARD_VER2)) - if (pin == SL_LED_LED0_PIN) - RSI_EGPIO_SetPin(EGPIO1, SL_LED_LED0_PORT, pin, 0); - else - RSI_EGPIO_SetPin(EGPIO, SL_LED_LED1_PORT, pin, 0); -#elif SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER - if (pin == SL_LED_LED0_PIN) - RSI_EGPIO_SetPin(EGPIO, SL_LED_LED0_PORT, pin, 0); - else - RSI_EGPIO_SetPin(EGPIO1, SL_LED_LED1_PORT, pin, 0); + sl_gpio_t led_gpio_port_pin; + led_gpio_port_pin.pin = pin; +#ifndef SI917_DEVKIT + if (pin == SL_LED_LED0_PIN) { + led_gpio_port_pin.port = SL_LED_LED0_PORT; + } else { + led_gpio_port_pin.port = SL_LED_LED1_PORT; + } + sl_gpio_driver_clear_pin(&led_gpio_port_pin); +#else + led_gpio_port_pin.port = SL_LED_LEDB_PORT; + sl_gpio_driver_set_pin(&led_gpio_port_pin); #endif } void sl_si91x_led_toggle(uint8_t pin) { -#if ((SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER) && (SLI_SI91X_MCU_CONFIG_RADIO_BOARD_VER2)) - if (pin == SL_LED_LED0_PIN) - RSI_EGPIO_TogglePort(EGPIO1, SL_LED_LED0_PORT, (1 << pin)); - else - RSI_EGPIO_TogglePort(EGPIO, SL_LED_LED1_PORT, (1 << pin)); -#elif SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER - if (pin == SL_LED_LED0_PIN) - RSI_EGPIO_TogglePort(EGPIO, SL_LED_LED0_PORT, (1 << pin)); - else - RSI_EGPIO_TogglePort(EGPIO1, SL_LED_LED1_PORT, (1 << pin)); + sl_gpio_t led_gpio_port_pin; + led_gpio_port_pin.pin = pin; +#ifndef SI917_DEVKIT + if (pin == SL_LED_LED0_PIN) { + led_gpio_port_pin.port = SL_LED_LED0_PORT; + } else { + led_gpio_port_pin.port = SL_LED_LED1_PORT; + } +#else + led_gpio_port_pin.port = SL_LED_LEDB_PORT; #endif + sl_gpio_driver_toggle_pin(&led_gpio_port_pin); } diff --git a/components/device/silabs/si91x/mcu/drivers/hardware_drivers/memlcd/src/memlcd_917/sl_memlcd_spi.c b/components/device/silabs/si91x/mcu/drivers/hardware_drivers/memlcd/src/memlcd_917/sl_memlcd_spi.c index 829c97bf0..d2d50cfd7 100644 --- a/components/device/silabs/si91x/mcu/drivers/hardware_drivers/memlcd/src/memlcd_917/sl_memlcd_spi.c +++ b/components/device/silabs/si91x/mcu/drivers/hardware_drivers/memlcd/src/memlcd_917/sl_memlcd_spi.c @@ -50,6 +50,8 @@ int32_t status_spi = 0; */ void mySPI_callback_spi(uint32_t event) { + // Clearing the instance number to evaluate the event + event &= SSI_INSTANCE_MASK; switch (event) { case ARM_SPI_EVENT_TRANSFER_COMPLETE: spi_done_ok = 1; diff --git a/components/device/silabs/si91x/mcu/drivers/hardware_drivers/memlcd/src/sl_memlcd.c b/components/device/silabs/si91x/mcu/drivers/hardware_drivers/memlcd/src/sl_memlcd.c index 4f19f13c4..1ad80eb71 100644 --- a/components/device/silabs/si91x/mcu/drivers/hardware_drivers/memlcd/src/sl_memlcd.c +++ b/components/device/silabs/si91x/mcu/drivers/hardware_drivers/memlcd/src/sl_memlcd.c @@ -40,14 +40,14 @@ *************************** DEFINES / MACROS ******************************** ******************************************************************************/ -#define SL_MEMLCD_SPI_CS_PORT 0 -#define SL_MEMLCD_SPI_CS_PIN 10 +#define SL_MEMLCD_SPI_CS_PORT RTE_MEMLCD_CS_PORT +#define SL_MEMLCD_SPI_CS_PIN RTE_MEMLCD_CS_PIN -#define SL_MEMLCD_EXTCOMIN_PIN 3 -#define SL_MEMLCD_EXTCOMIN_PORT 0 +#define SL_MEMLCD_EXTCOMIN_PIN RTE_MEMLCD_EXTCOMIN_PIN +#define SL_MEMLCD_EXTCOMIN_PORT RTE_MEMLCD_EXTCOMIN_PORT -#define SL_BOARD_ENABLE_DISPLAY_PIN 0 -#define SL_BOARD_ENABLE_DISPLAY_PORT 0 +#define SL_BOARD_ENABLE_DISPLAY_PIN RTE_MEMLCD_ENABLE_DISPLAY_PIN +#define SL_BOARD_ENABLE_DISPLAY_PORT RTE_MEMLCD_ENABLE_DISPLAY_PORT #define CMD_UPDATE 0x01 #define CMD_ALL_CLEAR 0x04 @@ -312,7 +312,6 @@ sl_status_t sl_memlcd_post_wakeup_init(void) if (status != SL_STATUS_OK) { return SL_STATUS_FAIL; } - return SL_STATUS_OK; } diff --git a/components/device/silabs/si91x/mcu/drivers/hardware_drivers/memlcd/src/sl_memlcd_display.c b/components/device/silabs/si91x/mcu/drivers/hardware_drivers/memlcd/src/sl_memlcd_display.c index 2b77bf86d..5a84a8125 100644 --- a/components/device/silabs/si91x/mcu/drivers/hardware_drivers/memlcd/src/sl_memlcd_display.c +++ b/components/device/silabs/si91x/mcu/drivers/hardware_drivers/memlcd/src/sl_memlcd_display.c @@ -33,6 +33,9 @@ sl_status_t sl_memlcd_init(void) { +#ifdef SI917_DEVKIT + return SL_STATUS_NOT_SUPPORTED; +#else sl_memlcd_t memlcd = { .width = SL_MEMLCD_DISPLAY_WIDTH, .height = SL_MEMLCD_DISPLAY_HEIGHT, @@ -46,4 +49,5 @@ sl_status_t sl_memlcd_init(void) }; return sl_memlcd_configure(&memlcd); +#endif } \ No newline at end of file diff --git a/components/device/silabs/si91x/mcu/drivers/hardware_drivers/rgb_led/config/sl_si91x_rgb_led_config.h b/components/device/silabs/si91x/mcu/drivers/hardware_drivers/rgb_led/config/sl_si91x_rgb_led_config.h index 37b3edba9..c334057d4 100644 --- a/components/device/silabs/si91x/mcu/drivers/hardware_drivers/rgb_led/config/sl_si91x_rgb_led_config.h +++ b/components/device/silabs/si91x/mcu/drivers/hardware_drivers/rgb_led/config/sl_si91x_rgb_led_config.h @@ -13,19 +13,19 @@ #define SL_SI91x_LED_COUNT 2 -#define SL_LED_RED_PIN RTE_LED0_PIN -#define SL_LED_RED_PORT RTE_LED0_PORT -#define SL_LED_RED_NUMBER RTE_LED0_NUMBER -#define SL_LED_RED_PAD RTE_LED0_PAD +#define SL_LED_RED_PIN RTE_LEDR_PIN +#define SL_LED_RED_PORT RTE_LEDR_PORT +#define SL_LED_RED_NUMBER RTE_LEDR_NUMBER +#define SL_LED_RED_PAD RTE_LEDR_PAD -#define SL_LED_GREEN_PIN RTE_LED1_PIN -#define SL_LED_GREEN_PORT RTE_LED1_PORT -#define SL_LED_GREEN_NUMBER RTE_LED1_NUMBER -#define SL_LED_GREEN_PAD RTE_LED1_PAD +#define SL_LED_GREEN_PIN RTE_LEDG_PIN +#define SL_LED_GREEN_PORT RTE_LEDG_PORT +#define SL_LED_GREEN_NUMBER RTE_LEDG_NUMBER +#define SL_LED_GREEN_PAD RTE_LEDG_PAD -#define SL_LED_BLUE_PIN RTE_LED2_PIN -#define SL_LED_BLUE_PORT RTE_LED2_PORT -#define SL_LED_BLUE_NUMBER RTE_LED2_NUMBER -#define SL_LED_BLUE_PAD RTE_LED2_PAD +#define SL_LED_BLUE_PIN RTE_LEDB_PIN +#define SL_LED_BLUE_PORT RTE_LEDB_PORT +#define SL_LED_BLUE_NUMBER RTE_LEDB_NUMBER +#define SL_LED_BLUE_PAD RTE_LEDB_PAD #endif // SL_SI91X_LED_CONFIG_H diff --git a/components/device/silabs/si91x/mcu/drivers/hardware_drivers/veml6035/src/sl_si91x_veml6035.c b/components/device/silabs/si91x/mcu/drivers/hardware_drivers/veml6035/src/sl_si91x_veml6035.c index cec712611..e677a7630 100644 --- a/components/device/silabs/si91x/mcu/drivers/hardware_drivers/veml6035/src/sl_si91x_veml6035.c +++ b/components/device/silabs/si91x/mcu/drivers/hardware_drivers/veml6035/src/sl_si91x_veml6035.c @@ -32,6 +32,14 @@ #include "sl_si91x_i2c.h" /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/******************************************************************************* + *************************** Defines / Macros ******************************** + ******************************************************************************/ +#define SENSITIVITY_LOW 1 +#define SENSITIVITY_HIGH 0 +#define GAIN_NORMAL 1 +#define GAIN_DOUBLE 2 +#define GAIN_QUADRULPLE 4 /***************************************************************************/ /** * Local prototypes ******************************************************************************/ @@ -61,17 +69,22 @@ sl_status_t sl_si91x_veml6035_init(sl_i2c_instance_t i2c_instance, uint8_t addr, // Do not access sensor too early following power-up sl_sleeptimer_delay_millisecond(10); + // Reset the sensor status = sl_si91x_veml6035_reset(i2c_instance, addr); if (status != SL_STATUS_OK) { return status; } // Configure to lowest sensitivity (highest range) - status = sl_si91x_veml6035_configure_sensitivity(i2c_instance, addr, true, 1); + status = sl_si91x_veml6035_configure_sensitivity(i2c_instance, addr, SENSITIVITY_LOW, GAIN_NORMAL); if (status != SL_STATUS_OK) { return status; } + // Configure the integration time + sl_si91x_veml6035_configure_integration_time(i2c_instance, addr, SL_VEML6035_ALS_IT_100MS); + + // Enable white channel if required if (white_enable) { status = veml6035_write_register_field(i2c_instance, addr, @@ -83,6 +96,7 @@ sl_status_t sl_si91x_veml6035_init(sl_i2c_instance_t i2c_instance, uint8_t addr, } } + // Enable sensor status = sl_si91x_veml6035_enable_sensor(i2c_instance, addr, true); return status; @@ -499,6 +513,9 @@ static sl_status_t veml6035_read_register(sl_i2c_instance_t i2c_instance, uint8_ uint8_t i2c_write_data[write_buffer_size]; uint8_t i2c_read_data[read_buffer_size]; + // Enable repeated start for data transfer + sl_i2c_driver_enable_repeated_start(i2c_instance, true); + // Validate invalid parameters if ((i2c_instance >= SL_I2C_LAST) || (reg >= SL_VEML6035_IF)) { return SL_STATUS_INVALID_PARAMETER; @@ -514,7 +531,10 @@ static sl_status_t veml6035_read_register(sl_i2c_instance_t i2c_instance, uint8_ if (status != SL_STATUS_OK) { return status; } - wait_till_i2c_gets_idle(I2C_BASE); + + // Disable repeated start for the cycle + sl_i2c_driver_enable_repeated_start(i2c_instance, false); + // Receive response for user register 1/ heater control register command from sensor status = sl_i2c_driver_receive_data_blocking(i2c_instance, addr, i2c_read_data, read_buffer_size); if (status != SL_STATUS_OK) { diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/component/rsilib_dcache.slcc b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/component/rsilib_dcache.slcc new file mode 100644 index 000000000..0ed94a5f7 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/component/rsilib_dcache.slcc @@ -0,0 +1,19 @@ +id: rsilib_dcache +label: D_CACHE +package: platform +description: > + DCACHE API's +category: Device|Si91x|MCU|Internal|RSI Peripheral Drivers +quality: production +component_root_path: "components/device/silabs/si91x/mcu/drivers/peripheral_drivers" +source: + - path: "src/rsi_d_cache.c" +include: + - path: "inc" + file_list: + - path: "rsi_d_cache.h" +provides: + - name: rsilib_dcache +template_contribution: + - name: psram_dcache + value: true \ No newline at end of file diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/component/sllib_m4_power_save.slcc b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/component/sllib_m4_power_save.slcc index c392bc404..22a86a69f 100644 --- a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/component/sllib_m4_power_save.slcc +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/component/sllib_m4_power_save.slcc @@ -12,15 +12,6 @@ include: - path: "inc" file_list: - path: "sl_si91x_m4_ps.h" -template_contribution: -- name: event_handler - condition: - - sli_si91x_mcu_interface - value: - event: platform_init - include: rsi_wisemcu_hardware_setup.h - handler: sl_si91x_hardware_setup - priority: -9995 provides: - name: sllib_m4_power_save requires: diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_crc.h b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_crc.h index 773e20670..bcc2ea124 100644 --- a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_crc.h +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_crc.h @@ -35,17 +35,17 @@ extern "C" { typedef struct { uint32_t crc; //Calculated CRC Value uint32_t polynomial; //Polynomial Value for CRC Calculation - uint32_t + unsigned int polyWidth : 5; //Number of bits/width of the polynomial has to be written here for the computation of final CRC uint32_t lfsrVal; //lfsr Initialization value for CRC Calculation - uint32_t widthType : 3; //Data Width taken Variable. - //When width_type - 0 :Take the data width from either reg programmed or from cnt - //width_type -1 :Take the data width from Reg. - //width_type-2 : Take the data width from CNT. - uint32_t dinWidth : 5; //Valid number of bits in the input data in din_width_from_reg set mode - uint32_t numBytes; //Input data number of bytes - uint32_t aempty : 4; //Almost empty Threshold value. Max value is 15 - uint32_t afull : 4; //Almost Full Threshold value. Max value is 15 + unsigned int widthType : 3; //Data Width taken Variable. + //When width_type - 0 :Take the data width from either reg programmed or from cnt + //width_type -1 :Take the data width from Reg. + //width_type-2 : Take the data width from CNT. + unsigned int dinWidth : 5; //Valid number of bits in the input data in din_width_from_reg set mode + uint32_t numBytes; //Input data number of bytes + unsigned int aempty : 4; //Almost empty Threshold value. Max value is 15 + unsigned int afull : 4; //Almost Full Threshold value. Max value is 15 uint32_t InputData; uint32_t swapLfsr; uint32_t swapDin; diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_ct.h b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_ct.h index 35d55f344..44e5bd411 100644 --- a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_ct.h +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_ct.h @@ -169,11 +169,11 @@ typedef CT_MUX_REG_Type RSI_CT_MUX_REG_T; ============================================================================**/ typedef struct { - uint32_t NoOfInputs : 3; /*!< Number of Input signals */ - uint32_t NoOfOutputs : 4; /*!< Number of Output signlas */ - uint32_t NumOfCounters : 4; /*!< Number of Counters present in CT module */ - uint32_t NoOfEvents : 6; /*!< Number of Events can be generated by input events */ - uint32_t DMAIntf : 1; /*!< Supports DMA interface or not */ + unsigned int NoOfInputs : 3; /*!< Number of Input signals */ + unsigned int NoOfOutputs : 4; /*!< Number of Output signlas */ + unsigned int NumOfCounters : 4; /*!< Number of Counters present in CT module */ + unsigned int NoOfEvents : 6; /*!< Number of Events can be generated by input events */ + unsigned int DMAIntf : 1; /*!< Supports DMA interface or not */ } RSI_CT_CAPABILITIES_T; /****** CT Events ******/ #define CT_EVT_0 1 @@ -791,7 +791,7 @@ STATIC INLINE void RSI_CT_OCUConfigSet(RSI_CT_T *pCT, uint32_t value) STATIC INLINE void RSI_CT_OCUConfigReset(RSI_CT_T *pCT, uint32_t value) { // OCU control parameters - pCT->CT_OCU_CTRL_REG &= ~(value); + pCT->CT_OCU_CTRL_REG &= ~value; } /*===================================================*/ @@ -859,25 +859,25 @@ STATIC INLINE void RSI_CT_InterruptClear(RSI_CT_T *pCT, uint32_t clrFlags) /*===================================================*/ /** - * @fn uint32_t RSI_CT_GetInterruptStatus(RSI_CT_T *pCT) + * @fn uint32_t RSI_CT_GetInterruptStatus(const RSI_CT_T *pCT) * @brief Clear the specified interrupt flag in State Configurable Timer * @param[in] pCT : Pointer to the CT instance register area * @return CT Interrupt status value */ -STATIC INLINE uint32_t RSI_CT_GetInterruptStatus(RSI_CT_T *pCT) +STATIC INLINE uint32_t RSI_CT_GetInterruptStatus(const RSI_CT_T *pCT) { return (pCT->CT_INTR_STS); } /*===================================================*/ /** - * @fn void RSI_CT_EdgeLevelEventControl(RSI_CT_T *pCT,uint32_t value) + * @fn void RSI_CT_EdgeLevelEventControl(const RSI_CT_T *pCT,uint32_t value) * @brief This API is used to control the input event generation to CT * @param[in] pSCT : Pointer to the SCT instance register area * @param[in] value : Mask value * @return none */ -STATIC INLINE void RSI_CT_EdgeLevelEventControl(RSI_CT_T *pCT, uint32_t value) +STATIC INLINE void RSI_CT_EdgeLevelEventControl(const RSI_CT_T *pCT, uint32_t value) { //pCT ->RE_FE_RFE_LEV0_LEV1_EVENT_ENABLE_REG = value; (void)pCT; @@ -1000,13 +1000,13 @@ STATIC INLINE void RSI_CT_SetMatchCount(RSI_CT_T *pCT, uint32_t value, boolean_t /*===================================================*/ /** - * @fn uint16_t RSI_CT_CaptureRead(RSI_CT_T *pCT, boolean_t counterNum) + * @fn uint16_t RSI_CT_CaptureRead(const RSI_CT_T *pCT, boolean_t counterNum) * @brief Gets the captured counter value * @param[in] pCT : Pointer to the CT instance register area * @param[in] counterNum : Counter 0/1 * @return Return counter value at the time of capture event occurs */ -STATIC INLINE uint16_t RSI_CT_CaptureRead(RSI_CT_T *pCT, boolean_t counterNum) +STATIC INLINE uint16_t RSI_CT_CaptureRead(const RSI_CT_T *pCT, boolean_t counterNum) { if (counterNum) { return (pCT->CT_CAPTURE_REG_b.COUNTER_1_CAPTURE); @@ -1017,14 +1017,14 @@ STATIC INLINE uint16_t RSI_CT_CaptureRead(RSI_CT_T *pCT, boolean_t counterNum) /*===================================================*/ /** - * @fn uint32_t RSI_CT_GetCounter( RSI_CT_T *pCT,boolean_t counterNum,boolean_t mode ) + * @fn uint32_t RSI_CT_GetCounter(const RSI_CT_T *pCT,boolean_t counterNum,boolean_t mode ) * @brief Gets the captured counter value * @param[in] pCT : Pointer to the CT instance register area * @param[in] counterNum : Counter 0/1 * @param[in] mode : mode 0/1 * @return Return the counter value */ -STATIC INLINE uint32_t RSI_CT_GetCounter(RSI_CT_T *pCT, boolean_t counterNum, boolean_t mode) +STATIC INLINE uint32_t RSI_CT_GetCounter(const RSI_CT_T *pCT, boolean_t counterNum, boolean_t mode) { if (mode) { return (pCT->CT_COUNTER_REG); diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_d_cache.h b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_d_cache.h new file mode 100644 index 000000000..6ea682624 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_d_cache.h @@ -0,0 +1,139 @@ +/******************************************************************************* +* @file rsi_d_cache.h +* @brief +******************************************************************************* +* # License +* Copyright 2024 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +// Includes files + +#include "stdint.h" + +#ifndef RSI_D_CACHE_H +#define RSI_D_CACHE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + *************************** Defines / Macros ******************************** + ******************************************************************************/ + +#define DCACHE_LINE_SIZE 32 // Cache line size + +#define M4SS_DCACHE_BASE_ADDR (0x44040000) // Memory address of the Data Cache registers + +#define DCACHE_CTRL_ENABLE (0X1) // Enables the data cache +#define DCACHE_CTRL_FORCE_WT (0x2) // Sets the data cache to write-through mode + +#define DCACHE_MAINT_STATUS_CACHE_ENABLED (0x1) // Indicates if the data cache is enabled +#define DCACHE_MAINT_STATUS_ONGOING_EN_DIS (0x2) // Indicates if a cache enable/disable operation is ongoing +#define DCACHE_MAINT_STATUS_ONGOING_MAINT (0x4) // Indicates if a cache maintenance operation is ongoing +#define DCACHE_MAINT_STATUS_ONGOING_PWR_MAINT \ + (0x8) // Indicates if a power-related cache maintenance operation is ongoing +#define DCACHE_MAINT_STATUS_CACHE_IS_CLEAN (0x100) // Indicates if all data in the cache is consistent with memory + +#define DCACHE_MAINT_CTRL_ALL_TRIG_CLEAN (0x1) // Initiates a clean operation for all cache lines +#define DCACHE_MAINT_CTRL_ALL_TRIG_INVALIDATE (0x2) // Initiates an invalidate operation for all cache lines + +#define DCACHE_SECIRQSCLR_CLEAR_ALL (0xFF) // Clears all pending data cache secure interrupts + +#define DCACHE_SECSTATCTRL_ENABLE_COUNTER (0x1) // Enables the data cache statistics counter +#define DCACHE_SECSTATCTRL_RESET_COUNTER (0x2) // Resets the data cache statistics counter to zero +#define DCACHE_SECIRQSTAT_NSECURE_CNT_SAT \ + (0x40) // Indicates if the data cache statistics counters are saturated (reached maximum value) + +#define DCACHE_MAINT_CTRL_LINES_TRIG_CLEAN (0x0) // Initiates a clean operation for a specific cache line +#define DCACHE_MAINT_CTRL_LINES_TRIG_INVALIDATE (0x1) // Initiates a invalidate operation for a specific cache line +#define DCACHE_MAINT_CTRL_LINES_LOWER_ADDRESS_MASK \ + (0x1F) // Mask to isolate the address of the cache line in a maintenance control register + +/******************************************************************************* + ****************************** Structure ******************************** + ******************************************************************************/ + +typedef struct { + volatile uint32_t HWPRMS; + volatile uint32_t RESV_1[3]; + volatile uint32_t CTRL; + volatile uint32_t NSEC_ACCESS; + volatile uint32_t RESV_2[2]; + volatile uint32_t MAINT_CTRL_ALL; + volatile uint32_t MAINT_CTRL_LINES; + volatile uint32_t MAINT_STATUS; + volatile uint32_t RESV_3[53]; + volatile uint32_t SECIRQSTAT; + volatile uint32_t SECIRQSCLR; + volatile uint32_t SECIRQEN; + volatile uint32_t SECIRQINFO1; + volatile uint32_t SECIRQINFO2; + volatile uint32_t RESV_4[11]; + volatile uint32_t NSECIRQSTAT; + volatile uint32_t NSECIRQSCLR; + volatile uint32_t NSECIRQEN; + volatile uint32_t NSECIRQINFO1; + volatile uint32_t NSECIRQINFO2; + volatile uint32_t RESV_5[107]; + volatile uint32_t SECHIT; + volatile uint32_t SECMISS; + volatile uint32_t SECSTATCTRL; + volatile uint32_t DUMMY; + volatile uint32_t NSECHIT; + volatile uint32_t NSECMISS; + volatile uint32_t NSECSTATCTRL; + volatile uint32_t RESV_6[185]; + volatile uint32_t PMSVR0; + volatile uint32_t PMSVR1; + volatile uint32_t PMSVR2; + volatile uint32_t PMSVR3; + volatile uint32_t RESV_7[28]; + volatile uint32_t PMSSSR; + volatile uint32_t RESV_8[27]; + volatile uint32_t PMSSCR; + volatile uint32_t PMSSRR; + volatile uint32_t RESV_9[566]; + volatile uint32_t PIDR4; + volatile uint32_t PIDR5; + volatile uint32_t PIDR6; + volatile uint32_t PIDR7; + volatile uint32_t PIDR0; + volatile uint32_t PIDR1; + volatile uint32_t PIDR2; + volatile uint32_t PIDR3; + volatile uint32_t CIDR0; + volatile uint32_t CIDR1; + volatile uint32_t CIDR2; + volatile uint32_t CIDR3; +} DCache_Reg_Type; + +/******************************************************************************* + ****************************** Prototypes ******************************** + ******************************************************************************/ + +void rsi_d_cache_enable(void); +void rsi_d_cache_disable(void); +void rsi_d_cache_invalidate_all(void); +void rsi_d_cache_clean_up_all(void); +void rsi_d_cache_invalidate_address(uint32_t address); +void rsi_d_cache_clean_up_address(uint32_t address); +void rsi_d_cache_disable_stats(void); +void rsi_d_cache_enable_stats(void); +void rsi_d_cache_clear_stats(void); +int rsi_d_cache_get_stats(int *hit_count, int *miss_count); + +#ifdef __cplusplus +} +#endif + +#endif //RSI_D_CACHE_H diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_egpio.h b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_egpio.h index 47dad87e1..7647ecc28 100644 --- a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_egpio.h +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_egpio.h @@ -175,9 +175,9 @@ void egpio_set_dir(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, boolean_t dir) void egpio_set_pin(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, uint8_t val); -boolean_t egpio_get_pin(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); +boolean_t egpio_get_pin(const EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); -boolean_t egpio_get_dir(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); +boolean_t egpio_get_dir(const EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); void egpio_pin_int_sel(EGPIO_Type *pEGPIO, uint8_t intCh, uint8_t port, uint8_t pin); @@ -201,7 +201,7 @@ void egpio_set_int_high_level_enable(EGPIO_Type *pEGPIO, uint8_t intCh); void egpio_set_int_high_level_disable(EGPIO_Type *pEGPIO, uint8_t intCh); -uint8_t egpio_get_int_stat(EGPIO_Type *pEGPIO, uint8_t intCh); +uint8_t egpio_get_int_stat(const EGPIO_Type *pEGPIO, uint8_t intCh); void egpio_int_clr(EGPIO_Type *pEGPIO, uint8_t intCh, uint8_t flags); @@ -225,7 +225,7 @@ void egpio_clr_port(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val); void egpio_toggle_port(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val); -uint16_t egpio_get_port(EGPIO_Type *pEGPIO, uint8_t port); +uint16_t egpio_get_port(const EGPIO_Type *pEGPIO, uint8_t port); void egpio_group_int_one_enable(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); @@ -249,7 +249,7 @@ void egpio_group_int_and(EGPIO_Type *pEGPIO, uint8_t grpInt); void egpio_group_int_or(EGPIO_Type *pEGPIO, uint8_t grpInt); -uint32_t egpio_group_int_stat(EGPIO_Type *pEGPIO, uint8_t grpInt); +uint32_t egpio_group_int_stat(const EGPIO_Type *pEGPIO, uint8_t grpInt); void egpio_group_int_wkeup_Enable(EGPIO_Type *pEGPIO, uint8_t grpInt); diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_gpdma.h b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_gpdma.h index 2f2df2a37..b851d7134 100644 --- a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_gpdma.h +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_gpdma.h @@ -322,10 +322,10 @@ typedef GPDMA_C_Type RSI_GPDMAC_T; // brief GPDMA Driver Capabilities. typedef struct { - uint32_t noOfChannels : 4; // Total supporting channels - uint32_t noOfMasterInterfaces : 2; // No of master interfaces supported - uint32_t noOfPeriSupport : 7; // total supporting peripherals - uint32_t noOfPriorityLevels : 3; // No of priority levels + unsigned int noOfChannels : 4; // Total supporting channels + unsigned int noOfMasterInterfaces : 2; // No of master interfaces supported + unsigned int noOfPeriSupport : 7; // total supporting peripherals + unsigned int noOfPriorityLevels : 3; // No of priority levels } RSI_GPDMA_CAPABILITIES_T; @@ -333,35 +333,35 @@ typedef struct { // brief chnl_ctrl_info typedef PRE_PACK struct POST_PACK { - uint32_t transSize : 12; // Transfer lenght in bytes - uint32_t transType : 2; // Type of DMA transfer - uint32_t dmaFlwCtrl : 2; // Flow control type - uint32_t mastrIfFetchSel : 1; // Master controller select to fetch data - uint32_t mastrIfSendSel : 1; // Master controller select to send data - uint32_t destDataWidth : 2; // Destination data width - uint32_t srcDataWidth : 2; // Source data width - uint32_t srcAlign : 1; // Source Alignment - uint32_t linkListOn : 1; // Linked transfer on - uint32_t linkListMstrSel : 1; // Master controller select for link transfers - uint32_t srcAddContiguous : 1; // Source address contiguous - uint32_t dstAddContiguous : 1; // Destination address contiguous - uint32_t retryOnErr : 1; // Retry on error - uint32_t linkInterrupt : 1; // Link interrupt enable - uint32_t srcFifoMode : 1; // Source FIFO mode - uint32_t dstFifoMode : 1; // Destination FIFO mode - uint32_t reserved : 1; + unsigned int transSize : 12; // Transfer lenght in bytes + unsigned int transType : 2; // Type of DMA transfer + unsigned int dmaFlwCtrl : 2; // Flow control type + unsigned int mastrIfFetchSel : 1; // Master controller select to fetch data + unsigned int mastrIfSendSel : 1; // Master controller select to send data + unsigned int destDataWidth : 2; // Destination data width + unsigned int srcDataWidth : 2; // Source data width + unsigned int srcAlign : 1; // Source Alignment + unsigned int linkListOn : 1; // Linked transfer on + unsigned int linkListMstrSel : 1; // Master controller select for link transfers + unsigned int srcAddContiguous : 1; // Source address contiguous + unsigned int dstAddContiguous : 1; // Destination address contiguous + unsigned int retryOnErr : 1; // Retry on error + unsigned int linkInterrupt : 1; // Link interrupt enable + unsigned int srcFifoMode : 1; // Source FIFO mode + unsigned int dstFifoMode : 1; // Destination FIFO mode + unsigned int reserved : 1; } RSI_GPDMA_CHA_CONTROL_T; //brief Misc_chnl_ctrl_info typedef PRE_PACK struct POST_PACK { - uint32_t ahbBurstSize : 3; // AHB Burst size - uint32_t destDataBurst : 6; // Destination data Burst size - uint32_t srcDataBurst : 6; // source data Burst size - uint32_t destChannelId : 6; // Dest channel ID - uint32_t srcChannelId : 6; // Source channel ID - uint32_t dmaProt : 3; - uint32_t memoryFillEn : 1; // Memory fill enable - uint32_t memoryOneFill : 1; // Memory fill with 1 or 0 + unsigned int ahbBurstSize : 3; // AHB Burst size + unsigned int destDataBurst : 6; // Destination data Burst size + unsigned int srcDataBurst : 6; // source data Burst size + unsigned int destChannelId : 6; // Dest channel ID + unsigned int srcChannelId : 6; // Source channel ID + unsigned int dmaProt : 3; + unsigned int memoryFillEn : 1; // Memory fill enable + unsigned int memoryOneFill : 1; // Memory fill with 1 or 0 } RSI_GPDMA_MISC_CHA_CONTROL_T; //brief GPDMA controller handle type diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_qspi.h b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_qspi.h index 5609811b5..b3730fbac 100644 --- a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_qspi.h +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_qspi.h @@ -537,8 +537,6 @@ struct qspi_reg_s { #define CHK_DUAL_MODE (spi_config->spi_config_1.data_mode == DUAL_MODE) #define CHK_OCTA_MODE (spi_config->spi_config_1.data_mode == OCTA_MODE) -//#define IS_QSPI_IN_OCTA (((qspi_reg->QSPI_BUS_MODE_REG & 0x6) >> 1) == OCTA_MODE) - // Macro to provide protection byte for SST #define SST_PROTECTION ((spi_config->spi_config_2.protection == EN_WR_PROT) ? 0xFF : 0) // Macro to provide protection byte for WB diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_qspi_proto.h b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_qspi_proto.h index c1fbf39bf..97939ba68 100644 --- a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_qspi_proto.h +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_qspi_proto.h @@ -79,12 +79,12 @@ typedef struct qspi_reg_s qspi_reg_t; typedef struct spi_config_1_s { // QSPI operation modes, all modes are single, dual or quad - uint32_t inst_mode : 2; // instruction will be sent in this mode - uint32_t addr_mode : 2; // addr will be sent in this mode - uint32_t data_mode : 2; // data will be sent/received in this mode - uint32_t dummy_mode : 2; // dummy bytes will be sent/received in this mode - uint32_t extra_byte_mode : 2; // extra bytes will be sent in this mode - // SPI mode + unsigned int inst_mode : 2; // instruction will be sent in this mode + unsigned int addr_mode : 2; // addr will be sent in this mode + unsigned int data_mode : 2; // data will be sent/received in this mode + unsigned int dummy_mode : 2; // dummy bytes will be sent/received in this mode + unsigned int extra_byte_mode : 2; // extra bytes will be sent in this mode + // SPI mode #define SINGLE_MODE 0 // dual mode #define DUAL_MODE 1 @@ -92,36 +92,36 @@ typedef struct spi_config_1_s { #define QUAD_MODE 2 #define OCTA_MODE 3 - uint32_t prefetch_en : 1; // prefetch enable + unsigned int prefetch_en : 1; // prefetch enable // prefetch will be enabled #define EN_PREFETCH 1 // prefetch will be disabled #define DIS_PREFETCH 0 - uint32_t dummy_W_or_R : 1; // dummy writes or read select + unsigned int dummy_W_or_R : 1; // dummy writes or read select // dummy's are read #define DUMMY_READS 0 // dummy's are written #define DUMMY_WRITES 1 - uint32_t extra_byte_en : 1; // Enable extra byte - // Extra byte will be enabled + unsigned int extra_byte_en : 1; // Enable extra byte + // Extra byte will be enabled #define EN_EXTRA_BYTE // Extra byte will be disabled #define DIS_EXTRA_BYTE - uint32_t d3d2_data : 2; // Data on D3 and D2 line in SPI or DUAL mode + unsigned int d3d2_data : 2; // Data on D3 and D2 line in SPI or DUAL mode - uint32_t continuous : 1; // continuous mode select - // continuous mode is selected + unsigned int continuous : 1; // continuous mode select + // continuous mode is selected #define CONTINUOUS 1 // discontinuous mode is selected #define DIS_CONTINUOUS 0 - uint32_t read_cmd : 8; // read cmd to be used + unsigned int read_cmd : 8; // read cmd to be used - uint32_t flash_type : 4; // flash defines - // sst spi flash + unsigned int flash_type : 4; // flash defines + // sst spi flash #define FREAD_QUAD_O 0x6B #define FREAD_QUAD_O_EB 0xEB @@ -164,19 +164,19 @@ typedef struct spi_config_1_s { #define XMC_FLASH 13 #endif - uint32_t no_of_dummy_bytes : 4; // no_of_dummy_bytes to be used for read operations + unsigned int no_of_dummy_bytes : 4; // no_of_dummy_bytes to be used for read operations } spi_config_1_t; // This structure members are used to configure qspi typedef struct spi_config_2_s { - uint32_t auto_mode : 1; // mode select + unsigned int auto_mode : 1; // mode select // Auto mode selection #define EN_AUTO_MODE 1 // Manual mode selection #define EN_MANUAL_MODE 0 - uint32_t cs_no : 2; // QSPI chip_select + unsigned int cs_no : 2; // QSPI chip_select // cs-0 #define CHIP_ZERO 0 // cs-1 @@ -186,25 +186,25 @@ typedef struct spi_config_2_s { // cs-3 #define CHIP_THREE 3 - uint32_t reserved1 : 1; // Jump Enable + unsigned int reserved1 : 1; // Jump Enable // Enables jump #define EN_JUMP 1 // Disables jump #define DIS_JUMP 0 - uint32_t neg_edge_sampling : 1; // For High speed mode, sample at neg edge + unsigned int neg_edge_sampling : 1; // For High speed mode, sample at neg edge // enables neg edge sampling #define NEG_EDGE_SAMPLING 1 // enables pos edge sampling #define POS_EDGE_SAMPLING 0 - uint32_t qspi_clk_en : 1; // qspi clk select + unsigned int qspi_clk_en : 1; // qspi clk select // full time clk will be provided #define QSPI_FULL_TIME_CLK 1 // dynamic clk gating will be enabled #define QSPI_DYNAMIC_CLK 0 - uint32_t protection : 2; // flash protection select + unsigned int protection : 2; // flash protection select // enable write protection #define EN_WR_PROT 2 // remove write protection @@ -212,19 +212,19 @@ typedef struct spi_config_2_s { // no change to wr protection #define DNT_REM_WR_PROT 0 - uint32_t dma_mode : 1; // dma mode enable + unsigned int dma_mode : 1; // dma mode enable // use dma only in manaul mode #define DMA_MODE 1 // dma will not be used #define NO_DMA 0 - uint32_t swap_en : 1; // swap enable for w/r + unsigned int swap_en : 1; // swap enable for w/r // swap will be enabled #define SWAP 1 // swap will be disabled #define NO_SWAP 0 - uint32_t full_duplex : 2; // full duplex mode select + unsigned int full_duplex : 2; // full duplex mode select // do nothing for full duplex #define IGNORE_FULL_DUPLEX 2 // enable full duplex @@ -232,7 +232,7 @@ typedef struct spi_config_2_s { // disable full duplex #define DIS_FULL_DUPLEX 0 - uint32_t wrap_len_in_bytes : 3; // wrap len to be used + unsigned int wrap_len_in_bytes : 3; // wrap len to be used // wrap is diabled #define NO_WRAP 7 // 8 byte wrap will be used @@ -251,11 +251,11 @@ typedef struct spi_config_2_s { // 64 byte wrap will be used #define MICRON_64BYTE_WRAP 2 - uint32_t addr_width_valid : 1; + unsigned int addr_width_valid : 1; // mode 3 clk will be used // mode 0 clk will be used - uint32_t addr_width : 3; // addr width to used + unsigned int addr_width : 3; // addr width to used // 32 bit addr is configured #define _32BIT_ADDR 4 // 24 bit addr is configured @@ -269,14 +269,14 @@ typedef struct spi_config_2_s { #define MANUAL_DUMMY_BYTE_OR_BIT_MODE BIT(25) #define DUMMY_BYTE_OR_BIT_MODE BIT(0) - uint32_t dummy_cycles_for_controller : 2; + unsigned int dummy_cycles_for_controller : 2; - uint32_t reserved2 : 6; + unsigned int reserved2 : 6; // uint32 jump_inst : 8; // Instruction to be used in case of jump - uint32_t pinset_valid : 1; + unsigned int pinset_valid : 1; - uint32_t flash_pinset : 4; // width of memory protection reg for sst flashes + unsigned int flash_pinset : 4; // width of memory protection reg for sst flashes } spi_config_2_t; @@ -284,73 +284,73 @@ typedef struct spi_config_2_s { typedef struct spi_config_3_s { #define CONTINUE_FETCH_EN BIT(12) #define WORD_SWAP_EN 20 - uint32_t en_word_swap : 1; - uint32_t _16bit_cmd_valid : 1; - uint32_t _16bit_rd_cmd_msb : 8; - uint32_t xip_mode : 1; - uint32_t no_of_dummy_bytes_wrap : 4; // no_of_dummy_bytes to be used for wrap operations + unsigned int en_word_swap : 1; + unsigned int _16bit_cmd_valid : 1; + unsigned int _16bit_rd_cmd_msb : 8; + unsigned int xip_mode : 1; + unsigned int no_of_dummy_bytes_wrap : 4; // no_of_dummy_bytes to be used for wrap operations #ifdef CHIP_9118 - uint32_t ddr_mode_en : 1; + unsigned int ddr_mode_en : 1; #else - uint32_t reserved : 1; + unsigned int reserved : 1; #endif - uint32_t wr_cmd : 8; - uint32_t wr_inst_mode : 2; - uint32_t wr_addr_mode : 2; - uint32_t wr_data_mode : 2; - uint32_t dummys_4_jump : 2; // no_of_dummy_bytes in case of jump instruction + unsigned int wr_cmd : 8; + unsigned int wr_inst_mode : 2; + unsigned int wr_addr_mode : 2; + unsigned int wr_data_mode : 2; + unsigned int dummys_4_jump : 2; // no_of_dummy_bytes in case of jump instruction } spi_config_3_t; typedef struct spi_config_4_s { - uint32_t _16bit_wr_cmd_msb : 8; - uint32_t high_perf_mode_en : 1; //used for high performance mode not ddr - uint32_t qspi_loop_back_mode_en : 1; + unsigned int _16bit_wr_cmd_msb : 8; + unsigned int high_perf_mode_en : 1; //used for high performance mode not ddr + unsigned int qspi_loop_back_mode_en : 1; #ifdef CHIP_9118 - uint32_t qspi_manual_ddr_phasse : 1; - uint32_t ddr_data_mode : 1; - uint32_t ddr_inst_mode : 1; - uint32_t ddr_addr_mode : 1; - uint32_t ddr_dummy_mode : 1; - uint32_t ddr_extra_byte : 1; + unsigned int qspi_manual_ddr_phasse : 1; + unsigned int ddr_data_mode : 1; + unsigned int ddr_inst_mode : 1; + unsigned int ddr_addr_mode : 1; + unsigned int ddr_dummy_mode : 1; + unsigned int ddr_extra_byte : 1; #else - uint32_t reserved : 1; - uint32_t reserved1 : 1; - uint32_t reserved2 : 1; - uint32_t reserved3 : 1; - uint32_t reserved4 : 1; - uint32_t reserved5 : 1; + unsigned int reserved : 1; + unsigned int reserved1 : 1; + unsigned int reserved2 : 1; + unsigned int reserved3 : 1; + unsigned int reserved4 : 1; + unsigned int reserved5 : 1; #endif - uint32_t dual_flash_mode : 1; - uint32_t secondary_csn : 1; - uint32_t polarity_mode : 1; - uint32_t valid_prot_bits : 4; - uint32_t no_of_ms_dummy_bytes : 4; + unsigned int dual_flash_mode : 1; + unsigned int secondary_csn : 1; + unsigned int polarity_mode : 1; + unsigned int valid_prot_bits : 4; + unsigned int no_of_ms_dummy_bytes : 4; #ifdef CHIP_9118 - uint32_t ddr_dll_en : 1; + unsigned int ddr_dll_en : 1; #else - uint32_t reserved6 : 1; + unsigned int reserved6 : 1; #endif - uint32_t continue_fetch_en : 1; - uint32_t dma_write : 1; - uint32_t prot_top_bottom : 1; - uint32_t auto_csn_based_addr_en : 1; + unsigned int continue_fetch_en : 1; + unsigned int dma_write : 1; + unsigned int prot_top_bottom : 1; + unsigned int auto_csn_based_addr_en : 1; } spi_config_4_t; typedef struct spi_config_5_s { - uint32_t block_erase_cmd : 16; - uint32_t busy_bit_pos : 3; - uint32_t d7_d4_data : 4; - uint32_t dummy_bytes_for_rdsr : 4; - uint32_t reset_type : 5; + unsigned int block_erase_cmd : 16; + unsigned int busy_bit_pos : 3; + unsigned int d7_d4_data : 4; + unsigned int dummy_bytes_for_rdsr : 4; + unsigned int reset_type : 5; } spi_config_5_t; typedef struct spi_config_6_s { - uint32_t chip_erase_cmd : 16; - uint32_t sector_erase_cmd : 16; + unsigned int chip_erase_cmd : 16; + unsigned int sector_erase_cmd : 16; } spi_config_6_t; typedef struct spi_config_7_s { - uint32_t status_reg_write_cmd : 16; - uint32_t status_reg_read_cmd : 16; + unsigned int status_reg_write_cmd : 16; + unsigned int status_reg_read_cmd : 16; } spi_config_7_t; // This structure has two daughter structures to configure qspi diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_timers.h b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_timers.h index 69ba02400..1c90ae126 100644 --- a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_timers.h +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_timers.h @@ -107,7 +107,7 @@ STATIC INLINE rsi_error_t RSI_TIMERS_SetDirection(RSI_TIMERS_T *pTIMER, uint8_t /*===================================================*/ /** - * @fn uint32_t RSI_TIMERS_getDirection(RSI_TIMERS_T *pTIMER, uint8_t timerNum) + * @fn uint32_t RSI_TIMERS_getDirection(const RSI_TIMERS_T *pTIMER, uint8_t timerNum) * @brief This API is used to get direction of the timer * @param[in] pTIMER : Pointer to the TIMERS instance register area * @param[in] timerNum : Timer number(0 to 3) @@ -116,7 +116,7 @@ STATIC INLINE rsi_error_t RSI_TIMERS_SetDirection(RSI_TIMERS_T *pTIMER, uint8_t * - 1 for UP_COUNTER * - 0 for DOWN_COUNTER */ -STATIC INLINE uint32_t RSI_TIMERS_getDirection(RSI_TIMERS_T *pTIMER, uint8_t timerNum) +STATIC INLINE uint32_t RSI_TIMERS_getDirection(const RSI_TIMERS_T *pTIMER, uint8_t timerNum) { uint8_t counterDir; if (timerNum <= TIMER_3) { @@ -129,13 +129,13 @@ STATIC INLINE uint32_t RSI_TIMERS_getDirection(RSI_TIMERS_T *pTIMER, uint8_t tim /*===================================================*/ /** - * @fn uint32_t RSI_TIMERS_GetTimerMode(RSI_TIMERS_T *pTIMER, uint8_t timerNum) + * @fn uint32_t RSI_TIMERS_GetTimerMode(const RSI_TIMERS_T *pTIMER, uint8_t timerNum) * @brief This API is used to get the mode of timer * @param[in] pTIMER : Pointer to the TIMERS instance register area * @param[in] timerNum : Timer number(0 to 3) * @return return the type of timer if valid timer else error code */ -STATIC INLINE uint32_t RSI_TIMERS_GetTimerMode(RSI_TIMERS_T *pTIMER, uint8_t timerNum) +STATIC INLINE uint32_t RSI_TIMERS_GetTimerMode(const RSI_TIMERS_T *pTIMER, uint8_t timerNum) { if (timerNum <= TIMER_3) { return (pTIMER->MATCH_CTRL[timerNum].MCUULP_TMR_CNTRL_b.TMR_MODE); @@ -254,13 +254,13 @@ STATIC INLINE rsi_error_t RSI_TIMERS_SetMatch(RSI_TIMERS_T *pTIMER, uint8_t time /*===================================================*/ /** - * @fn rsi_error_t RSI_TIMERS_InterruptStatus(RSI_TIMERS_T *pTIMER , uint8_t timerNum) + * @fn rsi_error_t RSI_TIMERS_InterruptStatus(const RSI_TIMERS_T *pTIMER , uint8_t timerNum) * @brief This API is used to get the timer interrupt status * @param[in] pTIMER : Pointer to the TIMERS instance register area * @param[in] timerNum : Timer number(0 to 3) * @return return the timer interrupt status if valid timer else 0. */ -STATIC INLINE uint8_t RSI_TIMERS_InterruptStatus(RSI_TIMERS_T *pTIMER, uint8_t timerNum) +STATIC INLINE uint8_t RSI_TIMERS_InterruptStatus(const RSI_TIMERS_T *pTIMER, uint8_t timerNum) { if (timerNum <= TIMER_3) { return (uint8_t)(pTIMER->MCUULP_TMR_INTR_STAT & (1 << timerNum)); @@ -322,13 +322,13 @@ STATIC INLINE rsi_error_t RSI_TIMERS_SetTimerMode(RSI_TIMERS_T *pTIMER, boolean_ /*===================================================*/ /** - * @fn uint32_t RSI_TIMERS_GetTimerType(RSI_TIMERS_T *pTIMER, uint8_t timerNum) + * @fn uint32_t RSI_TIMERS_GetTimerType(const RSI_TIMERS_T *pTIMER, uint8_t timerNum) * @brief This API is used to get the type of timer * @param[in] pTIMER : Pointer to the TIMERS instance register area * @param[in] timerNum : Timer number(0 to 3) * @return return the type of timer if valid timer else error code */ -STATIC INLINE uint32_t RSI_TIMERS_GetTimerType(RSI_TIMERS_T *pTIMER, uint8_t timerNum) +STATIC INLINE uint32_t RSI_TIMERS_GetTimerType(const RSI_TIMERS_T *pTIMER, uint8_t timerNum) { if (timerNum <= TIMER_3) { return (pTIMER->MATCH_CTRL[timerNum].MCUULP_TMR_CNTRL_b.TMR_TYPE); diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_udma.h b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_udma.h index b7a142ae1..d95c61ab1 100644 --- a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_udma.h +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_udma.h @@ -316,14 +316,14 @@ STATIC INLINE void RSI_UDMA_UDMADisable(RSI_UDMA_HANDLE_T pHandle) /*===================================================*/ /** - * @fn uint8_t RSI_UDMA_ErrorStatusGet(RSI_UDMA_T *pUDMA) + * @fn uint8_t RSI_UDMA_ErrorStatusGet(const RSI_UDMA_T *pUDMA) * @brief This API is used to get the error status/sets the signal low of UDMA. * @param[in] pUDMA : Pointer to the UDMA instance register area * @return Returns error status as below * - 0 : Error is LOW * - 1 : Error is HIGH */ -STATIC INLINE uint8_t RSI_UDMA_ErrorStatusGet(RSI_UDMA_T *pUDMA) +STATIC INLINE uint8_t RSI_UDMA_ErrorStatusGet(const RSI_UDMA_T *pUDMA) { return (pUDMA->ERR_CLR_b.ERR_CLR); } @@ -530,13 +530,13 @@ RSI_UDMA_CAPABILITIES_T RSI_UDMA_GetCapabilities(void); RSI_UDMA_HANDLE_T udma_init(void *mem, const RSI_UDMA_INIT_T *pInit); -uint32_t udma_get_channel_transfer_mode(RSI_UDMA_HANDLE_T pHandle, RSI_UDMA_CHA_CFG_T *pCfg); +uint32_t udma_get_channel_transfer_mode(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg); rsi_error_t udma_setup_channel_transfer(RSI_UDMA_HANDLE_T pHandle, - RSI_UDMA_CHA_CFG_T *pCfg, + const RSI_UDMA_CHA_CFG_T *pCfg, RSI_UDMA_CHA_CONFIG_DATA_T vsUdmaChaConfigData, void *pSrcAddr, - void *pDstAddr); + volatile void *pDstAddr); rsi_error_t udma_set_channel_scatter_gather_transfer(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh, @@ -545,19 +545,19 @@ rsi_error_t udma_set_channel_scatter_gather_transfer(RSI_UDMA_HANDLE_T pHandle, uint32_t transferType); uint32_t udma_get_channel_transfer_length(RSI_UDMA_HANDLE_T pHandle, - RSI_UDMA_CHA_CFG_T *pCfg, + const RSI_UDMA_CHA_CFG_T *pCfg, RSI_UDMA_CHA_CONFIG_DATA_T vsUDMAChaConfigData); -rsi_error_t udma_setup_channel(RSI_UDMA_HANDLE_T pHandle, RSI_UDMA_CHA_CFG_T *pCfg); +rsi_error_t udma_setup_channel(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg); -void udma_deInit(RSI_UDMA_HANDLE_T pHandle, RSI_UDMA_CHA_CFG_T *pCfg); +void udma_deInit(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg); void udma_interrupt_handler(RSI_UDMA_HANDLE_T pHandle); rsi_error_t udma_interrupt_enable(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh); -rsi_error_t RSI_UDMA_ChannelControlsDisable(RSI_UDMA_HANDLE_T pHandle, RSI_UDMA_CHA_CFG_T *pCfg); +rsi_error_t RSI_UDMA_ChannelControlsDisable(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg); void RSI_UDMA_SetSingleRequest(RSI_UDMA_HANDLE_T pHandle); -void RSI_UDMA_AckEnable(RSI_UDMA_HANDLE_T pHandle, uint32_t peripheral); +void RSI_UDMA_AckEnable(const void *pHandle, uint32_t peripheral); #ifdef __cplusplus } diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_udma_wrapper.h b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_udma_wrapper.h index 496235d12..2064a1d61 100644 --- a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_udma_wrapper.h +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_udma_wrapper.h @@ -47,28 +47,28 @@ typedef struct { UDMA_SignalEvent_t cb_event; } UDMA_Channel_Info; -RSI_UDMA_HANDLE_T uDMAx_Initialize(UDMA_RESOURCES *udma, +RSI_UDMA_HANDLE_T uDMAx_Initialize(const UDMA_RESOURCES *udma, RSI_UDMA_DESC_T *UDMA_Table, RSI_UDMA_HANDLE_T udmaHandle, uint32_t *mem); -int32_t uDMAx_Uninitialize(UDMA_RESOURCES *udma); -int32_t uDMAx_ChannelConfigure(UDMA_RESOURCES *udma, +int32_t uDMAx_Uninitialize(const UDMA_RESOURCES *udma); +int32_t uDMAx_ChannelConfigure(const UDMA_RESOURCES *udma, uint8_t ch, uint32_t src_addr, uint32_t dest_addr, uint32_t size, RSI_UDMA_CHA_CONFIG_DATA_T control, - RSI_UDMA_CHA_CFG_T *config, + const RSI_UDMA_CHA_CFG_T *config, UDMA_SignalEvent_t cb_event, UDMA_Channel_Info *chnl_info, RSI_UDMA_HANDLE_T udmaHandle); -int32_t uDMAx_ChannelEnable(uint8_t ch, UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle); -int32_t uDMAx_DMAEnable(UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle); -int32_t uDMAx_ChannelDisable(uint8_t ch, UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle); +int32_t uDMAx_ChannelEnable(uint8_t ch, const UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle); +int32_t uDMAx_DMAEnable(const UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle); +int32_t uDMAx_ChannelDisable(uint8_t ch, const UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle); uint32_t uDMAx_ChannelGetCount(uint8_t ch, RSI_UDMA_CHA_CONFIG_DATA_T control, RSI_UDMA_CHA_CFG_T config, - UDMA_RESOURCES *udma, + const UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle); void uDMAx_IRQHandler(UDMA_RESOURCES *udma, RSI_UDMA_DESC_T *UDMA_Table, UDMA_Channel_Info *chnl_info); diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_usart.h b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_usart.h index 7b450a668..aac7bc4e6 100644 --- a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_usart.h +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_usart.h @@ -43,32 +43,32 @@ void USART_UDMA_Rx_Event(uint32_t event, uint8_t dmaCh, USART_RESOURCES *usart); int32_t USART_SetBaudrate(uint32_t baudrate, uint32_t baseClk, USART_RESOURCES *usart); int32_t USART_Initialize(ARM_USART_SignalEvent_t cb_event, USART_RESOURCES *usart, - UDMA_RESOURCES *udma, + const UDMA_RESOURCES *udma, RSI_UDMA_DESC_T *UDMA_Table, RSI_UDMA_HANDLE_T *udmaHandle, uint32_t *mem); -int32_t USART_Uninitialize(USART_RESOURCES *usart, UDMA_RESOURCES *udma); +int32_t USART_Uninitialize(const USART_RESOURCES *usart, const UDMA_RESOURCES *udma); int32_t USART_PowerControl(ARM_POWER_STATE state, USART_RESOURCES *usart, - UDMA_RESOURCES *udma, + const UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle); int32_t USART_Send_Data(const void *data, uint32_t num, USART_RESOURCES *usart, - UDMA_RESOURCES *udma, + const UDMA_RESOURCES *udma, UDMA_Channel_Info *chnl_info, RSI_UDMA_HANDLE_T udmaHandle); int32_t USART_Receive_Data(const void *data, uint32_t num, USART_RESOURCES *usart, - UDMA_RESOURCES *udma, + const UDMA_RESOURCES *udma, UDMA_Channel_Info *chnl_info, RSI_UDMA_HANDLE_T udmaHandle); int32_t USART_Transfer(const void *data_out, void *data_in, uint32_t num, USART_RESOURCES *usart, - UDMA_RESOURCES *udma, + const UDMA_RESOURCES *udma, UDMA_Channel_Info *chnl_info, RSI_UDMA_HANDLE_T udmaHandle); uint32_t USART_GetTxCount(USART_RESOURCES *usart); @@ -77,7 +77,7 @@ int32_t USART_Control(uint32_t control, uint32_t arg, uint32_t baseClk, USART_RESOURCES *usart, - UDMA_RESOURCES *udma, + const UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle); ARM_USART_STATUS USART_GetStatus(USART_RESOURCES *usart); int32_t USART_SetModemControl(ARM_USART_MODEM_CONTROL control, USART_RESOURCES *usart); diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/sl_si91x_m4_ps.h b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/sl_si91x_m4_ps.h index 435349677..a0584b34a 100644 --- a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/sl_si91x_m4_ps.h +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/sl_si91x_m4_ps.h @@ -51,7 +51,6 @@ * retention submitting the buffer valid to the TA for the rx packets. */ void sl_si91x_m4_sleep_wakeup(void); -void sl_si91x_pre_supress_ticks_and_sleep(uint32_t *xExpectedIdleTime); /** * @fn initialize_m4_alarm. * @brief This function is to initialize Alarm block . diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/clock_update.c b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/clock_update.c index 26288c22f..ec99c2753 100644 --- a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/clock_update.c +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/clock_update.c @@ -110,6 +110,8 @@ uint32_t RSI_CLK_GetBaseClock(PERI_CLKS_T peri_src) case ULPSS_ULP_DOUBLER_CLK: src_clk = system_clocks.doubler_clock; break; + default: + break; } break; case USART_MODELPLLCLK2: @@ -124,6 +126,8 @@ uint32_t RSI_CLK_GetBaseClock(PERI_CLKS_T peri_src) case M4_SOCCLKFOROTHERCLOCKS: src_clk = system_clocks.soc_clock; break; + default: + break; } div_fac = M4CLK->CLK_CONFIG_REG2_b.USART1_SCLK_DIV_FAC; swallow_val = M4CLK->CLK_CONFIG_REG2_b.USART1_SCLK_FRAC_SEL; @@ -165,6 +169,8 @@ uint32_t RSI_CLK_GetBaseClock(PERI_CLKS_T peri_src) case ULPSS_ULP_DOUBLER_CLK: src_clk = system_clocks.doubler_clock; break; + default: + break; } break; case USART_MODELPLLCLK2: @@ -179,6 +185,8 @@ uint32_t RSI_CLK_GetBaseClock(PERI_CLKS_T peri_src) case M4_SOCCLKFOROTHERCLOCKS: src_clk = system_clocks.soc_clock; break; + default: + break; } div_fac = M4CLK->CLK_CONFIG_REG2_b.USART2_SCLK_DIV_FAC; swallow_val = M4CLK->CLK_CONFIG_REG2_b.USART2_SCLK_FRAC_SEL; @@ -220,6 +228,8 @@ uint32_t RSI_CLK_GetBaseClock(PERI_CLKS_T peri_src) case ULPSS_ULP_DOUBLER_CLK: src_clk = system_clocks.doubler_clock; break; + default: + break; } break; case SSI_SOCPLLCLK: @@ -237,6 +247,8 @@ uint32_t RSI_CLK_GetBaseClock(PERI_CLKS_T peri_src) case M4_SOCCLKFOROTHERCLKS: src_clk = system_clocks.soc_clock; break; + default: + break; } div_fac = (M4CLK->CLK_CONFIG_REG1_b.SSI_MST_SCLK_DIV_FAC); if (div_fac == 0) { @@ -269,6 +281,8 @@ uint32_t RSI_CLK_GetBaseClock(PERI_CLKS_T peri_src) case ULPSS_ULP_DOUBLER_CLK: src_clk = system_clocks.doubler_clock; break; + default: + break; } break; case CT_INTFPLLCLK: @@ -280,6 +294,8 @@ uint32_t RSI_CLK_GetBaseClock(PERI_CLKS_T peri_src) case M4_SOCCLKFOROTHERCLKSCT: src_clk = system_clocks.soc_clock; break; + default: + break; } div_fac = (M4CLK->CLK_CONFIG_REG5_b.CT_CLK_DIV_FAC); if (div_fac == 0) { @@ -304,6 +320,8 @@ uint32_t RSI_CLK_GetBaseClock(PERI_CLKS_T peri_src) case M4_SOCCLKFOROTHERCLKSSDMEM: src_clk = system_clocks.soc_clock; break; + default: + break; } swallow_val = M4CLK->SD_MEM_CLOCK_REG_b.SD_MEM_INTF_CLK_SWALLOW_SEL; div_fac = (M4CLK->SD_MEM_CLOCK_REG_b.SD_MEM_INTF_CLK_DIV_FAC); @@ -331,6 +349,8 @@ uint32_t RSI_CLK_GetBaseClock(PERI_CLKS_T peri_src) case CCI_INTF_PLL_CLK: src_clk = system_clocks.intf_pll_clock; break; + default: + break; } div_fac = (M4CLK->CLK_CONFIG_REG2_b.CCI_CLK_DIV_FAC); if (div_fac == 0) { @@ -358,6 +378,8 @@ uint32_t RSI_CLK_GetBaseClock(PERI_CLKS_T peri_src) case M4_SOCCLKNOSWLSYNCCLKTREEGATED: //TODO:src_clk =system_clocks. break; + default: + break; } swallow_val = (M4CLK->CLK_CONFIG_REG1_b.QSPI_CLK_SWALLOW_SEL); div_fac = (M4CLK->CLK_CONFIG_REG1_b.QSPI_CLK_DIV_FAC); @@ -411,6 +433,8 @@ uint32_t RSI_CLK_GetBaseClock(PERI_CLKS_T peri_src) case M4_SOCCLKNOSWLSYNCCLKTREEGATED: //TODO:src_clk =system_clocks. break; + default: + break; } swallow_val = (M4CLK->CLK_CONFIG_REG1_b.QSPI_CLK_SWALLOW_SEL); div_fac = (M4CLK->CLK_CONFIG_REG1_b.QSPI_CLK_DIV_FAC); @@ -472,6 +496,8 @@ uint32_t RSI_CLK_GetBaseClock(PERI_CLKS_T peri_src) case ULPSS_ULP_DOUBLER_CLK: src_clk = system_clocks.doubler_clock; break; + default: + break; } break; case GSPI_SOC_PLL_CLK: @@ -483,6 +509,8 @@ uint32_t RSI_CLK_GetBaseClock(PERI_CLKS_T peri_src) case GSPI_INTF_PLL_CLK: src_clk = system_clocks.intf_pll_clock; break; + default: + break; } break; @@ -495,6 +523,8 @@ uint32_t RSI_CLK_GetBaseClock(PERI_CLKS_T peri_src) case ETH_SOC_PLL_CLK: src_clk = system_clocks.soc_pll_clock; break; + default: + break; } div_fac = (M4CLK->CLK_CONFIG_REG1_b.PLL_INTF_CLK_DIV_FAC); @@ -523,6 +553,8 @@ uint32_t RSI_CLK_GetBaseClock(PERI_CLKS_T peri_src) case I2S_M4SOCCLKFOROTHERS: src_clk = system_clocks.soc_clock; break; + default: + break; } div_fac = (M4CLK->CLK_CONFIG_REG5_b.I2S_CLK_DIV_FAC); if (div_fac == 0) { @@ -556,6 +588,8 @@ uint32_t RSI_CLK_GetBaseClock(PERI_CLKS_T peri_src) case ULP_SSI_SOC_CLK: src_clk = system_clocks.soc_clock; break; + default: + break; } div_fac = (ULPCLK->ULP_I2C_SSI_CLK_GEN_REG_b.ULP_SSI_CLK_DIV_FACTOR); if (div_fac == 0) { @@ -586,6 +620,8 @@ uint32_t RSI_CLK_GetBaseClock(PERI_CLKS_T peri_src) case ULP_I2S_ULP_20MHZ_RO_CLK: src_clk = system_clocks.ro_20mhz_clock; break; + default: + break; } div_fac = (ULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_CLKDIV_FACTOR); if (div_fac == 0) { @@ -622,6 +658,8 @@ uint32_t RSI_CLK_GetBaseClock(PERI_CLKS_T peri_src) case ULP_UART_ULP_DOUBLER_CLK: src_clk = system_clocks.doubler_clock; break; + default: + break; } div_fac = (ULPCLK->ULP_UART_CLK_GEN_REG_b.ULP_UART_CLKDIV_FACTOR); if (div_fac == 0) { @@ -655,6 +693,8 @@ uint32_t RSI_CLK_GetBaseClock(PERI_CLKS_T peri_src) case ULP_TIMER_ULP_SOC_CLK: src_clk = system_clocks.soc_clock; break; + default: + break; } //no division factor break; @@ -689,6 +729,8 @@ uint32_t RSI_CLK_GetBaseClock(PERI_CLKS_T peri_src) case ULP_AUX_I2S_PLL_CLK: src_clk = system_clocks.i2s_pll_clock; break; + default: + break; } //no division factor break; @@ -717,6 +759,8 @@ uint32_t RSI_CLK_GetBaseClock(PERI_CLKS_T peri_src) case ULP_TOUCH_ULP_SOC_CLK: src_clk = system_clocks.soc_clock; break; + default: + break; } div_fac = (ULPCLK->ULP_TOUCH_CLK_GEN_REG_b.ULP_TOUCH_CLKDIV_FACTOR); if (div_fac == 0) { diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_adc.c b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_adc.c index 7eaa4618b..a5086b38c 100644 --- a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_adc.c +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_adc.c @@ -144,15 +144,16 @@ rsi_error_t ADC_Init(adc_ch_config_t adcChConfig, adc_config_t adcConfig, adccal // Power up of ADC block RSI_ADC_PowerControl(ADC_POWER_ON); - // Select 32MHZ RC clock for ADC + // Select 32MHz RC clock for ADC RSI_ULPSS_AuxClkConfig(ULPCLK, ENABLE_STATIC_CLK, ULP_AUX_32MHZ_RC_CLK); - // Clock division factor for calibration,Calibrate ADC on 4MHZ clock + // Clock division factor for calibration,Calibrate ADC on 4MHz clock RSI_ADC_ClkDivfactor(AUX_ADC_DAC_COMP, 0, 4); // Set analog reference voltage RSI_AUX_RefVoltageConfig((float)2.8, (float)3.2); + // TODO // ADC Calibration RSI_ADC_Calibration(); @@ -163,31 +164,30 @@ rsi_error_t ADC_Init(adc_ch_config_t adcChConfig, adc_config_t adcConfig, adccal clk_sel = (adcChConfig.sampling_rate[0] * (adcConfig.num_of_channel_enable * 2)); } - // Configure 32Khz RC clock to ADC + // Configure 32kHz RC clock to ADC if (clk_sel < SAMPLE_RATE_32KSPS) { - // Select 32KHZ RC clock for ADC + // Select 32KHz RC clock for ADC RSI_ULPSS_AuxClkConfig(ULPCLK, ENABLE_STATIC_CLK, ULP_AUX_32KHZ_RC_CLK); adc_commn_config.adc_clk_src = ADC_CLK_SOURCE_32KHZ; } - // Configure 20MHZ RC clock to ADC + // Configure 32MHz RC clock to ADC else if (clk_sel >= SAMPLE_RATE_32KSPS && clk_sel <= SAMPLE_RATE_800KSPS) { - RSI_IPMU_M20rcOsc_TrimEfuse(); - // Select 32MHZ RC clock for ADC + // Select 32MHz RC clock for ADC RSI_ULPSS_AuxClkConfig(ULPCLK, ENABLE_STATIC_CLK, ULP_AUX_32MHZ_RC_CLK); - adc_commn_config.adc_clk_src = ADC_CLK_SOURCE_20MHZ; + adc_commn_config.adc_clk_src = ADC_CLK_SOURCE_32MHZ; } else { - // Configure the 40Mhz XTAL clock to ADC + // Configure the 32MHz RC clock to ADC if (!(M4_ULP_SLP_STATUS_REG & ULP_MODE_SWITCHED_NPSS)) { #ifdef SIMULATION RSI_ULPSS_AuxClkConfig(ULPCLK, ENABLE_STATIC_CLK, ULP_AUX_32MHZ_RC_CLK); adc_commn_config.adc_clk_src = ADC_CLK_SOURCE_32MHZ; #else - // Select 40MHZ XTAL ULP reference clock + // Select 32MHz RC ULP reference clock RSI_ULPSS_RefClkConfig(ULPSS_ULP_32MHZ_RC_CLK); - // Select 40MHZ XTAL clock for ADC + // Select 40MHz XTAL clock for ADC RSI_ULPSS_AuxClkConfig(ULPCLK, ENABLE_STATIC_CLK, ULP_AUX_REF_CLK); adc_commn_config.adc_clk_src = ADC_CLK_SOURCE_40MHZ; @@ -203,11 +203,6 @@ rsi_error_t ADC_Init(adc_ch_config_t adcChConfig, adc_config_t adcConfig, adccal adc_commn_config.adc_diff_gain = 0x0; adc_commn_config.adc_sing_gain = 0x0; #else - // Trim 32Mhz rc clock to 20Mhz rc clock in PS2 state - if (M4_ULP_SLP_STATUS_REG & ULP_MODE_SWITCHED_NPSS) { - // Trim Mhz RC clock to 20Mhz - RSI_IPMU_M20rcOsc_TrimEfuse(); - } // Offset value and gain value read from efuse adc_commn_config.adc_sing_offset = (uint16_t)RSI_IPMU_Auxadcoff_SeEfuse(); @@ -233,7 +228,7 @@ rsi_error_t ADC_Init(adc_ch_config_t adcChConfig, adc_config_t adcConfig, adccal return RSI_OK; } -// Revisit for optimization To do +// Revisit for optimization TODO rsi_error_t ADC_Per_Channel_Init(adc_ch_config_t adcChConfig, adc_config_t adcConfig, adccallbacFunc event) { #ifndef SIMULATION @@ -274,10 +269,10 @@ rsi_error_t ADC_Per_Channel_Init(adc_ch_config_t adcChConfig, adc_config_t adcCo // Power up of ADC block RSI_ADC_PowerControl(ADC_POWER_ON); - // Select 32MHZ RC clock for ADC + // Select 32MHz RC clock for ADC RSI_ULPSS_AuxClkConfig(ULPCLK, ENABLE_STATIC_CLK, ULP_AUX_32MHZ_RC_CLK); - // Clock division factor for calibration,Calibrate ADC on 4MHZ clock + // Clock division factor for calibration,Calibrate ADC on 4MHz clock RSI_ADC_ClkDivfactor(AUX_ADC_DAC_COMP, 0, 4); // Set analog reference voltage @@ -286,35 +281,32 @@ rsi_error_t ADC_Per_Channel_Init(adc_ch_config_t adcChConfig, adc_config_t adcCo // ADC Calibration RSI_ADC_Calibration(); - // Configure 32Khz RC clock to ADC + // Configure clock source to ADC if (adcChConfig.sampling_rate[adc_channel] <= SAMPLE_RATE_9KSPS) { - // Select 32KHZ RC clock for ADC + // Select 32kHz RC clock for ADC RSI_ULPSS_AuxClkConfig(ULPCLK, ENABLE_STATIC_CLK, ULP_AUX_32KHZ_RC_CLK); adc_commn_config.adc_clk_src = ADC_CLK_SOURCE_32KHZ; - } - // Configure 64Khz RC clock to ADC - else if (adcChConfig.sampling_rate[adc_channel] > SAMPLE_RATE_9KSPS - && adcChConfig.sampling_rate[adc_channel] < SAMPLE_RATE_800KSPS) { - RSI_IPMU_M20rcOsc_TrimEfuse(); - // Select 32KHZ RC clock for ADC + } else if (adcChConfig.sampling_rate[adc_channel] > SAMPLE_RATE_9KSPS + && adcChConfig.sampling_rate[adc_channel] < SAMPLE_RATE_800KSPS) { + // Select 32MHz RC clock for ADC RSI_ULPSS_AuxClkConfig(ULPCLK, ENABLE_STATIC_CLK, ULP_AUX_32MHZ_RC_CLK); - adc_commn_config.adc_clk_src = ADC_CLK_SOURCE_20MHZ; + adc_commn_config.adc_clk_src = ADC_CLK_SOURCE_32MHZ; } else { - // Configure the 40Mhz XTAL clock to ADC + // Configure the 32MHz RC clock to ADC if (!(M4_ULP_SLP_STATUS_REG & ULP_MODE_SWITCHED_NPSS)) { #ifdef SIMULATION RSI_ULPSS_AuxClkConfig(ULPCLK, ENABLE_STATIC_CLK, ULP_AUX_32MHZ_RC_CLK); adc_commn_config.adc_clk_src = ADC_CLK_SOURCE_32MHZ; #else - // Select 40MHZ XTAL ULP reference clock + // Select 32MHz RC ULP reference clock RSI_ULPSS_RefClkConfig(ULPSS_ULP_32MHZ_RC_CLK); - // Select 40MHZ XTAL clock for ADC - RSI_ULPSS_AuxClkConfig(ULPCLK, ENABLE_STATIC_CLK, ULP_AUX_REF_CLK); + // Select 32MHz RC clock for ADC + RSI_ULPSS_AuxClkConfig(ULPCLK, ENABLE_STATIC_CLK, ULP_AUX_32MHZ_RC_CLK); - adc_commn_config.adc_clk_src = ADC_CLK_SOURCE_40MHZ; + adc_commn_config.adc_clk_src = ADC_CLK_SOURCE_32MHZ; #endif } else { adc_commn_config.adc_clk_src = ADC_CLK_SOURCE_20MHZ; @@ -327,12 +319,6 @@ rsi_error_t ADC_Per_Channel_Init(adc_ch_config_t adcChConfig, adc_config_t adcCo adc_commn_config.adc_diff_gain = 0x0; adc_commn_config.adc_sing_gain = 0x0; #else - // Trim 32Mhz rc clock to 20Mhz rc clock in PS2 state - if (M4_ULP_SLP_STATUS_REG & ULP_MODE_SWITCHED_NPSS) { - // Trim Mhz RC clock to 20Mhz - RSI_IPMU_M20rcOsc_TrimEfuse(); - } - // Offset value and gain value read from efuse adc_commn_config.adc_sing_offset = (uint16_t)RSI_IPMU_Auxadcoff_SeEfuse(); adc_commn_config.adc_diff_offset = (uint16_t)RSI_IPMU_Auxadcoff_DiffEfuse(); @@ -1561,7 +1547,7 @@ void RSI_ADC_Calibration(void) /*wait for 0*/ while ((ULP_SPI_MEM_MAP(SPAREREG2) & BIT(0))) ; - /*150 clocks of 1 Mhz wait*/ + /*150 clocks of 1MHz wait*/ auxadcCalibValue = ULP_SPI_MEM_MAP(AUXADCREG2); auxadcCalibValueLoad |= BIT(0) | BIT(7); auxadcCalibValueLoad |= (auxadcCalibValue & 0x1F) << 2; diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_crc.c b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_crc.c index fa3856203..05f849623 100644 --- a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_crc.c +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_crc.c @@ -21,6 +21,7 @@ #ifndef CRC_ROMDRIVER_PRESENT #include "rsi_rom_crc.h" +#include "si91x_device.h" /*==============================================*/ /** diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_d_cache.c b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_d_cache.c new file mode 100644 index 000000000..da2a676c3 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_d_cache.c @@ -0,0 +1,233 @@ +/******************************************************************************* +* @file rsi_d_cache.c +* @brief +******************************************************************************* +* # License +* Copyright 2024 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +/******************************************************************************* + *************************** Include Files ******************************** + ******************************************************************************/ + +#include "rsi_d_cache.h" + +DCache_Reg_Type *DCACHE = (DCache_Reg_Type *)M4SS_DCACHE_BASE_ADDR; // DCache register access handle + +/*==============================================*/ +/** + * @fn void rsi_d_cache_enable(void) + * @brief This API is used to enable the data cache and sets it to write-through mode + * @return None + */ +void rsi_d_cache_enable(void) +{ + /*Enable the Cache and write through*/ + DCACHE->CTRL |= (DCACHE_CTRL_ENABLE | DCACHE_CTRL_FORCE_WT); + + while (DCACHE->MAINT_STATUS != (DCACHE_MAINT_STATUS_CACHE_ENABLED | DCACHE_MAINT_STATUS_CACHE_IS_CLEAN)) + ; +} + +/*==============================================*/ +/** + * @fn void rsi_d_cache_disable(void) + * @brief This API is used to disable the data cache + * @return None + */ +void rsi_d_cache_disable(void) +{ + /*Disable the Cache*/ + DCACHE->CTRL &= ~(DCACHE_CTRL_ENABLE); + while ((DCACHE->MAINT_STATUS & (DCACHE_MAINT_STATUS_CACHE_ENABLED | DCACHE_MAINT_STATUS_ONGOING_EN_DIS)) != 0x0) + ; +} + +/*==============================================*/ +/** + * @fn void rsi_d_cache_invalidate_all(void) + * @brief This API is used to invalidate all cache lines, forcing data to be fetched from memory on subsequent accesses + * @return None + */ +void rsi_d_cache_invalidate_all(void) +{ + + /*Wait until ongoing cache op is done, wait for ONGOING_EN_DIS,ONGOING_MAINT and ONGOING_PWR_MAINT*/ + while ( + (DCACHE->MAINT_STATUS + & (DCACHE_MAINT_STATUS_ONGOING_EN_DIS | DCACHE_MAINT_STATUS_ONGOING_MAINT | DCACHE_MAINT_STATUS_ONGOING_PWR_MAINT)) + != 0x0) + ; + + /*Clear Pending all interrupts, if needs to be served, clear after Interrupt serve*/ + DCACHE->SECIRQSCLR = DCACHE_SECIRQSCLR_CLEAR_ALL; + + /*Initiate invalidate entire cache*/ + DCACHE->MAINT_CTRL_ALL |= DCACHE_MAINT_CTRL_ALL_TRIG_INVALIDATE; + + /*Wait until the operation is finished*/ + while ((DCACHE->MAINT_STATUS & DCACHE_MAINT_STATUS_ONGOING_MAINT) != 0x0) + ; +} + +/*==============================================*/ +/** + * @fn void rsi_d_cache_clean_up_all(void) + * @brief This API is used to write back all modified cache lines to memory, ensuring data consistency + * @return None + */ +void rsi_d_cache_clean_up_all(void) +{ + /*Wait until ongoing cache op is done, wait for ONGOING_EN_DIS,ONGOING_MAINT and ONGOING_PWR_MAINT*/ + while ( + (DCACHE->MAINT_STATUS + & (DCACHE_MAINT_STATUS_ONGOING_EN_DIS | DCACHE_MAINT_STATUS_ONGOING_MAINT | DCACHE_MAINT_STATUS_ONGOING_PWR_MAINT)) + != 0x0) + ; + + /*Clear Pending all interrupts, if needs to be served, clear after Interrupt serve*/ + DCACHE->SECIRQSCLR = DCACHE_SECIRQSCLR_CLEAR_ALL; + + /*Initiate clean up for entire cache*/ + DCACHE->MAINT_CTRL_ALL |= DCACHE_MAINT_CTRL_ALL_TRIG_CLEAN; + + /*Wait until the operation is finished*/ + while ((DCACHE->MAINT_STATUS & DCACHE_MAINT_STATUS_ONGOING_MAINT) != 0x0) + ; +} +/*==============================================*/ +/** + * @fn void rsi_d_cache_invalidate_address(uint32_t address) + * @brief This API is used to invalidate the cache line that contains the specified address, forcing subsequent accesses to fetch data from memory + * @param[in] address: The memory address whose cache line needs to be invalidated. + * @return None + */ +void rsi_d_cache_invalidate_address(uint32_t address) +{ + + /*Wait until ongoing cache op is done, wait for ONGOING_EN_DIS,ONGOING_MAINT and ONGOING_PWR_MAINT*/ + while ((DCACHE->MAINT_STATUS + & (DCACHE->MAINT_STATUS + & (DCACHE_MAINT_STATUS_ONGOING_EN_DIS | DCACHE_MAINT_STATUS_ONGOING_MAINT + | DCACHE_MAINT_STATUS_ONGOING_PWR_MAINT))) + != 0x0) + ; + + /*Clear Pending all interrupts, if needs to be served, clear after Interrupt serve*/ + DCACHE->SECIRQSCLR = DCACHE_SECIRQSCLR_CLEAR_ALL; + + address = address & ~(DCACHE_MAINT_CTRL_LINES_LOWER_ADDRESS_MASK); + + address = address | (1 << DCACHE_MAINT_CTRL_LINES_TRIG_INVALIDATE); + + DCACHE->MAINT_CTRL_LINES = address; + + /*Wait until the operation is finished*/ + while ((DCACHE->MAINT_STATUS & DCACHE_MAINT_STATUS_ONGOING_MAINT) != 0x0) + ; +} +/*==============================================*/ +/** + * @fn void rsi_d_cache_clean_up_address(uint32_t address) + * @brief This API is used to write back the cache line that contains the specified address to memory, ensuring data consistency for that line + * @param[in] address: The memory address whose cache line needs to be cleaned. + * @return None + */ +void rsi_d_cache_clean_up_address(uint32_t address) +{ + /*Wait until ongoing cache op is done, wait for ONGOING_EN_DIS,ONGOING_MAINT and ONGOING_PWR_MAINT*/ + while ((DCACHE->MAINT_STATUS + & (DCACHE->MAINT_STATUS + & (DCACHE_MAINT_STATUS_ONGOING_EN_DIS | DCACHE_MAINT_STATUS_ONGOING_MAINT + | DCACHE_MAINT_STATUS_ONGOING_PWR_MAINT))) + != 0x0) + ; + + /*Clear Pending all interrupts, if needs to be served, clear after Interrupt serve*/ + DCACHE->SECIRQSCLR = DCACHE_SECIRQSCLR_CLEAR_ALL; + + address = address & ~(DCACHE_MAINT_CTRL_LINES_LOWER_ADDRESS_MASK); + + address = address | (1 << DCACHE_MAINT_CTRL_LINES_TRIG_CLEAN); + DCACHE->MAINT_CTRL_LINES = address; + + /*Wait until the operation is finished*/ + while ((DCACHE->MAINT_STATUS & DCACHE_MAINT_STATUS_ONGOING_MAINT) != 0x0) + ; +} +/*==============================================*/ +/** + * @fn void rsi_d_cache_enable_stats(void) + * @brief This API is used to enable the data cache statistics counter and reset its value to zero + * @return None + */ +void rsi_d_cache_enable_stats(void) +{ + /*Clear Pending all interrupts, if needs to be served, clear after Interrupt serve*/ + DCACHE->SECIRQSCLR = DCACHE_SECIRQSCLR_CLEAR_ALL; + + /*Enable Statistic counter*/ + DCACHE->SECSTATCTRL |= DCACHE_SECSTATCTRL_ENABLE_COUNTER; + + /*Reset Statistic counter*/ + DCACHE->SECSTATCTRL |= DCACHE_SECSTATCTRL_RESET_COUNTER; +} + +/*==============================================*/ +/** + * @fn void rsi_d_cache_disable_stats(void) + * @brief This API is used to disable the data cache statistics counter + * @return None + */ +void rsi_d_cache_disable_stats(void) +{ + /*Clear Pending all interrupts, if needs to be served, clear after Interrupt serve*/ + DCACHE->SECIRQSCLR = DCACHE_SECIRQSCLR_CLEAR_ALL; + + /*Disable Statistic counter*/ + DCACHE->SECSTATCTRL &= ~(DCACHE_SECSTATCTRL_ENABLE_COUNTER); +} +/*==============================================*/ +/** + * @fn void rsi_d_cache_get_stats(int *hit_count, int *miss_count) + * @brief This API is used to retrieve the data cache hit and miss counts. + * @param[in] hit_count: Pointer to store the hit count. + * @param[in] miss_count: Pointer to store the miss count. + * @return 0 on success, -1 if the counters are saturated.. + * + * @note This function returns 0 for both hit and miss counts if the counters are saturated. + */ +int rsi_d_cache_get_stats(int *hit_count, int *miss_count) +{ + + /*Check if the counters are saturated*/ + if (DCACHE->SECIRQSTAT & DCACHE_SECIRQSTAT_NSECURE_CNT_SAT) { + *hit_count = 0x0; + *miss_count = 0x0; + return -1; + } + + *hit_count = DCACHE->SECHIT; + *miss_count = DCACHE->SECMISS; + return 0; +} +/*==============================================*/ +/** + * @fn void rsi_d_cache_clear_stats(void) + * @brief This API is used to reset the data cache statistics counter to zero. + * @return None + */ +void rsi_d_cache_clear_stats(void) +{ + /*Reset Statistic counter*/ + DCACHE->SECSTATCTRL |= DCACHE_SECSTATCTRL_RESET_COUNTER; +} diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_dac.c b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_dac.c index f6cb7c7ad..6f4d6c105 100644 --- a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_dac.c +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_dac.c @@ -42,6 +42,11 @@ extern RSI_UDMA_DESC_T __attribute__((section(".udma_addr1"))) UDMA1_Table[32]; extern RSI_UDMA_HANDLE_T udmaHandle1; #endif +#define DAC_SAMPLE_RATE_32KSPS 32000 +#define DAC_SAMPLE_RATE_80KSPS 80000 +#define DAC_CLK_SRC_32KHZ 32000 +#define DAC_CLK_SRC_32MHZ 32000000 + dac_config_t dac_callback_fun; uint8_t dac_pong_enable_sel = 0; uint32_t devMem[30]; @@ -227,7 +232,7 @@ uint32_t dac_set_clock(uint32_t sampl_rate) uint32_t clk_src_val = 0; uint16_t clk_div_fac = 0; - // Check the AUX-Clock is eable or not + // Check the AUX-Clock is enable or not if (ULPCLK->ULP_AUXADC_CLK_GEN_REG_b.ULP_AUX_CLK_EN_b) { clk_src_val = RSI_CLK_GetBaseClock(ULPSS_AUX); @@ -238,30 +243,27 @@ uint32_t dac_set_clock(uint32_t sampl_rate) } return clk_src_val; } else { - if (sampl_rate <= 32000) { - // Configured ADC clock as 20Khz RC + if (sampl_rate <= DAC_SAMPLE_RATE_32KSPS) { + // Configured DAC clock as 32Khz RC RSI_ULPSS_AuxClkConfig(ULPCLK, ENABLE_STATIC_CLK, ULP_AUX_32KHZ_RC_CLK); - clk_div_fac = (uint16_t)(ceil((2 * 32000) / sampl_rate)); + clk_div_fac = (uint16_t)(ceil((2 * DAC_CLK_SRC_32KHZ) / sampl_rate)); // Configure the DAC division factor for required sampling rate RSI_DAC_ClkDivFactor(AUX_ADC_DAC_COMP, clk_div_fac); return (uint32_t)((clk_div_fac * sampl_rate) / 2); } else { if (M4_ULP_SLP_STATUS_REG & ULP_MODE_SWITCHED_NPSS) { // Program in PS2 state Need to integrate - // Trim Mhz RC clock to 20Mhz - RSI_IPMU_M20rcOsc_TrimEfuse(); // Configured DAC clock as 32Mhz RC RSI_ULPSS_AuxClkConfig(ULPCLK, ENABLE_STATIC_CLK, ULP_AUX_32MHZ_RC_CLK); - clk_div_fac = (uint16_t)ceil((2 * 20000000) / sampl_rate); + clk_div_fac = (uint16_t)ceil((2 * DAC_CLK_SRC_32MHZ) / sampl_rate); // Configure the DAC division factor for required sampling rate RSI_DAC_ClkDivFactor(AUX_ADC_DAC_COMP, clk_div_fac); return (uint32_t)((clk_div_fac * sampl_rate) / 2); } else { - if (sampl_rate > 32000 && sampl_rate < 80000) { - RSI_IPMU_M20rcOsc_TrimEfuse(); + if (sampl_rate > DAC_SAMPLE_RATE_32KSPS && sampl_rate < DAC_SAMPLE_RATE_80KSPS) { // Configured DAC clock as 32Mhz RC RSI_ULPSS_AuxClkConfig(ULPCLK, ENABLE_STATIC_CLK, ULP_AUX_32MHZ_RC_CLK); - clk_div_fac = (uint16_t)ceil((2 * 20000000) / sampl_rate); + clk_div_fac = (uint16_t)ceil((2 * DAC_CLK_SRC_32MHZ) / sampl_rate); if (clk_div_fac > 0x03FF) { clk_div_fac = 0x03FF; } @@ -270,9 +272,9 @@ uint32_t dac_set_clock(uint32_t sampl_rate) return (uint32_t)((clk_div_fac * sampl_rate) / 2); } else { RSI_ULPSS_RefClkConfig(ULPSS_ULP_32MHZ_RC_CLK); - // Configured DAC clock as 40Mhz XTAL - RSI_ULPSS_AuxClkConfig(ULPCLK, ENABLE_STATIC_CLK, ULP_AUX_REF_CLK); - clk_div_fac = (uint16_t)ceil((2 * 40000000) / sampl_rate); + // Configured DAC clock as 32Mhz RC + RSI_ULPSS_AuxClkConfig(ULPCLK, ENABLE_STATIC_CLK, ULP_AUX_32MHZ_RC_CLK); + clk_div_fac = (uint16_t)ceil((2 * DAC_CLK_SRC_32MHZ) / sampl_rate); // Configure the DAC division factor for required sampling rate RSI_DAC_ClkDivFactor(AUX_ADC_DAC_COMP, clk_div_fac); return (uint32_t)((clk_div_fac * sampl_rate) / 2); diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_egpio.c b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_egpio.c index fe59b7c1e..337accce3 100644 --- a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_egpio.c +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_egpio.c @@ -62,21 +62,21 @@ void egpio_set_pin(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, uint8_t val) /*==============================================*/ /** - * @fn boolean_t egpio_get_pin(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin) + * @fn boolean_t egpio_get_pin(const EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin) * @brief This API is used get the GPIO pin status. * @param[in] pEGPIO : Pointer to the EGPIO register instance * @param[in] port : GPIO port number * @param[in] pin : GPIO pin number * @return returns Pin status */ -boolean_t egpio_get_pin(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin) +boolean_t egpio_get_pin(const EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin) { return ((boolean_t)(pEGPIO->PIN_CONFIG[(port * 16) + pin].BIT_LOAD_REG)); } /*==============================================*/ /** - * @fn boolean_t egpio_get_dir(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin) + * @fn boolean_t egpio_get_dir(const EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin) * @brief This API is used to Get the Direction GPIO(Direction of the GPIO pin. * '1' for INPUT,and '0'for OUTPUT) * @param[in] pEGPIO : Pointer to the EGPIO register instance @@ -84,7 +84,7 @@ boolean_t egpio_get_pin(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin) * @param[in] pin : GPIO pin number * @return returns the GPIO direction value */ -boolean_t egpio_get_dir(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin) +boolean_t egpio_get_dir(const EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin) { return pEGPIO->PIN_CONFIG[(port * 16) + pin].GPIO_CONFIG_REG_b.DIRECTION; } @@ -253,13 +253,13 @@ void egpio_set_int_high_level_disable(EGPIO_Type *pEGPIO, uint8_t intCh) /*==============================================*/ /** - * @fn uint8_t egpio_get_int_stat(EGPIO_Type *pEGPIO, uint8_t intCh) + * @fn uint8_t egpio_get_int_stat(const EGPIO_Type *pEGPIO, uint8_t intCh) * @brief This API is used to get the pin interrupt status register * @param[in] pEGPIO : Pointer to the EGPIO register instance * @param[in] intCh : GPIO pin interrupt channel number (0 to 7) * @return returns the interrupt status register */ -uint8_t egpio_get_int_stat(EGPIO_Type *pEGPIO, uint8_t intCh) +uint8_t egpio_get_int_stat(const EGPIO_Type *pEGPIO, uint8_t intCh) { return (uint8_t)(pEGPIO->INTR[intCh].GPIO_INTR_STATUS); } @@ -398,7 +398,7 @@ void egpio_port_masked_load(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val) */ void egpio_set_port(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val) { - pEGPIO->PORT_CONFIG[port].PORT_SET_REG = (val); + pEGPIO->PORT_CONFIG[port].PORT_SET_REG = val; } /*==============================================*/ @@ -413,7 +413,7 @@ void egpio_set_port(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val) */ void egpio_port_load(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val) { - pEGPIO->PORT_CONFIG[port].PORT_LOAD_REG = (val); + pEGPIO->PORT_CONFIG[port].PORT_LOAD_REG = val; } /*==============================================*/ @@ -428,7 +428,7 @@ void egpio_port_load(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val) */ void egpio_word_load(EGPIO_Type *pEGPIO, uint8_t pin, uint16_t val) { - pEGPIO->PIN_CONFIG[pin].WORD_LOAD_REG_b.WORD_LOAD = (val); + pEGPIO->PIN_CONFIG[pin].WORD_LOAD_REG_b.WORD_LOAD = val; } /*==============================================*/ @@ -443,7 +443,7 @@ void egpio_word_load(EGPIO_Type *pEGPIO, uint8_t pin, uint16_t val) */ void egpio_clr_port(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val) { - pEGPIO->PORT_CONFIG[port].PORT_CLEAR_REG = (val); + pEGPIO->PORT_CONFIG[port].PORT_CLEAR_REG = val; } /*==============================================*/ @@ -458,19 +458,19 @@ void egpio_clr_port(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val) */ void egpio_toggle_port(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val) { - pEGPIO->PORT_CONFIG[port].PORT_TOGGLE_REG = (val); + pEGPIO->PORT_CONFIG[port].PORT_TOGGLE_REG = val; } /*==============================================*/ /** - * @fn uint16_t egpio_get_port(EGPIO_Type *pEGPIO, uint8_t port) + * @fn uint16_t egpio_get_port(const EGPIO_Type *pEGPIO, uint8_t port) * @brief This API is used to used to get the EGPIO port value. * Reads the value on GPIO pins irrespective of the pin mode. * @param[in] pEGPIO : Pointer to the EGPIO register instance * @param[in] port : Port number to be read * @return port value */ -uint16_t egpio_get_port(EGPIO_Type *pEGPIO, uint8_t port) +uint16_t egpio_get_port(const EGPIO_Type *pEGPIO, uint8_t port) { return (pEGPIO->PORT_CONFIG[port].PORT_READ_REG & 0XFFFF); } @@ -625,13 +625,13 @@ void egpio_group_int_or(EGPIO_Type *pEGPIO, uint8_t grpInt) /*==============================================*/ /** - * @fn uint32_t egpio_group_int_stat(EGPIO_Type *pEGPIO, uint8_t grpInt) + * @fn uint32_t egpio_group_int_stat(const EGPIO_Type *pEGPIO, uint8_t grpInt) * @brief This API to used to get the group interrupt status * @param[in] pEGPIO : Pointer to the EGPIO register instance * @param[in] grpInt : Group interrupt number * @return returns the group interrupt status register */ -uint32_t egpio_group_int_stat(EGPIO_Type *pEGPIO, uint8_t grpInt) +uint32_t egpio_group_int_stat(const EGPIO_Type *pEGPIO, uint8_t grpInt) { return pEGPIO->GPIO_GRP_INTR[grpInt].GPIO_GRP_INTR_STS; } @@ -673,7 +673,7 @@ void egpio_group_int_wkeup_disable(EGPIO_Type *pEGPIO, uint8_t grpInt) */ void egpio_group_int_clr(EGPIO_Type *pEGPIO, uint8_t grpInt, uint8_t u8ClrFlags) { - pEGPIO->GPIO_GRP_INTR[grpInt].GPIO_GRP_INTR_STS = (u8ClrFlags); + pEGPIO->GPIO_GRP_INTR[grpInt].GPIO_GRP_INTR_STS = u8ClrFlags; } /*==============================================*/ @@ -1036,6 +1036,8 @@ void egpio_ulp_pad_driver_disable_state(uint8_t u8GpioNum, en_ulp_driver_disable reg |= (uint32_t)(disablestate << 14); ULP_PAD_CONFIG_REG_1 = reg; break; + default: + break; } } @@ -1092,6 +1094,8 @@ void egpio_ulp_pad_driver_strength_select(uint8_t u8GpioNum, en_ulp_driver_stren reg |= (uint32_t)(strength << 8); ULP_PAD_CONFIG_REG_1 = reg; break; + default: + break; } } @@ -1146,6 +1150,8 @@ void egpio_ulp_pad_power_on_start_enable(uint8_t u8GpioNum, uint8_t val) reg |= (uint32_t)(val << 10); ULP_PAD_CONFIG_REG_1 = reg; break; + default: + break; } } @@ -1197,6 +1203,8 @@ void egpio_ulp_pad_active_high_schmitt_trigger(uint8_t u8GpioNum, uint8_t val) reg |= (uint32_t)(val << 11); ULP_PAD_CONFIG_REG_1 = reg; break; + default: + break; } } @@ -1249,6 +1257,8 @@ void egpio_ulp_pad_slew_rate_controll(uint8_t u8GpioNum, uint8_t val) reg |= (uint32_t)(val << 13); ULP_PAD_CONFIG_REG_1 = reg; break; + default: + break; } } /** @} */ diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_gspi.c b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_gspi.c index df34f2fc3..cb5a1d734 100644 --- a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_gspi.c +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_gspi.c @@ -38,6 +38,10 @@ #define STATIC_CLOCK_DIV_FACTOR 1 // Static clock divison factor #define HALF_CLOCK_DIV_FACTOR 2 // To make the clock division factor half #define DUMMY_DATA (0x5AA5) +#define MAX_DATA_WIDTH 16 // Maximum data width gspi supports +#define DATA_WIDTH_8 8 // Data width 8 for differentiating DMA Transfers + +typedef uint32_t __attribute__((__may_alias__)) aliased_uint32_t; static uint8_t data_width_in_bytes = 0; // variable to store data width in bytes for current transfer static void GSPI_Convert_Data_Width_To_Bytes(uint16_t data_width); @@ -558,7 +562,7 @@ int32_t GSPI_Control(uint32_t control, // Configure Number of Data Bits data_bits = ((control & ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos); - if ((data_bits == 0) || (data_bits > 16)) { + if (data_bits > MAX_DATA_WIDTH) { return ARM_SPI_ERROR_DATA_BITS; } else { // Update the number of Data Bits @@ -643,7 +647,7 @@ int32_t GSPI_Send(const void *data, control.srcProtCtrl = 0x0; control.dstProtCtrl = 0x0; control.dstInc = DST_INC_NONE; - if ((data_bits <= 8) && (data_bits != 0)) { + if (data_bits <= DATA_WIDTH_8) { //8-bit data frame control.srcSize = SRC_SIZE_8; control.srcInc = SRC_INC_8; @@ -719,11 +723,12 @@ int32_t GSPI_Send(const void *data, // write first index data if (data_width_in_bytes == 1) { - *(volatile uint32_t *)(gspi->reg->GSPI_WRITE_FIFO) = (uint32_t) * (gspi->xfer->tx_buf + gspi->xfer->tx_cnt++); + *(volatile aliased_uint32_t *)(gspi->reg->GSPI_WRITE_FIFO) = + (uint32_t) * (gspi->xfer->tx_buf + gspi->xfer->tx_cnt++); } else if (data_width_in_bytes == 2) { data_16bit = *(gspi->xfer->tx_buf + gspi->xfer->tx_cnt++); data_16bit |= (uint16_t)(*(gspi->xfer->tx_buf + gspi->xfer->tx_cnt++) << 8U); - *(volatile uint32_t *)(gspi->reg->GSPI_WRITE_FIFO) = (uint32_t)data_16bit; + *(volatile aliased_uint32_t *)(gspi->reg->GSPI_WRITE_FIFO) = (uint32_t)data_16bit; } while (gspi->reg->GSPI_STATUS & GSPI_BUSY_F) ; @@ -809,7 +814,7 @@ int32_t GSPI_Receive(void *data, control.srcProtCtrl = 0x0; control.dstProtCtrl = 0x0; control.dstInc = DST_INC_NONE; - if ((data_bits <= 8) && (data_bits != 0)) { + if (data_bits <= DATA_WIDTH_8) { //8-bit data frame control.srcSize = SRC_SIZE_8; control.srcInc = SRC_INC_8; @@ -884,7 +889,7 @@ int32_t GSPI_Receive(void *data, control.srcProtCtrl = 0x0; control.dstProtCtrl = 0x0; control.srcInc = SRC_INC_NONE; - if ((data_bits <= 8) && (data_bits != 0)) { + if (data_bits <= DATA_WIDTH_8) { //8-bit data frame control.srcSize = SRC_SIZE_8; control.dstSize = DST_SIZE_8; @@ -968,9 +973,9 @@ int32_t GSPI_Receive(void *data, // write dummy for reading first index data if (data_width_in_bytes == 1) { - *(volatile uint32_t *)(gspi->reg->GSPI_WRITE_FIFO) = (uint32_t)DUMMY_DATA; + *(volatile aliased_uint32_t *)(gspi->reg->GSPI_WRITE_FIFO) = (uint32_t)DUMMY_DATA; } else if (data_width_in_bytes == 2) { - *(volatile uint32_t *)(gspi->reg->GSPI_WRITE_FIFO) = (uint32_t)DUMMY_DATA; + *(volatile aliased_uint32_t *)(gspi->reg->GSPI_WRITE_FIFO) = (uint32_t)DUMMY_DATA; } while (gspi->reg->GSPI_STATUS & GSPI_BUSY_F) ; @@ -1058,7 +1063,7 @@ int32_t GSPI_Transfer(const void *data_out, control.srcProtCtrl = 0x0; control.dstProtCtrl = 0x0; control.dstInc = DST_INC_NONE; - if ((data_bits <= 8) && (data_bits != 0)) { + if (data_bits <= DATA_WIDTH_8) { //8-bit data frame control.srcSize = SRC_SIZE_8; control.srcInc = SRC_INC_8; @@ -1127,7 +1132,7 @@ int32_t GSPI_Transfer(const void *data_out, control.srcProtCtrl = 0x0; control.dstProtCtrl = 0x0; control.srcInc = SRC_INC_NONE; - if ((data_bits <= 8) && (data_bits != 0)) { + if (data_bits <= DATA_WIDTH_8) { //8-bit data frame control.srcSize = SRC_SIZE_8; control.dstSize = DST_SIZE_8; @@ -1209,11 +1214,12 @@ int32_t GSPI_Transfer(const void *data_out, // write first index data if (data_width_in_bytes == 1) { - *(volatile uint32_t *)(gspi->reg->GSPI_WRITE_FIFO) = (uint32_t) * (gspi->xfer->tx_buf + gspi->xfer->tx_cnt++); + *(volatile aliased_uint32_t *)(gspi->reg->GSPI_WRITE_FIFO) = + (uint32_t) * (gspi->xfer->tx_buf + gspi->xfer->tx_cnt++); } else if (data_width_in_bytes == 2) { data_16bit = *(gspi->xfer->tx_buf + gspi->xfer->tx_cnt++); data_16bit |= (uint16_t)(*(gspi->xfer->tx_buf + gspi->xfer->tx_cnt++) << 8U); - *(volatile uint32_t *)(gspi->reg->GSPI_WRITE_FIFO) = (uint32_t)data_16bit; + *(volatile aliased_uint32_t *)(gspi->reg->GSPI_WRITE_FIFO) = (uint32_t)data_16bit; } while (gspi->reg->GSPI_STATUS & GSPI_BUSY_F) ; @@ -1313,11 +1319,11 @@ void GSPI_IRQHandler(const GSPI_RESOURCES *gspi) // read the next data available in the FIFO into rx_buf if (data_width_in_bytes == 1) { //8bit - data_8bit = *(volatile uint32_t *)(gspi->reg->GSPI_READ_FIFO); + data_8bit = *(volatile aliased_uint32_t *)(gspi->reg->GSPI_READ_FIFO); *(gspi->xfer->rx_buf + gspi->xfer->rx_cnt++) = data_8bit; } else if (data_width_in_bytes == 2) { //16bit - data_16bit = *(volatile uint32_t *)(gspi->reg->GSPI_READ_FIFO); + data_16bit = *(volatile aliased_uint32_t *)(gspi->reg->GSPI_READ_FIFO); *(gspi->xfer->rx_buf + gspi->xfer->rx_cnt++) = (uint8_t)data_16bit; *(gspi->xfer->rx_buf + gspi->xfer->rx_cnt++) = (uint8_t)(data_16bit >> 8U); } @@ -1330,16 +1336,16 @@ void GSPI_IRQHandler(const GSPI_RESOURCES *gspi) event |= ARM_SPI_EVENT_TRANSFER_COMPLETE; } else if (!(gspi->xfer->tx_buf)) { // Only meant to write dummy data in case of half-duplex mode "Receive-only" if (data_width_in_bytes == 1) { - *(volatile uint32_t *)(gspi->reg->GSPI_WRITE_FIFO) = (uint32_t)DUMMY_DATA; + *(volatile aliased_uint32_t *)(gspi->reg->GSPI_WRITE_FIFO) = (uint32_t)DUMMY_DATA; } else if (data_width_in_bytes == 2) { - *(volatile uint32_t *)(gspi->reg->GSPI_WRITE_FIFO) = (uint32_t)DUMMY_DATA; + *(volatile aliased_uint32_t *)(gspi->reg->GSPI_WRITE_FIFO) = (uint32_t)DUMMY_DATA; } } } } else { // Unanticipated receive, flush the fifo uint32_t flush_data; - flush_data = *(volatile uint32_t *)(gspi->reg->GSPI_READ_FIFO); + flush_data = *(volatile aliased_uint32_t *)(gspi->reg->GSPI_READ_FIFO); (void)flush_data; } } @@ -1349,12 +1355,12 @@ void GSPI_IRQHandler(const GSPI_RESOURCES *gspi) // verify if there are still some bytes to transmit if (gspi->xfer->tx_cnt < gspi->xfer->num) { if (data_width_in_bytes == 1) { - data_8bit = *(gspi->xfer->tx_buf + gspi->xfer->tx_cnt++); - *(volatile uint32_t *)(gspi->reg->GSPI_WRITE_FIFO) = (uint32_t)data_8bit; + data_8bit = *(gspi->xfer->tx_buf + gspi->xfer->tx_cnt++); + *(volatile aliased_uint32_t *)(gspi->reg->GSPI_WRITE_FIFO) = (uint32_t)data_8bit; } else if (data_width_in_bytes == 2) { data_16bit = *(gspi->xfer->tx_buf + gspi->xfer->tx_cnt++); data_16bit |= (uint16_t)(*(gspi->xfer->tx_buf + gspi->xfer->tx_cnt++) << 8); - *(volatile uint32_t *)(gspi->reg->GSPI_WRITE_FIFO) = (uint32_t)data_16bit; + *(volatile aliased_uint32_t *)(gspi->reg->GSPI_WRITE_FIFO) = (uint32_t)data_16bit; } while (gspi->reg->GSPI_STATUS_b.GSPI_BUSY) ; diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_i2s.c b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_i2s.c index fe18ff56b..13b767601 100644 --- a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_i2s.c +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_i2s.c @@ -887,11 +887,10 @@ int32_t I2S_Send(const void *data, } if (i2s->reg == I2S0) { chnl_cfg.channelPrioHigh = UDMA0_CHNL_PRIO_LVL; - chnl_cfg.dmaCh = RTE_I2S0_CHNL_UDMA_TX_CH; } else { chnl_cfg.channelPrioHigh = UDMA1_CHNL_PRIO_LVL; - chnl_cfg.dmaCh = RTE_I2S1_CHNL_UDMA_TX_CH; } + chnl_cfg.dmaCh = i2s->dma_tx->channel; chnl_cfg.periAck = 0; chnl_cfg.periphReq = 0; chnl_cfg.reqMask = 0; @@ -1032,11 +1031,10 @@ int32_t I2S_Receive(void *data, } if (i2s->reg == I2S0) { chnl_cfg.channelPrioHigh = UDMA0_CHNL_PRIO_LVL; - chnl_cfg.dmaCh = RTE_I2S0_CHNL_UDMA_RX_CH; } else { chnl_cfg.channelPrioHigh = UDMA1_CHNL_PRIO_LVL; - chnl_cfg.dmaCh = RTE_I2S1_CHNL_UDMA_RX_CH; } + chnl_cfg.dmaCh = i2s->dma_rx->channel; chnl_cfg.periAck = 0; chnl_cfg.periphReq = 0; chnl_cfg.reqMask = 0; diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_spi.c b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_spi.c index 476d3b237..23fc547f7 100644 --- a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_spi.c +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_spi.c @@ -26,6 +26,7 @@ #include "SPI.h" #include "rsi_rom_egpio.h" #include "rsi_rom_ulpss_clk.h" +#include "rsi_power_save.h" #ifdef SL_SI91X_SSI_DMA #include "sl_si91x_dma.h" #include "rsi_spi.h" @@ -42,6 +43,9 @@ #define BYTES_FOR_16_DATA_WIDTH 2 // Number of bytes for 16 bit data frame #define BYTES_FOR_32_DATA_WIDTH 4 // Number of bytes for 32 bit data frame #define DUMMY_DATA 0xA5 // Dummy data to be written in receive only mode by master +/*When use the ULP Master instance with DMA enabled, it is advisable ulp memory used for low power modes */ +#define ULP_SSI_DUMMY_DATA \ + (ULP_SRAM_START_ADDR + (1 * 800)) // Dummy data to be written in receive only mode by master while in PS2 state #if (defined(SSI_ULP_MASTER_RX_DMA_Instance) && (SSI_ULP_MASTER_RX_DMA_Instance == 1)) #define ULP_SSI_MASTER_BANK_OFFSET 0x800 // ULP Memory bank offset value. #define ULP_SSI_MASTER_BUF_MEMORY (ULP_SRAM_START_ADDR + (1 * ULP_SSI_MASTER_BANK_OFFSET)) @@ -931,6 +935,7 @@ ARM_SPI_STATUS SPI_GetStatus(const SPI_RESOURCES *spi) */ void SPI_IRQHandler(const SPI_RESOURCES *spi) { + typedef volatile uint32_t vuint32_t __attribute__((may_alias)); uint32_t data = 0U; uint32_t event; uint32_t isr; @@ -967,12 +972,12 @@ void SPI_IRQHandler(const SPI_RESOURCES *spi) *(spi->xfer->rx_buf + spi->xfer->rx_cnt++) = (uint8_t)(data); } else if (data_width_in_bytes == 2) { // For data width 8-16 - data = *(volatile uint32_t *)(&spi->reg->DR); + data = *(vuint32_t *)(&spi->reg->DR); *(spi->xfer->rx_buf + spi->xfer->rx_cnt++) = (uint8_t)(data); *(spi->xfer->rx_buf + spi->xfer->rx_cnt++) = (uint8_t)(data >> 8); } else if (data_width_in_bytes == 4) { // For data width 16-32 - data = *(volatile uint32_t *)(&spi->reg->DR); + data = *(vuint32_t *)(&spi->reg->DR); *(spi->xfer->rx_buf + spi->xfer->rx_cnt++) = (uint8_t)(data); *(spi->xfer->rx_buf + spi->xfer->rx_cnt++) = (uint8_t)(data >> 8); *(spi->xfer->rx_buf + spi->xfer->rx_cnt++) = (uint8_t)(data >> 16); @@ -990,8 +995,8 @@ void SPI_IRQHandler(const SPI_RESOURCES *spi) if (((spi->instance_mode == SPI_MASTER_MODE) || (spi->instance_mode == SPI_ULP_MASTER_MODE)) && (spi->xfer->tx_buf == NULL)) { // If master mode or ulp master mode and tx buffer is null means receive only conditon where dummy byte needs to be generated - *(volatile uint32_t *)(&spi->reg->DR) = DUMMY_DATA; // dummy data - // Waiting till the busy flag is cleared + *(vuint32_t *)(&spi->reg->DR) = DUMMY_DATA; // dummy data + // Waiting till the busy flag is cleared while (spi->reg->SR & BIT(0)) ; } @@ -1015,14 +1020,14 @@ void SPI_IRQHandler(const SPI_RESOURCES *spi) // For data width 8-16 data = *(spi->xfer->tx_buf + spi->xfer->tx_cnt++); data |= *(spi->xfer->tx_buf + spi->xfer->tx_cnt++) << 8; - *(volatile uint32_t *)(&spi->reg->DR) = (uint16_t)data; + *(vuint32_t *)(&spi->reg->DR) = (uint16_t)data; } else if (data_width_in_bytes == 4) { // For data width 16-32 data = *(spi->xfer->tx_buf + spi->xfer->tx_cnt++); data |= *(spi->xfer->tx_buf + spi->xfer->tx_cnt++) << 8; data |= *(spi->xfer->tx_buf + spi->xfer->tx_cnt++) << 16; data |= *(spi->xfer->tx_buf + spi->xfer->tx_cnt++) << 24; - *(volatile uint32_t *)(&spi->reg->DR) = data; + *(vuint32_t *)(&spi->reg->DR) = data; } // Waiting till the busy flag is cleared if ((spi->instance_mode == SPI_MASTER_MODE) || (spi->instance_mode == SPI_ULP_MASTER_MODE)) { @@ -1048,6 +1053,20 @@ void SPI_IRQHandler(const SPI_RESOURCES *spi) // Send event if (event && spi->info->cb_event) { + uint8_t ssi_instance = 0; + // Validate the SSI instance that triggered this event + if (spi->reg == SSI0) { + // Assigning instance number to the callback variable + ssi_instance = SSI_MASTER_INSTANCE; + } else if (spi->reg == SSISlave) { + // Assigning instance number to the callback variable + ssi_instance = SSI_SLAVE_INSTANCE; + } else if (spi->reg == SSI2) { + // Assigning instance number to the callback variable + ssi_instance = SSI_ULP_MASTER_INSTANCE; + } + // Appending the instance value in the callback event variable + event |= (ssi_instance << SSI_INSTANCE_BIT); spi->info->cb_event(event); if (spi->info->status.busy) { spi->info->status.busy = 0U; @@ -1407,7 +1426,11 @@ int32_t SPI_Receive(void *data, spi_tx_callback.transfer_complete_cb = ssi_transfer_complete_callback; spi_tx_callback.error_cb = ssi_error_callback; //Initialize sl_dma transfer structure - dma_transfer_tx.src_addr = (uint32_t *)((uint32_t) & (dummy_data)); + if (RSI_PS_IsPS2State()) { + dma_transfer_tx.src_addr = (uint32_t *)((uint32_t)(ULP_SSI_DUMMY_DATA)); + } else { + dma_transfer_tx.src_addr = (uint32_t *)((uint32_t) & (dummy_data)); + } dma_transfer_tx.dest_addr = (uint32_t *)((uint32_t) & (spi->reg->DR)); dma_transfer_tx.src_inc = control.srcInc; dma_transfer_tx.dst_inc = control.dstInc; @@ -1494,7 +1517,20 @@ int32_t SPI_Receive(void *data, void SPI_UDMA_Tx_Event(uint32_t event, uint8_t dmaCh, SPI_RESOURCES *spi) { (void)dmaCh; - uint32_t status_reg = 0; + uint32_t status_reg = 0; + uint32_t ssi_event = 0; + uint8_t ssi_instance = 0; + // Validate the SSI instance that triggered this event + if (spi->reg == SSI0) { + // Assigning instance number to the callback variable + ssi_instance = SSI_MASTER_INSTANCE; + } else if (spi->reg == SSISlave) { + // Assigning instance number to the callback variable + ssi_instance = SSI_SLAVE_INSTANCE; + } else if (spi->reg == SSI2) { + // Assigning instance number to the callback variable + ssi_instance = SSI_ULP_MASTER_INSTANCE; + } switch (event) { case UDMA_EVENT_XFER_DONE: // Update TX buffer info @@ -1506,8 +1542,10 @@ void SPI_UDMA_Tx_Event(uint32_t event, uint8_t dmaCh, SPI_RESOURCES *spi) status_reg = spi->reg->SR; spi->info->status.busy = 0U; (void)status_reg; + // Appending the instance value in the callback event variable + ssi_event = ARM_SPI_EVENT_TRANSFER_COMPLETE | (ssi_instance << SSI_INSTANCE_BIT); if ((spi->info->cb_event != NULL) && (spi->xfer->rx_buf == NULL)) { - spi->info->cb_event(ARM_SPI_EVENT_TRANSFER_COMPLETE); + spi->info->cb_event(ssi_event); } break; case UDMA_EVENT_ERROR: @@ -1525,7 +1563,20 @@ void SPI_UDMA_Tx_Event(uint32_t event, uint8_t dmaCh, SPI_RESOURCES *spi) void SPI_UDMA_Rx_Event(uint32_t event, uint8_t dmaCh, SPI_RESOURCES *spi) { (void)dmaCh; - uint32_t status_reg = 0; + uint32_t status_reg = 0; + uint32_t ssi_event = 0; + uint8_t ssi_instance = 0; + // Validate the SSI instance that triggered this event + if (spi->reg == SSI0) { + // Assigning instance number to the callback variable + ssi_instance = SSI_MASTER_INSTANCE; + } else if (spi->reg == SSISlave) { + // Assigning instance number to the callback variable + ssi_instance = SSI_SLAVE_INSTANCE; + } else if (spi->reg == SSI2) { + // Assigning instance number to the callback variable + ssi_instance = SSI_ULP_MASTER_INSTANCE; + } switch (event) { case UDMA_EVENT_XFER_DONE: spi->xfer->rx_cnt = spi->xfer->num; @@ -1537,12 +1588,14 @@ void SPI_UDMA_Rx_Event(uint32_t event, uint8_t dmaCh, SPI_RESOURCES *spi) // Clear error status by reading the register status_reg = spi->reg->SR; (void)status_reg; + // Appending the instance value in the callback event variable + ssi_event = ARM_SPI_EVENT_TRANSFER_COMPLETE | (ssi_instance << SSI_INSTANCE_BIT); break; case UDMA_EVENT_ERROR: break; } if (spi->info->cb_event != NULL) { - spi->info->cb_event(ARM_SPI_EVENT_TRANSFER_COMPLETE); + spi->info->cb_event(ssi_event); } } diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_udma.c b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_udma.c index b21c1d918..c5f4db500 100644 --- a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_udma.c +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_udma.c @@ -84,8 +84,8 @@ RSI_UDMA_HANDLE_T udma_init(void *mem, const RSI_UDMA_INIT_T *pInit) pDrv->base = (RSI_UDMA_T *)pInit->base; pDrv->sramBase = (RSI_UDMA_DESC_T *)pInit->sramBase; - if (((uint32_t)pInit->sramBase & ((uint32_t)(~0x3FF))) == (uint32_t)pInit->sramBase) { - pDrv->base->CTRL_BASE_PTR = (uint32_t)pInit->sramBase; + if ((pInit->sramBase & ((uint32_t)(~0x3FF))) == pInit->sramBase) { + pDrv->base->CTRL_BASE_PTR = pInit->sramBase; } else { return (RSI_UDMA_HANDLE_T)ERROR_UDMA_CTRL_BASE_INVALID; } @@ -100,7 +100,7 @@ RSI_UDMA_HANDLE_T udma_init(void *mem, const RSI_UDMA_INIT_T *pInit) * @param[in] pCfg : Pointer to channel configuration structure * @return RSI_OK - if success */ -rsi_error_t RSI_UDMA_ChannelControlsDisable(RSI_UDMA_HANDLE_T pHandle, RSI_UDMA_CHA_CFG_T *pCfg) +rsi_error_t RSI_UDMA_ChannelControlsDisable(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg) { RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle; @@ -128,7 +128,7 @@ rsi_error_t RSI_UDMA_ChannelControlsDisable(RSI_UDMA_HANDLE_T pHandle, RSI_UDMA_ } /*==============================================*/ /** - * @fn rsi_error_t udma_setup_channel_transfer(RSI_UDMA_HANDLE_T pHandle, RSI_UDMA_CHA_CFG_T *pCfg, RSI_UDMA_CHA_CONFIG_DATA_T vsUdmaChaConfigData, void *pSrcAddr, void *pDstAddr) + * @fn rsi_error_t udma_setup_channel_transfer(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg, RSI_UDMA_CHA_CONFIG_DATA_T vsUdmaChaConfigData, void *pSrcAddr, void *pDstAddr) * @brief This API is used to control parameters for a UDMA channel control structure * @param[in] pHandle : Pointer to driver context handle * @param[in] pCfg : Pointer to channel configuration structure @@ -140,10 +140,10 @@ rsi_error_t RSI_UDMA_ChannelControlsDisable(RSI_UDMA_HANDLE_T pHandle, RSI_UDMA_ * - RSI_OK - if success */ rsi_error_t udma_setup_channel_transfer(RSI_UDMA_HANDLE_T pHandle, - RSI_UDMA_CHA_CFG_T *pCfg, + const RSI_UDMA_CHA_CFG_T *pCfg, RSI_UDMA_CHA_CONFIG_DATA_T vsUdmaChaConfigData, void *pSrcAddr, - void *pDstAddr) + volatile void *pDstAddr) { uint32_t channelTableIndex = 0; uint32_t srcInc = 0; @@ -255,10 +255,10 @@ rsi_error_t udma_setup_channel_transfer(RSI_UDMA_HANDLE_T pHandle, if (dstInc != UDMA_DST_INC_NONE) { if ((vsUdmaChaConfigData.transferType == UDMA_MODE_MEM_SCATTER_GATHER) || (vsUdmaChaConfigData.transferType == UDMA_MODE_PER_SCATTER_GATHER)) { - pDstAddr = (void *)&pUDMAChaCtrlDataStruct[channelTableIndex | UDMA_ALT_SELECT].Spare; + pDstAddr = (volatile void *)&pUDMAChaCtrlDataStruct[channelTableIndex | UDMA_ALT_SELECT].Spare; } else { length = (uint16_t)((vsUdmaChaConfigData.totalNumOfDMATrans + 1) << dstInc); - pDstAddr = (void *)((uint32_t)pDstAddr + length - 1); + pDstAddr = (volatile void *)((volatile uint8_t *)pDstAddr + length - 1); } } @@ -334,7 +334,7 @@ rsi_error_t udma_set_channel_scatter_gather_transfer(RSI_UDMA_HANDLE_T pHandle, /*==============================================*/ /** * @fn uint32_t udma_get_channel_transfer_length(RSI_UDMA_HANDLE_T pHandle, - * RSI_UDMA_CHA_CFG_T *pCfg, + * const RSI_UDMA_CHA_CFG_T *pCfg, * RSI_UDMA_CHA_CONFIG_DATA_T vsUDMAChaConfigData) * @brief This API Gets the current transfer size for a UDMA channel control structure * @param[in] pHandle : Pointer to driver context handle @@ -343,15 +343,15 @@ rsi_error_t udma_set_channel_scatter_gather_transfer(RSI_UDMA_HANDLE_T pHandle, * @return RSI_OK - if success */ uint32_t udma_get_channel_transfer_length(RSI_UDMA_HANDLE_T pHandle, - RSI_UDMA_CHA_CFG_T *pCfg, + const RSI_UDMA_CHA_CFG_T *pCfg, RSI_UDMA_CHA_CONFIG_DATA_T vsUDMAChaConfigData) { UNUSED_PARAMETER(vsUDMAChaConfigData); uint32_t channelTableIndex = 0; uint32_t transferSize = 0; - RSI_UDMA_DESC_T *pUDMAChaCtrlDataStruct; + const RSI_UDMA_DESC_T *pUDMAChaCtrlDataStruct; - RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle; + const RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle; /* checks Alternate Data structure */ if (pCfg->altStruct == 1) { @@ -376,19 +376,19 @@ uint32_t udma_get_channel_transfer_length(RSI_UDMA_HANDLE_T pHandle, /*==============================================*/ /** - * @fn uint32_t udma_get_channel_transfer_mode(RSI_UDMA_HANDLE_T pHandle, RSI_UDMA_CHA_CFG_T *pCfg) + * @fn uint32_t udma_get_channel_transfer_mode(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg) * @brief This API Gets the current transfer size for a UDMA channel control structure * @param[in] pHandle : Pointer to driver context handle * @param[in] pCfg : Pointer to channel configuration structure * @return RSI_OK - if success */ -uint32_t udma_get_channel_transfer_mode(RSI_UDMA_HANDLE_T pHandle, RSI_UDMA_CHA_CFG_T *pCfg) +uint32_t udma_get_channel_transfer_mode(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg) { uint32_t channelTableIndex = 0; uint32_t transferMode = 0; - RSI_UDMA_DESC_T *pUDMAChaCtrlDataStruct; + const RSI_UDMA_DESC_T *pUDMAChaCtrlDataStruct; - RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle; + const RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle; // checks Alternate Data structure if (pCfg->altStruct == 1) { @@ -407,7 +407,7 @@ uint32_t udma_get_channel_transfer_mode(RSI_UDMA_HANDLE_T pHandle, RSI_UDMA_CHA_ // Get the transfer mode from the control memory data transferMode = pUDMAChaCtrlDataStruct[channelTableIndex].vsUDMAChaConfigData1.transferType; - return (transferMode); + return transferMode; } return RSI_OK; } @@ -448,13 +448,13 @@ rsi_error_t udma_interrupt_enable(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh) /*==============================================*/ /** - * @fn void RSI_UDMA_AckEnable(RSI_UDMA_HANDLE_T pHandle, uint32_t peripheral) + * @fn void RSI_UDMA_AckEnable(const void *pHandle, uint32_t peripheral) * @brief This API is used to enable ACK from DMA to the peripheral while transfers . * @param[in] pHandle : Pointer to driver context handle * @param[in] peripheral : ACK enable for required peripheral * @return none */ -void RSI_UDMA_AckEnable(RSI_UDMA_HANDLE_T pHandle, uint32_t peripheral) +void RSI_UDMA_AckEnable(const void *pHandle, uint32_t peripheral) { UNUSED_PARAMETER(pHandle); switch (peripheral) { @@ -485,6 +485,8 @@ void RSI_UDMA_AckEnable(RSI_UDMA_HANDLE_T pHandle, uint32_t peripheral) case I2C_ACK: PERIPHERAL_UDMA_DMA_SEL |= SET_BIT(7); break; + default: + break; } } @@ -496,7 +498,7 @@ void RSI_UDMA_AckEnable(RSI_UDMA_HANDLE_T pHandle, uint32_t peripheral) * @param[in] pCfg : Pointer to channel configuration structure * @return RSI_OK - if success */ -rsi_error_t udma_setup_channel(RSI_UDMA_HANDLE_T pHandle, RSI_UDMA_CHA_CFG_T *pCfg) +rsi_error_t udma_setup_channel(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg) { RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle; @@ -538,13 +540,13 @@ rsi_error_t udma_setup_channel(RSI_UDMA_HANDLE_T pHandle, RSI_UDMA_CHA_CFG_T *pC /*==============================================*/ /** - * @fn void udma_deInit(RSI_UDMA_HANDLE_T pHandle, RSI_UDMA_CHA_CFG_T *pCfg) + * @fn void udma_deInit(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg) * @brief This API is used to initialize driver context parameters * @param[in] pHandle : Pointer to driver context handle * @param[in] pCfg : Pointer to DMA channel configuration structure * @return none */ -void udma_deInit(RSI_UDMA_HANDLE_T pHandle, RSI_UDMA_CHA_CFG_T *pCfg) +void udma_deInit(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg) { RSI_UDMA_InterruptClear(pHandle, ((uint8_t)(pCfg->dmaCh))); @@ -567,7 +569,7 @@ void udma_interrupt_handler(RSI_UDMA_HANDLE_T pHandle) { uint32_t intr = 0; RSI_UDMA_DESC_T pDesc; - RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle; + const RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle; if (pDrv->udmaCompCB != NULL) { intr = pDrv->base->UDMA_DONE_STATUS_REG; @@ -702,24 +704,10 @@ void udma_interrupt_handler(RSI_UDMA_HANDLE_T pHandle) } } } else { + return; } } -/*ROM API Structure - -const ROM_UDMA_API_T udma_api = { - &udma_init, - &udma_get_channel_transfer_mode, - &udma_setup_channel_transfer, - &udma_set_channel_scatter_gather_transfer, - &udma_get_channel_transfer_length, - &udma_setup_channel, - &udma_deInit, - &udma_interrupt_handler, - &udma_interrupt_enable, -}; - -*/ #ifdef __cplusplus } #endif diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_udma_wrapper.c b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_udma_wrapper.c index cb1ddd1ea..a34ecdba7 100644 --- a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_udma_wrapper.c +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_udma_wrapper.c @@ -35,7 +35,7 @@ extern "C" { */ /*==============================================*/ /** - * @fn RSI_UDMA_HANDLE_T uDMAx_Initialize(UDMA_RESOURCES *udma, + * @fn RSI_UDMA_HANDLE_T uDMAx_Initialize(const UDMA_RESOURCES *udma, * RSI_UDMA_DESC_T *UDMA_Table, * RSI_UDMA_HANDLE_T udmaHandle, * uint32_t *mem) @@ -47,12 +47,13 @@ extern "C" { * @return Zero - if success * Non zero - if fails */ -RSI_UDMA_HANDLE_T uDMAx_Initialize(UDMA_RESOURCES *udma, +RSI_UDMA_HANDLE_T uDMAx_Initialize(const UDMA_RESOURCES *udma, RSI_UDMA_DESC_T *UDMA_Table, RSI_UDMA_HANDLE_T udmaHandle, uint32_t *mem) { - RSI_UDMA_INIT_T udmaInit0 = { 0 }, udmaInit1 = { 0 }; + RSI_UDMA_INIT_T udmaInit0 = { 0 }; + RSI_UDMA_INIT_T udmaInit1 = { 0 }; if (udma->reg == UDMA0) { #if defined(SLI_SI917) @@ -69,7 +70,7 @@ RSI_UDMA_HANDLE_T uDMAx_Initialize(UDMA_RESOURCES *udma, if (udma->reg == UDMA0) { udmaInit0.base = (uint32_t)UDMA0; udmaInit0.sramBase = (uint32_t)UDMA_Table; - udmaInit0.pUserData = (void *)NULL; + udmaInit0.pUserData = NULL; udmaHandle = RSI_UDMA_Init(mem, &udmaInit0); //doubt in mem if (udmaHandle == NULL) { return 0; @@ -87,7 +88,7 @@ RSI_UDMA_HANDLE_T uDMAx_Initialize(UDMA_RESOURCES *udma, } else { udmaInit1.sramBase = (uint32_t)UDMA_Table; } - udmaInit1.pUserData = (void *)NULL; + udmaInit1.pUserData = NULL; udmaHandle = RSI_UDMA_Init(mem, &udmaInit1); if (udmaHandle == NULL) { return 0; @@ -102,13 +103,13 @@ RSI_UDMA_HANDLE_T uDMAx_Initialize(UDMA_RESOURCES *udma, /*==============================================*/ /** - * @fn int32_t uDMAx_Uninitialize(UDMA_RESOURCES *udma) + * @fn int32_t uDMAx_Uninitialize(const UDMA_RESOURCES *udma) * @brief This API is used to De-initialize UDMA peripheral * @param[in] udma : Pointer to UDMA resources * @return Zero - if success * Non zero - if fails */ -int32_t uDMAx_Uninitialize(UDMA_RESOURCES *udma) +int32_t uDMAx_Uninitialize(const UDMA_RESOURCES *udma) { // Disable DMA clock,Disable and Clear DMA IRQ if (udma->reg == UDMA0) { @@ -125,13 +126,13 @@ int32_t uDMAx_Uninitialize(UDMA_RESOURCES *udma) /*==============================================*/ /** - * @fn int32_t uDMAx_ChannelConfigure(UDMA_RESOURCES *udma, + * @fn int32_t uDMAx_ChannelConfigure(const UDMA_RESOURCES *udma, * uint8_t ch, * uint32_t src_addr, * uint32_t dest_addr, * uint32_t size, * RSI_UDMA_CHA_CONFIG_DATA_T control, - * RSI_UDMA_CHA_CFG_T *config, + * const RSI_UDMA_CHA_CFG_T *config, * UDMA_SignalEvent_t cb_event, * UDMA_Channel_Info *chnl_info, * RSI_UDMA_HANDLE_T udmaHandle) @@ -149,13 +150,13 @@ int32_t uDMAx_Uninitialize(UDMA_RESOURCES *udma) * @return Zero - if success * Non zero - if fails */ -int32_t uDMAx_ChannelConfigure(UDMA_RESOURCES *udma, +int32_t uDMAx_ChannelConfigure(const UDMA_RESOURCES *udma, uint8_t ch, uint32_t src_addr, uint32_t dest_addr, uint32_t size, RSI_UDMA_CHA_CONFIG_DATA_T control, - RSI_UDMA_CHA_CFG_T *config, + const RSI_UDMA_CHA_CFG_T *config, UDMA_SignalEvent_t cb_event, UDMA_Channel_Info *chnl_info, RSI_UDMA_HANDLE_T udmaHandle) @@ -164,15 +165,13 @@ int32_t uDMAx_ChannelConfigure(UDMA_RESOURCES *udma, // as I2C and SSI data register does not belong to ULP memory section #if !(defined SL_SI91X_I2C_DMA) && !(defined SL_SI91X_SSI_DMA) && !(defined DAC_FIFO_MODE_EN) if (M4_ULP_SLP_STATUS_REG & ULP_MODE_SWITCHED_NPSS) { //PS2 state - if (control.dstInc == UDMA_DST_INC_NONE) { - if (!((src_addr >= ULP_SRAM_START_ADDR) && (src_addr <= ULP_SRAM_END_ADDR))) { - return ERROR_UDMA_SRC_ADDR; - } + if ((control.dstInc == UDMA_DST_INC_NONE) + && (!((src_addr >= ULP_SRAM_START_ADDR) && (src_addr <= ULP_SRAM_END_ADDR)))) { + return ERROR_UDMA_SRC_ADDR; } - if (control.srcInc == UDMA_SRC_INC_NONE) { - if (!((dest_addr >= ULP_SRAM_START_ADDR) && (dest_addr <= ULP_SRAM_END_ADDR))) { - return ERROR_UDMA_DST_ADDR; - } + if ((control.srcInc == UDMA_SRC_INC_NONE) + && (!((dest_addr >= ULP_SRAM_START_ADDR) && (dest_addr <= ULP_SRAM_END_ADDR)))) { + return ERROR_UDMA_DST_ADDR; } } #endif @@ -185,14 +184,10 @@ int32_t uDMAx_ChannelConfigure(UDMA_RESOURCES *udma, RSI_UDMA_ErrorStatusClear(udmaHandle); RSI_UDMA_SetupChannel(udmaHandle, config); - RSI_UDMA_SetupChannelTransfer(udmaHandle, - (RSI_UDMA_CHA_CFG_T *)config, - control, - (void *)src_addr, - (void *)dest_addr); + RSI_UDMA_SetupChannelTransfer(udmaHandle, config, control, (void *)src_addr, (void *)dest_addr); // Save channel information - chnl_info[ch].SrcAddr = (src_addr); - chnl_info[ch].DestAddr = (dest_addr); + chnl_info[ch].SrcAddr = src_addr; + chnl_info[ch].DestAddr = dest_addr; chnl_info[ch].Size = size; chnl_info[ch].Cnt = control.totalNumOfDMATrans + 1; } @@ -201,7 +196,7 @@ int32_t uDMAx_ChannelConfigure(UDMA_RESOURCES *udma, /*==============================================*/ /** - * @fn int32_t uDMAx_ChannelEnable(uint8_t ch, UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle) + * @fn int32_t uDMAx_ChannelEnable(uint8_t ch, const UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle) * @brief This API is used to Enable UDMA channel * @param[in] ch : Channel number (0..7) * @param[in] udma : Pointer to UDMA resources @@ -209,7 +204,7 @@ int32_t uDMAx_ChannelConfigure(UDMA_RESOURCES *udma, * @return Zero - if success * Non zero - if fails */ -int32_t uDMAx_ChannelEnable(uint8_t ch, UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle) +int32_t uDMAx_ChannelEnable(uint8_t ch, const UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle) { UNUSED_PARAMETER(udma); RSI_UDMA_ChannelEnable(udmaHandle, ch); @@ -218,14 +213,14 @@ int32_t uDMAx_ChannelEnable(uint8_t ch, UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T /*==============================================*/ /** - * @fn int32_t uDMAx_DMAEnable(UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle) + * @fn int32_t uDMAx_DMAEnable(const UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle) * @brief This API is used to Enable UDMA DMA * @param[in] udma : Pointer to UDMA resources * @param[in] udmaHandle: udma Handler * @return Zero - if success * Non zero - if fails */ -int32_t uDMAx_DMAEnable(UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle) +int32_t uDMAx_DMAEnable(const UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle) { UNUSED_PARAMETER(udma); RSI_UDMA_UDMAEnable(udmaHandle); @@ -234,7 +229,7 @@ int32_t uDMAx_DMAEnable(UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle) /*==============================================*/ /** - * @fn int32_t uDMAx_ChannelDisable(uint8_t ch, UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle) + * @fn int32_t uDMAx_ChannelDisable(uint8_t ch, const UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle) * @brief This API is used to Disable UDMA channel * @param[in] ch : Channel number (0..7) * @param[in] udma : Pointer to UDMA resources @@ -242,7 +237,7 @@ int32_t uDMAx_DMAEnable(UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle) * @return Zero - if success * Non zero - if fails */ -int32_t uDMAx_ChannelDisable(uint8_t ch, UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle) +int32_t uDMAx_ChannelDisable(uint8_t ch, const UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle) { UNUSED_PARAMETER(udma); RSI_UDMA_ChannelDisable(udmaHandle, ch); @@ -254,7 +249,7 @@ int32_t uDMAx_ChannelDisable(uint8_t ch, UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T * @fn uint32_t uDMAx_ChannelGetCount(uint8_t ch, * RSI_UDMA_CHA_CONFIG_DATA_T control, * RSI_UDMA_CHA_CFG_T config, - * UDMA_RESOURCES *udma, + * const UDMA_RESOURCES *udma, * RSI_UDMA_HANDLE_T udmaHandle) * @brief This API Gets the current transfer size for a UDMA channel control structure * @param[in] ch : Channel number @@ -267,7 +262,7 @@ int32_t uDMAx_ChannelDisable(uint8_t ch, UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T uint32_t uDMAx_ChannelGetCount(uint8_t ch, RSI_UDMA_CHA_CONFIG_DATA_T control, RSI_UDMA_CHA_CFG_T config, - UDMA_RESOURCES *udma, + const UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle) { UNUSED_PARAMETER(ch); @@ -277,18 +272,6 @@ uint32_t uDMAx_ChannelGetCount(uint8_t ch, /** @} */ -/*ROM API Structure -const ROM_UDMA_WRAPPER_API_T udma_wrapper_api = { - &uDMAx_Initialize, - &uDMAx_Uninitialize, - &uDMAx_ChannelConfigure, - &uDMAx_ChannelEnable, - &uDMAx_DMAEnable, - &uDMAx_ChannelDisable, - &uDMAx_ChannelGetCount, - &uDMAx_IRQHandler, -}; -*/ #ifdef __cplusplus } #endif diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_usart.c b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_usart.c index 6d11ac2b4..d0abd5ade 100644 --- a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_usart.c +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_usart.c @@ -65,15 +65,17 @@ sl_dma_init_t dma_init; */ void UartIrqHandler(USART_RESOURCES *usart) { - volatile uint32_t int_status, line_status, modem_status; - uint32_t event, val; + volatile uint32_t int_status; + volatile uint32_t line_status; + volatile uint32_t modem_status; + uint32_t event; + uint32_t val; uint8_t usart_instance = 0U; int_status = 0U; line_status = 0U; modem_status = 0U; event = 0U; - val = 0U; // Check which uart instance irq got triggered and update the usart instance if ((usart->pREGS == UART0) || (usart->pREGS == USART0)) { usart_instance = USART_0; @@ -93,24 +95,18 @@ void UartIrqHandler(USART_RESOURCES *usart) if ((int_status & USART_RX_LINE_STATUS) == USART_RX_LINE_STATUS) { line_status = usart->pREGS->LSR; // OverRun error - if ((line_status & USART_OVERRUN_ERR) == USART_OVERRUN_ERR) { - if (usart->info->cb_event) { - usart->info->rx_status.rx_overflow = 1U; - usart->info->cb_event(ARM_USART_EVENT_RX_OVERFLOW); - } + if (((line_status & USART_OVERRUN_ERR) == USART_OVERRUN_ERR) && (usart->info->cb_event)) { + usart->info->rx_status.rx_overflow = 1U; + usart->info->cb_event(ARM_USART_EVENT_RX_OVERFLOW); // Sync Slave mode: If Transmitter enabled, signal TX underflow - if (usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_SLAVE) { - if (usart->info->xfer.send_active != 0U) { - event |= ARM_USART_EVENT_TX_UNDERFLOW; - } + if ((usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_SLAVE) && (usart->info->xfer.send_active != 0U)) { + event |= ARM_USART_EVENT_TX_UNDERFLOW; } } // Parity error - if ((line_status & USART_PARITY_ERR) == USART_PARITY_ERR) { - if (usart->info->cb_event) { - usart->info->rx_status.rx_parity_error = 1U; - usart->info->cb_event(ARM_USART_EVENT_RX_PARITY_ERROR); - } + if (((line_status & USART_PARITY_ERR) == USART_PARITY_ERR) && (usart->info->cb_event)) { + usart->info->rx_status.rx_parity_error = 1U; + usart->info->cb_event(ARM_USART_EVENT_RX_PARITY_ERROR); } // Framing error if ((line_status & USART_FRAMING_ERR) == USART_FRAMING_ERR) { @@ -120,11 +116,9 @@ void UartIrqHandler(USART_RESOURCES *usart) } } // Break detected - else if ((line_status & USART_BREAK_ERR) == USART_BREAK_ERR) { - if (usart->info->cb_event) { - usart->info->rx_status.rx_break = 1U; - usart->info->cb_event(ARM_USART_EVENT_RX_BREAK); - } + else if (((line_status & USART_BREAK_ERR) == USART_BREAK_ERR) && (usart->info->cb_event)) { + usart->info->rx_status.rx_break = 1U; + usart->info->cb_event(ARM_USART_EVENT_RX_BREAK); } } if ((int_status & USART_THR_EMPTY) == USART_THR_EMPTY) { @@ -146,41 +140,39 @@ void UartIrqHandler(USART_RESOURCES *usart) } } } - if ((int_status & USART_RX_DATA_AVAILABLE) == USART_RX_DATA_AVAILABLE) { - if (usart->info->cb_event) { - //check if receiver contains atleast one char in RBR reg - if ((usart->pREGS->LSR_b.DR)) { - usart->info->xfer.rx_buf[usart->info->xfer.rx_cnt] = (uint8_t)usart->pREGS->RBR; - usart->info->xfer.rx_cnt++; - - // Check if requested amount of data is received - if (usart->info->xfer.rx_cnt == usart->info->xfer.rx_num) { - // Disable RDA)rx_data_available) interrupt - usart->pREGS->IER &= (uint32_t)(~USART_INTR_RX_DATA); - // Clear RX busy flag and set receive transfer complete event - usart->info->rx_status.rx_busy = 0U; - if ((usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_MASTER) - || (usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_SLAVE)) { - val = usart->info->xfer.sync_mode; - usart->info->xfer.sync_mode = 0U; - switch (val) { - case USART_SYNC_MODE_TX: - event |= ARM_USART_EVENT_SEND_COMPLETE; - break; - case USART_SYNC_MODE_RX: - event |= ARM_USART_EVENT_RECEIVE_COMPLETE; - break; - case USART_SYNC_MODE_TX_RX: - event |= ARM_USART_EVENT_TRANSFER_COMPLETE; - break; - default: - break; - } - } else { - event |= ARM_USART_EVENT_RECEIVE_COMPLETE; + if (((int_status & USART_RX_DATA_AVAILABLE) == USART_RX_DATA_AVAILABLE) && (usart->info->cb_event)) { + //check if receiver contains atleast one char in RBR reg + if ((usart->pREGS->LSR_b.DR)) { + usart->info->xfer.rx_buf[usart->info->xfer.rx_cnt] = (uint8_t)usart->pREGS->RBR; + usart->info->xfer.rx_cnt++; + + // Check if requested amount of data is received + if (usart->info->xfer.rx_cnt == usart->info->xfer.rx_num) { + // Disable RDA)rx_data_available) interrupt + usart->pREGS->IER &= (uint32_t)(~USART_INTR_RX_DATA); + // Clear RX busy flag and set receive transfer complete event + usart->info->rx_status.rx_busy = 0U; + if ((usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_MASTER) + || (usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_SLAVE)) { + val = usart->info->xfer.sync_mode; + usart->info->xfer.sync_mode = 0U; + switch (val) { + case USART_SYNC_MODE_TX: + event |= ARM_USART_EVENT_SEND_COMPLETE; + break; + case USART_SYNC_MODE_RX: + event |= ARM_USART_EVENT_RECEIVE_COMPLETE; + break; + case USART_SYNC_MODE_TX_RX: + event |= ARM_USART_EVENT_TRANSFER_COMPLETE; + break; + default: + break; } - usart->info->cb_event(event); + } else { + event |= ARM_USART_EVENT_RECEIVE_COMPLETE; } + usart->info->cb_event(event); } } //Check if requested amount of data is not received @@ -371,7 +363,7 @@ int32_t USART_SetBaudrate(uint32_t baudrate, uint32_t baseClk, USART_RESOURCES * /** * @fn int32_t int32_t USART_Initialize( ARM_USART_SignalEvent_t cb_event, * USART_RESOURCES *usart, - * UDMA_RESOURCES *udma, + * const UDMA_RESOURCES *udma, * RSI_UDMA_DESC_T *UDMA_Table, * RSI_UDMA_HANDLE_T *udmaHandle, * uint32_t *mem ) @@ -390,7 +382,7 @@ int32_t USART_SetBaudrate(uint32_t baudrate, uint32_t baseClk, USART_RESOURCES * */ int32_t USART_Initialize(ARM_USART_SignalEvent_t cb_event, USART_RESOURCES *usart, - UDMA_RESOURCES *udma, + const UDMA_RESOURCES *udma, RSI_UDMA_DESC_T *UDMA_Table, RSI_UDMA_HANDLE_T *udmaHandle, uint32_t *mem) @@ -476,13 +468,13 @@ int32_t USART_Initialize(ARM_USART_SignalEvent_t cb_event, } /** - * @fn int32_t USART_Uninitialize (USART_RESOURCES *usart, UDMA_RESOURCES *udma) + * @fn int32_t USART_Uninitialize (const USART_RESOURCES *usart, const UDMA_RESOURCES *udma) * @brief De-initialize USART Interface. * @param[in] usart Pointer to USART resources * @param[in] udma Pointer to UDMA resources * @return \ref execution_status */ -int32_t USART_Uninitialize(USART_RESOURCES *usart, UDMA_RESOURCES *udma) +int32_t USART_Uninitialize(const USART_RESOURCES *usart, const UDMA_RESOURCES *udma) { #ifdef SL_SI91X_USART_DMA //Added to suppress unused variable warning @@ -526,7 +518,7 @@ int32_t USART_Uninitialize(USART_RESOURCES *usart, UDMA_RESOURCES *udma) } /** - * @fn int32_t USART_PowerControl ( ARM_POWER_STATE state, USART_RESOURCES *usart, UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle ) + * @fn int32_t USART_PowerControl ( ARM_POWER_STATE state, USART_RESOURCES *usart, const UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle ) * @brief Control USART Interface Power. * @param[in] state Power state * @param[in] usart Pointer to USART resources @@ -536,7 +528,7 @@ int32_t USART_Uninitialize(USART_RESOURCES *usart, UDMA_RESOURCES *udma) */ int32_t USART_PowerControl(ARM_POWER_STATE state, USART_RESOURCES *usart, - UDMA_RESOURCES *udma, + const UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle) { #ifdef SL_SI91X_USART_DMA @@ -640,7 +632,7 @@ int32_t USART_PowerControl(ARM_POWER_STATE state, } /** - * @fn int32_t USART_Send_Data(const void *data, uint32_t num,USART_RESOURCES *usart, UDMA_RESOURCES *udma, UDMA_Channel_Info *chnl_info, RSI_UDMA_HANDLE_T udmaHandle) + * @fn int32_t USART_Send_Data(const void *data, uint32_t num,USART_RESOURCES *usart, const UDMA_RESOURCES *udma, UDMA_Channel_Info *chnl_info, RSI_UDMA_HANDLE_T udmaHandle) * @brief Start sending data to USART transmitter. * @param[in] data Pointer to buffer with data to send to USART transmitter * @param[in] num Number of data items to send @@ -653,7 +645,7 @@ int32_t USART_PowerControl(ARM_POWER_STATE state, int32_t USART_Send_Data(const void *data, uint32_t num, USART_RESOURCES *usart, - UDMA_RESOURCES *udma, + const UDMA_RESOURCES *udma, UDMA_Channel_Info *chnl_info, RSI_UDMA_HANDLE_T udmaHandle) { @@ -789,7 +781,7 @@ int32_t USART_Send_Data(const void *data, } /** - * @fn int32_t USART_Receive_Data( const void *data,uint32_t num,USART_RESOURCES *usart, UDMA_RESOURCES *udma, UDMA_Channel_Info *chnl_info, RSI_UDMA_HANDLE_T udmaHandle) + * @fn int32_t USART_Receive_Data( const void *data,uint32_t num,USART_RESOURCES *usart, const UDMA_RESOURCES *udma, UDMA_Channel_Info *chnl_info, RSI_UDMA_HANDLE_T udmaHandle) * @brief Start receiving data from USART receiver. * @param[out] data Pointer to buffer for data to receive from USART receiver * @param[in] num Number of data items to receive @@ -802,7 +794,7 @@ int32_t USART_Send_Data(const void *data, int32_t USART_Receive_Data(const void *data, uint32_t num, USART_RESOURCES *usart, - UDMA_RESOURCES *udma, + const UDMA_RESOURCES *udma, UDMA_Channel_Info *chnl_info, RSI_UDMA_HANDLE_T udmaHandle) { @@ -944,7 +936,7 @@ int32_t USART_Receive_Data(const void *data, } /** - * @fn int32_t USART_Transfer (const void *data_out, void *data_in, uint32_t num,USART_RESOURCES *usart,UDMA_RESOURCES *udma,UDMA_Channel_Info *chnl_info,RSI_UDMA_HANDLE_T udmaHandle) + * @fn int32_t USART_Transfer (const void *data_out, void *data_in, uint32_t num,USART_RESOURCES *usart,const UDMA_RESOURCES *udma,UDMA_Channel_Info *chnl_info,RSI_UDMA_HANDLE_T udmaHandle) * @brief Start sending/receiving data to/from USART transmitter/receiver. * @param[in] data_out Pointer to buffer with data to send to USART transmitter * @param[out] data_in Pointer to buffer for data to receive from USART receiver @@ -959,7 +951,7 @@ int32_t USART_Transfer(const void *data_out, void *data_in, uint32_t num, USART_RESOURCES *usart, - UDMA_RESOURCES *udma, + const UDMA_RESOURCES *udma, UDMA_Channel_Info *chnl_info, RSI_UDMA_HANDLE_T udmaHandle) { @@ -1023,7 +1015,7 @@ uint32_t USART_GetRxCount(USART_RESOURCES *usart) } /** - * @fn int32_t USART_Control (uint32_t control, uint32_t arg,uint32_t baseClk, USART_RESOURCES *usart, UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle) + * @fn int32_t USART_Control (uint32_t control, uint32_t arg,uint32_t baseClk, USART_RESOURCES *usart, const UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle) * @brief Control USART Interface. * @param[in] control Operation * @param[in] arg Argument of operation (optional) @@ -1037,7 +1029,7 @@ int32_t USART_Control(uint32_t control, uint32_t arg, uint32_t baseClk, USART_RESOURCES *usart, - UDMA_RESOURCES *udma, + const UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle) { #ifdef SL_SI91X_USART_DMA diff --git a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/sl_si91x_m4_ps.c b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/sl_si91x_m4_ps.c index 6731754fe..b6f58de51 100644 --- a/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/sl_si91x_m4_ps.c +++ b/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/sl_si91x_m4_ps.c @@ -94,15 +94,9 @@ static uint8_t m4_alarm_initialization_done; RTC_TIME_CONFIG_T sl_rtc_get_Time; uint32_t sl_bf_rtc_ticks, sl_af_rtc_ticks, sl_rtc_ticks; -void sli_m4_ta_interrupt_init(void); void set_alarm_interrupt_timer(uint16_t interval); -void m4_powersave_app(void); void wakeup_source_config(void); -#if (configUSE_TICKLESS_IDLE == 1) -static uint32_t sli_si91x_is_sleep_ready(); -#endif // - #if (configUSE_TICKLESS_IDLE == 0) #if SL_SI91X_MCU_BUTTON_BASED_WAKEUP @@ -372,6 +366,8 @@ void sl_si91x_m4_sleep_wakeup(void) /* Configure 320K RAM Usage and Retention Size */ sl_si91x_configure_ram_retention(WISEMCU_320KB_RAM_IN_USE, WISEMCU_RETAIN_DEFAULT_RAM_DURING_SLEEP); #endif + /*Enable first boot up*/ + RSI_PS_EnableFirstBootUp(1); /* Trigger M4 Sleep*/ sl_si91x_trigger_sleep(SLEEP_WITH_RETENTION, DISABLE_LF_MODE, @@ -435,27 +431,47 @@ void sl_si91x_post_sleep_update_ticks(uint32_t *xExpectedIdleTime) } } /************************************************************************** - * @fn sli_si91x_is_sleep_ready() - * @brief This function checks the readiness of the SI91x device for - *sleep. - * @return The status indicating whether the device is ready for sleep. - * - Returns a non-zero value if the device is ready for sleep. - * - Returns 0 if the device is not ready for sleep. + * @fn bool sli_si91x_ta_packet_initiated_to_m4(void) + * @brief This function will verify whether there are any pending packets in TA when m4 is inactive + * @param[in] None + * @param[out] true: allow to sleep + * false: Not allow to the sleep *******************************************************************************/ -__attribute__((weak)) uint32_t sl_app_sleep_ready() +bool sli_si91x_ta_packet_initiated_to_m4(void) { - //This API is inadequate as it allows users to implement sleep-preventing checks at the user level. - return true; -} -static uint32_t sli_si91x_is_sleep_ready() -{ - /*verifying common flash write progress before triggering sleep*/ - if ((sl_app_sleep_ready()) && (sl_si91x_power_manager_is_ok_to_sleep()) && (sli_si91x_is_sdk_ok_to_sleep())) { - return true; + boolean_t sli_p2p_status = true; + + // Indicate M4 is Inactive + P2P_STATUS_REG &= ~M4_is_active; + + // Wait one more clock cycle to ensure the M4 hardware register is updated + P2P_STATUS_REG; + + // This delay is introduced to synchronize between the M4 and the TA. + for (uint8_t delay = 0; delay < 10; delay++) { + __ASM("NOP"); } - return (false); -} + // Verify if the TA has already initiated a packet to the M4 + // The TA will clear RX_BUFFER_VALID if a packet has been triggered + if ((P2P_STATUS_REG & TA_wakeup_M4) || (P2P_STATUS_REG & M4_wakeup_TA) + || (!(M4SS_P2P_INTR_SET_REG & RX_BUFFER_VALID))) { + P2P_STATUS_REG |= M4_is_active; + sli_p2p_status = false; + } else { + //Clearing the RX_Buffer valid bit + M4SS_P2P_INTR_CLR_REG = RX_BUFFER_VALID; + M4SS_P2P_INTR_CLR_REG; + + TASS_P2P_INTR_MASK_SET = (TX_PKT_TRANSFER_DONE_INTERRUPT | RX_PKT_TRANSFER_DONE_INTERRUPT | TA_WRITING_ON_COMM_FLASH + | NWP_DEINIT_IN_COMM_FLASH +#ifdef SL_SI91X_SIDE_BAND_CRYPTO + | SIDE_BAND_CRYPTO_DONE +#endif + ); + } + return sli_p2p_status; +} /************************************************************************** * @fn sli_si91x_m4_ta_wakeup_configurations(void) * @brief It is essential to properly configure the TA and M4 status registers @@ -484,53 +500,5 @@ void sli_si91x_m4_ta_wakeup_configurations(void) ); #endif } -/************************************************************************** - * @fn sl_si91x_pre_supress_ticks_and_sleep(uint16_t - **xExpectedIdleTime) - * @brief set xExpectedIdleTime to 0 if the application prevents the - *device Sleep - * @param[in] None - * @param[out] None - *******************************************************************************/ -void sl_si91x_pre_supress_ticks_and_sleep(uint32_t *xExpectedIdleTime) -{ - // pointer check - if (xExpectedIdleTime != NULL) { - - if (!sli_si91x_is_sleep_ready()) { - *xExpectedIdleTime = 0; - } else { - // a preliminary check of the expected idle time is performed without making M4 inactive - if (*xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP) { - // Indicate M4 is Inactive - P2P_STATUS_REG &= ~M4_is_active; - // Waiting for one more clock cycle to make sure M4 H/W Register is updated - P2P_STATUS_REG; - - // TODO: This delay is added to sync between M4 and TA. It should be removed once the logic is moved to wifi SDK - for (uint8_t delay = 0; delay < 10; delay++) { - __ASM("NOP"); - } - // Checking if TA has already triggered a packet to M4 - // RX_BUFFER_VALID will be cleared by TA if any packet is triggered - if ((P2P_STATUS_REG & TA_wakeup_M4) || (P2P_STATUS_REG & M4_wakeup_TA) - || (!(M4SS_P2P_INTR_SET_REG & RX_BUFFER_VALID))) { - P2P_STATUS_REG |= M4_is_active; - *xExpectedIdleTime = 0; - } else { - M4SS_P2P_INTR_CLR_REG = RX_BUFFER_VALID; - M4SS_P2P_INTR_CLR_REG; - - TASS_P2P_INTR_MASK_SET = (TX_PKT_TRANSFER_DONE_INTERRUPT | RX_PKT_TRANSFER_DONE_INTERRUPT - | TA_WRITING_ON_COMM_FLASH | NWP_DEINIT_IN_COMM_FLASH -#ifdef SL_SI91X_SIDE_BAND_CRYPTO - | SIDE_BAND_CRYPTO_DONE -#endif - ); - } - } - } - } -} #endif // #if (configUSE_TICKLESS_IDLE == 1) -#endif \ No newline at end of file +#endif diff --git a/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_clks.h b/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_clks.h index c0d7971d7..c6b0fdea2 100644 --- a/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_clks.h +++ b/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_clks.h @@ -55,6 +55,11 @@ #include "rsi_rom_table_RS1xxxx.h" #endif +#if SL_WIFI_COMPONENT_INCLUDED +#include "sl_rsi_utility.h" +#include "rsi_m4.h" +#endif + #ifdef __cplusplus extern "C" { #endif @@ -97,7 +102,20 @@ STATIC INLINE rsi_error_t RSI_CLK_SocPllClkEnable(boolean_t clkEnable) } /** - * @fn STATIC INLINE rsi_error_t RSI_CLK_SetSocPllFreq(M4CLK_Type *pCLK,uint32_t socPllFreq,uint32_t pllRefClk) + * @fn STATIC INLINE rsi_error_t RSI_CLK_SocPllTurnOn() + * @brief This API is used to TurnOn the SOC_PLL + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_SocPllTurnOn() +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_soc_pll_turn_on(); +#else + return clk_soc_pll_turn_on(); +#endif +} +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_SetSocPllFreq(const M4CLK_Type *pCLK,uint32_t socPllFreq,uint32_t pllRefClk) * @brief This API is used to set the Soc PLL clock to particular frequency * @param[in] pCLK : Pointer to the pll register instance * @param[in] socPllFreq : Frequency value in Mhz for Soc_Pll_Clk . @@ -105,15 +123,22 @@ STATIC INLINE rsi_error_t RSI_CLK_SocPllClkEnable(boolean_t clkEnable) * @return returns zero \ref RSI_OK on success ,on failure return error code. * @note Only 1Mhz steps applicable to the this API, 0.96Mhz steps are not supported */ -STATIC INLINE rsi_error_t RSI_CLK_SetSocPllFreq(M4CLK_Type *pCLK, uint32_t socPllFreq, uint32_t pllRefClk) +STATIC INLINE rsi_error_t RSI_CLK_SetSocPllFreq(const M4CLK_Type *pCLK, uint32_t socPllFreq, uint32_t pllRefClk) { rsi_error_t ret = (rsi_error_t)0; system_clocks.soc_pll_clock = socPllFreq; - if (pllRefClk == 32000000UL) { - /* Selecting the PLL reference clock */ - /* 0 - XTAL_CLK, 1 - Reserved, 2 - RC_32MHZ_CLK, 3 - Reserved */ - PLL_REF_CLK_CONFIG_REG |= (0x02 << 14); // Selecting the 32 MHz RC as SOC-PLL reference clock + if (pllRefClk == RC_32MHZ_CLK_FREQ) { + PLL_REF_CLK_CONFIG_REG |= SELECT_RC_MHZ_CLOCK; // Selecting the 32 MHz RC as SOC-PLL reference clock + } + + if (pllRefClk == XTAL_CLK_FREQ) //avoid if XTAL req is already done + { +#if SL_WIFI_COMPONENT_INCLUDED + /* Notify TA that M4 requires XTAL clock source */ + sli_si91x_xtal_turn_on_request_from_m4_to_TA(); +#endif + PLL_REF_CLK_CONFIG_REG &= SELECT_XTAL_MHZ_CLOCK; // Selecting the XTAL as PLL reference clock } SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG9) = 0xD900; @@ -145,7 +170,7 @@ STATIC INLINE rsi_error_t RSI_CLK_SetSocPllFreq(M4CLK_Type *pCLK, uint32_t socPl } /** - * @fn STATIC INLINE rsi_error_t RSI_CLK_SocPllSetFreqDiv(M4CLK_Type *pCLK , boolean_t clk_en,uint16_t + * @fn STATIC INLINE rsi_error_t RSI_CLK_SocPllSetFreqDiv(const M4CLK_Type *pCLK , boolean_t clk_en,uint16_t * divFactor,uint16_t nFactor,uint16_t mFactor,uint16_t fCwf, * uint16_t dcofixsel,uint16_t ldoprog) * @brief This API is used to configure the SOC PLL clock frequency @@ -162,7 +187,7 @@ STATIC INLINE rsi_error_t RSI_CLK_SetSocPllFreq(M4CLK_Type *pCLK, uint32_t socPl * - For 201-250Mhz ---> ldo_prog =5 and dco_fix_sel=0 * - For >=251Mhz ---> ldo_prog =5 and dco_fix_sel=2 */ -STATIC INLINE rsi_error_t RSI_CLK_SocPllSetFreqDiv(M4CLK_Type *pCLK, +STATIC INLINE rsi_error_t RSI_CLK_SocPllSetFreqDiv(const M4CLK_Type *pCLK, boolean_t clk_en, uint16_t divFactor, uint16_t nFactor, @@ -180,12 +205,12 @@ STATIC INLINE rsi_error_t RSI_CLK_SocPllSetFreqDiv(M4CLK_Type *pCLK, } /** - * @fn STATIC INLINE rsi_error_t RSI_CLK_SocPllClkSet(M4CLK_Type *pCLK) + * @fn STATIC INLINE rsi_error_t RSI_CLK_SocPllClkSet(const M4CLK_Type *pCLK) * @brief This API is used to Enables the SoC-PLL * @param[in] pCLK : Pointer to the pll register instance * @return returns zero \ref RSI_OK on success ,on failure return error code. */ -STATIC INLINE rsi_error_t RSI_CLK_SocPllClkSet(M4CLK_Type *pCLK) +STATIC INLINE rsi_error_t RSI_CLK_SocPllClkSet(const M4CLK_Type *pCLK) { #if defined(CLOCK_ROMDRIVER_PRESENT) return ROMAPI_M4SS_CLK_API->clk_soc_pll_clk_set(pCLK); @@ -256,20 +281,6 @@ STATIC INLINE rsi_error_t RSI_CLK_SocPllTurnOff() #endif } -/** - * @fn STATIC INLINE rsi_error_t RSI_CLK_SocPllTurnOn() - * @brief This API is used to TurnOn the SOC_PLL - * @return returns zero \ref RSI_OK on success ,on failure return error code. - */ -STATIC INLINE rsi_error_t RSI_CLK_SocPllTurnOn() -{ -#if defined(CLOCK_ROMDRIVER_PRESENT) - return ROMAPI_M4SS_CLK_API->clk_soc_pll_turn_on(); -#else - return clk_soc_pll_turn_on(); -#endif -} - /** * @fn STATIC INLINE rsi_error_t RSI_CLK_I2sPllClkEnable(boolean_t clkEnable) * @brief This API is used to enable the I2s_PLL output clock @@ -348,16 +359,20 @@ STATIC INLINE rsi_error_t RSI_CLK_I2sPllTurnOn() } /** - * @fn STATIC INLINE rsi_error_t RSI_CLK_SetI2sPllFreq(M4CLK_Type *pCLK,uint32_t i2sPllFreq, uint32_t fXtal) + * @fn STATIC INLINE rsi_error_t RSI_CLK_SetI2sPllFreq(const M4CLK_Type *pCLK,uint32_t i2sPllFreq, uint32_t fXtal) * @brief This API is used to set the I2s_pll clock to particular frequency * @param[in] pCLK : Pointer to the pll register instance * @param[in] i2sPllFreq : Frequency value in Mhz for I2S_PLL Clk . * @param[in] fXtal : Frequency value in Mhz for crystal oscillator frequency. * @return returns zero \ref RSI_OK on success ,on failure return error code. */ -STATIC INLINE rsi_error_t RSI_CLK_SetI2sPllFreq(M4CLK_Type *pCLK, uint32_t i2sPllFreq, uint32_t fXtal) +STATIC INLINE rsi_error_t RSI_CLK_SetI2sPllFreq(const M4CLK_Type *pCLK, uint32_t i2sPllFreq, uint32_t fXtal) { - system_clocks.i2s_pll_clock = i2sPllFreq; + system_clocks.i2s_pll_clock = i2sPllFreq; +#if SL_WIFI_COMPONENT_INCLUDED + /* Notify TA that M4 requires XTAL clock source */ + sli_si91x_xtal_turn_on_request_from_m4_to_TA(); +#endif SPI_MEM_MAP_PLL(I2S_PLL_CTRL_REG9) = 0xD900; #if defined(CLOCK_ROMDRIVER_PRESENT) return ROMAPI_M4SS_CLK_API->clk_set_i2s_pll_freq(pCLK, i2sPllFreq, fXtal); @@ -367,7 +382,7 @@ STATIC INLINE rsi_error_t RSI_CLK_SetI2sPllFreq(M4CLK_Type *pCLK, uint32_t i2sPl } /** - * @fn STATIC INLINE rsi_error_t RSI_CLK_I2sPllSetFreqDiv(M4CLK_Type *pCLK,uint16_t u16DivFactor1, + * @fn STATIC INLINE rsi_error_t RSI_CLK_I2sPllSetFreqDiv(const M4CLK_Type *pCLK,uint16_t u16DivFactor1, * uint16_t u16DivFactor2,uint16_t nFactor,uint16_t mFactor, * uint16_t fcwF) * @brief This API is used to divide I2s_PLL Clock @@ -379,7 +394,7 @@ STATIC INLINE rsi_error_t RSI_CLK_SetI2sPllFreq(M4CLK_Type *pCLK, uint32_t i2sPl * @param[in] fcwF : Fractional Frequency Control Word. * @return returns zero \ref RSI_OK on success ,on failure return error code. */ -STATIC INLINE rsi_error_t RSI_CLK_I2sPllSetFreqDiv(M4CLK_Type *pCLK, +STATIC INLINE rsi_error_t RSI_CLK_I2sPllSetFreqDiv(const M4CLK_Type *pCLK, uint16_t u16DivFactor1, uint16_t u16DivFactor2, uint16_t nFactor, @@ -394,12 +409,12 @@ STATIC INLINE rsi_error_t RSI_CLK_I2sPllSetFreqDiv(M4CLK_Type *pCLK, } /** - * @fn STATIC INLINE rsi_error_t RSI_CLK_I2sPllClkSet(M4CLK_Type *pCLK) + * @fn STATIC INLINE rsi_error_t RSI_CLK_I2sPllClkSet(const M4CLK_Type *pCLK) * @brief This API is used to set the I2s_pll_clk * @param[in] pCLK : Pointer to the pll register instance * @return returns zero \ref RSI_OK on success ,on failure return error code. */ -STATIC INLINE rsi_error_t RSI_CLK_I2sPllClkSet(M4CLK_Type *pCLK) +STATIC INLINE rsi_error_t RSI_CLK_I2sPllClkSet(const M4CLK_Type *pCLK) { #if defined(CLOCK_ROMDRIVER_PRESENT) return ROMAPI_M4SS_CLK_API->clk_i2s_pll_clk_set(pCLK); @@ -470,7 +485,7 @@ STATIC INLINE rsi_error_t RSI_CLK_IntfPLLTurnOff() } /** - * @fn STATIC INLINE rsi_error_t RSI_CLK_SetIntfPllFreq(M4CLK_Type *pCLK,uint32_t intfPllFreq,uint32_t pllRefClk) + * @fn STATIC INLINE rsi_error_t RSI_CLK_SetIntfPllFreq(const M4CLK_Type *pCLK,uint32_t intfPllFreq,uint32_t pllRefClk) * @brief This API is used to set the INTFPLL clock to particular frequency * @param[in] pCLK : Pointer to the pll register instance * @param[in] intfPllFreq : Frequency value in Mhz for INTFPLL Clk . @@ -478,11 +493,22 @@ STATIC INLINE rsi_error_t RSI_CLK_IntfPLLTurnOff() * @return returns zero \ref RSI_OK on success ,on failure return error code. * @note Only 1Mhz steps applicable to the this API, 0.96Mhz steps are not supported */ -STATIC INLINE rsi_error_t RSI_CLK_SetIntfPllFreq(M4CLK_Type *pCLK, uint32_t intfPllFreq, uint32_t pllRefClk) +STATIC INLINE rsi_error_t RSI_CLK_SetIntfPllFreq(const M4CLK_Type *pCLK, uint32_t intfPllFreq, uint32_t pllRefClk) { rsi_error_t error = (rsi_error_t)0; system_clocks.intf_pll_clock = intfPllFreq; + if (pllRefClk == RC_32MHZ_CLK_FREQ) { + PLL_REF_CLK_CONFIG_REG |= SELECT_RC_MHZ_CLOCK; // Selecting the 32 MHz RC as SOC-PLL reference clock + } +#if SL_WIFI_COMPONENT_INCLUDED + if (pllRefClk == XTAL_CLK_FREQ) //avoid if XTAL req is already done + { + /* Notify TA that M4 requires XTAL clock source */ + sli_si91x_xtal_turn_on_request_from_m4_to_TA(); + PLL_REF_CLK_CONFIG_REG &= SELECT_XTAL_MHZ_CLOCK; // Selecting the XTAL as PLL reference clock + } +#endif SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG9) = 0xD900; #if defined(CLOCK_ROMDRIVER_PRESENT) error = ROMAPI_M4SS_CLK_API->clk_set_intf_pll_freq(pCLK, intfPllFreq, pllRefClk); @@ -510,7 +536,7 @@ STATIC INLINE rsi_error_t RSI_CLK_SetIntfPllFreq(M4CLK_Type *pCLK, uint32_t intf } /** - * @fn STATIC INLINE rsi_error_t RSI_CLK_IntfPllSetFreqDiv(M4CLK_Type *pCLK , boolean_t clk_en, + * @fn STATIC INLINE rsi_error_t RSI_CLK_IntfPllSetFreqDiv(const M4CLK_Type *pCLK , boolean_t clk_en, * uint16_t divFactor,uint16_t nFactor,uint16_t mFactor, * uint16_t fcwF,uint16_t dcoFixSel,uint16_t ldoProg) * @brief This API is used to divide the Intf PLL clock frequency @@ -527,7 +553,7 @@ STATIC INLINE rsi_error_t RSI_CLK_SetIntfPllFreq(M4CLK_Type *pCLK, uint32_t intf * - For 201-250Mhz ---> ldo_prog =5 and dco_fix_sel=0 * - For >=251Mhz ---> ldo_prog =5 and dco_fix_sel=2 */ -STATIC INLINE rsi_error_t RSI_CLK_IntfPllSetFreqDiv(M4CLK_Type *pCLK, +STATIC INLINE rsi_error_t RSI_CLK_IntfPllSetFreqDiv(const M4CLK_Type *pCLK, boolean_t clk_en, uint16_t divFactor, uint16_t nFactor, @@ -590,12 +616,12 @@ STATIC INLINE rsi_error_t RSI_CLK_IntfPllClkReset() } /** - * @fn STATIC INLINE rsi_error_t RSI_CLK_IntfPllClkSet(M4CLK_Type *pCLK) + * @fn STATIC INLINE rsi_error_t RSI_CLK_IntfPllClkSet(const M4CLK_Type *pCLK) * @brief This API is used to Enables the Intf-PLL * @param[in] pCLK : Pointer to the pll register instance * @return returns zero \ref RSI_OK on success ,on failure return error code. */ -STATIC INLINE rsi_error_t RSI_CLK_IntfPllClkSet(M4CLK_Type *pCLK) +STATIC INLINE rsi_error_t RSI_CLK_IntfPllClkSet(const M4CLK_Type *pCLK) { #if defined(CLOCK_ROMDRIVER_PRESENT) return ROMAPI_M4SS_CLK_API->clk_intf_pll_clk_set(pCLK); @@ -1039,14 +1065,20 @@ STATIC INLINE rsi_error_t RSI_ULPSS_DisableRefClks(REF_CLK_ENABLE_T clk_type) } /** - * @fn STATIC INLINE rsi_error_t RSI_CLK_M4ssRefClkConfig(M4CLK_Type *pCLK ,M4SS_REF_CLK_SEL_T clkSource) + * @fn STATIC INLINE rsi_error_t RSI_CLK_M4ssRefClkConfig(const M4CLK_Type *pCLK ,M4SS_REF_CLK_SEL_T clkSource) * @brief This API is used to configure the m4ss_ref clocks * @param[in] pCLK : Pointer to the pll register instance * @param[in] clkSource : Enum values of different M4 ref source clocks \ref M4SS_REF_CLK_SEL_T * @return returns zero \ref RSI_OK on success ,on failure return error code. */ -STATIC INLINE rsi_error_t RSI_CLK_M4ssRefClkConfig(M4CLK_Type *pCLK, M4SS_REF_CLK_SEL_T clkSource) +STATIC INLINE rsi_error_t RSI_CLK_M4ssRefClkConfig(const M4CLK_Type *pCLK, M4SS_REF_CLK_SEL_T clkSource) { +#if SL_WIFI_COMPONENT_INCLUDED + if (clkSource == RF_REF_CLK) { + /* Notify TA that M4 requires XTAL clock source */ + sli_si91x_xtal_turn_on_request_from_m4_to_TA(); + } +#endif return clk_m4ss_ref_clk_config(pCLK, clkSource); } diff --git a/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_egpio.h b/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_egpio.h index 2f7e37bfe..c1334024b 100644 --- a/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_egpio.h +++ b/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_egpio.h @@ -84,14 +84,14 @@ STATIC INLINE void RSI_EGPIO_SetPin(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pi } /** - * @fn STATIC INLINE boolean_t RSI_EGPIO_GetPin(EGPIO_Type *pEGPIO ,uint8_t port,uint8_t pin) + * @fn STATIC INLINE boolean_t RSI_EGPIO_GetPin(const EGPIO_Type *pEGPIO ,uint8_t port,uint8_t pin) * @brief This API is used get the GPIO pin status. * @param[in] pEGPIO : Pointer to the EGPIO register instance * @param[in] port : GPIO port number * @param[in] pin : GPIO pin number * @return returns Pin status */ -STATIC INLINE boolean_t RSI_EGPIO_GetPin(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin) +STATIC INLINE boolean_t RSI_EGPIO_GetPin(const EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin) { #if defined(ROMDRIVER_PRESENT) return ROMAPI_EGPIO_API->egpio_get_pin(pEGPIO, port, pin); @@ -101,14 +101,14 @@ STATIC INLINE boolean_t RSI_EGPIO_GetPin(EGPIO_Type *pEGPIO, uint8_t port, uint8 } /** - * @fn STATIC INLINE boolean_t RSI_EGPIO_GetDir(EGPIO_Type *pEGPIO,uint8_t port ,uint8_t pin) + * @fn STATIC INLINE boolean_t RSI_EGPIO_GetDir(const EGPIO_Type *pEGPIO,uint8_t port ,uint8_t pin) * @brief This API is used to Get the Direction GPIO(Direction of the GPIO pin. '1' for INPUT,and '0'for OUTPUT) * @param[in] pEGPIO : Pointer to the EGPIO register instance * @param[in] port : GPIO port number * @param[in] pin : GPIO pin number * @return returns the GPIO direction value */ -STATIC INLINE boolean_t RSI_EGPIO_GetDir(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin) +STATIC INLINE boolean_t RSI_EGPIO_GetDir(const EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin) { #if defined(ROMDRIVER_PRESENT) return ROMAPI_EGPIO_API->egpio_get_dir(pEGPIO, port, pin); @@ -307,13 +307,13 @@ STATIC INLINE void RSI_EGPIO_SetIntHighLevelDisable(EGPIO_Type *pEGPIO, uint8_t } /** - * @fn uint8_t RSI_EGPIO_GetIntStat(EGPIO_Type *pEGPIO ,uint8_t intCh) + * @fn uint8_t RSI_EGPIO_GetIntStat(const EGPIO_Type *pEGPIO ,uint8_t intCh) * @brief This API is used to get the pin interrupt status register * @param[in] pEGPIO : Pointer to the EGPIO register instance * @param[in] intCh : GPIO pin interrupt channel number (0 to 7) * @return returns the interrupt status register */ -STATIC INLINE uint8_t RSI_EGPIO_GetIntStat(EGPIO_Type *pEGPIO, uint8_t intCh) +STATIC INLINE uint8_t RSI_EGPIO_GetIntStat(const EGPIO_Type *pEGPIO, uint8_t intCh) { #if defined(ROMDRIVER_PRESENT) return ROMAPI_EGPIO_API->egpio_get_int_stat(pEGPIO, intCh); @@ -547,14 +547,14 @@ STATIC INLINE void RSI_EGPIO_TogglePort(EGPIO_Type *pEGPIO, uint8_t port, uint16 } /** - * @fn STATIC INLINE uint16_t RSI_EGPIO_GetPort(EGPIO_Type *pEGPIO ,uint8_t port) + * @fn STATIC INLINE uint16_t RSI_EGPIO_GetPort(const EGPIO_Type *pEGPIO ,uint8_t port) * @brief This API is used to used to get the EGPIO port value. * Reads the value on GPIO pins irrespective of the pin mode. * @param[in] pEGPIO : Pointer to the EGPIO register instance * @param[in] port : Port number to be read * @return port value */ -STATIC INLINE uint16_t RSI_EGPIO_GetPort(EGPIO_Type *pEGPIO, uint8_t port) +STATIC INLINE uint16_t RSI_EGPIO_GetPort(const EGPIO_Type *pEGPIO, uint8_t port) { #if defined(ROMDRIVER_PRESENT) return ROMAPI_EGPIO_API->egpio_get_port(pEGPIO, port); @@ -745,13 +745,13 @@ STATIC INLINE void RSI_EGPIO_GroupIntOr(EGPIO_Type *pEGPIO, uint8_t grpInt) } /** - * @fn STATIC INLINE uint32_t RSI_EGPIO_GroupIntStat(EGPIO_Type *pEGPIO ,uint8_t grpInt) + * @fn STATIC INLINE uint32_t RSI_EGPIO_GroupIntStat(const EGPIO_Type *pEGPIO ,uint8_t grpInt) * @brief This API to used to get the group interrupt status * @param[in] pEGPIO : Pointer to the EGPIO register instance * @param[in] grpInt : Group interrupt number * @return returns the group interrupt status register */ -STATIC INLINE uint32_t RSI_EGPIO_GroupIntStat(EGPIO_Type *pEGPIO, uint8_t grpInt) +STATIC INLINE uint32_t RSI_EGPIO_GroupIntStat(const EGPIO_Type *pEGPIO, uint8_t grpInt) { #if defined(ROMDRIVER_PRESENT) return ROMAPI_EGPIO_API->egpio_group_int_stat(pEGPIO, grpInt); diff --git a/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_power_save.h b/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_power_save.h index db1b72ac5..0c945c4a6 100644 --- a/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_power_save.h +++ b/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_power_save.h @@ -110,7 +110,6 @@ STATIC INLINE rsi_error_t RSI_PS_PowerStateChangePs4toPs2(ULP_MODE_T enCtxSel, uint8_t taRamRetEnable, uint8_t M4RamRetEnable) { - uint8_t x = 0; // TODO: Check silicon rev from flash/efuse offset; for 1.4V do this programming if (SiliconRev >= 0x14) { if (taRamRetEnable) { @@ -123,7 +122,7 @@ STATIC INLINE rsi_error_t RSI_PS_PowerStateChangePs4toPs2(ULP_MODE_T enCtxSel, #ifndef SLI_SI917 M4CLK->CLK_ENABLE_SET_REG1_b.M4SS_UM_CLK_STATIC_EN_b = 0x1; #endif - for (x = 0; x < 10; x++) { + for (uint8_t x = 0; x < 10; x++) { __ASM("NOP"); } #ifndef SLI_SI917 diff --git a/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_table_RS1xxxx.h b/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_table_RS1xxxx.h index 9a4513f7f..f490e1747 100644 --- a/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_table_RS1xxxx.h +++ b/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_table_RS1xxxx.h @@ -140,7 +140,7 @@ typedef PRE_PACK struct POST_PACK { boolean_t (*clk_check_pll_lock)(PLL_TYPE_T pllType); rsi_error_t (*clk_soc_pll_clk_enable)(boolean_t clkEnable); rsi_error_t (*clk_set_soc_pll_freq)(M4CLK_Type *pCLK, uint32_t socPllFreq, uint32_t pllRefClk); - rsi_error_t (*clk_soc_pll_set_freq_div)(M4CLK_Type *pCLK, + rsi_error_t (*clk_soc_pll_set_freq_div)(const M4CLK_Type *pCLK, boolean_t clk_en, uint16_t divFactor, uint16_t nFactor, @@ -148,7 +148,7 @@ typedef PRE_PACK struct POST_PACK { uint16_t fcwF, uint16_t dcoFixSel, uint16_t ldoProg); - rsi_error_t (*clk_soc_pll_clk_set)(M4CLK_Type *pCLK); + rsi_error_t (*clk_soc_pll_clk_set)(const M4CLK_Type *pCLK); rsi_error_t (*clk_soc_pll_clk_bypass_enable)(boolean_t clkEnable); rsi_error_t (*clk_soc_pll_clk_reset)(void); rsi_error_t (*clk_soc_pll_pd_enable)(boolean_t en); @@ -159,20 +159,20 @@ typedef PRE_PACK struct POST_PACK { rsi_error_t (*clk_i2s_pll_pd_enable)(boolean_t en); rsi_error_t (*clk_i2s_pll_turn_off)(void); rsi_error_t (*clk_i2s_pll_turn_on)(void); - rsi_error_t (*clk_set_i2s_pll_freq)(M4CLK_Type *pCLK, uint32_t i2sPllFreq, uint32_t fXtal); - rsi_error_t (*clk_i2s_pll_set_freq_div)(M4CLK_Type *pCLK, + rsi_error_t (*clk_set_i2s_pll_freq)(const M4CLK_Type *pCLK, uint32_t i2sPllFreq, uint32_t fXtal); + rsi_error_t (*clk_i2s_pll_set_freq_div)(const M4CLK_Type *pCLK, uint16_t u16DivFactor1, uint16_t u16DivFactor2, uint16_t nFactor, uint16_t mFactor, uint16_t fcwF); - rsi_error_t (*clk_i2s_pll_clk_set)(M4CLK_Type *pCLK); + rsi_error_t (*clk_i2s_pll_clk_set)(const M4CLK_Type *pCLK); rsi_error_t (*clk_i2s_pll_clk_reset)(void); rsi_error_t (*clk_intf_pll_clk_enable)(boolean_t clkEnable); rsi_error_t (*clk_intf_pll_pd_enable)(boolean_t en); rsi_error_t (*clk_intf_pll_turn_off)(void); rsi_error_t (*clk_set_intf_pll_freq)(M4CLK_Type *pCLK, uint32_t intfPllFreq, uint32_t pllRefClk); - rsi_error_t (*clk_intf_pll_set_freq_div)(M4CLK_Type *pCLK, + rsi_error_t (*clk_intf_pll_set_freq_div)(const M4CLK_Type *pCLK, boolean_t clk_en, uint16_t divFactor, uint16_t nFactor, @@ -183,7 +183,7 @@ typedef PRE_PACK struct POST_PACK { rsi_error_t (*clk_intf_pll_clk_bypass_enable)(boolean_t clkEnable); rsi_error_t (*clk_intf_pll_turn_on)(void); rsi_error_t (*clk_intf_pll_clk_reset)(void); - rsi_error_t (*clk_intf_pll_clk_set)(M4CLK_Type *pCLK); + rsi_error_t (*clk_intf_pll_clk_set)(const M4CLK_Type *pCLK); rsi_error_t (*clk_peripheral_clk_enable1)(M4CLK_Type *pCLK, uint32_t flags); rsi_error_t (*clk_peripheral_clk_disable1)(M4CLK_Type *pCLK, uint32_t flags); rsi_error_t (*clk_peripheral_clk_enable2)(M4CLK_Type *pCLK, uint32_t flags); @@ -195,7 +195,7 @@ typedef PRE_PACK struct POST_PACK { rsi_error_t (*clk_dynamic_clk_gate_enable)(M4CLK_Type *pCLK, uint32_t flags); rsi_error_t (*clk_dynamic_clk_gate_enable2)(M4CLK_Type *pCLK, uint32_t flags); rsi_error_t (*ulpss_enable_ref_clks)(REF_CLK_ENABLE_T enable, SRC_TYPE_T srcType, cdDelay delayFn); - rsi_error_t (*clk_m4ss_ref_clk_config)(M4CLK_Type *pCLK, M4SS_REF_CLK_SEL_T clkSource); + rsi_error_t (*clk_m4ss_ref_clk_config)(const M4CLK_Type *pCLK, M4SS_REF_CLK_SEL_T clkSource); rsi_error_t (*clk_m4_soc_clk_config)(M4CLK_Type *pCLK, M4_SOC_CLK_SRC_SEL_T clkSource, uint32_t divFactor); rsi_error_t (*clk_qspi_clk_config)(M4CLK_Type *pCLK, QSPI_CLK_SRC_SEL_T clkSource, @@ -823,7 +823,7 @@ typedef PRE_PACK struct POST_PACK { typedef PRE_PACK struct POST_PACK { RSI_UDMA_HANDLE_T (*udma_init)(void *mem, const RSI_UDMA_INIT_T *pInit); - uint32_t (*udma_get_channel_transfer_mode)(RSI_UDMA_HANDLE_T pHandle, RSI_UDMA_CHA_CFG_T *pCfg); + uint32_t (*udma_get_channel_transfer_mode)(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg); rsi_error_t (*udma_setup_channel_transfer)(RSI_UDMA_HANDLE_T pHandle, RSI_UDMA_CHA_CFG_T *pCfg, @@ -838,12 +838,12 @@ typedef PRE_PACK struct POST_PACK { uint32_t transferType); uint32_t (*udma_get_channel_transfer_length)(RSI_UDMA_HANDLE_T pHandle, - RSI_UDMA_CHA_CFG_T *pCfg, + const RSI_UDMA_CHA_CFG_T *pCfg, RSI_UDMA_CHA_CONFIG_DATA_T vsUDMAChaConfigData); - rsi_error_t (*udma_setup_channel)(RSI_UDMA_HANDLE_T pHandle, RSI_UDMA_CHA_CFG_T *pCfg); + rsi_error_t (*udma_setup_channel)(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg); - void (*udma_deInit)(RSI_UDMA_HANDLE_T pHandle, RSI_UDMA_CHA_CFG_T *pCfg); + void (*udma_deInit)(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg); void (*udma_interrupt_handler)(RSI_UDMA_HANDLE_T pHandle); diff --git a/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_table_si91x.h b/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_table_si91x.h index 6175e4ff1..1bfdeb3ab 100644 --- a/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_table_si91x.h +++ b/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_table_si91x.h @@ -65,8 +65,8 @@ extern "C" { typedef struct { void (*egpio_set_dir)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, boolean_t dir); void (*egpio_set_pin)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, uint8_t val); - boolean_t (*egpio_get_pin)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); - boolean_t (*egpio_get_dir)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); + boolean_t (*egpio_get_pin)(const EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); + boolean_t (*egpio_get_dir)(const EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); void (*egpio_pin_int_sel)(EGPIO_Type *pEGPIO, uint8_t intCh, uint8_t port, uint8_t pin); void (*egpio_set_int_fall_edge_enable)(EGPIO_Type *pEGPIO, uint8_t intCh); void (*egpio_set_int_fall_edge_disable)(EGPIO_Type *pEGPIO, uint8_t intCh); @@ -78,7 +78,7 @@ typedef struct { void (*egpio_set_int_low_level_disable)(EGPIO_Type *pEGPIO, uint8_t intCh); void (*egpio_set_int_high_level_enable)(EGPIO_Type *pEGPIO, uint8_t intCh); void (*egpio_set_int_high_level_disable)(EGPIO_Type *pEGPIO, uint8_t intCh); - uint8_t (*egpio_get_int_stat)(EGPIO_Type *pEGPIO, uint8_t intCh); + uint8_t (*egpio_get_int_stat)(const EGPIO_Type *pEGPIO, uint8_t intCh); void (*egpio_int_clr)(EGPIO_Type *pEGPIO, uint8_t intCh, uint8_t flags); void (*egpio_set_pin_mux)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, uint8_t mux); void (*egpio_ulp_soc_gpio_mode)(ULPCLK_Type *pULPCLK, uint8_t gpio, uint8_t mode); @@ -90,7 +90,7 @@ typedef struct { void (*egpio_word_load)(EGPIO_Type *pEGPIO, uint8_t pin, uint16_t val); void (*egpio_clr_port)(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val); void (*egpio_toggle_port)(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val); - uint16_t (*egpio_get_port)(EGPIO_Type *pEGPIO, uint8_t port); + uint16_t (*egpio_get_port)(const EGPIO_Type *pEGPIO, uint8_t port); void (*egpio_group_int_one_enable)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); void (*egpio_group_int_one_disable)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); void (*egpio_group_int_two_enable)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); @@ -102,7 +102,7 @@ typedef struct { void (*egpio_group_int_edge)(EGPIO_Type *pEGPIO, uint8_t grpInt); void (*egpio_group_int_and)(EGPIO_Type *pEGPIO, uint8_t grpInt); void (*egpio_group_int_or)(EGPIO_Type *pEGPIO, uint8_t grpInt); - uint32_t (*egpio_group_int_stat)(EGPIO_Type *pEGPIO, uint8_t grpInt); + uint32_t (*egpio_group_int_stat)(const EGPIO_Type *pEGPIO, uint8_t grpInt); void (*egpio_group_int_wkeup_Enable)(EGPIO_Type *pEGPIO, uint8_t grpInt); void (*egpio_group_int_wkeup_disable)(EGPIO_Type *pEGPIO, uint8_t grpInt); void (*egpio_group_int_clr)(EGPIO_Type *pEGPIO, uint8_t grpInt, uint8_t flags); @@ -289,9 +289,9 @@ typedef PRE_PACK struct POST_PACK { typedef PRE_PACK struct POST_PACK { RSI_UDMA_HANDLE_T (*udma_init)(void *mem, const RSI_UDMA_INIT_T *pInit); - uint32_t (*udma_get_channel_transfer_mode)(RSI_UDMA_HANDLE_T pHandle, RSI_UDMA_CHA_CFG_T *pCfg); + uint32_t (*udma_get_channel_transfer_mode)(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg); rsi_error_t (*udma_setup_channel_transfer)(RSI_UDMA_HANDLE_T pHandle, - RSI_UDMA_CHA_CFG_T *pCfg, + const RSI_UDMA_CHA_CFG_T *pCfg, RSI_UDMA_CHA_CONFIG_DATA_T vsUdmaChaConfigData, void *pSrcAddr, void *pDstAddr); @@ -303,12 +303,12 @@ typedef PRE_PACK struct POST_PACK { uint32_t transferType); uint32_t (*udma_get_channel_transfer_length)(RSI_UDMA_HANDLE_T pHandle, - RSI_UDMA_CHA_CFG_T *pCfg, + const RSI_UDMA_CHA_CFG_T *pCfg, RSI_UDMA_CHA_CONFIG_DATA_T vsUDMAChaConfigData); - rsi_error_t (*udma_setup_channel)(RSI_UDMA_HANDLE_T pHandle, RSI_UDMA_CHA_CFG_T *pCfg); + rsi_error_t (*udma_setup_channel)(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg); - void (*udma_deInit)(RSI_UDMA_HANDLE_T pHandle, RSI_UDMA_CHA_CFG_T *pCfg); + void (*udma_deInit)(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg); void (*udma_interrupt_handler)(RSI_UDMA_HANDLE_T pHandle); @@ -321,25 +321,25 @@ typedef PRE_PACK struct POST_PACK { //////////////////////////UDMA WRAPPERS ////////////////////////// typedef PRE_PACK struct POST_PACK { RSI_UDMA_HANDLE_T(*uDMAx_Initialize) - (UDMA_RESOURCES *udma, RSI_UDMA_DESC_T *UDMA_Table, RSI_UDMA_HANDLE_T udmaHandle, uint32_t *mem); - int32_t (*uDMAx_Uninitialize)(UDMA_RESOURCES *udma); - int32_t (*uDMAx_ChannelConfigure)(UDMA_RESOURCES *udma, + (const UDMA_RESOURCES *udma, RSI_UDMA_DESC_T *UDMA_Table, RSI_UDMA_HANDLE_T udmaHandle, uint32_t *mem); + int32_t (*uDMAx_Uninitialize)(const UDMA_RESOURCES *udma); + int32_t (*uDMAx_ChannelConfigure)(const UDMA_RESOURCES *udma, uint8_t ch, uint32_t src_addr, uint32_t dest_addr, uint32_t size, RSI_UDMA_CHA_CONFIG_DATA_T control, - RSI_UDMA_CHA_CFG_T *config, + const RSI_UDMA_CHA_CFG_T *config, UDMA_SignalEvent_t cb_event, UDMA_Channel_Info *chnl_info, RSI_UDMA_HANDLE_T udmaHandle); - int32_t (*uDMAx_ChannelEnable)(uint8_t ch, UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle); - int32_t (*uDMAx_DMAEnable)(UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle); - int32_t (*uDMAx_ChannelDisable)(uint8_t ch, UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle); + int32_t (*uDMAx_ChannelEnable)(uint8_t ch, const UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle); + int32_t (*uDMAx_DMAEnable)(const UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle); + int32_t (*uDMAx_ChannelDisable)(uint8_t ch, const UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle); uint32_t (*uDMAx_ChannelGetCount)(uint8_t ch, RSI_UDMA_CHA_CONFIG_DATA_T control, RSI_UDMA_CHA_CFG_T config, - UDMA_RESOURCES *udma, + const UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle); void (*uDMAx_IRQHandler)(UDMA_RESOURCES *udma, RSI_UDMA_DESC_T *UDMA_Table, UDMA_Channel_Info *chnl_info); @@ -811,8 +811,8 @@ typedef PRE_PACK struct POST_PACK { typedef PRE_PACK struct POST_PACK { boolean_t (*clk_check_pll_lock)(PLL_TYPE_T pllType); rsi_error_t (*clk_soc_pll_clk_enable)(boolean_t clkEnable); - rsi_error_t (*clk_set_soc_pll_freq)(M4CLK_Type *pCLK, uint32_t socPllFreq, uint32_t pllRefClk); - rsi_error_t (*clk_soc_pll_set_freq_div)(M4CLK_Type *pCLK, + rsi_error_t (*clk_set_soc_pll_freq)(const M4CLK_Type *pCLK, uint32_t socPllFreq, uint32_t pllRefClk); + rsi_error_t (*clk_soc_pll_set_freq_div)(const M4CLK_Type *pCLK, boolean_t clk_en, uint16_t divFactor, uint16_t nFactor, @@ -820,7 +820,7 @@ typedef PRE_PACK struct POST_PACK { uint16_t fcwF, uint16_t dcoFixSel, uint16_t ldoProg); - rsi_error_t (*clk_soc_pll_clk_set)(M4CLK_Type *pCLK); + rsi_error_t (*clk_soc_pll_clk_set)(const M4CLK_Type *pCLK); rsi_error_t (*clk_soc_pll_clk_bypass_enable)(boolean_t clkEnable); rsi_error_t (*clk_soc_pll_clk_reset)(void); rsi_error_t (*clk_soc_pll_pd_enable)(boolean_t en); @@ -831,20 +831,20 @@ typedef PRE_PACK struct POST_PACK { rsi_error_t (*clk_i2s_pll_pd_enable)(boolean_t en); rsi_error_t (*clk_i2s_pll_turn_off)(void); rsi_error_t (*clk_i2s_pll_turn_on)(void); - rsi_error_t (*clk_set_i2s_pll_freq)(M4CLK_Type *pCLK, uint32_t i2sPllFreq, uint32_t fXtal); - rsi_error_t (*clk_i2s_pll_set_freq_div)(M4CLK_Type *pCLK, + rsi_error_t (*clk_set_i2s_pll_freq)(const M4CLK_Type *pCLK, uint32_t i2sPllFreq, uint32_t fXtal); + rsi_error_t (*clk_i2s_pll_set_freq_div)(const M4CLK_Type *pCLK, uint16_t u16DivFactor1, uint16_t u16DivFactor2, uint16_t nFactor, uint16_t mFactor, uint16_t fcwF); - rsi_error_t (*clk_i2s_pll_clk_set)(M4CLK_Type *pCLK); + rsi_error_t (*clk_i2s_pll_clk_set)(const M4CLK_Type *pCLK); rsi_error_t (*clk_i2s_pll_clk_reset)(void); rsi_error_t (*clk_intf_pll_clk_enable)(boolean_t clkEnable); rsi_error_t (*clk_intf_pll_pd_enable)(boolean_t en); rsi_error_t (*clk_intf_pll_turn_off)(void); - rsi_error_t (*clk_set_intf_pll_freq)(M4CLK_Type *pCLK, uint32_t intfPllFreq, uint32_t pllRefClk); - rsi_error_t (*clk_intf_pll_set_freq_div)(M4CLK_Type *pCLK, + rsi_error_t (*clk_set_intf_pll_freq)(const M4CLK_Type *pCLK, uint32_t intfPllFreq, uint32_t pllRefClk); + rsi_error_t (*clk_intf_pll_set_freq_div)(const M4CLK_Type *pCLK, boolean_t clk_en, uint16_t divFactor, uint16_t nFactor, @@ -855,7 +855,7 @@ typedef PRE_PACK struct POST_PACK { rsi_error_t (*clk_intf_pll_clk_bypass_enable)(boolean_t clkEnable); rsi_error_t (*clk_intf_pll_turn_on)(void); rsi_error_t (*clk_intf_pll_clk_reset)(void); - rsi_error_t (*clk_intf_pll_clk_set)(M4CLK_Type *pCLK); + rsi_error_t (*clk_intf_pll_clk_set)(const M4CLK_Type *pCLK); rsi_error_t (*clk_peripheral_clk_enable1)(M4CLK_Type *pCLK, uint32_t flags); rsi_error_t (*clk_peripheral_clk_disable1)(M4CLK_Type *pCLK, uint32_t flags); rsi_error_t (*clk_peripheral_clk_enable2)(M4CLK_Type *pCLK, uint32_t flags); diff --git a/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_udma.h b/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_udma.h index dece16e15..2a8ffbfea 100644 --- a/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_udma.h +++ b/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_udma.h @@ -111,7 +111,7 @@ extern "C" { * @return \ref RSI_OK if no errors occurred, or an error code */ STATIC INLINE rsi_error_t RSI_UDMA_SetupChannelTransfer(RSI_UDMA_HANDLE_T pHandle, - RSI_UDMA_CHA_CFG_T *pCfg, + const RSI_UDMA_CHA_CFG_T *pCfg, RSI_UDMA_CHA_CONFIG_DATA_T vsUdmaChaConfigData, void *pSrcAddr, void *pDstAddr) @@ -166,7 +166,7 @@ STATIC INLINE rsi_error_t RSI_UDMA_SetChannelScatterGatherTransfer(RSI_UDMA_HAND complete, then 0 is returned. */ STATIC INLINE uint32_t RSI_UDMA_GetChannelTransferLength(RSI_UDMA_HANDLE_T pHandle, - RSI_UDMA_CHA_CFG_T *pCfg, + const RSI_UDMA_CHA_CFG_T *pCfg, RSI_UDMA_CHA_CONFIG_DATA_T vsUDMAChaConfigData) { #if defined(UDMA_ROMDRIVER_PRESENT) @@ -177,7 +177,7 @@ STATIC INLINE uint32_t RSI_UDMA_GetChannelTransferLength(RSI_UDMA_HANDLE_T pHand } /** - * @fn STATIC INLINE uint32_t RSI_UDMA_GetChannelTransferMode(RSI_UDMA_HANDLE_T pHandle, RSI_UDMA_CHA_CFG_T *pCfg) + * @fn STATIC INLINE uint32_t RSI_UDMA_GetChannelTransferMode(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg) * @brief Gets the transfer mode for a UDMA channel control structure. * @param[in] pHandle : Pointer to driver context handle * @param[in] pCfg : Pointer to DMA channel configuration structure \RSI_UDMA_CHA_CFG_T required parameter below @@ -198,7 +198,7 @@ STATIC INLINE uint32_t RSI_UDMA_GetChannelTransferLength(RSI_UDMA_HANDLE_T pHand - \ref UDMA_MODE_PER_SCATTER_GATHER */ -STATIC INLINE uint32_t RSI_UDMA_GetChannelTransferMode(RSI_UDMA_HANDLE_T pHandle, RSI_UDMA_CHA_CFG_T *pCfg) +STATIC INLINE uint32_t RSI_UDMA_GetChannelTransferMode(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg) { #if defined(UDMA_ROMDRIVER_PRESENT) return ROMAPI_UDMA_API->udma_get_channel_transfer_mode(pHandle, pCfg); @@ -239,7 +239,7 @@ STATIC INLINE RSI_UDMA_HANDLE_T RSI_UDMA_Init(void *mem, const RSI_UDMA_INIT_T * - \ref dmaCh :dma channel number(0-31) * @return - \ref RSI_OK if no errors occurred, or an error code */ -STATIC INLINE rsi_error_t RSI_UDMA_SetupChannel(RSI_UDMA_HANDLE_T pHandle, RSI_UDMA_CHA_CFG_T *pCfg) +STATIC INLINE rsi_error_t RSI_UDMA_SetupChannel(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg) { #if defined(UDMA_ROMDRIVER_PRESENT) return ROMAPI_UDMA_API->udma_setup_channel(pHandle, pCfg); @@ -248,13 +248,13 @@ STATIC INLINE rsi_error_t RSI_UDMA_SetupChannel(RSI_UDMA_HANDLE_T pHandle, RSI_U #endif } /** - * @fn STATIC INLINE void RSI_UDMA_DeInit(RSI_UDMA_HANDLE_T pHandle, RSI_UDMA_CHA_CFG_T *pCfg) + * @fn STATIC INLINE void RSI_UDMA_DeInit(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg) * @brief This API is used to Uninitialized driver context parameters * @param[in] pHandle : Pointer to driver context handle * @param[in] pCfg : Pointer to DMA channel configuration structure * @return none */ -STATIC INLINE void RSI_UDMA_DeInit(RSI_UDMA_HANDLE_T pHandle, RSI_UDMA_CHA_CFG_T *pCfg) +STATIC INLINE void RSI_UDMA_DeInit(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg) { #if defined(UDMA_ROMDRIVER_PRESENT) ROMAPI_UDMA_API->udma_deInit(pHandle, pCfg); @@ -299,7 +299,7 @@ STATIC INLINE rsi_error_t RSI_UDMA_InterruptEnable(RSI_UDMA_HANDLE_T pHandle, ui UDMA ROM FUNCTION PROTOTYPES **************************************************************************************/ rsi_error_t RSI_UDMA_SetupChannelTransfer(RSI_UDMA_HANDLE_T pHandle, - RSI_UDMA_CHA_CFG_T *pCfg, + const RSI_UDMA_CHA_CFG_T *pCfg, RSI_UDMA_CHA_CONFIG_DATA_T vsUdmaChaConfigData, void *pSrcAddr, void *pDstAddr); @@ -311,16 +311,16 @@ rsi_error_t RSI_UDMA_SetChannelScatterGatherTransfer(RSI_UDMA_HANDLE_T pHandle, uint32_t transferType); uint32_t RSI_UDMA_GetChannelTransferLength(RSI_UDMA_HANDLE_T pHandle, - RSI_UDMA_CHA_CFG_T *pCfg, + const RSI_UDMA_CHA_CFG_T *pCfg, RSI_UDMA_CHA_CONFIG_DATA_T vsUDMAChaConfigData); -uint32_t RSI_UDMA_GetChannelTransferMode(RSI_UDMA_HANDLE_T pHandle, RSI_UDMA_CHA_CFG_T *pCfg); +uint32_t RSI_UDMA_GetChannelTransferMode(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg); RSI_UDMA_HANDLE_T RSI_UDMA_Init(void *mem, const RSI_UDMA_INIT_T *pInit); -rsi_error_t RSI_UDMA_SetupChannel(RSI_UDMA_HANDLE_T pHandle, RSI_UDMA_CHA_CFG_T *pCfg); +rsi_error_t RSI_UDMA_SetupChannel(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg); -void RSI_UDMA_DeInit(RSI_UDMA_HANDLE_T pHandle, RSI_UDMA_CHA_CFG_T *pCfg); +static void RSI_UDMA_DeInit(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg); void RSI_UDMA_Interrupthandler(RSI_UDMA_HANDLE_T pHandle); diff --git a/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_udma_wrapper.h b/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_udma_wrapper.h index 16802b7a1..422664c2d 100644 --- a/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_udma_wrapper.h +++ b/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_udma_wrapper.h @@ -38,7 +38,7 @@ extern "C" { #endif -STATIC INLINE RSI_UDMA_HANDLE_T UDMAx_Initialize(UDMA_RESOURCES *udma, +STATIC INLINE RSI_UDMA_HANDLE_T UDMAx_Initialize(const UDMA_RESOURCES *udma, RSI_UDMA_DESC_T *UDMA_Table, RSI_UDMA_HANDLE_T udmaHandle, uint32_t *mem) @@ -50,7 +50,7 @@ STATIC INLINE RSI_UDMA_HANDLE_T UDMAx_Initialize(UDMA_RESOURCES *udma, #endif } -STATIC INLINE int32_t UDMAx_Uninitialize(UDMA_RESOURCES *udma) +STATIC INLINE int32_t UDMAx_Uninitialize(const UDMA_RESOURCES *udma) { #if defined(UDMA_ROMDRIVER_PRESENT) && defined(A11_ROM) return ROMAPI_UDMA_WRAPPER_API->uDMAx_Uninitialize(udma); @@ -59,13 +59,13 @@ STATIC INLINE int32_t UDMAx_Uninitialize(UDMA_RESOURCES *udma) #endif } -STATIC INLINE int32_t UDMAx_ChannelConfigure(UDMA_RESOURCES *udma, +STATIC INLINE int32_t UDMAx_ChannelConfigure(const UDMA_RESOURCES *udma, uint8_t ch, uint32_t src_addr, uint32_t dest_addr, uint32_t size, RSI_UDMA_CHA_CONFIG_DATA_T control, - RSI_UDMA_CHA_CFG_T *config, + const RSI_UDMA_CHA_CFG_T *config, UDMA_SignalEvent_t cb_event, UDMA_Channel_Info *chnl_info, RSI_UDMA_HANDLE_T udmaHandle) @@ -85,7 +85,7 @@ STATIC INLINE int32_t UDMAx_ChannelConfigure(UDMA_RESOURCES *udma, #endif } -STATIC INLINE int32_t UDMAx_ChannelEnable(uint8_t ch, UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle) +STATIC INLINE int32_t UDMAx_ChannelEnable(uint8_t ch, const UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle) { #if defined(UDMA_ROMDRIVER_PRESENT) && defined(A11_ROM) @@ -95,7 +95,7 @@ STATIC INLINE int32_t UDMAx_ChannelEnable(uint8_t ch, UDMA_RESOURCES *udma, RSI_ #endif } -STATIC INLINE int32_t UDMAx_DMAEnable(UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle) +STATIC INLINE int32_t UDMAx_DMAEnable(const UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle) { #if defined(UDMA_ROMDRIVER_PRESENT) && defined(A11_ROM) return ROMAPI_UDMA_WRAPPER_API->uDMAx_DMAEnable(udma, udmaHandle); @@ -104,7 +104,7 @@ STATIC INLINE int32_t UDMAx_DMAEnable(UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T ud #endif } -STATIC INLINE int32_t UDMAx_ChannelDisable(uint8_t ch, UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle) +STATIC INLINE int32_t UDMAx_ChannelDisable(uint8_t ch, const UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle) { #if defined(UDMA_ROMDRIVER_PRESENT) && defined(A11_ROM) return ROMAPI_UDMA_WRAPPER_API->uDMAx_ChannelDisable(ch, udma, udmaHandle); @@ -116,7 +116,7 @@ STATIC INLINE int32_t UDMAx_ChannelDisable(uint8_t ch, UDMA_RESOURCES *udma, RSI STATIC INLINE uint32_t UDMAx_ChannelGetCount(uint8_t ch, RSI_UDMA_CHA_CONFIG_DATA_T control, RSI_UDMA_CHA_CFG_T config, - UDMA_RESOURCES *udma, + const UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle) { #if defined(UDMA_ROMDRIVER_PRESENT) && defined(A11_ROM) diff --git a/components/device/silabs/si91x/mcu/drivers/service/clock_manager/src/sl_si91x_clock_manager.c b/components/device/silabs/si91x/mcu/drivers/service/clock_manager/src/sl_si91x_clock_manager.c index b233c3531..3c0d0222f 100644 --- a/components/device/silabs/si91x/mcu/drivers/service/clock_manager/src/sl_si91x_clock_manager.c +++ b/components/device/silabs/si91x/mcu/drivers/service/clock_manager/src/sl_si91x_clock_manager.c @@ -34,13 +34,14 @@ /************************************************************************************ ************************* DEFINES / MACROS *************************************** ************************************************************************************/ -#define MANUAL_LOCK 1 // Manual lock enable -#define BYPASS_MANUAL_LOCK 1 // Bypass manual lock enable -#define SOC_PLL_MM_COUNT_LIMIT 0xA4 // Soc pll count limit -#define DIVISION_FACTOR 0 // Division factor -#define QSPI_ODD_DIV_ENABLE 0 // Odd division enable for QSPI clock -#define QSPI_SWALLO_ENABLE 0 // Swallo enable for QSPI clock -#define QSPI_DIVISION_FACTOR 0 // Division factor for QSPI clock +#define MANUAL_LOCK 1 // Manual lock enable +#define BYPASS_MANUAL_LOCK 1 // Bypass manual lock enable +#define SOC_PLL_MM_COUNT_LIMIT 0xA4 // Soc pll count limit +#define DIVISION_FACTOR 0 // Division factor +#define QSPI_ODD_DIV_ENABLE 0 // Odd division enable for QSPI clock +#define QSPI_SWALLO_ENABLE 0 // Swallo enable for QSPI clock +#define QSPI_DIVISION_FACTOR 0 // Division factor for QSPI clock +#define PLL_PREFETCH_LIMIT ((uint32_t)(120000000)) // 120 MHz Limit for pll clock /************************************************************************************ ************************* LOCAL VARIABLES **************************************** ************************************************************************************/ @@ -128,6 +129,11 @@ sl_status_t sl_si91x_clock_manager_set_pll_freq(PLL_TYPE_T pll_type, uint32_t pl rsi_error_t error_status = RSI_OK; sl_status_t status; + // Configure the registers for clock more than 120 MHz in PS4 + if (pll_ref_clk >= PLL_PREFETCH_LIMIT) { + RSI_PS_PS4SetRegisters(); + } + switch (pll_type) { case SOC_PLL: // Configure SOC-PLL lock settings before configuring SOC PLL clock diff --git a/components/device/silabs/si91x/mcu/drivers/service/cpc/src/sl_cpc_drv_secondary_spi.c b/components/device/silabs/si91x/mcu/drivers/service/cpc/src/sl_cpc_drv_secondary_spi.c index 3aac27938..aa3026bbc 100644 --- a/components/device/silabs/si91x/mcu/drivers/service/cpc/src/sl_cpc_drv_secondary_spi.c +++ b/components/device/silabs/si91x/mcu/drivers/service/cpc/src/sl_cpc_drv_secondary_spi.c @@ -363,6 +363,8 @@ void SPI_CS_GPIO_PIN_FINT_IRQ_HANDLER(void) */ void sli_cpc_spi_drv_callback_slave(uint32_t event) { + // Clearing the instance number to evaluate the event + event &= SSI_INSTANCE_MASK; switch (event) { case ARM_SPI_EVENT_TRANSFER_COMPLETE: { // debug purpose diff --git a/components/device/silabs/si91x/mcu/drivers/service/iostream/config/si91x/sl_iostream_usart_vcom_config.h b/components/device/silabs/si91x/mcu/drivers/service/iostream/config/si91x/sl_iostream_usart_vcom_config.h index 52b6321c2..ef30f2f1a 100644 --- a/components/device/silabs/si91x/mcu/drivers/service/iostream/config/si91x/sl_iostream_usart_vcom_config.h +++ b/components/device/silabs/si91x/mcu/drivers/service/iostream/config/si91x/sl_iostream_usart_vcom_config.h @@ -64,7 +64,6 @@ // 6 data bits // 7 data bits // 8 data bits -// 9 data bits // Default: SL_USART_DATA_BITS_8 #define SL_IOSTREAM_USART_VCOM_DATA_BITS SL_USART_DATA_BITS_8 diff --git a/components/device/silabs/si91x/mcu/drivers/service/iostream/src/sl_iostream_usart_si91x.c b/components/device/silabs/si91x/mcu/drivers/service/iostream/src/sl_iostream_usart_si91x.c index 1542160f2..5d0e17402 100644 --- a/components/device/silabs/si91x/mcu/drivers/service/iostream/src/sl_iostream_usart_si91x.c +++ b/components/device/silabs/si91x/mcu/drivers/service/iostream/src/sl_iostream_usart_si91x.c @@ -42,13 +42,11 @@ #include #include #include "sl_si91x_usart.h" -#include "sl_si91x_clock_manager.h" /******************************************************************************* ******************************* DEFINES *********************************** ******************************************************************************/ -#define SOC_PLL_CLK ((uint32_t)(180000000)) // 180MHz default SoC PLL Clock as source to Processor -#define INTF_PLL_CLK ((uint32_t)(180000000)) // 180MHz default Interface PLL Clock as source to all peripherals + /******************************************************************************* ************************** GLOBAL VARIABLES ******************************* ******************************************************************************/ @@ -73,19 +71,6 @@ static sl_status_t usart_tx(void *context, char c); static sl_status_t usart_deinit(void *context); -static void default_clock_configuration(void); - -// Function to configure clock on powerup -static void default_clock_configuration(void) -{ - // Core Clock runs at 180MHz SOC PLL Clock - sl_si91x_clock_manager_m4_set_core_clk(M4_SOCPLLCLK, SOC_PLL_CLK); - - // All peripherals' source to be set to Interface PLL Clock - // and it runs at 180MHz - sl_si91x_clock_manager_set_pll_freq(INFT_PLL, INTF_PLL_CLK, PLL_REF_CLK_VAL_XTAL); -} - /******************************************************************************* ************************** GLOBAL FUNCTIONS ******************************* ******************************************************************************/ @@ -162,9 +147,6 @@ sl_status_t sl_iostream_usart_init(sl_iostream_uart_t *iostream_uart, { sl_status_t status; - // default clock configuration - default_clock_configuration(); - status = sli_iostream_uart_context_init(iostream_uart, &usart_context->context, uart_config, diff --git a/components/device/silabs/si91x/mcu/drivers/service/littlefs/component/sl_si91x_littlefs.slcc b/components/device/silabs/si91x/mcu/drivers/service/littlefs/component/sl_si91x_littlefs.slcc index d11913235..5707c9e30 100644 --- a/components/device/silabs/si91x/mcu/drivers/service/littlefs/component/sl_si91x_littlefs.slcc +++ b/components/device/silabs/si91x/mcu/drivers/service/littlefs/component/sl_si91x_littlefs.slcc @@ -17,6 +17,8 @@ requires: - name: romdriver_qspi template_contribution: - name: littlefs_enable - value: true + value: true + - name: max_flash_size + value: 2088960 #0x1fe000 provides: - name: sl_si91x_littlefs \ No newline at end of file diff --git a/components/device/silabs/si91x/mcu/drivers/service/nvm3/component/sl_si91x_common_flash_nvm3.slcc b/components/device/silabs/si91x/mcu/drivers/service/nvm3/component/sl_si91x_common_flash_nvm3.slcc index 147cac8e2..e7286a8d5 100644 --- a/components/device/silabs/si91x/mcu/drivers/service/nvm3/component/sl_si91x_common_flash_nvm3.slcc +++ b/components/device/silabs/si91x/mcu/drivers/service/nvm3/component/sl_si91x_common_flash_nvm3.slcc @@ -41,5 +41,7 @@ template_contribution: value: true - name: ram_execution value: true + - name: max_flash_size + value: 2088960 #0x1fe000 provides: - name: sl_si91x_common_flash_nvm3 \ No newline at end of file diff --git a/components/device/silabs/si91x/mcu/drivers/service/nvm3/component/sl_si91x_dual_flash_nvm3.slcc b/components/device/silabs/si91x/mcu/drivers/service/nvm3/component/sl_si91x_dual_flash_nvm3.slcc index 87dc858d5..a8f0c134a 100644 --- a/components/device/silabs/si91x/mcu/drivers/service/nvm3/component/sl_si91x_dual_flash_nvm3.slcc +++ b/components/device/silabs/si91x/mcu/drivers/service/nvm3/component/sl_si91x_dual_flash_nvm3.slcc @@ -35,5 +35,7 @@ requires: template_contribution: - name: nvm3_enable value: true + - name: max_flash_size + value: 2088960 #0x1fe000 provides: - name: sl_si91x_dual_flash_nvm3 \ No newline at end of file diff --git a/components/device/silabs/si91x/mcu/drivers/service/nvm3/inc/rsi_wlan_config.h b/components/device/silabs/si91x/mcu/drivers/service/nvm3/inc/rsi_wlan_config.h index 0b6856b21..db8eb284e 100644 --- a/components/device/silabs/si91x/mcu/drivers/service/nvm3/inc/rsi_wlan_config.h +++ b/components/device/silabs/si91x/mcu/drivers/service/nvm3/inc/rsi_wlan_config.h @@ -53,14 +53,14 @@ #define RSI_EXT_CUSTOM_FEATURE_BIT_MAP SL_SI91X_RAM_LEVEL_NWP_MEDIUM_MCU_MEDIUM #endif #else -#define RSI_EXT_CUSTOM_FEATURE_BIT_MAP SL_SI91X_RAM_LEVEL_NWP_ALL_MCU_ZERO +#define RSI_EXT_CUSTOM_FEATURE_BIT_MAP SL_SI91X_RAM_LEVEL_NWP_ALL_AVAILABLE #endif //! To set Extended TCPIP feature select bit map #define RSI_EXT_TCPIP_FEATURE_BITMAP (EXT_FEAT_HTTP_OTAF_SUPPORT | EXT_TCP_IP_SSL_16K_RECORD) //! Extended custom feature is selected internally //! SoC -- SL_SI91X_RAM_LEVEL_NWP_MEDIUM_MCU_MEDIUM -//! NCP -- SL_SI91X_RAM_LEVEL_NWP_ALL_MCU_ZERO +//! NCP -- SL_SI91X_RAM_LEVEL_NWP_ALL_AVAILABLE /*=======================================================================*/ //! Feature frame parameters /*=======================================================================*/ diff --git a/components/device/silabs/si91x/mcu/drivers/service/nvm3/src/sl_si91x_common_flash_intf.c b/components/device/silabs/si91x/mcu/drivers/service/nvm3/src/sl_si91x_common_flash_intf.c index 6faa19990..531fecd9f 100644 --- a/components/device/silabs/si91x/mcu/drivers/service/nvm3/src/sl_si91x_common_flash_intf.c +++ b/components/device/silabs/si91x/mcu/drivers/service/nvm3/src/sl_si91x_common_flash_intf.c @@ -21,6 +21,9 @@ #include "sl_si91x_driver.h" #include "sl_core.h" #include "cmsis_os2.h" +#if defined(SL_SI91X_TICKLESS_MODE) && (SL_SI91X_TICKLESS_MODE == 1) +#include "sl_si91x_power_manager.h" +#endif /******************************************************************************* *************************** DEFINES / MACROS ******************************** @@ -81,8 +84,17 @@ bool rsi_flash_erase_sector(uint32_t *sector_address) int status = 0; uint8_t dummy_buff[10] = { 0 }; + +#if defined(SL_SI91X_TICKLESS_MODE) && (SL_SI91X_TICKLESS_MODE == 1) + sl_si91x_power_manager_add_ps_requirement(SL_SI91X_POWER_MANAGER_PS4); +#endif + //Erase sector status = (int)sl_si91x_command_to_write_common_flash((uint32_t)sector_address, dummy_buff, SECTOR_SIZE, FLASH_ERASE); + +#if defined(SL_SI91X_TICKLESS_MODE) && (SL_SI91X_TICKLESS_MODE == 1) + sl_si91x_power_manager_remove_ps_requirement(SL_SI91X_POWER_MANAGER_PS4); +#endif return status; } @@ -93,8 +105,17 @@ bool rsi_flash_write(uint32_t *address, unsigned char *data, uint32_t length) { int status = 0; + +#if defined(SL_SI91X_TICKLESS_MODE) && (SL_SI91X_TICKLESS_MODE == 1) + sl_si91x_power_manager_add_ps_requirement(SL_SI91X_POWER_MANAGER_PS4); +#endif + //Write to flash status = (int)sl_si91x_command_to_write_common_flash((uint32_t)address, data, (uint16_t)length, FLASH_WRITE); + +#if defined(SL_SI91X_TICKLESS_MODE) && (SL_SI91X_TICKLESS_MODE == 1) + sl_si91x_power_manager_remove_ps_requirement(SL_SI91X_POWER_MANAGER_PS4); +#endif return status; } diff --git a/components/device/silabs/si91x/mcu/drivers/service/power_manager/component/wakeup_source_config.slcc b/components/device/silabs/si91x/mcu/drivers/service/power_manager/component/wakeup_source_config.slcc index 85b341673..7aac32910 100644 --- a/components/device/silabs/si91x/mcu/drivers/service/power_manager/component/wakeup_source_config.slcc +++ b/components/device/silabs/si91x/mcu/drivers/service/power_manager/component/wakeup_source_config.slcc @@ -4,6 +4,10 @@ package: platform description: > Wakeup Source Configuration component will enable the NPSS peripherals as wakeup source. This also initializes the peripheral and configure as a wakeup source as per the selection in User Configuration. + + Install the appropriate component based on the configured wakeup source. + + Note: The default sleep time for the deep sleep timer is 10 ms because reducing it further does not result in any decrease in sleep current. category: Device|Si91x|MCU|Service|Power Manager quality: production component_root_path: "components/device/silabs/si91x/mcu/drivers/service/power_manager" diff --git a/components/device/silabs/si91x/mcu/drivers/service/power_manager/config/sl_si91x_power_manager_wakeup_source_config.h b/components/device/silabs/si91x/mcu/drivers/service/power_manager/config/sl_si91x_power_manager_wakeup_source_config.h index f1ad2de68..56017eb52 100644 --- a/components/device/silabs/si91x/mcu/drivers/service/power_manager/config/sl_si91x_power_manager_wakeup_source_config.h +++ b/components/device/silabs/si91x/mcu/drivers/service/power_manager/config/sl_si91x_power_manager_wakeup_source_config.h @@ -48,10 +48,6 @@ extern "C" { // Default: 1 #define ENABLE_ALARM 0 -// Enable Milli Second Wakeup Source -// Default: 0 -#define ENABLE_MSEC 0 - // Alarm Time (in milliseconds) // Default: 5000 #define ALARM_TIME_MSEC 5000 @@ -78,16 +74,12 @@ extern "C" { #define ENABLE_NPSS_GPIO_3 0 // -// WDT Wakeup -#define SL_ENABLE_WDT_WAKEUP_SOURCE 0 -// - // Deep Sleep Timer Wakeup #define SL_ENABLE_DST_WAKEUP_SOURCE 0 -// Sleep Time (in microseconds) -// Default: 500 -#define DST_WAKEUP_TIME 500 +// Sleep Time (in microseconds) <10000-4294967295> +// Default: 10000 +#define DST_WAKEUP_TIME 10000 // diff --git a/components/device/silabs/si91x/mcu/drivers/service/power_manager/src/sl_si91x_power_manager.c b/components/device/silabs/si91x/mcu/drivers/service/power_manager/src/sl_si91x_power_manager.c index 111d4cf71..573ea3121 100644 --- a/components/device/silabs/si91x/mcu/drivers/service/power_manager/src/sl_si91x_power_manager.c +++ b/components/device/silabs/si91x/mcu/drivers/service/power_manager/src/sl_si91x_power_manager.c @@ -80,7 +80,8 @@ static void notify_power_state_transition(sl_power_state_t from, sl_power_state_ /******************************************************************************* *********************** Global function Definitions ************************* ******************************************************************************/ - +bool sli_si91x_is_sdk_ok_to_sleep(); +bool sli_si91x_ta_packet_initiated_to_m4(void); /******************************************************************************* * Initializes the Power Manager Service. * If service is not already initialized, then initialize the linked list and @@ -217,9 +218,6 @@ sl_status_t sl_si91x_power_manager_sleep(void) { sl_status_t status; -#ifdef SL_SLEEP_TIMER - RSI_PS_SetWkpSources(SYSRTC_BASED_WAKEUP); -#endif if (!sli_si91x_power_manager_is_valid_transition(current_state, SL_SI91X_POWER_MANAGER_SLEEP)) { // Validates the state transition for sleep, if invalid returns error code. return SL_STATUS_INVALID_STATE; @@ -229,9 +227,11 @@ sl_status_t sl_si91x_power_manager_sleep(void) // returns error code. return SL_STATUS_NOT_INITIALIZED; } +#if (SL_SI91X_TICKLESS_MODE == 0) if (!sl_si91x_power_manager_is_ok_to_sleep()) { return SL_STATUS_BUSY; } +#endif do { // Internal function to change active mode to sleep mode is called. // It sets the required configurations and goes into sleep mode. @@ -515,7 +515,7 @@ static void notify_power_state_transition(sl_power_state_t from, sl_power_state_ * @return True, if the system should actually sleep. * False, if not. * - * @note This is the fallback implementation of the callback, it can be + * @note This is the fall back implementation of the callback, it can be * overridden by the application or other components. ******************************************************************************/ boolean_t sl_si91x_power_manager_is_ok_to_sleep(void) @@ -524,8 +524,9 @@ boolean_t sl_si91x_power_manager_is_ok_to_sleep(void) #if (configUSE_TICKLESS_IDLE == 1) sl_wifi_performance_profile_t pm_ta_performance_profile; sl_wifi_get_performance_profile(&pm_ta_performance_profile); - if (SL_SI91X_POWER_MANAGER_SLEEP == sl_si91x_get_lowest_ps()) { - if (pm_ta_performance_profile.profile != STANDBY_POWER_SAVE) { + if (pm_ta_performance_profile.profile != STANDBY_POWER_SAVE) { + if ((SL_SI91X_POWER_MANAGER_SLEEP == sl_si91x_get_lowest_ps()) && (sli_si91x_is_sdk_ok_to_sleep()) + && (sli_si91x_ta_packet_initiated_to_m4())) { is_sleep_ready = true; } else { } @@ -535,6 +536,7 @@ boolean_t sl_si91x_power_manager_is_ok_to_sleep(void) #endif return is_sleep_ready; } + /***************************************************************************/ /** * Returns the Lowest possible power state from the requirement table. * It validates all the power state requirements and return the lowest possible state transition. diff --git a/components/device/silabs/si91x/mcu/drivers/service/power_manager/src/sli_si91x_power_manager.c b/components/device/silabs/si91x/mcu/drivers/service/power_manager/src/sli_si91x_power_manager.c index 7b5325746..e8d1e38e8 100644 --- a/components/device/silabs/si91x/mcu/drivers/service/power_manager/src/sli_si91x_power_manager.c +++ b/components/device/silabs/si91x/mcu/drivers/service/power_manager/src/sli_si91x_power_manager.c @@ -60,7 +60,7 @@ #define MAX_M4SS_RAM_SIZE 320 // Maximum m4ss RAM size #endif #define MAX_ULPSS_RAM_SIZE 8 // Maximum ulpss RAM size -#define SOC_PLL_REF_FREQUENCY 32000000 // SOC Pll reference frequency +#define SOC_PLL_REF_FREQUENCY 40000000 // SOC Pll reference frequency #define PS4_HP_FREQUENCY 100000000 // PS4 high power clock frequency #define PS4_LP_FREQUENCY 32000000 // PS4 low power clock frequency #define PS3_HP_FREQUENCY 80000000 // PS3 high power clock frequency @@ -237,7 +237,13 @@ sl_status_t sli_si91x_power_manager_set_sleep_configuration(sl_power_state_t sta // Low power hardware configuration to switch off the components which are not required. low_power_hardware_configuration(true); } - +#if (SL_SI91X_TICKLESS_MODE == 1) +#ifdef SL_SLEEP_TIMER + RSI_PS_SetWkpSources(SYSRTC_BASED_WAKEUP); //Setting SYSRTC as a wakeup source +#endif + MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE |= + WIRELESS_BASED_WAKEUP; //Configured wireless based wakeup as wakeup source +#endif #ifdef SL_SI91X_POWER_MANAGER_UC_AVAILABLE // Initializing and configuring the wakeup sources as per UC inputs, if available sl_si91x_power_manager_wakeup_init(); @@ -456,23 +462,11 @@ sl_status_t sli_si91x_power_manager_configure_clock(sl_power_state_t state, bool RSI_CLK_M4SocClkConfig(M4CLK, M4_ULPREFCLK, DIVISION_FACTOR); // Configures the required registers for 180 Mhz clock in PS4 RSI_PS_PS4SetRegisters(); -#if defined(SLI_WIRELESS_COMPONENT_PRESENT) && (SLI_WIRELESS_COMPONENT_PRESENT == 1) - // XTAL is required for configuring the SOC-PLL - //wakeup TA - P2P_STATUS_REG |= M4_WAKEUP_TA; - //wait for TA active - while (!(P2P_STATUS_REG & TA_IS_ACTIVE)) - ; -#endif // Configure the PLL frequency // Configure the SOC PLL to 180MHz RSI_CLK_SetSocPllFreq(M4CLK, PS4_HP_FREQUENCY, SOC_PLL_REF_FREQUENCY); // Switch M4 clock to PLL clock for speed operations RSI_CLK_M4SocClkConfig(M4CLK, M4_SOCPLLCLK, DIVISION_FACTOR); -#if defined(SLI_WIRELESS_COMPONENT_PRESENT) && (SLI_WIRELESS_COMPONENT_PRESENT == 1) - // Indicate TA that M4 does not have dependency on TA and TA can go to sleep - P2P_STATUS_REG &= ~M4_WAKEUP_TA; -#endif } else { // Default keep M4 in reference clock RSI_CLK_M4SocClkConfig(M4CLK, M4_ULPREFCLK, DIVISION_FACTOR); @@ -482,24 +476,11 @@ sl_status_t sli_si91x_power_manager_configure_clock(sl_power_state_t state, bool if (mode) { // Default keep M4 in reference clock RSI_CLK_M4SocClkConfig(M4CLK, M4_ULPREFCLK, DIVISION_FACTOR); - -#if defined(SLI_WIRELESS_COMPONENT_PRESENT) && (SLI_WIRELESS_COMPONENT_PRESENT == 1) - // XTAL is required for configuring the SOC-PLL - //wakeup TA - P2P_STATUS_REG |= M4_WAKEUP_TA; - //wait for TA active - while (!(P2P_STATUS_REG & TA_IS_ACTIVE)) - ; -#endif // Configure the PLL frequency // Configure the SOC PLL to 80MHz RSI_CLK_SetSocPllFreq(M4CLK, PS3_HP_FREQUENCY, SOC_PLL_REF_FREQUENCY); // Switch M4 clock to PLL clock for speed operations RSI_CLK_M4SocClkConfig(M4CLK, M4_SOCPLLCLK, DIVISION_FACTOR); -#if defined(SLI_WIRELESS_COMPONENT_PRESENT) && (SLI_WIRELESS_COMPONENT_PRESENT == 1) - // Indicate TA that M4 does not have dependency on TA and TA can go to sleep - P2P_STATUS_REG &= ~M4_WAKEUP_TA; -#endif } else { // Default keep M4 in reference clock RSI_CLK_M4SocClkConfig(M4CLK, M4_ULPREFCLK, DIVISION_FACTOR); @@ -775,8 +756,55 @@ static sl_status_t trigger_sleep(sli_power_sleep_config_t *config, uint8_t sleep config->wakeup_callback_address, config->vector_offset, config->mode); +#if SL_WIFI_COMPONENT_INCLUDED + if (!(M4_ULP_SLP_STATUS_REG & ULP_MODE_SWITCHED_NPSS)) { + + if (sl_si91x_is_device_initialized()) { + /* Check whether M4 is using XTAL */ + if (sli_si91x_is_xtal_in_use_by_m4() == true) { + if (system_clocks.soc_pll_clock != DEFAULT_SOC_PLL_CLOCK) { + /* TurnOff the SOC_PLL */ + RSI_CLK_SocPllTurnOff(); + } + + if (system_clocks.intf_pll_clock != DEFAULT_INTF_PLL_CLOCK) { + /* TurnOff the INTF_PLL */ + RSI_CLK_IntfPLLTurnOff(); + } + + if (system_clocks.i2s_pll_clock != DEFAULT_I2S_PLL_CLOCK) { + /* TurnOff the I2S_PLL */ + RSI_CLK_I2sPllTurnOff(); + } + + /* If M4 is using XTAL then request TA to turn OFF XTAL as M4 is going to sleep */ + sli_si91x_raise_xtal_interrupt_to_ta(TURN_OFF_XTAL_REQUEST); + } + } + } +#endif // According to the sleep type, with retention or without retention it enters the sleep mode. error_code = RSI_PS_EnterDeepSleep(sleep_type, config->low_freq_clock); + +#if SL_WIFI_COMPONENT_INCLUDED + if (!(M4_ULP_SLP_STATUS_REG & ULP_MODE_SWITCHED_NPSS)) { + + if (system_clocks.soc_pll_clock != DEFAULT_SOC_PLL_CLOCK) { + /* TurnON the SOC_PLL */ + RSI_CLK_SocPllTurnOn(); + } + + if (system_clocks.intf_pll_clock != DEFAULT_INTF_PLL_CLOCK) { + /* TurnON the INTF_PLL */ + RSI_CLK_IntfPLLTurnOn(); + } + + if (system_clocks.i2s_pll_clock != DEFAULT_I2S_PLL_CLOCK) { + /* TurnON the I2S_PLL */ + RSI_CLK_I2sPllTurnOn(); + } + } +#endif // If error is encountered, it is converted to sl error code. status = convert_rsi_to_sl_error_code(error_code); return status; diff --git a/components/device/silabs/si91x/mcu/drivers/service/power_manager/src/sli_si91x_power_manager_wakeup_init.c b/components/device/silabs/si91x/mcu/drivers/service/power_manager/src/sli_si91x_power_manager_wakeup_init.c index 0cace45af..6545278e6 100644 --- a/components/device/silabs/si91x/mcu/drivers/service/power_manager/src/sli_si91x_power_manager_wakeup_init.c +++ b/components/device/silabs/si91x/mcu/drivers/service/power_manager/src/sli_si91x_power_manager_wakeup_init.c @@ -381,8 +381,12 @@ static sl_status_t uulp_gpio_configuration(uint8_t pin) status = SL_STATUS_INVALID_PARAMETER; return status; } - GPIO_NPSS_GPIO_CONFIG_REG = CLR; //By default making all the interrupts zero. - status = sl_si91x_gpio_driver_select_uulp_npss_receiver(pin, SET); + // Unregister NPSS GPIO interrupts + status = sl_gpio_driver_unregister(UULP_GPIO_INSTANCE, pin, pin); + if (status != SL_STATUS_OK) { + return status; + } + status = sl_si91x_gpio_driver_select_uulp_npss_receiver(pin, SET); if (status != SL_STATUS_OK) { return status; } @@ -447,4 +451,4 @@ void WIRELESS_WAKEUP_IRQ() /*Clear interrupt */ RSI_PS_ClrWkpUpStatus(NPSS_TO_MCU_WIRELESS_INTR); } -#endif // SL_ENABLE_WIRELESS_WAKEUP_SOURCE +#endif // SL_ENABLE_WIRELESS_WAKEUP_SOURCE \ No newline at end of file diff --git a/components/device/silabs/si91x/mcu/drivers/service/sensorhub/src/sensor_hub.c b/components/device/silabs/si91x/mcu/drivers/service/sensorhub/src/sensor_hub.c index 2658af847..1df3e79d9 100644 --- a/components/device/silabs/si91x/mcu/drivers/service/sensorhub/src/sensor_hub.c +++ b/components/device/silabs/si91x/mcu/drivers/service/sensorhub/src/sensor_hub.c @@ -1840,6 +1840,8 @@ void sl_si91x_power_state_task(void) *******************************************************************************/ void mySPI_callback(uint32_t event) { + // Clearing the instance number to evaluate the event + event &= SSI_INSTANCE_MASK; switch (event) { case ARM_SPI_EVENT_TRANSFER_COMPLETE: break; diff --git a/components/device/silabs/si91x/mcu/drivers/service/sleeptimer/src/sl_sleeptimer_hal_si91x_sysrtc.c b/components/device/silabs/si91x/mcu/drivers/service/sleeptimer/src/sl_sleeptimer_hal_si91x_sysrtc.c index c85d1d6c9..44fa1294e 100644 --- a/components/device/silabs/si91x/mcu/drivers/service/sleeptimer/src/sl_sleeptimer_hal_si91x_sysrtc.c +++ b/components/device/silabs/si91x/mcu/drivers/service/sleeptimer/src/sl_sleeptimer_hal_si91x_sysrtc.c @@ -83,8 +83,14 @@ void sleeptimer_hal_init_timer(void) const rsi_sysrtc_group_channel_compare_config_t group_compare_channel_config = SYSRTC_GROUP_CHANNEL_COMPARE_CONFIG_DEFAULT_REGMODE; +#if defined(SL_SI91X_MODULE_BOARD) + // Enable 32kHz RC clock to SYSRTC peripheral + rsi_sysrtc_clk_set(RSI_SYSRTC_CLK_32kHz_RC, 0u); +#else // Enable 32kHz XTAL clock to SYSRTC peripheral rsi_sysrtc_clk_set(RSI_SYSRTC_CLK_32kHz_Xtal, 0u); +#endif // SL_SI91X_MODULE_BOARD + // Initialize SYSRTC module rsi_sysrtc_init(&sysrtc_config); @@ -298,7 +304,11 @@ void SLEEPTIMER_SI91X_INTERRUPT_HANDLER(void) uint32_t sleeptimer_hal_get_timer_frequency(void) { // There is currently no call for in Si91x library to obtain peripheral frequency of SYSRTC. +#if defined(SL_SI91X_MODULE_BOARD) + return DEFAULT_32KHZ_RC_CLOCK; +#else return DEFAULT_32KHZ_XTAL_CLOCK; +#endif // SL_SI91X_MODULE_BOARD } /******************************************************************************* diff --git a/components/device/silabs/si91x/mcu/drivers/service/wdt_manager/component/sl_wdt_manager.slcc b/components/device/silabs/si91x/mcu/drivers/service/wdt_manager/component/sl_wdt_manager.slcc new file mode 100644 index 000000000..1bd184b7b --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/service/wdt_manager/component/sl_wdt_manager.slcc @@ -0,0 +1,36 @@ +id: sl_wdt_manager +label: WDT Manager +package: platform +description: > + Initiates the WDT Manager (WDTM) component to manage the MCU's reset recovery mechanism , + provides API support for configuring wdt in the application. +category: Device|Si91x|MCU|Service +quality: production +component_root_path: "components/device/silabs/si91x/mcu/drivers/service/wdt_manager" +source: + - path: src/sl_si91x_wdt_manager.c +include: + - path: inc + file_list: + - path: sl_si91x_wdt_manager.h +requires: + - name: sl_watchdog_timer +config_file: + - path: "config/sl_si91x_wdt_config.h" +provides: + - name: sl_wdt_manager +template_contribution: + - name: event_handler + value: + event: service_init + include: sl_si91x_wdt_manager.h + handler: sl_watchdog_manager_init + priority: -1 + - name: event_handler + value: + event: service_init + include: sl_si91x_wdt_manager.h + handler: sl_watchdog_manager_start + priority: 0 +define: + - name: SL_WDT_MANAGER_PRESENT \ No newline at end of file diff --git a/components/device/silabs/si91x/mcu/drivers/service/wdt_manager/config/sl_si91x_wdt_config.h b/components/device/silabs/si91x/mcu/drivers/service/wdt_manager/config/sl_si91x_wdt_config.h new file mode 100644 index 000000000..59df26237 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/service/wdt_manager/config/sl_si91x_wdt_config.h @@ -0,0 +1,89 @@ +/***************************************************************************/ /** + * @file sl_si91x_wdt_config.h + * @brief Watchdog-Timer configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licenser of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_SI91X_WDT_CONFIG_H +#define SL_SI91X_WDT_CONFIG_H + +#include "sl_si91x_watchdog_timer.h" +#include "sl_si91x_wdt_manager.h" +#include "sl_component_catalog.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// WatchDog Timer UC Configuration +// Enable: Peripheral configuration is taken straight from the +// configuration set in the universal configuration (UC). +// Disable: If the application demands it to be modified during runtime, use the +// sl_si91x_watchdog_set_configuration API to modify the peripheral +// configuration. +// Default: 1 +#define WDT_UC 1 + +// Watchdog Timer Configuration + +// WDT Timeout Interval +// 0.0625 ms +// 0.125 ms +// 0.25 ms +// 0.5 ms +// 1 ms +// 2 ms +// 4 ms +// 8 ms +// 16 ms +// 32 ms +// 64 ms +// 128 ms +// 256 ms +// 512 ms +// 1024 ms +// 2048 ms +// 4096 ms +// 8192 ms +// 16384 ms +// 32768 ms +// 65536 ms +// 131072 ms +// 262144 ms +// 524288 ms +// 1048576 ms +// 2097152 ms +// 4194304 ms +// 8388608 ms +// 16777216 ms +// 33554432 ms +// 67108864 ms +// Selection of Interrupt Time +#define SL_SI91X_WATCHDOG_MANAGER_TIMEOUT_PERIOD SL_SI91X_WATCHDOG_MANAGER_TIMEOUT_INDEX_20 + +// +// +// <<< end of configuration section >>> + +#endif // SL_SI91X_WDT_CONFIG_H diff --git a/components/device/silabs/si91x/mcu/drivers/service/wdt_manager/inc/sl_si91x_wdt_manager.h b/components/device/silabs/si91x/mcu/drivers/service/wdt_manager/inc/sl_si91x_wdt_manager.h new file mode 100644 index 000000000..2108e68cd --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/service/wdt_manager/inc/sl_si91x_wdt_manager.h @@ -0,0 +1,203 @@ +/************************************************************************************ + * @file sl_si91x_wdt_manager.h + * @brief Watchdog Manager Service API implementation + ************************************************************************************ + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ************************************************************************************ + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ************************************************************************************/ + +#ifndef SL_SI91X_WDT_MANAGER_ +#define SL_SI91X_WDT_MANAGER_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "sl_status.h" +#include "rsi_wwdt.h" +#include "sl_si91x_watchdog_timer.h" + +/************************************************************************************ + * @addtogroup WDT-MANAGER Clock Manager + * @ingroup SI91X_SERVICE_APIS + * @{ + ************************************************************************************/ +// ----------------------------------------------------------------------------------- +// GLOBAL DEFINES / MACROS +// ----------------------------------------------------------------------------------- + +#define SL_SI91X_WAKEUP_INDICATION BIT(0) +#define SL_SI91X_TIMEOUT_WAKEUP BIT(1) +#define SL_SI91X_HOST_BASED_WAKEUP_S BIT(2) +#define SL_SI91X_MCU_PROCESSOR_WAKE_STAT BIT(4) +#define SL_SI91X_MCU_WWD_RESET BIT(5) +#define SL_SI91X_MCU_WWD_WINDOW_RESET BIT(6) +#define SL_SI91X_NWP_WWD_RESET BIT(8) +#define SL_SI91X_NWP_WWD_WINDOW_RESET BIT(9) +#define SL_SI91X_HOST_RESET_REQUEST BIT(10) + +#define SL_SI91X_WDT_RESET \ + (SL_SI91X_MCU_WWD_WINDOW_RESET | SL_SI91X_MCU_WWD_RESET | SL_SI91X_NWP_WWD_WINDOW_RESET | SL_SI91X_NWP_WWD_RESET \ + | SL_SI91X_HOST_RESET_REQUEST) + +// ----------------------------------------------------------------------------------- +// DATA TYPES +// ----------------------------------------------------------------------------------- +/// @brief Reason for the system being reset. +typedef enum { + SL_SI91X_WATCHDOG_MANAGER_RESET_POR, ///< A power-on reset was performed. + SL_SI91X_WATCHDOG_MANAGER_RESET_WATCHDOG, ///< System was reset by the watchdog manager service. + SL_SI91X_WATCHDOG_MANAGER_RESET_SOFTWARE, ///< A reset was invoked from the system firmware. + SL_SI91X_WATCHDOG_MANAGER_RESET_MAX +} sl_watchdog_manager_reset_reason_t; + +/// @brief Enumeration to represent possible time delays values for WDT interrupt time and system reset time with 32 KHZ clock freq. +typedef enum { + SL_SI91X_WATCHDOG_MANAGER_TIMEOUT_INDEX_0, ///< for time delay of 0.03125 milliseconds + SL_SI91X_WATCHDOG_MANAGER_TIMEOUT_INDEX_1, ///< for time delay of 0.0625 milliseconds + SL_SI91X_WATCHDOG_MANAGER_TIMEOUT_INDEX_2, ///< for time delay of 0.125 milliseconds + SL_SI91X_WATCHDOG_MANAGER_TIMEOUT_INDEX_3, ///< for time delay of 0.25 milliseconds + SL_SI91X_WATCHDOG_MANAGER_TIMEOUT_INDEX_4, ///< for time delay of 0.5 milliseconds + SL_SI91X_WATCHDOG_MANAGER_TIMEOUT_INDEX_5, ///< for time delay of 1 milliseconds + SL_SI91X_WATCHDOG_MANAGER_TIMEOUT_INDEX_6, ///< for time delay of 2 milliseconds + SL_SI91X_WATCHDOG_MANAGER_TIMEOUT_INDEX_7, ///< for time delay of 4 milliseconds + SL_SI91X_WATCHDOG_MANAGER_TIMEOUT_INDEX_8, ///< for time delay of 8 milliseconds + SL_SI91X_WATCHDOG_MANAGER_TIMEOUT_INDEX_9, ///< for time delay of 16 milliseconds + SL_SI91X_WATCHDOG_MANAGER_TIMEOUT_INDEX_10, ///< for time delay of 32 milliseconds + SL_SI91X_WATCHDOG_MANAGER_TIMEOUT_INDEX_11, ///< for time delay of 64 milliseconds + SL_SI91X_WATCHDOG_MANAGER_TIMEOUT_INDEX_12, ///< for time delay of 128 milliseconds + SL_SI91X_WATCHDOG_MANAGER_TIMEOUT_INDEX_13, ///< for time delay of 256 milliseconds + SL_SI91X_WATCHDOG_MANAGER_TIMEOUT_INDEX_14, ///< for time delay of 512 milliseconds + SL_SI91X_WATCHDOG_MANAGER_TIMEOUT_INDEX_15, ///< for time delay of 1.024 seconds + SL_SI91X_WATCHDOG_MANAGER_TIMEOUT_INDEX_16, ///< for time delay of 2.048 seconds + SL_SI91X_WATCHDOG_MANAGER_TIMEOUT_INDEX_17, ///< for time delay of 4.096 seconds + SL_SI91X_WATCHDOG_MANAGER_TIMEOUT_INDEX_18, ///< for time delay of 8.192 seconds + SL_SI91X_WATCHDOG_MANAGER_TIMEOUT_INDEX_19, ///< for time delay of 16.384 seconds + SL_SI91X_WATCHDOG_MANAGER_TIMEOUT_INDEX_20, ///< for time delay of 32.768 seconds + SL_SI91X_WATCHDOG_MANAGER_TIMEOUT_INDEX_21, ///< for time delay of 65.536 seconds + SL_SI91X_WATCHDOG_MANAGER_TIMEOUT_INDEX_22, ///< for time delay of 131.072 seconds + SL_SI91X_WATCHDOG_MANAGER_TIMEOUT_INDEX_23, ///< for time delay of 262.144 seconds + SL_SI91X_WATCHDOG_MANAGER_TIMEOUT_INDEX_24, ///< for time delay of 524.288 seconds + SL_SI91X_WATCHDOG_MANAGER_TIMEOUT_INDEX_25, ///< for time delay of 1048.576 seconds + SL_SI91X_WATCHDOG_MANAGER_TIMEOUT_INDEX_26, ///< for time delay of 2097.152 seconds + SL_SI91X_WATCHDOG_MANAGER_TIMEOUT_INDEX_27, ///< for time delay of 4194.304 seconds + SL_SI91X_WATCHDOG_MANAGER_TIMEOUT_INDEX_28, ///< for time delay of 8388.60 seconds + SL_SI91X_WATCHDOG_MANAGER_TIMEOUT_INDEX_29, ///< for time delay of 16777.216 seconds + SL_SI91X_WATCHDOG_MANAGER_TIMEOUT_INDEX_30, ///< for time delay of 33554.432 seconds + SL_SI91X_WATCHDOG_MANAGER_TIMEOUT_INDEX_31, ///< for time delay of 67108.864 seconds + SL_SI91X_WATCHDOG_MANAGER_TIMEOUT_INDEX_MAX, ///< for time delay value validation +} sl_watchdog_manager_wdog_timeout_t; + +// ----------------------------------------------------------------------------------- +// GLOBAL FUNCTION PROTOTYPES +// ----------------------------------------------------------------------------------- + +/***************************************************************************/ /** + * Configures the watchdog manager service. + * Configures the hardware watchdog timer. + * - The 91x watchdog peripheral's interrupt interval is set to 2 seconds less than the configured value of @ref SL_WDT_MANAGER_INTERRUPT_TIME. + * - The 91x watchdog peripheral's system reset interval is set to the configured value of @ref SL_WDT_SYSTEM_RESET_TIME. + * The hardware watchdog triggers an interrupt when this timeout expires. + * - The 91x watchdog peripheral's window interval is set almost equal to the difference between the system reset interval and interrupt interval. + * This is the period during which the software is permitted to feed the watchdog after the interrupt is triggered. + * + * @pre Pre-conditions: + * - none + * + * @param[in] none + * + * @return The following values are returned: + * - SL_STATUS_OK - Success + * - SL_STATUS_XXX - + ******************************************************************************/ +sl_status_t sl_watchdog_manager_init(void); + +/***************************************************************************/ /** + * Start the watchdog manager service. + * WDT starts counting the counter + * The hardware watchdog triggers an interrupt when WDT Timeout Interval is expired. + * + * @pre Pre-conditions: + * - \ref sl_watchdog_manager_init + * + * @param[in] none + * + * @return The following values are returned: + * - SL_STATUS_OK - Success + * - SL_STATUS_XXX - + ******************************************************************************/ +sl_status_t sl_watchdog_manager_start(void); + +/***************************************************************************/ /** + * Retrieve the system reset reason. + * Returns the reason for the system being reset. This may be invoked during a start up flow + * to determine if the system has recovered from an error condition such as a crash. + * + * @pre Pre-conditions: + * - None + * + * @param[out] reset_reason This is populated with the reason for the system being reset. This is of type @ref sl_watchdog_manager_reset_reason_t. + * + * @return The following values are returned: + * - \ref SL_SI91X_WATCHDOG_MANAGER_RESET_WATCHDOG - WDT System Reset + * - \ref SL_SI91X_WATCHDOG_MANAGER_RESET_SOFTWARE - Software System Reset + * - \ref SL_SI91X_WATCHDOG_MANAGER_RESET_POR - Power-on Reset + ******************************************************************************/ +sl_watchdog_manager_reset_reason_t sl_wdt_manager_get_system_reset_status(void); + +/***************************************************************************/ /** + * Disables the hardware watchdog in sleep mode + * The WDT counter stops running in sleep mode + * + * @pre Pre-conditions: + * - \ref sl_watchdog_manager_init + * + * @param[in] none + * + * @return none + ******************************************************************************/ +void sl_watchdog_disable_wdt_in_sleep(void); + +/***************************************************************************/ /** + * Enables the hardware watchdog in sleep mode + * The WDT counter starts running in sleep mode + * It enables the WDT as a wakeup source to the system to serve the ISR and + * kick the watchdog + * @pre Pre-conditions: + * - \ref sl_watchdog_manager_init + * + * @param[in] none + * + * @return none + ******************************************************************************/ +void sl_watchdog_enable_wdt_in_sleep(void); + +/// @} end group WDT-MANAGER ******************************************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* SL_SI91X_WDT_MANAGER */ diff --git a/components/device/silabs/si91x/mcu/drivers/service/wdt_manager/src/sl_si91x_wdt_manager.c b/components/device/silabs/si91x/mcu/drivers/service/wdt_manager/src/sl_si91x_wdt_manager.c new file mode 100644 index 000000000..3bde658d1 --- /dev/null +++ b/components/device/silabs/si91x/mcu/drivers/service/wdt_manager/src/sl_si91x_wdt_manager.c @@ -0,0 +1,239 @@ +/************************************************************************************ + * @file sl_si91x_wdt_manager.c + * @brief Watchdog Manager Service API implementation + ************************************************************************************ + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ************************************************************************************ + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ************************************************************************************/ + +#include "sl_si91x_wdt_manager.h" +#include "sl_si91x_wdt_config.h" + +#if defined(SLI_SI91X_ENABLE_OS) +#include "rsi_os.h" +#include "cmsis_os2.h" +#endif +#include "rsi_debug.h" + +/************************************************************************************ + ************************* DEFINES / MACROS *************************************** + ************************************************************************************/ +#if defined(SLI_SI91X_ENABLE_OS) +osSemaphoreId_t sl_semaphore_app_task_id; +#define SL_WDT_TASK_STACK_SIZE 512 +const osThreadAttr_t wdt_thread_attributes = { + .name = "WDT_Task", // Name of thread + .attr_bits = 0, + .cb_mem = 0, + .cb_size = 0, + .stack_mem = 0, + .stack_size = SL_WDT_TASK_STACK_SIZE, // Stack size of WDT task + .priority = osPriorityHigh7, // Priority of WDT task + .tz_module = 0, + .reserved = 0, +}; +#endif //SLI_SI91X_ENABLE_OS + +/************************************************************************************ + ************************* LOCAL VARIABLES **************************************** + ************************************************************************************/ + +/************************************************************************************ + ************************* LOCAL TYPE DEFINITIONS ********************************* + ************************************************************************************/ + +/************************************************************************************ + ************************* LOCAL FUNCTION PROTOTYPES ****************************** + ************************************************************************************/ +/************************************************************************************ + ************************* GLOBAL FUNCTION DEFINITIONS **************************** + ************************************************************************************/ + +/******************************************************************************* + * Callback function of watchdog-timer + * @param data (void pointer) + * @return none + ******************************************************************************/ +static void on_timeout_callback(void) +{ +#if defined(SLI_SI91X_ENABLE_OS) + + osStatus_t sl_semrel_status; + sl_semrel_status = osSemaphoreRelease(sl_semaphore_app_task_id); + if (sl_semrel_status != osOK) { + // osSemaphoreRelease failed + } +#else + // kick the watchdog timer + sl_si91x_watchdog_restart_timer(); +#endif +} +#if defined(SLI_SI91X_ENABLE_OS) + +/******************************************************************************* + * Watchdog-timer task to kick the watchdog + * @param *argument -Attributes structure for thread. + * @return none + ******************************************************************************/ +static void WDT_Task(void *argument) +{ + UNUSED_PARAMETER(argument); + osStatus_t sl_sem_wdt_taskacq_status; + + osSemaphoreAttr_t sl_wdt_semaphore_attr_st; + sl_wdt_semaphore_attr_st.attr_bits = 0U; + sl_wdt_semaphore_attr_st.cb_mem = NULL; + sl_wdt_semaphore_attr_st.cb_size = 0U; + sl_wdt_semaphore_attr_st.name = NULL; + + sl_semaphore_app_task_id = osSemaphoreNew(1U, 0U, &sl_wdt_semaphore_attr_st); + while (1) { + // waiting for the semaphore release + sl_sem_wdt_taskacq_status = osSemaphoreAcquire(sl_semaphore_app_task_id, osWaitForever); + if (sl_sem_wdt_taskacq_status != osOK) { + // osSemaphoreAcquire failed + } else { + //semaphore released + sl_si91x_watchdog_restart_timer(); + } + } +} +#endif + +/******************************************************************************* + * It retrieve the system reset reason. + * Returns the reason for the system being reset. + *******************************************************************************/ +sl_watchdog_manager_reset_reason_t sl_wdt_manager_get_system_reset_status(void) +{ + uint32_t get_status = 0; + get_status = RSI_PS_GetComnIntrSts(); + + switch (SL_SI91X_WDT_RESET & get_status) { + case SL_SI91X_MCU_WWD_WINDOW_RESET: + case SL_SI91X_MCU_WWD_RESET: + case SL_SI91X_NWP_WWD_WINDOW_RESET: + case SL_SI91X_NWP_WWD_RESET: + DEBUGOUT("\r\n WDT System Reset \r\n"); + return SL_SI91X_WATCHDOG_MANAGER_RESET_WATCHDOG; + + case SL_SI91X_HOST_RESET_REQUEST: + DEBUGOUT("\r\n Software System Reset \r\n"); + return SL_SI91X_WATCHDOG_MANAGER_RESET_SOFTWARE; + + default: + DEBUGOUT("\r\n Power-on Reset \r\n"); + return SL_SI91X_WATCHDOG_MANAGER_RESET_POR; + } +} + +/******************************************************************************* + * Initializes the Watchdog Manager Service + * It initializes call back handler to WDT + * It enables the WDT during the sleep + * It configures WDT as wakeup source + ******************************************************************************/ +sl_status_t sl_watchdog_manager_init(void) +{ + sl_status_t status; + watchdog_timer_config_t watchdog_config_internal; + + // Power-Up WDT domain + RSI_PS_NpssPeriPowerUp(SLPSS_PWRGATE_ULP_MCUWDT); + +#if defined(SLI_SI91X_ENABLE_OS) + osThreadId_t si91x_thread = 0; + + // Create WDT task + si91x_thread = osThreadNew((osThreadFunc_t)WDT_Task, NULL, &wdt_thread_attributes); + if (si91x_thread == NULL) { + return SL_STATUS_FAIL; + } +#endif + + // Initializing watchdog-timer + sl_si91x_watchdog_init_timer(); + + // Enable the Watchdog timer to reset the system on processor lockup + sl_si91x_watchdog_enable_system_reset_on_processor_lockup(); + + // Update system reset value based on configured interrupt time +#if defined(SL_SI91X_WATCHDOG_MANAGER_TIMEOUT_PERIOD) + watchdog_config_internal.interrupt_time = SL_SI91X_WATCHDOG_MANAGER_TIMEOUT_PERIOD; + + // Assigning system reset value to 4sec ,if WDT is not kicked at programmed interval it resets the system after 4sec(reset counter starts counting after the interrupt time expiry) + watchdog_config_internal.system_reset_time = SL_SI91X_WATCHDOG_MANAGER_TIMEOUT_INDEX_17; +#endif + // Configuring watchdog-timer + status = sl_si91x_watchdog_set_configuration(&watchdog_config_internal); + if (status != SL_STATUS_OK) { + } + + // Registering timeout callback + status = sl_si91x_watchdog_register_timeout_callback(on_timeout_callback); + if (status != SL_STATUS_OK) { + //Failed to register callback + } +#if defined(SL_SI91X_WATCHDOG_MANAGER_ENABLE_DURING_SLEEP) && (SL_SI91X_WATCHDOG_MANAGER_ENABLE_DURING_SLEEP == ENABLE) + // Enable the WDT in sleep + sl_watchdog_enable_wdt_in_sleep(); +#else + // Disable the WDT in sleep + sl_watchdog_disable_wdt_in_sleep(); +#endif //SL_ENABLE_WDT_DURING_SLEEP + + return status; +} + +/******************************************************************************* + * Starts the Watchdog Manager Service + ******************************************************************************/ +sl_status_t sl_watchdog_manager_start(void) +{ + // Start WDT timer + sl_si91x_watchdog_start_timer(); + + return SL_STATUS_OK; +} + +/******************************************************************************* + * Disables the WDT during sleep or shutdown states + *******************************************************************************/ +void sl_watchdog_disable_wdt_in_sleep(void) +{ + MCU_FSM->MCU_FSM_CRTL_PDM_AND_ENABLES_b.ENABLE_WDT_IN_SLEEP_b = 0; +} + +/******************************************************************************* + * Enables the WDT during sleep or shutdown states + * It sets WDT as a wake-up source to the system + *******************************************************************************/ +void sl_watchdog_enable_wdt_in_sleep(void) +{ + // Enable WDT as a wakeup source to kick the WDT + RSI_PS_SetWkpSources(WDT_INTR_BASED_WAKEUP); + // Enable WDT during sleep + MCU_FSM->MCU_FSM_CRTL_PDM_AND_ENABLES_b.ENABLE_WDT_IN_SLEEP_b = 1; +} diff --git a/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_ipmu.h b/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_ipmu.h index 6394456d3..61e19ea75 100644 --- a/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_ipmu.h +++ b/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_ipmu.h @@ -407,17 +407,17 @@ typedef struct retention_boot_status_word_s { #define SDIO_WITH_TA_USB_WITH_M4 2 #define SDIO_WITH_M4_USB_WITH_TA 1 #define SDIO_USB_WITH_M4 0 - uint32_t m4_present : 1; - uint32_t m4_flash_present : 1; - uint32_t m4_flash_pinset : 4; - uint32_t m4_flash_address_width_valid : 1; - uint32_t m4_flash_address_width : 2; - uint32_t select_host_inf_with_m4_valid : 1; - uint32_t select_host_inf_with_m4 : 2; - uint32_t m4_secure_boot_enable : 1; - uint32_t m4_encrypt_firmware : 1; - uint32_t host_if_with_ta : 1; - uint32_t mcu_wdt_hw_timer : 1; + unsigned int m4_present : 1; + unsigned int m4_flash_present : 1; + unsigned int m4_flash_pinset : 4; + unsigned int m4_flash_address_width_valid : 1; + unsigned int m4_flash_address_width : 2; + unsigned int select_host_inf_with_m4_valid : 1; + unsigned int select_host_inf_with_m4 : 2; + unsigned int m4_secure_boot_enable : 1; + unsigned int m4_encrypt_firmware : 1; + unsigned int host_if_with_ta : 1; + unsigned int mcu_wdt_hw_timer : 1; #ifdef CHIP_9118 #define NONE_MODE 0 #define NLINK 1 @@ -437,219 +437,219 @@ typedef struct retention_boot_status_word_s { #define NLINK 7 #define MCU 0xF // not supported #endif - uint32_t product_mode : 4; - uint32_t m4_flash_type : 4; - uint32_t m4_dual_flash : 1; - uint32_t m4_csum : 1; - uint32_t wise_aoc_mode : 1; - uint32_t wise_aoc_from_m4_rom : 1; - uint32_t m4_image_format : 1; - uint32_t clean_ulp_wakeup : 1; + unsigned int product_mode : 4; + unsigned int m4_flash_type : 4; + unsigned int m4_dual_flash : 1; + unsigned int m4_csum : 1; + unsigned int wise_aoc_mode : 1; + unsigned int wise_aoc_from_m4_rom : 1; + unsigned int m4_image_format : 1; + unsigned int clean_ulp_wakeup : 1; #define M4_IMAGE_VALID_IND BIT(30) - uint32_t m4_image_valid : 1; - uint32_t reserved : 1; /* one bit is reserved for hardware */ + unsigned int m4_image_valid : 1; + unsigned int reserved : 1; /* one bit is reserved for hardware */ } retention_boot_status_word_t; /* This structure contains format for efuse_dword0 */ typedef struct npss_boot_status_word_0_s { //! Data from EFUSE - uint32_t usb_fsel_valid : 1; - uint32_t mems_ref_clk_as_usb_phy_clk : 1; - uint32_t modem_pll_as_usb_phy_clk : 1; - uint32_t usb_phy_clk_fsel_external : 1; - uint32_t usb_fsel : 3; - uint32_t bypass_usb_detection : 1; + unsigned int usb_fsel_valid : 1; + unsigned int mems_ref_clk_as_usb_phy_clk : 1; + unsigned int modem_pll_as_usb_phy_clk : 1; + unsigned int usb_phy_clk_fsel_external : 1; + unsigned int usb_fsel : 3; + unsigned int bypass_usb_detection : 1; //! Data derived by bootloder - uint32_t host_sel_valid : 1; - uint32_t host_sel : 3; - uint32_t ta_flash_present : 1; - uint32_t ta_flash_pinset : 4; - uint32_t ta_flash_address_width_valid : 1; - uint32_t ta_flash_address_width : 2; - uint32_t ta_flash_type : 4; - // uint32_t ta_dual_flash : 1; - uint32_t fips_enable : 1; - uint32_t usb_fclk_div_factor : 2; + unsigned int host_sel_valid : 1; + unsigned int host_sel : 3; + unsigned int ta_flash_present : 1; + unsigned int ta_flash_pinset : 4; + unsigned int ta_flash_address_width_valid : 1; + unsigned int ta_flash_address_width : 2; + unsigned int ta_flash_type : 4; + // unsigned int ta_dual_flash : 1; + unsigned int fips_enable : 1; + unsigned int usb_fclk_div_factor : 2; #define BBFF_DATA_VALID BIT(27) - uint32_t bbff_data_valid : 1; + unsigned int bbff_data_valid : 1; //! Bits configured by FW #define NWP_SOFT_RESET BIT(28) - uint32_t soft_reset : 1; + unsigned int soft_reset : 1; #define FACTORY_RESET BIT(29) - uint32_t factory_reset : 1; + unsigned int factory_reset : 1; #define TAMPER_RECOVERY BIT(30) - uint32_t tamper_recovery : 1; - uint32_t reserved : 1; + unsigned int tamper_recovery : 1; + unsigned int reserved : 1; } npss_boot_status_word0_t; #ifdef CHIP_9118 typedef struct efuse_ipmu_s { - uint32_t trim_0p5na1 : 1; - uint32_t trim_0p5na2 : 1; - uint32_t bg_r_vdd_ulp : 4; - uint32_t bg_r_ptat_vdd_ulp : 3; - uint32_t resbank_trim : 2; - uint32_t trim_sel : 7; - uint32_t del_2x_sel : 6; - uint32_t freq_trim : 5; - uint32_t coarse_trim_16k : 2; - uint32_t fine_trim_16k : 7; - uint32_t coarse_trim_64k : 2; - uint32_t fine_trim_64k : 7; - uint32_t coarse_trim_32k : 2; - uint32_t fine_trim_32k : 7; - uint32_t xtal1_trim_32k : 4; - uint32_t xtal2_trim_32k : 4; - uint32_t trim_ring_osc : 7; - uint32_t vbatt_status_1 : 6; - uint32_t str_temp_slope : 10; - uint32_t f2_nominal : 10; - uint32_t str_nominal_temp : 7; - uint32_t str_bjt_temp_sense_off : 16; - uint32_t str_bjt_temp_sense_slope : 16; + unsigned int trim_0p5na1 : 1; + unsigned int trim_0p5na2 : 1; + unsigned int bg_r_vdd_ulp : 4; + unsigned int bg_r_ptat_vdd_ulp : 3; + unsigned int resbank_trim : 2; + unsigned int trim_sel : 7; + unsigned int del_2x_sel : 6; + unsigned int freq_trim : 5; + unsigned int coarse_trim_16k : 2; + unsigned int fine_trim_16k : 7; + unsigned int coarse_trim_64k : 2; + unsigned int fine_trim_64k : 7; + unsigned int coarse_trim_32k : 2; + unsigned int fine_trim_32k : 7; + unsigned int xtal1_trim_32k : 4; + unsigned int xtal2_trim_32k : 4; + unsigned int trim_ring_osc : 7; + unsigned int vbatt_status_1 : 6; + unsigned int str_temp_slope : 10; + unsigned int f2_nominal : 10; + unsigned int str_nominal_temp : 7; + unsigned int str_bjt_temp_sense_off : 16; + unsigned int str_bjt_temp_sense_slope : 16; #ifndef AT_EFUSE_DATA_1P19 - uint32_t reserved1 : 20; + unsigned int reserved1 : 20; #endif #ifdef AT_EFUSE_DATA_1P19 - uint32_t trim_sel_20Mhz : 7; // Trim value for 20mzh rc - uint32_t ro_32khz_00_trim : 5; - uint32_t scdc_dcdc_trim : 3; - uint32_t scdc_hpldo_trim : 3; - uint32_t reserved1 : 2; + unsigned int trim_sel_20Mhz : 7; // Trim value for 20mzh rc + unsigned int ro_32khz_00_trim : 5; + unsigned int scdc_dcdc_trim : 3; + unsigned int scdc_hpldo_trim : 3; + unsigned int reserved1 : 2; #endif - uint32_t ldo_ctrl : 4; + unsigned int ldo_ctrl : 4; #ifndef AT_EFUSE_DATA_1P19 - uint32_t reserved2 : 16; + unsigned int reserved2 : 16; #endif #ifdef AT_EFUSE_DATA_1P19 - uint32_t vbg_tsbjt_efuse : 12; - uint32_t retn_ldo_lptrim : 3; - uint32_t reserved2 : 1; + unsigned int vbg_tsbjt_efuse : 12; + unsigned int retn_ldo_lptrim : 3; + unsigned int reserved2 : 1; #endif - uint32_t auxadc_offset_diff : 12; - uint32_t auxadc_invgain_diff : 16; - uint32_t auxadc_offset_single : 12; - uint32_t auxadc_invgain_single : 16; - uint32_t set_vref1p3 : 4; + unsigned int auxadc_offset_diff : 12; + unsigned int auxadc_invgain_diff : 16; + unsigned int auxadc_offset_single : 12; + unsigned int auxadc_invgain_single : 16; + unsigned int set_vref1p3 : 4; #ifndef AT_EFUSE_DATA_1P19 - uint32_t set_vref_isense1p3 : 2; - uint32_t set_vref_adc : 2; - uint32_t vtrim_ldosoc : 2; + unsigned int set_vref_isense1p3 : 2; + unsigned int set_vref_adc : 2; + unsigned int vtrim_ldosoc : 2; #endif #ifdef AT_EFUSE_DATA_1P19 - uint32_t reserved13 : 6; + unsigned int reserved13 : 6; #endif - uint32_t trim_r1_resistorladder : 4; + unsigned int trim_r1_resistorladder : 4; #ifndef AT_EFUSE_DATA_1P19 - uint32_t enable_undershoot_reduction : 1; - uint32_t select_vref_comp : 2; + unsigned int enable_undershoot_reduction : 1; + unsigned int select_vref_comp : 2; #endif #ifdef AT_EFUSE_DATA_1P19 - uint32_t retn_ldo_hptrim : 3; + unsigned int retn_ldo_hptrim : 3; #endif #ifndef AT_EFUSE_DATA_1P19 - uint32_t pwr_gd_threshold_sel : 1; - uint32_t sel_overshoot_control : 1; - uint32_t ptat_load_ctrl : 3; - uint32_t ctrl_soc : 4; - uint32_t pt_gate_ctrl : 3; - uint32_t default_mode_ctrl : 1; - uint32_t ptat_load_enable : 1; - uint32_t ldosoc_outputpulldown_sel : 1; - uint32_t ldosoc_outputpulldown : 1; + unsigned int pwr_gd_threshold_sel : 1; + unsigned int sel_overshoot_control : 1; + unsigned int ptat_load_ctrl : 3; + unsigned int ctrl_soc : 4; + unsigned int pt_gate_ctrl : 3; + unsigned int default_mode_ctrl : 1; + unsigned int ptat_load_enable : 1; + unsigned int ldosoc_outputpulldown_sel : 1; + unsigned int ldosoc_outputpulldown : 1; #endif #ifdef AT_EFUSE_DATA_1P19 - uint32_t reserved12 : 16; + unsigned int reserved12 : 16; #endif - uint32_t scale_soc_ldo_vref : 1; + unsigned int scale_soc_ldo_vref : 1; #ifndef AT_EFUSE_DATA_1P19 - uint32_t ctrl_rf : 4; - uint32_t default_mode : 1; - uint32_t test_ldopulldown_sel : 1; - uint32_t test_ldopulldown : 1; - uint32_t drive_n : 2; - uint32_t drive_p : 2; - uint32_t deadtime_ctrl_n2p : 4; - uint32_t deadtime_ctrl_p2n : 4; - uint32_t revi_offset_prog : 3; - uint32_t tran_lo_ctr : 2; - uint32_t tran_hi_ctr : 2; - uint32_t tran_und_shoot_ctr : 3; + unsigned int ctrl_rf : 4; + unsigned int default_mode : 1; + unsigned int test_ldopulldown_sel : 1; + unsigned int test_ldopulldown : 1; + unsigned int drive_n : 2; + unsigned int drive_p : 2; + unsigned int deadtime_ctrl_n2p : 4; + unsigned int deadtime_ctrl_p2n : 4; + unsigned int revi_offset_prog : 3; + unsigned int tran_lo_ctr : 2; + unsigned int tran_hi_ctr : 2; + unsigned int tran_und_shoot_ctr : 3; #endif #ifdef AT_EFUSE_DATA_1P19 - uint32_t reserved11 : 7; - uint32_t reserved10 : 12; - uint32_t reserved9 : 10; + unsigned int reserved11 : 7; + unsigned int reserved10 : 12; + unsigned int reserved9 : 10; #endif - uint32_t dpwm_freq_trim : 4; + unsigned int dpwm_freq_trim : 4; #ifndef AT_EFUSE_DATA_1P19 - uint32_t pfmro_freq_trim : 3; - uint32_t test_revi_delay : 1; - uint32_t sel_sleep_nmos_ctrl : 1; - uint32_t p_1p3 : 13; - uint32_t i_steady_state1p3 : 13; - uint32_t d_1p3 : 15; - uint32_t i_soft_start1p3 : 13; - uint32_t dither_en1p3 : 1; - uint32_t auto_mode_tran_disable : 1; + unsigned int pfmro_freq_trim : 3; + unsigned int test_revi_delay : 1; + unsigned int sel_sleep_nmos_ctrl : 1; + unsigned int p_1p3 : 13; + unsigned int i_steady_state1p3 : 13; + unsigned int d_1p3 : 15; + unsigned int i_soft_start1p3 : 13; + unsigned int dither_en1p3 : 1; + unsigned int auto_mode_tran_disable : 1; #endif #ifdef AT_EFUSE_DATA_1P19 - uint32_t reserved73 : 1; - uint32_t reserved74 : 13; - uint32_t reserved75 : 13; - uint32_t reserved76 : 15; - uint32_t reserved77 : 13; - uint32_t reserved78 : 1; - uint32_t reserved79 : 1; + unsigned int reserved73 : 1; + unsigned int reserved74 : 13; + unsigned int reserved75 : 13; + unsigned int reserved76 : 15; + unsigned int reserved77 : 13; + unsigned int reserved78 : 1; + unsigned int reserved79 : 1; #endif - uint32_t pfm_pon_time_sel : 4; + unsigned int pfm_pon_time_sel : 4; #ifndef AT_EFUSE_DATA_1P19 - uint32_t pfm_non_time_sel : 3; - uint32_t pwm_cont_prog : 3; - uint32_t pfm_clk_up_del_sel : 3; - uint32_t pwm_to_pfm_pulse_count_prog : 2; - uint32_t pfm_to_pwm_pulse_count_prog : 2; - uint32_t pfm_to_pwm_cur_prog : 3; - uint32_t pwm_to_pfm_cur_prog : 3; - uint32_t max_duty_cycle_threshold : 3; - uint32_t min_duty_cycle_threshold : 3; - uint32_t bypass_pfm_to_pwm_counter_1 : 1; - uint32_t no_of_pfm_clk : 4; - uint32_t adc_op_thresh_sel : 2; + unsigned int pfm_non_time_sel : 3; + unsigned int pwm_cont_prog : 3; + unsigned int pfm_clk_up_del_sel : 3; + unsigned int pwm_to_pfm_pulse_count_prog : 2; + unsigned int pfm_to_pwm_pulse_count_prog : 2; + unsigned int pfm_to_pwm_cur_prog : 3; + unsigned int pwm_to_pfm_cur_prog : 3; + unsigned int max_duty_cycle_threshold : 3; + unsigned int min_duty_cycle_threshold : 3; + unsigned int bypass_pfm_to_pwm_counter_1 : 1; + unsigned int no_of_pfm_clk : 4; + unsigned int adc_op_thresh_sel : 2; #endif #ifdef AT_EFUSE_DATA_1P19 - uint32_t reserved6; - uint32_t reserved31 : 3; - uint32_t reserved32 : 3; - uint32_t reserved33 : 3; - uint32_t reserved34 : 2; - uint32_t reserved35 : 2; - uint32_t reserved36 : 3; - uint32_t reserved37 : 3; - uint32_t reserved38 : 3; - uint32_t reserved39 : 3; - uint32_t reserved40 : 1; - uint32_t reserved41 : 4; - uint32_t reserved42 : 2; + unsigned int reserved6; + unsigned int reserved31 : 3; + unsigned int reserved32 : 3; + unsigned int reserved33 : 3; + unsigned int reserved34 : 2; + unsigned int reserved35 : 2; + unsigned int reserved36 : 3; + unsigned int reserved37 : 3; + unsigned int reserved38 : 3; + unsigned int reserved39 : 3; + unsigned int reserved40 : 1; + unsigned int reserved41 : 4; + unsigned int reserved42 : 2; #endif - uint32_t reserved3 : 4; - uint32_t reserved4[2]; + unsigned int reserved3 : 4; + unsigned int reserved4[2]; uint16_t reserved5; } __attribute__((__packed__)) efuse_ipmu_t; @@ -657,59 +657,59 @@ typedef struct efuse_ipmu_s { #ifdef SLI_SI917 typedef struct efuse_ipmu_s { - uint32_t trim_0p5na1 : 1; - uint32_t bg_r_vdd_ulp : 5; - uint32_t bg_r_ptat_vdd_ulp : 3; - uint32_t reserved20 : 2; //Removed in RS9117 - uint32_t trim_sel : 7; - uint32_t del_2x_sel : 6; - uint32_t freq_trim : 5; - uint32_t coarse_trim_16k : 2; - uint32_t fine_trim_16k : 7; - uint32_t coarse_trim_64k : 2; - uint32_t fine_trim_64k : 7; - uint32_t coarse_trim_32k : 2; - uint32_t fine_trim_32k : 7; - uint32_t xtal1_trim_32k : 4; - uint32_t xtal2_trim_32k : 4; - uint32_t trim_ring_osc : 7; - uint32_t vbatt_status_1 : 6; - uint32_t str_temp_slope : 10; - uint32_t f2_nominal : 10; - uint32_t str_nominal_temp : 7; - uint32_t str_bjt_temp_sense_off : 16; - uint32_t str_bjt_temp_sense_slope : 16; - uint32_t trim_sel_20Mhz : 7; // Trim value for 20mzh rc - uint32_t ro_32khz_00_trim : 5; - uint32_t scdc_dcdc_trim : 3; - uint32_t scdc_hpldo_trim : 3; - uint32_t reserved1 : 2; - uint32_t ldo_ctrl : 4; - uint32_t vbg_tsbjt_efuse : 12; - uint32_t retn_ldo_lptrim : 3; - uint32_t reserved2 : 1; - uint32_t auxadc_offset_diff : 12; - uint32_t auxadc_invgain_diff : 16; - uint32_t auxadc_offset_single : 12; - uint32_t auxadc_invgain_single : 16; - uint32_t set_vref1p3 : 4; - uint32_t reserved13 : 6; - uint32_t trim_r1_resistorladder : 4; - uint32_t retn_ldo_hptrim : 3; - uint32_t reserved12 : 16; - uint32_t scale_soc_ldo_vref : 1; - uint32_t reserved11 : 7; - uint32_t reserved10 : 12; - uint32_t reserved9 : 10; - uint32_t dpwm_freq_trim : 4; - uint32_t reserved73 : 32; // 73 and 74 togther as 50 - uint32_t reserved74 : 18; // - uint32_t scdc_clk_freq : 5; - uint32_t reserved7 : 6; - uint32_t buck_ind_efuse : 4; - uint32_t reserved31 : 32; // 31,32 and 33 togther as 80 - uint32_t reserved32 : 32; - uint32_t reserved33 : 16; + unsigned int trim_0p5na1 : 1; + unsigned int bg_r_vdd_ulp : 5; + unsigned int bg_r_ptat_vdd_ulp : 3; + unsigned int reserved20 : 2; //Removed in RS9117 + unsigned int trim_sel : 7; + unsigned int del_2x_sel : 6; + unsigned int freq_trim : 5; + unsigned int coarse_trim_16k : 2; + unsigned int fine_trim_16k : 7; + unsigned int coarse_trim_64k : 2; + unsigned int fine_trim_64k : 7; + unsigned int coarse_trim_32k : 2; + unsigned int fine_trim_32k : 7; + unsigned int xtal1_trim_32k : 4; + unsigned int xtal2_trim_32k : 4; + unsigned int trim_ring_osc : 7; + unsigned int vbatt_status_1 : 6; + unsigned int str_temp_slope : 10; + unsigned int f2_nominal : 10; + unsigned int str_nominal_temp : 7; + unsigned int str_bjt_temp_sense_off : 16; + unsigned int str_bjt_temp_sense_slope : 16; + unsigned int trim_sel_20Mhz : 7; // Trim value for 20mzh rc + unsigned int ro_32khz_00_trim : 5; + unsigned int scdc_dcdc_trim : 3; + unsigned int scdc_hpldo_trim : 3; + unsigned int reserved1 : 2; + unsigned int ldo_ctrl : 4; + unsigned int vbg_tsbjt_efuse : 12; + unsigned int retn_ldo_lptrim : 3; + unsigned int reserved2 : 1; + unsigned int auxadc_offset_diff : 12; + unsigned int auxadc_invgain_diff : 16; + unsigned int auxadc_offset_single : 12; + unsigned int auxadc_invgain_single : 16; + unsigned int set_vref1p3 : 4; + unsigned int reserved13 : 6; + unsigned int trim_r1_resistorladder : 4; + unsigned int retn_ldo_hptrim : 3; + unsigned int reserved12 : 16; + unsigned int scale_soc_ldo_vref : 1; + unsigned int reserved11 : 7; + unsigned int reserved10 : 12; + unsigned int reserved9 : 10; + unsigned int dpwm_freq_trim : 4; + unsigned int reserved73 : 32; // 73 and 74 togther as 50 + unsigned int reserved74 : 18; // + unsigned int scdc_clk_freq : 5; + unsigned int reserved7 : 6; + unsigned int buck_ind_efuse : 4; + unsigned int reserved31 : 32; // 31,32 and 33 togther as 80 + unsigned int reserved32 : 32; + unsigned int reserved33 : 16; } __attribute__((__packed__)) efuse_ipmu_t; #endif @@ -767,10 +767,10 @@ void RSI_IPMU_PowerGateClr(uint32_t mask_vlaue); rsi_error_t RSI_IPMU_CommonConfig(void); void RSI_IPMU_ClockMuxSel(uint8_t bg_pmu_clk); uint32_t RSI_IPMU_32MHzClkClib(void); -rsi_error_t RSI_IPMU_ProgramConfigData(uint32_t *config); +rsi_error_t RSI_IPMU_ProgramConfigData(const uint32_t *config); void RSI_IPMU_InitCalibData(void); -void RSI_IPMU_UpdateIpmuCalibData_efuse(efuse_ipmu_t *ipmu_calib_data); -uint32_t RSI_APB_ProgramConfigData(uint32_t *config); +void RSI_IPMU_UpdateIpmuCalibData_efuse(const efuse_ipmu_t *ipmu_calib_data); +uint32_t RSI_APB_ProgramConfigData(const uint32_t *config); uint32_t RSI_IPMU_RO_TsConfig(void); void RSI_Configure_DCDC_LowerVoltage(void); void RSI_IPMU_32KHzRCClkClib(void); diff --git a/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_pll.h b/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_pll.h index 39a82ddf3..5a2263179 100644 --- a/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_pll.h +++ b/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_pll.h @@ -644,13 +644,13 @@ STATIC INLINE void _usdelay(uint32_t delayUs, cdDelay delayCb) } } -rsi_error_t clk_i2s_pll_clk_set(M4CLK_Type *pCLK); +rsi_error_t clk_i2s_pll_clk_set(const M4CLK_Type *pCLK); boolean_t clk_check_pll_lock(PLL_TYPE_T pllType); rsi_error_t clk_soc_pll_clk_enable(boolean_t clkEnable); -rsi_error_t clk_soc_pll_set_freq_div(M4CLK_Type *pCLK, +rsi_error_t clk_soc_pll_set_freq_div(const M4CLK_Type *pCLK, boolean_t clk_en, uint16_t divFactor, uint16_t nFactor, @@ -659,7 +659,7 @@ rsi_error_t clk_soc_pll_set_freq_div(M4CLK_Type *pCLK, uint16_t dcoFixSel, uint16_t ldoProg); -rsi_error_t clk_soc_pll_clk_set(M4CLK_Type *pCLK); +rsi_error_t clk_soc_pll_clk_set(const M4CLK_Type *pCLK); rsi_error_t clk_soc_pll_clk_bypass_enable(boolean_t clkEnable); @@ -681,7 +681,7 @@ rsi_error_t clk_i2s_pll_turn_off(void); rsi_error_t clk_i2s_pll_turn_on(void); -rsi_error_t clk_i2s_pll_set_freq_div(M4CLK_Type *pCLK, +rsi_error_t clk_i2s_pll_set_freq_div(const M4CLK_Type *pCLK, uint16_t u16DivFactor1, uint16_t u16DivFactor2, uint16_t nFactor, @@ -690,7 +690,7 @@ rsi_error_t clk_i2s_pll_set_freq_div(M4CLK_Type *pCLK, rsi_error_t clk_i2s_pll_clk_reset(void); -rsi_error_t clk_i2s_pll_clk_set(M4CLK_Type *pCLK); +rsi_error_t clk_i2s_pll_clk_set(const M4CLK_Type *pCLK); rsi_error_t clk_intf_pll_clk_enable(boolean_t clkEnable); @@ -698,7 +698,7 @@ rsi_error_t clk_intf_pll_pd_enable(boolean_t en); rsi_error_t clk_intf_pll_turn_off(void); -rsi_error_t clk_intf_pll_set_freq_div(M4CLK_Type *pCLK, +rsi_error_t clk_intf_pll_set_freq_div(const M4CLK_Type *pCLK, boolean_t clk_en, uint16_t divFactor, uint16_t nFactor, @@ -713,7 +713,7 @@ rsi_error_t clk_intf_pll_turn_on(void); rsi_error_t clk_intf_pll_clk_reset(void); -rsi_error_t clk_intf_pll_clk_set(M4CLK_Type *pCLK); +rsi_error_t clk_intf_pll_clk_set(const M4CLK_Type *pCLK); rsi_error_t clk_peripheral_clk_enable1(M4CLK_Type *pCLK, uint32_t flags); @@ -813,15 +813,15 @@ rsi_error_t clk_peripheral_clk_enable(M4CLK_Type *pCLK, PERIPHERALS_CLK_T module rsi_error_t clk_peripheral_clk_disable(M4CLK_Type *pCLK, PERIPHERALS_CLK_T module); -rsi_error_t clk_set_soc_pll_freq(M4CLK_Type *pCLK, uint32_t socPllFreq, uint32_t pllRefClk); +rsi_error_t clk_set_soc_pll_freq(const M4CLK_Type *pCLK, uint32_t socPllFreq, uint32_t pllRefClk); -rsi_error_t clk_set_intf_pll_freq(M4CLK_Type *pCLK, uint32_t intfPllFreq, uint32_t pllRefClk); +rsi_error_t clk_set_intf_pll_freq(const M4CLK_Type *pCLK, uint32_t intfPllFreq, uint32_t pllRefClk); rsi_error_t ulpss_enable_ref_clks(REF_CLK_ENABLE_T enable, SRC_TYPE_T srcType, cdDelay delayFn); -rsi_error_t clk_set_i2s_pll_freq(M4CLK_Type *pCLK, uint32_t i2sPllFreq, uint32_t fXtal); +rsi_error_t clk_set_i2s_pll_freq(const M4CLK_Type *pCLK, uint32_t i2sPllFreq, uint32_t fXtal); -void _usdelay(uint32_t delayUs, cdDelay delayCb); +static void _usdelay(uint32_t delayUs, cdDelay delayCb); rsi_error_t ulpss_disable_ref_clks(REF_CLK_ENABLE_T clk_type); @@ -829,8 +829,8 @@ void clk_config_pll_lock(boolean_t manual_lock, boolean_t bypass_manual_lock, ui void clk_config_pll_ref_clk(uint8_t ref_clk_src); rsi_error_t clk_m4_soc_clk_config(M4CLK_Type *pCLK, M4_SOC_CLK_SRC_SEL_T clkSource, uint32_t divFactor); -uint32_t RSI_CLK_CheckPresent(M4CLK_Type *pCLK, CLK_PRESENT_T clkPresent); -rsi_error_t clk_m4ss_ref_clk_config(M4CLK_Type *pCLK, M4SS_REF_CLK_SEL_T clkSource); +uint32_t RSI_CLK_CheckPresent(const M4CLK_Type *pCLK, CLK_PRESENT_T clkPresent); +rsi_error_t clk_m4ss_ref_clk_config(const M4CLK_Type *pCLK, M4SS_REF_CLK_SEL_T clkSource); rsi_error_t ulpss_disable_ref_clks(REF_CLK_ENABLE_T clk_type); /*End of file not truncated*/ diff --git a/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_power_save.h b/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_power_save.h index 7290be74e..44e9d944a 100644 --- a/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_power_save.h +++ b/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_power_save.h @@ -274,7 +274,6 @@ extern "C" { #define PMU_STS_SOC_LDO_ON BIT(8) /*PMU */ -//#define STANDBY_DC1P3_R BIT(19) #define STANDBY_LDOSOC_R BIT(18) #define STANDBY_LDORF_R BIT(17) #define BGPMU_SLEEP_EN_R BIT(16) @@ -1609,11 +1608,11 @@ STATIC INLINE uint32_t RSI_PS_BodClksPtatDisable(void) */ STATIC INLINE void RSI_PS_PS4SetRegisters(void) { - // Configure the prefetch and registering when SOC clock is more than 120Mhz - ICACHE2_ADDR_TRANSLATE_1_REG = BIT(21); // Icache registering when clk freq more than 120 - // When set, enables registering in M4-TA AHB2AHB. This will have performance penalty. This has to be set above 100MHz + // Configure the prefetch and registering when SOC clock is more than 120 MHz + ICACHE2_ADDR_TRANSLATE_1_REG = BIT(21); // Icache registering when clock frequency is more than 120 MHz + // When set, enables registering in M4-TA AHB2AHB. This will have performance penalty. This has to be set above 100 MHz MISC_CFG_SRAM_REDUNDANCY_CTRL = BIT(4); - MISC_CONFIG_MISC_CTRL1 |= BIT(4); // Enable Register ROM as clock frequency is 200 Mhz + MISC_CONFIG_MISC_CTRL1 |= BIT(4); // Enable Register ROM as clock frequency is 200 MHz } /** diff --git a/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_retention.h b/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_retention.h index fe5116553..38ab76f4d 100644 --- a/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_retention.h +++ b/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_retention.h @@ -29,8 +29,9 @@ extern "C" { #endif /*NPSS GPIO PIN MUX VALEUS*/ -#define NPSS_GPIO_STATUS (*(volatile uint32_t *)(NPSS_INTR_BASE + 0x14)) -#define NPSS_GPIO_CONFIG_REG (*(volatile uint32_t *)(NPSS_INTR_BASE + 0x10)) +#define NPSS_GPIO_STATUS (*(volatile uint32_t *)(NPSS_INTR_BASE + 0x14)) +#define NPSS_GPIO_CONFIG_REG (*(volatile uint32_t *)(NPSS_INTR_BASE + 0x10)) +#define NPSS_GPIO_CONFIG_CLR_REG (*(volatile uint32_t *)(NPSS_INTR_BASE + 0x8)) /*NPSS GPIO PIN MUX VALEUS*/ #define NPSSGPIO_PIN_MUX_MODE0 0 diff --git a/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_rtc.h b/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_rtc.h index 263cc6570..21305ff57 100644 --- a/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_rtc.h +++ b/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_rtc.h @@ -100,11 +100,11 @@ typedef struct RTC_TIME_CONFIG { void RSI_RTC_Start(RTC_Type *Cal); void RSI_RTC_Init(RTC_Type *Cal); void RSI_RTC_Stop(RTC_Type *Cal); -rsi_error_t RSI_RTC_SetDateTime(RTC_Type *Cal, RTC_TIME_CONFIG_T *date); -rsi_error_t RSI_RTC_GetDateTime(RTC_Type *Cal, RTC_TIME_CONFIG_T *date); -rsi_error_t RSI_RTC_SetAlarmDateTime(RTC_Type *Cal, RTC_TIME_CONFIG_T *alarm); +rsi_error_t RSI_RTC_SetDateTime(RTC_Type *Cal, const RTC_TIME_CONFIG_T *date); +rsi_error_t RSI_RTC_GetDateTime(const RTC_Type *Cal, RTC_TIME_CONFIG_T *date); +rsi_error_t RSI_RTC_SetAlarmDateTime(RTC_Type *Cal, const RTC_TIME_CONFIG_T *alarm); void RSI_RTC_AlamEnable(RTC_Type *Cal, boolean_t val); -rsi_error_t RSI_RTC_GetAlarmDateTime(RTC_Type *Cal, RTC_TIME_CONFIG_T *alarm); +rsi_error_t RSI_RTC_GetAlarmDateTime(const RTC_Type *Cal, RTC_TIME_CONFIG_T *alarm); void RSI_RTC_SetDayOfWeek(RTC_Type *Cal, RTC_DAY_OF_WEEK_T dayInWeek); void RSI_RTC_IntrUnMask(uint32_t intr); void RSI_RTC_IntrMask(uint32_t intr); diff --git a/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_temp_sensor.h b/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_temp_sensor.h index 883a52fca..5a3aa5278 100644 --- a/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_temp_sensor.h +++ b/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_temp_sensor.h @@ -1,18 +1,18 @@ -/******************************************************************************* -* @file rsi_temp_sensor.h -* @brief -******************************************************************************* -* # License -* Copyright 2020 Silicon Laboratories Inc. www.silabs.com -******************************************************************************* -* -* The licensor of this software is Silicon Laboratories Inc. Your use of this -* software is governed by the terms of Silicon Labs Master Software License -* Agreement (MSLA) available at -* www.silabs.com/about-us/legal/master-software-license-agreement. This -* software is distributed to you in Source Code format and is governed by the -* sections of the MSLA applicable to Source Code. -* +/******************************************************************************* +* @file rsi_temp_sensor.h +* @brief +******************************************************************************* +* # License +* Copyright 2020 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* ******************************************************************************/ /** @@ -49,9 +49,9 @@ void RSI_TS_Config(MCU_TEMP_Type *pstcTempSens, uint32_t u32Nomial); * @{ * */ -uint32_t RSI_TS_ReadTemp(MCU_TEMP_Type *pstcTempSens); -uint32_t RSI_TS_GetRefClkCnt(MCU_TEMP_Type *pstcTempSens); -uint32_t RSI_TS_GetPtatClkCnt(MCU_TEMP_Type *pstcTempSens); +uint32_t RSI_TS_ReadTemp(const MCU_TEMP_Type *pstcTempSens); +uint32_t RSI_TS_GetRefClkCnt(const MCU_TEMP_Type *pstcTempSens); +uint32_t RSI_TS_GetPtatClkCnt(const MCU_TEMP_Type *pstcTempSens); void RSI_TS_LoadBjt(MCU_TEMP_Type *pstcTempSens, uint8_t temp); void RSI_TS_RoBjtEnable(MCU_TEMP_Type *pstcTempSens, boolean_t enable); void RSI_Periodic_TempUpdate(TIME_PERIOD_Type *temp, uint8_t enable, uint8_t trigger_time); diff --git a/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_time_period.h b/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_time_period.h index f1e92ab26..029c65e9e 100644 --- a/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_time_period.h +++ b/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_time_period.h @@ -37,8 +37,8 @@ rsi_error_t RSI_TIMEPERIOD_RCCalibration(TIME_PERIOD_Type *pstcTimePeriod, boolean_t bTemperatureCalibEn, uint8_t u8TemperatureVal, uint8_t u8AverageFactor); -uint32_t RSI_TIMEPERIOD_RCCalibTimePeriodRead(TIME_PERIOD_Type *pstcTimePeriod); -uint32_t RSI_TIMEPERIOD_ROCalibTimePeriodRead(TIME_PERIOD_Type *pstcTimePeriod); +uint32_t RSI_TIMEPERIOD_RCCalibTimePeriodRead(const TIME_PERIOD_Type *pstcTimePeriod); +uint32_t RSI_TIMEPERIOD_ROCalibTimePeriodRead(const TIME_PERIOD_Type *pstcTimePeriod); rsi_error_t RSI_TIMEPERIOD_XTAL32KHzCalibration(TIME_PERIOD_Type *pstcTimePeriod, uint32_t u32TimePeriodRefClk, uint32_t u32XtalSettle, diff --git a/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_wwdt.h b/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_wwdt.h index 3079e7776..c16c5f556 100644 --- a/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_wwdt.h +++ b/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_wwdt.h @@ -137,11 +137,11 @@ STATIC INLINE void RSI_WWDT_SysRstOnProcLockDisable(MCU_WDT_Type *pstcWDT) } /** - * @fn void RSI_WWDT_GetProcLockSignal(MCU_WDT_Type *pstcWDT) + * @fn void RSI_WWDT_GetProcLockSignal(const MCU_WDT_Type *pstcWDT) * @brief This API is used to read signal for processor stuck reset enable * @return None */ -STATIC INLINE uint8_t RSI_WWDT_GetProcLockRstEnableSignal(MCU_WDT_Type *pstcWDT) +STATIC INLINE uint8_t RSI_WWDT_GetProcLockRstEnableSignal(const MCU_WDT_Type *pstcWDT) { if (pstcWDT->MCU_WWD_ARM_STUCK_EN_b.PROCESSOR_STUCK_RESET_EN_) { return 1; @@ -151,12 +151,12 @@ STATIC INLINE uint8_t RSI_WWDT_GetProcLockRstEnableSignal(MCU_WDT_Type *pstcWDT) } /** - * @fn uint16_t RSI_WWDT_GetIntrTime(MCU_WDT_Type *pstcWDT) + * @fn uint16_t RSI_WWDT_GetIntrTime(const MCU_WDT_Type *pstcWDT) * @brief This API is used to read the interrupt time of the watch dog timer * @param[in] pstcWDT : pointer to the WDT register instance * @return uint8_t : interrupt timer value */ -STATIC INLINE uint8_t RSI_WWDT_GetIntrTime(MCU_WDT_Type *pstcWDT) +STATIC INLINE uint8_t RSI_WWDT_GetIntrTime(const MCU_WDT_Type *pstcWDT) { uint8_t interrupt_time; interrupt_time = pstcWDT->MCU_WWD_INTERRUPT_TIMER_b.WWD_INTERRUPT_TIMER; @@ -164,12 +164,12 @@ STATIC INLINE uint8_t RSI_WWDT_GetIntrTime(MCU_WDT_Type *pstcWDT) } /** - * @fn uint16_t RSI_WWDT_GetSysRstTime(MCU_WDT_Type *pstcWDT) + * @fn uint16_t RSI_WWDT_GetSysRstTime(const MCU_WDT_Type *pstcWDT) * @brief This API is used to read the system reset time of the watch dog timer * @param[in] pstcWDT : pointer to the WDT register instance * @return uint8_t : system reset timer value */ -STATIC INLINE uint8_t RSI_WWDT_GetSysRstTime(MCU_WDT_Type *pstcWDT) +STATIC INLINE uint8_t RSI_WWDT_GetSysRstTime(const MCU_WDT_Type *pstcWDT) { uint8_t system_reset_time; system_reset_time = pstcWDT->MCU_WWD_SYSTEM_RESET_TIMER_b.WWD_SYSTEM_RESET_TIMER; @@ -177,12 +177,12 @@ STATIC INLINE uint8_t RSI_WWDT_GetSysRstTime(MCU_WDT_Type *pstcWDT) } /** - * @fn uint8_t RSI_WWDT_GetWindowTime(MCU_WDT_Type *pstcWDT) + * @fn uint8_t RSI_WWDT_GetWindowTime(const MCU_WDT_Type *pstcWDT) * @brief This API is used to read the system reset time of the watch dog timer * @param[in] pstcWDT : pointer to the WDT register instance * @return uint8_t : system reset timer value */ -STATIC INLINE uint8_t RSI_WWDT_GetWindowTime(MCU_WDT_Type *pstcWDT) +STATIC INLINE uint8_t RSI_WWDT_GetWindowTime(const MCU_WDT_Type *pstcWDT) { uint8_t window_time; window_time = pstcWDT->MCU_WWD_WINDOW_TIMER_b.WINDOW_TIMER; diff --git a/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_ipmu.c b/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_ipmu.c index e661bd069..74938231b 100644 --- a/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_ipmu.c +++ b/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_ipmu.c @@ -22,17 +22,23 @@ #include "rsi_ipmu.h" #include "rsi_pll.h" #include "rsi_ulpss_clk.h" +/** + * Defines + */ +#define SYSTEM_CLK_VAL_20MHZ ((uint32_t)(20000000)) // macro for 20MHz +#define SYSTEM_CLK_VAL_32MHZ ((uint32_t)(32000000)) // macro for 32MHz /** - * @fn void RSI_IPMU_UpdateIpmuCalibData_efuse(efuse_ipmu_t *ipmu_calib_data) + * @fn void RSI_IPMU_UpdateIpmuCalibData_efuse(const efuse_ipmu_t *ipmu_calib_data) * @brief This function prepares the data from the ipmu calib structure content and writes to each specific register * @param[in] ipmu_calib_data : pointer of calibrate data * @return none */ -void RSI_IPMU_UpdateIpmuCalibData_efuse(efuse_ipmu_t *ipmu_calib_data) +void RSI_IPMU_UpdateIpmuCalibData_efuse(const efuse_ipmu_t *ipmu_calib_data) { - uint32_t data = 0, value = 0; - uint32_t mask = 0; + uint32_t data = 0; + uint32_t value = 0; + uint32_t mask = 0; /* over writing the efuse arrays */ #ifdef CHIP_9118 @@ -161,8 +167,7 @@ void RSI_IPMU_UpdateIpmuCalibData_efuse(efuse_ipmu_t *ipmu_calib_data) #ifdef AT_EFUSE_DATA_1P19 /* m20rc_osc_trim_efuse */ - data = (ipmu_calib_data->trim_sel_20Mhz); - ; + data = (ipmu_calib_data->trim_sel_20Mhz); mask = MASK_BITS(22, 0); value = m20rc_osc_trim_efuse[2]; value &= ~mask; @@ -441,9 +446,10 @@ void RSI_Configure_Ipmu_Mode(void) } void update_efuse_system_configs(int data, uint32_t config_ptr[]) { - uint32_t mask = 0, value = 0; - mask = MASK_BITS(22, 0); - value = config_ptr[2]; + uint32_t mask = 0; + uint32_t value = 0; + mask = MASK_BITS(22, 0); + value = config_ptr[2]; value &= ~mask; value |= (uint32_t)data; config_ptr[2] = value; @@ -455,7 +461,8 @@ void update_efuse_system_configs(int data, uint32_t config_ptr[]) void RSI_Configure_DCDC_LowerVoltage(void) { - uint32_t pmu_1p2_ctrl_word, bypass_curr_ctrl_data; + uint32_t pmu_1p2_ctrl_word; + uint32_t bypass_curr_ctrl_data; bypass_curr_ctrl_data = PMU_SPI_DIRECT_ACCESS(PMU_1P3_CTRL_REG_OFFSET); pmu_1p2_ctrl_word = ((bypass_curr_ctrl_data >> 17) & 0xF) - 2; @@ -567,7 +574,8 @@ void RSI_IPMU_ClockMuxSel(uint8_t bg_pmu_clk) uint32_t RSI_IPMU_32MHzClkClib(void) { - volatile int i, trim_value = 0; + volatile int i; + volatile int trim_value = 0; /*Enables RC 32MHz clock and*/ ULP_SPI_MEM_MAP(0x104) = (0x3FFFFF & 0x41368000); /*Enable XTAL 40MHz clock through NPSS*/ @@ -607,18 +615,25 @@ uint32_t RSI_IPMU_32MHzClkClib(void) /*==============================================*/ /** - * @fn rsi_error_t RSI_IPMU_ProgramConfigData(uint32_t *config) + * @fn rsi_error_t RSI_IPMU_ProgramConfigData(const uint32_t *config) * @brief This API is used to program the any mcu configuration structure * @param[in] config : pointer configuration * @return RSI_OK on success */ -rsi_error_t RSI_IPMU_ProgramConfigData(uint32_t *config) +rsi_error_t RSI_IPMU_ProgramConfigData(const uint32_t *config) { - volatile uint32_t index = 0, program_len = 0, reg_addr = 0; - volatile uint32_t reg_write_data = 0, clear_cnt = 0, cnt = 0; - volatile uint32_t reg_read_data = 0, write_mask = 0, write_bit_pos = 0; - volatile uint8_t msb = 0, lsb = 0; + volatile uint32_t index = 0; + volatile uint32_t program_len = 0; + volatile uint32_t reg_addr = 0; + volatile uint32_t reg_write_data = 0; + volatile uint32_t clear_cnt = 0; + volatile uint32_t cnt = 0; + volatile uint32_t reg_read_data = 0; + volatile uint32_t write_mask = 0; + volatile uint32_t write_bit_pos = 0; + volatile uint8_t msb = 0; + volatile uint8_t lsb = 0; if (config == NULL) { return INVALID_PARAMETERS; @@ -662,18 +677,25 @@ rsi_error_t RSI_IPMU_ProgramConfigData(uint32_t *config) /*==============================================*/ /** - * @fn uint32_t RSI_APB_ProgramConfigData(uint32_t *config) + * @fn uint32_t RSI_APB_ProgramConfigData(const uint32_t *config) * @brief This API is used to program the any mcu configuration structure * @param[in] config : pointer configuration * @return reg_write_data on success. */ -uint32_t RSI_APB_ProgramConfigData(uint32_t *config) +uint32_t RSI_APB_ProgramConfigData(const uint32_t *config) { - volatile uint32_t index = 0, program_len = 0, reg_addr = 0; - volatile uint32_t clear_cnt = 0, cnt = 0; - volatile uint32_t reg_write_data = 0, reg_read_data = 0, write_mask = 0, write_bit_pos = 0; - volatile uint8_t msb = 0, lsb = 0; + volatile uint32_t index = 0; + volatile uint32_t program_len = 0; + volatile uint32_t reg_addr = 0; + volatile uint32_t clear_cnt = 0; + volatile uint32_t cnt = 0; + volatile uint32_t reg_write_data = 0; + volatile uint32_t reg_read_data = 0; + volatile uint32_t write_mask = 0; + volatile uint32_t write_bit_pos = 0; + volatile uint8_t msb = 0; + volatile uint8_t lsb = 0; (void)reg_addr; if (config == NULL) { @@ -819,7 +841,8 @@ void RSI_IPMU_RetnLdoLpmode(void) void RSI_IPMU_Retn_Voltage_Reduction(void) { - uint32_t value, mask; + uint32_t value; + uint32_t mask; value = retnLP_volt_trim_efuse[2]; mask = MASK_BITS(3, 0); value &= mask; @@ -907,21 +930,28 @@ rsi_error_t RSI_IPMU_M32rc_OscTrimEfuse(void) /*==============================================*/ /** - * @fn rsi_error_t RSI_IPMU_M20rcOsc_TrimEfuse(void) - * @brief This API is used to program the trim value for 20Mhz RC oscillator . - * @return RSI_IPMU_ProgramConfigData on success. + * @fn rsi_error_t RSI_IPMU_M20rcOsc_TrimEfuse(void) + * @brief This API is used to program the trim value for 20MHz RC oscillator + * @return RSI_IPMU_ProgramConfigData on success */ rsi_error_t RSI_IPMU_M20rcOsc_TrimEfuse(void) { - system_clocks.rc_32mhz_clock = 20000000; - if (system_clocks.m4_ref_clock_source == ULP_32MHZ_RC_CLK) { - system_clocks.m4ss_ref_clk = 20000000; - } - if (system_clocks.ulp_ref_clock_source == ULPSS_ULP_32MHZ_RC_CLK) { - system_clocks.ulpss_ref_clk = 20000000; + rsi_error_t error_status; + + error_status = RSI_IPMU_ProgramConfigData(m20rc_osc_trim_efuse); + + if (error_status == RSI_OK) { + system_clocks.rc_32mhz_clock = SYSTEM_CLK_VAL_20MHZ; + if (system_clocks.m4_ref_clock_source == ULP_32MHZ_RC_CLK) { + system_clocks.m4ss_ref_clk = SYSTEM_CLK_VAL_20MHZ; + } + if (system_clocks.ulp_ref_clock_source == ULPSS_ULP_32MHZ_RC_CLK) { + system_clocks.ulpss_ref_clk = SYSTEM_CLK_VAL_20MHZ; + } } - return RSI_IPMU_ProgramConfigData(m20rc_osc_trim_efuse); + + return error_status; } /*==============================================*/ @@ -933,7 +963,7 @@ rsi_error_t RSI_IPMU_M20rcOsc_TrimEfuse(void) rsi_error_t RSI_IPMU_DBLR32M_TrimEfuse(void) { - system_clocks.doubler_clock = 32000000; + system_clocks.doubler_clock = SYSTEM_CLK_VAL_32MHZ; return RSI_IPMU_ProgramConfigData(dblr_32m_trim_efuse); } @@ -1320,7 +1350,8 @@ rsi_error_t RSI_IPMU_BOD_Cmphyst(void) void RSI_IPMU_32KHzROClkClib(void) { - uint32_t ro32k_trim = 0, no_of_tst_clk_khz_ro = 0; + uint32_t ro32k_trim = 0; + uint32_t no_of_tst_clk_khz_ro = 0; /*Do until clock should be 32KHz */ do { @@ -1373,7 +1404,8 @@ void RSI_IPMU_32KHzROClkClib(void) void RSI_IPMU_32KHzRCClkClib(void) { - uint32_t rc32k_trim = 0, no_of_tst_clk_khz_rc = 0; + uint32_t rc32k_trim = 0; + uint32_t no_of_tst_clk_khz_rc = 0; /*Do until clock should be 32KHz */ do { @@ -1427,7 +1459,10 @@ void RSI_IPMU_32KHzRCClkClib(void) uint32_t RSI_Clks_Trim32MHzRC(uint32_t freq) { - volatile uint32_t no_oftst_clk_f = 0, no_oftst_clk = 0, i = 0, reg_read = 0, trim_value = 0; + volatile uint32_t no_oftst_clk_f = 0; + volatile uint32_t no_oftst_clk = 0; + volatile uint32_t reg_read = 0; + volatile uint32_t trim_value = 0; system_clocks.rc_32mhz_clock = (freq); @@ -1451,7 +1486,7 @@ uint32_t RSI_Clks_Trim32MHzRC(uint32_t freq) reg_read &= (uint32_t)(~(0x7F << TRIM_LSB_32MHZ)); ULP_SPI_MEM_MAP(ULPCLKS_32MRC_CLK_REG_OFFSET) = (reg_read); /* check's from 20 bit to 14 bit */ - for (i = TRIM_MSB_32MHZ; i >= TRIM_LSB_32MHZ; i--) { + for (volatile uint32_t i = TRIM_MSB_32MHZ; i >= TRIM_LSB_32MHZ; i--) { /* Measures MHz RC clock Clock Frequency */ no_oftst_clk_f = RSI_Clks_Calibration(ulp_ref_clk, none); /*To get in three digit of Measured frequency value in MHz e.g:20MHz as 200 */ @@ -1612,7 +1647,8 @@ uint32_t RSI_Clks_Calibration(INPUT_CLOCK_T inputclk, SLEEP_CLOCK_T sleep_clk_ty void RSI_IPMU_64KHZ_RCClktrim(void) { - uint32_t i, status = 0; + uint32_t i; + uint32_t status = 0; system_clocks.rc_32khz_clock = (64000); diff --git a/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_pll.c b/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_pll.c index d60af0016..a17fe6800 100644 --- a/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_pll.c +++ b/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_pll.c @@ -42,25 +42,15 @@ boolean_t clk_check_pll_lock(PLL_TYPE_T pllType) if (pllType == SOC_PLL) { lock = SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG13) >> 14; - if (lock & 1) { - return Enable; - } else { - return Disable; - } } else if (pllType == INFT_PLL) { lock = SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG13) >> 14; - if (lock & 1) { - return Enable; - } else { - return Disable; - } } else { lock = SPI_MEM_MAP_PLL(I2S_PLL_CTRL_REG13) >> 14; - if (lock & 1) { - return Enable; - } else { - return Disable; - } + } + if (lock & 1) { + return Enable; + } else { + return Disable; } } @@ -86,7 +76,7 @@ rsi_error_t clk_soc_pll_clk_enable(boolean_t clkEnable) /*==============================================*/ /** - * @fn rsi_error_t clk_set_soc_pll_freq(M4CLK_Type *pCLK, uint32_t socPllFreq, uint32_t pllRefClk) + * @fn rsi_error_t clk_set_soc_pll_freq(const M4CLK_Type *pCLK, uint32_t socPllFreq, uint32_t pllRefClk) * @brief This API is used to set the Soc PLL clock to particular frequency * @param[in] pCLK : pointer to the processor clock source * @param[in] socPllFreq : SoC PLL frequency for Soc PLL clock to particular frequency @@ -94,14 +84,16 @@ rsi_error_t clk_soc_pll_clk_enable(boolean_t clkEnable) * @return RSI_OK on success */ -rsi_error_t clk_set_soc_pll_freq(M4CLK_Type *pCLK, uint32_t socPllFreq, uint32_t pllRefClk) +rsi_error_t clk_set_soc_pll_freq(const M4CLK_Type *pCLK, uint32_t socPllFreq, uint32_t pllRefClk) { uint16_t shiftFac = 0; uint16_t socPllMulFac = 0; uint16_t dcoFreq = 0; uint16_t reg = 0; uint16_t socPllDivFac = 0; - uint16_t socreg1 = 0x31c9, socreg3 = 0, socPllTvRead = 0; + uint16_t socreg1 = 0x31c9; + uint16_t socreg3 = 0; + uint16_t socPllTvRead = 0; /*parameter validation*/ @@ -270,7 +262,7 @@ rsi_error_t clk_set_soc_pll_freq(M4CLK_Type *pCLK, uint32_t socPllFreq, uint32_t /*==============================================*/ /** - * @fn rsi_error_t clk_soc_pll_set_freq_div(M4CLK_Type *pCLK, + * @fn rsi_error_t clk_soc_pll_set_freq_div(const M4CLK_Type *pCLK, * boolean_t clk_en, * uint16_t divFactor, * uint16_t nFactor, @@ -290,7 +282,7 @@ rsi_error_t clk_set_soc_pll_freq(M4CLK_Type *pCLK, uint32_t socPllFreq, uint32_t * @return RSI_OK on success */ -rsi_error_t clk_soc_pll_set_freq_div(M4CLK_Type *pCLK, +rsi_error_t clk_soc_pll_set_freq_div(const M4CLK_Type *pCLK, boolean_t clk_en, uint16_t divFactor, uint16_t nFactor, @@ -299,7 +291,10 @@ rsi_error_t clk_soc_pll_set_freq_div(M4CLK_Type *pCLK, uint16_t dcoFixSel, uint16_t ldoProg) { - uint16_t socreg1 = 0x31c9, socreg3 = 0, reg = 0, socPllTvRead = 0; + uint16_t socreg1 = 0x31c9; + uint16_t socreg3 = 0; + uint16_t reg = 0; + uint16_t socPllTvRead = 0; if (pCLK == NULL) { return INVALID_PARAMETERS; } @@ -375,13 +370,13 @@ rsi_error_t clk_soc_pll_set_freq_div(M4CLK_Type *pCLK, /*==============================================*/ /** - * @fn rsi_error_t clk_soc_pll_clk_set(M4CLK_Type *pCLK) + * @fn rsi_error_t clk_soc_pll_clk_set(const M4CLK_Type *pCLK) * @brief This API is used to Enables the SoC-PLL * @param[in] pCLK : pointer to the processor clock source * @return RSI_OK on success */ -rsi_error_t clk_soc_pll_clk_set(M4CLK_Type *pCLK) +rsi_error_t clk_soc_pll_clk_set(const M4CLK_Type *pCLK) { SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG11) = 0xFFFF; /*Wait for lock*/ @@ -572,7 +567,7 @@ rsi_error_t clk_i2s_pll_turn_on(void) /*==============================================*/ /** - * @fn rsi_error_t clk_set_i2s_pll_freq(M4CLK_Type *pCLK, uint32_t i2sPllFreq, uint32_t fXtal) + * @fn rsi_error_t clk_set_i2s_pll_freq(const M4CLK_Type *pCLK, uint32_t i2sPllFreq, uint32_t fXtal) * @brief This API is used to set the I2s_pll clock to particular frequency * @param[in] pCLK : pointer to the processor clock source * @param[in] i2sPllFreq : PLL clock of I2S for particular frequency @@ -580,13 +575,22 @@ rsi_error_t clk_i2s_pll_turn_on(void) * @return RSI_OK on success */ -rsi_error_t clk_set_i2s_pll_freq(M4CLK_Type *pCLK, uint32_t i2sPllFreq, uint32_t fXtal) +rsi_error_t clk_set_i2s_pll_freq(const M4CLK_Type *pCLK, uint32_t i2sPllFreq, uint32_t fXtal) { - uint16_t p_div = 0, u16DivFactor1 = 0, u16DivFactor2 = 0, N = 0, M = 0, FCW_F = 0; - uint32_t fref = 0, Fdco; + uint16_t p_div = 0; + uint16_t u16DivFactor1 = 0; + uint16_t u16DivFactor2 = 0; + uint16_t N = 0; + uint16_t M = 0; + uint16_t FCW_F = 0; + uint32_t fref = 0; + uint32_t Fdco; float g; - double FCW, frac; - uint16_t i2sreg1 = 0x1244, i2sreg2 = 0x5850, i2sreg3 = 0xba60; + double FCW; + double frac; + uint16_t i2sreg1 = 0x1244; + uint16_t i2sreg2 = 0x5850; + uint16_t i2sreg3 = 0xba60; if (pCLK == NULL) { return INVALID_PARAMETERS; } @@ -655,7 +659,7 @@ rsi_error_t clk_set_i2s_pll_freq(M4CLK_Type *pCLK, uint32_t i2sPllFreq, uint32_t /*==============================================*/ /** - * @fn rsi_error_t clk_i2s_pll_set_freq_div(M4CLK_Type *pCLK, + * @fn rsi_error_t clk_i2s_pll_set_freq_div(const M4CLK_Type *pCLK, * uint16_t u16DivFactor1, * uint16_t u16DivFactor2, * uint16_t nFactor, @@ -671,14 +675,16 @@ rsi_error_t clk_set_i2s_pll_freq(M4CLK_Type *pCLK, uint32_t i2sPllFreq, uint32_t * @return RSI_OK on success */ -rsi_error_t clk_i2s_pll_set_freq_div(M4CLK_Type *pCLK, +rsi_error_t clk_i2s_pll_set_freq_div(const M4CLK_Type *pCLK, uint16_t u16DivFactor1, uint16_t u16DivFactor2, uint16_t nFactor, uint16_t mFactor, uint16_t fcwF) { - uint16_t i2sreg1 = 0x1244, i2sreg2 = 0x5850, i2sreg3 = 0xba60; + uint16_t i2sreg1 = 0x1244; + uint16_t i2sreg2 = 0x5850; + uint16_t i2sreg3 = 0xba60; if (pCLK == NULL) { return INVALID_PARAMETERS; } @@ -705,13 +711,13 @@ rsi_error_t clk_i2s_pll_set_freq_div(M4CLK_Type *pCLK, /*==============================================*/ /** - * @fn rsi_error_t clk_i2s_pll_clk_set(M4CLK_Type *pCLK) + * @fn rsi_error_t clk_i2s_pll_clk_set(const M4CLK_Type *pCLK) * @brief This API is used to set the I2s_pll_clk * @param[in] pCLK : pointer to the processor clock source * @return RSI_OK on success */ -rsi_error_t clk_i2s_pll_clk_set(M4CLK_Type *pCLK) +rsi_error_t clk_i2s_pll_clk_set(const M4CLK_Type *pCLK) { if (pCLK == NULL) { return INVALID_PARAMETERS; @@ -795,7 +801,7 @@ rsi_error_t clk_intf_pll_turn_off(void) /*==============================================*/ /** - * @fn rsi_error_t clk_set_intf_pll_freq(M4CLK_Type *pCLK, uint32_t intfPllFreq, uint32_t pllRefClk) + * @fn rsi_error_t clk_set_intf_pll_freq(const M4CLK_Type *pCLK, uint32_t intfPllFreq, uint32_t pllRefClk) * @brief This API is used to set the INTFPLL clock to particular frequency * @param[in] pCLK : pointer to the processor clock source * @param[in] intfPllFreq : input frequency of PLL frequency @@ -803,14 +809,16 @@ rsi_error_t clk_intf_pll_turn_off(void) * @return RSI_OK on success */ -rsi_error_t clk_set_intf_pll_freq(M4CLK_Type *pCLK, uint32_t intfPllFreq, uint32_t pllRefClk) +rsi_error_t clk_set_intf_pll_freq(const M4CLK_Type *pCLK, uint32_t intfPllFreq, uint32_t pllRefClk) { uint16_t shiftFac = 0; uint16_t intfPllMulFac = 0; uint16_t intfPllDivFac = 0; uint16_t reg = 0; uint16_t dcoFreq = 0; - uint16_t intfreg1 = 0x31c9, intfreg3 = 0, intfPllTvRead = 0; + uint16_t intfreg1 = 0x31c9; + uint16_t intfreg3 = 0; + uint16_t intfPllTvRead = 0; /*Parameter validation */ if ((pCLK == NULL) || (intfPllFreq < INTF_PLL_MIN_FREQUECY) || (intfPllFreq > INTF_PLL_MAX_FREQUECY)) { @@ -980,7 +988,7 @@ rsi_error_t clk_set_intf_pll_freq(M4CLK_Type *pCLK, uint32_t intfPllFreq, uint32 /*==============================================*/ /** - * @fn rsi_error_t clk_intf_pll_set_freq_div(M4CLK_Type *pCLK, + * @fn rsi_error_t clk_intf_pll_set_freq_div(const M4CLK_Type *pCLK, * boolean_t clk_en, * uint16_t divFactor, * uint16_t nFactor, @@ -1000,7 +1008,7 @@ rsi_error_t clk_set_intf_pll_freq(M4CLK_Type *pCLK, uint32_t intfPllFreq, uint32 * @return RSI_OK on success */ -rsi_error_t clk_intf_pll_set_freq_div(M4CLK_Type *pCLK, +rsi_error_t clk_intf_pll_set_freq_div(const M4CLK_Type *pCLK, boolean_t clk_en, uint16_t divFactor, uint16_t nFactor, @@ -1009,7 +1017,10 @@ rsi_error_t clk_intf_pll_set_freq_div(M4CLK_Type *pCLK, uint16_t dcoFixSel, uint16_t ldoProg) { - uint16_t intfreg1 = 0x31c9, intfreg3 = 0, reg = 0, intfPllTvRead = 0; + uint16_t intfreg1 = 0x31c9; + uint16_t intfreg3 = 0; + uint16_t reg = 0; + uint16_t intfPllTvRead = 0; if (pCLK == NULL) { return INVALID_PARAMETERS; @@ -1135,13 +1146,13 @@ rsi_error_t clk_intf_pll_clk_reset(void) /*==============================================*/ /** - * @fn rsi_error_t clk_intf_pll_clk_set(M4CLK_Type *pCLK) + * @fn rsi_error_t clk_intf_pll_clk_set(const M4CLK_Type *pCLK) * @brief This API is used to Enable the Intf_PLL * @param[in] pCLK : pointer to the processor clock source * @return RSI_OK on success */ -rsi_error_t clk_intf_pll_clk_set(M4CLK_Type *pCLK) +rsi_error_t clk_intf_pll_clk_set(const M4CLK_Type *pCLK) { if (pCLK == NULL) { return INVALID_PARAMETERS; @@ -2740,7 +2751,7 @@ void clk_config_pll_lock(boolean_t manual_lock, boolean_t bypass_manual_lock, ui /*==============================================*/ /** - * @fn uint32_t RSI_CLK_CheckPresent(M4CLK_Type *pCLK ,CLK_PRESENT_T clkPresent) + * @fn uint32_t RSI_CLK_CheckPresent(const M4CLK_Type *pCLK ,CLK_PRESENT_T clkPresent) * @brief This API is used to enable the dynamic clock gate for peripherals * @param[in] pCLK : Pointer to the pll register instance \ref M4CLK_Type * @param[in] clkPresent : structure variable of CLK_PRESENT_T , \ref CLK_PRESENT_T @@ -2749,7 +2760,7 @@ void clk_config_pll_lock(boolean_t manual_lock, boolean_t bypass_manual_lock, ui * ERROR_CLOCK_NOT_ENABLED */ -uint32_t RSI_CLK_CheckPresent(M4CLK_Type *pCLK, CLK_PRESENT_T clkPresent) +uint32_t RSI_CLK_CheckPresent(const M4CLK_Type *pCLK, CLK_PRESENT_T clkPresent) { uint32_t errorReturn = 0; switch (clkPresent) { @@ -2787,14 +2798,14 @@ uint32_t RSI_CLK_CheckPresent(M4CLK_Type *pCLK, CLK_PRESENT_T clkPresent) /*==============================================*/ /** - * @fn rsi_error_t clk_m4ss_ref_clk_config(M4CLK_Type *pCLK, M4SS_REF_CLK_SEL_T clkSource) + * @fn rsi_error_t clk_m4ss_ref_clk_config(const M4CLK_Type *pCLK, M4SS_REF_CLK_SEL_T clkSource) * @brief This API is used to configure the m4ss_ref clocks * @param[in] pCLK is pointer to the processor clock source * @param[in] clkSource is source clock * @return RSI_OK on success */ -rsi_error_t clk_m4ss_ref_clk_config(M4CLK_Type *pCLK, M4SS_REF_CLK_SEL_T clkSource) +rsi_error_t clk_m4ss_ref_clk_config(const M4CLK_Type *pCLK, M4SS_REF_CLK_SEL_T clkSource) { if (pCLK == NULL) { return INVALID_PARAMETERS; diff --git a/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_rtc.c b/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_rtc.c index a7add0937..a65357277 100644 --- a/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_rtc.c +++ b/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_rtc.c @@ -94,7 +94,7 @@ void RSI_RTC_Stop(RTC_Type *Cal) /*==============================================*/ /** - * @fn rsi_error_t RSI_RTC_SetDateTime(RTC_Type *Cal, RTC_TIME_CONFIG_T *date) + * @fn rsi_error_t RSI_RTC_SetDateTime(RTC_Type *Cal, const RTC_TIME_CONFIG_T *date) * @brief This API is used to set the rtc configuration * @param[in] Cal : pointer to the rtc register instance * @param[in] date : pointer to the rtc configuration structure @@ -103,7 +103,7 @@ void RSI_RTC_Stop(RTC_Type *Cal) * - Error code on failure */ -rsi_error_t RSI_RTC_SetDateTime(RTC_Type *Cal, RTC_TIME_CONFIG_T *date) +rsi_error_t RSI_RTC_SetDateTime(RTC_Type *Cal, const RTC_TIME_CONFIG_T *date) { if ((Cal == NULL) || (date == NULL)) { return ERROR_CAL_INVALID_PARAMETERS; @@ -132,7 +132,7 @@ rsi_error_t RSI_RTC_SetDateTime(RTC_Type *Cal, RTC_TIME_CONFIG_T *date) /*==============================================*/ /** - * @fn rsi_error_t RSI_RTC_GetDateTime(RTC_Type *Cal, RTC_TIME_CONFIG_T *date) + * @fn rsi_error_t RSI_RTC_GetDateTime(const RTC_Type *Cal, RTC_TIME_CONFIG_T *date) * @brief This API is used to Get the RTC time * @param[in] Cal : pointer to the rtc register instance * @param[in] date : pointer to the rtc structure to hold the current time parameters @@ -141,7 +141,7 @@ rsi_error_t RSI_RTC_SetDateTime(RTC_Type *Cal, RTC_TIME_CONFIG_T *date) * - Error code on failure */ -rsi_error_t RSI_RTC_GetDateTime(RTC_Type *Cal, RTC_TIME_CONFIG_T *date) +rsi_error_t RSI_RTC_GetDateTime(const RTC_Type *Cal, RTC_TIME_CONFIG_T *date) { if ((Cal == NULL) || (date == NULL)) { return ERROR_CAL_INVALID_PARAMETERS; @@ -161,7 +161,7 @@ rsi_error_t RSI_RTC_GetDateTime(RTC_Type *Cal, RTC_TIME_CONFIG_T *date) /*==============================================*/ /** - * @fn rsi_error_t RSI_RTC_SetAlarmDateTime(RTC_Type *Cal, RTC_TIME_CONFIG_T *alarm) + * @fn rsi_error_t RSI_RTC_SetAlarmDateTime(RTC_Type *Cal, const RTC_TIME_CONFIG_T *alarm) * @brief This API is used to Set the alarm for RTC module * @param[in] Cal : pointer to the rtc register instance * @param[in] alarm : pointer to alarm configuration structure @@ -170,7 +170,7 @@ rsi_error_t RSI_RTC_GetDateTime(RTC_Type *Cal, RTC_TIME_CONFIG_T *date) * - Error code on failure */ -rsi_error_t RSI_RTC_SetAlarmDateTime(RTC_Type *Cal, RTC_TIME_CONFIG_T *alarm) +rsi_error_t RSI_RTC_SetAlarmDateTime(RTC_Type *Cal, const RTC_TIME_CONFIG_T *alarm) { if ((Cal == NULL) || (alarm == NULL)) { return ERROR_CAL_INVALID_PARAMETERS; @@ -215,7 +215,7 @@ void RSI_RTC_AlamEnable(RTC_Type *Cal, boolean_t val) /*==============================================*/ /** - * @fn rsi_error_t RSI_RTC_GetAlarmDateTime(RTC_Type *Cal, RTC_TIME_CONFIG_T *alarm) + * @fn rsi_error_t RSI_RTC_GetAlarmDateTime(const RTC_Type *Cal, RTC_TIME_CONFIG_T *alarm) * @brief This API is used to Get alarm configurations for RTC * @param[in] Cal : pointer to the rtc register instance * @param[in] alarm : pointer to the rtc alarm configuration structure @@ -224,7 +224,7 @@ void RSI_RTC_AlamEnable(RTC_Type *Cal, boolean_t val) * - Error code on failure */ -rsi_error_t RSI_RTC_GetAlarmDateTime(RTC_Type *Cal, RTC_TIME_CONFIG_T *alarm) +rsi_error_t RSI_RTC_GetAlarmDateTime(const RTC_Type *Cal, RTC_TIME_CONFIG_T *alarm) { if ((Cal == NULL) || (alarm == NULL)) { return ERROR_CAL_INVALID_PARAMETERS; diff --git a/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_temp_sensor.c b/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_temp_sensor.c index f55a3e693..24ca6e770 100644 --- a/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_temp_sensor.c +++ b/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_temp_sensor.c @@ -95,13 +95,13 @@ void RSI_TS_Config(MCU_TEMP_Type *pstcTempSens, uint32_t u32Nomial) /*==============================================*/ /** - * @fn uint32_t RSI_TS_ReadTemp(MCU_TEMP_Type *pstcTempSens) + * @fn uint32_t RSI_TS_ReadTemp(const MCU_TEMP_Type *pstcTempSens) * @brief This API is used to read the temperature value * @param[in] pstcTempSens : pointer to the temperature sensor register instance * @return returns the temperature value */ -uint32_t RSI_TS_ReadTemp(MCU_TEMP_Type *pstcTempSens) +uint32_t RSI_TS_ReadTemp(const MCU_TEMP_Type *pstcTempSens) { /*Wait for done */ while (pstcTempSens->TS_ENABLE_AND_TEMPERATURE_DONE_b.TEMP_MEASUREMENT_DONE != 1) @@ -123,7 +123,6 @@ uint32_t RSI_TS_ReadTemp(MCU_TEMP_Type *pstcTempSens) void RSI_TS_RoBjtEnable(MCU_TEMP_Type *pstcTempSens, boolean_t enable) { - uint32_t i; if (pstcTempSens->TS_SLOPE_SET_b.BJT_BASED_TEMP == 1U) { if (enable == 1U) { @@ -135,7 +134,7 @@ void RSI_TS_RoBjtEnable(MCU_TEMP_Type *pstcTempSens, boolean_t enable) if (pstcTempSens->TS_SLOPE_SET_b.BJT_BASED_TEMP == 0U) { if (enable == 1U) { pstcTempSens->TS_SLOPE_SET_b.BJT_BASED_TEMP = 1; - for (i = 100; i; i--) + for (uint32_t i = 100; i; i--) ; // wait for 100 us } else { pstcTempSens->TS_SLOPE_SET_b.BJT_BASED_TEMP = (unsigned int)(enable & 0x01); //0 @@ -161,13 +160,13 @@ void RSI_TS_LoadBjt(MCU_TEMP_Type *pstcTempSens, uint8_t temp) /*==============================================*/ /** - * @fn uint32_t RSI_TS_GetRefClkCnt(MCU_TEMP_Type *pstcTempSens) + * @fn uint32_t RSI_TS_GetRefClkCnt(const MCU_TEMP_Type *pstcTempSens) * @brief This API is used to read the reference clock count * @param[in] pstcTempSens : pointer to the temperature sensor register instance * @return returns the reference clock count */ -uint32_t RSI_TS_GetRefClkCnt(MCU_TEMP_Type *pstcTempSens) +uint32_t RSI_TS_GetRefClkCnt(const MCU_TEMP_Type *pstcTempSens) { /*Return the count value*/ return pstcTempSens->TS_COUNTS_READ_b.COUNT_F1; @@ -175,13 +174,13 @@ uint32_t RSI_TS_GetRefClkCnt(MCU_TEMP_Type *pstcTempSens) /*==============================================*/ /** - * @fn uint32_t RSI_TS_GetPtatClkCnt(MCU_TEMP_Type *pstcTempSens) + * @fn uint32_t RSI_TS_GetPtatClkCnt(const MCU_TEMP_Type *pstcTempSens) * @brief This API is used to read the ptat clock count * @param[in] pstcTempSens : pointer to the temperature sensor register instance * @return returns the ptat clock count */ -uint32_t RSI_TS_GetPtatClkCnt(MCU_TEMP_Type *pstcTempSens) +uint32_t RSI_TS_GetPtatClkCnt(const MCU_TEMP_Type *pstcTempSens) { /*Return the count value*/ return pstcTempSens->TS_COUNTS_READ_b.COUNT_F2; diff --git a/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_time_period.c b/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_time_period.c index db375869c..11fd02196 100644 --- a/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_time_period.c +++ b/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_time_period.c @@ -113,12 +113,12 @@ rsi_error_t RSI_TIMEPERIOD_RCCalibration(TIME_PERIOD_Type *pstcTimePeriod, /*==============================================*/ /** - * @fn uint32_t RSI_TIMEPERIOD_RCCalibTimePeriodRead(TIME_PERIOD_Type *pstcTimePeriod) + * @fn uint32_t RSI_TIMEPERIOD_RCCalibTimePeriodRead(const TIME_PERIOD_Type *pstcTimePeriod) * @brief This API is used to read calibrated timeperiod of RC * @param[in] pstcTimePeriod is pointer to the timperiod calibration registration instance * @return Returns the time period on success */ -uint32_t RSI_TIMEPERIOD_RCCalibTimePeriodRead(TIME_PERIOD_Type *pstcTimePeriod) +uint32_t RSI_TIMEPERIOD_RCCalibTimePeriodRead(const TIME_PERIOD_Type *pstcTimePeriod) { if (pstcTimePeriod == NULL) { return ERROR_TIME_PERIOD_PARAMETERS; @@ -132,13 +132,13 @@ uint32_t RSI_TIMEPERIOD_RCCalibTimePeriodRead(TIME_PERIOD_Type *pstcTimePeriod) /*==============================================*/ /** - * @fn uint32_t RSI_TIMEPERIOD_ROCalibTimePeriodRead(TIME_PERIOD_Type *pstcTimePeriod) + * @fn uint32_t RSI_TIMEPERIOD_ROCalibTimePeriodRead(const TIME_PERIOD_Type *pstcTimePeriod) * @brief This API is used to read calibrated timeperiod of RO * @param[in] pstcTimePeriod : pointer to the timperiod calibration registration instance * @return Returns the time period on success */ -uint32_t RSI_TIMEPERIOD_ROCalibTimePeriodRead(TIME_PERIOD_Type *pstcTimePeriod) +uint32_t RSI_TIMEPERIOD_ROCalibTimePeriodRead(const TIME_PERIOD_Type *pstcTimePeriod) { if (pstcTimePeriod == NULL) { return ERROR_TIME_PERIOD_PARAMETERS; diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/component/bss_segment_in_psram.slcc b/components/device/silabs/si91x/mcu/drivers/unified_api/component/bss_segment_in_psram.slcc index 57aae9d89..7014915ec 100644 --- a/components/device/silabs/si91x/mcu/drivers/unified_api/component/bss_segment_in_psram.slcc +++ b/components/device/silabs/si91x/mcu/drivers/unified_api/component/bss_segment_in_psram.slcc @@ -7,6 +7,8 @@ category: Device|Si91x|MCU|Peripheral|PSRAM Driver|PSRAM Linker Configurations quality: production provides: - name: bss_segment_in_psram +requires: + - name: wiseconnect_toolchain_psram_linker template_contribution: - name: bss_segment_in_psram value: 1 diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/component/data_segment_in_psram.slcc b/components/device/silabs/si91x/mcu/drivers/unified_api/component/data_segment_in_psram.slcc index 0ad925fbf..8cc0a00ab 100644 --- a/components/device/silabs/si91x/mcu/drivers/unified_api/component/data_segment_in_psram.slcc +++ b/components/device/silabs/si91x/mcu/drivers/unified_api/component/data_segment_in_psram.slcc @@ -5,8 +5,13 @@ description: > This component puts Data segment in PSRAM memory region category: Device|Si91x|MCU|Peripheral|PSRAM Driver|PSRAM Linker Configurations quality: production +define: + - name: NO_DATA_SEGMENT_IN_PSRAM + condition: [device_needs_ram_execution] provides: - name: data_segment_in_psram +requires: + - name: wiseconnect_toolchain_psram_linker template_contribution: - name: data_segment_in_psram value: 1 diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/component/heap_segment_in_psram.slcc b/components/device/silabs/si91x/mcu/drivers/unified_api/component/heap_segment_in_psram.slcc index e23e34cd6..6886e4137 100644 --- a/components/device/silabs/si91x/mcu/drivers/unified_api/component/heap_segment_in_psram.slcc +++ b/components/device/silabs/si91x/mcu/drivers/unified_api/component/heap_segment_in_psram.slcc @@ -7,6 +7,8 @@ category: Device|Si91x|MCU|Peripheral|PSRAM Driver|PSRAM Linker Configurations quality: production provides: - name: heap_segment_in_psram +requires: + - name: wiseconnect_toolchain_psram_linker template_contribution: - name: heap_segment_in_psram value: 1 diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/component/i2c_instance.slcc b/components/device/silabs/si91x/mcu/drivers/unified_api/component/i2c_instance.slcc index bbdb3c702..7d80cb814 100644 --- a/components/device/silabs/si91x/mcu/drivers/unified_api/component/i2c_instance.slcc +++ b/components/device/silabs/si91x/mcu/drivers/unified_api/component/i2c_instance.slcc @@ -18,6 +18,9 @@ description: > I2C Supports instances. Instances created must be named as I2C0, I2C1, I2C2. + + Note: When utilizing the I2C2 instance in high power mode with DMA enabled, it is advisable to allocate buffers in the ULP Memory block. + For further details on buffer allocation, please refer to the ULP I2C Driver Leader example. category: Device|Si91x|MCU|Peripheral quality: production instantiable: diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/component/sl_dma.slcc b/components/device/silabs/si91x/mcu/drivers/unified_api/component/sl_dma.slcc index 3c135cf2e..10555e26d 100644 --- a/components/device/silabs/si91x/mcu/drivers/unified_api/component/sl_dma.slcc +++ b/components/device/silabs/si91x/mcu/drivers/unified_api/component/sl_dma.slcc @@ -11,6 +11,9 @@ description: > When you install this component, it will also be installing the DMA dependency component, which is the DMA driver's implementation. + + Note: When utilizing the UDMA1 instance in high power mode, it is advisable to allocate buffers in the ULP Memory block. + For further details on buffer allocation, please refer to the ULP UDMA example. category: Device|Si91x|MCU|Peripheral quality: production root_path: "components/device/silabs/si91x/mcu/drivers/unified_api" diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/component/sl_i2s.slcc b/components/device/silabs/si91x/mcu/drivers/unified_api/component/sl_i2s.slcc index ee7da59d0..ce9967af4 100644 --- a/components/device/silabs/si91x/mcu/drivers/unified_api/component/sl_i2s.slcc +++ b/components/device/silabs/si91x/mcu/drivers/unified_api/component/sl_i2s.slcc @@ -13,6 +13,9 @@ description: > When you install this component, it will also be installing the I2S dependency component, which is the I2S driver's implementation. + + Note: When utilizing the I2S1 instance in high power mode with DMA enabled, it is advisable to allocate buffers in the ULP Memory block. + For further details on buffer allocation, please refer to the ULP I2S example. category: Device|Si91x|MCU|Peripheral quality: production root_path: "components/device/silabs/si91x/mcu/drivers/unified_api" diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/component/sl_ro_temperature_sensor.slcc b/components/device/silabs/si91x/mcu/drivers/unified_api/component/sl_ro_temperature_sensor.slcc deleted file mode 100644 index 9546060ff..000000000 --- a/components/device/silabs/si91x/mcu/drivers/unified_api/component/sl_ro_temperature_sensor.slcc +++ /dev/null @@ -1,26 +0,0 @@ -id: sl_ro_temperature_sensor -label: RO Temperature Sensor -package: platform -description: > - A Ring Oscillator Temperature Sensor (RO Temperature Sensor) is a type of temperature sensor that utilizes - a ring oscillator circuit to measure temperature variations. - A ring oscillator is a circuit configuration that consists of an odd number of inverters connected in a loop. - The frequency of oscillation of the ring oscillator is influenced by various factors, including temperature. - It is dependent on some of the parameters like: - Ring Oscillator, Temperature Sensitivity, Frequency measurement, Temperature Calibration. -category: Device|Si91x|MCU|Peripheral -quality: production -component_root_path: "components/device/silabs/si91x/mcu/drivers/unified_api" -source: - - path: "src/sl_si91x_ro_temperature_sensor.c" -include: - - path: "inc" - file_list: - - path: "sl_si91x_ro_temperature_sensor.h" -provides: - - name: sl_ro_temperature_sensor -requires: - - name: systemlevel_temp_sensor -documentation: - docset: wiseconnect - document: wiseconnect-api-reference-guide-si91x-peripherals/rotempsensor \ No newline at end of file diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/component/sl_sio_peripheral.slcc b/components/device/silabs/si91x/mcu/drivers/unified_api/component/sl_sio_peripheral.slcc deleted file mode 100644 index 82c51e44c..000000000 --- a/components/device/silabs/si91x/mcu/drivers/unified_api/component/sl_sio_peripheral.slcc +++ /dev/null @@ -1,39 +0,0 @@ -id: sl_sio_peripheral -label: SIO -package: platform -description: > - SIO (Serial Input Output) is used for data transfer between sensors and - Micro controllers by using SPI and UART protocols. - In SIO SPI transfer of data will be between MOSI and MISO that is master/slave communication. - As well as demonstrates SIO UART send and receive data - Configurable parameters in SIO: - - Frequency - - Select the Mode - - Baud Rate - - Channel Number - - Data width -category: Device|Si91x|MCU|Peripheral -quality: production -root_path: "components/device/silabs/si91x/mcu/drivers" -config_file: - - path: unified_api/config/sl_si91x_sio_config.h -source: - - path: "unified_api/src/sl_si91x_sio.c" - - path: "unified_peripheral_drivers/src/sl_si91x_peripheral_gpio.c" -include: - - path: "unified_api/inc" - file_list: - - path: "sl_si91x_sio.h" - - path: "unified_peripheral_drivers/inc" - file_list: - - path: "sl_si91x_peripheral_gpio.h" - - path: "sl_si91x_gpio.h" - - path: "sl_si91x_gpio_common.h" -provides: - - name: sl_sio_peripheral -requires: - - name: udma_linker_config - - name: rsilib_sio -documentation: - docset: wiseconnect - document: wiseconnect-api-reference-guide-si91x-peripherals/sio \ No newline at end of file diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/component/sl_ssi.slcc b/components/device/silabs/si91x/mcu/drivers/unified_api/component/sl_ssi.slcc index 968371aef..e0abd9a82 100644 --- a/components/device/silabs/si91x/mcu/drivers/unified_api/component/sl_ssi.slcc +++ b/components/device/silabs/si91x/mcu/drivers/unified_api/component/sl_ssi.slcc @@ -12,6 +12,9 @@ description: > When you install this component, it will also be installing the SSI dependency component, which is the SSI driver's implementation. + + Note: When utilizing the ULP SSI instance in high power mode with DMA enabled, it is advisable to allocate buffers in the ULP Memory block. + For further details on buffer allocation, please refer to the ULP SSI MASTER example. category: Device|Si91x|MCU|Peripheral quality: production root_path: "components/device/silabs/si91x/mcu/drivers/unified_api" diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/component/sl_ulp_uart.slcc b/components/device/silabs/si91x/mcu/drivers/unified_api/component/sl_ulp_uart.slcc index e93ff88c0..d28761675 100644 --- a/components/device/silabs/si91x/mcu/drivers/unified_api/component/sl_ulp_uart.slcc +++ b/components/device/silabs/si91x/mcu/drivers/unified_api/component/sl_ulp_uart.slcc @@ -9,6 +9,9 @@ description: > Configurable parameters in ULP UART: - Baud Rate - Data Width + + Note: When utilizing the ULP UART instance in high power mode with DMA enabled, it is advisable to allocate buffers in the ULP Memory block. + For further details on buffer allocation, please refer to the ULP UART example. category: Device|Si91x|MCU|Peripheral quality: production root_path: "components/device/silabs/si91x/mcu/drivers/unified_api" diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/component/sl_watchdog_timer.slcc b/components/device/silabs/si91x/mcu/drivers/unified_api/component/sl_watchdog_timer.slcc index 3dccb8e35..776bdb4c5 100644 --- a/components/device/silabs/si91x/mcu/drivers/unified_api/component/sl_watchdog_timer.slcc +++ b/components/device/silabs/si91x/mcu/drivers/unified_api/component/sl_watchdog_timer.slcc @@ -12,6 +12,7 @@ quality: production root_path: "components/device/silabs/si91x/mcu/drivers/unified_api" config_file: - path: "config/sl_si91x_watchdog_timer_config.h" + unless: [sl_wdt_manager] source: - path: "src/sl_si91x_watchdog_timer.c" include: diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/component/stack_segment_in_psram.slcc b/components/device/silabs/si91x/mcu/drivers/unified_api/component/stack_segment_in_psram.slcc index f83e9cbb0..bf400ca09 100644 --- a/components/device/silabs/si91x/mcu/drivers/unified_api/component/stack_segment_in_psram.slcc +++ b/components/device/silabs/si91x/mcu/drivers/unified_api/component/stack_segment_in_psram.slcc @@ -7,6 +7,8 @@ category: Device|Si91x|MCU|Peripheral|PSRAM Driver|PSRAM Linker Configurations quality: production provides: - name: stack_segment_in_psram +requires: + - name: wiseconnect_toolchain_psram_linker template_contribution: - name: stack_segment_in_psram value: 1 diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/component/text_segment_in_psram.slcc b/components/device/silabs/si91x/mcu/drivers/unified_api/component/text_segment_in_psram.slcc index 412370895..b6d68ec34 100644 --- a/components/device/silabs/si91x/mcu/drivers/unified_api/component/text_segment_in_psram.slcc +++ b/components/device/silabs/si91x/mcu/drivers/unified_api/component/text_segment_in_psram.slcc @@ -7,10 +7,10 @@ category: Device|Si91x|MCU|Peripheral|PSRAM Driver|PSRAM Linker Configurations quality: production provides: - name: text_segment_in_psram +requires: + - name: wiseconnect_toolchain_psram_linker template_contribution: - name: text_segment_in_psram value: 1 - name: psram_linker_config_enabled - value: 1 -conflicts: - - name: device_needs_ram_execution \ No newline at end of file + value: 1 \ No newline at end of file diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/config/sl_si91x_dac_config.h b/components/device/silabs/si91x/mcu/drivers/unified_api/config/sl_si91x_dac_config.h index 9b575c411..b4202400a 100644 --- a/components/device/silabs/si91x/mcu/drivers/unified_api/config/sl_si91x_dac_config.h +++ b/components/device/silabs/si91x/mcu/drivers/unified_api/config/sl_si91x_dac_config.h @@ -43,7 +43,6 @@ extern "C" { // DAC operation mode // FIFO mode // Static mode -// Reference voltage for ADC // Selection of DAC operation mode. #define SL_DAC_OPERATION_MODE SL_DAC_STATIC_MODE @@ -55,49 +54,26 @@ extern "C" { // Default: 3 #define SL_DAC_FIFO_THRESHOLD 3 -// ADC Channel -// Channel_0 -// Channel_1 -// Channel_2 -// Channel_3 -// Channel_4 -// Channel_5 -// Channel_6 -// Channel_7 -// Channel_8 -// Channel_9 -// Channel_10 -// Channel_11 -// Channel_12 -// Channel_13 -// Channel_14 -// Channel_15 -// Selection of ADC Channel. -#define SL_DAC_ADC_CHANNEL SL_DAC_ADC_CHANNEL_0 - // // <<< end of configuration section >>> // <<< sl:start pin_tool >>> -// SL_DAC0 +// SL_DAC0 // $[DAC_SL_DAC0] #ifndef SL_DAC0_PERIPHERAL #define SL_DAC0_PERIPHERAL DAC0 #endif -#ifndef SL_DAC0_PERIPHERAL_NO -#define SL_DAC0_PERIPHERAL_NO 0 -#endif -// DAC0 IN1 on GPIO_30 -#ifndef SL_DAC0_IN1_PORT -#define SL_DAC0_IN1_PORT 0 +// DAC0 OUT on ULP_GPIO_4/GPIO_68 +#ifndef SL_DAC0_OUT_PORT +#define SL_DAC0_OUT_PORT 0 #endif -#ifndef SL_DAC0_IN1_PIN -#define SL_DAC0_IN1_PIN 4 +#ifndef SL_DAC0_OUT_PIN +#define SL_DAC0_OUT_PIN 4 #endif -#ifndef SL_DAC0_IN1_LOC -#define SL_DAC0_IN1_LOC 0 +#ifndef SL_DAC0_OUT_LOC +#define SL_DAC0_OUT_LOC 0 #endif // [DAC_SL_DAC0]$ // <<< sl:end pin_tool >>> @@ -107,14 +83,14 @@ extern "C" { #define SL_DAC_OUTPUT_PORT 0 #define SL_DAC_OUTPUT_PIN 30 #else -#define SL_DAC_OUTPUT_PORT SL_DAC0_IN1_PORT -#define SL_DAC_OUTPUT_PIN SL_DAC0_IN1_PIN +#define SL_DAC_OUTPUT_PORT SL_DAC0_OUT_PORT +#define SL_DAC_OUTPUT_PIN SL_DAC0_OUT_PIN #endif sl_dac_config_t sl_dac_config = { .operating_mode = SL_DAC_OPERATION_MODE, .dac_fifo_threshold = SL_DAC_FIFO_THRESHOLD, .dac_sample_rate = SL_DAC_SAMPLE_RATE, - .adc_channel = SL_DAC_ADC_CHANNEL, + .adc_channel = 0, .dac_pin = SL_DAC_OUTPUT_PIN, .dac_port = SL_DAC_OUTPUT_PORT }; diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/config/sl_si91x_gspi_config.h b/components/device/silabs/si91x/mcu/drivers/unified_api/config/sl_si91x_gspi_config.h index 15d4b1a12..15f57384d 100644 --- a/components/device/silabs/si91x/mcu/drivers/unified_api/config/sl_si91x_gspi_config.h +++ b/components/device/silabs/si91x/mcu/drivers/unified_api/config/sl_si91x_gspi_config.h @@ -57,13 +57,13 @@ extern "C" { // Default: 10000000 #define SL_GSPI_BITRATE 10000000 -// Data Width <1-15> +// Data Width <1-16> // Default: 8 #define SL_GSPI_BIT_WIDTH 8 // Byte-wise Swapping Read -// Default: 1 -#define SL_GSPI_SWAP_READ_DATA 1 +// Default: 0 +#define SL_GSPI_SWAP_READ_DATA 0 // Byte-wise Swapping Write // Default: 0 diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/config/sl_si91x_sio_config.h b/components/device/silabs/si91x/mcu/drivers/unified_api/config/sl_si91x_sio_config.h deleted file mode 100644 index f8f37cb64..000000000 --- a/components/device/silabs/si91x/mcu/drivers/unified_api/config/sl_si91x_sio_config.h +++ /dev/null @@ -1,767 +0,0 @@ -/***************************************************************************/ /** - * @file sl_si91x_sio_config.h - * @brief SL SIO Config. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_SIO_CONFIG_H -#define SL_SIO_CONFIG_H - -#include "sl_si91x_sio.h" -#include "sl_sio_board.h" - -// <<< Use Configuration Wizard in Context Menu >>> -#ifdef __cplusplus -extern "C" { -#endif - -// SIO UC Configuration -// Enable: Peripheral configuration is taken straight from the configuration set in the universal configuration (UC). -// Disable: If the application demands it to be modified during runtime, use the sl_si91x_sio_spi_init API to modify the peripheral configuration. -// Default: 1 -#define SIO_UC 1 - -// SPI Configuration - -// Clock <9600-7372800> -// Default: 1000000 -#define SL_SIO_SPI_CLK_FREQUENCY 1000000 - -// Mode -// Mode 0 -// Mode 3 -// Default: SL_SIO_SPI_MODE_3 -#define SL_SIO_SPI_MODE SL_SIO_SPI_MODE_3 - -// Clock Channel -// Channel 0 -// Channel 1 -// Channel 2 -// Channel 3 -// Channel 4 -// Channel 5 -// Channel 6 -// Channel 7 -// Default: SL_SIO_CH_1 -#define SL_SIO_SPI_CLK_CH SL_SIO_CH_1 - -// MOSI Channel -// Channel 0 -// Channel 1 -// Channel 2 -// Channel 3 -// Channel 4 -// Channel 5 -// Channel 6 -// Channel 7 -// Default: SL_SIO_CH_3 -#define SL_SIO_SPI_MOSI_CH SL_SIO_CH_3 - -// MISO Channel -// Channel 0 -// Channel 1 -// Channel 2 -// Channel 3 -// Channel 4 -// Channel 5 -// Channel 6 -// Channel 7 -// Default: SL_SIO_CH_2 -#define SL_SIO_SPI_MISO_CH SL_SIO_CH_2 - -// CS Channel -// Channel 0 -// Channel 1 -// Channel 2 -// Channel 3 -// Channel 4 -// Channel 5 -// Channel 6 -// Channel 7 -// Default: SL_SIO_CH_0 -#define SL_SIO_SPI_CS_CH SL_SIO_CH_0 - -// Data Width -// Data Width 8 -// Data Width 16 -// Default: SL_SIO_SPI_BIT_16 -#define SL_SIO_SPI_BIT_LEN SL_SIO_SPI_BIT_16 - -// MSB/LSB First -// MSB First -// LSB First -// Default: SL_SIO_SPI_MSB_FIRST -#define SL_SIO_SPI_MSB_LSB_FIRST SL_SIO_SPI_MSB_FIRST -// - -// UART Configuration - -// Baud Rate <4800-128000> -// Default: 115200 -#define SL_SIO_UART_BAUD_RATE 115200 - -// Bit Length -// Bit Length 8 -// Bit Length 9 -// Default: SL_SIO_UART_BIT_8 -#define SL_SIO_UART_BIT_LENGTH SL_SIO_UART_BIT_8 - -// Parity -// Even Parity 0 -// Odd Parity 1 -// Default: SL_SIO_UART_EVEN_PARITY -#define SL_SIO_UART_PARITY SL_SIO_UART_EVEN_PARITY - -// Receive Channel -// Channel 0 -// Channel 1 -// Channel 2 -// Channel 3 -// Channel 4 -// Channel 5 -// Channel 6 -// Channel 7 -// Default: SL_SIO_CH_2 -#define SL_SIO_UART_RX_CH SL_SIO_CH_2 - -// Transmit channel -// Channel 0 -// Channel 1 -// Channel 2 -// Channel 3 -// Channel 4 -// Channel 5 -// Channel 6 -// Channel 7 -// Default: SL_SIO_CH_3 -#define SL_SIO_UART_TX_CH SL_SIO_CH_3 - -// Stop Bit -// Stop Bit 1 -// Stop Bit 2 -// Default: SL_SIO_UART_STOP_BIT_1 -#define SL_SIO_UART_STOP_BIT SL_SIO_UART_STOP_BIT_1 - -// - -// - -#define SL_SIO_I2C_SAMPLE_RATE 100000 - -#define SL_SIO_I2C_SCL_CHANNEL SL_SIO_CH_6 - -#define SL_SIO_I2C_SDA_CHANNEL SL_SIO_CH_7 - -#ifdef __cplusplus -} -#endif -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_SIO -// $[SIO_SL_SIO] -#ifndef SL_SIO_PERIPHERAL -#define SL_SIO_PERIPHERAL SIO -#endif - -// SIO SIO0 on GPIO_6 -#ifndef SL_SIO_SIO0_PORT -#define SL_SIO_SIO0_PORT 0 -#endif -#ifndef SL_SIO_SIO0_PIN -#define SL_SIO_SIO0_PIN 6 -#endif -#ifndef SL_SIO_0_LOC -#define SL_SIO_0_LOC 0 -#endif - -// SIO SIO1 on GPIO_26 -#ifndef SL_SIO_SIO1_PORT -#define SL_SIO_SIO1_PORT 0 -#endif -#ifndef SL_SIO_SIO1_PIN -#define SL_SIO_SIO1_PIN 26 -#endif -#ifndef SL_SIO_1_LOC -#define SL_SIO_1_LOC 5 -#endif - -// SIO SIO2 on GPIO_27 -#ifndef SL_SIO_SIO2_PORT -#define SL_SIO_SIO2_PORT 0 -#endif -#ifndef SL_SIO_SIO2_PIN -#define SL_SIO_SIO2_PIN 27 -#endif -#ifndef SL_SIO_2_LOC -#define SL_SIO_2_LOC 9 -#endif - -// SIO SIO3 on GPIO_28 -#ifndef SL_SIO_SIO3_PORT -#define SL_SIO_SIO3_PORT 0 -#endif -#ifndef SL_SIO_SIO3_PIN -#define SL_SIO_SIO3_PIN 28 -#endif -#ifndef SL_SIO_3_LOC -#define SL_SIO_3_LOC 12 -#endif - -// SIO SIO4 on GPIO_29 -#ifndef SL_SIO_SIO4_PORT -#define SL_SIO_SIO4_PORT 0 -#endif -#ifndef SL_SIO_SIO4_PIN -#define SL_SIO_SIO4_PIN 29 -#endif -#ifndef SL_SIO_4_LOC -#define SL_SIO_4_LOC 15 -#endif - -// SIO SIO5 on GPIO_11 -#ifndef SL_SIO_SIO5_PORT -#define SL_SIO_SIO5_PORT 0 -#endif -#ifndef SL_SIO_SIO5_PIN -#define SL_SIO_SIO5_PIN 11 -#endif -#ifndef SL_SIO_5_LOC -#define SL_SIO_5_LOC 17 -#endif - -// SIO SIO6 on ULP_GPIO_6/GPIO_70 -#ifndef SL_SIO_SIO6_PORT -#define SL_SIO_SIO6_PORT 0 -#endif -#ifndef SL_SIO_SIO6_PIN -#define SL_SIO_SIO6_PIN 6 -#endif -#ifndef SL_SIO_6_LOC -#define SL_SIO_6_LOC 20 -#endif - -// SIO SIO7 on ULP_GPIO_7/GPIO_71 -#ifndef SL_SIO_SIO7_PORT -#define SL_SIO_SIO7_PORT 0 -#endif -#ifndef SL_SIO_SIO7_PIN -#define SL_SIO_SIO7_PIN 7 -#endif -#ifndef SL_SIO_7_LOC -#define SL_SIO_7_LOC 22 -#endif -// [SIO_SL_SIO]$ -// <<< sl:end pin_tool >>> - -#if defined(SL_SIO_SPI_CLK_FREQUENCY) -stc_sio_spi_cfg_t pstcSpiConfigUc = { - .u32SpiClockFrq = SL_SIO_SPI_CLK_FREQUENCY, - .u8BitOrder = SL_SIO_SPI_MSB_LSB_FIRST, - .u8SpiClkCh = SL_SIO_SPI_CLK_CH, - .u8SpiMosiCh = SL_SIO_SPI_MOSI_CH, - .u8SpiMisoCh = SL_SIO_SPI_MISO_CH, - .u8SpiCsCh = SL_SIO_SPI_CS_CH, - .u8BitLen = SL_SIO_SPI_BIT_LEN, - .u8Mode = SL_SIO_SPI_MODE, -}; - -#if (SL_SIO_0_LOC == 2) -#define SL_SI91X_SIO0_PIN (SL_SIO_SIO0_PIN + 64) -#else -#define SL_SI91X_SIO0_PIN SL_SIO_SIO0_PIN -#endif -#if (SL_SIO_1_LOC == 2) -#define SL_SI91X_SIO1_PIN (SL_SIO_SIO1_PIN + 64) -#else -#define SL_SI91X_SIO1_PIN SL_SIO_SIO1_PIN -#endif -#if ((SL_SIO_2_LOC == 2) || (SL_SIO_2_LOC == 3)) -#define SL_SI91X_SIO2_PIN (SL_SIO_SIO2_PIN + 64) -#else -#define SL_SI91X_SIO2_PIN SL_SIO_SIO2_PIN -#endif -#define SL_SI91X_SIO3_PIN SL_SIO_SIO3_PIN -#define SL_SI91X_SIO4_PIN SL_SIO_SIO4_PIN -#define SL_SI91X_SIO5_PIN SL_SIO_SIO5_PIN -#define SL_SI91X_SIO6_PIN (SL_SIO_SIO6_PIN + 64) -#define SL_SI91X_SIO7_PIN (SL_SIO_SIO7_PIN + 64) - -#if (SL_SIO_SPI_CLK_CH == SL_SIO_CH_0) -#define SL_SI91X_SIO_SPI_CLK_PORT SL_SIO_SIO0_PORT -#define SL_SI91X_SIO_SPI_CLK_PIN SL_SI91X_SIO0_PIN -#define SL_SI91X_SIO_SPI_CLK_MUX SL_SI91X_SIO_0_MUX -#define SL_SI91X_SIO_SPI_CLK_PAD SL_SI91X_SIO_0_PAD - -#elif (SL_SIO_SPI_CLK_CH == SL_SIO_CH_1) -#define SL_SI91X_SIO_SPI_CLK_PORT SL_SIO_SIO1_PORT -#define SL_SI91X_SIO_SPI_CLK_PIN SL_SI91X_SIO1_PIN -#define SL_SI91X_SIO_SPI_CLK_MUX SL_SI91X_SIO_1_MUX -#define SL_SI91X_SIO_SPI_CLK_PAD SL_SI91X_SIO_1_PAD - -#elif (SL_SIO_SPI_CLK_CH == SL_SIO_CH_2) -#define SL_SI91X_SIO_SPI_CLK_PORT SL_SIO_SIO2_PORT -#define SL_SI91X_SIO_SPI_CLK_PIN SL_SI91X_SIO2_PIN -#define SL_SI91X_SIO_SPI_CLK_MUX SL_SI91X_SIO_2_MUX -#define SL_SI91X_SIO_SPI_CLK_PAD SL_SI91X_SIO_2_PAD - -#elif (SL_SIO_SPI_CLK_CH == SL_SIO_CH_3) -#define SL_SI91X_SIO_SPI_CLK_PORT SL_SIO_SIO3_PORT -#define SL_SI91X_SIO_SPI_CLK_PIN SL_SI91X_SIO3_PIN -#define SL_SI91X_SIO_SPI_CLK_MUX SL_SI91X_SIO_3_MUX -#define SL_SI91X_SIO_SPI_CLK_PAD SL_SI91X_SIO_3_PAD - -#elif (SL_SIO_SPI_CLK_CH == SL_SIO_CH_4) -#define SL_SI91X_SIO_SPI_CLK_PORT SL_SIO_SIO4_PORT -#define SL_SI91X_SIO_SPI_CLK_PIN SL_SI91X_SIO4_PIN -#define SL_SI91X_SIO_SPI_CLK_MUX SL_SI91X_SIO_4_MUX -#define SL_SI91X_SIO_SPI_CLK_PAD SL_SI91X_SIO_4_PAD - -#elif (SL_SIO_SPI_CLK_CH == SL_SIO_CH_5) -#define SL_SI91X_SIO_SPI_CLK_PORT SL_SIO_SIO5_PORT -#define SL_SI91X_SIO_SPI_CLK_PIN SL_SI91X_SIO5_PIN -#define SL_SI91X_SIO_SPI_CLK_MUX SL_SI91X_SIO_5_MUX -#define SL_SI91X_SIO_SPI_CLK_PAD SL_SI91X_SIO_5_PAD - -#elif (SL_SIO_SPI_CLK_CH == SL_SIO_CH_6) -#define SL_SI91X_SIO_SPI_CLK_PORT SL_SIO_SIO6_PORT -#define SL_SI91X_SIO_SPI_CLK_PIN SL_SI91X_SIO6_PIN -#define SL_SI91X_SIO_SPI_CLK_MUX SL_SI91X_SIO_6_MUX -#define SL_SI91X_SIO_SPI_CLK_PAD SL_SI91X_SIO_6_PAD - -#elif (SL_SIO_SPI_CLK_CH == SL_SIO_CH_7) -#define SL_SI91X_SIO_SPI_CLK_PORT SL_SIO_SIO7_PORT -#define SL_SI91X_SIO_SPI_CLK_PIN SL_SI91X_SIO7_PIN -#define SL_SI91X_SIO_SPI_CLK_MUX SL_SI91X_SIO_7_MUX -#define SL_SI91X_SIO_SPI_CLK_PAD SL_SI91X_SIO_7_PAD -#endif - -#if (SL_SIO_SPI_CS_CH == SL_SIO_CH_0) -#define SL_SI91X_SIO_SPI_CS_PORT SL_SIO_SIO0_PORT -#define SL_SI91X_SIO_SPI_CS_PIN SL_SI91X_SIO0_PIN -#define SL_SI91X_SIO_SPI_CS_MUX SL_SI91X_SIO_0_MUX -#define SL_SI91X_SIO_SPI_CS_PAD SL_SI91X_SIO_0_PAD - -#elif (SL_SIO_SPI_CS_CH == SL_SIO_CH_1) -#define SL_SI91X_SIO_SPI_CS_PORT SL_SIO_SIO1_PORT -#define SL_SI91X_SIO_SPI_CS_PIN SL_SI91X_SIO1_PIN -#define SL_SI91X_SIO_SPI_CS_MUX SL_SI91X_SIO_1_MUX -#define SL_SI91X_SIO_SPI_CS_PAD SL_SI91X_SIO_1_PAD - -#elif (SL_SIO_SPI_CS_CH == SL_SIO_CH_2) -#define SL_SI91X_SIO_SPI_CS_PORT SL_SIO_SIO2_PORT -#define SL_SI91X_SIO_SPI_CS_PIN SL_SI91X_SIO2_PIN -#define SL_SI91X_SIO_SPI_CS_MUX SL_SI91X_SIO_2_MUX -#define SL_SI91X_SIO_SPI_CS_PAD SL_SI91X_SIO_2_PAD - -#elif (SL_SIO_SPI_CS_CH == SL_SIO_CH_3) -#define SL_SI91X_SIO_SPI_CS_PORT SL_SIO_SIO3_PORT -#define SL_SI91X_SIO_SPI_CS_PIN SL_SI91X_SIO3_PIN -#define SL_SI91X_SIO_SPI_CS_MUX SL_SI91X_SIO_3_MUX -#define SL_SI91X_SIO_SPI_CS_PAD SL_SI91X_SIO_3_PAD - -#elif (SL_SIO_SPI_CS_CH == SL_SIO_CH_4) -#define SL_SI91X_SIO_SPI_CS_PORT SL_SIO_SIO4_PORT -#define SL_SI91X_SIO_SPI_CS_PIN SL_SI91X_SIO4_PIN -#define SL_SI91X_SIO_SPI_CS_MUX SL_SI91X_SIO_4_MUX -#define SL_SI91X_SIO_SPI_CS_PAD SL_SI91X_SIO_4_PAD - -#elif (SL_SIO_SPI_CS_CH == SL_SIO_CH_5) -#define SL_SI91X_SIO_SPI_CS_PORT SL_SIO_SIO5_PORT -#define SL_SI91X_SIO_SPI_CS_PIN SL_SI91X_SIO5_PIN -#define SL_SI91X_SIO_SPI_CS_MUX SL_SI91X_SIO_5_MUX -#define SL_SI91X_SIO_SPI_CS_PAD SL_SI91X_SIO_5_PAD - -#elif (SL_SIO_SPI_CS_CH == SL_SIO_CH_6) -#define SL_SI91X_SIO_SPI_CS_PORT SL_SIO_SIO6_PORT -#define SL_SI91X_SIO_SPI_CS_PIN SL_SI91X_SIO6_PIN -#define SL_SI91X_SIO_SPI_CS_MUX SL_SI91X_SIO_6_MUX -#define SL_SI91X_SIO_SPI_CS_PAD SL_SI91X_SIO_6_PAD - -#elif (SL_SIO_SPI_CS_CH == SL_SIO_CH_7) -#define SL_SI91X_SIO_SPI_CS_PORT SL_SIO_SIO7_PORT -#define SL_SI91X_SIO_SPI_CS_PIN SL_SI91X_SIO7_PIN -#define SL_SI91X_SIO_SPI_CS_MUX SL_SI91X_SIO_7_MUX -#define SL_SI91X_SIO_SPI_CS_PAD SL_SI91X_SIO_7_PAD -#endif - -#if (SL_SIO_SPI_MOSI_CH == SL_SIO_CH_0) -#define SL_SI91X_SIO_SPI_MOSI_PORT SL_SIO_SIO0_PORT -#define SL_SI91X_SIO_SPI_MOSI_PIN SL_SI91X_SIO0_PIN -#define SL_SI91X_SIO_SPI_MOSI_MUX SL_SI91X_SIO_0_MUX -#define SL_SI91X_SIO_SPI_MOSI_PAD SL_SI91X_SIO_0_PAD - -#elif (SL_SIO_SPI_MOSI_CH == SL_SIO_CH_1) -#define SL_SI91X_SIO_SPI_MOSI_PORT SL_SIO_SIO1_PORT -#define SL_SI91X_SIO_SPI_MOSI_PIN SL_SI91X_SIO1_PIN -#define SL_SI91X_SIO_SPI_MOSI_MUX SL_SI91X_SIO_1_MUX -#define SL_SI91X_SIO_SPI_MOSI_PAD SL_SI91X_SIO_1_PAD - -#elif (SL_SIO_SPI_MOSI_CH == SL_SIO_CH_2) -#define SL_SI91X_SIO_SPI_MOSI_PORT SL_SIO_SIO2_PORT -#define SL_SI91X_SIO_SPI_MOSI_PIN SL_SI91X_SIO2_PIN -#define SL_SI91X_SIO_SPI_MOSI_MUX SL_SI91X_SIO_2_MUX -#define SL_SI91X_SIO_SPI_MOSI_PAD SL_SI91X_SIO_2_PAD - -#elif (SL_SIO_SPI_MOSI_CH == SL_SIO_CH_3) -#define SL_SI91X_SIO_SPI_MOSI_PORT SL_SIO_SIO3_PORT -#define SL_SI91X_SIO_SPI_MOSI_PIN SL_SI91X_SIO3_PIN -#define SL_SI91X_SIO_SPI_MOSI_MUX SL_SI91X_SIO_3_MUX -#define SL_SI91X_SIO_SPI_MOSI_PAD SL_SI91X_SIO_3_PAD - -#elif (SL_SIO_SPI_MOSI_CH == SL_SIO_CH_4) -#define SL_SI91X_SIO_SPI_MOSI_PORT SL_SIO_SIO4_PORT -#define SL_SI91X_SIO_SPI_MOSI_PIN SL_SI91X_SIO4_PIN -#define SL_SI91X_SIO_SPI_MOSI_MUX SL_SI91X_SIO_4_MUX -#define SL_SI91X_SIO_SPI_MOSI_PAD SL_SI91X_SIO_4_PAD - -#elif (SL_SIO_SPI_MOSI_CH == SL_SIO_CH_5) -#define SL_SI91X_SIO_SPI_MOSI_PORT SL_SIO_SIO5_PORT -#define SL_SI91X_SIO_SPI_MOSI_PIN SL_SI91X_SIO5_PIN -#define SL_SI91X_SIO_SPI_MOSI_MUX SL_SI91X_SIO_5_MUX -#define SL_SI91X_SIO_SPI_MOSI_PAD SL_SI91X_SIO_5_PAD - -#elif (SL_SIO_SPI_MOSI_CH == SL_SIO_CH_6) -#define SL_SI91X_SIO_SPI_MOSI_PORT SL_SIO_SIO6_PORT -#define SL_SI91X_SIO_SPI_MOSI_PIN SL_SI91X_SIO6_PIN -#define SL_SI91X_SIO_SPI_MOSI_MUX SL_SI91X_SIO_6_MUX -#define SL_SI91X_SIO_SPI_MOSI_PAD SL_SI91X_SIO_6_PAD - -#elif (SL_SIO_SPI_MOSI_CH == SL_SIO_CH_7) -#define SL_SI91X_SIO_SPI_MOSI_PORT SL_SIO_SIO7_PORT -#define SL_SI91X_SIO_SPI_MOSI_PIN SL_SI91X_SIO7_PIN -#define SL_SI91X_SIO_SPI_MOSI_MUX SL_SI91X_SIO_7_MUX -#define SL_SI91X_SIO_SPI_MOSI_PAD SL_SI91X_SIO_7_PAD -#endif - -#if (SL_SIO_SPI_MISO_CH == SL_SIO_CH_0) -#define SL_SI91X_SIO_SPI_MISO_PORT SL_SIO_SIO0_PORT -#define SL_SI91X_SIO_SPI_MISO_PIN SL_SI91X_SIO0_PIN -#define SL_SI91X_SIO_SPI_MISO_MUX SL_SI91X_SIO_0_MUX -#define SL_SI91X_SIO_SPI_MISO_PAD SL_SI91X_SIO_0_PAD - -#elif (SL_SIO_SPI_MISO_CH == SL_SIO_CH_1) -#define SL_SI91X_SIO_SPI_MISO_PORT SL_SIO_SIO1_PORT -#define SL_SI91X_SIO_SPI_MISO_PIN SL_SI91X_SIO1_PIN -#define SL_SI91X_SIO_SPI_MISO_MUX SL_SI91X_SIO_1_MUX -#define SL_SI91X_SIO_SPI_MISO_PAD SL_SI91X_SIO_1_PAD - -#elif (SL_SIO_SPI_MISO_CH == SL_SIO_CH_2) -#define SL_SI91X_SIO_SPI_MISO_PORT SL_SIO_SIO2_PORT -#define SL_SI91X_SIO_SPI_MISO_PIN SL_SI91X_SIO2_PIN -#define SL_SI91X_SIO_SPI_MISO_MUX SL_SI91X_SIO_2_MUX -#define SL_SI91X_SIO_SPI_MISO_PAD SL_SI91X_SIO_2_PAD - -#elif (SL_SIO_SPI_MISO_CH == SL_SIO_CH_3) -#define SL_SI91X_SIO_SPI_MISO_PORT SL_SIO_SIO3_PORT -#define SL_SI91X_SIO_SPI_MISO_PIN SL_SI91X_SIO3_PIN -#define SL_SI91X_SIO_SPI_MISO_MUX SL_SI91X_SIO_3_MUX -#define SL_SI91X_SIO_SPI_MISO_PAD SL_SI91X_SIO_3_PAD - -#elif (SL_SIO_SPI_MISO_CH == SL_SIO_CH_4) -#define SL_SI91X_SIO_SPI_MISO_PORT SL_SIO_SIO4_PORT -#define SL_SI91X_SIO_SPI_MISO_PIN SL_SI91X_SIO4_PIN -#define SL_SI91X_SIO_SPI_MISO_MUX SL_SI91X_SIO_4_MUX -#define SL_SI91X_SIO_SPI_MISO_PAD SL_SI91X_SIO_4_PAD - -#elif (SL_SIO_SPI_MISO_CH == SL_SIO_CH_5) -#define SL_SI91X_SIO_SPI_MISO_PORT SL_SIO_SIO5_PORT -#define SL_SI91X_SIO_SPI_MISO_PIN SL_SI91X_SIO5_PIN -#define SL_SI91X_SIO_SPI_MISO_MUX SL_SI91X_SIO_5_MUX -#define SL_SI91X_SIO_SPI_MISO_PAD SL_SI91X_SIO_5_PAD - -#elif (SL_SIO_SPI_MISO_CH == SL_SIO_CH_6) -#define SL_SI91X_SIO_SPI_MISO_PORT SL_SIO_SIO6_PORT -#define SL_SI91X_SIO_SPI_MISO_PIN SL_SI91X_SIO6_PIN -#define SL_SI91X_SIO_SPI_MISO_MUX SL_SI91X_SIO_6_MUX -#define SL_SI91X_SIO_SPI_MISO_PAD SL_SI91X_SIO_6_PAD - -#elif (SL_SIO_SPI_MISO_CH == SL_SIO_CH_7) -#define SL_SI91X_SIO_SPI_MISO_PORT SL_SIO_SIO7_PORT -#define SL_SI91X_SIO_SPI_MISO_PIN SL_SI91X_SIO7_PIN -#define SL_SI91X_SIO_SPI_MISO_MUX SL_SI91X_SIO_7_MUX -#define SL_SI91X_SIO_SPI_MISO_PAD SL_SI91X_SIO_7_PAD -#endif - -sl_sio_spi_t sl_sio_spi_init = { - .spi_cs_port = SL_SI91X_SIO_SPI_CS_PORT, - .spi_cs_pin = SL_SI91X_SIO_SPI_CS_PIN, - .spi_cs_mux = SL_SI91X_SIO_SPI_CS_MUX, - .spi_cs_pad = SL_SI91X_SIO_SPI_CS_PAD, - .spi_clk_port = SL_SI91X_SIO_SPI_CLK_PORT, - .spi_clk_pin = SL_SI91X_SIO_SPI_CLK_PIN, - .spi_clk_mux = SL_SI91X_SIO_SPI_CLK_MUX, - .spi_clk_pad = SL_SI91X_SIO_SPI_CLK_PAD, - .spi_mosi_port = SL_SI91X_SIO_SPI_MOSI_PORT, - .spi_mosi_pin = SL_SI91X_SIO_SPI_MOSI_PIN, - .spi_mosi_mux = SL_SI91X_SIO_SPI_MOSI_MUX, - .spi_mosi_pad = SL_SI91X_SIO_SPI_MOSI_PAD, - .spi_miso_port = SL_SI91X_SIO_SPI_MISO_PORT, - .spi_miso_pin = SL_SI91X_SIO_SPI_MISO_PIN, - .spi_miso_mux = SL_SI91X_SIO_SPI_MISO_MUX, - .spi_miso_pad = SL_SI91X_SIO_SPI_MISO_PAD, -}; -#endif - -#if defined(SL_SIO_UART_BAUD_RATE) -stc_sio_uart_config_t UartInitstcUc = { - .u32BaudRate = SL_SIO_UART_BAUD_RATE, - .u8Bitlen = SL_SIO_UART_BIT_8, - .u8Parity = SL_SIO_UART_EVEN_PARITY, - .u8SioUartRxChannel = SL_SIO_UART_RX_CH, - .u8SioUartTxChannel = SL_SIO_UART_TX_CH, - .u8StopBits = SL_SIO_UART_STOP_BIT, -}; - -#if (SL_SIO_UART_TX_CH == SL_SIO_CH_0) -#define SL_SI91X_SIO_UART_TX_PORT SL_SIO_SIO0_PORT -#define SL_SI91X_SIO_UART_TX_PIN SL_SI91X_SIO0_PIN -#define SL_SI91X_SIO_UART_TX_MUX SL_SI91X_SIO_0_MUX -#define SL_SI91X_SIO_UART_TX_PAD SL_SI91X_SIO_0_PAD - -#elif (SL_SIO_UART_TX_CH == SL_SIO_CH_1) -#define SL_SI91X_SIO_UART_TX_PORT SL_SIO_SIO1_PORT -#define SL_SI91X_SIO_UART_TX_PIN SL_SI91X_SIO1_PIN -#define SL_SI91X_SIO_UART_TX_MUX SL_SI91X_SIO_1_MUX -#define SL_SI91X_SIO_UART_TX_PAD SL_SI91X_SIO_1_PAD - -#elif (SL_SIO_UART_TX_CH == SL_SIO_CH_2) -#define SL_SI91X_SIO_UART_TX_PORT SL_SIO_SIO2_PORT -#define SL_SI91X_SIO_UART_TX_PIN SL_SI91X_SIO2_PIN -#define SL_SI91X_SIO_UART_TX_MUX SL_SI91X_SIO_2_MUX -#define SL_SI91X_SIO_UART_TX_PAD SL_SI91X_SIO_2_PAD - -#elif (SL_SIO_UART_TX_CH == SL_SIO_CH_3) -#define SL_SI91X_SIO_UART_TX_PORT SL_SIO_SIO3_PORT -#define SL_SI91X_SIO_UART_TX_PIN SL_SI91X_SIO3_PIN -#define SL_SI91X_SIO_UART_TX_MUX SL_SI91X_SIO_3_MUX -#define SL_SI91X_SIO_UART_TX_PAD SL_SI91X_SIO_3_PAD - -#elif (SL_SIO_UART_TX_CH == SL_SIO_CH_4) -#define SL_SI91X_SIO_UART_TX_PORT SL_SIO_SIO4_PORT -#define SL_SI91X_SIO_UART_TX_PIN SL_SI91X_SIO4_PIN -#define SL_SI91X_SIO_UART_TX_MUX SL_SI91X_SIO_4_MUX -#define SL_SI91X_SIO_UART_TX_PAD SL_SI91X_SIO_4_PAD - -#elif (SL_SIO_UART_TX_CH == SL_SIO_CH_5) -#define SL_SI91X_SIO_UART_TX_PORT SL_SIO_SIO5_PORT -#define SL_SI91X_SIO_UART_TX_PIN SL_SI91X_SIO5_PIN -#define SL_SI91X_SIO_UART_TX_MUX SL_SI91X_SIO_5_MUX -#define SL_SI91X_SIO_UART_TX_PAD SL_SI91X_SIO_5_PAD - -#elif (SL_SIO_UART_TX_CH == SL_SIO_CH_6) -#define SL_SI91X_SIO_UART_TX_PORT SL_SIO_SIO6_PORT -#define SL_SI91X_SIO_UART_TX_PIN SL_SI91X_SIO6_PIN -#define SL_SI91X_SIO_UART_TX_MUX SL_SI91X_SIO_6_MUX -#define SL_SI91X_SIO_UART_TX_PAD SL_SI91X_SIO_6_PAD - -#elif (SL_SIO_UART_TX_CH == SL_SIO_CH_7) -#define SL_SI91X_SIO_UART_TX_PORT SL_SIO_SIO7_PORT -#define SL_SI91X_SIO_UART_TX_PIN SL_SI91X_SIO7_PIN -#define SL_SI91X_SIO_UART_TX_MUX SL_SI91X_SIO_7_MUX -#define SL_SI91X_SIO_UART_TX_PAD SL_SI91X_SIO_7_PAD -#endif - -#if (SL_SIO_UART_RX_CH == SL_SIO_CH_0) -#define SL_SI91X_SIO_UART_RX_PORT SL_SIO_SIO0_PORT -#define SL_SI91X_SIO_UART_RX_PIN SL_SI91X_SIO0_PIN -#define SL_SI91X_SIO_UART_RX_MUX SL_SI91X_SIO_0_MUX -#define SL_SI91X_SIO_UART_RX_PAD SL_SI91X_SIO_0_PAD - -#elif (SL_SIO_UART_RX_CH == SL_SIO_CH_1) -#define SL_SI91X_SIO_UART_RX_PORT SL_SIO_SIO1_PORT -#define SL_SI91X_SIO_UART_RX_PIN SL_SI91X_SIO1_PIN -#define SL_SI91X_SIO_UART_RX_MUX SL_SI91X_SIO_1_MUX -#define SL_SI91X_SIO_UART_RX_PAD SL_SI91X_SIO_1_PAD - -#elif (SL_SIO_UART_RX_CH == SL_SIO_CH_2) -#define SL_SI91X_SIO_UART_RX_PORT SL_SIO_SIO2_PORT -#define SL_SI91X_SIO_UART_RX_PIN SL_SI91X_SIO2_PIN -#define SL_SI91X_SIO_UART_RX_MUX SL_SI91X_SIO_2_MUX -#define SL_SI91X_SIO_UART_RX_PAD SL_SI91X_SIO_2_PAD - -#elif (SL_SIO_UART_RX_CH == SL_SIO_CH_3) -#define SL_SI91X_SIO_UART_RX_PORT SL_SIO_SIO3_PORT -#define SL_SI91X_SIO_UART_RX_PIN SL_SI91X_SIO3_PIN -#define SL_SI91X_SIO_UART_RX_MUX SL_SI91X_SIO_3_MUX -#define SL_SI91X_SIO_UART_RX_PAD SL_SI91X_SIO_3_PAD - -#elif (SL_SIO_UART_RX_CH == SL_SIO_CH_4) -#define SL_SI91X_SIO_UART_RX_PORT SL_SIO_SIO4_PORT -#define SL_SI91X_SIO_UART_RX_PIN SL_SI91X_SIO4_PIN -#define SL_SI91X_SIO_UART_RX_MUX SL_SI91X_SIO_4_MUX -#define SL_SI91X_SIO_UART_RX_PAD SL_SI91X_SIO_4_PAD - -#elif (SL_SIO_UART_RX_CH == SL_SIO_CH_5) -#define SL_SI91X_SIO_UART_RX_PORT SL_SIO_SIO5_PORT -#define SL_SI91X_SIO_UART_RX_PIN SL_SI91X_SIO5_PIN -#define SL_SI91X_SIO_UART_RX_MUX SL_SI91X_SIO_5_MUX -#define SL_SI91X_SIO_UART_RX_PAD SL_SI91X_SIO_5_PAD - -#elif (SL_SIO_UART_RX_CH == SL_SIO_CH_6) -#define SL_SI91X_SIO_UART_RX_PORT SL_SIO_SIO6_PORT -#define SL_SI91X_SIO_UART_RX_PIN SL_SI91X_SIO6_PIN -#define SL_SI91X_SIO_UART_RX_MUX SL_SI91X_SIO_6_MUX -#define SL_SI91X_SIO_UART_RX_PAD SL_SI91X_SIO_6_PAD - -#elif (SL_SIO_UART_RX_CH == SL_SIO_CH_7) -#define SL_SI91X_SIO_UART_RX_PORT SL_SIO_SIO7_PORT -#define SL_SI91X_SIO_UART_RX_PIN SL_SI91X_SIO7_PIN -#define SL_SI91X_SIO_UART_RX_MUX SL_SI91X_SIO_7_MUX -#define SL_SI91X_SIO_UART_RX_PAD SL_SI91X_SIO_7_PAD -#endif - -sl_sio_uart_t sl_sio_uart_init = { - .uart_tx_port = SL_SI91X_SIO_UART_TX_PORT, - .uart_tx_pin = SL_SI91X_SIO_UART_TX_PIN, - .uart_tx_mux = SL_SI91X_SIO_UART_TX_MUX, - .uart_tx_pad = SL_SI91X_SIO_UART_TX_PAD, - .uart_rx_port = SL_SI91X_SIO_UART_RX_PORT, - .uart_rx_pin = SL_SI91X_SIO_UART_RX_PIN, - .uart_rx_mux = SL_SI91X_SIO_UART_RX_MUX, - .uart_rx_pad = SL_SI91X_SIO_UART_RX_PAD, -}; -#endif - -#if defined(SL_SIO_I2C_SAMPLE_RATE) -stc_sio_i2c_config_t i2cConfigUc = { - .u32SampleRate = SL_SIO_I2C_SAMPLE_RATE, - .u8SioI2cScl = SL_SIO_I2C_SCL_CHANNEL, - .u8SioI2cSda = SL_SIO_I2C_SDA_CHANNEL, -}; - -#if (SL_SIO_I2C_SCL_CHANNEL == SL_SIO_CH_0) -#define SL_SI91X_SIO_I2C_SCL_PORT SL_SIO_SIO0_PORT -#define SL_SI91X_SIO_I2C_SCL_PIN SL_SI91X_SIO0_PIN -#define SL_SI91X_SIO_I2C_SCL_MUX SL_SI91X_SIO_0_MUX -#define SL_SI91X_SIO_I2C_SCL_PAD SL_SI91X_SIO_0_PAD - -#elif (SL_SIO_I2C_SCL_CHANNEL == SL_SIO_CH_1) -#define SL_SI91X_SIO_I2C_SCL_PORT SL_SIO_SIO1_PORT -#define SL_SI91X_SIO_I2C_SCL_PIN SL_SI91X_SIO1_PIN -#define SL_SI91X_SIO_I2C_SCL_MUX SL_SI91X_SIO_1_MUX -#define SL_SI91X_SIO_I2C_SCL_PAD SL_SI91X_SIO_1_PAD - -#elif (SL_SIO_I2C_SCL_CHANNEL == SL_SIO_CH_2) -#define SL_SI91X_SIO_I2C_SCL_PORT SL_SIO_SIO2_PORT -#define SL_SI91X_SIO_I2C_SCL_PIN SL_SI91X_SIO2_PIN -#define SL_SI91X_SIO_I2C_SCL_MUX SL_SI91X_SIO_2_MUX -#define SL_SI91X_SIO_I2C_SCL_PAD SL_SI91X_SIO_2_PAD - -#elif (SL_SIO_I2C_SCL_CHANNEL == SL_SIO_CH_3) -#define SL_SI91X_SIO_I2C_SCL_PORT SL_SIO_SIO3_PORT -#define SL_SI91X_SIO_I2C_SCL_PIN SL_SI91X_SIO3_PIN -#define SL_SI91X_SIO_I2C_SCL_MUX SL_SI91X_SIO_3_MUX -#define SL_SI91X_SIO_I2C_SCL_PAD SL_SI91X_SIO_3_PAD - -#elif (SL_SIO_I2C_SCL_CHANNEL == SL_SIO_CH_4) -#define SL_SI91X_SIO_I2C_SCL_PORT SL_SIO_SIO4_PORT -#define SL_SI91X_SIO_I2C_SCL_PIN SL_SI91X_SIO4_PIN -#define SL_SI91X_SIO_I2C_SCL_MUX SL_SI91X_SIO_4_MUX -#define SL_SI91X_SIO_I2C_SCL_PAD SL_SI91X_SIO_4_PAD - -#elif (SL_SIO_I2C_SCL_CHANNEL == SL_SIO_CH_5) -#define SL_SI91X_SIO_I2C_SCL_PORT SL_SIO_SIO5_PORT -#define SL_SI91X_SIO_I2C_SCL_PIN SL_SI91X_SIO5_PIN -#define SL_SI91X_SIO_I2C_SCL_MUX SL_SI91X_SIO_5_MUX -#define SL_SI91X_SIO_I2C_SCL_PAD SL_SI91X_SIO_5_PAD - -#elif (SL_SIO_I2C_SCL_CHANNEL == SL_SIO_CH_6) -#define SL_SI91X_SIO_I2C_SCL_PORT SL_SIO_SIO6_PORT -#define SL_SI91X_SIO_I2C_SCL_PIN SL_SI91X_SIO6_PIN -#define SL_SI91X_SIO_I2C_SCL_MUX SL_SI91X_SIO_6_MUX -#define SL_SI91X_SIO_I2C_SCL_PAD SL_SI91X_SIO_6_PAD - -#elif (SL_SIO_I2C_SCL_CHANNEL == SL_SIO_CH_7) -#define SL_SI91X_SIO_I2C_SCL_PORT SL_SIO_SIO7_PORT -#define SL_SI91X_SIO_I2C_SCL_PIN SL_SI91X_SIO7_PIN -#define SL_SI91X_SIO_I2C_SCL_MUX SL_SI91X_SIO_7_MUX -#define SL_SI91X_SIO_I2C_SCL_PAD SL_SI91X_SIO_7_PAD -#endif - -#if (SL_SIO_I2C_SDA_CHANNEL == SL_SIO_CH_0) -#define SL_SI91X_SIO_I2C_SDA_PORT SL_SIO_SIO0_PORT -#define SL_SI91X_SIO_I2C_SDA_PIN SL_SI91X_SIO0_PIN -#define SL_SI91X_SIO_I2C_SDA_MUX SL_SI91X_SIO_0_MUX -#define SL_SI91X_SIO_I2C_SDA_PAD SL_SI91X_SIO_0_PAD - -#elif (SL_SIO_I2C_SDA_CHANNEL == SL_SIO_CH_1) -#define SL_SI91X_SIO_I2C_SDA_PORT SL_SIO_SIO1_PORT -#define SL_SI91X_SIO_I2C_SDA_PIN SL_SI91X_SIO1_PIN -#define SL_SI91X_SIO_I2C_SDA_MUX SL_SI91X_SIO_1_MUX -#define SL_SI91X_SIO_I2C_SDA_PAD SL_SI91X_SIO_1_PAD - -#elif (SL_SIO_I2C_SDA_CHANNEL == SL_SIO_CH_2) -#define SL_SI91X_SIO_I2C_SDA_PORT SL_SIO_SIO2_PORT -#define SL_SI91X_SIO_I2C_SDA_PIN SL_SI91X_SIO2_PIN -#define SL_SI91X_SIO_I2C_SDA_MUX SL_SI91X_SIO_2_MUX -#define SL_SI91X_SIO_I2C_SDA_PAD SL_SI91X_SIO_2_PAD - -#elif (SL_SIO_I2C_SDA_CHANNEL == SL_SIO_CH_3) -#define SL_SI91X_SIO_I2C_SDA_PORT SL_SIO_SIO3_PORT -#define SL_SI91X_SIO_I2C_SDA_PIN SL_SI91X_SIO3_PIN -#define SL_SI91X_SIO_I2C_SDA_MUX SL_SI91X_SIO_3_MUX -#define SL_SI91X_SIO_I2C_SDA_PAD SL_SI91X_SIO_3_PAD - -#elif (SL_SIO_I2C_SDA_CHANNEL == SL_SIO_CH_4) -#define SL_SI91X_SIO_I2C_SDA_PORT SL_SIO_SIO4_PORT -#define SL_SI91X_SIO_I2C_SDA_PIN SL_SI91X_SIO4_PIN -#define SL_SI91X_SIO_I2C_SDA_MUX SL_SI91X_SIO_4_MUX -#define SL_SI91X_SIO_I2C_SDA_PAD SL_SI91X_SIO_4_PAD - -#elif (SL_SIO_I2C_SDA_CHANNEL == SL_SIO_CH_5) -#define SL_SI91X_SIO_I2C_SDA_PORT SL_SIO_SIO5_PORT -#define SL_SI91X_SIO_I2C_SDA_PIN SL_SI91X_SIO5_PIN -#define SL_SI91X_SIO_I2C_SDA_MUX SL_SI91X_SIO_5_MUX -#define SL_SI91X_SIO_I2C_SDA_PAD SL_SI91X_SIO_5_PAD - -#elif (SL_SIO_I2C_SDA_CHANNEL == SL_SIO_CH_6) -#define SL_SI91X_SIO_I2C_SDA_PORT SL_SIO_SIO6_PORT -#define SL_SI91X_SIO_I2C_SDA_PIN SL_SI91X_SIO6_PIN -#define SL_SI91X_SIO_I2C_SDA_MUX SL_SI91X_SIO_6_MUX -#define SL_SI91X_SIO_I2C_SDA_PAD SL_SI91X_SIO_6_PAD - -#elif (SL_SIO_I2C_SDA_CHANNEL == SL_SIO_CH_7) -#define SL_SI91X_SIO_I2C_SDA_PORT SL_SIO_SIO7_PORT -#define SL_SI91X_SIO_I2C_SDA_PIN SL_SI91X_SIO7_PIN -#define SL_SI91X_SIO_I2C_SDA_MUX SL_SI91X_SIO_7_MUX -#define SL_SI91X_SIO_I2C_SDA_PAD SL_SI91X_SIO_7_PAD -#endif - -sl_sio_i2c_t sl_sio_i2c_init = { - .i2c_scl_port = SL_SI91X_SIO_I2C_SCL_PORT, - .i2c_scl_pin = SL_SI91X_SIO_I2C_SCL_PIN, - .i2c_scl_mux = SL_SI91X_SIO_I2C_SCL_MUX, - .i2c_scl_pad = SL_SI91X_SIO_I2C_SCL_PAD, - .i2c_sda_port = SL_SI91X_SIO_I2C_SDA_PORT, - .i2c_sda_pin = SL_SI91X_SIO_I2C_SDA_PIN, - .i2c_sda_mux = SL_SI91X_SIO_I2C_SDA_MUX, - .i2c_sda_pad = SL_SI91X_SIO_I2C_SDA_PAD, -}; -#endif - -#endif //SL_SIO_CONFIG_H \ No newline at end of file diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/config/sl_si91x_uart_config.h b/components/device/silabs/si91x/mcu/drivers/unified_api/config/sl_si91x_uart_config.h index 113c52e5e..f5fcc8b59 100644 --- a/components/device/silabs/si91x/mcu/drivers/unified_api/config/sl_si91x_uart_config.h +++ b/components/device/silabs/si91x/mcu/drivers/unified_api/config/sl_si91x_uart_config.h @@ -74,7 +74,6 @@ extern "C" { // 6 // 7 // 8 -// 9 // Default: USART_DATA_BITS_8 #define SL_UART1_DATA_BITS SL_USART_DATA_BITS_8 diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/config/sl_si91x_ulp_uart_config.h b/components/device/silabs/si91x/mcu/drivers/unified_api/config/sl_si91x_ulp_uart_config.h index e323b3762..c26558d7b 100644 --- a/components/device/silabs/si91x/mcu/drivers/unified_api/config/sl_si91x_ulp_uart_config.h +++ b/components/device/silabs/si91x/mcu/drivers/unified_api/config/sl_si91x_ulp_uart_config.h @@ -74,15 +74,11 @@ extern "C" { // 6 // 7 // 8 -// 9 // Default: USART_DATA_BITS_8 #define SL_ULP_UART_DATA_BITS SL_USART_DATA_BITS_8 // Flow control // None -// CTS -// RTS -// CTS/RTS // Default: USART_FLOW_CONTROL_NONE #define SL_ULP_UART_FLOW_CONTROL_TYPE SL_USART_FLOW_CONTROL_NONE #endif diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/config/sl_si91x_usart_config.h b/components/device/silabs/si91x/mcu/drivers/unified_api/config/sl_si91x_usart_config.h index 5a9b55812..398fd9c3c 100644 --- a/components/device/silabs/si91x/mcu/drivers/unified_api/config/sl_si91x_usart_config.h +++ b/components/device/silabs/si91x/mcu/drivers/unified_api/config/sl_si91x_usart_config.h @@ -84,7 +84,6 @@ extern "C" { // 6 // 7 // 8 -// 9 // Default: USART_DATA_BITS_8 #define SL_USART_DATA_BITS SL_USART_DATA_BITS_8 diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_adc.h b/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_adc.h index 7faa51b98..924e53b72 100644 --- a/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_adc.h +++ b/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_adc.h @@ -48,7 +48,6 @@ extern "C" { typedef adc_ch_config_t sl_adc_channel_config_t; ///< Renamed ADC channel configuration structure typedef adc_config_t sl_adc_config_t; ///< Renamed ADC configuration structure typedef adc_inter_config_t sl_adc_internal_config_t; ///< Renamed ADC internal configuration structure -typedef adc_extr_config_t sl_adc_external_config_t; ///< Renamed ADC external trigger configuration structure /***************************************************************************/ /** * Typedef for user supplied callback function, which is called when ADC sample completes @@ -92,40 +91,6 @@ typedef enum { SL_ADC_CHANNEL_TYPE_LAST, ///< Last member of enum for validation } sl_adc_channel_type_typedef_t; -/// @brief Enumeration for ADC external trigger type -typedef enum { - SL_ULP_TIMER_EXT_TRIGGER = ULP_TIMER_EXT_TRIGGER, ///< ULP timer external trigger type - SL_ULP_GPIO_EXT_TRIGGER = ULP_GPIO_EXT_TRIGGER, ///< ULP gpio external trigger type - SL_M4_CT_EXT_TRIGGER = M4_CT_EXT_TRIGGER, ///< M4 CT external trigger type - SL_ADC_EXT_TRIGGER_TYPE_LAST, ///< Last member of enum for validation -} sl_adc_ext_trigger_type_t; - -/// @brief Enumeration for ADC external trigger number -typedef enum { - SL_ADC_EXT_TRIGGER_1 = DETECTION1, ///< External trigger detection 1 - SL_ADC_EXT_TRIGGER_2 = DETECTION2, ///< External trigger detection 2 - SL_ADC_EXT_TRIGGER_3 = DETECTION3, ///< External trigger detection 3 - SL_ADC_EXT_TRIGGER_4 = DETECTION4, ///< External trigger detection 4 - SL_ADC_EXT_TRIGGER_LAST, ///< Last member of enum for validation -} sl_adc_ext_trigger_num_t; - -/// @brief Enumeration for ADC external trigger edge selection -typedef enum { - SL_ADC_EXT_TRIGGER_POS_EDGE = POSITIVE_EDGE, ///< External trigger positive edge - SL_ADC_EXT_TRIGGER_NEG_EDGE = NEGATIVE_EDGE, ///< External trigger negative edge - SL_ADC_EXT_TRIGGER_POS_NEG_EDGE = POS_NEG_EDGE, ///< External trigger positive and negative edge - SL_ADC_EXT_TRIGGER_EDGE_LAST, ///< Last member of enum for validation -} sl_adc_ext_trigger_edge_t; - -/// @brief Enumeration for ADC external trigger selection -typedef enum { - SL_ADC_EXT_TRIGGER_SEL_1 = EXT_TRIGGER_SEL1, ///< External trigger selection 1 - SL_ADC_EXT_TRIGGER_SEL_2 = EXT_TRIGGER_SEL2, ///< External trigger selection 2 - SL_ADC_EXT_TRIGGER_SEL_3 = EXT_TRIGGER_SEL3, ///< External trigger selection 3 - SL_ADC_EXT_TRIGGER_SEL_4 = EXT_TRIGGER_SEL4, ///< External trigger selection 4 - SL_ADC_EXT_TRIGGER_SEL_LAST, ///< Last member of enum for validation -} sl_adc_ext_trigger_sel_t; - /// @brief Enumeration for ADC channel. typedef enum { SL_ADC_CHANNEL_1, ///< ADC channel 1 @@ -268,27 +233,6 @@ sl_status_t sl_si91x_adc_register_event_callback(sl_adc_callback_t callback_even ******************************************************************************/ void sl_si91x_adc_unregister_event_callback(void); -/***************************************************************************/ /** - * @brief Configure the ADC external trigger. - * @details Triggers can be used in PS4 State to collect samples from a predefined channel. - * ADC can provide a sample for the selected trigger if the trigger matches. - * There are three external triggers enabled by - * - ULPSS Timer Interrupts - * - ULPSS GPIOs - * - M4SS Configuration Timer. - * The trigger match can be verified by reading the \ref sl_si91x_adc_get_external_trigger_status. - * @pre Pre-conditions: - * - \ref sl_si91x_adc_configure_clock - * - \ref sl_si91x_adc_init - * - \ref sl_si91x_adc_set_channel_configuration - * @param[in] adc_external_trigger : ADC external trigger configuration structure variable. - * @return status 0 if successful, else error code as follow - * - SL_STATUS_OK (0x0000) - Success - * - SL_STATUS_NULL_POINTER (0x0022) - The parameter is a null pointer - * - SL_STATUS_INVALID_PARAMETER (0x0021) - Parameters are invalid - ******************************************************************************/ -sl_status_t sl_si91x_adc_configure_external_trigger(sl_adc_external_config_t adc_external_trigger); - /***************************************************************************/ /** * @brief Configure the ADC sampling rate for the ADC channels. * @details It adjusts the channel offset and frequency for each channel to determine the sample rate. @@ -304,42 +248,6 @@ sl_status_t sl_si91x_adc_configure_external_trigger(sl_adc_external_config_t adc sl_status_t sl_si91x_adc_configure_channel_sampling_rate(sl_adc_internal_config_t adc_internal_config, uint8_t channel_num); -/***************************************************************************/ /** - * @brief This API will provide the status of an external trigger. - * @details This will read the status of an external trigger and update in the ext_trigger. - * @pre Pre-conditions: - * - \ref sl_si91x_adc_configure_clock - * - \ref sl_si91x_adc_init - * - \ref sl_si91x_adc_set_channel_configuration - * - \ref sl_si91x_adc_configure_external_trigger - * @param[in] adc_external_trigger : ADC external trigger configuration structure variable. - * @param[out] ext_trigger : The status of external trigger will be store in this. - * @return status 0 if successful, else error code as follow - * - SL_STATUS_OK (0x0000) - Success - * - SL_STATUS_NULL_POINTER (0x0022) - The parameter is a null pointer - * - SL_STATUS_INVALID_PARAMETER (0x0021) - Parameters are invalid - ******************************************************************************/ -sl_status_t sl_si91x_adc_get_external_trigger_status(sl_adc_external_config_t adc_external_trigger, - uint8_t *ext_trigger); - -/***************************************************************************/ /** - * @brief Clear the ADC external trigger. - * @details After reading the trigger match, use the \ref sl_si91x_adc_clear_external_trigger - * API to clear a specific trigger. - * @pre Pre-conditions: - * - \ref sl_si91x_adc_configure_clock - * - \ref sl_si91x_adc_init - * - \ref sl_si91x_adc_set_channel_configuration - * - \ref sl_si91x_adc_configure_external_trigger - * - \ref sl_si91x_adc_register_event_callback - * - \ref sl_si91x_adc_star - * @param[in] adc_external_trigger : ADC external trigger configuration structure variable. - * @return status 0 if successful, else error code as follow - * - SL_STATUS_OK (0x0000) - Success - * - SL_STATUS_INVALID_PARAMETER (0x0021) - Parameters are invalid - ******************************************************************************/ -sl_status_t sl_si91x_adc_clear_external_trigger(sl_adc_external_config_t adc_external_trigger); - /***************************************************************************/ /** * @brief Configure the ADC ping and pong memory location and length. * @details Configure the ping and pong memory locations, diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_config_timer.h b/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_config_timer.h index 4be8892b6..9e81d6254 100644 --- a/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_config_timer.h +++ b/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_config_timer.h @@ -172,7 +172,7 @@ typedef enum { SL_EVENT2_RISING_EDGE_REGISTERED_OR_EVENT, ///< enum for input-2 rising edge registered or-event SL_EVENT3_RISING_EDGE_REGISTERED_AND_EVENT, ///< enum for input-3 rising edge registered and-event SL_EVENT3_RISING_EDGE_REGISTERED_OR_EVENT, ///< enum for input-3 rising edge registered or-event - SL_EVENT_LAST, ///< Last member of enum for validation + SL_CT_EVENT_LAST, ///< Last member of enum for validation } sl_config_timer_event_t; /// @brief Enumeration to represent various timer actions @@ -442,6 +442,17 @@ sl_status_t sl_si91x_config_timer_set_match_count(sl_config_timer_mode_t mode, sl_counter_number_t counter_number, uint32_t match_value); +/***************************************************************************/ /** +* @brief API to calculate and return the match value of the timer for desired time period +* +* @param[in] time_period_in_us : Time period in microseconds +* @param[out] match_value : Gets match value of the timer for desired time period +* @return status 0 if successful, else error-code as follow +* - \ref SL_STATUS_INVALID_COUNT (0x002B) - Count is invalid. +* - \ref SL_STATUS_OK (0x0000) - Success. +*******************************************************************************/ +sl_status_t sl_si91x_config_timer_get_match_value(uint32_t time_period_in_us, uint32_t *match_value); + /***************************************************************************/ /** * @brief This API will get Config-timer current count. * @details This API will get Config-timer current count as per timer mode and counter-number diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_dac.h b/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_dac.h index 2479d391d..58b890ab7 100644 --- a/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_dac.h +++ b/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_dac.h @@ -64,7 +64,7 @@ typedef void (*sl_dac_callback_t)(uint8_t event); // typedef enum { SL_DAC_FIFO_MODE, ///< operation mode as fifo mode SL_DAC_STATIC_MODE, ///< operation mode as static mode - SL_DAC_OUTPUT_REF_VOLTAGE_FOR_ADC, ///< operation mode as dac output reference voltage for ADC + SL_DAC_OUTPUT_REF_VOLTAGE_FOR_ADC, ///< This mode is currently not supported SL_DAC_OPERATION_MODE_LAST, ///< Last member of enum for validation } sl_dac_operation_mode_t; @@ -75,6 +75,7 @@ typedef enum { } sl_dac_callback_event_t; /// @brief Enumeration for ADC channel this enum only used on Reference voltage for ADC mode of DAC. +/// note: These enums are not used as SL_DAC_OUTPUT_REF_VOLTAGE_FOR_ADC mode is not supported currently. typedef enum { SL_DAC_ADC_CHANNEL_0, ///< ADC channel 0 SL_DAC_ADC_CHANNEL_1, ///< ADC channel 1 diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_driver_gpio.h b/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_driver_gpio.h index 43a5b90f8..baf119cb1 100644 --- a/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_driver_gpio.h +++ b/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_driver_gpio.h @@ -156,9 +156,11 @@ sl_status_t sl_si91x_gpio_driver_enable_pad_selection(uint8_t gpio_padnum); /***************************************************************************/ /** * @brief Enable the host pad selection bit in the PAD selection register. + * GPIO pin number(25 to 30) are valid for HOST PAD selection, referring + * to SL_GPIO_PORT_B, pins 9 to 14. * @pre Pre-condition: * - \ref sl_si91x_gpio_driver_enable_clock() - * @param[in] gpio_num - GPIO pin number to be used + * @param[in] gpio_num - GPIO pin number(25-30) to be used * @return returns status 0 if successful, * else error code as follow. * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_gspi.h b/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_gspi.h index 0bf7520ce..c1b513c15 100644 --- a/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_gspi.h +++ b/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_gspi.h @@ -197,10 +197,11 @@ sl_status_t sl_si91x_gspi_deinit(sl_gspi_handle_t gspi_handle); * - The configurations are listed below: * - swap_read (enable/disable) * - swap_write (enable/disable) - * - bit_width (8_bit/16_bit) + * - bit_width (1-16 bits) * - clock_mode (mode0/mode3) * - slave_select_mode (hw_output/sw) * - bitrate + * @note Swap Read and Swap Write can be used only if the bit_width is configured as 16. * @pre Pre-conditions: * - \ref sl_si91x_gspi_configure_clock * - \ref sl_si91x_gspi_init diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_ro_temperature_sensor.h b/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_ro_temperature_sensor.h deleted file mode 100644 index f9f42e4b2..000000000 --- a/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_ro_temperature_sensor.h +++ /dev/null @@ -1,284 +0,0 @@ -/***************************************************************************/ /** - * @file sl_si91x_ro_temperature_sensor.h - * @brief RO temperature sensor API implementation - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_SI91X_RO_TEMPERATURE_SENSOR_H_ -#define SL_SI91X_RO_TEMPERATURE_SENSOR_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -//// Includes -#include "sl_status.h" -#include "rsi_temp_sensor.h" - -/***************************************************************************/ /** - * @addtogroup ROTEMPSENSOR RO Temperature Sensor - * @ingroup SI91X_PERIPHERAL_APIS - * @{ - * - ******************************************************************************/ -/******************************************************************************* - ****************************** Defines / Macros *************************** - ******************************************************************************/ - -/******************************************************************************* - ******************************** Local Variables ************************** - ******************************************************************************/ - -/******************************************************************************* - *************************** Global VARIABLES ******************************** - ******************************************************************************/ - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ -///@brief RO temperature sensor reference clock -typedef enum { - SL_RO_REF_CLK, ///< Enable RO kHz clock from analog as reference clock - SL_RO_FSM_CLK, ///< Enable MCU FSM clock as reference clock - SL_RO_CLK_LAST, ///< Last member of enum for validation -} sl_ro_reference_clock_t; - -///@brief Enable/Disable RO temperature sensor -typedef enum { - SL_RO_TEMPERATURE_DISABLE, ///< Temperature sensing disable - SL_RO_TEMPERATURE_ENABLE, ///< Temperature sensing enable - SL_RO_TEMPERATURE_LAST, ///< Last member of enum for validation -} sl_ro_temperature_state_t; - -///@brief Enable/Disable BJT based temperature update -typedef enum { - SL_RO_TEMP_BJT_UPDATE_ENABLE, ///< Enable BJT based temperature through RO calculation - SL_RO_TEMP_SPI_UPDATE_ENABLE, ///< Disable BJT based temperature through RO calculation and Enable update through SPI. - SL_RO_TEMP_BJT_UPDATE_LAST, ///< Last member of enum for validation -} sl_ro_temperature_update_t; - -///@brief Enable/Disable RO periodic temperature checking -typedef enum { - SL_RO_TEMPERATURE_PERIODIC_DISABLE, ///< Periodic temperature checking disable - SL_RO_TEMPERATURE_PERIODIC_ENABLE, ///< Periodic temperature checking enable - SL_RO_TEMPERATURE_PERIODIC_LAST, ///< Last member of enum for validation -} sl_ro_temperature_periodic_check_t; - -///@brief RO temperature periodic check time -typedef enum { - SL_RO_TEMPERATURE_TRIGGER_1SEC, ///< RO temperature update for every 1second - SL_RO_TEMPERATURE_TRIGGER_2SEC, ///< RO temperature update for every 2seconds - SL_RO_TEMPERATURE_TRIGGER_4SEC, ///< RO temperature update for every 4seconds - SL_RO_TEMPERATURE_TRIGGER_5SEC, ///< RO temperature update for every 5seconds - SL_RO_TEMPERATURE_TRIGGER_LAST, ///< Last member of enum for validation -} sl_ro_temperature_trigger_time_t; - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -/***************************************************************************/ /** - * @brief Set reference clock count for RO temperature sensor - * @details This API is used to set the count of reference clock on which ptat clock counts. - * - * @param[in] count Count of reference clock on which ptat clock counts (0- 1024) - * - * @return Status 0 if successful, else error code: - * - SL_STATUS_OK on success - * - SL_STATUS_INVALID_PARAMETER (0x0021) , The parameter is invalid argument - * - SL_STATUS_NULL_POINTER (0x0022) , The parameter is null pointer - ******************************************************************************/ -sl_status_t sl_si91x_ro_temperature_set_count(uint32_t count); - -/***************************************************************************/ /** - * @brief Select reference clock for RO temperature sensor - * @details This API is used to select the reference clock to the temperature sensor - * @param[in] ref_clk Reference clock selection: - * - 0 - reference RO clock from analog - * - 1 - MCU FSM clock - * @return Status 0 if successful, else error code: - * - SL_STATUS_OK on success \n - * - SL_STATUS_INVALID_PARAMETER (0x0021) , The parameter is invalid argument - * - SL_STATUS_NULL_POINTER (0x0022) , The parameter is null pointer - ******************************************************************************/ -sl_status_t sl_si91x_ro_temperature_select_reference_clock(sl_ro_reference_clock_t ref_clk); - -/***************************************************************************/ /** - * @brief Enable/disable RO temperature sensor - * @details This API is used to enable / disable the temperature sensor - * @param[in] state Enable / disable the temperature sensor: - * - 0 - Disable - * - 1 - Enable - * @return Status 0 if successful, else error code: - * - SL_STATUS_OK on success - * - SL_STATUS_INVALID_PARAMETER (0x0021) , The parameter is invalid argument - * - SL_STATUS_NULL_POINTER (0x0022) , The parameter is null pointer - ******************************************************************************/ -sl_status_t sl_si91x_ro_temperature_enable(sl_ro_temperature_state_t state); - -/***************************************************************************/ /** - * @brief Set nominal value for RO temperature sensor - * @details This API is used to set the nominal value of the temperature sensor - * - * @param[in] value Calibrated temperature value(0-128). - * - * @return Status 0 if successful, else error code: - * - SL_STATUS_OK on success - * - SL_STATUS_INVALID_PARAMETER (0x0021) , The parameter is invalid argument - * - SL_STATUS_NULL_POINTER (0x0022) , The parameter is null pointer - ******************************************************************************/ -sl_status_t sl_si91x_ro_temperature_nominal(uint32_t value); - -/***************************************************************************/ /** - * @brief Read value from RO temperature sensor - * @details This API is used to read the temperature value - * @param[out] temperature Temperature value reading - * @return Status 0 if successful, else error code: - * - SL_STATUS_OK on success - * - SL_STATUS_NULL_POINTER (0x0022) , The parameter is null pointer - ******************************************************************************/ -sl_status_t sl_si91x_ro_temperature_read(int32_t *temperature); - -/***************************************************************************/ /** - * @brief Calculate temperature from RO temperature sensor reading - * @details This API is used to updating temperature through RO based calculation - * @param[in] enable Enable RO based BJT temperature update - * @return Status 0 if successful, else error code: - * - SL_STATUS_OK on success - * - SL_STATUS_INVALID_PARAMETER (0x0021) , The parameter is invalid argument - * - SL_STATUS_NULL_POINTER (0x0022) , The parameter is null pointer - ******************************************************************************/ -sl_status_t sl_si91x_ro_temperature_based_update(sl_ro_temperature_update_t enable); - -/***************************************************************************/ /** - * @brief Update temperature for RO temperature sensor - * @details This API is used to updating temperature - * - * @param[in] temperature Known temperature (0- 255) - * - * @return SL_STATUS_OK on success - ******************************************************************************/ -sl_status_t sl_si91x_ro_temperature_load(uint8_t temperature); - -/***************************************************************************/ /** - * @brief Get reference clock count for RO temperature sensor - * @details This API is used to read the reference clock count - * @param[out] ref_count Count of f1 clock cycles - * @return Status 0 if successful, else error code: - * - SL_STATUS_OK on success - * - SL_STATUS_NULL_POINTER (0x0022) , The parameter is null pointer - ******************************************************************************/ -sl_status_t sl_si91x_ro_temperature_get_reference_clk_count(uint32_t *ref_count); - -/***************************************************************************/ /** - * @brief Get ptat clock count for RO temperature sensor - * @details This API is used to read the ptat clock count - * @param[out] ptat_count Count of f2 clock cycles - * @return Status 0 if successful, else error code: - * - SL_STATUS_OK on success - * - SL_STATUS_NULL_POINTER (0x0022) , The parameter is null pointer - ******************************************************************************/ -sl_status_t sl_si91x_ro_temperature_get_ptat_clk_count(uint32_t *ptat_count); - -/***************************************************************************/ /** - * @brief Update temperature periodically for RO temperature sensor - * @details This API is used to update the temperature periodically after some time - * @param[in] periodic_check Enable periodic checking of temperature - * @param[in] trigger_time Periodic check time in sec: - * - 0 - for every 1 sec - * - 1 - for every 2 secs - * - 2 - for every 4 secs - * - 3 - for every 5 secs - * @return Status 0 if successful, else error code: - * - SL_STATUS_OK on success - * - SL_STATUS_INVALID_PARAMETER (0x0021) , The parameter is invalid argument - * - SL_STATUS_NULL_POINTER (0x0022) , The parameter is null pointer - ******************************************************************************/ -sl_status_t sl_si91x_ro_temperature_periodic_update(sl_ro_temperature_periodic_check_t periodic_check, - sl_ro_temperature_trigger_time_t trigger_time); - -// ******** THE REST OF THE FILE IS DOCUMENTATION ONLY !*********************** -/// @addtogroup ROTEMPSENSOR RO Temperature Sensor -/// @{ -/// -/// @details -/// -/// -/// @n @section ROTEMPSENSOR_Intro Introduction -/// -/// -/// A Ring Oscillator Temperature Sensor (RO Temperature Sensor) is a type of temperature sensor that utilizes -/// a ring oscillator circuit to measure temperature variations. A ring oscillator is a circuit configuration that -/// consists of an odd number of inverters connected in a loop. The frequency of oscillation of the ring oscillator -/// is influenced by various factors, including temperature. -/// -/// Here's how a Ring Oscillator Temperature Sensor typically works: -/// -/// @li **Ring Oscillator Circuit**: The ring oscillator is designed with an odd number of inverters (amplifiers) connected in a loop. -/// The delay through each inverter contributes to the overall oscillation frequency of the ring. -/// -/// @li **Temperature Sensitivity**: The delay through each inverter is sensitive to temperature variations. As the temperature changes, -/// the characteristics of the transistors in the inverters are affected, causing a change in the overall delay and, consequently, the oscillation frequency. -/// -/// @li **Frequency Measurement**: The frequency of the ring oscillator is measured or monitored. This frequency is directly related to the -/// temperature of the environment or the temperature of the integrated circuit itself. -/// -/// @li **Temperature Calibration**: The sensor is often calibrated to provide an accurate temperature reading based on the measured oscillation frequency. -/// Calibration may involve correlating the frequency with a temperature reference to create a temperature-sensitive output. -/// -/// @n @section ROTEMPSENSOR_Config Configuration -/// -/// By altering the mode in the structure below, one can update the trigger time @li @ref sl_ro_temperature_trigger_time_t. -/// -/// @n @section ROTEMPSENSOR_Use Usage -/// -/// RO temperature sensor is set with nominal temperature and the temperature sensor is enabled -/// after the Temperature is updated through RO based calculation. RO temperature sensor will be -/// triggered and updated for every 2 seconds. -/// And the apis used in the RO Temperature Sensor are: -/// -/// 1. @ref sl_si91x_ro_temperature_select_reference_clock -/// -/// 2. @ref sl_si91x_ro_temperature_nominal -/// -/// 3. @ref sl_si91x_ro_temperature_based_update -/// -/// 4. @ref sl_si91x_ro_temperature_set_count -/// -/// 5. @ref sl_si91x_ro_temperature_enable -/// -/// 6. @ref sl_si91x_ro_temperature_periodic_update -/// -/// 7. @ref sl_si91x_ro_temperature_read -/// -/** @} (end addtogroup SL_SI91X_RO_TEMPERATURE_SENSOR) */ - -#ifdef __cplusplus -} -#endif - -#endif /* SL_SI91X_RO_TEMPERATURE_SENSOR_H_ */ diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_sio.h b/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_sio.h deleted file mode 100644 index b4097a78d..000000000 --- a/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_sio.h +++ /dev/null @@ -1,947 +0,0 @@ -/***************************************************************************/ /** - * @file sl_si91x_sio.h - * @brief SIO API implementation - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_SI91X_SIO_H -#define SL_SI91X_SIO_H - -#ifdef __cplusplus -extern "C" { -#endif - -//// Includes -#include "rsi_sio.h" -#include "sl_status.h" - -/***************************************************************************/ /** - * @addtogroup SIO Serial Input-Output - * @ingroup SI91X_PERIPHERAL_APIS - * @{ - * - *******************************************************************************/ - -/******************************************************************************* - *************************** DEFINES / MACROS ******************************** - ******************************************************************************/ -#define SL_SIO_CH_0 0 ///< SIO-SPI channel 0 -#define SL_SIO_CH_1 1 ///< SIO-SPI channel 1 -#define SL_SIO_CH_2 2 ///< SIO-SPI channel 2 -#define SL_SIO_CH_3 3 ///< SIO-SPI channel 3 -#define SL_SIO_CH_4 4 ///< SIO-SPI channel 4 -#define SL_SIO_CH_5 5 ///< SIO-SPI channel 5 -#define SL_SIO_CH_6 6 ///< SIO-SPI channel 6 -#define SL_SIO_CH_7 7 ///< SIO-SPI channel 7 - -typedef stc_sio_spi_cfg_t sl_sio_spi_config_t; ///< SIO-SPI configuration structure -typedef stc_sio_spi_xfer_t sl_sio_spi_xfer_config_t; ///< SIO-SPI Transfer structure -typedef stc_sio_i2s_config_t sl_sio_i2s_config_t; ///< SIO-I2S configuration structure -typedef stc_sio_i2s_xfer_t sl_sio_i2s_xfer_config_t; ///< SIO-I2S Transfer structure -typedef stc_sio_uart_config_t sl_sio_uart_config_t; ///< SIO-UART configuration structure -typedef sio_i2s_func_ptr_t sl_sio_i2s_callback_t; ///< SIO-I2S callback function pointer -typedef sio_Spi_func_ptr_t sl_sio_spi_callback_t; ///< SIO-SPI callback function pointer -typedef sio_Uart_func_ptr_t sl_sio_uart_callback_t; ///< SIO_UART callback function pointer -typedef stc_sio_i2c_config_t sl_sio_i2c_config_t; ///< SIO-I2C configuration structure - -/******************************************************************************* - ******************************** Local Variables ************************** - ******************************************************************************/ - -/******************************************************************************* - *************************** Global VARIABLES ******************************** - ******************************************************************************/ - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ -///@brief SIO-SPI Events -typedef enum { - SL_SIO_SPI_TX_DONE, ///< SIO-SPI Transfer done event - SL_SIO_SPI_RX_DONE, ///< SIO-SPI Receive done event -} sl_sio_spi_event_t; - -///@brief SIO-UART Events -typedef enum { - SL_SIO_UART_TX_DONE, ///< SIO-UART transfer done event - SL_SIO_UART_RX_DONE, ///< SIO-UART receive done event - SL_SIO_UART_PARITY_ERR, ///< SIO-UART parity error - SL_SIO_UART_FRAMING_ERR, ///< SIO-UART framing error - SL_SIO_UART_RECEIVE_CHAR, ///< SIO-UART receive character -} sl_sio_uart_event_t; - -///@brief SIO-SPI modes configurations -typedef enum { - SL_SIO_SPI_MODE_0 = 0, ///< SIO-SPI mode 0 - SL_SIO_SPI_MODE_3 = 3, ///< SIO-SPI mode 3 -} sl_sio_spi_mode_t; - -///@brief SIO-SPI bit width configurations -typedef enum { - SL_SIO_SPI_BIT_8 = 8, ///< SIO-SPI bit width 8 - SL_SIO_SPI_BIT_16 = 16, ///< SIO-SPI bit width 16 -} sl_sio_spi_bit_width_t; - -///@brief SIO-SPI MSB/LSB first configurations -typedef enum { - SL_SIO_SPI_LSB_FIRST = 0, ///< SIO-SPI LSB first - SL_SIO_SPI_MSB_FIRST = 1, ///< SIO-SPI MSB first -} sl_sio_spi_msb_lsb_t; - -///@brief SIO-UART bit length configurations -typedef enum { - SL_SIO_UART_BIT_8 = 8, ///< SIO-SPI bit length 8 - SL_SIO_UART_BIT_16 = 16, ///< SIO-SPI bit length 16 -} sl_sio_spi_bit_length_t; - -///@brief SIO-UART parity configurations -typedef enum { - SL_SIO_UART_EVEN_PARITY = 0, ///< SIO-SPI even parity - SL_SIO_UART_ODD_PARITY = 1, ///< SIO-SPI odd parity -} sl_sio_spi_parity_t; - -///@brief SIO-UART stop bit configurations -typedef enum { - SL_SIO_UART_STOP_BIT_1 = 1, ///< SIO-UART stop bit 1 - SL_SIO_UART_STOP_BIT_2 = 2, ///< SIO-UART stop bit 2 -} sl_sio_spi_stop_bit_t; - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ -/// @brief Structure to hold the different versions of the peripheral API -typedef struct { - uint8_t release; ///< Release version number - uint8_t major; ///< Major version number - uint8_t minor; ///< Minor version number -} sl_sio_version_t; - -///@brief Structure to hold the port and pin of SIO SPI -typedef struct { - uint8_t spi_cs_port; ///< SIO SPI CS port - uint8_t spi_cs_pin; ///< SIO SPI CS pin - uint8_t spi_cs_mux; ///< SIO SPI CS mux - uint8_t spi_cs_pad; ///< SIO SPI CS pad - uint8_t spi_clk_port; ///< SIO SPI CLK port - uint8_t spi_clk_pin; ///< SIO SPI CLK pin - uint8_t spi_clk_mux; ///< SIO SPI CLK mux - uint8_t spi_clk_pad; ///< SIO SPI CLK pad - uint8_t spi_mosi_port; ///< SIO SPI MOSI port - uint8_t spi_mosi_pin; ///< SIO SPI MOSI pin - uint8_t spi_mosi_mux; ///< SIO SPI MOSI mux - uint8_t spi_mosi_pad; ///< SIO SPI MOSI pad - uint8_t spi_miso_port; ///< SIO SPI MISO port - uint8_t spi_miso_pin; ///< SIO SPI MISO pin - uint8_t spi_miso_mux; ///< SIO SPI MISO mux - uint8_t spi_miso_pad; ///< SIO SPI MISO pad -} sl_sio_spi_t; - -///@brief Structure to hold the port and pin of SIO UART -typedef struct { - uint8_t uart_tx_port; ///< SIO UART TX port - uint8_t uart_tx_pin; ///< SIO UART TX pin - uint8_t uart_tx_mux; ///< SIO UART TX mux - uint8_t uart_tx_pad; ///< SIO UART TX pad - uint8_t uart_rx_port; ///< SIO UART RX port - uint8_t uart_rx_pin; ///< SIO UART RX pin - uint8_t uart_rx_mux; ///< SIO UART RX mux - uint8_t uart_rx_pad; ///< SIO UART RX pad -} sl_sio_uart_t; - -///@brief Structure to hold the port and pin of SIO I2C -typedef struct { - uint8_t i2c_sda_port; ///< SIO I2C SDA port - uint8_t i2c_sda_pin; ///< SIO I2C SDA pin - uint8_t i2c_sda_mux; ///< SIO I2C SDA mux - uint8_t i2c_sda_pad; ///< SIO I2C SDA pad - uint8_t i2c_scl_port; ///< SIO I2C SCL port - uint8_t i2c_scl_pin; ///< SIO I2C SCL pin - uint8_t i2c_scl_mux; ///< SIO I2C SCL mux - uint8_t i2c_scl_pad; ///< SIO I2C SCL pad -} sl_sio_i2c_t; - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -/***************************************************************************/ /** - * @brief Initialize the SIO module. It initializes the SIO - * GPIO's and enables the SIO module clock. - * - * @param none - * - * @return returns status 0 if successful, else error code as follows: - * - \ref SL_STATUS_FAIL (0x0001) - Fail, SIO initialization failed - * - \ref SL_STATUS_OK (0x0000) - Success, SIO initialization successful -******************************************************************************/ -sl_status_t sl_si91x_sio_init(void); - -/***************************************************************************/ /** - * @brief Initialize the SIO-SPI module. It configures - * the SPI mode, bit length, bit order, SIO frequency, and the SIO channels for - * the SPI transfer lines. - * @pre Pre-condition: - * - \ref sl_si91x_sio_init() - * @param[in] configuration - Pointer to SIO-SPI configuration structure - * \ref sl_sio_spi_config_t - * @return returns status 0 if successful, - * else error code as follows: - * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument - * - \ref SL_STATUS_NULL_POINTER (0x0022) - The parameter is a null pointer - * - \ref SL_STATUS_OK (0x0000) - Success, SPI initialization done properly -******************************************************************************/ -sl_status_t sl_si91x_sio_spi_init(sl_sio_spi_config_t *configuration); - -/***************************************************************************/ /** - * @brief This API is used to De-initialize SIO module - * @param none - * @return none - ******************************************************************************/ -void sl_si91x_sio_deinit(void); - -/***************************************************************************/ /** - * @brief Initialize SIO SPI pins and clock - * @param[in] sio_spi_init : Pointer to the structure of type \ref sl_sio_spi_t - * @return returns status 0 if successful, - * else error code as follows: - * - \ref SL_STATUS_OK - Success - * - \ref SL_STATUS_NULL_POINTER - The parameter is a null pointer -******************************************************************************/ -sl_status_t sl_si91x_sio_spi_pin_initialization(sl_sio_spi_t *sio_spi_init); - -/***************************************************************************/ /** - * @brief Initialize SIO UART pins and clock. This holds the UART Tx, Rx pins - * configuration. - * - * @param[in] sio_uart_init : Pointer to the structure of type \ref sl_sio_uart_t - * - * @return returns status 0 if successful, - * else error code as follows: - * - \ref SL_STATUS_OK - Success - * - \ref SL_STATUS_NULL_POINTER - The parameter is a null pointer -******************************************************************************/ -sl_status_t sl_si91x_sio_uart_pin_initialization(sl_sio_uart_t *sio_uart_init); - -/***************************************************************************/ /** - * @brief Initialize SIO I2C pins and clock. This holds the I2C SDA, SCL pins - * configuration. - * - * @param[in] sio_i2c_init : Pointer to the structure of type \ref sl_sio_i2c_t - * - * @return returns status 0 if successful, - * else error code as follows: - * - \ref SL_STATUS_OK - Success - * - \ref SL_STATUS_NULL_POINTER - The parameter is a null pointer -******************************************************************************/ -sl_status_t sl_si91x_sio_i2c_pin_initialization(sl_sio_i2c_t *sio_i2c_init); - -/***************************************************************************/ /** - * @brief Assert the SIO SPI chip select. - * @details This tells peripheral that it should wake up - * and receive / send data and is also used when multiple peripherals are present to - * select the one you'd like to communicate with. - * @pre Pre-conditions: - * - \ref sl_si91x_sio_init() - * - \ref sl_si91x_sio_spi_init() - * @param[in] chip_select_num - Chip select number (0 to 7) - * @return returns status 0 if successful, - * else error code as follows: - * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument - * - \ref SL_STATUS_NULL_POINTER (0x0022) - The parameter is a null pointer - * - \ref SL_STATUS_OK (0x0000) - Success -******************************************************************************/ -sl_status_t sl_si91x_sio_spi_cs_assert(uint8_t chip_select_num); - -/***************************************************************************/ /** - * @brief De-assert the SIO SPI chip select. This is used to disable after the last byte - * is transmitted / received. - * @pre Pre-conditions: - * - \ref sl_si91x_sio_init() - * - \ref sl_si91x_sio_spi_init() - * - \ref sl_si91x_sio_spi_cs_assert() - * - \ref sl_si91x_sio_spi_transfer() - * @param[in] chip_select_num - Chip select number (0 to 7) - * @return returns status 0 if successful, - * else error code as follows: - * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument - * - \ref SL_STATUS_NULL_POINTER (0x0022) - The parameter is a null pointer - * - \ref SL_STATUS_OK (0x0000) - Success -******************************************************************************/ -sl_status_t sl_si91x_sio_spi_cs_deassert(uint8_t chip_select_num); - -/***************************************************************************/ /** - * @brief Register the user callback function. It registers the callback, i.e., - * stores the callback function address and pass to the variable that is called - * in Interrupt Handler. If another callback is registered without unregistering - * previous callback then, it returns an error code, so it is mandatory to unregister - * the callback before registering another callback. It will returns error if any - * callback is already registered. - * @pre Pre-conditions: - * - \ref sl_si91x_sio_init() - * - \ref sl_si91x_sio_spi_init() - * @param[in] callback_event - Pointer to the function \ref sl_sio_spi_callback_t - * which needs to be called at the time of interrupt. - * @return returns status 0 if successful, - * else error code as follows: - * - \ref SL_STATUS_OK (0x0000) - Success - * - \ref SL_STATUS_NULL_POINTER (0x0022) - The parameter is a null pointer - * - \ref SL_STATUS_BUSY (0x0004) - Driver is busy -******************************************************************************/ -sl_status_t sl_si91x_sio_spi_register_event_callback(sl_sio_spi_callback_t callback_event); - -/***************************************************************************/ /** - * @brief Un-register the user callback function, i.e., clear the callback - * function address and disables IRQ handler. - * @pre Pre-conditions: - * - \ref sl_si91x_sio_init() - * - \ref sl_si91x_sio_spi_init() - * - \ref sl_si91x_sio_spi_register_event_callback() - * @param none - * @return none -******************************************************************************/ -void sl_si91x_sio_spi_unregister_event_callback(void); - -/***************************************************************************/ /** - * @brief Transfer the SIO SPI data. It is used to make the SIO-SPI - * transfer in non-blocking mode. - * @pre Pre-conditions: - * - \ref sl_si91x_sio_init() - * - \ref sl_si91x_sio_spi_init() - * - \ref sl_si91x_sio_spi_cs_assert() - * - * @param[in] xfer_config - Pointer to SIO-SPI transfer configuration structure - * \ref sl_sio_spi_xfer_config_t - * - * @return returns status 0 if successful, else error code as follows: - * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument - * - \ref SL_STATUS_NULL_POINTER (0x0022) - The parameter is a null pointer - * - \ref SL_STATUS_OK (0x0000) - Success -******************************************************************************/ -sl_status_t sl_si91x_sio_spi_transfer(sl_sio_spi_xfer_config_t *xfer_config); - -/***************************************************************************/ /** - * @brief Get the SIO version. It is used to get the release, SQA and DEV version - * of the SIO module. - * @param none - * @return returns structure of type \ref sl_sio_version_t -******************************************************************************/ -sl_sio_version_t sl_si91x_sio_get_version(void); - -/***************************************************************************/ /** - * @brief Initialize SIO-UART, i.e., set baud rate, parity, - * channel selection, stop bits, and data length. - * @pre Pre-conditions: - * - \ref sl_si91x_sio_init() - * @param[in] configuration - Pointer to SIO-UART configuration structure - * \ref sl_sio_uart_config_t - * @return returns status 0 if successful, - * else error code as follows: - * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument - * - \ref SL_STATUS_NULL_POINTER (0x0022) - The parameter is a null pointer - * - \ref SL_STATUS_OK (0x0000) - Success, UART initialization done properly -******************************************************************************/ -sl_status_t sl_si91x_sio_uart_init(sl_sio_uart_config_t *configuration); - -/***************************************************************************/ /** - * @brief Send the data over SIO-UART in non-blocking mode. Transmit bytes from the - * buffer using an interrupt service. Will return immediately, but cannot be called - * again until the previous call has finished. - * @pre Pre-conditions: - * - \ref sl_si91x_sio_init() - * - \ref sl_si91x_sio_uart_init() - * @param[in] buffer - data pointer to send - * @param[in] length - data length - * @return returns status 0 if successful, - * else error code as follows: - * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument - * - \ref SL_STATUS_NULL_POINTER (0x0022) - The parameter is a null pointer - * - \ref SL_STATUS_OK (0x0000) - Success -******************************************************************************/ -sl_status_t sl_si91x_sio_uart_send(const void *buffer, uint16_t length); - -/***************************************************************************/ /** - * @brief Send the data over SIO-UART in blocking mode. Transmit bytes from the - * buffer using a blocking send byte function. Does not return until all bytes are sent. - * @pre Pre-conditions: - * - \ref sl_si91x_sio_init() - * - \ref sl_si91x_sio_uart_init() - * - \ref sl_si91x_sio_uart_send() (or) \ref sl_si91x_sio_uart_send_blocking() - * @param[in] buffer - data pointer to send - * @param[in] length - number of bytes to send - * @return returns status 0 if successful, - * else error code as follows: - * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument - * - \ref SL_STATUS_NULL_POINTER (0x0022) - The parameter is a null pointer - * - \ref SL_STATUS_OK (0x0000) - Success -******************************************************************************/ -sl_status_t sl_si91x_sio_uart_send_blocking(const void *buffer, uint16_t length); - -/***************************************************************************/ /** - * @brief Read data from SIO-UART in non-blocking mode. - * @pre Pre-conditions: - * - \ref sl_si91x_sio_init() - * - \ref sl_si91x_sio_uart_init() - * - \ref sl_si91x_sio_uart_send() (or) \ref sl_si91x_sio_uart_send_blocking() - * @param[out] data_buffer - data buffer pointer to read - * @param[in] num_bytes - number of bytes read - * @return returns status 0 if successful, - * else error code as follows: - * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument - * - \ref SL_STATUS_NULL_POINTER (0x0022) - The parameter is a null pointer - * - \ref SL_STATUS_OK (0x0000) - Success -******************************************************************************/ -sl_status_t sl_si91x_sio_uart_read(void *data_buffer, uint16_t num_bytes); - -/***************************************************************************/ /** - * @brief Read data from UART in blocking mode. - * @pre Pre-conditions: - * - \ref sl_si91x_sio_init() - * - \ref sl_si91x_sio_uart_init() - * - \ref sl_si91x_sio_uart_send() (or) - * - \ref sl_si91x_sio_uart_send_blocking() - * @param[out] data_buffer - data buffer pointer to read - * @param[in] num_bytes - number of bytes read - * @return returns status 0 if successful, - * else error code as follows: - * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument - * - \ref SL_STATUS_NULL_POINTER (0x0022) - The parameter is a null pointer - * - \ref SL_STATUS_OK (0x0000) - Success -******************************************************************************/ -sl_status_t sl_si91x_sio_uart_read_blocking(void *data_buffer, uint16_t num_bytes); - -/***************************************************************************/ /** - * @brief Register the user callback function. - * @pre Pre-conditions: - * - \ref sl_si91x_sio_init() - * - \ref sl_si91x_sio_uart_init() - * @param[in] callback_event - Pointer to the function \ref sl_sio_uart_callback_t - * which needs to be called at the time of interrupt. - * @return returns status 0 if successful, - * else error code as follows: - * - \ref SL_STATUS_OK (0x0000) - Success - * - \ref SL_STATUS_NULL_POINTER (0x0022) - The parameter is a null pointer - * - \ref SL_STATUS_BUSY (0x0004) - Driver is busy -******************************************************************************/ -sl_status_t sl_si91x_sio_uart_register_event_callback(sl_sio_uart_callback_t callback_event); - -/***************************************************************************/ /** - * @brief Write data using SIO-I2C. - * @pre Pre-conditions: - * - \ref sl_si91x_sio_init() - * - \ref sl_si91x_sio_i2c_generate_start() - * @param[in] configuration - pointer to the I2C configuration structure - * \ref stc_sio_i2c_config_t in SIO module - * @param[in] address - slave address(1- 255). - * @param[in] data - pointer to the data - * @param[in] length - data length - * @return returns status 0 if successful, - * else error code as follows: - * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument - * - \ref SL_STATUS_NULL_POINTER (0x0022) - The parameter is a null pointer - * - \ref SL_STATUS_OK (0X000) - Success -******************************************************************************/ -sl_status_t sl_si91x_sio_i2c_write(stc_sio_i2c_config_t *configuration, - uint8_t address, - uint8_t *data, - uint16_t length); - -/***************************************************************************/ /** - * @brief Read data using SIO-I2C. - * @pre Pre-conditions: - * - \ref sl_si91x_sio_init() - * - \ref sl_si91x_sio_i2c_generate_start() - * - \ref sl_si91x_sio_i2c_write() (or) - * - \ref sl_si91x_sio_i2c_transfer() - * @param[in] configuration - pointer to the I2C configuration structure - * \ref stc_sio_i2c_config_t in SIO module - * @param[in] address - slave address(1- 255). - * @param[out] data - pointer to the data - * @param[in] length - data length - * @return returns status 0 if successful, - * else error code as follows: - * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument - * - \ref SL_STATUS_NULL_POINTER (0x0022) - The parameter is a null pointer - * - \ref SL_STATUS_OK (0X000) - Success -******************************************************************************/ -sl_status_t sl_si91x_sio_i2c_read(stc_sio_i2c_config_t *configuration, uint8_t address, uint8_t *data, uint16_t length); - -/***************************************************************************/ /** - * @brief Transfer data using SIO-I2C. - * @pre Pre-conditions: - * - \ref sl_si91x_sio_init() - * - \ref sl_si91x_sio_i2c_generate_start() - * @param[in] configuration - Pointer to the I2C configuration structure - * \ref stc_sio_i2c_config_t in SIO module - * @param[in] address - Slave address (1- 255). - * @param[in] tx_buffer - Pointer to the data transmit buffer - * @param[in] tx_length - TX data length - * @param[out] rx_buffer - Pointer to the data receive buffer - * @param[in] rx_length - RX data length - * @return returns status 0 if successful, - * else error code as follows: - * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument - * - \ref SL_STATUS_NULL_POINTER (0x0022) - The parameter is a null pointer - * - \ref SL_STATUS_OK (0X000) - Success -******************************************************************************/ -sl_status_t sl_si91x_sio_i2c_transfer(stc_sio_i2c_config_t *configuration, - uint8_t address, - uint8_t *tx_buffer, - uint16_t tx_length, - uint8_t *rx_buffer, - uint16_t rx_length); - -/***************************************************************************/ /** - * @brief Generate I2C start in SIO. - * @pre Pre-condition: - * - \ref sl_si91x_sio_init() - * @param none - * @return none -******************************************************************************/ -void sl_si91x_sio_i2c_generate_start(void); - -/***************************************************************************/ /** - * @brief Generate I2C stop in SIO. - * @pre Pre-conditions: - * - \ref sl_si91x_sio_init() - * - \ref sl_si91x_sio_i2c_generate_start() - * - \ref sl_si91x_sio_i2c_write() (or) - * - \ref sl_si91x_sio_i2c_transfer() - * @param none - * @return none -******************************************************************************/ -void sl_si91x_sio_i2c_generate_stop(void); - -/***************************************************************************/ -/** - * @brief Un-register the user callback function. - * @pre Pre-conditions: - * - \ref sl_si91x_sio_init() - * - \ref sl_si91x_sio_uart_init() - * - \ref sl_si91x_sio_uart_register_event_callback() - * @param none - * @return none -******************************************************************************/ -void sl_si91x_sio_uart_unregister_event_callback(void); - -/***************************************************************************/ /** - * @brief Used when UART receive is done. - * @pre Pre-conditions: - * - \ref sl_si91x_sio_init() - * - \ref sl_si91x_sio_uart_init() - * - \ref sl_si91x_sio_uart_send() - * - \ref sl_si91x_sio_uart_read() - * @param none - * @return none -******************************************************************************/ -void sl_si91x_sio_uart_rx_done(void); - -/***************************************************************************/ /** - * @brief Configure pin detection mode to be considered for GPIO interrupt. - * @pre Pre-conditions: - * - \ref sl_si91x_sio_init() - * @param[in] channel - SIO channel to be selected \ref en_sio_channels_t - * @param[in] flag - GPIO interrupt generated \ref interrupt_flag_t - * - Rise edge: 0 - * - Fall edge: 1 - * - Level 0: 2 - * - Level 1: 3 - * @return returns status 0 if successful, - * else error code as follows: - * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument - * - \ref SL_STATUS_NULL_POINTER (0x0022) - The parameter is a null pointer - * - \ref SL_STATUS_OK (0X000) - Success -******************************************************************************/ -sl_status_t sl_si91x_sio_configure_interrupt(en_sio_channels_t channel, interrupt_flag_t flag); - -/***************************************************************************/ /** - * @brief Match the pattern with data to be detected. - * @pre Pre-conditions: - * - \ref sl_si91x_sio_init() - * @param[in] channel - SIO channel to be selected \ref en_sio_channels_t - * @param[in] pattern - Pattern match bit to be enabled for pattern match to take place \ref pattern_match_t - * - Pattern match disable: 0 - * - Pattern match enable: 1 - * @param[in] slice - Slice number (0,1,2,8,9,10) to select. - * @param[in] slice_pattern - Pattern to match for selected slice - * @return returns status 0 if successful, - * else error code as follows: - * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument - * - \ref SL_STATUS_NULL_POINTER (0x0022) - The parameter is a null pointer - * - \ref SL_STATUS_OK (0X000) - Success -******************************************************************************/ -sl_status_t sl_si91x_sio_match_pattern(en_sio_channels_t channel, - pattern_match_t pattern, - uint8_t slice, - uint32_t slice_pattern); - -/***************************************************************************/ /** - * @brief Generate the shift clock. - * @pre Pre-conditions: - * - \ref sl_si91x_sio_init() - * @param[in] divider - Desired clock frequency configuration - * @param[in] channel - SIO channel to be selected \ref en_sio_channels_t - * @return returns status 0 if successful, - * else error code as follows: - * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument - * - \ref SL_STATUS_NULL_POINTER (0x0022) - The parameter is a null pointer - * - \ref SL_STATUS_OK (0X000) - Success -******************************************************************************/ -sl_status_t sl_si91x_sio_shift_clock(uint32_t divider, en_sio_channels_t channel); - -/***************************************************************************/ /** - * @brief Select SIO peripheral clock. - * @pre Pre-conditions: - * - \ref sl_si91x_sio_init() - * - \ref sl_si91x_sio_uart_init() - * - \ref sl_si91x_sio_uart_register_event_callback() - * - \ref sl_si91x_sio_uart_send() - * @param[in] channel - SIO channel to be selected \ref en_sio_channels_t - * @param[in] clock - Clock used for shift operations \ref clock_type_t - * - Internal clock: 0 - * - External clock: 1 - * @return returns status 0 if successful, - * else error code as follows: - * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument - * - \ref SL_STATUS_NULL_POINTER (0x0022n) - The parameter is null pointer - * - \ref SL_STATUS_OK (0X000) - Success -******************************************************************************/ -sl_status_t sl_si91x_sio_select_clock(en_sio_channels_t channel, clock_type_t clock); - -/***************************************************************************/ /** - * @brief Shift the number of bits. Number of shifts to happen before reloading - * the shift register with data/pausing the operation. i.e. value to be - * set = (total no. of valid bits in shift register/ number of bits per shift) – 1 - * @pre Pre-conditions: - * - \ref sl_si91x_sio_init() - * @param[in] channel - SIO channel to be selected \ref en_sio_channels_t - * @param[in] data_shift - Number of shifts to happen before reloading register with data. - * Value to be set = (total no. of valid bits in shift register/ no. of bits per shift) - 1 - * @return returns status 0 if successful, - * else error code as follows: - * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument - * - \ref SL_STATUS_NULL_POINTER (0x0022) - The parameter is null pointer - * - \ref SL_STATUS_OK (0X000) - Success -******************************************************************************/ -sl_status_t sl_si91x_sio_position_counter(en_sio_channels_t channel, uint32_t data_shift); - -/***************************************************************************/ /** - * @brief Enable/disable the flow control bit. - * @pre Pre-conditions: - * - \ref sl_si91x_sio_init() - * @param[in] channel - SIO channel to be selected \ref en_sio_channels_t - * @param[in] flow_control - It decides whether to continue data shifting based on data - * present in shift register validation \ref flow_control_t - * - Flow control disable: 0 - * - Flow control enable: 1 - * @return returns status 0 if successful, - * else error code as follows: - * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument - * - \ref SL_STATUS_NULL_POINTER (0x0022n) - The parameter is null pointer - * - \ref SL_STATUS_OK (0X000) - Success -******************************************************************************/ -sl_status_t sl_si91x_sio_control_flow(en_sio_channels_t channel, flow_control_t flow_control); - -/***************************************************************************/ /** - * @brief Load data to buffer in reverse order. - * @pre Pre-condition: - * - \ref sl_si91x_sio_init() - * @param[in] channel - SIO channel to be selected \ref en_sio_channels_t - * @param[in] reverse - If data to be shifted out MSB first, it is to be set \ref reverse_load_t - * @return returns status 0 if successful, - * else error code as follows: - * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument - * - \ref SL_STATUS_NULL_POINTER (0x0022n) - The parameter is null pointer - * - \ref SL_STATUS_OK (0X000) - Success -******************************************************************************/ -sl_status_t sl_si91x_sio_reverse_load(en_sio_channels_t channel, reverse_load_t reverse); - -/***************************************************************************/ /** - * @brief Enable the common swap interrupt. - * @pre Pre-condition: - * - \ref sl_si91x_sio_init() - * @param[in] channel - SIO channel to be selected \ref en_sio_channels_t - * @return returns status 0 if successful, - * else error code as follows: - * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument - * - \ref SL_STATUS_NULL_POINTER (0x0022n) - The parameter is null pointer - * - \ref SL_STATUS_OK (0X000) - Success -******************************************************************************/ -sl_status_t sl_si91x_sio_set_interrupt(en_sio_channels_t channel); - -/***************************************************************************/ /** - * @brief Disable the common swap interrupt. - * @pre Pre-conditions: - * - \ref sl_si91x_sio_init() - * - \ref sl_si91x_sio_i2c_generate_start() - * - \ref sl_si91x_sio_i2c_write() (or) - * - \ref sl_si91x_sio_i2c_transfer() - * @param[in] channel - SIO channel to be selected \ref en_sio_channels_t - * @return returns status 0 if successful, - * else error code as follows: - * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument - * - \ref SL_STATUS_NULL_POINTER (0x0022n) - The parameter is null pointer - * - \ref SL_STATUS_OK (0X000) - Success -******************************************************************************/ -sl_status_t sl_si91x_sio_clear_interrupt(en_sio_channels_t channel); - -/***************************************************************************/ /** - * @brief Mask the common swap interrupt. - * @pre Pre-conditions: - * - \ref sl_si91x_sio_init() - * @param[in] channel - SIO channel to be selected \ref en_sio_channels_t - * @return returns status 0 if successful, - * else error code as follows: - * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument - * - \ref SL_STATUS_NULL_POINTER (0x0022n) - The parameter is null pointer - * - \ref SL_STATUS_OK (0X000) - Success -******************************************************************************/ -sl_status_t sl_si91x_sio_mask_interrupt(en_sio_channels_t channel); - -/***************************************************************************/ /** - * @brief Unmask the common swap interrupt. - * @pre Pre-condition: - * - \ref sl_si91x_sio_init() - * @param[in] channel - SIO channel to be selected \ref en_sio_channels_t - * @return returns status 0 if successful, - * else error code as follows: - * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument - * - \ref SL_STATUS_NULL_POINTER (0x0022n) - The parameter is null pointer - * - \ref SL_STATUS_OK (0X000) - Success -******************************************************************************/ -sl_status_t sl_si91x_sio_unmask_interrupt(en_sio_channels_t channel); - -/***************************************************************************/ /** - * @brief Read the common swap interrupt status. - * @pre Pre-condition: - * - \ref sl_si91x_sio_init() - * @param none - * @return returns interrupt status -******************************************************************************/ -uint32_t sl_si91x_sio_get_interrupt_status(void); - -/***************************************************************************/ /** - * @brief Enable the common shift interrupt. - * @pre Pre-condition: - * - \ref sl_si91x_sio_init() - * @param[in] channel - SIO channel to be selected \ref en_sio_channels_t - * @return returns status 0 if successful, - * else error code as follows: - * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument - * - \ref SL_STATUS_NULL_POINTER (0x0022n) - The parameter is null pointer - * - \ref SL_STATUS_OK (0X000) - Success -******************************************************************************/ -sl_status_t sl_si91x_sio_set_shift_interrupt(en_sio_channels_t channel); - -/***************************************************************************/ /** - * @brief Disable the common shift interrupt. - * @pre Pre-condition: - * - \ref sl_si91x_sio_init() - * @param[in] channel - SIO channel to be selected \ref en_sio_channels_t - * @return returns status 0 if successful, - * else error code as follows: - * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument - * - \ref SL_STATUS_NULL_POINTER (0x0022n) - The parameter is null pointer - * - \ref SL_STATUS_OK (0X000) - Success -******************************************************************************/ -sl_status_t sl_si91x_sio_clear_shift_interrupt(en_sio_channels_t channel); - -/***************************************************************************/ /** - * @brief Mask the common shift interrupt. - * @pre Pre-condition: - * - \ref sl_si91x_sio_init() - * @param[in] channel - SIO channel to be selected \ref en_sio_channels_t - * @return returns status 0 if successful, - * else error code as follows: - * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument - * - \ref SL_STATUS_NULL_POINTER (0x0022n) - The parameter is null pointer - * - \ref SL_STATUS_OK (0X000) - Success -******************************************************************************/ -sl_status_t sl_si91x_sio_mask_shift_interrupt(en_sio_channels_t channel); - -/***************************************************************************/ /** - * @brief Unmask the common shift interrupt. - * @pre Pre-condition: - * - \ref sl_si91x_sio_init() - * @param[in] channel - SIO channel to be selected \ref en_sio_channels_t - * @return returns status 0 if successful, - * else error code as follows: - * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument - * - \ref SL_STATUS_NULL_POINTER (0x0022n) - The parameter is null pointer - * - \ref SL_STATUS_OK (0X000) - Success -******************************************************************************/ -sl_status_t sl_si91x_sio_unmask_shift_interrupt(en_sio_channels_t channel); - -/***************************************************************************/ /** - * @brief Read the common shift interrupt status. - * @pre Pre-condition: - * - \ref sl_si91x_sio_init() - * @param[in] channel - SIO channel to be selected \ref en_sio_channels_t - * @return returns shift interrupt status -******************************************************************************/ -uint32_t sl_si91x_sio_shift_interrupt_status(void); - -/***************************************************************************/ /** - * @brief Select edge of the clock cycle for sampling bits. - * @pre Pre-condition: - * - \ref sl_si91x_sio_init() - * @param[in] channel - SIO channel to be selected \ref en_sio_channels_t - * @param[in] edge_sel - Select the edge for bit sample to start \ref edge_select_t - * - Positive edge: 0 - * - Negative edge: 1 - * @return returns status 0 if successful, - * else error code as follows: - * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument - * - \ref SL_STATUS_NULL_POINTER (0x0022n) - The parameter is null pointer - * - \ref SL_STATUS_OK (0X000) - Success -******************************************************************************/ -sl_status_t sl_si91x_sio_edge_select(en_sio_channels_t channel, edge_select_t edge_sel); - -/***************************************************************************/ /** - * @brief Read SIO buffer register. - * @pre Pre-condition: - * - \ref sl_si91x_sio_init() - * - \ref sl_si91x_sio_uart_init() - * - \ref sl_si91x_sio_uart_register_event_callback() - * - \ref sl_si91x_sio_uart_send() - * @param[in] channel - SIO channel to be selected \ref en_sio_channels_t - * @return returns data from buffer -******************************************************************************/ -uint32_t sl_si91x_sio_read_buffer(en_sio_channels_t channel); - -/***************************************************************************/ /** - * @brief Write into SIO buffer register. - * @pre Pre-condition: - * - \ref sl_si91x_sio_init() - * - \ref sl_si91x_sio_uart_init() - * - \ref sl_si91x_sio_uart_register_event_callback() - * - \ref sl_si91x_sio_uart_send() - * @param[in] channel - SIO channel to be selected \ref en_sio_channels_t - * @param[in] data - Data to be written to buffer - * @return returns status 0 if successful, - * else error code as follows: - * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument - * - \ref SL_STATUS_NULL_POINTER (0x0022n) - The parameter is null pointer - * - \ref SL_STATUS_OK (0X000) - Success -******************************************************************************/ -sl_status_t sl_si91x_sio_write_buffer(en_sio_channels_t channel, uint32_t data); - -// ******** THE REST OF THE FILE IS DOCUMENTATION ONLY! *********************** -/// @addtogroup SIO Serial Input-Output -/// @{ -/// -/// @details -/// -/// -/// @n @section SIO_Intro Introduction -/// -/// -/// Serial Input/Output (SIO) refers to a method of data transfer where information is sent and received -/// sequentially, one bit at a time, over a single communication channel. This communication can occur between -/// different electronic devices, such as micro-controllers, sensors, or other components. -/// -/// Key features of SIO include: -/// -/// @li SIO Functionality is supported by Eight GPIO pins. -/// -/// @li Detects a 32-bit pattern on the input pins. -/// -/// @li SIO will transmit or receive the MSB First. -/// -/// @n @section SIO_Config Configuration -/// -/// Various parameters SPI bit order, SPI clock, MOSI channel, MISO channel, -/// SPI CS channel, bit length, SPI mode can be configured. -/// Various parameters UART baud rate, bit length, parity, receive channel selection, transmit -/// channel selection, stop bits can be configured with below given Enumerations. -/// -/// 1. @ref sl_sio_spi_event_t -/// -/// 2. @ref sl_sio_uart_event_t -/// -/// 3. @ref sl_sio_spi_mode_t -/// -/// 4. @ref sl_sio_spi_bit_width_t -/// -/// 5. @ref sl_sio_spi_msb_lsb_t -/// -/// 6. @ref sl_sio_spi_bit_length_t -/// -/// 7. @ref sl_sio_spi_parity_t -/// -/// 8. @ref sl_sio_spi_stop_bit_t -/// -/// @li For more information on configuring available parameters refer to the respective peripheral example readme document. -/// -/// @n @section SIO_Use Usage -/// -/// Data is transferred over SIO SPI after it has been initialized and configured. A callback -/// API is then called to register the callback at the moment of the event. Before transfer has -/// begin, chip select assert is to be done. In order to do this test, the MISO and MOSI pins must -/// be connected in loopback mode. -/// -/// After transfer completion, chip select de-assert is to be done using When the transfer complete event -/// is generated, it compares the sent and received data. -/// -/// 1. @ref sl_si91x_sio_spi_pin_initialization -/// -/// 2. @ref sl_si91x_sio_spi_init -/// -/// 3. @ref sl_si91x_sio_spi_register_event_callback -/// -/// 4. @ref sl_si91x_sio_spi_cs_assert -/// -/// 5. @ref sl_si91x_sio_spi_transfer -/// -/// 6. @ref sl_si91x_sio_spi_cs_deassert -/// -/// 7. @ref sl_si91x_sio_deinit -/// -/// Data is sent and received by SIO UART after it has been initiated and configured. A callback API is -/// then called to register the callback at the moment of the event. Subsequently, the transfer buffer will -/// transmit the required number of bytes, and the receive buffer will obtain the data bytes. It compares the -/// sent and received data when the receive complete event is created. -/// -/// 1. @ref sl_si91x_sio_uart_pin_initialization -/// -/// 2. @ref sl_si91x_sio_uart_init -/// -/// 2. @ref sl_si91x_sio_uart_register_event_callback -/// -/// 3. @ref sl_si91x_sio_uart_send -/// -/// 4. @ref sl_si91x_sio_uart_read -/// -/// 5. @ref sl_si91x_sio_deinit -/// -/** @} (end addtogroup PWM) */ - -#ifdef __cplusplus -} -#endif - -#endif ///< SL_SI91X_SIO_H -/**************************************************************************************************/ diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_usart.h b/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_usart.h index a786171dd..8624bf852 100644 --- a/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_usart.h +++ b/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_usart.h @@ -95,7 +95,6 @@ typedef enum { SL_USART_DATA_BITS_6 = ARM_USART_DATA_BITS_6, ///< 6 data bits SL_USART_DATA_BITS_7 = ARM_USART_DATA_BITS_7, ///< 7 data bits SL_USART_DATA_BITS_8 = ARM_USART_DATA_BITS_8, ///< 8 data bits - SL_USART_DATA_BITS_9 = ARM_USART_DATA_BITS_9, ///< 9 data bits } usart_databits_typedef_t; /// @brief Parity selection @@ -394,7 +393,10 @@ uint32_t sl_si91x_usart_get_rx_data_count(sl_usart_handle_t usart_handle); * @param[in] usart_handle Pointer to the USART/UART driver * * @param[in] control_configuration pointer to the USART configurations -* +* @note +* control_configuration - This parameter is used to pass the respective peripheral configuration when +* USART_UC, UART_UC, ULP_UART_UC macros are disabled for particular instance. When this macros are enabled +* configuration are taken directly from the UC and this parameter is not considered. * @return status 0 if successful, else error code * - \ref SL_STATUS_BUSY (0x0004) - Busy ,already data transfer is going on * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is invalid argument diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_watchdog_timer.h b/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_watchdog_timer.h index 1bd6654f1..a29c2bebb 100644 --- a/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_watchdog_timer.h +++ b/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_watchdog_timer.h @@ -161,8 +161,7 @@ sl_status_t sl_si91x_watchdog_configure_clock(watchdog_timer_clock_config_t *tim * @brief This API configures watchdog timer parameters. * @details The configurable parameters are interrupt time (WDT restart time), * system reset time & window time (lower time stamp for WDT restart, if required). - * System reset time should be greater than interrupt time. - * And Interrupt time should be greater than window time, else API will give an error. + * Interrupt time should be greater than window time, else API will give an error. * * @pre Pre-conditions: * - \ref sl_si91x_watchdog_init_timer @@ -172,8 +171,8 @@ sl_status_t sl_si91x_watchdog_configure_clock(watchdog_timer_clock_config_t *tim * @return status 0 if successful, else error code as follows: * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - Timer configuration structure members have invalid values, * for members \ref watchdog_timer_config_t - * - \ref SL_STATUS_INVALID_CONFIGURATION (0x0023) - Timer configuration structure member 'system_reset_time' is less than or equal to 'interrupt_time'. - * It should be greater than interrupt time of timer. + * - \ref SL_STATUS_INVALID_CONFIGURATION (0x0023) - Timer configuration structure member 'interrupt_time' is less than or equal to 'window_time'. + * It should be greater than window time of timer. * - \ref SL_STATUS_NULL_POINTER (0x0022) - The parameter is a null pointer * - \ref SL_STATUS_OK (0x0000) - Success, timer parameters configured properly *******************************************************************************/ @@ -199,7 +198,7 @@ sl_status_t sl_si91x_watchdog_register_timeout_callback(watchdog_timer_callback_ * @details This also referred as upper time-stamp for WDT restart * Its maximum value is 31. * @li Number of clock pulses for timer timeout = 2^(interrupt_time) - * @note The timeout value should be less than system-reset time and greater than window time. + * @note The 'interrupt time' value should be greater than window time. * * @pre Pre-conditions: * - \ref sl_si91x_watchdog_init_timer @@ -209,7 +208,7 @@ sl_status_t sl_si91x_watchdog_register_timeout_callback(watchdog_timer_callback_ * Number of clock pulses = 2^(interrupt_time), \ref time_delays_t * @return status 0 if successful, else error code as follows: * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - 'interrupt_time' parameter has an invalid value. - * - \ref SL_STATUS_INVALID_CONFIGURATION (0x0023) - 'interrupt_time' value is less than window time or greater than system reset time + * - \ref SL_STATUS_INVALID_CONFIGURATION (0x0023) - 'interrupt_time' value is less than window time. * - \ref SL_STATUS_OK (0x0000) - Successfully set watchdog timer timeout time value *******************************************************************************/ sl_status_t sl_si91x_watchdog_set_interrupt_time(time_delays_t interrupt_time); @@ -230,7 +229,7 @@ uint8_t sl_si91x_watchdog_get_interrupt_time(void); * @brief This API will set the Watchdog timer system-reset time duration. * @details Number of clock pulses for system reset time = 2^(system_reset_time). * Its maximum value is 31. - * This value should be greater than timer interrupt time & window time. + * This value should be greater than timer window time. * @pre Pre-conditions: * - \ref sl_si91x_watchdog_init_timer * - \ref sl_si91x_watchdog_configure_clock @@ -238,7 +237,7 @@ uint8_t sl_si91x_watchdog_get_interrupt_time(void); * Number of clock pulses = 2^(system_reset_time), \ref time_delays_t * @return status 0 if successful, else error code as follows: * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - 'system_reset_time' parameter has an invalid value. - * - \ref SL_STATUS_INVALID_CONFIGURATION (0x0023) - 'system_reset_time' value is less than window time or interrupt time + * - \ref SL_STATUS_INVALID_CONFIGURATION (0x0023) - 'system_reset_time' value is less than window time. * - \ref SL_STATUS_OK (0x0000) - Successfully set watchdog timer system-reset time value *******************************************************************************/ sl_status_t sl_si91x_watchdog_set_system_reset_time(time_delays_t system_reset_time); diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_adc.c b/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_adc.c index 9ddc4793a..52e94c3d7 100644 --- a/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_adc.c +++ b/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_adc.c @@ -44,7 +44,6 @@ #ifndef MISC_CONFIG_MISC_CTRL1 #define MISC_CONFIG_MISC_CTRL1 *(volatile uint32_t *)(0x46008000 + 0x44) #endif // MISC_CONFIG_MISC_CTRL1 -#define SOC_PLL_LIMIT 120000000 // Limit for soc pll clock. #define MAX_SAMPLE_RATE 2500000 // Maximum sampling rate 2.5 Msps. #define MINIMUM_NUMBER_OF_CHANNEL 1 // Minimum number of channel enable #define MAXIMUM_NUMBER_OF_CHANNEL 16 // Maximum number of channel enable @@ -82,7 +81,6 @@ static sl_status_t convert_rsi_to_sl_error_code(rsi_error_t error); static sl_status_t validate_adc_parameters(sl_adc_config_t *adc_config); static sl_status_t validate_adc_channel_parameters(sl_adc_channel_config_t *adc_channel_config); static sl_status_t validate_adc_thrld_parameters(sl_adc_fifo_thrld_config_t *adc_fifo_threshold); -static sl_status_t validate_adc_ext_trigger_parameters(sl_adc_external_config_t *adc_external_trigger); static sl_status_t validate_adc_internal_parameters(sl_adc_internal_config_t *adc_internal_config); static sl_status_t sl_si91x_adc_channel_interrupt_clear(sl_adc_config_t adc_config, uint8_t channel_num); static sl_status_t sl_si91x_adc_configure_reference_voltage(float vref_value, float chip_voltage); @@ -122,16 +120,8 @@ sl_status_t sl_si91x_adc_configure_clock(sl_adc_clock_config_t *clock_configurat status = SL_STATUS_NULL_POINTER; break; } - if (clock_configuration->soc_pll_clock >= SOC_PLL_LIMIT) { - /*Configure the prefetch and registering when SOC clock is more than 120Mhz*/ - /*Configure the SOC PLL to 220MHz*/ - ICACHE2_ADDR_TRANSLATE_1_REG = BIT(21); //Icache registering when clk freq more than 120 - /*When set, enables registering in M4-TA AHB2AHB. This will have performance penalty. This has to be set above 100MHz*/ - MISC_CFG_SRAM_REDUNDANCY_CTRL = BIT(4); - MISC_CONFIG_MISC_CTRL1 |= BIT(4); //Enable Register ROM as clock frequency is 200 Mhz - } clock_configuration->division_factor = 1; - /* Switch ULP Pro clock to 90 MHZ */ + /* Switch ULP Pro clock to 90MHz */ RSI_ULPSS_ClockConfig(M4CLK, adc_clock, clock_configuration->division_factor, odd_divfactor); } while (false); return status; @@ -364,25 +354,6 @@ void sl_si91x_adc_unregister_event_callback(void) user_callback = NULL; } -/******************************************************************************* - * To configure external trigger as ULP_timer, ULP_gpio,M4_CT based on this - * it will detect edge and channel trigger selection will be happen. - * RSI errors are converted to the SL errors via convert_rsi_to_sl_error_code - * function. - ******************************************************************************/ -sl_status_t sl_si91x_adc_configure_external_trigger(sl_adc_external_config_t adc_external_trigger) -{ - sl_status_t status; - rsi_error_t error_status; - // Validate adc_external_trigger parameters. - status = validate_adc_ext_trigger_parameters(&adc_external_trigger); - if (status == SL_STATUS_OK) { - error_status = RSI_ADC_ExtTrigConfig(AUX_ADC_DAC_COMP, adc_external_trigger); - status = convert_rsi_to_sl_error_code(error_status); - } - return status; -} - /******************************************************************************* * To configure the ADC sampling rate for ADC channels. * It will set channel offset value and channel frequency for each channel to set the @@ -863,42 +834,6 @@ sl_status_t sl_si91x_adc_channel_disable(uint8_t channel_num) return status; } -/******************************************************************************* - * To read the external trigger status of ADC. - * RSI errors are converted to the SL errors via convert_rsi_to_sl_error_code - * function. - ******************************************************************************/ -sl_status_t sl_si91x_adc_get_external_trigger_status(sl_adc_external_config_t adc_external_trigger, - uint8_t *ext_trigger) -{ - sl_status_t status; - // Validate adc_external_trigger parameters. - status = validate_adc_ext_trigger_parameters(&adc_external_trigger); - if (status == SL_STATUS_OK) { - *ext_trigger = RSI_ADC_ExtTrigStatusRead(AUX_ADC_DAC_COMP, adc_external_trigger); - status = SL_STATUS_OK; - } - return status; -} - -/******************************************************************************* - * To clear the external trigger status. - * RSI errors are converted to the SL errors via convert_rsi_to_sl_error_code - * function. - ******************************************************************************/ -sl_status_t sl_si91x_adc_clear_external_trigger(sl_adc_external_config_t adc_external_trigger) -{ - sl_status_t status; - // Validate adc_external_trigger parameters. - status = validate_adc_ext_trigger_parameters(&adc_external_trigger); - if (status == SL_STATUS_OK) { - RSI_ADC_ExtTrigStatusClear(AUX_ADC_DAC_COMP, adc_external_trigger); - // In rsi not returning RSI_OK, so that we passing SL_STATUS_OK here. - status = SL_STATUS_OK; - } - return status; -} - /******************************************************************************* * To Unmask the ADC channel. * The interrupt will clear when static mode interrupt will detect, threshold @@ -1070,41 +1005,6 @@ static sl_status_t validate_adc_channel_parameters(sl_adc_channel_config_t *adc_ return status; } -/******************************************************************************* - * To validate the parameters of ADC external trigger and build a 32 bit integer - * It takes pointer to ADC external trigger configuration structure and pointer - * to the uint32_t as argument and builds the integer using the validations and - * 'OR' operation. - * According to the values in external trigger configuration structure, it - * performs the 'OR' operation of the values. - ******************************************************************************/ -static sl_status_t validate_adc_ext_trigger_parameters(sl_adc_external_config_t *adc_external_trigger) -{ - sl_status_t status; - do { - //Validate ADC external trigger type. - if (adc_external_trigger->trigger_type >= SL_ADC_EXT_TRIGGER_TYPE_LAST) { - status = SL_STATUS_INVALID_PARAMETER; - break; - } - // Validate ADC external trigger detection and edge trigger. - if ((adc_external_trigger->trigger_num >= SL_ADC_EXT_TRIGGER_LAST) - || (adc_external_trigger->detection_edge_sel >= SL_ADC_EXT_TRIGGER_EDGE_LAST)) { - status = SL_STATUS_INVALID_PARAMETER; - break; - } - // Validate ADC external trigger selection and channel_id. - if ((adc_external_trigger->trigger_sel_val >= MAXIMUM_CHANNEL_ID) - || (adc_external_trigger->trigger_sel >= SL_ADC_EXT_TRIGGER_SEL_LAST)) { - status = SL_STATUS_INVALID_PARAMETER; - break; - } - // Returns SL_STATUS_OK if the parameter are appropriate - status = SL_STATUS_OK; - } while (false); - return status; -} - /******************************************************************************* * To validate the parameters of ADC internal parameters and build a 32 bit integer * It takes pointer to ADC internal parameters configuration structure and pointer diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_bjt_temperature_sensor.c b/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_bjt_temperature_sensor.c index 3b926bb86..28d83c28c 100644 --- a/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_bjt_temperature_sensor.c +++ b/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_bjt_temperature_sensor.c @@ -40,7 +40,7 @@ #define VREF_VALUE 2.61f // default reference voltage #define BOD_TEST_SEL_VALUE 3 // BOD test selection value #define LOAD_BJT_TEMP 25 // load bjt temperature -#define SAMPLING_RATE 50000 // sampling rate value for adc +#define SAMPLING_RATE 9000 // sampling rate value for adc #define CHANNEL_NUMBER 0 // channel number for adc #define POS_IP_OPAMP 20 // Positive input to ADC using OPAMP #define POS_IP_BJT 23 // positive input to ADC using bjt temperature sensor @@ -68,7 +68,7 @@ static float adc_output_bjt[CHANNEL_SAMPLE_LENGTH] = { 0 }; static float adc_output_bg[CHANNEL_SAMPLE_LENGTH] = { 0 }; adc_config_t sl_bjt_config = { SL_ADC_STATIC_MODE, NUMBER_OF_CHANNELS }; -adc_ch_config_t sl_bjt_channel_config = { .input_type[0] = CHANNEL_NUMBER, +adc_ch_config_t sl_bjt_channel_config = { .input_type[0] = SL_ADC_SINGLE_ENDED, .sampling_rate[0] = SAMPLING_RATE, .num_of_samples[0] = CHANNEL_SAMPLE_LENGTH }; diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_config_timer.c b/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_config_timer.c index 0db7a0691..648539607 100644 --- a/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_config_timer.c +++ b/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_config_timer.c @@ -31,7 +31,7 @@ #include "sl_si91x_config_timer_config.h" #include "rsi_rom_ct.h" #include "rsi_rom_clks.h" - +#include "clock_update.h" /******************************************************************************* *************************** DEFINES / MACROS ******************************** ******************************************************************************/ @@ -298,6 +298,27 @@ sl_status_t sl_si91x_config_timer_set_match_count(sl_config_timer_mode_t mode, return status; } +/******************************************************************************* +* @brief: API to calculate and return the match value of the timer for desired time period +*******************************************************************************/ +sl_status_t sl_si91x_config_timer_get_match_value(uint32_t time_period_in_us, uint32_t *match_value) +{ + uint32_t ct_base_clock; + // Get CT base clock + ct_base_clock = RSI_CLK_GetBaseClock(M4_CT); + ct_base_clock /= 1000000; + // Validate the time period by comparing with maximum count of 16-bit counter and the CT base clock. + // For example, for a CT base clock of 32MHz, the maximum time period achieved is 2047us. + // For a CT base clock of 180MHz, the maximum time period achieved is 364us. + // The counter can be loaded multiple times if requires a higher time period. + if (time_period_in_us > (MAX_COUNT_VALUE_16BIT / ct_base_clock)) { + return SL_STATUS_INVALID_COUNT; + } + // Calculate match value + *match_value = ct_base_clock * time_period_in_us; // time period in microseconds + return SL_STATUS_OK; +} + /******************************************************************************* * @brief:sets initial value for counter-0 or counter-1 ,as per ct MODE * @@ -481,10 +502,10 @@ sl_status_t sl_si91x_config_timer_configure_action_event(sl_config_action_event_ break; } // Validating event value - if ((event_config_handle->and_event_counter0 >= SL_EVENT_LAST) - || (event_config_handle->or_event_counter0 >= SL_EVENT_LAST) - || (event_config_handle->and_event_counter1 >= SL_EVENT_LAST) - || (event_config_handle->or_event_counter1 >= SL_EVENT_LAST)) { + if ((event_config_handle->and_event_counter0 >= SL_CT_EVENT_LAST) + || (event_config_handle->or_event_counter0 >= SL_CT_EVENT_LAST) + || (event_config_handle->and_event_counter1 >= SL_CT_EVENT_LAST) + || (event_config_handle->or_event_counter1 >= SL_CT_EVENT_LAST)) { status = SL_STATUS_INVALID_PARAMETER; break; } @@ -569,7 +590,7 @@ sl_status_t sl_si91x_config_timer_select_action_event(sl_config_timer_action_t a break; } // Validating select-event value - if ((select_event_counter0 >= SL_EVENT_LAST) || (select_event_counter1 >= SL_EVENT_LAST)) { + if ((select_event_counter0 >= SL_CT_EVENT_LAST) || (select_event_counter1 >= SL_CT_EVENT_LAST)) { status = SL_STATUS_INVALID_PARAMETER; break; } diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_crc.c b/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_crc.c index ac10643f6..a8af8d2db 100644 --- a/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_crc.c +++ b/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_crc.c @@ -189,7 +189,7 @@ sl_status_t sl_si91x_crc_write_data(sl_crc_params_t *pCRCParams, uint32_t data, * sl_crc_params_t *pCRCParams, * uint32_t crc) * @brief This API is used to monitor the CRC Calculation status and the - *returns the CRC Value. + * returns the CRC Value. *******************************************************************************/ sl_status_t sl_si91x_crc_monitor_crc_calc(sl_crc_params_t *pCRCParams, uint32_t *crc) { @@ -259,7 +259,7 @@ sl_status_t sl_si91x_crc_enable(void) /******************************************************************************* * @fn sl_status_t sl_si91x_crc_disable(void) - * @brief Enables the CRC peripheral. + * @brief Disables the CRC peripheral. * * This function disable the CRC peripheral by disabling its clock. ******************************************************************************/ diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_driver_gpio.c b/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_driver_gpio.c index d02720eb6..8794a0ebb 100644 --- a/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_driver_gpio.c +++ b/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_driver_gpio.c @@ -198,14 +198,16 @@ sl_status_t sl_gpio_set_configuration(sl_si91x_gpio_pin_config_t pin_config) case SL_GPIO_PORT_B: case SL_GPIO_PORT_C: case SL_GPIO_PORT_D: + status = sl_gpio_validation(&pin_config.port_pin); + if (status != SL_STATUS_OK) { + return status; + } // Check if the GPIO pad is selected and it's not NO PAD. if (m4_gpio_pad[(pin_config.port_pin.port * MAX_GPIO_PORT_PIN) + pin_config.port_pin.pin] != GPIO_PAD_SELECT_NO_PAD) { // Check if the GPIO pad is selected and not PAD_SELECT_9. if (m4_gpio_pad[(pin_config.port_pin.port * MAX_GPIO_PORT_PIN) + pin_config.port_pin.pin] != PAD_SELECT_9) { - if ((pin_config.port_pin.pin >= HOST_PAD_MIN && pin_config.port_pin.pin <= HOST_PAD_MAX) - || ((pin_config.port_pin.port == SL_GPIO_PORT_B && pin_config.port_pin.pin >= GPIO_PIN_NUMBER9) - && (pin_config.port_pin.port == SL_GPIO_PORT_B && pin_config.port_pin.pin <= GPIO_PIN_NUMBER14))) { + if (SL_GPIO_VALIDATE_HOST_PIN(pin_config.port_pin.port, pin_config.port_pin.pin)) { status = sl_si91x_gpio_driver_enable_host_pad_selection( m4_gpio_pad[(pin_config.port_pin.port * MAX_GPIO_PORT_PIN) + pin_config.port_pin.pin]); if (status != SL_STATUS_OK) { @@ -783,7 +785,7 @@ sl_status_t sl_si91x_gpio_driver_enable_pad_selection(uint8_t gpio_padnum) sl_status_t sl_si91x_gpio_driver_enable_host_pad_selection(uint8_t gpio_num) { // Check if the GPIO pin number exceeds the maximum allowed value. - if (gpio_num >= HOST_PAD_MIN && gpio_num <= HOST_PAD_MAX) { + if (!(gpio_num >= HOST_PAD_MIN && gpio_num <= HOST_PAD_MAX)) { return SL_STATUS_INVALID_PARAMETER; } // Enable host pad selection for the GPIO pin. @@ -1856,12 +1858,6 @@ void PIN_IRQ6_Handler(void) ******************************************************************************/ void PIN_IRQ7_Handler(void) { -// A temporary fix (delay of 46 micro seconds) to supress dual interrupts with rising edge. -#ifdef SL_SI91x_DUAL_INTERRUPTS_ERRATA - for (int i = 0; i < 1000; i++) - __asm__("nop;"); -#endif // SL_SI91x_DUAL_INTERRUPTS_ERRATA - sl_gpio_driver_clear_interrupts(PIN_INTR_7); gpio_callback_function_pointer[PIN_INTR_7](PIN_INTR_7); } @@ -1909,7 +1905,9 @@ void UULP_PIN_IRQ_Handler(void) sl_si91x_gpio_driver_clear_uulp_interrupt(UULP_INTR_5); flag = PIN_INTR_4; } - gpio_uulp_pin_int_callback_fptr[flag](flag); + if (gpio_uulp_pin_int_callback_fptr[flag] != NULL) { + gpio_uulp_pin_int_callback_fptr[flag](flag); + } } /******************************************************************************* @@ -1967,6 +1965,7 @@ void ULP_GROUP_IRQ_Handler(void) sl_si91x_gpio_driver_clear_ulp_group_interrupt(GROUP_INT_2); flag = GROUP_INT_2; } + gpio_ulp_group_int_callback_fptr[flag](flag); } diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_gspi.c b/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_gspi.c index 4a89dd3e7..df42838c5 100644 --- a/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_gspi.c +++ b/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_gspi.c @@ -235,7 +235,7 @@ static sl_status_t sli_si91x_gspi_configure_power_mode(sl_gspi_handle_t gspi_han * It configures GSPI mode, Bit width (frame length), master mode, bitrate, * swap read, swap write and slave select mode. * - GSPI Mode, Value: GSPI_MODE_0 / GSPI_MODE_3 - * - Bit width (frame length), Value: 4 to 16 + * - Bit width (frame length), Value: 1 to 16 * - Master Mode, Value: GSPI_MASTER_ACTIVE / GSPI_MASTER_INACTIVE * - Bitrate, Value: Less than 40000000 * - Swap Read, Value: ENABLE / DISABLE @@ -275,7 +275,10 @@ sl_status_t sl_si91x_gspi_set_configuration(sl_gspi_handle_t gspi_handle, if (status != SL_STATUS_OK) { break; } - + if (control_configuration->bit_width == MAX_BIT_WIDTH) { + // For 16 data width, it is required to set the data width as 0. + control_configuration->bit_width = 0; + } input_mode = (control_configuration->clock_mode | SL_GSPI_MASTER_ACTIVE | control_configuration->slave_select_mode | ARM_SPI_DATA_BITS(control_configuration->bit_width)); // CMSIS API for GSPI control is called and the arm error code returned from @@ -699,7 +702,7 @@ static sl_status_t validate_control_parameters(sl_gspi_control_config_t *control } // If the bit width is not in range i.e., between 0 and 16, // returns the error code. - if ((control_configuration->bit_width == MIN_BIT_WIDTH) || (control_configuration->bit_width >= MAX_BIT_WIDTH)) { + if ((control_configuration->bit_width == MIN_BIT_WIDTH) || (control_configuration->bit_width > MAX_BIT_WIDTH)) { status = SL_STATUS_INVALID_PARAMETER; break; } diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_i2c.c b/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_i2c.c index 897108ce5..2731b75d6 100644 --- a/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_i2c.c +++ b/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_i2c.c @@ -149,6 +149,7 @@ sl_i2c_status_t sl_i2c_driver_init(sl_i2c_instance_t i2c_instance, const sl_i2c_ // will return an error code, also validating members of i2c-config // structure. if ((p_user_config == NULL) || (i2c_instance >= SL_I2C_LAST) || (p_user_config->mode > SL_I2C_FOLLOWER_MODE) + || (p_user_config->operating_mode < SL_I2C_STANDARD_MODE) || (p_user_config->operating_mode >= SL_I2C_OPERATING_MODE_LAST) || (p_user_config->transfer_type >= SL_I2C_TRANFER_TYPE_LAST)) { i2c_status = SL_I2C_INVALID_PARAMETER; @@ -170,7 +171,6 @@ sl_i2c_status_t sl_i2c_driver_init(sl_i2c_instance_t i2c_instance, const sl_i2c_ i2c = (I2C0_Type *)i2c_addr(i2c_instance); // Initializing I2c clock i2c_clock_init(i2c); - if ((p_user_config->operating_mode == SL_I2C_FAST_PLUS_MODE) || (p_user_config->operating_mode == SL_I2C_HIGH_SPEED_MODE)) { if (i2c_instance == SL_I2C2) { @@ -179,7 +179,6 @@ sl_i2c_status_t sl_i2c_driver_init(sl_i2c_instance_t i2c_instance, const sl_i2c_ RSI_ULPSS_UlpProcClkConfig(ULPCLK, ULP_PROC_SOC_CLK, ULP_PRO_CLOCK_DIV_FACTOR, DELAY_DISABLE); } } - // Read the current M4 Core clock sl_si91x_clock_manager_m4_get_core_clk_src_freq(&config.freq); // Registering callback as per transfer type diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_ro_temperature_sensor.c b/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_ro_temperature_sensor.c deleted file mode 100644 index 10f2d145a..000000000 --- a/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_ro_temperature_sensor.c +++ /dev/null @@ -1,286 +0,0 @@ -/***************************************************************************/ /** - * @file sl_si91x_ro_temperature_sensor.c - * @brief RO temperature sensor API implementation - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_si91x_ro_temperature_sensor.h" -#include "rsi_ipmu.h" - -/******************************************************************************* - *************************** DEFINES / MACROS ******************************* - ******************************************************************************/ -#define SIGN_BIT_POSITION 10 // Temperature read in signed format bit -#define NOMINAL_TEMP 25 // Nominal temperature value -#define ARRAY_SIZE 31 // Array size -#define MSB_BIT_POSITION 31 // MSB bit for sign check -#define MAX_NOMINAL_VALUE 128 // Maximum nominal value -#define KNOWN_TEMP 255 // Known temperature -#define MAX_COUNT_VALUE 1024 // Maximum count value -#define NEG_VALUE 1.3437f // value multiplied for conversion to negative -/******************************************************************************* - *************************** Global VARIABLES ******************************** - ******************************************************************************/ - -/******************************************************************************* - *************************** LOCAL VARIABLES ******************************** - ******************************************************************************/ -static int16_t temp_decimal_value; - -/******************************************************************************* - ************************** Global function Definitions ******************** - ******************************************************************************/ - -/******************************************************************************* - ********************* LOCAL FUNCTION PROTOTYPES *************************** - ******************************************************************************/ -static void temp_conversion(uint32_t temp); - -/****************************************************************************** - * Sets the count of reference clock on which ptat clock counts. - *****************************************************************************/ -sl_status_t sl_si91x_ro_temperature_set_count(uint32_t count) -{ - sl_status_t status; - // Returns invalid parameter if count of reference count is greater than MAX_COUNT_VALUE - if (count > MAX_COUNT_VALUE) { - status = SL_STATUS_INVALID_PARAMETER; - } else { - // set the count of reference clock on which ptat clock counts - RSI_TS_SetCntFreez(MCU_TEMP, count); - status = SL_STATUS_OK; - } - return status; -} - -/****************************************************************************** - * Selects the reference clock (use RO kHz clock (or) MCU FSM clock) to the temperature sensor. - *****************************************************************************/ -sl_status_t sl_si91x_ro_temperature_select_reference_clock(sl_ro_reference_clock_t ref_clk) -{ - sl_status_t status; - // Returns invalid parameter if reference clock selection is not proper - if (ref_clk >= SL_RO_CLK_LAST) { - status = SL_STATUS_INVALID_PARAMETER; - } else { - // Selects the reference clock based on sl_ro_reference_clock_t selection - RSI_TS_RefClkSel(MCU_TEMP, ref_clk); - status = SL_STATUS_OK; - } - return status; -} - -/****************************************************************************** - * Used to enable/disable the temperature sensor. It is a self clearing register. - *****************************************************************************/ -sl_status_t sl_si91x_ro_temperature_enable(sl_ro_temperature_state_t state) -{ - sl_status_t status; - // Returns invalid parameter if other than enabling (or) disabling is choosen - if (state >= SL_RO_TEMPERATURE_LAST) { - status = SL_STATUS_INVALID_PARAMETER; - } else { - // Enable/Disable the sensor based on sl_ro_temperature_t selection - RSI_TS_Enable(MCU_TEMP, state); - status = SL_STATUS_OK; - } - return status; -} - -/****************************************************************************** - * Used to set the calibrated temperature value of the sensor. By default it is set to 25. - *****************************************************************************/ -sl_status_t sl_si91x_ro_temperature_nominal(uint32_t value) -{ - sl_status_t status; - // Returns invalid parameter if calibrated temperature value > MAX_NOMINAL_VALUE - if (value > MAX_NOMINAL_VALUE) { - status = SL_STATUS_INVALID_PARAMETER; - } else { - // Calibrates temperature value of sensor - RSI_TS_Config(MCU_TEMP, value); - status = SL_STATUS_OK; - } - return status; -} - -/****************************************************************************** - * Reads the temperature value in signed format. - *****************************************************************************/ -sl_status_t sl_si91x_ro_temperature_read(int32_t *temperature) -{ - sl_status_t status; - uint32_t temp_read, f2_count; - int32_t temp; - // Validates the null pointer, if true returns error code - if (temperature == NULL) { - status = SL_STATUS_NULL_POINTER; - } else { - // Reads the temperature from sensor - temp = (int32_t)RSI_TS_ReadTemp(MCU_TEMP); - if (temp & BIT(SIGN_BIT_POSITION)) { - // read the f2 count - f2_count = RSI_TS_GetPtatClkCnt(MCU_TEMP); - // subtract f2_nominal count from f2_count NOTE:configure the f2_nominal - // temp_read=(f2-f2_nominal) - temp_read = (f2_count - RSI_IPMU_RO_TsEfuse()); - if (temp_read & BIT(MSB_BIT_POSITION)) { - temp_conversion(temp_read); - // calculate the negative temperature - *temperature = (int32_t)(NOMINAL_TEMP - (temp_decimal_value * NEG_VALUE)); - } - } else { - *temperature = temp; - } - status = SL_STATUS_OK; - } - return status; -} - -/****************************************************************************** - * Enable/Disable bjt based temperature updation. - *****************************************************************************/ -sl_status_t sl_si91x_ro_temperature_based_update(sl_ro_temperature_update_t enable) -{ - sl_status_t status; - // Returns invalid parameter if temperature update based on RO is >= SL_RO_TEMP_BJT_UPDATE_LAST - if (enable >= SL_RO_TEMP_BJT_UPDATE_LAST) { - status = SL_STATUS_INVALID_PARAMETER; - } else { - // Enables the temperature update based on RO calculation - RSI_TS_RoBjtEnable(MCU_TEMP, enable); - status = SL_STATUS_OK; - } - return status; -} - -/****************************************************************************** - * Updation of RO temperature through SPI. - *****************************************************************************/ -sl_status_t sl_si91x_ro_temperature_load(uint8_t temperature) -{ - sl_status_t status; - // Returns invalid parameter if known temperature >= KNOWN_TEMP - if (temperature >= KNOWN_TEMP) { - status = SL_STATUS_INVALID_PARAMETER; - } else { - // Read the temperature value for spi based - RSI_TS_LoadBjt(MCU_TEMP, temperature); - status = SL_STATUS_OK; - } - return status; -} - -/****************************************************************************** - * Reads the count of f1 clock cycles. - *****************************************************************************/ -sl_status_t sl_si91x_ro_temperature_get_reference_clk_count(uint32_t *ref_count) -{ - sl_status_t status; - // Validates the null pointer, if true returns error code - if (ref_count == NULL) { - status = SL_STATUS_NULL_POINTER; - } else { - // Reads the f1 clock cycles count - *ref_count = RSI_TS_GetRefClkCnt(MCU_TEMP); - status = SL_STATUS_OK; - } - return status; -} - -/****************************************************************************** - * Reads the count of f2 clock cycles. - *****************************************************************************/ -sl_status_t sl_si91x_ro_temperature_get_ptat_clk_count(uint32_t *ptat_count) -{ - sl_status_t status; - // Validates the null pointer, if true returns error code - if (ptat_count == NULL) { - status = SL_STATUS_NULL_POINTER; - } else { - // Reads the f2 clock cycles count - *ptat_count = RSI_TS_GetPtatClkCnt(MCU_TEMP); - status = SL_STATUS_OK; - } - return status; -} - -/****************************************************************************** - * Updates the temperature periodically based on trigger time selected - *****************************************************************************/ -sl_status_t sl_si91x_ro_temperature_periodic_update(sl_ro_temperature_periodic_check_t periodic_check, - sl_ro_temperature_trigger_time_t trigger_time) -{ - sl_status_t status; - // Validates periodic and trigger times and if true returns error code - if ((periodic_check >= SL_RO_TEMPERATURE_PERIODIC_LAST) || (trigger_time >= SL_RO_TEMPERATURE_TRIGGER_LAST)) { - status = SL_STATUS_INVALID_PARAMETER; - } else { - // Updates the temperature periodically - RSI_Periodic_TempUpdate(TIME_PERIOD, periodic_check, trigger_time); - status = SL_STATUS_OK; - } - return status; -} - -/****************************************************************************** - * Two's complement conversion function - *****************************************************************************/ -static void temp_conversion(uint32_t temp) -{ - int16_t base = 1; - char binary[ARRAY_SIZE], ones_comp[ARRAY_SIZE], twos_comp[ARRAY_SIZE]; - uint8_t i = 0, rem, carry = 1; - uint8_t num = 0; - temp_decimal_value = 0, base = 1; - while (temp > 0) { - binary[i] = temp % 2; - temp = temp / 2; - i++; - } - for (i = 0; i < MSB_BIT_POSITION; i++) { - if (binary[i] == 0) - ones_comp[i] = 1; - else - ones_comp[i] = 0; - } - for (i = 0; i < MSB_BIT_POSITION; i++) { - if (ones_comp[i] == 1 && (carry == 1)) { - twos_comp[i] = 0; - } else if ((ones_comp[i] == 0) && (carry == 1)) { - twos_comp[i] = 1; - carry = 0; - } else { - twos_comp[i] = ones_comp[i]; - } - } - for (i = 0; i < MSB_BIT_POSITION; i++) { - num = twos_comp[i]; - rem = num % 10; - temp_decimal_value = (int16_t)(temp_decimal_value + rem * base); - base = base * 2; - } -} diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_sio.c b/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_sio.c deleted file mode 100644 index d9587fd72..000000000 --- a/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_sio.c +++ /dev/null @@ -1,1186 +0,0 @@ -/***************************************************************************/ /** -* @file sl_si91x_sio.c -* @brief SIO API implementation -******************************************************************************* -* # License -* Copyright 2023 Silicon Laboratories Inc. www.silabs.com -******************************************************************************* -* -* SPDX-License-Identifier: Zlib -* -* The licensor of this software is Silicon Laboratories Inc. -* -* This software is provided 'as-is', without any express or implied -* warranty. In no event will the authors be held liable for any damages -* arising from the use of this software. -* -* Permission is granted to anyone to use this software for any purpose, -* including commercial applications, and to alter it and redistribute it -* freely, subject to the following restrictions: -* -* 1. The origin of this software must not be misrepresented; you must not -* claim that you wrote the original software. If you use this software -* in a product, an acknowledgment in the product documentation would be -* appreciated but is not required. -* 2. Altered source versions must be plainly marked as such, and must not be -* misrepresented as being the original software. -* 3. This notice may not be removed or altered from any source distribution. -* -******************************************************************************/ -#include "sl_si91x_sio.h" -#include "sl_si91x_sio_config.h" -#include "sl_si91x_peripheral_gpio.h" -#include "rsi_rom_clks.h" -#include "clock_update.h" -/******************************************************************************* - *************************** LOCAL MACROS *********************************** - ******************************************************************************/ -#define CS_NUM_MIN 0 ///< Minimum chip select number -#define OUTPUT 1 ///< Output value set -#define CLOCK_TYPE 2 ///< Maximum types of clocks -#define PATTERN_MATCH 2 ///< Maximum pattern match number -#define FLOW_CONTROL 2 ///< Maximum flow control number -#define REVERSE_LOAD 2 ///< Maximum reverse load number -#define EDGE_SELECT 2 ///< Maximum edge select number -#define FLAG 3 ///< Maximum interrupt flag -#define ULP_PORT 4 ///< GPIO ULP port -#define ULP_MODE 6 ///< ULP GPIO mode -#define SIO_CHANNEL 7 ///< SIO maximum channel -#define CS_NUM_MAX 7 ///< Maximum chip select number -#define HOST_MIN 24 ///< GPIO host pad minimum pin number -#define HOST_MAX 31 ///< GPIO host pad maximum pin number -#define MAX_GPIO 64 ///< maximum GPIO pins -#define SIO_RELEASE_VERSION 0 ///< SIO Release version -#define SIO_SQA_VERSION 0 ///< SIO SQA version -#define SIO_DEV_VERSION 2 ///< SIO Developer version -#define SLI_SIO_INTERRUPT SIO_IRQn ///< SIO interrupt handler - -/******************************************************************************* - *************************** Global VARIABLES ******************************** - ******************************************************************************/ - -/******************************************************************************* - *************************** LOCAL VARIABLES ******************************** - ******************************************************************************/ -sl_sio_i2s_callback_t i2s_user_callback; -sl_sio_spi_callback_t spi_user_callback; -sl_sio_uart_callback_t uart_user_callback; -stc_sio_uart_config_t UartInitstc = { 0 }; - -/******************************************************************************* - ********************* LOCAL FUNCTION PROTOTYPES *************************** - ******************************************************************************/ -static sl_status_t convert_rsi_to_sl_error_code(rsi_error_t error); -static void callback_event_handler(en_sio_spi_events_t en_event); - -/******************************************************************************* - ************************** Global function Definitions ******************** - ******************************************************************************/ - -/******************************************************************************* - * This API initializes SIO gpio's and enables SIO module clock - ******************************************************************************/ -sl_status_t sl_si91x_sio_init(void) -{ - sl_status_t status; - rsi_error_t error_status; - // Initialize the SIO - error_status = RSI_SIO_Initialization(); - if (error_status == RSI_OK) { - status = SL_STATUS_OK; // Returns status OK if no error occurs - } else { - status = SL_STATUS_FAIL; // Returns status error code - } - return status; -} - -/******************************************************************************* - * This API is used to De-initialize SIO module - ******************************************************************************/ -void sl_si91x_sio_deinit(void) -{ - sl_si91x_sio_spi_unregister_event_callback(); - sl_si91x_sio_uart_unregister_event_callback(); - RSI_CLK_PeripheralClkDisable3(M4CLK, (SGPIO_PCLK_ENABLE)); -} - -/******************************************************************************* - * This API initializes SIO-SPI i.e SPI mode, bit length, bit order, SIO - * frequency and the SIO channels for the SPI transfer lines. The actions to be - * performed before SPI initialization is: - * - Initialize SIO using @ref sl_si91x_sio_init() API - ******************************************************************************/ -sl_status_t sl_si91x_sio_spi_init(sl_sio_spi_config_t *configuration) -{ -#if (SIO_UC == 1) - configuration = &pstcSpiConfigUc; -#endif - sl_status_t status; - rsi_error_t error_status; - do { - if (configuration == NULL) { - status = SL_STATUS_NULL_POINTER; // Returns null pointer status code - break; - } - // Initialize the SIO-SPI - error_status = RSI_SIO_InitSpi(SIO, configuration); - status = convert_rsi_to_sl_error_code(error_status); // Returns status code - } while (false); - return status; -} - -/******************************************************************************* - * This API is used for initialize sio spi pins and clock. The formal argument passed - * takes pointer to structure of type \ref sl_sio_uart_t. This holds the spi cs, clk, - * mosi, miso pins configuration. The members are assigned to SL macros defined in - * sl_sio_board.h. The SL macros are integrated to RTE macros present in RTE device file. - ******************************************************************************/ -sl_status_t sl_si91x_sio_spi_pin_initialization(sl_sio_spi_t *sio_spi_init) -{ - sl_status_t status; - do { - // Validates the null pointer, if true returns error code - if (sio_spi_init == NULL) { - status = SL_STATUS_NULL_POINTER; - break; - } - // sio spi chip select pin muxing - if (sio_spi_init->spi_cs_pin >= GPIO_MAX_PIN) { - sl_si91x_gpio_enable_ulp_pad_receiver((uint8_t)(sio_spi_init->spi_cs_pin - GPIO_MAX_PIN)); - sl_gpio_set_pin_mode(ULP_PORT, (uint8_t)(sio_spi_init->spi_cs_pin - GPIO_MAX_PIN), ULP_GPIO_MODE_6, OUTPUT); - } else { - sl_si91x_gpio_enable_pad_receiver(sio_spi_init->spi_cs_pin); - } - if (sio_spi_init->spi_cs_pin >= (HOST_PAD_GPIO_MIN - 1) && sio_spi_init->spi_cs_pin <= (HOST_PAD_GPIO_MAX + 1)) { - sl_si91x_gpio_enable_pad_selection(sio_spi_init->spi_cs_pin); - } else { - sl_si91x_gpio_enable_pad_selection(sio_spi_init->spi_cs_pad); - } - sl_gpio_set_pin_mode(sio_spi_init->spi_cs_port, sio_spi_init->spi_cs_pin, sio_spi_init->spi_cs_mux, OUTPUT); - // sio spi clock pin muxing - if (sio_spi_init->spi_clk_pin >= GPIO_MAX_PIN) { - sl_si91x_gpio_enable_ulp_pad_receiver((uint8_t)(sio_spi_init->spi_clk_pin - GPIO_MAX_PIN)); - sl_gpio_set_pin_mode(ULP_PORT, (uint8_t)(sio_spi_init->spi_clk_pin - GPIO_MAX_PIN), ULP_GPIO_MODE_6, OUTPUT); - } else { - sl_si91x_gpio_enable_pad_receiver(sio_spi_init->spi_clk_pin); - } - if (sio_spi_init->spi_clk_pin >= (HOST_PAD_GPIO_MIN - 1) && sio_spi_init->spi_clk_pin <= (HOST_PAD_GPIO_MAX + 1)) { - sl_si91x_gpio_enable_pad_selection(sio_spi_init->spi_clk_pin); - } else { - sl_si91x_gpio_enable_pad_selection(sio_spi_init->spi_clk_pad); - } - sl_gpio_set_pin_mode(sio_spi_init->spi_clk_port, sio_spi_init->spi_clk_pin, sio_spi_init->spi_clk_mux, OUTPUT); - // sio spi mosi pin muxing - if (sio_spi_init->spi_mosi_pin >= GPIO_MAX_PIN) { - sl_si91x_gpio_enable_ulp_pad_receiver((uint8_t)(sio_spi_init->spi_mosi_pin - GPIO_MAX_PIN)); - sl_gpio_set_pin_mode(ULP_PORT, (uint8_t)(sio_spi_init->spi_mosi_pin - GPIO_MAX_PIN), ULP_GPIO_MODE_6, OUTPUT); - } else { - sl_si91x_gpio_enable_pad_receiver(sio_spi_init->spi_mosi_pin); - } - if (sio_spi_init->spi_mosi_pin >= (HOST_PAD_GPIO_MIN - 1) - && sio_spi_init->spi_mosi_pin <= (HOST_PAD_GPIO_MAX + 1)) { - sl_si91x_gpio_enable_pad_selection(sio_spi_init->spi_mosi_pin); - } else { - sl_si91x_gpio_enable_pad_selection(sio_spi_init->spi_mosi_pad); - } - sl_gpio_set_pin_mode(sio_spi_init->spi_mosi_port, sio_spi_init->spi_mosi_pin, sio_spi_init->spi_mosi_mux, OUTPUT); - // sio spi miso pin muxing - if (sio_spi_init->spi_miso_pin >= GPIO_MAX_PIN) { - sl_si91x_gpio_enable_ulp_pad_receiver((uint8_t)(sio_spi_init->spi_miso_pin - GPIO_MAX_PIN)); - sl_gpio_set_pin_mode(ULP_PORT, (uint8_t)(sio_spi_init->spi_miso_pin - GPIO_MAX_PIN), ULP_GPIO_MODE_6, OUTPUT); - } else { - sl_si91x_gpio_enable_pad_receiver(sio_spi_init->spi_miso_pin); - } - if (sio_spi_init->spi_miso_pin >= (HOST_PAD_GPIO_MIN - 1) - && sio_spi_init->spi_miso_pin <= (HOST_PAD_GPIO_MAX + 1)) { - sl_si91x_gpio_enable_pad_selection(sio_spi_init->spi_miso_pin); - } else { - sl_si91x_gpio_enable_pad_selection(sio_spi_init->spi_miso_pad); - } - sl_gpio_set_pin_mode(sio_spi_init->spi_miso_port, sio_spi_init->spi_miso_pin, sio_spi_init->spi_miso_mux, OUTPUT); - // SIO CLock enable - RSI_SIO_ClockEnable(); - status = SL_STATUS_OK; - } while (false); - return status; -} - -/******************************************************************************* - * This API asserts the SIO SPI chip select - * The actions to be performed before SPI chip select assert are: - * - Initialize SIO using @ref sl_si91x_sio_init() API - * - Initialize SIO-SPI using @ref sl_si91x_sio_spi_init() API - ******************************************************************************/ -sl_status_t sl_si91x_sio_spi_cs_assert(uint8_t chip_select_num) -{ - sl_status_t status; - do { - if (chip_select_num > CS_NUM_MAX) { - // Returns invalid parameter status code if chip select > 7 - status = SL_STATUS_INVALID_PARAMETER; - break; - } - // Assert the SPI chip select - RSI_SIO_SpiCsAssert(SIO, chip_select_num); - status = SL_STATUS_OK; - } while (false); - return status; -} - -/******************************************************************************* - * This API de-asserts the SIO-SPI chip select - * The actions to be performed before SPI chip select de-assert are: - * - Initialize SIO using @ref sl_si91x_sio_init() API - * - Initialize SIO-SPI using @ref sl_si91x_sio_spi_init() API - * - Assert SIO chip select using @ref sl_si91x_sio_spi_cs_assert() API - * - Transfer data using @ref sl_si91x_sio_spi_transfer() API - ******************************************************************************/ -sl_status_t sl_si91x_sio_spi_cs_deassert(uint8_t chip_select_num) -{ - sl_status_t status; - do { - if (chip_select_num > CS_NUM_MAX) { - // Returns invalid parameter status code if chip select > 7 - status = SL_STATUS_INVALID_PARAMETER; - break; - } - // Deassert the SPI chip select - RSI_SIO_SpiCsDeAssert(SIO, chip_select_num); - status = SL_STATUS_OK; - } while (false); - return status; -} - -/******************************************************************************* - * This API is used to register the event callback. - * It registers the callback, i.e., stores the callback function address - * and pass to the variable that is called in Interrupt Handler. - * If another callback is registered without unregistering previous callback - * then, it returns an error code, so it is mandatory to unregister the callback - * before registering another callback. It will returns error if any callback is - * already registered. The actions to be performed before callback are: - * - Initialize SIO using @ref sl_si91x_sio_init() API - * - Initialize SIO-SPI using @ref sl_si91x_sio_spi_init() API - ******************************************************************************/ -sl_status_t sl_si91x_sio_spi_register_event_callback(sl_sio_spi_callback_t callback_event) -{ - sl_status_t status; - do { - // Validates the null pointer, if true returns error code - if (callback_event == NULL) { - status = SL_STATUS_NULL_POINTER; - break; - } - // To validate the function pointer if the parameters is not NULL then, it - // returns an error code - if (spi_user_callback != NULL) { - status = SL_STATUS_BUSY; - break; - } - // Enable the SIO interrupt - NVIC_EnableIRQ(SLI_SIO_INTERRUPT); - // User callback address is passed to the static variable which is called at - // the time of interrupt - spi_user_callback = callback_event; - // Returns SL_STATUS_OK if callback is successfully registered - status = SL_STATUS_OK; - } while (false); - return status; -} - -/******************************************************************************* - * It unregisters the callback, i.e., clear the callback function address - * and pass NULL value to the variable - ******************************************************************************/ -void sl_si91x_sio_spi_unregister_event_callback(void) -{ - // Pass the NULL value to the static variable which is called at the time of - // interrupt. - // It is further validated in register callback API. - spi_user_callback = NULL; - NVIC_DisableIRQ(SLI_SIO_INTERRUPT); -} - -/******************************************************************************* - * This API updates the callback function which in turns call the user callback - * API and used to make the SIO-SPI Transfer in non blocking mode. - * The actions to be performed before SPI transfer are: - * - Initialize SIO using @ref sl_si91x_sio_init() API - * - Initialize SIO-SPI using @ref sl_si91x_sio_spi_init() API - * - Assert SIO chip select using @ref sl_si91x_sio_spi_cs_assert() API - ******************************************************************************/ -sl_status_t sl_si91x_sio_spi_transfer(sl_sio_spi_xfer_config_t *xfer_config) -{ -#if (SIO_UC == 1) - xfer_config->u8BitLen = pstcSpiConfigUc.u8BitLen; -#endif - sl_status_t status; - rsi_error_t error_status; - do { - if (xfer_config == NULL) { - status = SL_STATUS_NULL_POINTER; // Returns null pointer status code - break; - } - // Update the callback function - xfer_config->pfnCb = callback_event_handler; - // Initiate the SIO data transfer - error_status = RSI_SIO_SpiTrasnfer(SIO, xfer_config); - status = convert_rsi_to_sl_error_code(error_status); - } while (false); - return status; -} - -/******************************************************************************* - * This API is a Static callback function for handling the callbacks - ******************************************************************************/ -static void callback_event_handler(en_sio_spi_events_t en_event) -{ - switch (en_event) { - // Handle SPI TX done event here - case SioSpiTxDone: - break; - // Handle SPI RX done event here - case SioSpiRxDone: - break; - } - spi_user_callback(en_event); - return; -} - -/******************************************************************************* - * This API is to validate the RSI error code. - * While calling the RSI APIs, it returns the RSI Error codes. - * This function converts the RSI error codes into SL error codes. - * It takes argument as RSI error type and returns the SL error type. - * It has a single switch statement which is mapped with the SL error code and - * after successful conversion it breaks the switch statement. - * If the error code is not listed, by default is SL_STATUS_FAIL. - ******************************************************************************/ -static sl_status_t convert_rsi_to_sl_error_code(rsi_error_t error) -{ - sl_status_t status; - switch (error) { - case RSI_OK: - status = SL_STATUS_OK; - break; - case INVALID_PARAMETERS: - status = SL_STATUS_INVALID_PARAMETER; - break; - case ERROR_INVALID_INPUT_FREQUENCY: - status = SL_STATUS_INVALID_PARAMETER; - break; - case ERROR_CLOCK_NOT_ENABLED: - status = SL_STATUS_NOT_INITIALIZED; - break; - default: - status = SL_STATUS_FAIL; - break; - } - return status; -} - -/******************************************************************************* - * This API is used to get the release, SQA and DEV version of SIO - * It returns the structure for SIO version. - * Structure includes three members: - * - Release version - * - SQA version - * - DEV version - ******************************************************************************/ -sl_sio_version_t sl_si91x_sio_get_version(void) -{ - sl_sio_version_t version; - version.minor = SIO_DEV_VERSION; - version.release = SIO_RELEASE_VERSION; - version.major = SIO_SQA_VERSION; - return version; -} - -/******************************************************************************* - * This API is used for initialize sio uart pins and clock. The formal argument passed - * takes pointer to structure of type \ref sl_sio_uart_t. This holds the uart tx, rx pins - * configuration. The members are assigned to SL macros defined in sl_sio_board.h. - * The SL macros are integrated to RTE macros present in RTE device file. - ******************************************************************************/ -sl_status_t sl_si91x_sio_uart_pin_initialization(sl_sio_uart_t *sio_uart_init) -{ - sl_status_t status; - do { - // Validates the null pointer, if true returns error code - if (sio_uart_init == NULL) { - status = SL_STATUS_NULL_POINTER; - break; - } - // sio uart tx pin muxing - if (sio_uart_init->uart_tx_pin >= GPIO_MAX_PIN) { - sl_si91x_gpio_enable_ulp_pad_receiver((uint8_t)(sio_uart_init->uart_tx_pin - GPIO_MAX_PIN)); - sl_gpio_set_pin_mode(ULP_PORT, (uint8_t)(sio_uart_init->uart_tx_pin - GPIO_MAX_PIN), ULP_GPIO_MODE_6, OUTPUT); - } else { - sl_si91x_gpio_enable_pad_receiver(sio_uart_init->uart_tx_pin); - } - if (sio_uart_init->uart_tx_pin >= (HOST_PAD_GPIO_MIN - 1) - && sio_uart_init->uart_tx_pin <= (HOST_PAD_GPIO_MAX + 1)) { - sl_si91x_gpio_enable_pad_selection(sio_uart_init->uart_tx_pin); - } else { - sl_si91x_gpio_enable_pad_selection(sio_uart_init->uart_tx_pad); - } - sl_gpio_set_pin_mode(sio_uart_init->uart_tx_port, sio_uart_init->uart_tx_pin, sio_uart_init->uart_tx_mux, OUTPUT); - // sio uart rx pin muxing - if (sio_uart_init->uart_rx_pin >= GPIO_MAX_PIN) { - sl_si91x_gpio_enable_ulp_pad_receiver((uint8_t)(sio_uart_init->uart_rx_pin - GPIO_MAX_PIN)); - sl_gpio_set_pin_mode(ULP_PORT, (uint8_t)(sio_uart_init->uart_rx_pin - GPIO_MAX_PIN), ULP_GPIO_MODE_6, OUTPUT); - } else { - sl_si91x_gpio_enable_pad_receiver(sio_uart_init->uart_rx_pin); - } - if (sio_uart_init->uart_rx_pin >= (HOST_PAD_GPIO_MIN - 1) - && sio_uart_init->uart_rx_pin <= (HOST_PAD_GPIO_MAX + 1)) { - sl_si91x_gpio_enable_pad_selection(sio_uart_init->uart_rx_pin); - } else { - sl_si91x_gpio_enable_pad_selection(sio_uart_init->uart_rx_pad); - } - sl_gpio_set_pin_mode(sio_uart_init->uart_rx_port, sio_uart_init->uart_rx_pin, sio_uart_init->uart_rx_mux, OUTPUT); - // SIO CLock enable - RSI_SIO_ClockEnable(); - status = SL_STATUS_OK; - } while (false); - return status; -} - -/******************************************************************************* - * This API is used for SIO-UART initialization i.e., setting baud rate, parity, - * channel selection, stop bits, data length. - * The actions to be performed before UART initialization is: - * - Initialize SIO using @ref sl_si91x_sio_init() API - ******************************************************************************/ -sl_status_t sl_si91x_sio_uart_init(sl_sio_uart_config_t *configuration) -{ -#if (SIO_UC == 1) - configuration = &UartInitstcUc; - UartInitstc = UartInitstcUc; -#endif - sl_status_t status; - rsi_error_t error_status; - configuration->pfn = uart_user_callback; - do { - if (configuration == NULL) { - status = SL_STATUS_NULL_POINTER; // Returns null pointer status code - break; - } - // Initialize the SIO-UART - error_status = RSI_SIO_UartInit(SIO, configuration); - status = convert_rsi_to_sl_error_code(error_status); - } while (false); - return status; -} - -/******************************************************************************* - * This API is used to send the data over SIO-UART. - * The actions to be performed before UART initialization is: - * - Initialize SIO using @ref sl_si91x_sio_init() API - * - Initialize SIO-UART using @ref sl_si91x_sio_uart_init() API - ******************************************************************************/ -sl_status_t sl_si91x_sio_uart_send(const void *buffer, uint16_t length) -{ - sl_status_t status; - rsi_error_t error_status; - do { - if (buffer == NULL) { - status = SL_STATUS_NULL_POINTER; // Returns null pointer status code - break; - } - // Send the data over UART - error_status = RSI_SIO_UARTSend(SIO, buffer, length); - status = convert_rsi_to_sl_error_code(error_status); - } while (false); - return status; -} - -/******************************************************************************* - * This API is used to write data in SIO-UART mode. - * The actions to be performed before UART initialization is: - * - Initialize SIO using @ref sl_si91x_sio_init() API - * - Initialize SIO-UART using @ref sl_si91x_sio_uart_init() API - ******************************************************************************/ -sl_status_t sl_si91x_sio_uart_send_blocking(const void *buffer, uint16_t length) -{ - sl_status_t status; - rsi_error_t error_status; - do { - if (buffer == NULL) { - status = SL_STATUS_NULL_POINTER; // Returns null pointer status code - break; - } - // write data in UART mode - error_status = RSI_SIO_UARTSendBlocking(SIO, buffer, length); - status = convert_rsi_to_sl_error_code(error_status); - } while (false); - return status; -} - -/******************************************************************************* - * This API is used to read data in UART mode. - * The actions to be performed before UART initialization is: - * - Initialize SIO using @ref sl_si91x_sio_init() API - * - Initialize SIO-UART using @ref sl_si91x_sio_uart_init() API - * - Send data using @ref sl_si91x_sio_uart_send() API(or) - * @ref sl_si91x_sio_uart_send_blocking() API - ******************************************************************************/ -sl_status_t sl_si91x_sio_uart_read(void *data_buffer, uint16_t num_bytes) -{ - sl_status_t status; - rsi_error_t error_status; - do { - if (data_buffer == NULL) { - status = SL_STATUS_NULL_POINTER; // Returns null pointer status code - break; - } - // Read data in UART mode - - error_status = RSI_SIO_UARTRead(SIO, data_buffer, num_bytes); - status = convert_rsi_to_sl_error_code(error_status); - } while (false); - return status; -} - -/******************************************************************************* - * This API is used to read data in UART blocking mode - * The actions to be performed before UART initialization is: - * - Initialize SIO using @ref sl_si91x_sio_init() API - * - Initialize SIO-UART using @ref sl_si91x_sio_uart_init() API - * - Send data using @ref sl_si91x_sio_uart_send() API(or) - * @ref sl_si91x_sio_uart_send_blocking() API - ******************************************************************************/ -sl_status_t sl_si91x_sio_uart_read_blocking(void *data_buffer, uint16_t num_bytes) -{ - sl_status_t status; - rsi_error_t error_status; - do { - if (data_buffer == NULL) { - status = SL_STATUS_NULL_POINTER; // Returns null pointer status code - break; - } - // Read data in UART blocking mode - error_status = RSI_SIO_UARTReadBlocking(SIO, data_buffer, num_bytes); - status = convert_rsi_to_sl_error_code(error_status); - } while (false); - return status; -} - -/******************************************************************************* - * This API is used to register the event callback. - * It registers the callback, i.e., stores the callback function address - * and pass to the variable that is called in Interrupt Handler. - * If another callback is registered without unregistering previous callback - * then, it returns an error code, so it is mandatory to unregister the callback - * before registering another callback. It will returns error if any callback is - * already registered. The actions to be performed before callback are: - * - Initialize SIO using @ref sl_si91x_sio_init() API - * - Initialize SIO-UART using @ref sl_si91x_sio_uart_init() API - ******************************************************************************/ -sl_status_t sl_si91x_sio_uart_register_event_callback(sl_sio_uart_callback_t callback_event) -{ - sl_status_t status; - do { - // Validates the null pointer, if true returns error code - if (callback_event == NULL) { - status = SL_STATUS_NULL_POINTER; - break; - } - // To validate the function pointer if the parameters is not NULL then, it - // returns an error code - if (uart_user_callback != NULL) { - status = SL_STATUS_BUSY; - break; - } - // Enable the SIO interrupt - NVIC_EnableIRQ(SLI_SIO_INTERRUPT); - // User callback address is passed to the static variable which is called at - // the time of interrupt - uart_user_callback = callback_event; - // Returns SL_STATUS_OK if callback is successfully registered - status = SL_STATUS_OK; - } while (false); - return status; -} - -/******************************************************************************* - * It unregisters the callback, i.e., clear the callback function address - * and pass NULL value to the variable - ******************************************************************************/ -void sl_si91x_sio_uart_unregister_event_callback(void) -{ - // Pass the NULL value to the static variable which is called at the time of - // interrupt. - // It is further validated in register callback API. - uart_user_callback = NULL; - NVIC_DisableIRQ(SLI_SIO_INTERRUPT); -} - -/******************************************************************************* - * This API is used when UART receive is done. - ******************************************************************************/ -void sl_si91x_sio_uart_rx_done(void) -{ - gstcSioCb.uart_sio.u16UartRxDone = 0; -} - -/******************************************************************************* - * This API is used for initialize sio i2c pins and clock. The formal argument passed - * takes pointer to structure of type \ref sl_sio_i2c_t. This holds the i2c sda, scl pins - * configuration. The members are assigned to SL macros defined in sl_sio_board.h. - * The SL macros are integrated to RTE macros present in RTE device file. - ******************************************************************************/ -sl_status_t sl_si91x_sio_i2c_pin_initialization(sl_sio_i2c_t *sio_i2c_init) -{ - sl_status_t status; - do { - // Validates the null pointer, if true returns error code - if (sio_i2c_init == NULL) { - status = SL_STATUS_NULL_POINTER; - break; - } - // sio i2c scl pin muxing - if (sio_i2c_init->i2c_scl_pin >= GPIO_MAX_PIN) { - sl_si91x_gpio_enable_ulp_pad_receiver((uint8_t)(sio_i2c_init->i2c_scl_pin - GPIO_MAX_PIN)); - sl_gpio_set_pin_mode(ULP_PORT, (uint8_t)(sio_i2c_init->i2c_scl_pin - GPIO_MAX_PIN), ULP_GPIO_MODE_6, OUTPUT); - } else { - sl_si91x_gpio_enable_pad_receiver(sio_i2c_init->i2c_scl_pin); - } - if (sio_i2c_init->i2c_scl_pin >= (HOST_PAD_GPIO_MIN - 1) && sio_i2c_init->i2c_scl_pin <= (HOST_PAD_GPIO_MAX + 1)) { - sl_si91x_gpio_enable_pad_selection(sio_i2c_init->i2c_scl_pin); - } else { - sl_si91x_gpio_enable_pad_selection(sio_i2c_init->i2c_scl_pad); - } - sl_gpio_set_pin_mode(sio_i2c_init->i2c_scl_port, sio_i2c_init->i2c_scl_pin, sio_i2c_init->i2c_scl_mux, OUTPUT); - // sio i2c sda pin muxing - if (sio_i2c_init->i2c_sda_pin >= GPIO_MAX_PIN) { - sl_si91x_gpio_enable_ulp_pad_receiver((uint8_t)(sio_i2c_init->i2c_sda_pin - GPIO_MAX_PIN)); - sl_gpio_set_pin_mode(ULP_PORT, (uint8_t)(sio_i2c_init->i2c_sda_pin - GPIO_MAX_PIN), ULP_GPIO_MODE_6, OUTPUT); - } else { - sl_si91x_gpio_enable_pad_receiver(sio_i2c_init->i2c_sda_pin); - } - if (sio_i2c_init->i2c_sda_pin >= (HOST_PAD_GPIO_MIN - 1) && sio_i2c_init->i2c_sda_pin <= (HOST_PAD_GPIO_MAX + 1)) { - sl_si91x_gpio_enable_pad_selection(sio_i2c_init->i2c_sda_pin); - } else { - sl_si91x_gpio_enable_pad_selection(sio_i2c_init->i2c_sda_pad); - } - sl_gpio_set_pin_mode(sio_i2c_init->i2c_sda_port, sio_i2c_init->i2c_sda_pin, sio_i2c_init->i2c_sda_mux, OUTPUT); - // SIO CLock enable - RSI_SIO_ClockEnable(); - status = SL_STATUS_OK; - } while (false); - return status; -} - -/******************************************************************************* - * This API is used to write the data over SIO-I2C. - * The actions to be performed before I2C write are: - * - Initialize SIO using @ref sl_si91x_sio_init() API - * - I2C generate start using @ref sl_si91x_sio_i2c_generate_start() API - ******************************************************************************/ -sl_status_t sl_si91x_sio_i2c_write(stc_sio_i2c_config_t *configuration, uint8_t address, uint8_t *data, uint16_t length) -{ - sl_status_t status; - rsi_error_t error_status; -#if (SIO_UC == 1) - configuration = &i2cConfigUc; -#endif - do { - // Returns null pointer status code - if (configuration == NULL) { - status = SL_STATUS_NULL_POINTER; - break; - } - // Write data over I2C - error_status = RSI_SIO_I2cWrite(SIO, configuration, address, data, length); - status = convert_rsi_to_sl_error_code(error_status); - } while (false); - return status; -} - -/******************************************************************************* - * This API is used to read the data over SIO-I2C. - * The actions to be performed before I2C read are: - * - Initialize SIO using @ref sl_si91x_sio_init() API - * - I2C generate start using @ref sl_si91x_sio_i2c_generate_start() API - * - Write data using @ref sl_si91x_sio_i2c_write() API - * (OR) @ref sl_si91x_sio_i2c_transfer() API - ******************************************************************************/ -sl_status_t sl_si91x_sio_i2c_read(stc_sio_i2c_config_t *configuration, uint8_t address, uint8_t *data, uint16_t length) -{ - sl_status_t status; - rsi_error_t error_status; -#if (SIO_UC == 1) - configuration = &i2cConfigUc; -#endif - do { - // Returns null pointer status code - if (configuration == NULL) { - status = SL_STATUS_NULL_POINTER; - break; - } - // Read data over I2C - error_status = RSI_SIO_I2cRead(SIO, configuration, address, data, length); - status = convert_rsi_to_sl_error_code(error_status); - } while (false); - return status; -} - -/******************************************************************************* - * This API is used to transfer the data over SIO-I2C. - * The actions to be performed before I2C transfer are: - * - Initialize SIO using @ref sl_si91x_sio_init() API - * - I2C generate start using @ref sl_si91x_sio_i2c_generate_start() API - ******************************************************************************/ -sl_status_t sl_si91x_sio_i2c_transfer(stc_sio_i2c_config_t *configuration, - uint8_t address, - uint8_t *tx_buffer, - uint16_t tx_length, - uint8_t *rx_buffer, - uint16_t rx_length) -{ -#if (SIO_UC == 1) - configuration = &i2cConfigUc; -#endif - sl_status_t status; - rsi_error_t error_status; - do { - // Returns null pointer status code - if (configuration == NULL) { - status = SL_STATUS_NULL_POINTER; - break; - } - // Transfer data over I2C - error_status = RSI_SIO_I2cTransfer(SIO, configuration, address, tx_buffer, tx_length, rx_buffer, rx_length); - status = convert_rsi_to_sl_error_code(error_status); - } while (false); - return status; -} - -/******************************************************************************* - * This API is used for i2c generate start over SIO-I2C. - * The actions to be performed before I2C generate start is: - * - Initialize SIO using @ref sl_si91x_sio_init() API - ******************************************************************************/ -void sl_si91x_sio_i2c_generate_start(void) -{ - RSI_SIO_I2cGenerateStart(SIO); -} - -/******************************************************************************* - * This API is used for i2c generate stop over SIO-I2C. - * The actions to be performed before i2c generate stop are: - * - Initialize SIO using @ref sl_si91x_sio_init() API - * - I2C generate start using @ref sl_si91x_sio_i2c_generate_start() API - * - Write data using @ref sl_si91x_sio_i2c_write() API - * (OR) @ref sl_si91x_sio_i2c_transfer() API - ******************************************************************************/ -void sl_si91x_sio_i2c_generate_stop(void) -{ - RSI_SIO_I2cGenerateStop(SIO); -} - -/******************************************************************************* - * This API is used for configure gpio interrupt. - * The actions to be performed before configuring interrupt is: - * - Initialize SIO using @ref sl_si91x_sio_init() API - ******************************************************************************/ -sl_status_t sl_si91x_sio_configure_interrupt(en_sio_channels_t channel, interrupt_flag_t flag) -{ - sl_status_t status; - do { - // Returns invalid parameter status code if channel > 7 and flag > 3 - if ((channel > SIO_CHANNEL) || (flag > FLAG)) { - status = SL_STATUS_INVALID_PARAMETER; - break; - } - RSI_SIO_Configure_Interrupt(SIO, channel, flag); - status = SL_STATUS_OK; - } while (false); - return status; -} - -/******************************************************************************* - * This API is used to match the pattern with data to be detected - * When pattern match bit is enabled, pattern match register should be - * programmed with data pattern to be detected. - * Pattern mask register to be programmed with valid bits to match. - * The actions to be performed before pattern match is: - * - Initialize SIO using @ref sl_si91x_sio_init() API - ******************************************************************************/ -sl_status_t sl_si91x_sio_match_pattern(en_sio_channels_t channel, - pattern_match_t pattern, - uint8_t slice, - uint32_t slice_pattern) -{ - sl_status_t status; - do { - // Returns invalid parameter status code if channel > 7 and pattern > 1 - if ((channel > SIO_CHANNEL) || (pattern >= PATTERN_MATCH)) { - status = SL_STATUS_INVALID_PARAMETER; - break; - } - RSI_SIO_Match_Pattern(SIO, channel, pattern, slice, slice_pattern); - status = SL_STATUS_OK; - } while (false); - return status; -} - -/******************************************************************************* - * This API is used to generate shift clock - * The actions to be performed before shift clock is: - * - Initialize SIO using @ref sl_si91x_sio_init() API - ******************************************************************************/ -sl_status_t sl_si91x_sio_shift_clock(uint32_t divider, en_sio_channels_t channel) -{ - sl_status_t status; - do { - // Returns invalid parameter status code if channel > 7 - if (channel > SIO_CHANNEL) { - status = SL_STATUS_INVALID_PARAMETER; - break; - } - RSI_SIO_Shift_Clock(SIO, divider, channel); - status = SL_STATUS_OK; - } while (false); - return status; -} - -/******************************************************************************* - * This API is used to select internal/external clock - * When external clock is used, shift/capture happens one system clock - * after the external clock edge - * The actions to be performed before select clock is: - * - Initialize SIO using @ref sl_si91x_sio_init() API - ******************************************************************************/ -sl_status_t sl_si91x_sio_select_clock(en_sio_channels_t channel, clock_type_t clock) -{ - sl_status_t status; - do { - // Returns invalid parameter status code if channel > 7 and clock > 1 - if ((channel > SIO_CHANNEL) || (clock >= CLOCK_TYPE)) { - status = SL_STATUS_INVALID_PARAMETER; - break; - } - RSI_SIO_Select_Clock(SIO, channel, clock); - status = SL_STATUS_OK; - } while (false); - return status; -} - -/******************************************************************************* - * This API is used to shift number of bits - * No. of shifts to happen before reloading the shift register with data/pausing - * the operation. i.e. value to be set = (total no. of valid bits in shift - * register/ number of bits per shift) – 1 The actions to be performed are: - * - Initialize SIO using @ref sl_si91x_sio_init() API - ******************************************************************************/ -sl_status_t sl_si91x_sio_position_counter(en_sio_channels_t channel, uint32_t data_shift) -{ - sl_status_t status; - do { - // Returns invalid parameter status code if channel > 7 - if (channel > SIO_CHANNEL) { - status = SL_STATUS_INVALID_PARAMETER; - break; - } - RSI_SIO_Position_Counter(SIO, channel, data_shift); - status = SL_STATUS_OK; - } while (false); - return status; -} - -/******************************************************************************* - * This API is used to enable/disable flow control bit. If flow control - * disabled, Data shifting continues even when data in shift register is not - * valid. Counters keep moving. If flow control is enabled, Counters and shift - * operations pause when data is not available. - * The actions to be performed are: - * - Initialize SIO using @ref sl_si91x_sio_init() API - ******************************************************************************/ -sl_status_t sl_si91x_sio_control_flow(en_sio_channels_t channel, flow_control_t flow_control) -{ - sl_status_t status; - do { - // Returns invalid parameter status code if channel > 7 and flow_control > 1 - if ((channel > SIO_CHANNEL) || (flow_control >= FLOW_CONTROL)) { - status = SL_STATUS_INVALID_PARAMETER; - break; - } - RSI_SIO_Control_Flow(SIO, channel, flow_control); - status = SL_STATUS_OK; - } while (false); - return status; -} - -/******************************************************************************* - * This API is used to load data to buffer in reverse order - * When set, the data on APB is loaded to buffer is reverse order. If the - * requirement is to shift out the MSB first, this has to be enabled. - * The actions to be performed are: - * - Initialize SIO using @ref sl_si91x_sio_init() API - ******************************************************************************/ -sl_status_t sl_si91x_sio_reverse_load(en_sio_channels_t channel, reverse_load_t reverse) -{ - sl_status_t status; - do { - // Returns invalid parameter status code if channel > 7 and reverse > 1 - if ((channel > SIO_CHANNEL) || (reverse >= REVERSE_LOAD)) { - status = SL_STATUS_INVALID_PARAMETER; - break; - } - RSI_SIO_Reverse_Load(SIO, channel, reverse); - status = SL_STATUS_OK; - } while (false); - return status; -} - -/******************************************************************************* - * This API is used for common swap interrupt enable set - * Common swap interrupt enable set register for all SIOs. Each bit - * corresponds to one SIO. When '1' is written, swap interrupt - * enable gets set. Interrupt would be raised if not masked and interrupt - * status would be reflected in interrupt status register. - * The actions to be performed are: - * - Initialize SIO using @ref sl_si91x_sio_init() API - ******************************************************************************/ -sl_status_t sl_si91x_sio_set_interrupt(en_sio_channels_t channel) -{ - sl_status_t status; - do { - // Returns invalid parameter status code if channel > 7 - if (channel > SIO_CHANNEL) { - status = SL_STATUS_INVALID_PARAMETER; - break; - } - RSI_SIO_Set_Interrupt(SIO, channel); - status = SL_STATUS_OK; - } while (false); - return status; -} - -/******************************************************************************* - * This API is used for common swap interrupt enable clear - * Common swap interrupt enable clear register for all SIOs. Each bit - * corresponds to one SIO. When '1' is written, swap interrupt - * enable gets cleared. Interrupt would not be raised and interrupt status - * would not be reflected in interrupt status register. - * The actions to be performed are: - * - Initialize SIO using @ref sl_si91x_sio_init() API - ******************************************************************************/ -sl_status_t sl_si91x_sio_clear_interrupt(en_sio_channels_t channel) -{ - sl_status_t status; - do { - // Returns invalid parameter status code if channel > 7 - if (channel > SIO_CHANNEL) { - status = SL_STATUS_INVALID_PARAMETER; - break; - } - RSI_SIO_Clear_Interrupt(SIO, channel); - status = SL_STATUS_OK; - } while (false); - return status; -} - -/******************************************************************************* - * This API is used for common swap interrupt mask set - * The actions to be performed are: - * - Initialize SIO using @ref sl_si91x_sio_init() API - ******************************************************************************/ -sl_status_t sl_si91x_sio_mask_interrupt(en_sio_channels_t channel) -{ - sl_status_t status; - do { - // Returns invalid parameter status code if channel > 7 - if (channel > SIO_CHANNEL) { - status = SL_STATUS_INVALID_PARAMETER; - break; - } - RSI_SIO_Mask_Interrupt(SIO, channel); - status = SL_STATUS_OK; - } while (false); - return status; -} - -/******************************************************************************* - * This API is used for common swap interrupt mask clear - * The actions to be performed are: - * - Initialize SIO using @ref sl_si91x_sio_init() API - ******************************************************************************/ -sl_status_t sl_si91x_sio_unmask_interrupt(en_sio_channels_t channel) -{ - sl_status_t status; - do { - // Returns invalid parameter status code if channel > 7 - if (channel > SIO_CHANNEL) { - status = SL_STATUS_INVALID_PARAMETER; - break; - } - RSI_SIO_UnMask_Interrupt(SIO, channel); - status = SL_STATUS_OK; - } while (false); - return status; -} - -/******************************************************************************* - * This API is used to read common swap interrupt status - * The actions to be performed are: - * - Initialize SIO using @ref sl_si91x_sio_init() API - ******************************************************************************/ -uint32_t sl_si91x_sio_get_interrupt_status(void) -{ - return RSI_SIO_Get_Interrupt_Status(SIO); -} - -/******************************************************************************* - * This API is used for common shift interrupt enable set - * Common shift interrupt enable set register for all SIOs. Each bit - * corresponds to one SIO. When '1' is written, shift interrupt - * enable gets set. Interrupt would be raised if not masked and interrupt - * status would be reflected in interrupt status register. - * The actions to be performed are: - * - Initialize SIO using @ref sl_si91x_sio_init() API - ******************************************************************************/ -sl_status_t sl_si91x_sio_set_shift_interrupt(en_sio_channels_t channel) -{ - sl_status_t status; - do { - // Returns invalid parameter status code if channel > 7 - if (channel > SIO_CHANNEL) { - status = SL_STATUS_INVALID_PARAMETER; - break; - } - RSI_SIO_Set_Shift_Interrupt(SIO, channel); - status = SL_STATUS_OK; - } while (false); - return status; -} - -/******************************************************************************* - * This API is used for common shift interrupt enable clear - * Common shift interrupt enable clear register for all SIOs. Each bit - * corresponds to one SIO. When '1' is written, shift interrupt - * enable gets cleared. Interrupt would not be raised and interrupt status - * would not be reflected in interrupt status register. - * The actions to be performed are: - * - Initialize SIO using @ref sl_si91x_sio_init() API - ******************************************************************************/ -sl_status_t sl_si91x_sio_clear_shift_interrupt(en_sio_channels_t channel) -{ - sl_status_t status; - do { - // Returns invalid parameter status code if channel > 7 - if (channel > SIO_CHANNEL) { - status = SL_STATUS_INVALID_PARAMETER; - break; - } - RSI_SIO_Clear_Shift_Interrupt(SIO, channel); - status = SL_STATUS_OK; - } while (false); - return status; -} - -/******************************************************************************* - * This API is used for common shift interrupt mask set - * The actions to be performed are: - * - Initialize SIO using @ref sl_si91x_sio_init() API - ******************************************************************************/ -sl_status_t sl_si91x_sio_mask_shift_interrupt(en_sio_channels_t channel) -{ - sl_status_t status; - do { - // Returns invalid parameter status code if channel > 7 - if (channel > SIO_CHANNEL) { - status = SL_STATUS_INVALID_PARAMETER; - break; - } - RSI_SIO_Mask_Shift_Interrupt(SIO, channel); - status = SL_STATUS_OK; - } while (false); - return status; -} - -/******************************************************************************* - * This API is used for common shift interrupt mask clear - * The actions to be performed are: - * - Initialize SIO using @ref sl_si91x_sio_init() API - ******************************************************************************/ -sl_status_t sl_si91x_sio_unmask_shift_interrupt(en_sio_channels_t channel) -{ - sl_status_t status; - do { - // Returns invalid parameter status code if channel > 7 - if (channel > SIO_CHANNEL) { - status = SL_STATUS_INVALID_PARAMETER; - break; - } - RSI_SIO_UnMask_Shift_Interrupt(SIO, channel); - status = SL_STATUS_OK; - } while (false); - return status; -} - -/******************************************************************************* - * This API is used to read common shift interrupt status - * The actions to be performed are: - * - Initialize SIO using @ref sl_si91x_sio_init() API - ******************************************************************************/ -uint32_t sl_si91x_sio_shift_interrupt_status(void) -{ - return RSI_SIO_Shift_Interrupt_Status(SIO); -} - -/******************************************************************************* - * This API is used to select edge of the clock cycle for sampling bits - * The actions to be performed are: - * - Initialize SIO using @ref sl_si91x_sio_init() API - ******************************************************************************/ -sl_status_t sl_si91x_sio_edge_select(en_sio_channels_t channel, edge_select_t edge_sel) -{ - sl_status_t status; - do { - // Returns invalid parameter status code if channel > 7 and edge_sel > 1 - if ((channel > SIO_CHANNEL) || (edge_sel >= EDGE_SELECT)) { - status = SL_STATUS_INVALID_PARAMETER; - break; - } - RSI_SIO_Edge_Select(SIO, channel, edge_sel); - status = SL_STATUS_OK; - } while (false); - return status; -} - -/******************************************************************************* - * This API is used to read sio buffer register - * The actions to be performed are: - * - Initialize SIO using @ref sl_si91x_sio_init() API - * - Initialize SPI using @ref sl_si91x_sio_spi_init() API for SIO-SPI - * - Initialize UART using @ref sl_si91x_sio_uart_init() API for SIO-UART - ******************************************************************************/ -uint32_t sl_si91x_sio_read_buffer(en_sio_channels_t channel) -{ - return RSI_SIO_Read_Buffer(SIO, channel); -} - -/******************************************************************************* - * This API is used to write into sio buffer register - * The actions to be performed are: - * - Initialize SIO using @ref sl_si91x_sio_init() API - * - Initialize SPI using @ref sl_si91x_sio_spi_init() API for SIO-SPI - * - Initialize UART using @ref sl_si91x_sio_uart_init() API for SIO-UART - ******************************************************************************/ -sl_status_t sl_si91x_sio_write_buffer(en_sio_channels_t channel, uint32_t data) -{ - sl_status_t status; - do { - // Returns invalid parameter status code if channel > 7 - if (channel > SIO_CHANNEL) { - status = SL_STATUS_INVALID_PARAMETER; - break; - } - RSI_SIO_Write_Buffer(SIO, channel, data); - status = SL_STATUS_OK; - } while (false); - return status; -} diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_ssi.c b/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_ssi.c index f3690ae44..37c910cab 100644 --- a/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_ssi.c +++ b/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_ssi.c @@ -47,12 +47,12 @@ #define MIN_BIT_WIDTH 4 // Minimum Bit width #define MAX_SLAVE_BIT_WIDTH 16 // Maximum Slave Bit width #define MAX_BIT_WIDTH 16 // Maximum Bit width +#define MAX_INSTANCE 3 // Maximum SSI Instance /******************************************************************************* *************************** LOCAL VARIABLES ******************************* ******************************************************************************/ -static const void *local_ssi_handle = NULL; -static sl_ssi_signal_event_t user_callback = NULL; +static sl_ssi_signal_event_t user_callback[] = { NULL, NULL, NULL }; extern sl_ssi_driver_t Driver_SSI_MASTER; extern sl_ssi_driver_t Driver_SSI_SLAVE; extern sl_ssi_driver_t Driver_SSI_ULP_MASTER; @@ -72,6 +72,7 @@ static void callback_event_handler(uint32_t event); static void sl_ssi_set_receive_sample_delay(sl_ssi_handle_t ssi_handle, uint32_t sample_delay); static boolean_t validate_ssi_handle(sl_ssi_handle_t ssi_handle); static sl_status_t sli_si91x_ssi_configure_power_mode(sl_ssi_handle_t ssi_handle, sl_ssi_power_state_t state); +static uint8_t convert_handle_to_instance(sl_ssi_handle_t ssi_handle); /******************************************************************************* **********************  Local Function Definition**************************** @@ -176,8 +177,10 @@ sl_status_t sl_si91x_ssi_deinit(sl_ssi_handle_t ssi_handle) status = SL_STATUS_INVALID_PARAMETER; break; } - // Unregister the user callback function. - user_callback = NULL; + // Getting the instance number from the input handle + uint8_t instance = convert_handle_to_instance(ssi_handle); + // NULL is passed to the callback function pointer of instance which is deinitialized + user_callback[instance] = NULL; error_status = ((sl_ssi_driver_t *)ssi_handle)->Uninitialize(); status = convert_arm_to_sl_error_code(error_status); @@ -554,16 +557,17 @@ sl_status_t sl_si91x_ssi_register_event_callback(sl_ssi_handle_t ssi_handle, sl_ status = SL_STATUS_INVALID_PARAMETER; break; } + // Getting the instance number from the input handle + uint8_t instance = convert_handle_to_instance(ssi_handle); // To validate the function pointer if the parameters is not NULL then, it // returns an error code - if ((user_callback != NULL) || (local_ssi_handle != NULL)) { + if (user_callback[instance] != NULL) { status = SL_STATUS_BUSY; break; } // User callback address is passed to the static variable which is called at the time of // interrupt - user_callback = callback_event; - local_ssi_handle = ssi_handle; + user_callback[instance] = callback_event; // Returns SL_STATUS_OK if callback is successfully registered status = SL_STATUS_OK; } while (false); @@ -580,8 +584,10 @@ void sl_si91x_ssi_unregister_event_callback(void) // Pass the NULL value to the static variable which is called at the time of // interrupt. // It is further validated in register callback API. - user_callback = NULL; - local_ssi_handle = NULL; + for (int i = 0; i < MAX_INSTANCE; i++) { + // Clearing all the three instance callbacks + user_callback[i] = NULL; + } } /******************************************************************************* @@ -731,9 +737,26 @@ uint32_t sl_si91x_ssi_get_receiver_sample_delay(sl_ssi_handle_t ssi_handle) static void callback_event_handler(uint32_t event) { + uint8_t ssi_instance = 0; + ARM_DRIVER_SPI *handle = NULL; + // Extracting the instance number from the event variable + ssi_instance = (uint8_t)(event >> SSI_INSTANCE_BIT); + if (ssi_instance == SSI_MASTER_INSTANCE) { + // assigning local handle to the master mode address + handle = &Driver_SSI_MASTER; + } else if (ssi_instance == SSI_SLAVE_INSTANCE) { + // assigning local handle to the slave mode address + handle = &Driver_SSI_SLAVE; + } else if (ssi_instance == SSI_ULP_MASTER_INSTANCE) { + // assigning local handle to the ulp master mode address + handle = &Driver_SSI_ULP_MASTER; + } + // Clearing the instance number to evaluate the event + event &= SSI_INSTANCE_MASK; switch (event) { case SSI_EVENT_TRANSFER_COMPLETE: - ((sl_ssi_driver_t *)local_ssi_handle)->Control(ARM_SPI_CONTROL_SS, ARM_SPI_SS_INACTIVE); + // Disabling the slave select line after the transfer complete + handle->Control(ARM_SPI_CONTROL_SS, ARM_SPI_SS_INACTIVE); break; case SSI_EVENT_DATA_LOST: // Occurs in slave mode when data is requested/sent by master @@ -748,7 +771,8 @@ static void callback_event_handler(uint32_t event) default: break; } - user_callback(event); + // Calling the callback as per the instance + user_callback[ssi_instance](event); } /******************************************************************************* @@ -899,3 +923,30 @@ static boolean_t validate_ssi_handle(sl_ssi_handle_t ssi_handle) } return status; } + +/******************************************************************************* + * Internal function to convert ssi handle to the instance number. + * + * @param[in] ssi handle. + * @return instance, 0,1,2 for master, slave and ulp master respectively + * +*******************************************************************************/ +static uint8_t convert_handle_to_instance(sl_ssi_handle_t ssi_handle) +{ + uint8_t instance = 0; + do { + if (ssi_handle == &Driver_SSI_MASTER) { + instance = SSI_MASTER_INSTANCE; + break; + } + if (ssi_handle == &Driver_SSI_SLAVE) { + instance = SSI_SLAVE_INSTANCE; + break; + } + if (ssi_handle == &Driver_SSI_ULP_MASTER) { + instance = SSI_ULP_MASTER_INSTANCE; + break; + } + } while (false); + return instance; +} diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_usart.c b/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_usart.c index f24a8681f..7207c6861 100644 --- a/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_usart.c +++ b/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_usart.c @@ -663,6 +663,8 @@ sl_status_t sl_si91x_usart_set_configuration(sl_usart_handle_t usart_handle, uint32_t input_mode = false; sl_si91x_usart_control_config_t control_config[NO_OF_UART_INSTANCES]; usart_peripheral_t uart_instance; + (void)control_config; + (void)uart_instance; /* USART_UC is defined by default. when this macro (USART_UC) is defined, peripheral * configuration is directly taken from the configuration set in the universal configuration (UC). diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_watchdog_timer.c b/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_watchdog_timer.c index e1d0ce9ea..6711c8532 100644 --- a/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_watchdog_timer.c +++ b/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_watchdog_timer.c @@ -28,8 +28,9 @@ * ******************************************************************************/ #include "sl_si91x_watchdog_timer.h" +#ifndef SL_WDT_MANAGER_PRESENT #include "sl_si91x_watchdog_timer_config.h" - +#endif #include "rsi_rtc.h" /******************************************************************************* *************************** DEFINES / MACROS ******************************** @@ -136,9 +137,9 @@ sl_status_t sl_si91x_watchdog_configure_clock(watchdog_timer_clock_config_t *tim * @brief: Configures watchdog-timer parameters * * @details: -* Sets interrupt timeout time (with default value '15' for 1-secs delay) -* Sets system reset time (with default value '17' for 4-secs delay) -* Sets system window time (with default value 0) +* Sets interrupt timeout time +* Sets system reset time +* Sets system window time *******************************************************************************/ sl_status_t sl_si91x_watchdog_set_configuration(watchdog_timer_config_t *timer_config_ptr) { @@ -165,9 +166,8 @@ sl_status_t sl_si91x_watchdog_set_configuration(watchdog_timer_config_t *timer_c status = SL_STATUS_INVALID_PARAMETER; break; } - // Comparing time values with each other - if ((timer_config_ptr->system_reset_time <= timer_config_ptr->interrupt_time) - || (timer_config_ptr->interrupt_time <= timer_config_ptr->window_time)) { + // Comparing interrupt time with window time + if (timer_config_ptr->interrupt_time <= timer_config_ptr->window_time) { status = SL_STATUS_INVALID_CONFIGURATION; break; } @@ -230,8 +230,6 @@ sl_status_t sl_si91x_watchdog_register_timeout_callback(watchdog_timer_callback_ * timer restart. * * Number of clock pulses for timer timeout = 2^(interrupt_time) -* -* This value should be less than system-reset time. *******************************************************************************/ sl_status_t sl_si91x_watchdog_set_interrupt_time(time_delays_t interrupt_time) { @@ -243,11 +241,6 @@ sl_status_t sl_si91x_watchdog_set_interrupt_time(time_delays_t interrupt_time) status = SL_STATUS_INVALID_PARAMETER; break; } - // Validating interrupt time as per system reset time value - if (RSI_WWDT_GetSysRstTime(MCU_WDT) <= interrupt_time) { - status = SL_STATUS_INVALID_CONFIGURATION; - break; - } // Validating interrupt time as per window time value if (RSI_WWDT_GetWindowTime(MCU_WDT) >= interrupt_time) { status = SL_STATUS_INVALID_CONFIGURATION; @@ -312,9 +305,8 @@ sl_status_t sl_si91x_watchdog_set_window_time(time_delays_t window_time) * 'WWD_SYSTEM_RESET_TIMER' register (5-bit), so its maximum value is 31. * * It is used to calculate clock pulse count of FSM clock, to reset the system -* Number of clock pulses for system reset delay = 2^(system_reset_time) -* -* This value should be greater than timer interrupt time. +* Number of clock pulses for system reset delay = 2^(system_reset_time) +* This value should be greater than timer window time. *******************************************************************************/ sl_status_t sl_si91x_watchdog_set_system_reset_time(time_delays_t system_reset_time) { @@ -326,11 +318,6 @@ sl_status_t sl_si91x_watchdog_set_system_reset_time(time_delays_t system_reset_t status = SL_STATUS_INVALID_PARAMETER; break; } - // Validating system-reset time as per interrupt time value - if (RSI_WWDT_GetIntrTime(MCU_WDT) >= system_reset_time) { - status = SL_STATUS_INVALID_CONFIGURATION; - break; - } // Validating system reset time as per window time value if (RSI_WWDT_GetWindowTime(MCU_WDT) >= system_reset_time) { status = SL_STATUS_INVALID_CONFIGURATION; diff --git a/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc/sl_si91x_gpio_common.h b/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc/sl_si91x_gpio_common.h index 9e695318a..250dcff17 100644 --- a/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc/sl_si91x_gpio_common.h +++ b/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc/sl_si91x_gpio_common.h @@ -143,7 +143,11 @@ extern "C" { : port == 2 ? ((pin > GPIO_PC_PIN_MAX_VALIDATE) ? 0 : 1) \ : port == 3 ? ((pin > GPIO_PD_PIN_MAX_VALIDATE) ? 0 : 1) \ : 0) - +///< Validate GPIO host pad port and pin +#define SL_GPIO_VALIDATE_HOST_PIN(port, pin) \ + (port == SL_GPIO_PORT_A ? (((pin >= HOST_PAD_MIN) && (pin <= HOST_PAD_MAX)) ? TRUE : FALSE) \ + : port == SL_GPIO_PORT_B ? (((pin >= GPIO_PIN_NUMBER9) && (pin <= GPIO_PIN_NUMBER14)) ? TRUE : FALSE) \ + : FALSE) #define SL_GPIO_VALIDATE_ULP_PORT_PIN(port, pin) (port == 4 ? ((pin > 11) ? 0 : 1) : 0) ///< Validate ULP port and pin #define SL_GPIO_VALIDATE_UULP_PORT_PIN(port, pin) (port == 5 ? ((pin > 5) ? 0 : 1) : 0) ///< Validate UULP port and pin diff --git a/components/device/silabs/si91x/mcu/hal/inc/rsi_m4.h b/components/device/silabs/si91x/mcu/hal/inc/rsi_m4.h deleted file mode 100644 index 2d77d07ce..000000000 --- a/components/device/silabs/si91x/mcu/hal/inc/rsi_m4.h +++ /dev/null @@ -1,215 +0,0 @@ -/******************************************************************************* -* @file rsi_m4.h -* @brief -******************************************************************************* -* # License -* Copyright 2020 Silicon Laboratories Inc. www.silabs.com -******************************************************************************* -* -* The licensor of this software is Silicon Laboratories Inc. Your use of this -* software is governed by the terms of Silicon Labs Master Software License -* Agreement (MSLA) available at -* www.silabs.com/about-us/legal/master-software-license-agreement. This -* software is distributed to you in Source Code format and is governed by the -* sections of the MSLA applicable to Source Code. -* -******************************************************************************/ - -#ifndef _RSI_M4_HAL_H_ -#define _RSI_M4_HAL_H_ -#ifdef SLI_SI91X_MCU_INTERFACE - -#include "rsi_pkt_mgmt.h" -#include "RS1xxxx.h" -#include "core_cm4.h" -/****************************************************** - * * Constants - * ******************************************************/ - -#define M4_ISR_IRQ 74 - -#define TA_MEMORY_OFFSET_ADDRESS 0x00400000 -#ifdef SLI_SI917 -#define M4_MEMORY_OFFSET_ADDRESS 0x00500000 -#else -#define M4_MEMORY_OFFSET_ADDRESS 0x00200000 -#endif - -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#ifndef NVIC -#define NVIC ((NVIC_Type *)NVIC_BASE) /*!< NVIC configuration struct */ -#endif - -#define M4SS_P2P_INT_BASE_ADDRESS 0x46008000 -#define MCU_PWR_CTRL_BASE_ADDR 0x24048400 -#define MISC_CFG_HOST_CTRL *(volatile uint32_t *)(M4SS_P2P_INT_BASE_ADDRESS + 0x0C) - -#define M4SS_P2P_INTR_SET_REG *(volatile uint32_t *)(M4SS_P2P_INT_BASE_ADDRESS + 0x16C) -#define M4SS_P2P_INTR_CLR_REG *(volatile uint32_t *)(M4SS_P2P_INT_BASE_ADDRESS + 0x170) -#define P2P_STATUS_REG *(volatile uint32_t *)(M4SS_P2P_INT_BASE_ADDRESS + 0x174) -#define TASS_P2P_INTR_MASK_SET *(volatile uint32_t *)(M4SS_P2P_INT_BASE_ADDRESS + 0x178) -#define TASS_P2P_INTR_MASK_CLR *(volatile uint32_t *)(M4SS_P2P_INT_BASE_ADDRESS + 0x17C) -#define TASS_P2P_INTR_CLEAR *(volatile uint32_t *)(M4SS_P2P_INT_BASE_ADDRESS + 0x180) - -#define TASS_P2P_INT_BASE_ADDRESS 0x41050000 - -#define TASS_P2P_INTR_SET_REG *(volatile uint32_t *)(TASS_P2P_INT_BASE_ADDRESS + 0x8C) -#define TASS_P2P_INTR_CLR_REG *(volatile uint32_t *)(TASS_P2P_INT_BASE_ADDRESS + 0x90) - -#define M4_TX_DMA_DESC_REG *(volatile uint32_t *)(TASS_P2P_INT_BASE_ADDRESS + 0x34) -#define M4_RX_DMA_DESC_REG *(volatile uint32_t *)(TASS_P2P_INT_BASE_ADDRESS + 0x5C) -#define HOST_INTR_STATUS_REG *(volatile uint32_t *)(TASS_P2P_INT_BASE_ADDRESS + 0x04) - -#define DMA_DESC_REG_VALID (0xA0 << 8) - -#define TA_wakeup_M4 BIT(2) -#define TA_is_active BIT(3) -#define M4_wakeup_TA BIT(0) -#define M4_is_active BIT(1) -#define NWP_DEINIT_IN_COMM_FLASH BIT(7) -#define ARM_MASK_1 0xE000E100 -#define ARM_MASK_1 0xE000E100 -#define ARM_MASK_1 0xE000E100 - -#ifndef BIT -#define BIT(x) (1 << (x)) -#endif - -//! This interrupt is raised by M4 to TA when there is a TX packet from M4 to read -#define RX_BUFFER_VALID BIT(1) -#define TX_PKT_PENDING_INTERRUPT BIT(2) -#define UPGRADE_M4_IMAGE BIT(5) -#ifdef SLI_SI917 -#define M4_WAITING_FOR_TA_TO_WR_ON_FLASH BIT(6) -#endif - -#define TX_PKT_TRANSFER_DONE_INTERRUPT BIT(2) -//! This interrupt is received from TA when RX packet is pending from TA - -#define RX_PKT_TRANSFER_DONE_INTERRUPT BIT(1) -//! This interrupt is received from TA when TX packet transfer from M4 to TA is done - -#define M4_IMAGE_UPGRADATION_PENDING_INTERRUPT BIT(4) -//! This interrupt is raised by TA to M4 when there is a TX packet from M4 to read - -#ifdef SLI_SI917 -//! This interrupt is raised by TA to M4 when there is a flash write request from M4 to TA in comm flash mode -#define TA_WRITING_ON_COMM_FLASH BIT(5) -#endif - -#ifndef RSI_BUFFER_FULL -//! buffer full indication register value from module -#define RSI_BUFFER_FULL BIT(0) -#endif - -#ifdef SLI_SI917 -//! Option value for m4 app from flash to ram API -#define UPGRADE_M4_IMAGE_OTA 1 -#define TA_WRITES_ON_COMM_FLASH 2 -#endif - -#ifdef SLI_SI91X_ENABLE_OS -#define TASS_P2P_INTR_PRI 5 -#define SYSTICK_INTR_PRI 7 -#endif -/****************************************************** - * * Enumerations - * ******************************************************/ - -/****************************************************** - * * Type Definitions - * ******************************************************/ -typedef struct rsi_m4ta_desc_dword1_s { - //! Reserved - uint32_t reserved : 15; - - //! 1 bit : indicates the presence of more descriptors - //! 1 - last descriptor - //! 0 - more descriptors are present - uint32_t last_desc : 1; - - //! Buffer queue_no to be transfered for this descriptor - uint32_t queue_no : 4; - - //! Buffer length to be transfered for this descriptor - uint32_t length : 12; - -} rsi_m4ta_desc_dword1_t; - -typedef struct rsi_m4ta_desc_s { - //! source address - uint32_t addr; - - uint16_t length; - //! descriptor control fields - //rsi_m4ta_desc_dword1_t dword1; - -} rsi_m4ta_desc_t; - -//! host descriptor structure -typedef struct rsi_frame_desc_s { - //! Data frame body length. Bits 14:12=queue, 000 for data, Bits 11:0 are the length - uint8_t frame_len_queue_no[2]; - //! Frame type - uint8_t frame_type; - //! Unused , set to 0x00 - uint8_t reserved[9]; - //! Management frame descriptor response status, 0x00=success, else error - uint8_t status; - uint8_t reserved1[3]; -} rsi_frame_desc_t; - -//! P2P registers Backup structure -typedef struct rsi_p2p_intr_status_bkp_s { - uint32_t tass_p2p_intr_mask_clr_bkp; - uint32_t m4ss_p2p_intr_set_reg_bkp; -} rsi_p2p_intr_status_bkp_t; - -/****************************************************** - * * Structures - * ******************************************************/ - -/****************************************************** - * * Global Variables - * ******************************************************/ -/****************************************************** - * * Function Declarations - * ******************************************************/ -int16_t rsi_frame_write(rsi_frame_desc_t *uFrameDscFrame, uint8_t *payloadparam, uint16_t size_param); -rsi_pkt_t *rsi_frame_read(void); -int16_t rsi_device_interrupt_status(uint8_t *int_status); - -void rsi_m4_interrupt_isr(void); -void rsi_m4_ta_interrupt_init(void); -void rsi_raise_pkt_pending_interrupt_to_ta(void); -int32_t rsi_send_pkt_to_ta(rsi_m4ta_desc_t *tx_desc); -void rsi_transfer_to_ta_done_isr(void); -void rsi_pkt_pending_from_ta_isr(void); -void rsi_receive_from_ta_done_isr(void); -int16_t rsi_device_buffer_full_status(void); -int rsi_submit_rx_pkt(void); -void unmask_ta_interrupt(uint32_t interrupt_no); -void raise_m4_to_ta_interrupt(uint32_t interrupt_no); -void clear_m4_to_ta_interrupt(uint32_t interrupt_no); -void clear_ta_interrupt_mask(void); -void set_ta_interrupt_mask(void); -void mask_ta_interrupt(uint32_t interrupt_no); -void unmask_ta_interrupt(uint32_t interrupt_no); -void clear_ta_to_m4_interrupt(uint32_t interrupt_no); -void ROM_WL_raise_m4_to_ta_interrupt(uint32_t interrupt_no); -void ROM_WL_clear_m4_to_ta_interrupt(uint32_t interrupt_no); -void ROM_WL_clear_ta_interrupt_mask(void); -void ROM_WL_set_ta_interrupt_mask(void); -void ROM_WL_mask_ta_interrupt(uint32_t interrupt_no); -void ROM_WL_unmask_ta_interrupt(uint32_t interrupt_no); -void ROM_WL_clear_ta_to_m4_interrupt(uint32_t interrupt_no); -uint32_t NVIC_GetIRQEnable(IRQn_Type IRQn); -void rsi_config_m4_dma_desc_on_reset(void); -void rsi_update_tx_dma_desc(uint8_t skip_dma_valid); -void rsi_update_rx_dma_desc(void); -void IRQ074_Handler(void); - -#endif -#endif diff --git a/components/device/silabs/si91x/mcu/hal/inc/sl_si91x_hal_soc_soft_reset.h b/components/device/silabs/si91x/mcu/hal/inc/sl_si91x_hal_soc_soft_reset.h index 1fcf0b621..cbb69a561 100644 --- a/components/device/silabs/si91x/mcu/hal/inc/sl_si91x_hal_soc_soft_reset.h +++ b/components/device/silabs/si91x/mcu/hal/inc/sl_si91x_hal_soc_soft_reset.h @@ -31,6 +31,10 @@ #ifndef __SL_SI91X_HAL_SOC_SOFT_RESET__ #define __SL_SI91X_HAL_SOC_SOFT_RESET__ +#define M4_BBFF_STORAGE1 *(volatile uint32 *)0x24048580 +#define M4_QSPI_AES_CONFIG *(volatile uint32 *)0x120000C8 +#define AES_QSPI_KEY_SIZE BIT(16) +#define KEY_LENGTH BIT(11) /* * * @brief This API is used to config WDT @@ -38,4 +42,11 @@ * @return None */ void sl_si91x_soc_soft_reset(void); +/* + * + * @brief This API is used to do soc NVIC reset with the debug module disabled. + * @param None + * @return None + */ +void sl_si91x_soc_nvic_reset(void); #endif \ No newline at end of file diff --git a/components/device/silabs/si91x/mcu/hal/src/sl_si91x_hal_soc_soft_reset.c b/components/device/silabs/si91x/mcu/hal/src/sl_si91x_hal_soc_soft_reset.c index 3410643f8..df1630aa1 100644 --- a/components/device/silabs/si91x/mcu/hal/src/sl_si91x_hal_soc_soft_reset.c +++ b/components/device/silabs/si91x/mcu/hal/src/sl_si91x_hal_soc_soft_reset.c @@ -30,7 +30,7 @@ #include "rsi_wwdt.h" #include "cmsis_os2.h" #include "sl_si91x_hal_soc_soft_reset.h" -#define M4_BBFF_STORAGE1 *(volatile uint32 *)0x24048580 + /* * * @brief WDT interrupt handler @@ -64,8 +64,44 @@ void sl_si91x_soc_soft_reset(void) NVIC_EnableIRQ(NVIC_WDT); /*Start WDT */ RSI_WWDT_Start(MCU_WDT); + /*Upon Reset key size is 16 by default in case of inline encryption */ - M4_BBFF_STORAGE1 = 0; + /*Store key length bit (32 Bytes) in BBFF if device security is with 32 Bytes key*/ + if (M4_QSPI_AES_CONFIG & AES_QSPI_KEY_SIZE) { + M4_BBFF_STORAGE1 |= KEY_LENGTH; + } while (1) ; } +/* + * + * @brief This API is used to do soc NVIC reset with the debug module disabled. + * @param None + * @return None + */ +void sl_si91x_soc_nvic_reset(void) +{ + /*Upon Reset key size is 16 by default in case of inline encryption */ + /*Store key length bit (32 Bytes) in BBFF if device security is with 32 Bytes key*/ + if (M4_QSPI_AES_CONFIG & AES_QSPI_KEY_SIZE) { + M4_BBFF_STORAGE1 |= KEY_LENGTH; + } + __asm volatile("cpsid i" ::: "memory"); + /*Data Synchronization Barrier */ + __DSB(); + /*Instruction Synchronization Barrier */ + __ISB(); + /*Power Down the Debug Module */ + RSI_PS_M4ssPeriPowerDown(M4SS_PWRGATE_ULP_M4_DEBUG_FPU); + /*Set the SYSRESETREQ bit in the AIRCR register to initiate a system reset */ + SCB->AIRCR = (0x5FA << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk; + /*Ensure the instruction is not optimized out */ + /*Data Synchronization Barrier */ + __DSB(); + /*Instruction Synchronization Barrier */ + __ISB(); + /*Wait for the reset to occur */ + while (1) { + /* Infinite loop to keep the program running until the reset happens */ + } +} diff --git a/components/device/silabs/si91x/mcu/toolchain/component/wiseconnect_toolchain_plugin.slcc b/components/device/silabs/si91x/mcu/toolchain/component/wiseconnect_toolchain_plugin.slcc index 3aa70fcc5..32102793f 100644 --- a/components/device/silabs/si91x/mcu/toolchain/component/wiseconnect_toolchain_plugin.slcc +++ b/components/device/silabs/si91x/mcu/toolchain/component/wiseconnect_toolchain_plugin.slcc @@ -10,8 +10,10 @@ root_path: components/device/silabs/si91x/mcu/toolchain provides: - name: wiseconnect_toolchain_plugin template_file: + - path: linkerfile_psram_SoC.ld.jinja + condition: [wiseconnect_toolchain_psram_linker] - path: linkerfile_SoC.ld.jinja - unless: [wiseconnect_toolchain_gcc_override, wiseconnect_toolchain_custom_linker] + unless: [wiseconnect_toolchain_gcc_override, wiseconnect_toolchain_custom_linker, wiseconnect_toolchain_psram_linker] requires: - name: toolchain_gcc - name: toolchain_variant_arm @@ -24,9 +26,12 @@ library: unless: - wiseconnect_toolchain_gcc_override toolchain_settings: + - option: linkerfile + value: autogen/linkerfile_psram_SoC.ld + condition: [wiseconnect_toolchain_psram_linker] - option: linkerfile value: autogen/linkerfile_SoC.ld - unless: [wiseconnect_toolchain_gcc_override, wiseconnect_toolchain_custom_linker] + unless: [wiseconnect_toolchain_gcc_override, wiseconnect_toolchain_custom_linker, wiseconnect_toolchain_psram_linker] - option: gcc_linker_option value: "-u _printf_float" - option: gcc_compiler_option diff --git a/components/device/silabs/si91x/mcu/toolchain/component/wiseconnect_toolchain_psram_linker.slcc b/components/device/silabs/si91x/mcu/toolchain/component/wiseconnect_toolchain_psram_linker.slcc new file mode 100644 index 000000000..3ed12bff2 --- /dev/null +++ b/components/device/silabs/si91x/mcu/toolchain/component/wiseconnect_toolchain_psram_linker.slcc @@ -0,0 +1,14 @@ +id: wiseconnect_toolchain_psram_linker +label: Toolchain support for PSRAM Linker +package: platform +description: > + Selecting this will include the PSRAM Linker component. +category: Device|Si91x|MCU|Toolchain +ui_hints: + visibility: never +quality: production +root_path: components/device/silabs/si91x/mcu/toolchain +provides: + - name: wiseconnect_toolchain_psram_linker +requires: + - name: wiseconnect_toolchain_plugin \ No newline at end of file diff --git a/components/device/silabs/si91x/mcu/toolchain/linkerfile.ld.jinja b/components/device/silabs/si91x/mcu/toolchain/linkerfile.ld.jinja deleted file mode 100644 index 8e3570907..000000000 --- a/components/device/silabs/si91x/mcu/toolchain/linkerfile.ld.jinja +++ /dev/null @@ -1,341 +0,0 @@ -/***************************************************************************//** - * GCC Linker script for Silicon Labs devices - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -{#- - Device specific sizes and addresses. These variables describes the physical - memory of the device. -#} -{%- set sram_addr = device_ram_addr | first %} -{%- set sram_size = device_ram_size | first %} -{%- set flash_addr = device_flash_addr | first %} -{%- set flash_size = device_flash_size | first %} -{%- set flash_page_size = device_flash_page_size | first %} - -{%- if udma_enable %} - {%- set udma0_main_size = udma0_size | sum %} - {%- set udma0_start_addr = udma0 | sum %} - {%- set udma1_main_size = udma1_size | sum %} - {%- set udma1_start_addr = udma1 | sum %} -{%- endif %} - -{#- - Application specific sizes. Here we start to calculate the application view - of the physical memory. -#} -{%- set app_flash_start = flash_addr %} -{%- set app_flash_end = flash_addr + flash_size %} -{%- set app_ram_start = sram_addr %} -{%- set app_ram_end = sram_addr + sram_size %} - -{#- - Calculate application flash and ram size based on start and end address. -#} -{%- set app_flash_size = app_flash_end - app_flash_start %} -{%- set app_ram_size = app_ram_end - app_ram_start %} - -{%- if udma_enable %} - {%- set udma_buffer = udma_buffer | sum %} - {%- set app_ram_size = app_ram_size - udma_buffer %} - {%- set udma0_start_addr = app_ram_size %} - {%- set udma1_start_addr = udma1_start_addr - udma_buffer%} -{%- endif %} - -{%- set rtt = 0 %} -{% if linker_rtt_section is defined %} -{%- set rtt = 1 %} -{% endif %} - -{%- if nvm3_flash_size %} - {%- set nvm_size = nvm3_size | first%} - {%- set app_flash_size = app_flash_size - nvm_size %} -{%- endif %} - MEMORY - { - rom (rx) : ORIGIN = 0x{{ '%0x' % app_flash_start }}, LENGTH = 0x{{ '%0x' % app_flash_size }} - ram (rwx) : ORIGIN = 0x{{ '%0x' % app_ram_start }}, LENGTH = 0x{{ '%0x' % app_ram_size }} - } - -{%- if udma_enable %} - MEMORY - { - udma0 (rwx) : ORIGIN = 0x{{ '%0x' % udma0_start_addr }}, LENGTH = 0x{{ '%0x' % udma0_main_size }} - udma1 (rwx) : ORIGIN = 0x{{ '%0x' % udma1_start_addr }}, LENGTH = 0x{{ '%0x' % udma1_main_size }} - } -{%- endif %} - -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - {% if not EXECUTION_FROM_RAM_PS2 %} - {% if not SLI_SI91X_MCU_ENABLE_RAM_BASED_EXECUTION %} - *(.text*) - {% endif %} - {% if EXECUTION_FROM_RAM %} - KEEP(*(.reset_handler)) - *(EXCLUDE_FILE( *rsi_common.o *rsi_driver.o *rsi_driver_event_handlers.o *rsi_events.o *rsi_os_none.o *rsi_pkt_mgmt.o *rsi_queue.o *rsi_scheduler.o *rsi_timer.o *rsi_utils.o *rsi_wlan.o *rsi_common_apis.o *rsi_wlan_apis.o *rsi_apis_non_rom.o *rsi_hal_mcu_timer.o *rsi_hal_mcu_interrupt.o *rsi_hal_mcu_m4.o *rsi_hal_mcu_platform_init.o *rsi_apis_rom.o *rsi_events_rom.o *rsi_hal_mcu_m4_rom.o *rsi_hal_mcu_m4_ram.o *rsi_pkt_mgmt_rom.o *rsi_queue_rom.o *rsi_scheduler_rom.o *rsi_socket_rom.o *rsi_utils_rom.o *rsi_nwk_rom.o *rsi_os_wrapper.o *port.o *heap_4.o *timers.o *croutine.o *event_groups.o *list.o *queue.o *tasks.o *stream_buffer.o *network_sapi_wrapper.o *rsi_deepsleep_soc.o ) .text*) - {% endif %} - {% if not EXECUTION_FROM_RAM %} - *(EXCLUDE_FILE(*rsi_deepsleep_soc.o *rsi_hal_mcu_m4_ram.o) .text*) - KEEP(*(.init)) - KEEP(*(.fini)) - {% endif %} - {% endif %} - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - {% if not EXECUTION_FROM_RAM_PS2 %} - {% if not EXECUTION_FROM_RAM %} - *(.rodata*) - {% endif %} - {% if not SLI_SI91X_MCU_ENABLE_RAM_BASED_EXECUTION %} - *(.rodata*) - {% endif %} - {% endif %} - KEEP(*(.eh_fram e*)) - } > rom - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > rom - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > rom - __exidx_end = .; - __etext = .; - - /* _sidata is used in startup code */ - _sidata = __etext; - - .data : - { - __data_start__ = .; - - /* _sdata is used in startup code */ - _sdata = __data_start__; - {% if EXECUTION_FROM_RAM %} - KEEP(*(.ramVector)) - KEEP(*(.init)) - KEEP(*(.fini)) - *(.rodata*) - {% endif %} - {% if EXECUTION_FROM_RAM_PS2 %} - KEEP(*(.ramVector)) - KEEP(*(.init)) - KEEP(*(.fini)) - *(.rodata*) - *(.text*) - {% endif %} - *(vtable) - *(.data*) - {% if EXECUTION_FROM_RAM %} - *rsi_common.o(.text*) - *rsi_driver.o(.text*) - *rsi_driver_event_handlers.o(.text*) - *rsi_events.o(.text*) - *rsi_os_none.o(.text*) - *rsi_pkt_mgmt.o(.text*) - *rsi_queue.o(.text*) - *rsi_scheduler.o(.text*) - *rsi_timer.o(.text*) - *rsi_utils.o(.text*) - *rsi_wlan.o(.text*) - *rsi_common_apis.o(.text*) - *rsi_wlan_apis.o(.text*) - *rsi_apis_non_rom.o(.text*) - *rsi_hal_mcu_timer.o(.text*) - *rsi_hal_mcu_m4.o(.text*) - *rsi_hal_mcu_interrupt.o(.text*) - *rsi_hal_mcu_platform_init.o(.text*) - *rsi_hal_mcu_m4_rom.o(.text*) - *rsi_hal_mcu_m4_ram.o(.text*) - *rsi_apis_rom.o(.text*) - *rsi_events_rom.o(.text*) - *rsi_pkt_mgmt_rom.o(.text*) - *rsi_queue_rom.o(.text*) - *rsi_scheduler_rom.o(.text*) - *rsi_socket_rom.o(.text*) - *rsi_utils_rom.o(.text*) - *rsi_nwk_rom.o(.text*) - *rsi_os_wrapper.o(.text*) - *timers.o(.text*) - *croutine.o(.text*) - *event_groups.o(.text*) - *list.o(.text*) - *queue.o(.text*) - *stream_buffer.o(.text*) - *tasks.o(.text*) - *heap_4.o(.text*) - *port.o(.text*) - *network_sapi_wrapper.o(.text*) - *rsi_deepsleep_soc.o(.text*) - {% endif %} - {% if not EXECUTION_FROM_RAM_PS2 %} - {% if not EXECUTION_FROM_RAM %} - *rsi_deepsleep_soc.o(.text*) - *rsi_hal_mcu_m4_ram.o(.text*) - {% endif %} - {% endif %} - {% if SLI_SI91X_MCU_ENABLE_RAM_BASED_EXECUTION %} - *(.text*) - *(.rodata*) - KEEP(*(.init)) - KEEP(*(.fini)) - {% endif %} - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - /* _edata is used in startup code */ - _edata = __data_end__; - } > ram AT> rom - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - _sbss = __bss_start__; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - _ebss = __bss_end__; - } > ram - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - Co_Stack_Size = 0x3000; - .co_stack ALIGN(8) (NOLOAD): - { - __co_stackLimit = .; - KEEP(*(.co_stack*)) - . = ALIGN(4); - . += Co_Stack_Size; - __co_stackTop = .; - } > ram - - StackSize = 0x1400; - .stack ALIGN(8) (NOLOAD): - { - __StackLimit = .; - KEEP(*(.stack*)) - . = ALIGN(4); - . += StackSize; - __StackTop = .; - PROVIDE(__stack = __StackTop); - } > ram - - .heap (COPY): - { - __HeapBase = .; - __end__ = .; - end = __end__; - _end = __end__; - KEEP(*(.heap*)) - . = ORIGIN(ram) + LENGTH(ram); - __HeapLimit = .; - } > ram - __heap_size = __HeapLimit - __HeapBase; - -{%- if udma_enable %} - .udma_addr0 : - { - *(.udma_addr0*) - } > udma0 AT> rom - - .udma_addr1 : - { - *(.udma_addr1*) - } > udma1 AT> rom -{%- endif %} - -{%- if nvm3_enable %} - __ram_end__ = 0x{{ '%0x' % app_ram_start }} + 0x{{ '%0x' % app_ram_size }}; - __main_flash_end__ = 0x{{ '%0x' % app_flash_start }} + 0x{{ '%0x' % app_flash_size }}; - - /* This is where we handle flash storage blocks. We use dummy sections for finding the configured - * block sizes and then "place" them at the end of flash when the size is known. */ - .internal_storage (DSECT) : { - KEEP(*(.internal_storage*)) - } > rom - - .nvm (DSECT) : { - KEEP(*(.simee*)) - } > rom - - linker_nvm_end = __main_flash_end__; - linker_nvm_begin = linker_nvm_end - SIZEOF(.nvm); - linker_nvm_size = SIZEOF(.nvm); - linker_storage_end = linker_nvm_begin; - __nvm3Base = linker_nvm_begin; - - linker_storage_begin = linker_storage_end - SIZEOF(.internal_storage); - linker_storage_size = SIZEOF(.internal_storage); - ASSERT((linker_storage_begin >= (__etext + SIZEOF(.data))), "FLASH memory overflowed !") -{%- endif %} -} \ No newline at end of file diff --git a/components/device/silabs/si91x/mcu/toolchain/linkerfile_SoC.ld.jinja b/components/device/silabs/si91x/mcu/toolchain/linkerfile_SoC.ld.jinja index c57146459..cd3091c9e 100644 --- a/components/device/silabs/si91x/mcu/toolchain/linkerfile_SoC.ld.jinja +++ b/components/device/silabs/si91x/mcu/toolchain/linkerfile_SoC.ld.jinja @@ -39,12 +39,6 @@ {%- endif %} {%- set flash_page_size = device_flash_page_size | first %} - -{%- if psram_present %} - {%- set psram_addr = device_psram_addr | first %} - {%- set psram_size = device_psram_size | first %} -{%- endif %} - {%- if udma_enable %} {%- set udma0_main_size = udma0_size | sum %} {%- set udma0_start_addr = udma0 | sum %} @@ -63,16 +57,6 @@ {%- set app_ram_start = sram_addr %} {%- set app_ram_end = sram_size %} -{%- if psram_present %} - {%- set app_psram_start = psram_addr %} - {%- if text_segment_in_psram %} - {#- Adds 0x1000 offset (4096 in decimal) #} - {%- set psram_start_offset = 4096 %} - {%- set app_psram_start = psram_addr + psram_start_offset %} - {%- endif %} - {%- set app_psram_end = psram_addr + psram_size %} -{%- endif %} - {#- Calculate application flash and ram size based on start and end address. #} @@ -88,10 +72,6 @@ {%- set udma1_start_addr = udma1_start_addr - udma_buffer%} {%- endif %} -{%- if psram_present %} - {%- set app_psram_size = app_psram_end - app_psram_start %} -{%- endif %} - {%- set rtt = 0 %} {% if linker_rtt_section is defined %} {%- set rtt = 1 %} @@ -102,15 +82,16 @@ {%- set app_flash_size = app_flash_size - nvm_size %} {%- endif %} +{%- if nvm3_enable or littlefs_enable %} + {%- set nvm3_app_max_flash_size = max_flash_size | first %} +{%- endif %} + MEMORY { {%- if flash_present %} rom (rx) : ORIGIN = 0x{{ '%0x' % app_flash_start }}, LENGTH = 0x{{ '%0x' % app_flash_size }} {% endif %} ram (rwx) : ORIGIN = 0x{{ '%0x' % app_ram_start }}, LENGTH = 0x{{ '%0x' % app_ram_size }} - {%- if psram_present %} - psram (rwx) : ORIGIN = 0x{{ '%0x' % app_psram_start }}, LENGTH = 0x{{ '%0x' % app_psram_size }} - {%- endif %} } {%- if udma_enable %} @@ -121,12 +102,6 @@ } {%- endif %} -{%- if psram_present and psram_linker_config_enabled %} - -_last_psram_location = ORIGIN(psram); -_last_ram_location = ORIGIN(ram); -{%- endif %} - ENTRY(Reset_Handler) SECTIONS @@ -134,22 +109,20 @@ SECTIONS .text : { KEEP(*(.isr_vector)) - {%- if ram_execution %} - KEEP(*(.reset_handler)) + {%- if not power_manager_ps2 %} + {%- if ram_execution %} + KEEP(*(.reset_handler)) *(EXCLUDE_FILE(*sl_si91x_bus.o *sl_si91x_driver.o *sli_si91x_multithreaded.o *rsi_deepsleep_soc.o *rsi_hal_mcu_m4_ram.o *rsi_hal_mcu_m4_rom.o *UDMA.o *sl_sleeptimer.o *sl_sleeptimer_hal_si91x_sysrtc.o *rsi_sysrtc.o *sl_si91x_low_power_tickless_mode.o *croutine.o *event_groups.o *list.o *queue.o *stream_buffer.o *tasks.o *timers.o *cmsis_os2.o *freertos_umm_malloc_host.o *malloc_buffers.o *sl_rsi_utility.o *port.o *heap_*.o) .text*) - {% endif %} - {% if psram_present and psram_linker_config_enabled and psram_powersave_handle %} - *(EXCLUDE_FILE(*rsi_deepsleep_soc.o *sl_si91x_psram.o *rsi_qspi.o *rsi_pll.o *rsi_egpio.o *UDMA.o *sl_rsi_utility.o) .text*) - {% elif power_manager_ps2 %} + {% else %} + *(EXCLUDE_FILE(*UDMA.o).text*) + KEEP(*(.init)) + KEEP(*(.fini)) + {% endif %} + {% endif %} + + {% if power_manager_ps2 %} *(EXCLUDE_FILE( *cmsis_gcc.o *cmsis_os2.o *port.o *queue.o *sl_rsi_utility.o *tasks.o *clock_update.o *rsi_deepsleep_soc.o *rsi_egpio.o *rsi_ipmu.o *ipmu_apis.o *rsi_pll.o *rsi_power_save.o *rsi_ps_ram_func.o *rsi_system_config.o *rsi_time_period.o *rsi_ulpss_clk.o *system_si91x.o *sl_slist.o *strcmp.o *sl_si91x_power_manager.o *sli_si91x_power_manager.o *sl_si91x_power_manager_handler.o *sl_si91x_power_manager_debug.o *sli_si91x_power_manager_wakeup_init.o *sl_si91x_power_manager_wakeup_handler.o *sl_sleeptimer.o *sl_sleeptimer_hal_si91x_sysrtc.o *rsi_sysrtc.o *sl_si91x_low_power_tickless_mode.o *sl_core_cortexm.o *UDMA.o {% for c in debug_ps2 %}*{{c}} {% endfor %}{% for c in calendar_ps2 %}*{{c}} {% endfor %}{% for c in ulp_timer_ps2 %}*{{c}} {% endfor %}{% for c in wdt_ps2 %}*{{c}} {% endfor %}{% for c in adc_ps2 %}*{{c}} {% endfor %}{% for c in bod_ps2 %}*{{c}} {% endfor %}{% for c in comparator_ps2 %}*{{c}} {% endfor %}{% for c in cts_ps2 %}*{{c}} {% endfor %}{% for c in dac_ps2 %}*{{c}} {% endfor %}{% for c in dma_ps2 %}*{{c}} {% endfor %}{% for c in gpio_ps2 %}*{{c}} {% endfor %}{% for c in i2c_ps2 %}*{{c}} {% endfor %}{% for c in i2s_ps2 %}*{{c}} {% endfor %}{% for c in ir_ps2 %}*{{c}} {% endfor %}{% for c in ssi_ps2 %}*{{c}} {% endfor %}{% for c in sysrtc_ps2 %}*{{c}} {% endfor %}{% for c in usart_ps2 %}*{{c}} {% endfor %}{% for c in user_files_ps2 %}*{{c}} {% endfor %}) .text*) - {% elif ulp_mode_execution %} - *(.copysection*) - *(.zerosection*) - - {% elif not ram_execution %} - *(EXCLUDE_FILE(*UDMA.o).text*) - KEEP(*(.init)) - KEEP(*(.fini)) + {%- endif %} /* .ctors */ @@ -166,17 +139,13 @@ SECTIONS *(SORT(.dtors.*)) *(.dtors) - {%- if not ulp_mode_execution %} {%- if not power_manager_ps2 %} *(.rodata*) {%- endif %} - {%- endif %} KEEP(*(.eh_fram e*)) - {%- if psram_present and text_segment_in_psram %} - _last_psram_location = .; - } > psram - {%- elif flash_present %} + + {%- if flash_present %} } > rom {%- else %} } > ram @@ -185,10 +154,8 @@ SECTIONS .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) - {%- if psram_present and text_segment_in_psram %} - _last_psram_location = .; - } > psram - {%- elif flash_present %} + + {%- if flash_present %} } > rom {%- else %} } > ram @@ -198,10 +165,8 @@ SECTIONS .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) - {%- if psram_present and text_segment_in_psram %} - _last_psram_location = .; - } > psram - {%- elif flash_present %} + + {%- if flash_present %} } > rom {%- else %} } > ram @@ -209,119 +174,40 @@ SECTIONS __exidx_end = .; __etext = .; - {%- if flash_present %} - {% if ulp_mode_execution %} - .copysection : - { - . = ALIGN(4); - __copysection_start__ = .; - *(.copysection*) - __copysection_end__ = .; - } > rom - - .zerosection : - { - . = ALIGN(4); - __zerosection_start__ = .; - *(.zerosection*) - __zerosection_end__ = .; - } > rom - {% endif %} - {% endif %} - - {% if psram_present and psram_linker_config_enabled and psram_powersave_handle %} - _slpcode = __etext; - - . = _last_ram_location; - /* Power save & PSRAM driver code */ - .sleep_psram_driver : - { - __sleep_code_start__ = .; - /* _scode is used in code startup code */ - _scode = __sleep_code_start__; - . = ALIGN(4); - *rsi_deepsleep_soc.o(.text*) - *sl_si91x_psram.o(.text*) - *sl_si91x_psram_handle.o(.text*) - *rsi_qspi.o(.text*) - *rsi_pll.o(.text*) - *rsi_egpio.o(.text*) - *rsi_deepsleep_soc.o(.data*) - *sl_si91x_psram.o(.data*) - *sl_si91x_psram_handle.o(.data*) - *rsi_qspi.o(.data*) - *rsi_pll.o(.data*) - *rsi_egpio.o(.data*) - __sleep_code_end__ = .; - /* _ecode is used in code startup code */ - _ecode = __sleep_code_end__; - _last_ram_location = .; - {%- if text_segment_in_psram %} - } > ram AT> psram - - /* _sidata is used in code startup code */ - _sidata = __etext + (__sleep_code_end__ - __sleep_code_start__); - _last_psram_location = _sidata; - {%- elif flash_present %} - } > ram AT> rom - {%- else %} - } > ram - /* _sidata is used in code startup code */ - _sidata = __etext + (__sleep_code_end__ - __sleep_code_start__); - {% endif %} - {%- else %} /* _sidata is used in code startup code */ _sidata = __etext; - {% endif %} + + + - {%- if psram_present and psram_linker_config_enabled %} - {%- if data_segment_in_psram %} - . = _last_psram_location; - {%- else %} - . = _last_ram_location; - {% endif %} - {% endif %} - {%- if psram_present and psram_linker_config_enabled %} - .data . : - {%- else %} .data : - {% endif %} + { __data_start__ = .; /* _sdata is used in startup code */ _sdata = __data_start__; {%- if not power_manager_ps2 %} + {%- if ram_execution %} KEEP(*(.ramVector)) KEEP(*(.init)) KEEP(*(.fini)) *(.data*) - {% endif %} - {%- if ulp_mode_execution %} - *(.text*) - *(.rodata*) - KEEP(*(.init)) - KEEP(*(.fini)) - {% endif %} - {%- if ram_execution %} - {%- if not ulp_mode_execution %} *rsi_hal_mcu_m4_ram.o(.text*) *rsi_hal_mcu_m4_rom.o(.text*) *sl_si91x_driver.o(.text*) *sl_si91x_bus.o(.text*) - *UDMA.o(.text*) + *UDMA.o(.text*) *sl_sleeptimer.o(.text*) *sl_sleeptimer_hal_si91x_sysrtc.o(.text*) *rsi_sysrtc.o(.text*) *sl_si91x_low_power_tickless_mode.o(.text*) *sli_si91x_multithreaded.o(.text*) - {%- if not psram_linker_config_enabled %} *rsi_deepsleep_soc.o(.text*) - {%- endif %} *croutine.o(.text*) *event_groups.o(.text*) *list.o(.text*) @@ -335,17 +221,9 @@ SECTIONS *sl_rsi_utility.o(.text*) *port.o(.text*) *heap_*.o(.text*) - {%- elif ulp_mode_execution %} - *(.text*) - *(.rodata*) - *(.data*) - KEEP(*(.init)) - KEEP(*(.fini)) - {%- else %} - *(.data*) - {% endif %} {%- else %} *(.data*) + *UDMA.o(.text*) {% endif %} {% endif %} {%- if power_manager_ps2 %} @@ -385,7 +263,7 @@ SECTIONS *rsi_sysrtc.o(.text*) *sl_si91x_low_power_tickless_mode.o(.text*) *sl_core_cortexm.o(.text*) - *UDMA.o(.text*) + *UDMA.o(.text*) {% for c in debug_ps2 %}*{{c}}(.text*) {% endfor %}{% for c in calendar_ps2 %}*{{c}}(.text*) {% endfor %}{% for c in ulp_timer_ps2 %}*{{c}}(.text*) @@ -406,11 +284,7 @@ SECTIONS {% endfor %}{% for c in user_files_ps2 %}*{{c}}(.text*) {% endfor %} {% endif %} - {%- if udma_in_ram %} - *UDMA.o(.text*) - {% endif %} - - + . = ALIGN(4); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); @@ -439,31 +313,11 @@ SECTIONS /* _edata is used in startup code */ _edata = __data_end__; - {%- if psram_present and data_segment_in_psram and not text_segment_in_psram and flash_present %} - _last_psram_location = .; - } > psram AT> rom - {%- elif psram_present and data_segment_in_psram and text_segment_in_psram %} - _last_psram_location = .; - } > psram - {%- elif psram_present and text_segment_in_psram %} - _last_ram_location = .; - } > ram AT> psram - {%- elif psram_present and psram_linker_config_enabled and flash_present %} - _last_ram_location = .; - } > ram AT> rom - {%- elif flash_present %} + {%- if flash_present %} } > ram AT> rom {%- else %} } > ram {% endif %} - - {%- if psram_present and psram_linker_config_enabled %} - {%- if bss_segment_in_psram %} - . = _last_psram_location; - {%- else %} - . = _last_ram_location; - {% endif %} - {% endif %} .bss (NOLOAD) : { @@ -473,23 +327,8 @@ SECTIONS *(COMMON) . = ALIGN(4); __bss_end__ = .; - {%- if psram_present and bss_segment_in_psram %} - _last_psram_location = .; - } > psram - {%- elif psram_present and psram_linker_config_enabled %} - _last_ram_location = .; - } > ram - {%- else %} } > ram - {% endif %} - - {%- if psram_present and psram_linker_config_enabled %} - {%- if stack_segment_in_psram %} - . = _last_psram_location; - {%- else %} - . = _last_ram_location; - {% endif %} - {% endif %} + .stack (NOLOAD): { @@ -497,24 +336,8 @@ SECTIONS KEEP(*(.stack*)) . = ALIGN(4); __StackTop = .; - PROVIDE(__stack = __StackTop); - {%- if psram_present and stack_segment_in_psram %} - _last_psram_location = .; - } > psram - {%- elif psram_present and psram_linker_config_enabled %} - _last_ram_location = .; - } > ram - {%- else %} + PROVIDE(__stack = __StackTop); } > ram - {% endif %} - - {%- if psram_present and psram_linker_config_enabled %} - {%- if heap_segment_in_psram %} - . = _last_psram_location; - {%- else %} - . = _last_ram_location; - {% endif %} - {% endif %} .heap (COPY): { __HeapBase = .; @@ -522,18 +345,10 @@ SECTIONS end = __end__; _end = __end__; KEEP(*(.heap*)) - {%- if psram_present and heap_segment_in_psram %} - . = ORIGIN(psram) + LENGTH(psram); - {%- else %} . = ORIGIN(ram) + LENGTH(ram); - {% endif %} - __HeapLimit = .; - {%- if psram_present and heap_segment_in_psram %} - _last_psram_location = .; - } > psram - {%- else %} + __HeapLimit = .; } > ram - {% endif %} + __heap_size = __HeapLimit - __HeapBase; @@ -542,26 +357,22 @@ SECTIONS .udma_addr0 : { *(.udma_addr0*) - {%- if psram_present and text_segment_in_psram %} - } > udma0 AT> psram - {%- else %} } > udma0 AT> rom - {% endif %} .udma_addr1 : { - *(.udma_addr1*) - {%- if psram_present and text_segment_in_psram %} - } > udma1 AT> psram - {%- else %} + *(.udma_addr1*) } > udma1 AT> rom - {%- endif %} {%- endif %} {% endif %} {%- if nvm3_enable %} __ram_end__ = 0x{{ '%0x' % app_ram_start }} + 0x{{ '%0x' % app_ram_size }}; - __main_flash_end__ = 0x{{ '%0x' % app_flash_start }} + 0x{{ '%0x' % app_flash_size }}; + {%- if app_flash_size >= nvm3_app_max_flash_size %} + __main_flash_end__ = 0x{{ '%0x' % app_flash_start }} + 0x{{ '%0x' % nvm3_app_max_flash_size }}; + {%- else %} + __main_flash_end__ = 0x{{ '%0x' % app_flash_start }} + 0x{{ '%0x' % app_flash_size }}; + {% endif %} /* This is where we handle flash storage blocks. We use dummy sections for finding the configured * block sizes and then "place" them at the end of flash when the size is known. */ .internal_storage1 (DSECT) : { @@ -585,6 +396,8 @@ SECTIONS {%- if littlefs_enable %} {%- if nvm3_enable %} __main_flash_end__ = linker_nvm_begin; +{%- elif app_flash_size >= nvm3_app_max_flash_size %} + __main_flash_end__ = 0x{{ '%0x' % app_flash_start }} + 0x{{ '%0x' % nvm3_app_max_flash_size }}; {%- else %} __main_flash_end__ = 0x{{ '%0x' % app_flash_start }} + 0x{{ '%0x' % app_flash_size }}; {%- endif %} diff --git a/components/device/silabs/si91x/mcu/toolchain/linkerfile_psram_SoC.ld.jinja b/components/device/silabs/si91x/mcu/toolchain/linkerfile_psram_SoC.ld.jinja new file mode 100644 index 000000000..28313d982 --- /dev/null +++ b/components/device/silabs/si91x/mcu/toolchain/linkerfile_psram_SoC.ld.jinja @@ -0,0 +1,489 @@ +/***************************************************************************//** + * GCC Linker script for Silicon Labs devices + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +{#- + Device specific sizes and addresses. These variables describes the physical + memory of the device. +#} +{%- set sram_addr = device_ram_addr | first %} +{%- set sram_size = device_ram_size | first %} +{%- if flash_present %} + {%- set flash_addr = device_flash_addr | first %} + {%- set flash_size = device_flash_size | first %} +{%- endif %} +{%- set flash_page_size = device_flash_page_size | first %} + + +{%- if psram_present %} + {%- set psram_addr = device_psram_addr | first %} + {%- set psram_size = device_psram_size | first %} +{%- endif %} + +{%- if udma_enable %} + {%- set udma0_main_size = udma0_size | sum %} + {%- set udma0_start_addr = udma0 | sum %} + {%- set udma1_main_size = udma1_size | sum %} + {%- set udma1_start_addr = udma1 | sum %} +{%- endif %} + +{#- + Application specific sizes. Here we start to calculate the application view + of the physical memory. +#} +{%- if flash_present %} + {%- set app_flash_start = flash_addr %} + {%- set app_flash_end = flash_addr + flash_size %} +{%- endif %} +{%- set app_ram_start = sram_addr %} +{%- set app_ram_end = sram_size %} + +{%- if psram_present %} + {%- set app_psram_start = psram_addr %} + {%- if text_segment_in_psram %} + {#- Adds 0x1000 offset (4096 in decimal) #} + {%- set psram_start_offset = 4096 %} + {%- set app_psram_start = psram_addr + psram_start_offset %} + {%- endif %} + {%- set app_psram_end = psram_addr + psram_size %} +{%- endif %} + +{#- + Calculate application flash and ram size based on start and end address. +#} +{%- if flash_present %} +{%- set app_flash_size = app_flash_end - app_flash_start %} +{%- endif %} +{%- set app_ram_size = app_ram_end - app_ram_start %} + +{%- if udma_enable %} + {%- set udma_buffer = udma_buffer | sum %} + {%- set app_ram_size = app_ram_size - udma_buffer %} + {%- set udma0_start_addr = app_ram_size + app_ram_start %} + {%- set udma1_start_addr = udma1_start_addr - udma_buffer%} +{%- endif %} + +{%- if psram_present %} + {%- set app_psram_size = app_psram_end - app_psram_start %} +{%- endif %} + +{%- set rtt = 0 %} +{% if linker_rtt_section is defined %} +{%- set rtt = 1 %} +{% endif %} + + + MEMORY + { +{%- if flash_present %} + rom (rx) : ORIGIN = 0x{{ '%0x' % app_flash_start }}, LENGTH = 0x{{ '%0x' % app_flash_size }} +{% endif %} + ram (rwx) : ORIGIN = 0x{{ '%0x' % app_ram_start }}, LENGTH = 0x{{ '%0x' % app_ram_size }} + {%- if psram_present %} + psram (rwx) : ORIGIN = 0x{{ '%0x' % app_psram_start }}, LENGTH = 0x{{ '%0x' % app_psram_size }} + {%- endif %} + } + +{%- if udma_enable %} + MEMORY + { + udma0 (rwx) : ORIGIN = 0x{{ '%0x' % udma0_start_addr }}, LENGTH = 0x{{ '%0x' % udma0_main_size }} + udma1 (rwx) : ORIGIN = 0x{{ '%0x' % udma1_start_addr }}, LENGTH = 0x{{ '%0x' % udma1_main_size }} + } +{%- endif %} + +{%- if psram_present and psram_linker_config_enabled %} + +_last_psram_location = ORIGIN(psram); +_last_ram_location = ORIGIN(ram); +{%- endif %} + +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + {% if (psram_present and psram_linker_config_enabled and ram_execution) %} + KEEP(*(.reset_handler)) + *(EXCLUDE_FILE(*sl_si91x_bus.o *sl_si91x_driver.o *sli_si91x_multithreaded.o *rsi_deepsleep_soc.o *rsi_hal_mcu_m4_ram.o *rsi_hal_mcu_m4_rom.o *sl_sleeptimer.o *sl_sleeptimer_hal_si91x_sysrtc.o *rsi_sysrtc.o *sl_si91x_low_power_tickless_mode.o *croutine.o *event_groups.o *list.o *queue.o *stream_buffer.o *tasks.o *timers.o *cmsis_os2.o *freertos_umm_malloc_host.o *malloc_buffers.o *port.o *heap_*.o *sl_si91x_psram.o *rsi_qspi.o *rsi_pll.o *rsi_egpio.o *UDMA.o *sl_rsi_utility.o *ipmu_apis.o *rsi_d_cache.o) .text*) + {%- else %} + *(EXCLUDE_FILE(*UDMA.o).text*) + KEEP(*(.init)) + KEEP(*(.fini)) + {% endif %} + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_fram e*)) + {%- if psram_present and text_segment_in_psram %} + _last_psram_location = .; + } > psram + {%- elif flash_present %} + } > rom + {%- else %} + } > ram + {% endif %} + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + {%- if psram_present and text_segment_in_psram %} + _last_psram_location = .; + } > psram + {%- elif flash_present %} + } > rom + {%- else %} + } > ram + {% endif %} + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + {%- if psram_present and text_segment_in_psram %} + _last_psram_location = .; + } > psram + {%- elif flash_present %} + } > rom + {%- else %} + } > ram + {% endif %} + __exidx_end = .; + __etext = .; + +{% if data_segment_in_psram %} + {% if psram_present and psram_linker_config_enabled and ram_execution %} + _slpcode = __etext; + + . = _last_ram_location; + + /* Power save & PSRAM driver code */ + .sleep_psram_driver : + { + __sleep_code_start__ = .; + /* _scode is used in code startup code */ + _scode = __sleep_code_start__; + . = ALIGN(4); + KEEP(*(.ramVector)) + *rsi_deepsleep_soc.o(.text*) + *sl_si91x_psram.o(.text*) + *sl_si91x_psram_handle.o(.text*) + *rsi_qspi.o(.text*) + *rsi_pll.o(.text*) + *rsi_egpio.o(.text*) + *rsi_deepsleep_soc.o(.data*) + *sl_si91x_psram.o(.data*) + *sl_si91x_psram_handle.o(.data*) + *rsi_qspi.o(.data*) + *rsi_pll.o(.data*) + *rsi_egpio.o(.data*) + *rsi_hal_mcu_m4_ram.o(.text*) + *rsi_hal_mcu_m4_rom.o(.text*) + *sl_si91x_driver.o(.text*) + *sl_si91x_bus.o(.text*) + *UDMA.o(.text*) + *sl_sleeptimer.o(.text*) + *sl_sleeptimer_hal_si91x_sysrtc.o(.text*) + *rsi_sysrtc.o(.text*) + *sl_si91x_low_power_tickless_mode.o(.text*) + *sli_si91x_multithreaded.o(.text*) + *croutine.o(.text*) + *event_groups.o(.text*) + *list.o(.text*) + *queue.o(.text*) + *cmsis_os2.o(.text*) + *stream_buffer.o(.text*) + *tasks.o(.text*) + *timers.o(.text*) + *freertos_umm_malloc_host.o(.text*) + *malloc_buffers.o(.text*) + *sl_rsi_utility.o(.text*) + *port.o(.text*) + *heap_*.o(.text*) + *ipmu_apis.o(.text*) + *rsi_d_cache.o(.text*) + __sleep_code_end__ = .; + /* _ecode is used in code startup code */ + _ecode = __sleep_code_end__; + _last_ram_location = .; + {%- if text_segment_in_psram %} + } > ram AT> psram + + /* _sidata is used in code startup code */ + _sidata = __etext + (__sleep_code_end__ - __sleep_code_start__); + _last_psram_location = _sidata; + {%- elif data_segment_in_psram %} + } > ram AT> rom + + /* _sidata is used in code startup code */ + _sidata = __etext + (__sleep_code_end__ - __sleep_code_start__); + _last_ram_location = _sidata; + + {%- elif flash_present %} + } > ram AT> rom + {%- else %} + } > ram + + /* _sidata is used in code startup code */ + _sidata = __etext + (__sleep_code_end__ - __sleep_code_start__); + {% endif %} + {%- else %} + /* _sidata is used in code startup code */ + _sidata = __etext; + {% endif %} +{%- else %} + /* _sidata is used in code startup code */ + _sidata = __etext; +{% endif %} + + {%- if psram_present and psram_linker_config_enabled %} + {%- if data_segment_in_psram %} + . = _last_psram_location; + {%- else %} + . = _last_ram_location; + {% endif %} + {% endif %} + + {%- if psram_present and psram_linker_config_enabled %} + .data . : + {%- else %} + .data : + {% endif %} + { + __data_start__ = .; + + /* _sdata is used in startup code */ + _sdata = __data_start__; + + {%- if (ram_execution and not data_segment_in_psram) %} + KEEP(*(.ramVector)) + *rsi_deepsleep_soc.o(.text*) + *sl_si91x_psram.o(.text*) + *sl_si91x_psram_handle.o(.text*) + *rsi_qspi.o(.text*) + *rsi_pll.o(.text*) + *rsi_egpio.o(.text*) + *rsi_deepsleep_soc.o(.data*) + *sl_si91x_psram.o(.data*) + *sl_si91x_psram_handle.o(.data*) + *rsi_qspi.o(.data*) + *rsi_pll.o(.data*) + *rsi_egpio.o(.data*) + *rsi_hal_mcu_m4_ram.o(.text*) + *rsi_hal_mcu_m4_rom.o(.text*) + *sl_si91x_driver.o(.text*) + *sl_si91x_bus.o(.text*) + *UDMA.o(.text*) + *sl_sleeptimer.o(.text*) + *sl_sleeptimer_hal_si91x_sysrtc.o(.text*) + *rsi_sysrtc.o(.text*) + *sl_si91x_low_power_tickless_mode.o(.text*) + *sli_si91x_multithreaded.o(.text*) + *croutine.o(.text*) + *event_groups.o(.text*) + *list.o(.text*) + *queue.o(.text*) + *cmsis_os2.o(.text*) + *stream_buffer.o(.text*) + *tasks.o(.text*) + *timers.o(.text*) + *freertos_umm_malloc_host.o(.text*) + *malloc_buffers.o(.text*) + *sl_rsi_utility.o(.text*) + *port.o(.text*) + *heap_*.o(.text*) + *(.data*) + {%- else %} + *(.data*) + *UDMA.o(.text*) + {% endif %} + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + /* _edata is used in startup code */ + _edata = __data_end__; + {%- if psram_present and data_segment_in_psram and not text_segment_in_psram and flash_present %} + _last_psram_location = .; + } > psram AT> rom + {%- elif psram_present and data_segment_in_psram and text_segment_in_psram %} + _last_psram_location = .; + } > psram + {%- elif psram_present and text_segment_in_psram %} + _last_ram_location = .; + } > ram AT> psram + {%- elif psram_present and psram_linker_config_enabled and flash_present %} + _last_ram_location = .; + } > ram AT> rom + {%- elif flash_present %} + } > ram AT> rom + {%- else %} + } > ram + {% endif %} + + {%- if psram_present and psram_linker_config_enabled %} + {%- if bss_segment_in_psram %} + . = _last_psram_location; + {%- else %} + . = _last_ram_location; + {% endif %} + {% endif %} + + .bss (NOLOAD) : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + {%- if psram_present and bss_segment_in_psram %} + _last_psram_location = .; + } > psram + {%- elif psram_present and psram_linker_config_enabled %} + _last_ram_location = .; + } > ram + {%- else %} + } > ram + {% endif %} + + {%- if psram_present and psram_linker_config_enabled %} + {%- if stack_segment_in_psram %} + . = _last_psram_location; + {%- else %} + . = _last_ram_location; + {% endif %} + {% endif %} + + .stack (NOLOAD): + { + __StackLimit = .; + KEEP(*(.stack*)) + . = ALIGN(4); + __StackTop = .; + PROVIDE(__stack = __StackTop); + {%- if psram_present and stack_segment_in_psram %} + _last_psram_location = .; + } > psram + {%- elif psram_present and psram_linker_config_enabled %} + _last_ram_location = .; + } > ram + {%- else %} + } > ram + {% endif %} + + {%- if psram_present and psram_linker_config_enabled %} + {%- if heap_segment_in_psram %} + . = _last_psram_location; + {%- else %} + . = _last_ram_location; + {% endif %} + {% endif %} + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + {%- if psram_present and heap_segment_in_psram %} + . = ORIGIN(psram) + LENGTH(psram); + {%- else %} + . = ORIGIN(ram) + LENGTH(ram); + {% endif %} + __HeapLimit = .; + {%- if psram_present and heap_segment_in_psram %} + _last_psram_location = .; + } > psram + {%- else %} + } > ram + {% endif %} + __heap_size = __HeapLimit - __HeapBase; + + +{%- if flash_present %} +{%- if udma_enable %} + .udma_addr0 : + { + *(.udma_addr0*) + {%- if psram_present and text_segment_in_psram %} + } > udma0 AT> psram + {%- else %} + } > udma0 AT> rom + {% endif %} + + .udma_addr1 : + { + *(.udma_addr1*) + {%- if psram_present and text_segment_in_psram %} + } > udma1 AT> psram + {%- else %} + } > udma1 AT> rom + {%- endif %} +{%- endif %} +{% endif %} +} diff --git a/components/device/silabs/si91x/wireless/ahb_interface/inc/rsi_m4.h b/components/device/silabs/si91x/wireless/ahb_interface/inc/rsi_m4.h index 1fe1f9061..7b76cf112 100644 --- a/components/device/silabs/si91x/wireless/ahb_interface/inc/rsi_m4.h +++ b/components/device/silabs/si91x/wireless/ahb_interface/inc/rsi_m4.h @@ -73,6 +73,14 @@ #define M4_wakeup_TA BIT(0) #define M4_is_active BIT(1) +/*Macro used to define the PTE CRC value of the Firmware 17 Boards*/ +#define FIRMWARE_17_PTE_CRC_VALUE 0 + +/*Macro used to notify TA about M4 XTAL usage*/ +#define TURN_ON_XTAL_REQUEST BIT(9) +#define TURN_OFF_XTAL_REQUEST BIT(10) +#define M4_IS_USING_XTAL_REQUEST BIT(11) + #define ARM_MASK_1 0xE000E100 #define ARM_MASK_1 0xE000E100 #define ARM_MASK_1 0xE000E100 @@ -155,7 +163,6 @@ typedef struct rsi_m4ta_desc_s { uint16_t length; //! descriptor control fields - //rsi_m4ta_desc_dword1_t dword1; } rsi_m4ta_desc_t; @@ -218,6 +225,12 @@ void rsi_update_tx_dma_desc(uint8_t skip_dma_valid); void rsi_update_rx_dma_desc(void); sl_status_t si91x_req_wakeup(void); void sl_si91x_ta_events_init(void); /*Function used to create and initialize event mechanism for TA related events */ - +bool sli_si91x_is_m4_using_xtal(void); +bool sli_si91x_is_xtal_in_use_by_m4(void); +void sli_si91x_set_m4_is_using_xtal(void); +void sli_si91x_set_xtal_in_use_by_m4(void); +void sli_si91x_xtal_turn_on_request_from_m4_to_TA(void); +void sli_si91x_raise_xtal_interrupt_to_ta(uint16_t xtal_enable); +void sli_si91x_send_m4_xtal_usage_notification_to_ta(void); #endif #endif diff --git a/components/device/silabs/si91x/wireless/ahb_interface/inc/sli_siwx917_soc.h b/components/device/silabs/si91x/wireless/ahb_interface/inc/sli_siwx917_soc.h index b695f99cb..f9ead2f67 100644 --- a/components/device/silabs/si91x/wireless/ahb_interface/inc/sli_siwx917_soc.h +++ b/components/device/silabs/si91x/wireless/ahb_interface/inc/sli_siwx917_soc.h @@ -43,7 +43,7 @@ #define HOST_INTERACT_REG_VALID_READ (0xAB << 8) #endif -#define RSI_RESET_LOOP_COUNTER(X) X = 0; +#define RSI_RESET_LOOP_COUNTER(X) X = 0 #define RSI_WHILE_LOOP(X, Y) while ((X++) < (uint32_t)Y) #define RSI_LOOP_COUNT_UPGRADE_IMAGE 0xFFFF #define RSI_LOOP_COUNT_WAKEUP_REQ 0xFFFFFFFF @@ -53,10 +53,10 @@ #define RSI_LOOP_COUNT_UPGRADE_STATUS 0xFFFF #define RSI_LOOP_COUNT_SELECT_OPTION 0xFFFF #define RSI_CHECK_LOOP_COUNTER(X, Y) \ - { \ + do { \ if (X >= Y) \ return -1; \ - } + } while (0) void sli_siwx917_update_system_core_clock(void); void RSI_Set_Cntrls_To_M4(void); @@ -69,4 +69,4 @@ int16_t rsi_select_option(uint8_t cmd); int16_t rsi_bl_select_option(uint8_t cmd); int16_t rsi_boot_insn(uint8_t type, uint16_t *data); int16_t rsi_mem_rd(uint32_t addr, uint16_t len, uint8_t *dBuf); -void sl_si91x_ulp_wakeup_init(void); \ No newline at end of file +void sl_si91x_ulp_wakeup_init(void); diff --git a/components/device/silabs/si91x/wireless/ahb_interface/inc/sli_siwx917_timer.h b/components/device/silabs/si91x/wireless/ahb_interface/inc/sli_siwx917_timer.h index d679a8e2d..e8def6ecc 100644 --- a/components/device/silabs/si91x/wireless/ahb_interface/inc/sli_siwx917_timer.h +++ b/components/device/silabs/si91x/wireless/ahb_interface/inc/sli_siwx917_timer.h @@ -39,7 +39,7 @@ typedef struct { void sl_si91x_timer_expiry_interrupt_handler(void); uint32_t sl_si91x_timer_read_counter(void); void sl_si91x_timer_init(sl_si91x_timer_t *timer, uint32_t duration); -int32_t sl_si91x_timer_expired(sl_si91x_timer_t *timer); -uint32_t sl_si91x_timer_left(sl_si91x_timer_t *timer); +int32_t sl_si91x_timer_expired(const sl_si91x_timer_t *timer); +uint32_t sl_si91x_timer_left(const sl_si91x_timer_t *timer); uint32_t rsi_hal_gettickcount(void); diff --git a/components/device/silabs/si91x/wireless/ahb_interface/src/rsi_hal_mcu_m4_rom.c b/components/device/silabs/si91x/wireless/ahb_interface/src/rsi_hal_mcu_m4_rom.c index bce91947b..e036746b0 100644 --- a/components/device/silabs/si91x/wireless/ahb_interface/src/rsi_hal_mcu_m4_rom.c +++ b/components/device/silabs/si91x/wireless/ahb_interface/src/rsi_hal_mcu_m4_rom.c @@ -21,6 +21,7 @@ #include "sl_device.h" #include "sl_rsi_utility.h" #include "rsi_m4.h" +#include "rsi_ipmu.h" #ifdef SL_WIFI_COMPONENT_INCLUDED #include "sl_si91x_host_interface.h" @@ -33,6 +34,9 @@ osEventFlagsId_t ta_events = NULL; #define SIDE_BAND_DONE (1 << 2) #endif +static bool m4_is_using_xtal_without_ta_notification; +static bool m4_using_xtal; + /** @addtogroup SOC4 * @{ */ @@ -46,7 +50,120 @@ void sli_si91x_raise_pkt_pending_interrupt_to_ta(void) { // Write the packet pending interrupt to TA register M4SS_P2P_INTR_SET_REG = TX_PKT_PENDING_INTERRUPT; - osEventFlagsWait(ta_events, TA_PKT_TX_DONE, (osFlagsWaitAny), osWaitForever); + osEventFlagsWait(ta_events, TA_PKT_TX_DONE, osFlagsWaitAny, osWaitForever); +} +/** + * @fn bool sli_si91x_is_m4_using_xtal(void); + * @brief This API is used to get the whether XTAL is enabled by M4 without notifying TA + * @return true : XTAL is enabled by M4 without notifying TA + * false : XTAL is not enabled by M4 + */ +bool sli_si91x_is_m4_using_xtal(void) +{ + return m4_is_using_xtal_without_ta_notification; +} +/** + * @fn void sli_si91x_set_m4_is_using_xtal(void); + * @brief This API is set XTAL is enabled by M4 without notifying TA + */ +void sli_si91x_set_m4_is_using_xtal(void) +{ + m4_is_using_xtal_without_ta_notification = true; +} + +/** + * @fn bool sli_si91x_is_xtal_in_use_by_m4(void); + * @brief This API is used to get the whether XTAL is used by M4 or any of HP peripherals + * @return true : XTAL is being used by M4 or HP peripherals + * false : XTAL is not being used + */ +bool sli_si91x_is_xtal_in_use_by_m4(void) +{ + return m4_using_xtal; +} + +/** + * @fn void sli_si91x_set_xtal_in_use_by_m4(void); + * @brief This API is used set XTAL is used by M4 or any of HP peripherals + */ +void sli_si91x_set_xtal_in_use_by_m4(void) +{ + m4_using_xtal = true; +} + +/** + * @fn void sli_si91x_xtal_turn_on_request_from_m4_to_TA(void); + * @brief This API is used to Notify TA that M4 requires XTAL clock source + */ +void sli_si91x_xtal_turn_on_request_from_m4_to_TA(void) +{ + if ((TASS_P2P_INTR_CLEAR_REG & TURN_ON_XTAL_REQUEST)) { + clear_ta_to_m4_interrupt(TURN_ON_XTAL_REQUEST); + } else { + /* Set M4 XTAL usage flag */ + sli_si91x_set_xtal_in_use_by_m4(); + + /* Confirm if the TA has completed its initialization process */ + if (sl_si91x_is_device_initialized()) { + /* Raise the turn ON xtal interrupt to TA */ + sli_si91x_raise_xtal_interrupt_to_ta(TURN_ON_XTAL_REQUEST); + /* If M4 is using XTAL then notify TA to turn ON XTAL during programing common flash*/ + sli_si91x_raise_xtal_interrupt_to_ta(M4_IS_USING_XTAL_REQUEST); + } + /*If the 'M4 Enabled XTAL without TA Notification, +* then after net initialization (TA device initialization), a request to turn on the XTAL will be sent to the TA*/ + else { + /* set XTAL is enabled by M4 without notifying TA */ + sli_si91x_set_m4_is_using_xtal(); + } + } +} + +/** + * @fn void sli_si91x_raise_xtal_interrupt_to_ta(uint16_t interrupt_no) + * @brief Raise the turn on/off xtal interrupt to TA + * @param[in] xtal_enable - true to enable xtal, false to disable xtal + * @return void + */ +void sli_si91x_raise_xtal_interrupt_to_ta(uint16_t interrupt_no) +{ + //! Wake up TA + P2P_STATUS_REG |= M4_WAKEUP_TA; + + //!wait for TA active + while (!(P2P_STATUS_REG & TA_IS_ACTIVE)) + ; + + // Write the turn_on_xtal interrupt to TA register + M4SS_P2P_INTR_SET_REG = interrupt_no; + + //! Poll for bit to clear + //!Wait for TA using flash bit + while (!(TASS_P2P_INTR_CLEAR_REG & interrupt_no)) + ; + clear_ta_to_m4_interrupt(interrupt_no); + + sl_si91x_host_clear_sleep_indicator(); +} + +/** + * @fn void sli_si91x_send_m4_xtal_usage_notification_to_ta(void); + * @brief This API sends a notification to the TA indicating whether + * the M4 core is currently utilizing the XTAL as its clock source. + */ +void sli_si91x_send_m4_xtal_usage_notification_to_ta(void) +{ + +#if !(SLI_SI91X_MCU_PSRAM_PRESENT) + /* Check whether M4 is using XTAL */ + if (sli_si91x_is_m4_using_xtal() == true) +#endif + { + /* If M4 is using XTAL then request TA to turn ON XTAL*/ + sli_si91x_raise_xtal_interrupt_to_ta(TURN_ON_XTAL_REQUEST); + /* If M4 is using XTAL then notify TA to turn ON XTAL during programing common flash*/ + sli_si91x_raise_xtal_interrupt_to_ta(M4_IS_USING_XTAL_REQUEST); + } } #ifdef SL_SI91X_SIDE_BAND_CRYPTO diff --git a/components/device/silabs/si91x/wireless/ahb_interface/src/sl_platform.c b/components/device/silabs/si91x/wireless/ahb_interface/src/sl_platform.c index fb27284cd..ac1824cd2 100644 --- a/components/device/silabs/si91x/wireless/ahb_interface/src/sl_platform.c +++ b/components/device/silabs/si91x/wireless/ahb_interface/src/sl_platform.c @@ -50,6 +50,10 @@ void sli_si91x_platform_init(void) // Set P2P Intr priority NVIC_SetPriority(SysTick_IRQn, SYSTICK_INTR_PRI); #endif + //On boot-up, verify the M4_wakeup_TA bit in the P2P status register and clearing the bit if it is set. + if ((P2P_STATUS_REG & M4_wakeup_TA)) { + P2P_STATUS_REG &= ~M4_wakeup_TA; + } } void sl_board_enable_vcom(void) diff --git a/components/device/silabs/si91x/wireless/ahb_interface/src/sl_platform_wireless.c b/components/device/silabs/si91x/wireless/ahb_interface/src/sl_platform_wireless.c index e2edd743c..c65f09828 100644 --- a/components/device/silabs/si91x/wireless/ahb_interface/src/sl_platform_wireless.c +++ b/components/device/silabs/si91x/wireless/ahb_interface/src/sl_platform_wireless.c @@ -197,6 +197,8 @@ void sli_si91x_configure_wireless_frontend_controls(uint32_t switch_sel) RSI_EGPIO_SetPinMux(EGPIO1, 0, GPIO7, 6); #endif break; + default: + break; } #endif } @@ -261,17 +263,16 @@ void sl_si91x_trigger_sleep(SLEEP_TYPE_T sleepType, #if (configUSE_TICKLESS_IDLE == 0) - volatile uint8_t delay; if ((osEventFlagsGet(si91x_events) | osEventFlagsGet(si91x_bus_events) | osEventFlagsGet(si91x_async_events)) #ifdef SL_SI91X_SIDE_BAND_CRYPTO || (osMutexGetOwner(side_band_crypto_mutex) != NULL) #endif - || ((sl_si91x_host_get_queue_packet_count((sl_si91x_queue_type_t)SI91X_COMMON_CMD) - | sl_si91x_host_get_queue_packet_count((sl_si91x_queue_type_t)SI91X_WLAN_CMD) - | sl_si91x_host_get_queue_packet_count((sl_si91x_queue_type_t)SI91X_NETWORK_CMD) - | sl_si91x_host_get_queue_packet_count((sl_si91x_queue_type_t)SI91X_SOCKET_CMD) - | sl_si91x_host_get_queue_packet_count((sl_si91x_queue_type_t)SI91X_BT_CMD) - | sl_si91x_host_get_queue_packet_count((sl_si91x_queue_type_t)SI91X_SOCKET_DATA)))) { + || (sl_si91x_host_get_queue_packet_count((sl_si91x_queue_type_t)SI91X_COMMON_CMD) + | sl_si91x_host_get_queue_packet_count((sl_si91x_queue_type_t)SI91X_WLAN_CMD) + | sl_si91x_host_get_queue_packet_count((sl_si91x_queue_type_t)SI91X_NETWORK_CMD) + | sl_si91x_host_get_queue_packet_count((sl_si91x_queue_type_t)SI91X_SOCKET_CMD) + | sl_si91x_host_get_queue_packet_count((sl_si91x_queue_type_t)SI91X_BT_CMD) + | sl_si91x_host_get_queue_packet_count((sl_si91x_queue_type_t)SI91X_SOCKET_DATA))) { return; } // Disabling the interrupts & clearing m4_is_active as m4 is going to sleep @@ -281,7 +282,7 @@ void sl_si91x_trigger_sleep(SLEEP_TYPE_T sleepType, P2P_STATUS_REG &= ~M4_is_active; P2P_STATUS_REG; // Adding delay to sync m4 with TA - for (delay = 0; delay < 10; delay++) { + for (volatile uint8_t delay = 0; delay < 10; delay++) { __ASM("NOP"); } @@ -318,12 +319,24 @@ void sl_si91x_trigger_sleep(SLEEP_TYPE_T sleepType, printf("RSI_CLK_M4SocClkConfig failed\n"); } + /* Check whether M4 is using XTAL */ + if (sli_si91x_is_xtal_in_use_by_m4() == true) { + /* If M4 is using XTAL then request TA to turn OFF XTAL as M4 is going to sleep */ + sli_si91x_raise_xtal_interrupt_to_ta(TURN_OFF_XTAL_REQUEST); + } + // Configure sleep parameters required by bootloader upon Wake-up - RSI_PS_RetentionSleepConfig(stack_address, (uint32_t)jump_cb_address, vector_offset, mode); + RSI_PS_RetentionSleepConfig(stack_address, jump_cb_address, vector_offset, mode); // Trigger M4 to sleep RSI_PS_EnterDeepSleep(sleepType, lf_clk_mode); + /* Check whether M4 is using XTAL */ + if (sli_si91x_is_xtal_in_use_by_m4() == true) { + /* If M4 is using XTAL then request TA to turn ON XTAL as M4 is going to sleep */ + sli_si91x_raise_xtal_interrupt_to_ta(TURN_ON_XTAL_REQUEST); + } + #ifdef SLI_SI917 // Upon wake up program wireless GPIO frontend switch controls if (frontend_switch_control != 0) { @@ -394,7 +407,7 @@ void sl_si91x_configure_ram_retention(uint32_t rams_in_use, uint32_t rams_retent RSI_PS_M4ssRamBanksPowerDown(rams_to_be_powered_down); /* Turn off Unused SRAM Core/Periphery domains*/ - RSI_PS_M4ssRamBanksPeriPowerDown(rams_in_use); + RSI_PS_M4ssRamBanksPeriPowerDown(rams_to_be_powered_down); /* Clear all RAM retention control before configuring the user RAM retentions*/ RSI_PS_ClrRamRetention(M4ULP_RAM16K_RETENTION_MODE_EN | TA_RAM_RETENTION_MODE_EN | M4ULP_RAM_RETENTION_MODE_EN); @@ -420,4 +433,4 @@ void sl_si91x_configure_ram_retention(uint32_t rams_in_use, uint32_t rams_retent } } -/** @} */ \ No newline at end of file +/** @} */ diff --git a/components/device/silabs/si91x/wireless/ahb_interface/src/sl_si91x_bus.c b/components/device/silabs/si91x/wireless/ahb_interface/src/sl_si91x_bus.c index 873a9165d..c9f263371 100644 --- a/components/device/silabs/si91x/wireless/ahb_interface/src/sl_si91x_bus.c +++ b/components/device/silabs/si91x/wireless/ahb_interface/src/sl_si91x_bus.c @@ -69,13 +69,13 @@ sl_status_t sli_si91x_submit_rx_pkt(void) rx_desc[0].addr = (M4_MEMORY_OFFSET_ADDRESS + (uint32_t)pkt_buffer); // Fill source address in the TX descriptors - rx_desc[0].length = (16); + rx_desc[0].length = 16; // Fill source address in the TX descriptors rx_desc[1].addr = (M4_MEMORY_OFFSET_ADDRESS + (uint32_t)(pkt_buffer + 16)); // Fill source address in the TX descriptors - rx_desc[1].length = (1600); + rx_desc[1].length = 1600; raise_m4_to_ta_interrupt(RX_BUFFER_VALID); @@ -107,13 +107,13 @@ sl_status_t sl_si91x_bus_write_frame(sl_si91x_packet_t *packet, const uint8_t *p tx_desc[0].addr = (M4_MEMORY_OFFSET_ADDRESS + (uint32_t)&packet->desc[0]); // Fill source address in the TX descriptors - tx_desc[0].length = (16); + tx_desc[0].length = 16; // Fill source address in the TX descriptors tx_desc[1].addr = (M4_MEMORY_OFFSET_ADDRESS + (uint32_t)payloadparam); // Fill source address in the TX descriptors - tx_desc[1].length = (size_param); + tx_desc[1].length = size_param; sli_si91x_raise_pkt_pending_interrupt_to_ta(); diff --git a/components/device/silabs/si91x/wireless/ahb_interface/src/sl_si91x_timer.c b/components/device/silabs/si91x/wireless/ahb_interface/src/sl_si91x_timer.c index 691b53949..caa2c9dac 100644 --- a/components/device/silabs/si91x/wireless/ahb_interface/src/sl_si91x_timer.c +++ b/components/device/silabs/si91x/wireless/ahb_interface/src/sl_si91x_timer.c @@ -18,12 +18,8 @@ /* Include files */ -//#include "rsi_driver.h" -//#include "rsi_timer.h" -//#include "rsi_hal.h" #include "sli_siwx917_timer.h" #include "sl_device.h" -//#include "cmsis_os2.h" /** @addtogroup DRIVER11 * @{ @@ -37,11 +33,6 @@ * */ -//void rsi_timer_expiry_interrupt_handler(void) -//{ -// rsi_driver_cb_non_rom->timer_counter++; -//} - /*==============================================*/ /** * @fn uint32_t rsi_timer_read_counter() @@ -56,7 +47,6 @@ uint32_t sl_si91x_timer_read_counter(void) extern uint32_t SystemCoreClock; #define CYCLES_PER_MILLISECOND (SystemCoreClock / 1000) return DWT->CYCCNT / CYCLES_PER_MILLISECOND; - // return osKernelGetTickCount(); } /*==============================================*/ @@ -85,7 +75,7 @@ void sl_si91x_timer_init(sl_si91x_timer_t *rsi_timer, uint32_t duration) * */ -int32_t sl_si91x_timer_expired(sl_si91x_timer_t *timer) +int32_t sl_si91x_timer_expired(const sl_si91x_timer_t *timer) { if ((sl_si91x_timer_read_counter() - (timer->start_time)) > (timer->timeout)) return 1; @@ -103,7 +93,7 @@ int32_t sl_si91x_timer_expired(sl_si91x_timer_t *timer) * */ -uint32_t sl_si91x_timer_left(sl_si91x_timer_t *timer) +uint32_t sl_si91x_timer_left(const sl_si91x_timer_t *timer) { int32_t left = (timer->timeout) - (sl_si91x_timer_read_counter() - (timer->start_time)); return (left < 0) ? 0 : left; diff --git a/components/device/silabs/si91x/wireless/ahb_interface/src/sli_siwx917_soc.c b/components/device/silabs/si91x/wireless/ahb_interface/src/sli_siwx917_soc.c index 4832d9399..83d661b97 100644 --- a/components/device/silabs/si91x/wireless/ahb_interface/src/sli_siwx917_soc.c +++ b/components/device/silabs/si91x/wireless/ahb_interface/src/sli_siwx917_soc.c @@ -49,30 +49,6 @@ typedef struct { #define SI91X_PING_BUFFER ((sli_si91x_pingpong_buffer_t *)(0x19000)) #define SI91X_PONG_BUFFER ((sli_si91x_pingpong_buffer_t *)(0x1A000)) -// #if defined(__GNUC__) -// #pragma GCC diagnostic push -// #pragma GCC diagnostic ignored "-Warray-bounds" -// #pragma GCC diagnostic ignored "-Wcast-align" -// #endif // __GNUC__ - -/** - *@} - */ -//static void rsi_mem_wr(uint32_t addr, uint16_t len, uint8_t *dBuf) -//{ -// UNUSED_PARAMETER(len); -// *(uint32_t *)addr = *(uint32_t *)dBuf; -//} - -//void rsi_mem_rd(uint32_t addr, uint16_t len, uint8_t *dBuf) -//{ -// UNUSED_PARAMETER(len); -// *(uint32_t *)dBuf = *(uint32_t *)addr; -//} -// #if defined(__GNUC__) -// #pragma GCC diagnostic pop -// #endif // __GNUC__ - /** * @fn int16_t rsi_bl_select_option(uint8_t cmd) * @brief Send firmware load request to module or update default configurations. @@ -193,55 +169,13 @@ int16_t sli_si91x_send_boot_instruction(uint8_t type, uint16_t *data) switch (type) { case RSI_REG_READ: - *data = SI91X_INTERFACE_OUT_REGISTER; + *data = (uint16_t)SI91X_INTERFACE_OUT_REGISTER; break; case RSI_REG_WRITE: SI91X_INTERFACE_IN_REGISTER = *data; break; - // case RSI_PING_WRITE: - // - // for (j = 0; j <= RSI_PING_PONG_CHUNK_SIZE / RSI_HAL_MAX_WR_BUFF_LEN; j++) { - // if (j == RSI_PING_PONG_CHUNK_SIZE / RSI_HAL_MAX_WR_BUFF_LEN) { - // len = (RSI_PING_PONG_CHUNK_SIZE % RSI_HAL_MAX_WR_BUFF_LEN); - // if (len == 0) { - // break; - // } - // } else { - // len = RSI_HAL_MAX_WR_BUFF_LEN; - // } - // rsi_mem_wr(RSI_PING_BUFFER_ADDR + offset, len, (uint8_t *)((uint32_t)data + offset)); - // if (retval < 0) { - // return retval; - // } - // offset += len; - // } - // SI91X_INTERFACE_IN_REGISTER = RSI_PING_AVAIL | RSI_HOST_INTERACT_REG_VALID; - // break; - // case RSI_PONG_WRITE: - // - // for (j = 0; j <= RSI_PING_PONG_CHUNK_SIZE / RSI_HAL_MAX_WR_BUFF_LEN; j++) { - // if (j == RSI_PING_PONG_CHUNK_SIZE / RSI_HAL_MAX_WR_BUFF_LEN) { - // len = (RSI_PING_PONG_CHUNK_SIZE % RSI_HAL_MAX_WR_BUFF_LEN); - // if (len == 0) { - // break; - // } - // } else { - // len = RSI_HAL_MAX_WR_BUFF_LEN; - // } - // retval = rsi_mem_wr(RSI_PONG_BUFFER_ADDR + offset, len, (uint8_t *)((uint32_t)data + offset)); - // if (retval < 0) { - // return retval; - // } - // offset += len; - // } - // // Perform the write operation - // local = (RSI_PONG_AVAIL | RSI_HOST_INTERACT_REG_VALID); - // - // SI91X_INTERFACE_IN_REGISTER = local; - // break; - case BURN_NWP_FW: cmd = BURN_NWP_FW | RSI_HOST_INTERACT_REG_VALID; @@ -250,7 +184,7 @@ int16_t sli_si91x_send_boot_instruction(uint8_t type, uint16_t *data) sl_si91x_timer_init(&timer_instance, 300); do { - read_data = SI91X_INTERFACE_OUT_REGISTER; + read_data = (uint16_t)SI91X_INTERFACE_OUT_REGISTER; if (sl_si91x_timer_expired(&timer_instance)) { return RSI_ERROR_FW_LOAD_OR_UPGRADE_TIMEOUT; } @@ -442,7 +376,7 @@ int16_t rsi_boot_insn(uint8_t type, uint16_t *data) switch (type) { case REG_READ: - *data = SI91X_INTERFACE_OUT_REGISTER; + *data = (uint16_t)SI91X_INTERFACE_OUT_REGISTER; break; case REG_WRITE: @@ -465,7 +399,7 @@ int16_t rsi_boot_insn(uint8_t type, uint16_t *data) RSI_RESET_LOOP_COUNTER(loop_counter); RSI_WHILE_LOOP((uint32_t)loop_counter, RSI_LOOP_COUNT_UPGRADE_IMAGE) { - read_data = SI91X_INTERFACE_OUT_REGISTER; + read_data = (uint16_t)SI91X_INTERFACE_OUT_REGISTER; if (read_data == (RSI_SEND_RPS_FILE | HOST_INTERACT_REG_VALID)) { break; } @@ -484,7 +418,7 @@ int16_t rsi_boot_insn(uint8_t type, uint16_t *data) RSI_RESET_LOOP_COUNTER(loop_counter); RSI_WHILE_LOOP((uint32_t)loop_counter, RSI_LOOP_COUNT_UPGRADE_IMAGE) { - read_data = SI91X_INTERFACE_OUT_REGISTER; + read_data = (uint16_t)SI91X_INTERFACE_OUT_REGISTER; if (read_data == (RSI_SEND_RPS_FILE | HOST_INTERACT_REG_VALID)) { break; } diff --git a/components/device/silabs/si91x/wireless/asynchronous_socket/inc/sl_si91x_socket.h b/components/device/silabs/si91x/wireless/asynchronous_socket/inc/sl_si91x_socket.h index 930698141..6eceb71e9 100644 --- a/components/device/silabs/si91x/wireless/asynchronous_socket/inc/sl_si91x_socket.h +++ b/components/device/silabs/si91x/wireless/asynchronous_socket/inc/sl_si91x_socket.h @@ -205,7 +205,7 @@ int sl_si91x_send_async(int socket, * @note The flags parameter is not currently supported. */ int sl_si91x_sendto(int socket, - uint8_t *buffer, + const uint8_t *buffer, size_t buffer_length, int32_t flags, const struct sockaddr *addr, @@ -235,7 +235,7 @@ int sl_si91x_sendto(int socket, * @note The flags parameter is not currently supported. */ int sl_si91x_sendto_async(int socket, - uint8_t *buffer, + const uint8_t *buffer, size_t buffer_length, int32_t flags, const struct sockaddr *to_addr, @@ -344,7 +344,7 @@ int sl_si91x_select(int nfds, fd_set *readfds, fd_set *writefds, fd_set *exceptfds, - struct timeval *timeout, + const struct timeval *timeout, select_callback callback); /** diff --git a/components/device/silabs/si91x/wireless/asynchronous_socket/src/sl_si91x_socket.c b/components/device/silabs/si91x/wireless/asynchronous_socket/src/sl_si91x_socket.c index 22766d1de..4f4d17a11 100644 --- a/components/device/silabs/si91x/wireless/asynchronous_socket/src/sl_si91x_socket.c +++ b/components/device/silabs/si91x/wireless/asynchronous_socket/src/sl_si91x_socket.c @@ -62,7 +62,7 @@ int sl_si91x_socket_async(int family, int type, int protocol, receive_data_callb return sli_si91x_socket(family, type, protocol, callback); } -int sli_si91x_socket(int family, int type, int protocol, receive_data_callback callback) +static int sli_si91x_socket(int family, int type, int protocol, receive_data_callback callback) { // Validate the socket parameters SET_ERRNO_AND_RETURN_IF_TRUE(family != AF_INET && family != AF_INET6, EAFNOSUPPORT); @@ -84,7 +84,7 @@ int sli_si91x_socket(int family, int type, int protocol, receive_data_callback c // Populate the socket structure with provided parameters and callbacks si91x_socket->type = type; - si91x_socket->local_address.sin6_family = family; + si91x_socket->local_address.sin6_family = (uint8_t)family; si91x_socket->protocol = protocol; si91x_socket->state = INITIALIZED; si91x_socket->recv_data_callback = callback; @@ -95,40 +95,7 @@ int sli_si91x_socket(int family, int type, int protocol, receive_data_callback c int sl_si91x_bind(int socket, const struct sockaddr *addr, socklen_t addr_len) { - // Retrieve the socket using the socket index - si91x_socket_t *si91x_socket = get_si91x_socket(socket); - struct sockaddr_in *socket_address = (struct sockaddr_in *)addr; - - // Check if the socket is valid - SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket == NULL || si91x_socket->state != INITIALIZED, EBADF); - SET_ERRNO_AND_RETURN_IF_TRUE( - (si91x_socket->local_address.sin6_family == AF_INET && addr_len < sizeof(struct sockaddr_in)) - || (si91x_socket->local_address.sin6_family == AF_INET6 && addr_len < sizeof(struct sockaddr_in6)), - EINVAL); - - // Check if the provided address is valid and if the specified port is available - SET_ERRNO_AND_RETURN_IF_TRUE(addr == NULL, EFAULT); - - if (!is_port_available(socket_address->sin_port)) { - SET_ERROR_AND_RETURN(EADDRINUSE); - } - - // Copy the provided address and set the socket state to BOUND - memcpy(&si91x_socket->local_address, - addr, - (addr_len > sizeof(struct sockaddr_in6)) ? sizeof(struct sockaddr_in6) : addr_len); - - si91x_socket->state = BOUND; - - // For UDP sockets, create and send a socket request. - if (si91x_socket->type == SOCK_DGRAM) { - sl_status_t socket_create_request_status = create_and_send_socket_request(socket, SI91X_SOCKET_LUDP, NULL); - SOCKET_VERIFY_STATUS_AND_RETURN(socket_create_request_status, SI91X_NO_ERROR, SI91X_UNDEFINED_ERROR); - - si91x_socket->state = UDP_UNCONNECTED_READY; - } - - return SI91X_NO_ERROR; + return sli_si91x_bind(socket, addr, addr_len); } int sl_si91x_connect(int socket, const struct sockaddr *addr, socklen_t addr_len) @@ -147,7 +114,7 @@ int sl_si91x_listen(int socket, int max_number_of_clients) SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket->type != SOCK_STREAM, EOPNOTSUPP); // Create and send a socket request to make it a TCP server with the specified maximum number of clients - status = create_and_send_socket_request(socket, SI91X_SOCKET_TCP_SERVER, (int *)&max_number_of_clients); + status = create_and_send_socket_request(socket, SI91X_SOCKET_TCP_SERVER, &max_number_of_clients); SOCKET_VERIFY_STATUS_AND_RETURN(status, SI91X_NO_ERROR, SI91X_UNDEFINED_ERROR); si91x_socket->state = LISTEN; @@ -172,25 +139,12 @@ int sl_si91x_accept_async(int socket, accept_callback callback) static int sli_si91x_accept_async(int socket, const struct sockaddr *addr, socklen_t addr_len, accept_callback callback) { - - // Get the server socket associated with the given socket ID - si91x_socket_t *si91x_server_socket = get_si91x_socket(socket); - si91x_socket_t *si91x_client_socket = NULL; - - // Create variables for context and client socket - sl_si91x_socket_context_t *context = NULL; - int *client_socket = NULL; - - // Create an accept request structure and LTCP response structure + sl_status_t status = SL_STATUS_OK; + si91x_socket_t *si91x_server_socket = + get_si91x_socket(socket); // Get the server socket associated with the given socket ID + si91x_socket_t *si91x_client_socket = NULL; sl_si91x_socket_accept_request_t accept_request = { 0 }; - sl_si91x_rsp_ltcp_est_t *ltcp = NULL; - - sl_wifi_buffer_t *buffer = NULL; - sl_si91x_packet_t *packet = NULL; - sl_si91x_wait_period_t wait_time = 0; - - sl_status_t status = SL_STATUS_OK; - int32_t client_socket_id = -1; + int32_t client_socket_id = -1; // Check if the server socket is valid SET_ERRNO_AND_RETURN_IF_TRUE(si91x_server_socket == NULL, EBADF); @@ -210,58 +164,34 @@ static int sli_si91x_accept_async(int socket, const struct sockaddr *addr, sockl memcpy(&si91x_client_socket->local_address, &si91x_server_socket->local_address, sizeof(struct sockaddr_in6)); // Create accept request - accept_request.socket_id = si91x_server_socket->id; + accept_request.socket_id = (uint8_t)si91x_server_socket->id; accept_request.source_port = si91x_server_socket->local_address.sin6_port; - // Set the wait time based on whether a callback is provided - wait_time = - (callback == NULL ? (SL_SI91X_WAIT_FOR_EVER | SL_SI91X_WAIT_FOR_RESPONSE_BIT) : SL_SI91X_RETURN_IMMEDIATELY); - + // Set the callback and client socket ID. + sli_si91x_set_accept_callback(si91x_server_socket, callback, client_socket_id); if (callback != NULL) { - // Set the callback and client socket ID. - sli_si91x_set_accept_callback(callback, client_socket_id); status = sl_si91x_driver_send_async_command(RSI_WLAN_REQ_SOCKET_ACCEPT, SI91X_SOCKET_CMD_QUEUE, &accept_request, sizeof(accept_request)); SOCKET_VERIFY_STATUS_AND_RETURN(status, SL_STATUS_OK, SI91X_UNDEFINED_ERROR); - return SI91X_NO_ERROR; + return SL_STATUS_OK; } else { - status = sl_si91x_driver_send_command(RSI_WLAN_REQ_SOCKET_ACCEPT, - SI91X_SOCKET_CMD_QUEUE, - &accept_request, - sizeof(accept_request), - wait_time, - context, - &buffer); + status = sli_si91x_sync_accept_command(si91x_server_socket, (void *)&accept_request, sizeof(accept_request)); } // If the accept request fails, clean up allocated memory and return an error if (status != SL_STATUS_OK) { - SL_CLEANUP_MALLOC(client_socket); - SL_CLEANUP_MALLOC(context); close(client_socket_id); - if (buffer != NULL) - sl_si91x_host_free_buffer(buffer); SET_ERROR_AND_RETURN(SI91X_UNDEFINED_ERROR); } - // Extract LTCP response from the received buffer - packet = sl_si91x_host_get_buffer_data(buffer, 0, NULL); - ltcp = (sl_si91x_rsp_ltcp_est_t *)packet->data; - - // Handle the accept response and update the client socket's state - handle_accept_response(client_socket_id, ltcp); - sl_si91x_host_free_buffer(buffer); - - if (addr_len <= 0) { - return client_socket_id; + if ((addr != NULL) && (addr_len > 0)) { + memcpy((struct sockaddr *)&addr, + &si91x_client_socket->remote_address, + (addr_len > sizeof(struct sockaddr_in6)) ? sizeof(struct sockaddr_in6) : addr_len); } - memcpy((struct sockaddr *)&addr, - &si91x_client_socket->remote_address, - (addr_len > sizeof(struct sockaddr_in6)) ? sizeof(struct sockaddr_in6) : addr_len); - return client_socket_id; } @@ -282,7 +212,7 @@ int sl_si91x_setsockopt_async(int32_t sockID, SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket == NULL, EBADF); // Check if the option value is not NULL - SET_ERRNO_AND_RETURN_IF_TRUE(option_value == NULL, EFAULT) + SET_ERRNO_AND_RETURN_IF_TRUE(option_value == NULL, EFAULT); switch (option_name) { case SL_SI91X_SO_RCVTIME: { @@ -294,7 +224,7 @@ int sl_si91x_setsockopt_async(int32_t sockID, timeout->tv_usec = 1000; } // Calculate the timeout value in milliseconds - timeout_val = (timeout->tv_usec / 1000) + (timeout->tv_sec * 1000); + timeout_val = (uint16_t)((timeout->tv_usec / 1000) + (timeout->tv_sec * 1000)); // Need to add check here if Synchronous bit map is set (after async socket_id implementation) memcpy(&si91x_socket->read_timeout, @@ -306,14 +236,14 @@ int sl_si91x_setsockopt_async(int32_t sockID, case SL_SI91X_SO_MAXRETRY: { // Set the maximum number of TCP retries memcpy(&si91x_socket->max_tcp_retries, - (uint16_t *)option_value, + (const uint16_t *)option_value, GET_SAFE_MEMCPY_LENGTH(sizeof(si91x_socket->max_tcp_retries), option_len)); break; } case SL_SI91X_SO_MSS: { memcpy(&si91x_socket->mss, - (uint16_t *)option_value, + (const uint16_t *)option_value, GET_SAFE_MEMCPY_LENGTH(sizeof(si91x_socket->mss), option_len)); break; } @@ -321,7 +251,7 @@ int sl_si91x_setsockopt_async(int32_t sockID, case SL_SI91X_SO_TCP_KEEPALIVE: { // Set the TCP keep-alive initial time memcpy(&si91x_socket->tcp_keepalive_initial_time, - (uint16_t *)option_value, + (const uint16_t *)option_value, GET_SAFE_MEMCPY_LENGTH(sizeof(si91x_socket->tcp_keepalive_initial_time), option_len)); break; } @@ -362,10 +292,16 @@ int sl_si91x_setsockopt_async(int32_t sockID, case SL_SI91X_SO_SOCK_VAP_ID: { // Set the VAP ID for the socket - si91x_socket->vap_id = *((uint8_t *)option_value); + si91x_socket->vap_id = *((const uint8_t *)option_value); break; } + case SL_SI91x_SO_TCP_ACK_INDICATION: { + // Enable TCP_ACK_INDICATION + SET_ERRNO_AND_RETURN_IF_TRUE((*(uint8_t *)option_value) != SI91X_SOCKET_FEAT_TCP_ACK_INDICATION, EINVAL); + si91x_socket->socket_bitmap |= SI91X_SOCKET_FEAT_TCP_ACK_INDICATION; + break; + } #ifdef SLI_SI917 case SL_SI91X_SO_SSL_V_1_3_ENABLE: { // Enable SSL version 1.3 for the socket. @@ -376,23 +312,18 @@ int sl_si91x_setsockopt_async(int32_t sockID, } #endif - // case si91x_SO_TCP_ACK_INDICATION:{ - // SET_ERRNO_AND_RETURN_IF_TRUE(*(uint8_t *)option_value !=SI91X_SOCKET_FEAT_TCP_ACK_INDICATION,EINVAL ); - // si91x_socket->ssl_bitmap |= SI91X_SOCKET_FEAT_TCP_ACK_INDICATION; - // break; - // } case SL_SI91X_SO_CERT_INDEX: { SET_ERRNO_AND_RETURN_IF_TRUE( ((*(uint8_t *)option_value < SI91X_CERT_INDEX_0) || (*(uint8_t *)option_value > SI91X_CERT_INDEX_2)), EINVAL); - si91x_socket->certificate_index = *(uint8_t *)option_value; + si91x_socket->certificate_index = *(const uint8_t *)option_value; break; } case SL_SI91X_SO_TLS_SNI: { sl_status_t status = add_server_name_indication_extension(&si91x_socket->sni_extensions, - (si91x_socket_type_length_value_t *)option_value); + (const si91x_socket_type_length_value_t *)option_value); if (status != SL_STATUS_OK) { SET_ERROR_AND_RETURN(ENOMEM); @@ -402,9 +333,10 @@ int sl_si91x_setsockopt_async(int32_t sockID, #ifdef SLI_SI917 case SL_SI91X_SO_MAX_RETRANSMISSION_TIMEOUT_VALUE: { - if (IS_POWER_OF_TWO((*(uint8_t *)option_value)) && ((*(uint8_t *)option_value) < MAX_RETRANSMISSION_TIME_VALUE)) { + if (IS_POWER_OF_TWO((*(uint8_t *)option_value)) + && ((*(const uint8_t *)option_value) < MAX_RETRANSMISSION_TIME_VALUE)) { memcpy(&si91x_socket->max_retransmission_timeout_value, - (uint8_t *)option_value, + (const uint8_t *)option_value, GET_SAFE_MEMCPY_LENGTH(sizeof(si91x_socket->max_retransmission_timeout_value), option_len)); } else { SL_DEBUG_LOG("\n Max retransmission timeout value in between 1 - 32 and " @@ -433,11 +365,11 @@ int sl_si91x_send_async(int socket, int32_t flags, data_transfer_complete_handler callback) { - return sl_si91x_sendto_async(socket, (uint8_t *)buffer, buffer_length, flags, NULL, 0, callback); + return sl_si91x_sendto_async(socket, buffer, buffer_length, flags, NULL, 0, callback); } int sl_si91x_sendto(int socket, - uint8_t *buffer, + const uint8_t *buffer, size_t buffer_length, int32_t flags, const struct sockaddr *addr, @@ -448,11 +380,11 @@ int sl_si91x_sendto(int socket, int sl_si91x_send_large_data(int socket, const uint8_t *buffer, size_t buffer_length, int32_t flags) { - si91x_socket_t *si91x_socket = get_si91x_socket(socket); - int bsd_ret_code = 0; - size_t offset = 0; - size_t chunk_size = 0; - size_t max_len = 0; + const si91x_socket_t *si91x_socket = get_si91x_socket(socket); + int bsd_ret_code = 0; + size_t offset = 0; + size_t chunk_size = 0; + size_t max_len = 0; SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket == NULL, EBADF); SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket->state == RESET || si91x_socket->state == INITIALIZED, EBADF); @@ -485,7 +417,7 @@ int sl_si91x_send_large_data(int socket, const uint8_t *buffer, size_t buffer_le } int sl_si91x_sendto_async(int socket, - uint8_t *buffer, + const uint8_t *buffer, size_t buffer_length, int32_t flags, const struct sockaddr *to_addr, @@ -502,6 +434,9 @@ int sl_si91x_sendto_async(int socket, SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket == NULL, EBADF); SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket->type == SOCK_STREAM && si91x_socket->state != CONNECTED, ENOTCONN); SET_ERRNO_AND_RETURN_IF_TRUE(buffer == NULL, EFAULT); + if (si91x_socket->socket_bitmap & SI91X_SOCKET_FEAT_TCP_ACK_INDICATION) { + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket->is_waiting_on_ack == true, EWOULDBLOCK); + } SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket->state != CONNECTED && to_addr == NULL, EFAULT); // Set the data transfer callback for this socket @@ -520,6 +455,10 @@ int sl_si91x_sendto_async(int socket, : DEFAULT_STREAM_MSS_SIZE_IPV6; SET_ERRNO_AND_RETURN_IF_TRUE(buffer_length > max_size, EMSGSIZE); } + if (si91x_socket->socket_bitmap & SI91X_SOCKET_FEAT_TCP_ACK_INDICATION) { + // When using SOCK_STREAM (TCP), socket will wait for an ack if the SI91X_SOCKET_FEAT_TCP_ACK_INDICATION bit is set. + si91x_socket->is_waiting_on_ack = true; + } } else if (si91x_socket->type == SOCK_DGRAM) { // For SOCK_DGRAM (UDP), check the message size against the default maximum size size_t max_size = (si91x_socket->local_address.sin6_family == AF_INET) ? DEFAULT_DATAGRAM_MSS_SIZE_IPV4 @@ -528,7 +467,7 @@ int sl_si91x_sendto_async(int socket, } if (si91x_socket->type == SOCK_DGRAM && (si91x_socket->state == BOUND || si91x_socket->state == INITIALIZED)) { - sl_status_t status = create_and_send_socket_request(socket, SI91X_SOCKET_LUDP, NULL); + status = create_and_send_socket_request(socket, SI91X_SOCKET_LUDP, NULL); SET_ERRNO_AND_RETURN_IF_TRUE(status != SL_STATUS_OK, SI91X_UNDEFINED_ERROR); si91x_socket->state = UDP_UNCONNECTED_READY; @@ -542,15 +481,15 @@ int sl_si91x_sendto_async(int socket, si91x_socket->state == UDP_UNCONNECTED_READY && ((si91x_socket->local_address.sin6_family == AF_INET && to_addr_len < sizeof(struct sockaddr_in)) || (si91x_socket->local_address.sin6_family == AF_INET6 && to_addr_len < sizeof(struct sockaddr_in6))), - EINVAL) + EINVAL); // create a socket send request if (si91x_socket->local_address.sin6_family == AF_INET6) { // If the socket uses IPv6, set the IP version and destination IPv6 address - struct sockaddr_in6 *socket_address = (struct sockaddr_in6 *)to_addr; - request.ip_version = SL_IPV6_ADDRESS_LENGTH; + const struct sockaddr_in6 *socket_address = (const struct sockaddr_in6 *)to_addr; + request.ip_version = SL_IPV6_ADDRESS_LENGTH; request.data_offset = (si91x_socket->type == SOCK_STREAM) ? TCP_V6_HEADER_LENGTH : UDP_V6_HEADER_LENGTH; - uint8_t *destination_ip = + const uint8_t *destination_ip = (si91x_socket->state == UDP_UNCONNECTED_READY || to_addr_len >= sizeof(struct sockaddr_in6)) ? socket_address->sin6_addr.__u6_addr.__u6_addr8 : si91x_socket->remote_address.sin6_addr.__u6_addr.__u6_addr8; @@ -561,22 +500,25 @@ int sl_si91x_sendto_async(int socket, struct sockaddr_in *socket_address = (struct sockaddr_in *)to_addr; request.ip_version = SL_IPV4_ADDRESS_LENGTH; request.data_offset = (si91x_socket->type == SOCK_STREAM) ? TCP_HEADER_LENGTH : UDP_HEADER_LENGTH; - uint32_t *destination_ip = + uint32_t destination_ip = (si91x_socket->state == UDP_UNCONNECTED_READY || to_addr_len >= sizeof(struct sockaddr_in)) - ? &socket_address->sin_addr.s_addr - : &((struct sockaddr_in *)&si91x_socket->remote_address)->sin_addr.s_addr; + ? socket_address->sin_addr.s_addr + : ((struct sockaddr_in *)&si91x_socket->remote_address)->sin_addr.s_addr; - memcpy(&request.dest_ip_addr.ipv4_address[0], destination_ip, SL_IPV4_ADDRESS_LENGTH); + memcpy(&request.dest_ip_addr.ipv4_address[0], &destination_ip, SL_IPV4_ADDRESS_LENGTH); } // Set other parameters in the send request - request.socket_id = si91x_socket->id; - request.dest_port = ((si91x_socket->state == UDP_UNCONNECTED_READY || to_addr_len > 0)) - ? ((struct sockaddr_in *)to_addr)->sin_port + request.socket_id = (uint16_t)si91x_socket->id; + request.dest_port = (si91x_socket->state == UDP_UNCONNECTED_READY || to_addr_len > 0) + ? ((const struct sockaddr_in *)to_addr)->sin_port : si91x_socket->remote_address.sin6_port; request.length = buffer_length; // Send the socket data status = sl_si91x_driver_send_socket_data(&request, buffer, 0); + if (status != SL_STATUS_OK && (si91x_socket->socket_bitmap & SI91X_SOCKET_FEAT_TCP_ACK_INDICATION)) { + si91x_socket->is_waiting_on_ack = false; + } SOCKET_VERIFY_STATUS_AND_RETURN(status, SL_STATUS_OK, ENOBUFS); return buffer_length; @@ -584,7 +526,7 @@ int sl_si91x_sendto_async(int socket, int sl_si91x_recv(int socket, uint8_t *buf, size_t buf_len, int32_t flags) { - return recvfrom(socket, buf, buf_len, flags, NULL, NULL); + return sl_si91x_recvfrom(socket, buf, buf_len, flags, NULL, NULL); } int sl_si91x_recvfrom(int socket, @@ -597,14 +539,14 @@ int sl_si91x_recvfrom(int socket, UNUSED_PARAMETER(flags); // Initialize variables for socket communication - sl_si91x_wait_period_t wait_time = 0; - sl_si91x_req_socket_read_t request = { 0 }; - uint32_t event = NCP_HOST_SOCKET_RESPONSE_EVENT; - ssize_t bytes_read = 0; - si91x_rsp_socket_recv_t *response = NULL; - si91x_socket_t *si91x_socket = get_si91x_socket(socket); - sl_wifi_buffer_t *buffer = NULL; - void *sdk_context = NULL; + sl_si91x_wait_period_t wait_time = 0; + sl_si91x_req_socket_read_t request = { 0 }; + uint32_t event = NCP_HOST_SOCKET_RESPONSE_EVENT; + ssize_t bytes_read = 0; + sl_si91x_socket_metadata_t *response = NULL; + si91x_socket_t *si91x_socket = get_si91x_socket(socket); + sl_wifi_buffer_t *buffer = NULL; + void *sdk_context = NULL; // Check if the socket is valid SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket == NULL, EBADF); @@ -614,7 +556,7 @@ int sl_si91x_recvfrom(int socket, SET_ERRNO_AND_RETURN_IF_TRUE(buf == NULL, EFAULT); // Check if the specified buffer length is valid - SET_ERRNO_AND_RETURN_IF_TRUE(buf_len <= 0, EINVAL) + SET_ERRNO_AND_RETURN_IF_TRUE(buf_len <= 0, EINVAL); // create and send a socket request to configure it as UDP. if (si91x_socket->type == SOCK_DGRAM && (si91x_socket->state == BOUND || si91x_socket->state == INITIALIZED)) { @@ -625,7 +567,7 @@ int sl_si91x_recvfrom(int socket, } // Possible states are only reset and disconnected. - SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket->state != CONNECTED && si91x_socket->state != UDP_UNCONNECTED_READY, EBADF) + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket->state != CONNECTED && si91x_socket->state != UDP_UNCONNECTED_READY, EBADF); // Limit the buffer length based on the socket type if (si91x_socket->type == SOCK_STREAM) { @@ -639,7 +581,7 @@ int sl_si91x_recvfrom(int socket, } // Initialize the socket read request with the socket ID and requested buffer length - request.socket_id = si91x_socket->id; + request.socket_id = (uint8_t)si91x_socket->id; sdk_context = &(request.socket_id); memcpy(request.requested_bytes, &buf_len, sizeof(buf_len)); wait_time = (SL_SI91X_WAIT_FOR_EVER | SL_SI91X_WAIT_FOR_RESPONSE_BIT); @@ -660,7 +602,7 @@ int sl_si91x_recvfrom(int socket, sl_si91x_host_free_buffer(buffer); } - SOCKET_VERIFY_STATUS_AND_RETURN(status, SL_STATUS_OK, SI91X_UNDEFINED_ERROR) + SOCKET_VERIFY_STATUS_AND_RETURN(status, SL_STATUS_OK, SI91X_UNDEFINED_ERROR); // Determine the number of bytes read, considering the buffer length and response length bytes_read = (response->length <= buf_len) ? response->length : buf_len; @@ -700,13 +642,21 @@ int sl_si91x_select(int nfds, fd_set *readfds, fd_set *writefds, fd_set *exceptfds, - struct timeval *timeout, + const struct timeval *timeout, select_callback callback) { UNUSED_PARAMETER(exceptfds); sl_status_t status = SL_STATUS_OK; + if (callback == NULL) { + int total_fd_set_count = select(nfds, readfds, writefds, exceptfds, timeout); + if (total_fd_set_count == 0 || total_fd_set_count == -1) { + return SI91X_UNDEFINED_ERROR; + } + return SI91X_NO_ERROR; + } + // Define a structure to hold the select request parameters sl_si91x_socket_select_req_t request = { 0 }; @@ -732,7 +682,7 @@ int sl_si91x_select(int nfds, for (uint8_t host_socket_index = 0; host_socket_index < nfds; host_socket_index++) { // Retrieve the si91x_socket associated with the host socket index - si91x_socket_t *socket = get_si91x_socket(host_socket_index); + const si91x_socket_t *socket = get_si91x_socket(host_socket_index); // Throw error if the socket file descriptor set by developer is not valid if (socket == NULL @@ -747,30 +697,26 @@ int sl_si91x_select(int nfds, continue; } - if (readfds != NULL) { - // Check if the socket is set for read operations in the readfds set - if (FD_ISSET(host_socket_index, readfds)) { - // Set the corresponding bit in the read file descriptor set - request.read_fds.fd_array[0] |= (1U << socket->id); - } + // Check if the socket is set for read operations in the readfds set + // Set the corresponding bit in the read file descriptor set + if ((readfds != NULL) && (FD_ISSET(host_socket_index, readfds))) { + request.read_fds.fd_array[0] |= (1U << socket->id); } - if (writefds != NULL) { - // Check if the socket is set for write operations in the writefds set - if (FD_ISSET(host_socket_index, writefds)) { - // Set the corresponding bit in the write file descriptor set - request.write_fds.fd_array[0] |= (1U << socket->id); - } + // Check if the socket is set for write operations in the writefds set + // Set the corresponding bit in the write file descriptor set + if ((writefds != NULL) && (FD_ISSET(host_socket_index, writefds))) { + request.write_fds.fd_array[0] |= (1U << socket->id); } // Update the maximum file descriptor number encountered if (request.num_fd <= socket->id) { - request.num_fd = socket->id + 1; + request.num_fd = (uint8_t)(socket->id + 1); } } // Check if a timeout value is provided - if (timeout != NULL && ((timeout->tv_sec != 0) || (timeout->tv_usec != 0))) { + if (timeout != NULL) { request.select_timeout.tv_sec = timeout->tv_sec; request.select_timeout.tv_usec = timeout->tv_usec; } else { diff --git a/components/device/silabs/si91x/wireless/ble/inc/rsi_ble.h b/components/device/silabs/si91x/wireless/ble/inc/rsi_ble.h index 5c0daebc2..89b593f20 100644 --- a/components/device/silabs/si91x/wireless/ble/inc/rsi_ble.h +++ b/components/device/silabs/si91x/wireless/ble/inc/rsi_ble.h @@ -48,7 +48,6 @@ #define BLE_AE_REPORTING_ENABLED 0x00 #define BLE_AE_PERODIC_DUPLICATE_FILTERING_ENABLED 0x01 #define BLE_AE_PERODIC_DUPLICATE_FILTERING_DISABLED 0x00 -#define BLE_AE_PERIODIC_LIST_NOT_USED 0x00 #define BLE_AE_PERIODIC_LIST_USED 0x01 /****************************************************** @@ -1067,9 +1066,6 @@ typedef struct rsi_ble_get_local_att_value_s { typedef struct rsi_ble_gatt_read_response_s { //uint8[6], remote device address. uint8_t dev_addr[RSI_DEV_ADDR_LEN]; - //uint8[2], attribute handle. - // uint16_t handle; - // uint16_t offset; uint8_t type; uint8_t reserved; //uint8[2], attribute value length. @@ -1130,12 +1126,10 @@ typedef struct rsi_ble_att_error_response_s { uint8_t err_code; } rsi_ble_att_error_response_t; -//accept list(cmd), cmd_ix = 0x00AB typedef struct rsi_ble_gatt_remove_serv_s { uint32_t serv_hndler; } rsi_ble_gatt_remove_serv_t; -//accept list(cmd), cmd_ix = 0x00AC typedef struct rsi_ble_gatt_remove_att_s { uint32_t serv_hndler; uint16_t att_hndl; @@ -1160,11 +1154,11 @@ typedef struct rsi_ble_mtu_exchange_resp_s { } rsi_ble_mtu_exchange_resp_t; typedef struct rsi_ble_ae_get_supported_no_of_adv_sets_s { - uint16_t reserved; //sets_cnt; + uint16_t reserved; } SL_ATTRIBUTE_PACKED rsi_ble_ae_get_supported_no_of_adv_sets_t; typedef struct rsi_ble_ae_read_supported_max_adv_data_s { - uint16_t reserved; //max_adv_data_len; + uint16_t reserved; } SL_ATTRIBUTE_PACKED rsi_ble_ae_read_supported_max_adv_data_t; // AE Set Random Address (cmd), cmd_ix = @@ -1432,7 +1426,6 @@ typedef struct rsi_ble_ae_set_scan_enable_s { uint16_t period; } SL_ATTRIBUTE_PACKED rsi_ble_ae_set_scan_enable_t; -//#pragma pack(push, 1) typedef struct rsi_ble_ae_set_periodic_adv_create_sync_s { /** uint8_t, Options field, The Options parameter is used to determine whether the Periodic Advertiser List is used @@ -1630,7 +1623,6 @@ typedef struct rsi_ble_ae_pdu { rsi_ble_ae_extended_create_connect_t extended_create_conn; - //uint8_t data[1]; } SL_ATTRIBUTE_PACKED pdu_type; } SL_ATTRIBUTE_PACKED rsi_ble_ae_pdu_t; diff --git a/components/device/silabs/si91x/wireless/ble/inc/rsi_ble_apis.h b/components/device/silabs/si91x/wireless/ble/inc/rsi_ble_apis.h index bac477ee7..8b8c0ba48 100644 --- a/components/device/silabs/si91x/wireless/ble/inc/rsi_ble_apis.h +++ b/components/device/silabs/si91x/wireless/ble/inc/rsi_ble_apis.h @@ -1620,7 +1620,7 @@ int32_t rsi_ble_start_advertising(void); * 0x4046 - Invalid Arguments * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . */ -int32_t rsi_ble_start_advertising_with_values(void *rsi_ble_adv); +int32_t rsi_ble_start_advertising_with_values(const void *rsi_ble_adv); /*==============================================*/ /** @@ -1640,7 +1640,7 @@ int32_t rsi_ble_start_advertising_with_values(void *rsi_ble_adv); * -4 - Buffer not available to serve the command * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . */ -int32_t rsi_ble_encrypt(uint8_t *key, uint8_t *data, uint8_t *resp); +int32_t rsi_ble_encrypt(const uint8_t *key, const uint8_t *data, uint8_t *resp); /*==============================================*/ /** @@ -1677,7 +1677,7 @@ int32_t rsi_ble_stop_advertising(void); * @note The maximum length of advertising data payload is 31 bytes. * @note The basic format of advertising payload record contains length and data. */ -int32_t rsi_ble_set_advertise_data(uint8_t *data, uint16_t data_len); +int32_t rsi_ble_set_advertise_data(const uint8_t *data, uint16_t data_len); /*========================================================*/ /** @@ -1694,7 +1694,7 @@ int32_t rsi_ble_set_advertise_data(uint8_t *data, uint16_t data_len); * -4 - Buffer not available to serve the command * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . */ -int32_t rsi_ble_set_scan_response_data(uint8_t *data, uint16_t data_len); +int32_t rsi_ble_set_scan_response_data(const uint8_t *data, uint16_t data_len); /*==============================================*/ /** @@ -1816,7 +1816,7 @@ int32_t rsi_ble_stop_scanning(void); * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . */ int32_t rsi_ble_connect_with_params(uint8_t remote_dev_addr_type, - int8_t *remote_dev_addr, + const int8_t *remote_dev_addr, uint16_t scan_interval, uint16_t scan_window, uint16_t conn_interval_max, @@ -1845,7 +1845,7 @@ int32_t rsi_ble_connect_with_params(uint8_t remote_dev_addr_type, * @note To recover from this situation, the application can implement a timeout and call rsi_ble_connect_cancel() to cancel the connection request. * @note Subsequent calls of this command have to wait for the ongoing command to complete. */ -int32_t rsi_ble_connect(uint8_t remote_dev_addr_type, int8_t *remote_dev_addr); +int32_t rsi_ble_connect(uint8_t remote_dev_addr_type, const int8_t *remote_dev_addr); /*==============================================*/ /** @@ -1921,7 +1921,7 @@ int32_t rsi_ble_enhance_connect_with_params(void *ble_enhance_conn_params); * - 0x4E02 - Unknown Connection Identifier * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . */ -int32_t rsi_ble_connect_cancel(int8_t *remote_dev_address); +int32_t rsi_ble_connect_cancel(const int8_t *remote_dev_address); /*==============================================*/ /** @@ -1939,7 +1939,7 @@ int32_t rsi_ble_connect_cancel(int8_t *remote_dev_address); * 0x4D04 BLE not connected * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . */ -int32_t rsi_ble_disconnect(int8_t *remote_dev_address); +int32_t rsi_ble_disconnect(const int8_t *remote_dev_address); /*==============================================*/ /** @@ -1994,7 +1994,7 @@ int32_t rsi_ble_set_smp_pairing_cap_data(rsi_ble_set_smp_pairing_capabilty_data_ * - Non-Zero Value - Failure * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . */ -int32_t rsi_ble_set_local_irk_value(uint8_t *l_irk); +int32_t rsi_ble_set_local_irk_value(const uint8_t *l_irk); /*==============================================*/ /** @@ -2015,7 +2015,7 @@ int32_t rsi_ble_set_local_irk_value(uint8_t *l_irk); * - 0x4E02 - Unknown Connection Identifier * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . */ -int32_t rsi_ble_conn_param_resp(uint8_t *remote_dev_address, uint8_t status); +int32_t rsi_ble_conn_param_resp(const uint8_t *remote_dev_address, uint8_t status); /*==============================================*/ /** @@ -2092,7 +2092,7 @@ int32_t rsi_ble_smp_pair_failed(uint8_t *remote_dev_address, uint8_t reason); * - 0x4D04 BLE not connected * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . */ -int32_t rsi_ble_ltk_req_reply(uint8_t *remote_dev_address, uint8_t reply_type, uint8_t *ltk); +int32_t rsi_ble_ltk_req_reply(uint8_t *remote_dev_address, uint8_t reply_type, const uint8_t *ltk); /*==============================================*/ /** @@ -2225,7 +2225,7 @@ int32_t rsi_ble_clear_acceptlist(void); * @note Maximum number of device address that firmware can store is 10. * Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . */ -int32_t rsi_ble_addto_acceptlist(int8_t *dev_address, uint8_t dev_addr_type); +int32_t rsi_ble_addto_acceptlist(const int8_t *dev_address, uint8_t dev_addr_type); /*==============================================*/ /** @@ -2242,7 +2242,7 @@ int32_t rsi_ble_addto_acceptlist(int8_t *dev_address, uint8_t dev_addr_type); * - -4 - Buffer not available to serve the command * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . */ -int32_t rsi_ble_deletefrom_acceptlist(int8_t *dev_address, uint8_t dev_addr_type); +int32_t rsi_ble_deletefrom_acceptlist(const int8_t *dev_address, uint8_t dev_addr_type); /*==============================================*/ /** * @fn int32_t rsi_ble_resolvlist(uint8_t process_type, @@ -2273,8 +2273,8 @@ int32_t rsi_ble_deletefrom_acceptlist(int8_t *dev_address, uint8_t dev_addr_type int32_t rsi_ble_resolvlist(uint8_t process_type, uint8_t remote_dev_addr_type, uint8_t *remote_dev_address, - uint8_t *peer_irk, - uint8_t *local_irk); + const uint8_t *peer_irk, + const uint8_t *local_irk); /*==============================================*/ /** @@ -2345,7 +2345,7 @@ int32_t rsi_ble_set_privacy_mode(uint8_t remote_dev_addr_type, uint8_t *remote_d * Non-Zero Value - Failure * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . */ -int32_t rsi_ble_readphy(int8_t *remote_dev_address, rsi_ble_resp_read_phy_t *resp); +int32_t rsi_ble_readphy(const int8_t *remote_dev_address, rsi_ble_resp_read_phy_t *resp); /*==============================================*/ /** @@ -2379,7 +2379,7 @@ int32_t rsi_ble_readphy(int8_t *remote_dev_address, rsi_ble_resp_read_phy_t *res * - 0x4D04 BLE not connected * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . */ -int32_t rsi_ble_setphy(int8_t *remote_dev_address, uint8_t tx_phy, uint8_t rx_phy, uint16_t coded_phy); +int32_t rsi_ble_setphy(const int8_t *remote_dev_address, uint8_t tx_phy, uint8_t rx_phy, uint16_t coded_phy); /*==============================================*/ /** @@ -2415,7 +2415,7 @@ int32_t rsi_ble_setphy(int8_t *remote_dev_address, uint8_t tx_phy, uint8_t rx_ph Max supported peripheral latency is 32 when Device is in peripheral Role. * */ -int32_t rsi_ble_conn_params_update(uint8_t *remote_dev_address, +int32_t rsi_ble_conn_params_update(const uint8_t *remote_dev_address, uint16_t min_int, uint16_t max_int, uint16_t latency, @@ -2583,7 +2583,7 @@ int32_t rsi_ble_per_receive(struct rsi_ble_per_receive_s *rsi_ble_per_rx); int32_t rsi_ble_accept_list_using_adv_data(uint8_t enable, uint8_t data_compare_index, uint8_t len_for_compare_data, - uint8_t *payload); + const uint8_t *payload); /*==============================================*/ /** @@ -2597,7 +2597,7 @@ int32_t rsi_ble_accept_list_using_adv_data(uint8_t enable, * @return The following values are returned: * void */ -void BT_LE_ADPacketExtract(uint8_t *remote_name, uint8_t *pbuf, uint8_t buf_len); +void BT_LE_ADPacketExtract(uint8_t *remote_name, const uint8_t *pbuf, uint8_t buf_len); /*==============================================*/ /** @@ -2623,7 +2623,7 @@ void BT_LE_ADPacketExtract(uint8_t *remote_name, uint8_t *pbuf, uint8_t buf_len) * - 0x4D04 BLE not connected * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors). */ -int32_t rsi_ble_start_encryption(uint8_t *remote_dev_address, uint16_t ediv, uint8_t *rand, uint8_t *ltk); +int32_t rsi_ble_start_encryption(uint8_t *remote_dev_address, uint16_t ediv, const uint8_t *rand, const uint8_t *ltk); /*==============================================*/ /** @@ -2971,7 +2971,7 @@ int32_t rsi_ble_get_att_value(uint8_t *dev_addr, uint16_t handle, rsi_ble_resp_a */ int32_t rsi_ble_get_multiple_att_values(uint8_t *dev_addr, uint8_t num_of_handlers, - uint16_t *handles, + const uint16_t *handles, rsi_ble_resp_att_value_t *p_att_vals); /*==============================================*/ @@ -3019,7 +3019,7 @@ int32_t rsi_ble_get_long_att_value(uint8_t *dev_addr, * - Non-Zero Value - Failure * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . */ -int32_t rsi_ble_set_att_value(uint8_t *dev_addr, uint16_t handle, uint8_t data_len, uint8_t *p_data); +int32_t rsi_ble_set_att_value(uint8_t *dev_addr, uint16_t handle, uint8_t data_len, const uint8_t *p_data); /*==============================================*/ /** @@ -3043,7 +3043,7 @@ int32_t rsi_ble_set_att_value(uint8_t *dev_addr, uint16_t handle, uint8_t data_l * - 0x4E65 - Invalid Attribute Length When Small Buffer Mode is Configured * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . */ -int32_t rsi_ble_set_att_cmd(uint8_t *dev_addr, uint16_t handle, uint8_t data_len, uint8_t *p_data); +int32_t rsi_ble_set_att_cmd(uint8_t *dev_addr, uint16_t handle, uint8_t data_len, const uint8_t *p_data); /*==============================================*/ /** @@ -3072,7 +3072,7 @@ int32_t rsi_ble_set_long_att_value(uint8_t *dev_addr, uint16_t handle, uint16_t offset, uint8_t data_len, - uint8_t *p_data); + const uint8_t *p_data); /*==============================================*/ /** @@ -3095,7 +3095,11 @@ int32_t rsi_ble_set_long_att_value(uint8_t *dev_addr, * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . * */ -int32_t rsi_ble_prepare_write(uint8_t *dev_addr, uint16_t handle, uint16_t offset, uint8_t data_len, uint8_t *p_data); +int32_t rsi_ble_prepare_write(uint8_t *dev_addr, + uint16_t handle, + uint16_t offset, + uint8_t data_len, + const uint8_t *p_data); /*==============================================*/ /** @@ -3185,7 +3189,7 @@ int32_t rsi_ble_add_attribute(rsi_ble_req_add_att_t *p_attribute); * @note Rule 4: If the services are maintained in the Application/Host, * then need to use \ref rsi_ble_notify_value() API to send the notifications to the remote devices. */ -int32_t rsi_ble_set_local_att_value(uint16_t handle, uint16_t data_len, uint8_t *p_data); +int32_t rsi_ble_set_local_att_value(uint16_t handle, uint16_t data_len, const uint8_t *p_data); /*==============================================*/ /** @@ -3213,7 +3217,7 @@ int32_t rsi_ble_set_local_att_value(uint16_t handle, uint16_t data_len, uint8_t * - 0x4E64 - BLE Buffer already in use * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . */ -int32_t rsi_ble_set_wo_resp_notify_buf_info(uint8_t *dev_addr, uint8_t buf_mode, uint8_t buf_cnt); +int32_t rsi_ble_set_wo_resp_notify_buf_info(const uint8_t *dev_addr, uint8_t buf_mode, uint8_t buf_cnt); /*==============================================*/ /** @@ -3241,7 +3245,7 @@ int32_t rsi_ble_set_wo_resp_notify_buf_info(uint8_t *dev_addr, uint8_t buf_mode, * then need to use \ref rsi_ble_notify_value() API instead of using \ref rsi_ble_set_local_att_value() API * to send the notifications to the remote devices. */ -int32_t rsi_ble_notify_value(uint8_t *dev_addr, uint16_t handle, uint16_t data_len, uint8_t *p_data); +int32_t rsi_ble_notify_value(const uint8_t *dev_addr, uint16_t handle, uint16_t data_len, const uint8_t *p_data); /*==============================================*/ /** @@ -3262,7 +3266,7 @@ int32_t rsi_ble_notify_value(uint8_t *dev_addr, uint16_t handle, uint16_t data_l * - 0x4E60 - Invalid Handle Range * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) */ -int32_t rsi_ble_indicate_value(uint8_t *dev_addr, uint16_t handle, uint16_t data_len, uint8_t *p_data); +int32_t rsi_ble_indicate_value(const uint8_t *dev_addr, uint16_t handle, uint16_t data_len, const uint8_t *p_data); /** @} */ /** @addtogroup BT-LOW-ENERGY4 @@ -3291,7 +3295,7 @@ int32_t rsi_ble_indicate_value(uint8_t *dev_addr, uint16_t handle, uint16_t data * - 0x4E60 - Invalid Handle Range * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) */ -int32_t rsi_ble_indicate_value_sync(uint8_t *dev_addr, uint16_t handle, uint16_t data_len, uint8_t *p_data); +int32_t rsi_ble_indicate_value_sync(const uint8_t *dev_addr, uint16_t handle, uint16_t data_len, const uint8_t *p_data); /*==============================================*/ /** @@ -3306,7 +3310,7 @@ int32_t rsi_ble_indicate_value_sync(uint8_t *dev_addr, uint16_t handle, uint16_t * - 0x4D05 - BLE socket not available * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) */ -int32_t rsi_ble_indicate_confirm(uint8_t *dev_addr); +int32_t rsi_ble_indicate_confirm(const uint8_t *dev_addr); /** @} */ /** @addtogroup BT-LOW-ENERGY5 @@ -3365,7 +3369,7 @@ int32_t rsi_ble_gatt_read_response(uint8_t *dev_addr, uint16_t handle, uint16_t offset, uint16_t length, - uint8_t *p_data); + const uint8_t *p_data); /*==============================================*/ /** @@ -3508,7 +3512,7 @@ int32_t rsi_ble_gatt_prepare_write_response(uint8_t *dev_addr, uint16_t handle, uint16_t offset, uint16_t length, - uint8_t *data); + const uint8_t *data); /** @} */ /** @addtogroup BT-LOW-ENERGY1 @@ -3551,7 +3555,7 @@ int32_t rsi_ble_get_max_no_of_supp_adv_sets(uint8_t *resp); * @return The following values are returned: * - !0 = failure */ -int32_t rsi_ble_set_ae_set_random_address(uint8_t handle, uint8_t *rand_addr); +int32_t rsi_ble_set_ae_set_random_address(uint8_t handle, const uint8_t *rand_addr); /*========================================================*/ /** @@ -3983,7 +3987,7 @@ int32_t rsi_ble_get_att_value_async(uint8_t *dev_addr, uint16_t handle, rsi_ble_ */ int32_t rsi_ble_get_multiple_att_values_async(uint8_t *dev_addr, uint8_t num_of_handlers, - uint16_t *handles, + const uint16_t *handles, rsi_ble_resp_att_value_t *p_att_vals); /*==============================================*/ @@ -4038,7 +4042,7 @@ int32_t rsi_ble_get_long_att_value_async(uint8_t *dev_addr, * - 0x4D05 - BLE Socket not available * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . */ -int32_t rsi_ble_set_att_value_async(uint8_t *dev_addr, uint16_t handle, uint8_t data_len, uint8_t *p_data); +int32_t rsi_ble_set_att_value_async(uint8_t *dev_addr, uint16_t handle, uint8_t data_len, const uint8_t *p_data); /*==============================================*/ /** @@ -4069,7 +4073,7 @@ int32_t rsi_ble_prepare_write_async(uint8_t *dev_addr, uint16_t handle, uint16_t offset, uint8_t data_len, - uint8_t *p_data); + const uint8_t *p_data); /*==============================================*/ /** diff --git a/components/device/silabs/si91x/wireless/ble/inc/rsi_bt_common_apis.h b/components/device/silabs/si91x/wireless/ble/inc/rsi_bt_common_apis.h index 3a8729467..f4dcd6fe1 100644 --- a/components/device/silabs/si91x/wireless/ble/inc/rsi_bt_common_apis.h +++ b/components/device/silabs/si91x/wireless/ble/inc/rsi_bt_common_apis.h @@ -71,7 +71,7 @@ extern "C" { * - 3 - Command is given in wrong state (i.e., not immediate after opermode) * @note This is a blocking API. Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . */ -int32_t rsi_bt_set_bd_addr(uint8_t *dev_addr); +int32_t rsi_bt_set_bd_addr(const uint8_t *dev_addr); /*==============================================*/ /** @@ -86,7 +86,7 @@ int32_t rsi_bt_set_bd_addr(uint8_t *dev_addr); * - Non-Zero Value - Failure * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors). */ -int32_t rsi_bt_set_local_name(uint8_t *local_name); +int32_t rsi_bt_set_local_name(const uint8_t *local_name); /*==============================================*/ /** diff --git a/components/device/silabs/si91x/wireless/ble/inc/rsi_utils.h b/components/device/silabs/si91x/wireless/ble/inc/rsi_utils.h index ed05e76d7..31f9483a4 100644 --- a/components/device/silabs/si91x/wireless/ble/inc/rsi_utils.h +++ b/components/device/silabs/si91x/wireless/ble/inc/rsi_utils.h @@ -53,16 +53,16 @@ * ******************************************************/ void rsi_uint32_to_4bytes(uint8_t *dBuf, uint32_t val); void rsi_uint16_to_2bytes(uint8_t *dBuf, uint16_t val); -uint16_t rsi_bytes2R_to_uint16(uint8_t *dBuf); -uint32_t rsi_bytes4R_to_uint32(uint8_t *dBuf); +uint16_t rsi_bytes2R_to_uint16(const uint8_t *dBuf); +uint32_t rsi_bytes4R_to_uint32(const uint8_t *dBuf); uint8_t *rsi_ascii_dev_address_to_6bytes_rev(uint8_t *hex_addr, int8_t *ascii_mac_address); -uint8_t *rsi_6byte_dev_address_to_ascii(uint8_t *ascii_mac_address, uint8_t *hex_addr); +uint8_t *rsi_6byte_dev_address_to_ascii(uint8_t *ascii_mac_address, const uint8_t *hex_addr); uint8_t convert_lower_case_to_upper_case(uint8_t lwrcase); -void string2array(uint8_t *dst, uint8_t *src, uint32_t length); +void string2array(uint8_t *dst, const uint8_t *src, uint32_t length); int32_t rsi_atoi(const int8_t *str); void rsi_ascii_dot_address_to_4bytes(uint8_t *hexAddr, int8_t *asciiDotAddress); void rsi_ascii_mac_address_to_6bytes(uint8_t *hexAddr, int8_t *asciiMacAddress); -uint64_t ip_to_reverse_hex(char *ip); +uint64_t ip_to_reverse_hex(const char *ip); int8_t rsi_ascii_hex2num(int8_t ascii_hex_in); int8_t rsi_char_hex2dec(int8_t *cBuf); diff --git a/components/device/silabs/si91x/wireless/ble/src/rsi_ble_gap_apis.c b/components/device/silabs/si91x/wireless/ble/src/rsi_ble_gap_apis.c index 0a7acbae1..2c0dbc65d 100644 --- a/components/device/silabs/si91x/wireless/ble/src/rsi_ble_gap_apis.c +++ b/components/device/silabs/si91x/wireless/ble/src/rsi_ble_gap_apis.c @@ -192,7 +192,7 @@ int32_t rsi_ble_start_advertising(void) * 0x4046 - Invalid Arguments * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . */ -int32_t rsi_ble_start_advertising_with_values(void *rsi_ble_adv) +int32_t rsi_ble_start_advertising_with_values(const void *rsi_ble_adv) { SL_PRINTF(SL_RSI_BLE_START_ADV_WITH_VALUES_TRIGGER, BLE, LOG_INFO); rsi_ble_req_adv_t ble_adv = { 0 }; @@ -221,7 +221,7 @@ int32_t rsi_ble_start_advertising_with_values(void *rsi_ble_adv) * -4 - Buffer not available to serve the command * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . */ -int32_t rsi_ble_encrypt(uint8_t *key, uint8_t *data, uint8_t *resp) +int32_t rsi_ble_encrypt(const uint8_t *key, const uint8_t *data, uint8_t *resp) { SL_PRINTF(SL_RSI_BLE_ENCRYPT_TRIGGER, BLE, LOG_INFO); @@ -274,13 +274,13 @@ int32_t rsi_ble_stop_advertising(void) * @note 1. The maximum length of advertising data payload is 31 bytes. \n * 2. The basic format of advertising payload record contains length and data. \n */ -int32_t rsi_ble_set_advertise_data(uint8_t *data, uint16_t data_len) +int32_t rsi_ble_set_advertise_data(const uint8_t *data, uint16_t data_len) { SL_PRINTF(SL_RSI_BLE_SET_ADV_DATA_TRIGGER, BLE, LOG_INFO); rsi_ble_req_adv_data_t ble_adv_data = { 0 }; - ble_adv_data.data_len = RSI_MIN(data_len, sizeof(ble_adv_data.adv_data)); + ble_adv_data.data_len = (uint8_t)(RSI_MIN(data_len, sizeof(ble_adv_data.adv_data))); memcpy(ble_adv_data.adv_data, data, ble_adv_data.data_len); // Send stop advertise command @@ -300,12 +300,12 @@ int32_t rsi_ble_set_advertise_data(uint8_t *data, uint16_t data_len) * -4 - Buffer not available to serve the command * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . */ -int32_t rsi_ble_set_scan_response_data(uint8_t *data, uint16_t data_len) +int32_t rsi_ble_set_scan_response_data(const uint8_t *data, uint16_t data_len) { SL_PRINTF(SL_RSI_BLE_SET_SCAN_RESPONSE_DATA_TRIGGER, BLE, LOG_INFO); rsi_ble_req_scanrsp_data_t ble_scanrsp_data = { 0 }; - ble_scanrsp_data.data_len = RSI_MIN(data_len, sizeof(ble_scanrsp_data.scanrsp_data)); + ble_scanrsp_data.data_len = (uint8_t)(RSI_MIN(data_len, sizeof(ble_scanrsp_data.scanrsp_data))); memcpy(ble_scanrsp_data.scanrsp_data, data, ble_scanrsp_data.data_len); return rsi_bt_driver_send_cmd(RSI_BLE_SET_SCAN_RESPONSE_DATA, &ble_scanrsp_data, NULL); @@ -464,7 +464,7 @@ int32_t rsi_ble_stop_scanning(void) */ int32_t rsi_ble_connect_with_params(uint8_t remote_dev_addr_type, - int8_t *remote_dev_addr, + const int8_t *remote_dev_addr, uint16_t scan_interval, uint16_t scan_window, uint16_t conn_interval_max, @@ -530,7 +530,7 @@ int32_t rsi_ble_connect_with_params(uint8_t remote_dev_addr_type, * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . */ -int32_t rsi_ble_connect(uint8_t remote_dev_addr_type, int8_t *remote_dev_addr) +int32_t rsi_ble_connect(uint8_t remote_dev_addr_type, const int8_t *remote_dev_addr) { SL_PRINTF(SL_RSI_BLE_CONNECT, BLE, LOG_INFO, "ADDRESS_TYPE: %2x", remote_dev_addr_type); @@ -590,7 +590,7 @@ int32_t rsi_ble_enhance_connect_with_params(void *ble_enhance_conn_params) * 0x4E02 - Unknown Connection Identifier \n * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . */ -int32_t rsi_ble_connect_cancel(int8_t *remote_dev_address) +int32_t rsi_ble_connect_cancel(const int8_t *remote_dev_address) { SL_PRINTF(SL_RSI_BLE_CONNECT_CANCEL, BLE, LOG_INFO); @@ -621,7 +621,7 @@ int32_t rsi_ble_connect_cancel(int8_t *remote_dev_address) * 0x4D04 BLE not connected \n * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . */ -int32_t rsi_ble_disconnect(int8_t *remote_dev_address) +int32_t rsi_ble_disconnect(const int8_t *remote_dev_address) { SL_PRINTF(SL_RSI_BLE_DISCONNECT, BLE, LOG_INFO, "ADDRESS: %1x", *remote_dev_address); rsi_ble_req_disconnect_t ble_disconnect = { 0 }; @@ -692,7 +692,7 @@ int32_t rsi_ble_set_smp_pairing_cap_data(rsi_ble_set_smp_pairing_capabilty_data_ * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . */ -int32_t rsi_ble_set_local_irk_value(uint8_t *l_irk) +int32_t rsi_ble_set_local_irk_value(const uint8_t *l_irk) { SL_PRINTF(SL_RSI_BLE_SET_LOCAL_IRK_VALUE, BLE, LOG_INFO); @@ -722,7 +722,7 @@ int32_t rsi_ble_set_local_irk_value(uint8_t *l_irk) * */ -int32_t rsi_ble_conn_param_resp(uint8_t *remote_dev_address, uint8_t status) +int32_t rsi_ble_conn_param_resp(const uint8_t *remote_dev_address, uint8_t status) { SL_PRINTF(SL_RSI_BLE_CONN_PARAM_RESPONSE, BLE, LOG_INFO, "STATUS: %1x", status); @@ -844,7 +844,7 @@ int32_t rsi_ble_smp_pair_failed(uint8_t *remote_dev_address, uint8_t reason) * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . */ -int32_t rsi_ble_ltk_req_reply(uint8_t *remote_dev_address, uint8_t reply_type, uint8_t *ltk) +int32_t rsi_ble_ltk_req_reply(uint8_t *remote_dev_address, uint8_t reply_type, const uint8_t *ltk) { SL_PRINTF(SL_RSI_BLE_LTK_REQ_REPLY, BLE, LOG_INFO, "REPLY_TYPE: %1x", reply_type); @@ -981,7 +981,7 @@ int32_t rsi_ble_get_le_ping_timeout(uint8_t *remote_dev_address, uint16_t *time_ #else memcpy(leping_cmd.dev_addr, (int8_t *)remote_dev_address, 6); #endif - status = rsi_bt_driver_send_cmd(RSI_BLE_GET_LE_PING, &leping_cmd, &le_ping_rsp); + status = (uint16_t)(rsi_bt_driver_send_cmd(RSI_BLE_GET_LE_PING, &leping_cmd, &le_ping_rsp)); if (status == 0) { *time_out = le_ping_rsp.time_out; } @@ -1059,7 +1059,7 @@ int32_t rsi_ble_clear_acceptlist(void) * @note Maximum number of device address that firmware can store is 10. \n Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . */ -int32_t rsi_ble_addto_acceptlist(int8_t *dev_address, uint8_t dev_addr_type) +int32_t rsi_ble_addto_acceptlist(const int8_t *dev_address, uint8_t dev_addr_type) { SL_PRINTF(SL_RSI_BLE_ADD_TO_ACCEPTLIST, BLE, LOG_INFO, "DEVICE_ADDRESS_TYPE: %1x", dev_addr_type); @@ -1088,7 +1088,7 @@ int32_t rsi_ble_addto_acceptlist(int8_t *dev_address, uint8_t dev_addr_type) * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . */ -int32_t rsi_ble_deletefrom_acceptlist(int8_t *dev_address, uint8_t dev_addr_type) +int32_t rsi_ble_deletefrom_acceptlist(const int8_t *dev_address, uint8_t dev_addr_type) { SL_PRINTF(SL_RSI_BLE_DELETEFROM_ACCEPTLIST, BLE, LOG_INFO, "DEVICE_ADDRESS_TYPE: %1x", dev_addr_type); @@ -1133,8 +1133,8 @@ int32_t rsi_ble_deletefrom_acceptlist(int8_t *dev_address, uint8_t dev_addr_type int32_t rsi_ble_resolvlist(uint8_t process_type, uint8_t remote_dev_addr_type, uint8_t *remote_dev_address, - uint8_t *peer_irk, - uint8_t *local_irk) + const uint8_t *peer_irk, + const uint8_t *local_irk) { SL_PRINTF(SL_RSI_BLE_RESOLVLIST, @@ -1250,7 +1250,7 @@ int32_t rsi_ble_set_privacy_mode(uint8_t remote_dev_addr_type, uint8_t *remote_d * Non-Zero Value - Failure * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . */ -int32_t rsi_ble_readphy(int8_t *remote_dev_address, rsi_ble_resp_read_phy_t *resp) +int32_t rsi_ble_readphy(const int8_t *remote_dev_address, rsi_ble_resp_read_phy_t *resp) { SL_PRINTF(SL_RSI_BLE_READPHY, BLE, LOG_INFO); @@ -1295,7 +1295,7 @@ int32_t rsi_ble_readphy(int8_t *remote_dev_address, rsi_ble_resp_read_phy_t *res * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . */ -int32_t rsi_ble_setphy(int8_t *remote_dev_address, uint8_t tx_phy, uint8_t rx_phy, uint16_t coded_phy) +int32_t rsi_ble_setphy(const int8_t *remote_dev_address, uint8_t tx_phy, uint8_t rx_phy, uint16_t coded_phy) { SL_PRINTF(SL_RSI_SETPHY_TRIGGER, BLE, LOG_INFO); @@ -1347,7 +1347,7 @@ int32_t rsi_ble_setphy(int8_t *remote_dev_address, uint8_t tx_phy, uint8_t rx_ph Max supported peripheral latency is 32 when Device is in Peripheral Role. * */ -int32_t rsi_ble_conn_params_update(uint8_t *remote_dev_address, +int32_t rsi_ble_conn_params_update(const uint8_t *remote_dev_address, uint16_t min_int, uint16_t max_int, uint16_t latency, @@ -1614,7 +1614,7 @@ int32_t rsi_ble_vendor_rf_type(uint8_t ble_power_index) int32_t rsi_ble_accept_list_using_adv_data(uint8_t enable, uint8_t data_compare_index, uint8_t len_for_compare_data, - uint8_t *payload) + const uint8_t *payload) { SL_PRINTF(SL_RSI_BLE_ACCEPTLIST_USING_ADV_DATA, BLE, LOG_INFO); @@ -1645,7 +1645,7 @@ int32_t rsi_ble_accept_list_using_adv_data(uint8_t enable, * @return void */ -void BT_LE_ADPacketExtract(uint8_t *remote_name, uint8_t *pbuf, uint8_t buf_len) +void BT_LE_ADPacketExtract(uint8_t *remote_name, const uint8_t *pbuf, uint8_t buf_len) { SL_PRINTF(SL_RSI_BLE_AD_PACKET_EXTRACT, BLE, LOG_INFO); @@ -1706,7 +1706,7 @@ void BT_LE_ADPacketExtract(uint8_t *remote_name, uint8_t *pbuf, uint8_t buf_len) * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . */ -int32_t rsi_ble_start_encryption(uint8_t *remote_dev_address, uint16_t ediv, uint8_t *rand, uint8_t *ltk) +int32_t rsi_ble_start_encryption(uint8_t *remote_dev_address, uint16_t ediv, const uint8_t *rand, const uint8_t *ltk) { SL_PRINTF(SL_RSI_BLE_ENCRYPTION_TRIGGER, BLE, LOG_INFO); @@ -1830,7 +1830,7 @@ int32_t rsi_ble_get_max_adv_data_len(uint8_t *resp) * @section description * This function is used by the host to set the random device address specified by the Random_Address_parameter */ -int32_t rsi_ble_set_ae_set_random_address(uint8_t handle, uint8_t *rand_addr) +int32_t rsi_ble_set_ae_set_random_address(uint8_t handle, const uint8_t *rand_addr) { rsi_ble_ae_pdu_t ae_pdu = { 0 }; diff --git a/components/device/silabs/si91x/wireless/ble/src/rsi_ble_gatt_apis.c b/components/device/silabs/si91x/wireless/ble/src/rsi_ble_gatt_apis.c index 67ea793ed..048440462 100644 --- a/components/device/silabs/si91x/wireless/ble/src/rsi_ble_gatt_apis.c +++ b/components/device/silabs/si91x/wireless/ble/src/rsi_ble_gatt_apis.c @@ -366,21 +366,20 @@ int32_t rsi_ble_get_att_value_async(uint8_t *dev_addr, uint16_t handle, rsi_ble_ int32_t rsi_ble_get_multiple_att_values_async(uint8_t *dev_addr, uint8_t num_of_handlers, - uint16_t *handles, + const uint16_t *handles, rsi_ble_resp_att_value_t *p_att_vals) { SL_PRINTF(SL_RSI_BLE_GET_MULTIPLE_ATT_VALUES_ASYNC, BLE, LOG_INFO, "NUMBER_OF_HANDLERS: %1x", num_of_handlers); rsi_ble_req_multi_att_values_t req_att_vals; memset(&req_att_vals, 0, sizeof(req_att_vals)); - uint8_t ix; #ifdef BD_ADDR_IN_ASCII rsi_ascii_dev_address_to_6bytes_rev(req_att_vals.dev_addr, dev_addr); #else memcpy((uint8_t *)req_att_vals.dev_addr, (int8_t *)dev_addr, 6); #endif - req_att_vals.num_of_handles = RSI_MIN(num_of_handlers, RSI_BLE_MAX_REQ_LIST); - for (ix = 0; ix < req_att_vals.num_of_handles; ix++) { + req_att_vals.num_of_handles = (uint8_t)(RSI_MIN(num_of_handlers, RSI_BLE_MAX_REQ_LIST)); + for (uint8_t ix = 0; ix < req_att_vals.num_of_handles; ix++) { req_att_vals.handles[ix] = handles[ix]; } @@ -452,7 +451,7 @@ int32_t rsi_ble_get_long_att_value_async(uint8_t *dev_addr, * */ -int32_t rsi_ble_set_att_value_async(uint8_t *dev_addr, uint16_t handle, uint8_t data_len, uint8_t *p_data) +int32_t rsi_ble_set_att_value_async(uint8_t *dev_addr, uint16_t handle, uint8_t data_len, const uint8_t *p_data) { SL_PRINTF(SL_RSI_BLE_SET_ATT_VALUE_ASYNC, BLE, LOG_INFO, "HANDLE: %2x, DATA_LEN: %1x", handle, data_len); @@ -464,7 +463,7 @@ int32_t rsi_ble_set_att_value_async(uint8_t *dev_addr, uint16_t handle, uint8_t memcpy((uint8_t *)set_att_val.dev_addr, (int8_t *)dev_addr, 6); #endif rsi_uint16_to_2bytes(set_att_val.handle, handle); - set_att_val.length = RSI_MIN(sizeof(set_att_val.att_value), data_len); + set_att_val.length = (uint8_t)(RSI_MIN(sizeof(set_att_val.att_value), data_len)); memcpy(set_att_val.att_value, p_data, set_att_val.length); return rsi_bt_driver_send_cmd(RSI_BLE_SET_DESCVALUE_ASYNC, &set_att_val, NULL); @@ -498,7 +497,7 @@ int32_t rsi_ble_prepare_write_async(uint8_t *dev_addr, uint16_t handle, uint16_t offset, uint8_t data_len, - uint8_t *p_data) + const uint8_t *p_data) { SL_PRINTF(SL_RSI_BLE_PREPARE_WRITE_ASYNC, @@ -518,7 +517,7 @@ int32_t rsi_ble_prepare_write_async(uint8_t *dev_addr, #endif rsi_uint16_to_2bytes(req_prepare_write.handle, handle); rsi_uint16_to_2bytes(req_prepare_write.offset, offset); - req_prepare_write.length = RSI_MIN(sizeof(req_prepare_write.att_value), data_len); + req_prepare_write.length = (uint8_t)(RSI_MIN(sizeof(req_prepare_write.att_value), data_len)); memcpy(req_prepare_write.att_value, p_data, req_prepare_write.length); return rsi_bt_driver_send_cmd(RSI_BLE_SET_PREPAREWRITE_ASYNC, &req_prepare_write, NULL); @@ -870,20 +869,19 @@ int32_t rsi_ble_get_att_value(uint8_t *dev_addr, uint16_t handle, rsi_ble_resp_a int32_t rsi_ble_get_multiple_att_values(uint8_t *dev_addr, uint8_t num_of_handlers, - uint16_t *handles, + const uint16_t *handles, rsi_ble_resp_att_value_t *p_att_vals) { SL_PRINTF(SL_RSI_BLE_GET_MULTIPLE_ATT_VALUES, BLE, LOG_INFO, "NUMBER_OF_HANDLERS: %1x", num_of_handlers); rsi_ble_req_multi_att_values_t req_att_vals; memset(&req_att_vals, 0, sizeof(req_att_vals)); - uint8_t ix; #ifdef BD_ADDR_IN_ASCII rsi_ascii_dev_address_to_6bytes_rev(req_att_vals.dev_addr, dev_addr); #else memcpy((uint8_t *)req_att_vals.dev_addr, (int8_t *)dev_addr, 6); #endif - req_att_vals.num_of_handles = RSI_MIN(num_of_handlers, RSI_BLE_MAX_REQ_LIST); - for (ix = 0; ix < req_att_vals.num_of_handles; ix++) { + req_att_vals.num_of_handles = (uint8_t)(RSI_MIN(num_of_handlers, RSI_BLE_MAX_REQ_LIST)); + for (uint8_t ix = 0; ix < req_att_vals.num_of_handles; ix++) { req_att_vals.handles[ix] = handles[ix]; } @@ -949,7 +947,7 @@ int32_t rsi_ble_get_long_att_value(uint8_t *dev_addr, * */ -int32_t rsi_ble_set_att_value(uint8_t *dev_addr, uint16_t handle, uint8_t data_len, uint8_t *p_data) +int32_t rsi_ble_set_att_value(uint8_t *dev_addr, uint16_t handle, uint8_t data_len, const uint8_t *p_data) { SL_PRINTF(SL_RSI_BLE_SET_ATT_VALUE, BLE, LOG_INFO); @@ -961,7 +959,7 @@ int32_t rsi_ble_set_att_value(uint8_t *dev_addr, uint16_t handle, uint8_t data_l memcpy((uint8_t *)set_att_val.dev_addr, (int8_t *)dev_addr, 6); #endif rsi_uint16_to_2bytes(set_att_val.handle, handle); - set_att_val.length = RSI_MIN(sizeof(set_att_val.att_value), data_len); + set_att_val.length = (uint8_t)(RSI_MIN(sizeof(set_att_val.att_value), data_len)); memcpy(set_att_val.att_value, p_data, set_att_val.length); return rsi_bt_driver_send_cmd(RSI_BLE_REQ_WRITE, &set_att_val, NULL); @@ -988,7 +986,7 @@ int32_t rsi_ble_set_att_value(uint8_t *dev_addr, uint16_t handle, uint8_t data_l * */ -int32_t rsi_ble_set_att_cmd(uint8_t *dev_addr, uint16_t handle, uint8_t data_len, uint8_t *p_data) +int32_t rsi_ble_set_att_cmd(uint8_t *dev_addr, uint16_t handle, uint8_t data_len, const uint8_t *p_data) { SL_PRINTF(SL_RSI_BLE_SET_ATT_COMMAND, BLE, LOG_INFO, "HANDLE: %2x, DATA_LEN: %1x", handle, data_len); @@ -1000,7 +998,7 @@ int32_t rsi_ble_set_att_cmd(uint8_t *dev_addr, uint16_t handle, uint8_t data_len memcpy((uint8_t *)set_att_cmd.dev_addr, (int8_t *)dev_addr, 6); #endif rsi_uint16_to_2bytes(set_att_cmd.handle, handle); - set_att_cmd.length = RSI_MIN(sizeof(set_att_cmd.att_value), data_len); + set_att_cmd.length = (uint8_t)(RSI_MIN(sizeof(set_att_cmd.att_value), data_len)); memcpy(set_att_cmd.att_value, p_data, set_att_cmd.length); return rsi_bt_driver_send_cmd(RSI_BLE_REQ_WRITE_NO_ACK, &set_att_cmd, NULL); @@ -1033,7 +1031,7 @@ int32_t rsi_ble_set_long_att_value(uint8_t *dev_addr, uint16_t handle, uint16_t offset, uint8_t data_len, - uint8_t *p_data) + const uint8_t *p_data) { SL_PRINTF(SL_RSI_BLE_SET_LONG_ATT_VALUE, @@ -1052,7 +1050,7 @@ int32_t rsi_ble_set_long_att_value(uint8_t *dev_addr, #endif rsi_uint16_to_2bytes(set_long_att.handle, handle); rsi_uint16_to_2bytes(set_long_att.offset, offset); - set_long_att.length = RSI_MIN(sizeof(set_long_att.att_value), data_len); + set_long_att.length = (uint8_t)(RSI_MIN(sizeof(set_long_att.att_value), data_len)); memcpy(set_long_att.att_value, p_data, set_long_att.length); return rsi_bt_driver_send_cmd(RSI_BLE_REQ_LONG_WRITE, &set_long_att, NULL); @@ -1078,7 +1076,11 @@ int32_t rsi_ble_set_long_att_value(uint8_t *dev_addr, * */ -int32_t rsi_ble_prepare_write(uint8_t *dev_addr, uint16_t handle, uint16_t offset, uint8_t data_len, uint8_t *p_data) +int32_t rsi_ble_prepare_write(uint8_t *dev_addr, + uint16_t handle, + uint16_t offset, + uint8_t data_len, + const uint8_t *p_data) { SL_PRINTF(SL_RSI_BLE_PREPARE_WRITE, BLE, @@ -1096,7 +1098,7 @@ int32_t rsi_ble_prepare_write(uint8_t *dev_addr, uint16_t handle, uint16_t offse #endif rsi_uint16_to_2bytes(req_prepare_write.handle, handle); rsi_uint16_to_2bytes(req_prepare_write.offset, offset); - req_prepare_write.length = RSI_MIN(sizeof(req_prepare_write.att_value), data_len); + req_prepare_write.length = (uint8_t)(RSI_MIN(sizeof(req_prepare_write.att_value), data_len)); memcpy(req_prepare_write.att_value, p_data, req_prepare_write.length); return rsi_bt_driver_send_cmd(RSI_BLE_REQ_PREPARE_WRITE, &req_prepare_write, NULL); @@ -1217,14 +1219,14 @@ int32_t rsi_ble_add_attribute(rsi_ble_req_add_att_t *p_attribute) * then need to use \ref rsi_ble_notify_value() API to send the notifications to the remote devices.\n */ -int32_t rsi_ble_set_local_att_value(uint16_t handle, uint16_t data_len, uint8_t *p_data) +int32_t rsi_ble_set_local_att_value(uint16_t handle, uint16_t data_len, const uint8_t *p_data) { SL_PRINTF(SL_RSI_BLE_SET_LOCAL_ATT_VALUE, BLE, LOG_INFO, "HANDLE: %2x", handle); rsi_ble_set_local_att_value_t rec_data = { 0 }; rec_data.handle = handle; - rec_data.data_len = RSI_MIN(data_len, sizeof(rec_data.data)); + rec_data.data_len = (uint16_t)(RSI_MIN(data_len, sizeof(rec_data.data))); memcpy(rec_data.data, p_data, rec_data.data_len); return rsi_bt_driver_send_cmd(RSI_BLE_SET_LOCAL_ATT_VALUE, &rec_data, NULL); @@ -1257,7 +1259,7 @@ int32_t rsi_ble_set_local_att_value(uint16_t handle, uint16_t data_len, uint8_t * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . * */ -int32_t rsi_ble_set_wo_resp_notify_buf_info(uint8_t *dev_addr, uint8_t buf_mode, uint8_t buf_cnt) +int32_t rsi_ble_set_wo_resp_notify_buf_info(const uint8_t *dev_addr, uint8_t buf_mode, uint8_t buf_cnt) { SL_PRINTF(SL_RSI_BLE_SET_WO_RESP_NOTIFY_BUF_INFO, BLE, LOG_INFO, "BUF_MODE: %1x, BUF_COUNT: %1x", buf_mode, buf_cnt); @@ -1298,7 +1300,7 @@ int32_t rsi_ble_set_wo_resp_notify_buf_info(uint8_t *dev_addr, uint8_t buf_mode, * then need to use \ref rsi_ble_notify_value() API instead of using \ref rsi_ble_set_local_att_value() API\n * to send the notifications to the remote devices. */ -int32_t rsi_ble_notify_value(uint8_t *dev_addr, uint16_t handle, uint16_t data_len, uint8_t *p_data) +int32_t rsi_ble_notify_value(const uint8_t *dev_addr, uint16_t handle, uint16_t data_len, const uint8_t *p_data) { SL_PRINTF(SL_RSI_BLE_NOTIFY_VALUE_TRIGGER, BLE, LOG_INFO, "HANDLE: %2x", handle); @@ -1311,7 +1313,7 @@ int32_t rsi_ble_notify_value(uint8_t *dev_addr, uint16_t handle, uint16_t data_l #endif rec_data.handle = handle; - rec_data.data_len = RSI_MIN(data_len, sizeof(rec_data.data)); + rec_data.data_len = (uint16_t)(RSI_MIN(data_len, sizeof(rec_data.data))); memcpy(rec_data.data, p_data, rec_data.data_len); return rsi_bt_driver_send_cmd(RSI_BLE_CMD_NOTIFY, &rec_data, NULL); @@ -1336,7 +1338,7 @@ int32_t rsi_ble_notify_value(uint8_t *dev_addr, uint16_t handle, uint16_t data_l * */ -int32_t rsi_ble_indicate_value(uint8_t *dev_addr, uint16_t handle, uint16_t data_len, uint8_t *p_data) +int32_t rsi_ble_indicate_value(const uint8_t *dev_addr, uint16_t handle, uint16_t data_len, const uint8_t *p_data) { SL_PRINTF(SL_RSI_BLE_INDICATE_VOLUME_TRIGGER, BLE, LOG_INFO); @@ -1349,7 +1351,7 @@ int32_t rsi_ble_indicate_value(uint8_t *dev_addr, uint16_t handle, uint16_t data #endif rec_data.handle = handle; - rec_data.data_len = RSI_MIN(data_len, sizeof(rec_data.data)); + rec_data.data_len = (uint16_t)(RSI_MIN(data_len, sizeof(rec_data.data))); memcpy(rec_data.data, p_data, rec_data.data_len); return rsi_bt_driver_send_cmd(RSI_BLE_CMD_INDICATE, &rec_data, NULL); @@ -1377,7 +1379,7 @@ int32_t rsi_ble_indicate_value(uint8_t *dev_addr, uint16_t handle, uint16_t data * */ -int32_t rsi_ble_indicate_value_sync(uint8_t *dev_addr, uint16_t handle, uint16_t data_len, uint8_t *p_data) +int32_t rsi_ble_indicate_value_sync(const uint8_t *dev_addr, uint16_t handle, uint16_t data_len, const uint8_t *p_data) { SL_PRINTF(SL_RSI_BLE_INDICATE_VALUE_SYNC, BLE, LOG_INFO); @@ -1390,7 +1392,7 @@ int32_t rsi_ble_indicate_value_sync(uint8_t *dev_addr, uint16_t handle, uint16_t #endif rec_data.handle = handle; - rec_data.data_len = RSI_MIN(data_len, sizeof(rec_data.data)); + rec_data.data_len = (uint16_t)(RSI_MIN(data_len, sizeof(rec_data.data))); memcpy(rec_data.data, p_data, rec_data.data_len); return rsi_bt_driver_send_cmd(RSI_BLE_CMD_INDICATE_SYNC, &rec_data, NULL); @@ -1412,7 +1414,7 @@ int32_t rsi_ble_indicate_value_sync(uint8_t *dev_addr, uint16_t handle, uint16_t * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) \n * */ -int32_t rsi_ble_indicate_confirm(uint8_t *dev_addr) +int32_t rsi_ble_indicate_confirm(const uint8_t *dev_addr) { SL_PRINTF(SL_RSI_BLE_INDICATE_CONFIRM, BLE, LOG_INFO); @@ -1489,7 +1491,7 @@ int32_t rsi_ble_gatt_read_response(uint8_t *dev_addr, uint16_t handle, uint16_t offset, uint16_t length, - uint8_t *p_data) + const uint8_t *p_data) { SL_PRINTF(SL_RSI_BLE_GATT_READ_RESPONSE, BLE, LOG_INFO); @@ -1504,8 +1506,8 @@ int32_t rsi_ble_gatt_read_response(uint8_t *dev_addr, memcpy((uint8_t *)local_read_blob_resp.dev_addr, (int8_t *)dev_addr, 6); #endif local_read_blob_resp.type = read_type; - local_read_blob_resp.data_len = RSI_MIN(length, sizeof(local_read_blob_resp.data)); - memcpy(local_read_blob_resp.data, p_data, local_read_blob_resp.data_len); //local_read_blob_resp.data_len); + local_read_blob_resp.data_len = (uint16_t)(RSI_MIN(length, sizeof(local_read_blob_resp.data))); + memcpy(local_read_blob_resp.data, p_data, local_read_blob_resp.data_len); return rsi_bt_driver_send_cmd(RSI_BLE_CMD_READ_RESP, &local_read_blob_resp, NULL); } @@ -1715,7 +1717,7 @@ int32_t rsi_ble_gatt_prepare_write_response(uint8_t *dev_addr, uint16_t handle, uint16_t offset, uint16_t length, - uint8_t *data) + const uint8_t *data) { SL_PRINTF(SL_RSI_BLE_GATT_PREPARE_WRITE_RESPONSE, diff --git a/components/device/silabs/si91x/wireless/ble/src/rsi_bt_ble.c b/components/device/silabs/si91x/wireless/ble/src/rsi_bt_ble.c index f8a36d6f7..cf3b16b99 100644 --- a/components/device/silabs/si91x/wireless/ble/src/rsi_bt_ble.c +++ b/components/device/silabs/si91x/wireless/ble/src/rsi_bt_ble.c @@ -22,23 +22,21 @@ #include "sl_wifi_host_interface.h" #include "sl_si91x_driver.h" +#include "rsi_bt_common.h" +#include "rsi_ble.h" +#include "stdio.h" + +#include "sl_si91x_host_interface.h" + sl_status_t sl_si91x_allocate_command_buffer(sl_wifi_buffer_t **host_buffer, void **buffer, uint32_t requested_buffer_size, uint32_t wait_duration_ms); -uint32_t rsi_get_bt_state(rsi_bt_cb_t *bt_cb); -/* - Include files - */ -#include "rsi_bt_common.h" -#include "rsi_ble.h" -#include "stdio.h" +uint32_t rsi_get_bt_state(const rsi_bt_cb_t *bt_cb); #define BT_SEM 0x1 #define BT_CMD_SEM 0x2 -#include "sl_si91x_host_interface.h" - /* * Global Variables * */ @@ -46,10 +44,10 @@ uint32_t rsi_get_bt_state(rsi_bt_cb_t *bt_cb); // rsi_bt_ble.c function declarations void rsi_bt_common_register_callbacks(rsi_bt_get_ber_pkt_t rsi_bt_get_ber_pkt_from_app); uint32_t rsi_bt_get_timeout(uint16_t cmd_type, uint16_t protocol_type); -uint32_t rsi_bt_get_status(rsi_bt_cb_t *bt_cb); -void rsi_ble_update_le_dev_buf(rsi_ble_event_le_dev_buf_ind_t *rsi_ble_event_le_dev_buf_ind); -void rsi_add_remote_ble_dev_info(rsi_ble_event_enhance_conn_status_t *remote_dev_info); -void rsi_remove_remote_ble_dev_info(rsi_ble_event_disconnect_t *remote_dev_info); +uint32_t rsi_bt_get_status(const rsi_bt_cb_t *bt_cb); +void rsi_ble_update_le_dev_buf(const rsi_ble_event_le_dev_buf_ind_t *rsi_ble_event_le_dev_buf_ind); +void rsi_add_remote_ble_dev_info(const rsi_ble_event_enhance_conn_status_t *remote_dev_info); +void rsi_remove_remote_ble_dev_info(const rsi_ble_event_disconnect_t *remote_dev_info); int32_t rsi_driver_process_bt_resp( rsi_bt_cb_t *bt_cb, sl_si91x_packet_t *pkt, @@ -96,8 +94,6 @@ uint16_t rsi_bt_get_proto_type(uint16_t rsp_type, rsi_bt_cb_t **bt_cb) { SL_PRINTF(SL_RSI_BT_GET_PROTO_TYPE_TRIGGER, BLUETOOTH, LOG_INFO, "RESPONSE_TYPE: %2x", rsp_type); uint16_t return_value = 0xFF; - //static uint16_t local_prototype; - //static rsi_bt_cb_t *local_cb; if (rsp_type == RSI_BLE_EVENT_DISCONNECT) { if (rsi_driver_cb->bt_common_cb->dev_type == RSI_BT_LE_DEVICE) { @@ -106,7 +102,6 @@ uint16_t rsi_bt_get_proto_type(uint16_t rsp_type, rsi_bt_cb_t **bt_cb) } return return_value; - //} } /** @} */ // Determine the protocol type by looking at the packet type @@ -140,11 +135,6 @@ uint16_t rsi_bt_get_proto_type(uint16_t rsp_type, rsi_bt_cb_t **bt_cb) return_value = RSI_PROTO_BLE; *bt_cb = rsi_driver_cb->ble_cb; } - /*if (return_value != RSI_PROTO_BT_COMMON) - { - local_prototype = return_value; - local_cb = *bt_cb; - }*/ return return_value; } @@ -181,15 +171,15 @@ uint32_t rsi_bt_get_timeout(uint16_t cmd_type, uint16_t protocol_type) case RSI_PROTO_BLE: { if (((cmd_type >= RSI_BLE_REQ_ADV) && (cmd_type <= RSI_BLE_SMP_PASSKEY)) || ((cmd_type >= RSI_BLE_SET_ADVERTISE_DATA) && (cmd_type <= RSI_BLE_PER_RX_MODE)) - || ((cmd_type == RSI_BLE_CONN_PARAM_RESP_CMD)) - || ((cmd_type == RSI_BLE_MTU_EXCHANGE_REQUEST) || ((cmd_type == RSI_BLE_CMD_MTU_EXCHANGE_RESP)))) { + || (cmd_type == RSI_BLE_CONN_PARAM_RESP_CMD) + || ((cmd_type == RSI_BLE_MTU_EXCHANGE_REQUEST) || (cmd_type == RSI_BLE_CMD_MTU_EXCHANGE_RESP))) { return_value = RSI_BLE_GAP_CMD_RESP_WAIT_TIME; } else if (((cmd_type >= RSI_BLE_REQ_PROFILES) && (cmd_type <= RSI_BLE_CMD_INDICATE)) || ((cmd_type >= RSI_BLE_CMD_ATT_ERROR) && (cmd_type <= RSI_BLE_SET_SMP_PAIRING_CAPABILITY_DATA)) - || ((cmd_type == RSI_BLE_CMD_INDICATE_CONFIRMATION)) || (cmd_type == RSI_BLE_CMD_INDICATE_SYNC)) { + || (cmd_type == RSI_BLE_CMD_INDICATE_CONFIRMATION) || (cmd_type == RSI_BLE_CMD_INDICATE_SYNC)) { return_value = RSI_BLE_GATT_CMD_RESP_WAIT_TIME; } else { - return_value = RSI_BT_BLE_CMD_MAX_RESP_WAIT_TIME; //RSI_WAIT_FOREVER; + return_value = RSI_BT_BLE_CMD_MAX_RESP_WAIT_TIME; } } break; @@ -222,7 +212,7 @@ void rsi_bt_common_tx_done(sl_si91x_packet_t *pkt) rsp_type = rsi_bytes2R_to_uint16(host_desc + RSI_BT_RSP_TYPE_OFFSET); // Get the protocol Type - protocol_type = rsi_bt_get_proto_type(rsp_type, &bt_cb); + protocol_type = (uint8_t)rsi_bt_get_proto_type(rsp_type, &bt_cb); if (protocol_type == 0xFF) { return; @@ -249,7 +239,7 @@ void rsi_bt_common_tx_done(sl_si91x_packet_t *pkt) * Non-Zero Value - Failure */ -uint32_t rsi_get_bt_state(rsi_bt_cb_t *bt_cb) +uint32_t rsi_get_bt_state(const rsi_bt_cb_t *bt_cb) { SL_PRINTF(SL_RSI_BT_STATE_TRIGGER, BLUETOOTH, LOG_INFO); return bt_cb->state; @@ -278,7 +268,7 @@ void rsi_bt_set_status(rsi_bt_cb_t *bt_cb, int32_t status) * @return 0 - Success \n * Non-Zero Value - Failure */ -uint32_t rsi_bt_get_status(rsi_bt_cb_t *bt_cb) +uint32_t rsi_bt_get_status(const rsi_bt_cb_t *bt_cb) { return bt_cb->status; } @@ -290,14 +280,13 @@ uint32_t rsi_bt_get_status(rsi_bt_cb_t *bt_cb) * */ -void rsi_ble_update_le_dev_buf(rsi_ble_event_le_dev_buf_ind_t *rsi_ble_event_le_dev_buf_ind) +void rsi_ble_update_le_dev_buf(const rsi_ble_event_le_dev_buf_ind_t *rsi_ble_event_le_dev_buf_ind) { SL_PRINTF(SL_RSI_BT_UPDATE_LE_DEV_BUF_TRIGGER, BLUETOOTH, LOG_INFO); - uint8_t inx = 0; rsi_bt_cb_t *le_cb = rsi_driver_cb->ble_cb; - for (inx = 0; inx < (RSI_BLE_MAX_NBR_PERIPHERALS + RSI_BLE_MAX_NBR_CENTRALS); inx++) { + for (uint8_t inx = 0; inx < (RSI_BLE_MAX_NBR_PERIPHERALS + RSI_BLE_MAX_NBR_CENTRALS); inx++) { if (!memcmp(rsi_ble_event_le_dev_buf_ind->remote_dev_bd_addr, le_cb->remote_ble_info[inx].remote_dev_bd_addr, RSI_DEV_ADDR_LEN)) { @@ -322,14 +311,13 @@ void rsi_ble_update_le_dev_buf(rsi_ble_event_le_dev_buf_ind_t *rsi_ble_event_le_ * */ -void rsi_add_remote_ble_dev_info(rsi_ble_event_enhance_conn_status_t *remote_dev_info) +void rsi_add_remote_ble_dev_info(const rsi_ble_event_enhance_conn_status_t *remote_dev_info) { SL_PRINTF(SL_RSI_ADD_REMOTE_BLE_DEV_INFO_TRIGGER, BLUETOOTH, LOG_INFO); - uint8_t inx = 0; rsi_bt_cb_t *le_cb = rsi_driver_cb->ble_cb; - for (inx = 0; inx < (RSI_BLE_MAX_NBR_PERIPHERALS + RSI_BLE_MAX_NBR_CENTRALS); inx++) { + for (uint8_t inx = 0; inx < (RSI_BLE_MAX_NBR_PERIPHERALS + RSI_BLE_MAX_NBR_CENTRALS); inx++) { if (!le_cb->remote_ble_info[inx].used) { memcpy(le_cb->remote_ble_info[inx].remote_dev_bd_addr, remote_dev_info->dev_addr, RSI_DEV_ADDR_LEN); le_cb->remote_ble_info[inx].used = 1; @@ -351,14 +339,13 @@ void rsi_add_remote_ble_dev_info(rsi_ble_event_enhance_conn_status_t *remote_dev * */ -void rsi_remove_remote_ble_dev_info(rsi_ble_event_disconnect_t *remote_dev_info) +void rsi_remove_remote_ble_dev_info(const rsi_ble_event_disconnect_t *remote_dev_info) { SL_PRINTF(SL_RSI_REMOVE_REMOTE_BLE_DEV_INFO_TRIGGER, BLUETOOTH, LOG_INFO); - uint8_t inx = 0; rsi_bt_cb_t *le_cb = rsi_driver_cb->ble_cb; - for (inx = 0; inx < (RSI_BLE_MAX_NBR_PERIPHERALS + RSI_BLE_MAX_NBR_CENTRALS); inx++) { + for (uint8_t inx = 0; inx < (RSI_BLE_MAX_NBR_PERIPHERALS + RSI_BLE_MAX_NBR_CENTRALS); inx++) { if (!memcmp(remote_dev_info->dev_addr, le_cb->remote_ble_info[inx].remote_dev_bd_addr, RSI_DEV_ADDR_LEN)) { memset(le_cb->remote_ble_info[inx].remote_dev_bd_addr, 0, RSI_DEV_ADDR_LEN); le_cb->remote_ble_info[inx].used = 0; @@ -425,11 +412,12 @@ int32_t rsi_driver_process_bt_resp( if (bt_cb->expected_response_type == RSI_BT_EVENT_CARD_READY) { bt_cb->state = RSI_BT_STATE_OPERMODE_DONE; } - if (status == RSI_SUCCESS) { //To not allow BT SetAddress after these states are triggered - if (bt_cb->expected_response_type == RSI_BLE_REQ_ADV || bt_cb->expected_response_type == RSI_BLE_REQ_SCAN - || bt_cb->expected_response_type == RSI_BLE_REQ_CONN) { - rsi_driver_cb->bt_common_cb->state = RSI_BT_STATE_NONE; - } + + //To not allow BT SetAddress after these states are triggered + if ((status == RSI_SUCCESS) + && (bt_cb->expected_response_type == RSI_BLE_REQ_ADV || bt_cb->expected_response_type == RSI_BLE_REQ_SCAN + || bt_cb->expected_response_type == RSI_BLE_REQ_CONN)) { + rsi_driver_cb->bt_common_cb->state = RSI_BT_STATE_NONE; } expected_resp = bt_cb->expected_response_type; // Clear expected response type @@ -437,7 +425,6 @@ int32_t rsi_driver_process_bt_resp( // Copy the expected response to response structure/buffer, if any, passed in API if (bt_cb->expected_response_buffer != NULL) { - // If (payload_length <= RSI_BLE_GET_MAX_PAYLOAD_LENGTH(expected_response_type)) memcpy(bt_cb->expected_response_buffer, payload, payload_length); // Save expected_response pointer to a local variable, since it is being cleared below @@ -451,23 +438,21 @@ int32_t rsi_driver_process_bt_resp( if (bt_cb->sync_rsp) { /* handling this for the new buf configuration */ - if (expected_resp == RSI_BLE_RSP_SET_WWO_RESP_NOTIFY_BUF_INFO) { - if (status == RSI_SUCCESS) { - rsi_ble_set_wo_resp_notify_buf_info_t *buf_info = (rsi_ble_set_wo_resp_notify_buf_info_t *)payload; - - bt_cb->remote_ble_info[bt_cb->remote_ble_index].mode = buf_info->buf_mode; - - if (buf_info->buf_mode == 0) /* small buf cnt */ - { - bt_cb->remote_ble_info[bt_cb->remote_ble_index].max_buf_cnt = (buf_info->buf_count * 10); - bt_cb->remote_ble_info[bt_cb->remote_ble_index].avail_buf_cnt = (buf_info->buf_count * 10); - } else /* big buf cnt */ - { - bt_cb->remote_ble_info[bt_cb->remote_ble_index].max_buf_cnt = buf_info->buf_count; - bt_cb->remote_ble_info[bt_cb->remote_ble_index].avail_buf_cnt = buf_info->buf_count; - } - bt_cb->remote_ble_index = 0; /* assigning value to 0 after successful response */ + if ((expected_resp == RSI_BLE_RSP_SET_WWO_RESP_NOTIFY_BUF_INFO) && (status == RSI_SUCCESS)) { + const rsi_ble_set_wo_resp_notify_buf_info_t *buf_info = (rsi_ble_set_wo_resp_notify_buf_info_t *)payload; + + bt_cb->remote_ble_info[bt_cb->remote_ble_index].mode = buf_info->buf_mode; + + if (buf_info->buf_mode == 0) /* small buf cnt */ + { + bt_cb->remote_ble_info[bt_cb->remote_ble_index].max_buf_cnt = (buf_info->buf_count * 10); + bt_cb->remote_ble_info[bt_cb->remote_ble_index].avail_buf_cnt = (buf_info->buf_count * 10); + } else /* big buf cnt */ + { + bt_cb->remote_ble_info[bt_cb->remote_ble_index].max_buf_cnt = buf_info->buf_count; + bt_cb->remote_ble_info[bt_cb->remote_ble_index].avail_buf_cnt = buf_info->buf_count; } + bt_cb->remote_ble_index = 0; /* assigning value to 0 after successful response */ } // Signal the bt semaphore osSemaphoreRelease(bt_cb->bt_sem); @@ -501,21 +486,19 @@ uint16_t rsi_driver_process_bt_resp_handler(void *rx_pkt) { SL_PRINTF(SL_RSI_DRIVER_PROCESS_BT_RESP_HANDLER_TRIGGER, BLUETOOTH, LOG_INFO); - sl_si91x_packet_t *pkt = (sl_si91x_packet_t *)rx_pkt; - uint8_t *host_desc = NULL; - uint8_t protocol_type = 0; - uint16_t rsp_type = 0; - // uint16_t rsp_len = 0; - int16_t status = RSI_SUCCESS; - rsi_bt_cb_t *bt_cb = NULL; - rsi_ble_event_disconnect_t *temp_data = NULL; + sl_si91x_packet_t *pkt = (sl_si91x_packet_t *)rx_pkt; + uint8_t *host_desc = NULL; + uint8_t protocol_type = 0; + uint16_t rsp_type = 0; + int16_t status = RSI_SUCCESS; + rsi_bt_cb_t *bt_cb = NULL; + const rsi_ble_event_disconnect_t *temp_data = NULL; // Get Host Descriptor host_desc = pkt->desc; // Get Command response Type rsp_type = rsi_bytes2R_to_uint16(host_desc + RSI_BT_RSP_TYPE_OFFSET); - //rsp_len = rsi_bytes2R_to_uint16(host_desc + RSI_BT_RSP_LEN_OFFSET) & RSI_BT_RSP_LEN_MASK; if (rsp_type == RSI_BLE_EVENT_DISCONNECT) { @@ -526,7 +509,7 @@ uint16_t rsi_driver_process_bt_resp_handler(void *rx_pkt) } // Get the protocol Type - protocol_type = rsi_bt_get_proto_type(rsp_type, &bt_cb); + protocol_type = (uint8_t)rsi_bt_get_proto_type(rsp_type, &bt_cb); SL_PRINTF(SL_RSI_BT_DRIVER_PROCESS_BT_RESP_HANDLER_TRIGGER, BLUETOOTH, LOG_INFO, "PROTOCOL_TYPE: %1x", protocol_type); if (protocol_type == 0xFF) { @@ -535,10 +518,10 @@ uint16_t rsi_driver_process_bt_resp_handler(void *rx_pkt) // Call the corresponding protocol process rsp handler if (protocol_type == RSI_PROTO_BT_COMMON) { // Call BT common process rsp handler - status = rsi_driver_process_bt_resp(bt_cb, pkt, NULL, protocol_type); + status = (int16_t)rsi_driver_process_bt_resp(bt_cb, pkt, NULL, protocol_type); } else { // Call BLE process response handler - status = rsi_driver_process_bt_resp(bt_cb, pkt, rsi_ble_callbacks_handler, protocol_type); + status = (int16_t)rsi_driver_process_bt_resp(bt_cb, pkt, rsi_ble_callbacks_handler, protocol_type); } return status; } @@ -1005,15 +988,15 @@ void rsi_ble_callbacks_handler(rsi_bt_cb_t *ble_cb, uint16_t rsp_type, uint8_t * // This statement is added only to resolve compilation warning, value is unchanged UNUSED_PARAMETER(payload_length); // Get ble cb struct pointer - rsi_ble_cb_t *ble_specific_cb = ble_cb->bt_global_cb->ble_specific_cb; - uint16_t status = 0; - uint16_t sync_status = 0; - uint8_t le_cmd_inuse_check = 0; + const rsi_ble_cb_t *ble_specific_cb = ble_cb->bt_global_cb->ble_specific_cb; + uint16_t status = 0; + uint16_t sync_status = 0; + uint8_t le_cmd_inuse_check = 0; // updating the response status; - status = ble_cb->async_status; + status = (uint16_t)ble_cb->async_status; - sync_status = rsi_bt_get_status(ble_cb); + sync_status = (uint16_t)rsi_bt_get_status(ble_cb); SL_PRINTF(SL_RSI_BLE_CALLBACKS_HANDLER_STATUS, BLE, LOG_INFO, "STATUS: %2x", status); @@ -1029,7 +1012,6 @@ void rsi_ble_callbacks_handler(rsi_bt_cb_t *ble_cb, uint16_t rsp_type, uint8_t * ((rsi_ble_event_conn_status_t *)payload)->status = status; ble_specific_cb->ble_on_conn_status_event((rsi_ble_event_conn_status_t *)payload); } - // rsi_bt_set_status(ble_cb, RSI_BLE_STATE_CONNECTION); rsi_add_remote_ble_dev_info((rsi_ble_event_enhance_conn_status_t *)payload); } break; @@ -1038,7 +1020,6 @@ void rsi_ble_callbacks_handler(rsi_bt_cb_t *ble_cb, uint16_t rsp_type, uint8_t * ((rsi_ble_event_enhance_conn_status_t *)payload)->status = status; ble_specific_cb->ble_on_enhance_conn_status_event((rsi_ble_event_enhance_conn_status_t *)payload); } - // rsi_bt_set_status(ble_cb, RSI_BLE_STATE_CONNECTION); rsi_add_remote_ble_dev_info((rsi_ble_event_enhance_conn_status_t *)payload); } break; @@ -1046,7 +1027,6 @@ void rsi_ble_callbacks_handler(rsi_bt_cb_t *ble_cb, uint16_t rsp_type, uint8_t * if (ble_specific_cb->ble_on_disconnect_event != NULL) { ble_specific_cb->ble_on_disconnect_event((rsi_ble_event_disconnect_t *)payload, status); } - // rsi_bt_set_status(ble_cb, RSI_BLE_STATE_DSICONNECT); rsi_remove_remote_ble_dev_info((rsi_ble_event_disconnect_t *)payload); } break; case RSI_BLE_EVENT_GATT_ERROR_RESPONSE: { @@ -1383,21 +1363,19 @@ void rsi_ble_callbacks_handler(rsi_bt_cb_t *ble_cb, uint16_t rsp_type, uint8_t * ble_specific_cb->ble_on_rcp_resp_rcvd_event(status, (rsi_ble_event_rcp_rcvd_info_t *)payload); } } - default: { - } + default: + break; } if (le_cmd_inuse_check) { - uint8_t inx = 0; - uint8_t *remote_dev_bd_addr = (uint8_t *)payload; - for (inx = 0; inx < (RSI_BLE_MAX_NBR_PERIPHERALS + RSI_BLE_MAX_NBR_CENTRALS); inx++) { + const uint8_t *remote_dev_bd_addr = payload; + for (uint8_t inx = 0; inx < (RSI_BLE_MAX_NBR_PERIPHERALS + RSI_BLE_MAX_NBR_CENTRALS); inx++) { if (!memcmp(ble_cb->remote_ble_info[inx].remote_dev_bd_addr, remote_dev_bd_addr, RSI_DEV_ADDR_LEN)) { - if (ble_cb->remote_ble_info[inx].cmd_in_use) { - if ((rsp_type == RSI_BLE_EVENT_GATT_ERROR_RESPONSE) - || (rsp_type == ble_cb->remote_ble_info[inx].expected_resp)) { - ble_cb->remote_ble_info[inx].cmd_in_use = 0; - ble_cb->remote_ble_info[inx].expected_resp = 0; - } + if ((ble_cb->remote_ble_info[inx].cmd_in_use) + && ((rsp_type == RSI_BLE_EVENT_GATT_ERROR_RESPONSE) + || (rsp_type == ble_cb->remote_ble_info[inx].expected_resp))) { + ble_cb->remote_ble_info[inx].cmd_in_use = 0; + ble_cb->remote_ble_info[inx].expected_resp = 0; } break; } @@ -1501,14 +1479,14 @@ uint16_t rsi_bt_prepare_common_pkt(uint16_t cmd_type, void *cmd_struct, sl_si91x payload_size = sizeof(rsi_ble_per_receive_t); memcpy(pkt->data, cmd_struct, payload_size); break; - default: { - } + default: + return RSI_ERROR_INVALID_PARAM; } } break; case RSI_BT_VENDOR_SPECIFIC: { pkt->data[0] = ((uint8_t *)cmd_struct)[0]; pkt->data[1] = ((uint8_t *)cmd_struct)[1]; - switch ((pkt->data[0] | (pkt->data[1] << 8))) { + switch (pkt->data[0] | (pkt->data[1] << 8)) { case BLE_VENDOR_RF_TYPE_CMD_OPCODE: payload_size = sizeof(rsi_ble_vendor_rf_type_t); memcpy(pkt->data, cmd_struct, payload_size); @@ -2030,9 +2008,8 @@ uint16_t rsi_bt_prepare_le_pkt(uint16_t cmd_type, void *cmd_struct, sl_si91x_pac } if (le_buf_check || le_cmd_inuse_check || le_buf_in_use_check) { - uint8_t inx = 0; uint8_t *remote_dev_bd_addr = (uint8_t *)cmd_struct; - for (inx = 0; inx < (RSI_BLE_MAX_NBR_PERIPHERALS + RSI_BLE_MAX_NBR_CENTRALS); inx++) { + for (uint8_t inx = 0; inx < (RSI_BLE_MAX_NBR_PERIPHERALS + RSI_BLE_MAX_NBR_CENTRALS); inx++) { if (!memcmp(le_cb->remote_ble_info[inx].remote_dev_bd_addr, remote_dev_bd_addr, RSI_DEV_ADDR_LEN)) { /* ERROR PRONE : Do not changes if else checks order */ diff --git a/components/device/silabs/si91x/wireless/ble/src/rsi_bt_common_apis.c b/components/device/silabs/si91x/wireless/ble/src/rsi_bt_common_apis.c index 544add49e..36a7a212a 100644 --- a/components/device/silabs/si91x/wireless/ble/src/rsi_bt_common_apis.c +++ b/components/device/silabs/si91x/wireless/ble/src/rsi_bt_common_apis.c @@ -26,14 +26,14 @@ /****************************************************** * Function Declarations ******************************************************/ -int32_t rsi_bt_set_bd_addr(uint8_t *dev_addr); -int32_t rsi_bt_set_local_name(uint8_t *local_name); +int32_t rsi_bt_set_bd_addr(const uint8_t *dev_addr); +int32_t rsi_bt_set_local_name(const uint8_t *local_name); int32_t rsi_bt_cmd_update_gain_table_offset_or_max_pwr(uint8_t node_id, uint8_t payload_len, - uint8_t *payload, + const uint8_t *payload, uint8_t req_type); int32_t rsi_bt_get_local_name(rsi_bt_resp_get_local_name_t *bt_resp_get_local_name); -int32_t rsi_bt_get_rssi(uint8_t *dev_addr, int8_t *resp); +int32_t rsi_bt_get_rssi(const uint8_t *dev_addr, int8_t *resp); int32_t rsi_bt_get_local_device_address(uint8_t *resp); int32_t rsi_bt_get_bt_stack_version(rsi_bt_resp_get_bt_stack_version_t *bt_resp_get_bt_stack_version); int32_t rsi_bt_init(void); @@ -57,7 +57,7 @@ int32_t rsi_bt_per_stats(uint8_t cmd_type, struct rsi_bt_per_stats_s *per_stats) * -3 - Command is given in wrong state(i.e not immediate after opermode) * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . */ -int32_t rsi_bt_set_bd_addr(uint8_t *dev_addr) +int32_t rsi_bt_set_bd_addr(const uint8_t *dev_addr) { rsi_bt_set_local_bd_addr_t bd_addr; #ifdef BD_ADDR_IN_ASCII @@ -86,11 +86,11 @@ int32_t rsi_bt_set_bd_addr(uint8_t *dev_addr) * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . * */ -int32_t rsi_bt_set_local_name(uint8_t *local_name) +int32_t rsi_bt_set_local_name(const uint8_t *local_name) { uint8_t name_len; rsi_bt_req_set_local_name_t bt_req_set_local_name = { 0 }; - name_len = RSI_MIN(strlen((const char *)local_name), (RSI_DEV_NAME_LEN - 1)); + name_len = (uint8_t)RSI_MIN(strlen((const char *)local_name), (RSI_DEV_NAME_LEN - 1)); memcpy(bt_req_set_local_name.name, local_name, name_len); bt_req_set_local_name.name[name_len] = 0; @@ -123,7 +123,7 @@ int32_t rsi_bt_set_local_name(uint8_t *local_name) */ int32_t rsi_bt_cmd_update_gain_table_offset_or_max_pwr(uint8_t node_id, uint8_t payload_len, - uint8_t *payload, + const uint8_t *payload, uint8_t req_type) { rsi_bt_cmd_update_gain_table_offset_or_maxpower_t bt_gain_table_offset = { 0 }; @@ -163,7 +163,7 @@ int32_t rsi_bt_get_local_name(rsi_bt_resp_get_local_name_t *bt_resp_get_local_na * Non-Zero Value - Failure * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . */ -int32_t rsi_bt_get_rssi(uint8_t *dev_addr, int8_t *resp) +int32_t rsi_bt_get_rssi(const uint8_t *dev_addr, int8_t *resp) { rsi_bt_get_rssi_t bt_rssi = { { 0 } }; #ifdef BD_ADDR_IN_ASCII @@ -382,7 +382,7 @@ int32_t rsi_bt_power_save_profile(uint8_t psp_mode, uint8_t psp_type) } break; case RSI_SLEEP_MODE_2: { if (psp_type == RSI_MAX_PSP) { - profile.profile = ASSOCIATED_POWER_SAVE; + profile.profile = ASSOCIATED_POWER_SAVE_LOW_LATENCY; } else { return RSI_FEATURE_NOT_SUPPORTED; } diff --git a/components/device/silabs/si91x/wireless/ble/src/rsi_common_apis.c b/components/device/silabs/si91x/wireless/ble/src/rsi_common_apis.c index 0fabf6ef6..62890c970 100644 --- a/components/device/silabs/si91x/wireless/ble/src/rsi_common_apis.c +++ b/components/device/silabs/si91x/wireless/ble/src/rsi_common_apis.c @@ -68,14 +68,12 @@ int32_t rsi_ble_driver_init(uint8_t *buffer, uint32_t length) { uint32_t actual_length = 0; - // If (((uint32_t)buffer & 3) != 0) if (((uintptr_t)buffer & 3) != 0) // To avoid compiler warning, replace uint32_t with uintptr_t { // Making buffer 4 byte aligned // Length -= (4 - ((uint32_t)buffer & 3)); // To avoid compiler warning, replace uint32_t with uintptr_t length -= (4 - ((uintptr_t)buffer & 3)); - // Buffer = (uint8_t *)(((uint32_t)buffer + 3) & ~3);// To avoid compiler warning, replace uint32_t with uintptr_t buffer = (uint8_t *)(((uintptr_t)buffer + 3) & ~3); } @@ -163,7 +161,7 @@ int32_t rsi_ble_driver_deinit(void) SL_PRINTF(SL_DRIVER_DEINIT_ENTRY, COMMON, LOG_INFO); uint32_t actual_length = 0; - if ((rsi_driver_cb->device_state < RSI_DRIVER_INIT_DONE)) { + if (rsi_driver_cb->device_state < RSI_DRIVER_INIT_DONE) { // Command given in wrong state return RSI_ERROR_COMMAND_GIVEN_IN_WRONG_STATE; } diff --git a/components/device/silabs/si91x/wireless/ble/src/rsi_utils.c b/components/device/silabs/si91x/wireless/ble/src/rsi_utils.c index 865722f1a..de6f5a498 100644 --- a/components/device/silabs/si91x/wireless/ble/src/rsi_utils.c +++ b/components/device/silabs/si91x/wireless/ble/src/rsi_utils.c @@ -78,7 +78,7 @@ void rsi_uint32_to_4bytes(uint8_t *dBuf, uint32_t val) * @param[in] dBuf - Pointer to a buffer to get the data from * @return Converted 16 bit data */ -uint16_t rsi_bytes2R_to_uint16(uint8_t *dBuf) +uint16_t rsi_bytes2R_to_uint16(const uint8_t *dBuf) { uint16_t val; if (rsi_driver_cb->endian == IS_LITTLE_ENDIAN) { @@ -101,7 +101,7 @@ uint16_t rsi_bytes2R_to_uint16(uint8_t *dBuf) * @return Converted 32 bit data */ -uint32_t rsi_bytes4R_to_uint32(uint8_t *dBuf) +uint32_t rsi_bytes4R_to_uint32(const uint8_t *dBuf) { // the 32-bit value to return uint32_t val; @@ -157,8 +157,7 @@ int8_t rsi_ascii_hex2num(int8_t ascii_hex_in) int8_t rsi_char_hex2dec(int8_t *cBuf) { int8_t k = 0; - uint8_t i; - for (i = 0; i < strlen((char *)cBuf); i++) { + for (uint8_t i = 0; i < strlen((char *)cBuf); i++) { k = ((k * 16) + rsi_ascii_hex2num(cBuf[i])); } return k; @@ -175,14 +174,13 @@ int8_t rsi_char_hex2dec(int8_t *cBuf) uint8_t *rsi_ascii_dev_address_to_6bytes_rev(uint8_t *hex_addr, int8_t *ascii_mac_address) { - uint8_t i; // loop counter uint8_t cBufPos; // which char in the ASCII representation uint8_t byteNum; // which byte in the 32Bithex_address int8_t cBuf[6]; // temporary buffer byteNum = 5; cBufPos = 0; - for (i = 0; i < strlen((char *)ascii_mac_address); i++) { + for (uint8_t i = 0; i < strlen((char *)ascii_mac_address); i++) { // this will take care of the first 5 octets if (ascii_mac_address[i] == ':') { // we are at the end of the address octet cBuf[cBufPos] = 0; // terminate the string @@ -233,7 +231,6 @@ int8_t hex_to_ascii(uint8_t hex_num) case 0xf: ascii = (hex_num & 0x0F) - 10 + 'A'; return ascii; - // break; default: break; } @@ -250,14 +247,12 @@ int8_t hex_to_ascii(uint8_t hex_num) * @return Converted ASCII mac address */ -uint8_t *rsi_6byte_dev_address_to_ascii(uint8_t *ascii_mac_address, uint8_t *hex_addr) +uint8_t *rsi_6byte_dev_address_to_ascii(uint8_t *ascii_mac_address, const uint8_t *hex_addr) { - int8_t i; // loop counter uint8_t cBufPos; // which char in the ASCII representation - //byteNum = 5; cBufPos = 0; - for (i = 5; i >= 0; i--) { + for (int8_t i = 5; i >= 0; i--) { ascii_mac_address[cBufPos++] = hex_to_ascii(hex_addr[i] >> 4); ascii_mac_address[cBufPos++] = hex_to_ascii(hex_addr[i]); if (i != 0) { @@ -291,12 +286,11 @@ uint8_t convert_lower_case_to_upper_case(uint8_t lwrcase) * @return void */ -void string2array(uint8_t *dst, uint8_t *src, uint32_t length) +void string2array(uint8_t *dst, const uint8_t *src, uint32_t length) { - uint32_t i = 0, j = 0; - for (i = 0, j = 0; i < (length * 2) && j < length; i += 2, j++) + for (uint32_t i = 0, j = 0; i < (length * 2) && j < length; i += 2, j++) if (src[i] && src[i + 1]) { - dst[j] = ((uint16_t)convert_lower_case_to_upper_case(src[i])) * 16; + dst[j] = (uint8_t)((convert_lower_case_to_upper_case(src[i])) * 16); dst[j] += convert_lower_case_to_upper_case(src[i + 1]); } else { dst[j] = 0; @@ -313,7 +307,8 @@ void string2array(uint8_t *dst, uint8_t *src, uint32_t length) uint8_t *rsi_itoa(uint32_t val, uint8_t *str) { - int16_t ii = 0, jj = 0; + int16_t ii = 0; + int16_t jj = 0; uint8_t tmp[10]; if (val == 0) { // if value is zero then handling @@ -392,8 +387,7 @@ int8_t asciihex_2_num(int8_t ascii_hex_in) int8_t rsi_charhex_2_dec(int8_t *cBuf) { int8_t k = 0; - uint8_t i; - for (i = 0; i < strlen((char *)cBuf); i++) { + for (uint8_t i = 0; i < strlen((char *)cBuf); i++) { k = ((k * 16) + asciihex_2_num(cBuf[i])); } return k; @@ -409,14 +403,13 @@ int8_t rsi_charhex_2_dec(int8_t *cBuf) */ void rsi_ascii_mac_address_to_6bytes(uint8_t *hexAddr, int8_t *asciiMacAddress) { - uint8_t i; // loop counter uint8_t cBufPos; // which char in the ASCII representation uint8_t byteNum; // which byte in the 32BitHexAddress int8_t cBuf[6]; // temporary buffer byteNum = 0; cBufPos = 0; - for (i = 0; i < strlen((char *)asciiMacAddress); i++) { + for (uint8_t i = 0; i < strlen((char *)asciiMacAddress); i++) { // this will take care of the first 5 octets if (asciiMacAddress[i] == ':') { // we are at the end of the address octet cBuf[cBufPos] = 0; // terminate the string @@ -441,8 +434,6 @@ void rsi_ascii_mac_address_to_6bytes(uint8_t *hexAddr, int8_t *asciiMacAddress) */ void rsi_ascii_dot_address_to_4bytes(uint8_t *hexAddr, int8_t *asciiDotAddress) { - uint8_t i; - // loop counter uint8_t cBufPos; // which char in the ASCII representation uint8_t byteNum; @@ -452,7 +443,7 @@ void rsi_ascii_dot_address_to_4bytes(uint8_t *hexAddr, int8_t *asciiDotAddress) byteNum = 0; cBufPos = 0; - for (i = 0; i < strlen((char *)asciiDotAddress); i++) { + for (uint8_t i = 0; i < strlen((char *)asciiDotAddress); i++) { // this will take care of the first 3 octets if (asciiDotAddress[i] == '.') { // we are at the end of the address octet @@ -480,9 +471,12 @@ void rsi_ascii_dot_address_to_4bytes(uint8_t *hexAddr, int8_t *asciiDotAddress) * @param[in] ip - IP address to convert. * @return IP address in reverse Hex format */ -uint64_t ip_to_reverse_hex(char *ip) +uint64_t ip_to_reverse_hex(const char *ip) { - uint32_t ip1, ip2, ip3, ip4; + uint32_t ip1; + uint32_t ip2; + uint32_t ip3; + uint32_t ip4; uint64_t ip_hex; uint32_t status; @@ -508,7 +502,7 @@ uint64_t ip_to_reverse_hex(char *ip) // network to host long uint32_t rsi_ntohl(uint32_t a) { - return ((((a)&0xff000000) >> 24) | (((a)&0x00ff0000) >> 8) | (((a)&0x0000ff00) << 8) | (((a)&0x000000ff) << 24)); + return (((a & 0xff000000) >> 24) | ((a & 0x00ff0000) >> 8) | ((a & 0x0000ff00) << 8) | ((a & 0x000000ff) << 24)); } /** @} */ diff --git a/components/device/silabs/si91x/wireless/crypto/attestation/src/sl_si91x_attestation.c b/components/device/silabs/si91x/wireless/crypto/attestation/src/sl_si91x_attestation.c index af401c0c1..887202d05 100644 --- a/components/device/silabs/si91x/wireless/crypto/attestation/src/sl_si91x_attestation.c +++ b/components/device/silabs/si91x/wireless/crypto/attestation/src/sl_si91x_attestation.c @@ -54,8 +54,8 @@ sl_status_t sl_si91x_attestation_get_token(uint8_t *token, uint16_t length, uint return SL_STATUS_INVALID_PARAMETER; } sl_status_t status; - sl_wifi_buffer_t *buffer; - sl_si91x_packet_t *packet; + sl_wifi_buffer_t *buffer = NULL; + sl_si91x_packet_t *packet = NULL; sl_si91x_rsi_token_req_t *attest = (sl_si91x_rsi_token_req_t *)malloc(sizeof(sl_si91x_rsi_token_req_t)); @@ -73,6 +73,7 @@ sl_status_t sl_si91x_attestation_get_token(uint8_t *token, uint16_t length, uint attest->total_msg_length = length; #ifdef SL_SI91X_SIDE_BAND_CRYPTO + UNUSED_VARIABLE(packet); // to avoid unused variable warning attest->msg = nonce; attest->token_buf = token; #else diff --git a/components/device/silabs/si91x/wireless/crypto/ccm/src/sl_si91x_ccm.c b/components/device/silabs/si91x/wireless/crypto/ccm/src/sl_si91x_ccm.c index 5c769cb79..96c9598f3 100644 --- a/components/device/silabs/si91x/wireless/crypto/ccm/src/sl_si91x_ccm.c +++ b/components/device/silabs/si91x/wireless/crypto/ccm/src/sl_si91x_ccm.c @@ -39,6 +39,39 @@ #endif #include +static sl_status_t sli_si91x_ccm_config_check(sl_si91x_ccm_config_t *config) +{ + // Only 32 bytes M4 OTA built-in key support is present + if (config->key_config.b0.key_type == SL_SI91X_BUILT_IN_KEY) { + if (((int)config->key_config.b0.key_size != (int)SL_SI91X_KEY_SIZE_1) + || (config->key_config.b0.key_slot != SL_SI91X_KEY_SLOT_1)) + return SL_STATUS_INVALID_PARAMETER; + } + + if ((config->nonce_length < SL_SI91X_CCM_IV_MIN_SIZE) || (config->nonce_length > SL_SI91X_CCM_IV_MAX_SIZE)) { + return SL_STATUS_INVALID_PARAMETER; + } + + return SL_STATUS_OK; +} + +#ifdef SLI_SI917B0 +static void sli_si91x_ccm_get_key_info(sl_si91x_ccm_request_t *request, const sl_si91x_ccm_config_t *config) +{ + request->key_info.key_type = config->key_config.b0.key_type; + request->key_info.key_detail.key_size = config->key_config.b0.key_size; + request->key_info.key_detail.key_spec.key_slot = config->key_config.b0.key_slot; + request->key_info.key_detail.key_spec.wrap_iv_mode = config->key_config.b0.wrap_iv_mode; + request->key_info.reserved = config->key_config.b0.reserved; + if (config->key_config.b0.wrap_iv_mode) { + memcpy(request->key_info.key_detail.key_spec.wrap_iv, config->key_config.b0.wrap_iv, SL_SI91X_IV_SIZE); + } + memcpy(request->key_info.key_detail.key_spec.key_buffer, + config->key_config.b0.key_buffer, + config->key_config.b0.key_size); +} +#endif + #ifndef SL_SI91X_SIDE_BAND_CRYPTO static sl_status_t sli_si91x_ccm_pending(sl_si91x_ccm_config_t *config, uint16_t chunk_length, @@ -52,15 +85,9 @@ static sl_status_t sli_si91x_ccm_pending(sl_si91x_ccm_config_t *config, SL_VERIFY_POINTER_OR_RETURN(request, SL_STATUS_ALLOCATION_FAILED); - // Only 32 bytes M4 OTA built-in key support is present - if (config->key_config.b0.key_type == SL_SI91X_BUILT_IN_KEY) { - if (((int)config->key_config.b0.key_size != (int)SL_SI91X_KEY_SIZE_1) - || (config->key_config.b0.key_slot != SL_SI91X_KEY_SLOT_1)) - return SL_STATUS_INVALID_PARAMETER; - } - - if ((config->nonce_length < SL_SI91X_CCM_IV_MIN_SIZE) || (config->nonce_length > SL_SI91X_CCM_IV_MAX_SIZE)) { - return SL_STATUS_INVALID_PARAMETER; + status = sli_si91x_ccm_config_check(config); + if (status != SL_STATUS_OK) { + return status; } memset(request, 0, sizeof(sl_si91x_ccm_request_t)); @@ -84,17 +111,7 @@ static sl_status_t sli_si91x_ccm_pending(sl_si91x_ccm_config_t *config, memcpy(request->tag, config->tag, config->tag_length); #ifdef SLI_SI917B0 - request->key_info.key_type = config->key_config.b0.key_type; - request->key_info.key_detail.key_size = config->key_config.b0.key_size; - request->key_info.key_detail.key_spec.key_slot = config->key_config.b0.key_slot; - request->key_info.key_detail.key_spec.wrap_iv_mode = config->key_config.b0.wrap_iv_mode; - request->key_info.reserved = config->key_config.b0.reserved; - if (config->key_config.b0.wrap_iv_mode) { - memcpy(request->key_info.key_detail.key_spec.wrap_iv, config->key_config.b0.wrap_iv, SL_SI91X_IV_SIZE); - } - memcpy(request->key_info.key_detail.key_spec.key_buffer, - config->key_config.b0.key_buffer, - config->key_config.b0.key_size); + sli_si91x_ccm_get_key_info(request, config); #else memcpy(request->key, config->key_config.a0.key, request->key_length); @@ -143,15 +160,9 @@ static sl_status_t sli_si91x_ccm_side_band(sl_si91x_ccm_config_t *config, uint8_ SL_VERIFY_POINTER_OR_RETURN(request, SL_STATUS_ALLOCATION_FAILED); - // Only 32 bytes M4 OTA built-in key support is present - if (config->key_config.b0.key_type == SL_SI91X_BUILT_IN_KEY) { - if (((int)config->key_config.b0.key_size != (int)SL_SI91X_KEY_SIZE_1) - || (config->key_config.b0.key_slot != SL_SI91X_KEY_SLOT_1)) - return SL_STATUS_INVALID_PARAMETER; - } - - if ((config->nonce_length < SL_SI91X_CCM_IV_MIN_SIZE) || (config->nonce_length > SL_SI91X_CCM_IV_MAX_SIZE)) { - return SL_STATUS_INVALID_PARAMETER; + status = sli_si91x_ccm_config_check(config); + if (status != SL_STATUS_OK) { + return status; } memset(request, 0, sizeof(sl_si91x_ccm_request_t)); @@ -172,18 +183,7 @@ static sl_status_t sli_si91x_ccm_side_band(sl_si91x_ccm_config_t *config, uint8_ request->nonce = (uint8_t *)config->nonce; request->tag = config->tag; - request->key_info.key_type = config->key_config.b0.key_type; - request->key_info.key_detail.key_size = config->key_config.b0.key_size; - request->key_info.key_detail.key_spec.key_slot = config->key_config.b0.key_slot; - request->key_info.key_detail.key_spec.wrap_iv_mode = config->key_config.b0.wrap_iv_mode; - request->key_info.reserved = config->key_config.b0.reserved; - if (config->key_config.b0.wrap_iv_mode) { - memcpy(request->key_info.key_detail.key_spec.wrap_iv, config->key_config.b0.wrap_iv, SL_SI91X_IV_SIZE); - } - memcpy(request->key_info.key_detail.key_spec.key_buffer, - config->key_config.b0.key_buffer, - config->key_config.b0.key_size); - + sli_si91x_ccm_get_key_info(request, config); request->output = output; status = sl_si91x_driver_send_side_band_crypto(RSI_COMMON_REQ_ENCRYPT_CRYPTO, diff --git a/components/device/silabs/si91x/wireless/crypto/ecdsa/src/sl_si91x_psa_ecdsa.c b/components/device/silabs/si91x/wireless/crypto/ecdsa/src/sl_si91x_psa_ecdsa.c index 86e49dcfa..a67f3e47d 100644 --- a/components/device/silabs/si91x/wireless/crypto/ecdsa/src/sl_si91x_psa_ecdsa.c +++ b/components/device/silabs/si91x/wireless/crypto/ecdsa/src/sl_si91x_psa_ecdsa.c @@ -31,14 +31,6 @@ #include "sl_si91x_driver.h" #include -// ----------------------------------------------------------------------------- -// Global Variables -// ----------------------------------------------------------------------------- -uint8_t r_size = 0; -uint8_t s_size = 0; -uint8_t r_bit = 0; -uint8_t s_bit = 0; - /** * \brief Validate that the curve and algorithm combination is supported by hardware * @@ -200,31 +192,49 @@ psa_status_t sli_si91x_crypto_sign_message(const psa_key_attributes_t *attribute status = SL_STATUS_INVALID_SIGNATURE; /* Convert DER format signature to compact format */ - r_size = sign_buf[3]; - s_size = sign_buf[5 + r_size]; + uint8_t r_size = sign_buf[3]; + uint8_t s_size = sign_buf[5 + r_size]; - uint8_t r_index = 4; - uint8_t s_index = 6 + r_size; + uint8_t r_index = 4; + uint8_t s_index = 6 + r_size; + uint8_t r_bit = 0; + uint8_t s_bit = 0; + uint8_t r_leading = 0; + uint8_t s_leading = 0; if (key_buffer_size == SL_SI91X_ECDSA_PRIV_KEY_SIZE_224) { if (r_size == SL_SI91X_ECDSA_SIGN_HALF_SIZE_P224R1 + 1) r_bit = 1; if (s_size == SL_SI91X_ECDSA_SIGN_HALF_SIZE_P224R1 + 1) s_bit = 1; - memcpy(signature, &sign_buf[r_index + r_bit], SL_SI91X_ECDSA_SIGN_HALF_SIZE_P224R1); - memcpy(&signature[SL_SI91X_ECDSA_SIGN_HALF_SIZE_P224R1], + if (r_size == SL_SI91X_ECDSA_SIGN_HALF_SIZE_P224R1 - 1) + r_leading = 1; + if (s_size == SL_SI91X_ECDSA_SIGN_HALF_SIZE_P224R1 - 1) + s_leading = 1; + + signature[0] = 0x00; + signature[SL_SI91X_ECDSA_SIGN_HALF_SIZE_P224R1] = 0x00; + memcpy(&signature[0 + r_leading], &sign_buf[r_index + r_bit], SL_SI91X_ECDSA_SIGN_HALF_SIZE_P224R1 - r_leading); + memcpy(&signature[SL_SI91X_ECDSA_SIGN_HALF_SIZE_P224R1 + s_leading], &sign_buf[s_index + s_bit], - SL_SI91X_ECDSA_SIGN_HALF_SIZE_P224R1); + SL_SI91X_ECDSA_SIGN_HALF_SIZE_P224R1 - s_leading); } else if (key_buffer_size == SL_SI91X_ECDSA_PRIV_KEY_SIZE_256) { if (r_size == SL_SI91X_ECDSA_SIGN_HALF_SIZE_P256R1 + 1) r_bit = 1; if (s_size == SL_SI91X_ECDSA_SIGN_HALF_SIZE_P256R1 + 1) s_bit = 1; - memcpy(signature, &sign_buf[r_index + r_bit], SL_SI91X_ECDSA_SIGN_HALF_SIZE_P256R1); - memcpy(&signature[SL_SI91X_ECDSA_SIGN_HALF_SIZE_P256R1], + if (r_size == SL_SI91X_ECDSA_SIGN_HALF_SIZE_P256R1 - 1) + r_leading = 1; + if (s_size == SL_SI91X_ECDSA_SIGN_HALF_SIZE_P256R1 - 1) + s_leading = 1; + + signature[0] = 0x00; + signature[SL_SI91X_ECDSA_SIGN_HALF_SIZE_P256R1] = 0x00; + memcpy(&signature[0 + r_leading], &sign_buf[r_index + r_bit], SL_SI91X_ECDSA_SIGN_HALF_SIZE_P256R1 - r_leading); + memcpy(&signature[SL_SI91X_ECDSA_SIGN_HALF_SIZE_P256R1 + s_leading], &sign_buf[s_index + s_bit], - SL_SI91X_ECDSA_SIGN_HALF_SIZE_P256R1); + SL_SI91X_ECDSA_SIGN_HALF_SIZE_P256R1 - s_leading); } /* gets the si91x error codes and returns its equivalent psa_status codes */ @@ -349,8 +359,55 @@ psa_status_t sli_si91x_crypto_verify_message(const psa_key_attributes_t *attribu config.key_config.a0.key_length = key_buffer_size; #endif + uint8_t r_size = 0; + uint8_t s_size = 0; + uint8_t r_bit = 0; + uint8_t s_bit = 0; + uint8_t r_leading = 0; + uint8_t s_leading = 0; + /* Convert compact format signature to DER format */ + if (key_buffer_size == SL_SI91X_ECDSA_PUB_KEY_SIZE_224) { + r_size = s_size = SL_SI91X_ECDSA_SIGN_HALF_SIZE_P224R1; + if (signature[0] >= 0x80) { + r_bit = 1; + r_size++; + } + if (signature[SL_SI91X_ECDSA_SIGN_HALF_SIZE_P224R1] >= 0x80) { + s_bit = 1; + s_size++; + } + if (signature[0] == 0x00) { + r_leading++; + r_size--; + } + if (signature[SL_SI91X_ECDSA_SIGN_HALF_SIZE_P224R1] == 0x00) { + s_leading++; + s_size--; + } + } + + else if (key_buffer_size == SL_SI91X_ECDSA_PUB_KEY_SIZE_256) { + r_size = s_size = SL_SI91X_ECDSA_SIGN_HALF_SIZE_P256R1; + if (signature[0] >= 0x80) { + r_bit = 1; + r_size++; + } + if (signature[SL_SI91X_ECDSA_SIGN_HALF_SIZE_P256R1] >= 0x80) { + s_bit = 1; + s_size++; + } + if (signature[0] == 0x00) { + r_leading++; + r_size--; + } + if (signature[SL_SI91X_ECDSA_SIGN_HALF_SIZE_P256R1] == 0x00) { + s_leading++; + s_size--; + } + } + uint8_t sign_size = r_size + s_size + 4; uint8_t total_size = sign_size + 2; uint8_t s_index = r_size + 6; @@ -369,17 +426,13 @@ psa_status_t sli_si91x_crypto_verify_message(const psa_key_attributes_t *attribu sign_buf[s_index] = 0; if (key_buffer_size == SL_SI91X_ECDSA_PUB_KEY_SIZE_224) { - memcpy(&sign_buf[r_index + r_bit], &signature[0], SL_SI91X_ECDSA_SIGN_HALF_SIZE_P224R1); - memcpy(&sign_buf[s_index + s_bit], - &signature[SL_SI91X_ECDSA_SIGN_HALF_SIZE_P224R1], - SL_SI91X_ECDSA_SIGN_HALF_SIZE_P224R1); + memcpy(&sign_buf[r_index + r_bit], &signature[0 + r_leading], r_size - r_bit); + memcpy(&sign_buf[s_index + s_bit], &signature[SL_SI91X_ECDSA_SIGN_HALF_SIZE_P224R1 + s_leading], s_size - s_bit); } else if (key_buffer_size == SL_SI91X_ECDSA_PUB_KEY_SIZE_256) { - memcpy(&sign_buf[r_index + r_bit], &signature[0], SL_SI91X_ECDSA_SIGN_HALF_SIZE_P256R1); - memcpy(&sign_buf[s_index + s_bit], - &signature[SL_SI91X_ECDSA_SIGN_HALF_SIZE_P256R1], - SL_SI91X_ECDSA_SIGN_HALF_SIZE_P256R1); + memcpy(&sign_buf[r_index + r_bit], &signature[0 + r_leading], r_size - r_bit); + memcpy(&sign_buf[s_index + s_bit], &signature[SL_SI91X_ECDSA_SIGN_HALF_SIZE_P256R1 + s_leading], s_size - s_bit); } uint8_t *output = (uint8_t *)malloc(sizeof(uint8_t)); diff --git a/components/device/silabs/si91x/wireless/crypto/gcm/src/sl_si91x_gcm.c b/components/device/silabs/si91x/wireless/crypto/gcm/src/sl_si91x_gcm.c index 7527e8db5..e5253f0a1 100644 --- a/components/device/silabs/si91x/wireless/crypto/gcm/src/sl_si91x_gcm.c +++ b/components/device/silabs/si91x/wireless/crypto/gcm/src/sl_si91x_gcm.c @@ -39,6 +39,22 @@ #endif #include +#ifdef SLI_SI917B0 +static void sli_si91x_gcm_get_key_info(sl_si91x_gcm_request_t *request, const sl_si91x_gcm_config_t *config) +{ + request->gcm_mode = config->gcm_mode; + request->key_info.key_type = config->key_config.b0.key_type; + request->key_info.key_detail.key_size = (config->key_config.b0.key_size) * 8; + request->key_info.key_detail.key_spec.key_slot = config->key_config.b0.key_slot; + request->key_info.key_detail.key_spec.wrap_iv_mode = config->key_config.b0.wrap_iv_mode; + request->key_info.reserved = config->key_config.b0.reserved; + if (config->key_config.b0.wrap_iv_mode) { + memcpy(request->key_info.key_detail.key_spec.wrap_iv, config->key_config.b0.wrap_iv, SL_SI91X_IV_SIZE); + } + memcpy(request->key_info.key_detail.key_spec.key_buffer, config->key_config.b0.key_buffer, SL_SI91X_KEY_BUFFER_SIZE); +} +#endif + #ifndef SL_SI91X_SIDE_BAND_CRYPTO static sl_status_t sli_si91x_gcm_pending(sl_si91x_gcm_config_t *config, uint16_t chunk_length, @@ -84,18 +100,7 @@ static sl_status_t sli_si91x_gcm_pending(sl_si91x_gcm_config_t *config, memcpy(request->msg, config->msg, chunk_length); #ifdef SLI_SI917B0 - request->gcm_mode = config->gcm_mode; - request->key_info.key_type = config->key_config.b0.key_type; - request->key_info.key_detail.key_size = (config->key_config.b0.key_size) * 8; - request->key_info.key_detail.key_spec.key_slot = config->key_config.b0.key_slot; - request->key_info.key_detail.key_spec.wrap_iv_mode = config->key_config.b0.wrap_iv_mode; - request->key_info.reserved = config->key_config.b0.reserved; - if (config->key_config.b0.wrap_iv_mode) { - memcpy(request->key_info.key_detail.key_spec.wrap_iv, config->key_config.b0.wrap_iv, SL_SI91X_IV_SIZE); - } - memcpy(request->key_info.key_detail.key_spec.key_buffer, - config->key_config.b0.key_buffer, - config->key_config.b0.key_size); + sli_si91x_gcm_get_key_info(request, config); #else memcpy(request->key, config->key_config.a0.key, request->key_length); @@ -165,18 +170,7 @@ static sl_status_t sli_si91x_gcm_side_band(sl_si91x_gcm_config_t *config, uint8_ request->msg = (uint8_t *)config->msg; request->output = output; - request->gcm_mode = config->gcm_mode; - request->key_info.key_type = config->key_config.b0.key_type; - request->key_info.key_detail.key_size = (config->key_config.b0.key_size) * 8; - request->key_info.key_detail.key_spec.key_slot = config->key_config.b0.key_slot; - request->key_info.key_detail.key_spec.wrap_iv_mode = config->key_config.b0.wrap_iv_mode; - request->key_info.reserved = config->key_config.b0.reserved; - if (config->key_config.b0.wrap_iv_mode) { - memcpy(request->key_info.key_detail.key_spec.wrap_iv, config->key_config.b0.wrap_iv, SL_SI91X_IV_SIZE); - } - memcpy(request->key_info.key_detail.key_spec.key_buffer, - config->key_config.b0.key_buffer, - config->key_config.b0.key_size); + sli_si91x_gcm_get_key_info(request, config); status = sl_si91x_driver_send_side_band_crypto(RSI_COMMON_REQ_ENCRYPT_CRYPTO, request, diff --git a/components/device/silabs/si91x/wireless/crypto/hmac/src/sl_si91x_hmac.c b/components/device/silabs/si91x/wireless/crypto/hmac/src/sl_si91x_hmac.c index e02da0de6..ec513da90 100644 --- a/components/device/silabs/si91x/wireless/crypto/hmac/src/sl_si91x_hmac.c +++ b/components/device/silabs/si91x/wireless/crypto/hmac/src/sl_si91x_hmac.c @@ -173,6 +173,10 @@ sl_status_t sl_si91x_hmac(sl_si91x_hmac_config_t *config, uint8_t *output) memcpy((data + key_length), config->msg, config->msg_length); // Copy message into data #ifdef SL_SI91X_SIDE_BAND_CRYPTO + // to avoid unused variable warning + UNUSED_VARIABLE(chunk_len); + UNUSED_VARIABLE(offset); + UNUSED_VARIABLE(hmac_sha_flags); status = sli_si91x_hmac_side_band(total_length, data, config, output); return status; #else diff --git a/components/device/silabs/si91x/wireless/crypto/sha/src/sl_si91x_sha.c b/components/device/silabs/si91x/wireless/crypto/sha/src/sl_si91x_sha.c index fc4fd7f1f..8846a6d4e 100644 --- a/components/device/silabs/si91x/wireless/crypto/sha/src/sl_si91x_sha.c +++ b/components/device/silabs/si91x/wireless/crypto/sha/src/sl_si91x_sha.c @@ -27,13 +27,13 @@ #include "sl_si91x_sha.h" #include +#ifndef SL_SI91X_SIDE_BAND_CRYPTO static const uint8_t sha_digest_len_table[] = { [SL_SI91x_SHA_1] = SL_SI91x_SHA_1_DIGEST_LEN, [SL_SI91x_SHA_256] = SL_SI91x_SHA_256_DIGEST_LEN, [SL_SI91x_SHA_384] = SL_SI91x_SHA_384_DIGEST_LEN, [SL_SI91x_SHA_512] = SL_SI91x_SHA_512_DIGEST_LEN, [SL_SI91x_SHA_224] = SL_SI91x_SHA_224_DIGEST_LEN }; -#ifndef SL_SI91X_SIDE_BAND_CRYPTO static sl_status_t sli_si91x_sha_pending(uint8_t sha_mode, uint8_t *msg, uint16_t msg_length, @@ -94,6 +94,9 @@ static sl_status_t sli_si91x_sha_pending(uint8_t sha_mode, packet = sl_si91x_host_get_buffer_data(buffer, 0, NULL); + if (pending_flag == (LAST_CHUNK | FIRST_CHUNK) || pending_flag == LAST_CHUNK) { + SL_ASSERT(packet->length == sha_digest_len_table[sha_mode]); + } memcpy(digest, packet->data, sha_digest_len_table[sha_mode]); free(request); @@ -147,12 +150,6 @@ sl_status_t sl_si91x_sha(uint8_t sha_mode, uint8_t *msg, uint16_t msg_length, ui { sl_status_t status = SL_STATUS_OK; SL_PRINTF(SL_SHA_ENTRY, CRYPTO, LOG_INFO); - uint16_t total_len = 0; - uint16_t chunk_len = 0; - uint16_t offset = 0; - uint8_t sha_flags = 0; - - total_len = msg_length; #if defined(SLI_MULTITHREAD_DEVICE_SI91X) if (crypto_sha_mutex == NULL) { @@ -165,7 +162,12 @@ sl_status_t sl_si91x_sha(uint8_t sha_mode, uint8_t *msg, uint16_t msg_length, ui status = sli_si91x_sha_side_band(sha_mode, msg, msg_length, digest); return status; #else + uint16_t total_len = 0; + uint16_t chunk_len = 0; + uint16_t offset = 0; + uint8_t sha_flags = 0; + total_len = msg_length; if (total_len != 0) { while (total_len) { // Check total length diff --git a/components/device/silabs/si91x/wireless/crypto/trng/src/sl_si91x_trng.c b/components/device/silabs/si91x/wireless/crypto/trng/src/sl_si91x_trng.c index 7102eb5bd..b5a0f0980 100644 --- a/components/device/silabs/si91x/wireless/crypto/trng/src/sl_si91x_trng.c +++ b/components/device/silabs/si91x/wireless/crypto/trng/src/sl_si91x_trng.c @@ -31,6 +31,39 @@ uint32_t trng_key[TRNG_KEY_SIZE] = { 0x16157E2B, 0xA6D2AE28, 0x8815F7AB, 0x3C4FCF09 }; #endif //SLI_TRNG_DEVICE_SI91X +#ifndef SL_SI91X_SIDE_BAND_CRYPTO +static sl_status_t sli_si91x_trng_send_command(sl_si91x_trng_request_t *request, sl_wifi_buffer_t **buffer) +{ + sl_status_t status = SL_STATUS_OK; + +#if defined(SLI_MULTITHREAD_DEVICE_SI91X) + if (crypto_trng_mutex == NULL) { + crypto_trng_mutex = sl_si91x_crypto_threadsafety_init(crypto_trng_mutex); + } + mutex_result = sl_si91x_crypto_mutex_acquire(crypto_trng_mutex); +#endif + + status = sl_si91x_driver_send_command(RSI_COMMON_REQ_ENCRYPT_CRYPTO, + SI91X_COMMON_CMD_QUEUE, + request, + sizeof(sl_si91x_trng_request_t), + SL_SI91X_WAIT_FOR_RESPONSE(32000), + NULL, + buffer); + if (status != SL_STATUS_OK) { + free(request); + if (*buffer != NULL) + sl_si91x_host_free_buffer(*buffer); +#if defined(SLI_MULTITHREAD_DEVICE_SI91X) + mutex_result = sl_si91x_crypto_mutex_release(crypto_trng_mutex); +#endif + } + VERIFY_STATUS_AND_RETURN(status); + + return status; +} +#endif + sl_status_t sl_si91x_trng_init(sl_si91x_trng_config_t *config, uint32_t *output) { sl_wifi_buffer_t *buffer = NULL; @@ -65,29 +98,11 @@ sl_status_t sl_si91x_trng_init(sl_si91x_trng_config_t *config, uint32_t *output) memcpy(request->trng_key, config->trng_key, TRNG_KEY_SIZE * 4); memcpy(request->msg, config->trng_test_data, config->input_length * 4); -#if defined(SLI_MULTITHREAD_DEVICE_SI91X) - if (crypto_trng_mutex == NULL) { - crypto_trng_mutex = sl_si91x_crypto_threadsafety_init(crypto_trng_mutex); - } - mutex_result = sl_si91x_crypto_mutex_acquire(crypto_trng_mutex); -#endif + status = sli_si91x_trng_send_command(request, &buffer); - status = sl_si91x_driver_send_command(RSI_COMMON_REQ_ENCRYPT_CRYPTO, - SI91X_COMMON_CMD_QUEUE, - request, - sizeof(sl_si91x_trng_request_t), - SL_SI91X_WAIT_FOR_RESPONSE(32000), - NULL, - &buffer); if (status != SL_STATUS_OK) { - free(request); - if (buffer != NULL) - sl_si91x_host_free_buffer(buffer); -#if defined(SLI_MULTITHREAD_DEVICE_SI91X) - mutex_result = sl_si91x_crypto_mutex_release(crypto_trng_mutex); -#endif + return status; } - VERIFY_STATUS_AND_RETURN(status); packet = sl_si91x_host_get_buffer_data(buffer, 0, NULL); memcpy(output, packet->data, packet->length); #endif @@ -172,30 +187,11 @@ sl_status_t sl_si91x_trng_program_key(uint32_t *trng_key, uint16_t key_length) #else memcpy(request->trng_key, trng_key, TRNG_KEY_SIZE * 4); -#if defined(SLI_MULTITHREAD_DEVICE_SI91X) - if (crypto_trng_mutex == NULL) { - crypto_trng_mutex = sl_si91x_crypto_threadsafety_init(crypto_trng_mutex); - } - mutex_result = sl_si91x_crypto_mutex_acquire(crypto_trng_mutex); -#endif + status = sli_si91x_trng_send_command(request, &buffer); - status = sl_si91x_driver_send_command(RSI_COMMON_REQ_ENCRYPT_CRYPTO, - SI91X_COMMON_CMD_QUEUE, - request, - sizeof(sl_si91x_trng_request_t), - SL_SI91X_WAIT_FOR_RESPONSE(32000), - NULL, - &buffer); if (status != SL_STATUS_OK) { - free(request); - if (buffer != NULL) - sl_si91x_host_free_buffer(buffer); -#if defined(SLI_MULTITHREAD_DEVICE_SI91X) - mutex_result = sl_si91x_crypto_mutex_release(crypto_trng_mutex); -#endif + return status; } - VERIFY_STATUS_AND_RETURN(status); - packet = sl_si91x_host_get_buffer_data(buffer, 0, NULL); memcpy(trng_key, packet->data, packet->length); #endif diff --git a/components/device/silabs/si91x/wireless/crypto/wrap/inc/sl_si91x_psa_wrap.h b/components/device/silabs/si91x/wireless/crypto/wrap/inc/sl_si91x_psa_wrap.h index 0dd1d4da0..d43f887ba 100644 --- a/components/device/silabs/si91x/wireless/crypto/wrap/inc/sl_si91x_psa_wrap.h +++ b/components/device/silabs/si91x/wireless/crypto/wrap/inc/sl_si91x_psa_wrap.h @@ -25,6 +25,10 @@ extern unsigned char WRAP_IV[]; #define PSA_KEY_VOLATILE_PERSISTENT_WRAPPED ((psa_key_location_t)0x000001) +// The PSA key is given in wrapped format to psa_import_key and other APIs + +#define PSA_KEY_VOLATILE_PERSISTENT_WRAP_IMPORT ((psa_key_location_t)0x800000) +// The PSA key is given in plain format, to be wrapped in psa_import_key API and used in wrapped format with other APIs /** * @brief diff --git a/components/device/silabs/si91x/wireless/crypto/wrap/src/sl_si91x_psa_wrap.c b/components/device/silabs/si91x/wireless/crypto/wrap/src/sl_si91x_psa_wrap.c index 0b817626f..fc5a0d36e 100644 --- a/components/device/silabs/si91x/wireless/crypto/wrap/src/sl_si91x_psa_wrap.c +++ b/components/device/silabs/si91x/wireless/crypto/wrap/src/sl_si91x_psa_wrap.c @@ -27,26 +27,44 @@ unsigned char WRAP_IV[] = { 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46 }; -psa_status_t sli_si91x_crypto_wrap_key(uint8_t *key_buffer, - size_t key_buffer_size, - uint32_t wrap_mode, - uint8_t *wrap_iv_var) +static psa_status_t sli_si91x_crypto_get_wrap_config_key_info(uint8_t *key_buffer, + size_t key_buffer_size, + uint32_t wrap_mode, + uint8_t *wrap_iv_var, + sl_si91x_wrap_config_t *wrap_config) { /* Input pointer check */ - if ((key_buffer == NULL) || (key_buffer_size == 0) || (wrap_iv_var == NULL) + if ((key_buffer == NULL) || (key_buffer_size == 0) || (wrap_iv_var == NULL) || (wrap_config == NULL) || ((wrap_mode != SL_SI91X_WRAP_IV_ECB_MODE) && (wrap_mode != SL_SI91X_WRAP_IV_CBC_MODE))) { return PSA_ERROR_INVALID_ARGUMENT; } - psa_status_t status = PSA_SUCCESS; - sl_status_t si91x_status = SL_STATUS_OK; - sl_si91x_wrap_config_t wrap_config = { 0 }; + /* Fill the key info */ /* We are passing plain key to get wrap key */ - wrap_config.key_type = SL_SI91X_TRANSPARENT_KEY; - wrap_config.key_size = key_buffer_size; - wrap_config.wrap_iv_mode = wrap_mode; + wrap_config->key_type = SL_SI91X_TRANSPARENT_KEY; + wrap_config->key_size = key_buffer_size; + wrap_config->wrap_iv_mode = wrap_mode; if (wrap_mode == SL_SI91X_WRAP_IV_CBC_MODE) { - memcpy(wrap_config.wrap_iv, wrap_iv_var, SL_SI91X_IV_SIZE); + memcpy(wrap_config->wrap_iv, wrap_iv_var, SL_SI91X_IV_SIZE); + } + + return PSA_SUCCESS; +} + +psa_status_t sli_si91x_crypto_wrap_key(uint8_t *key_buffer, + size_t key_buffer_size, + uint32_t wrap_mode, + uint8_t *wrap_iv_var) +{ + + psa_status_t status = PSA_SUCCESS; + sl_status_t si91x_status = SL_STATUS_OK; + sl_si91x_wrap_config_t wrap_config = { 0 }; + + status = sli_si91x_crypto_get_wrap_config_key_info(key_buffer, key_buffer_size, wrap_mode, wrap_iv_var, &wrap_config); + + if (status != PSA_SUCCESS) { + return PSA_ERROR_INVALID_ARGUMENT; } memcpy(wrap_config.key_buffer, key_buffer, wrap_config.key_size); @@ -67,23 +85,15 @@ psa_status_t sli_si91x_crypto_generate_symm_key(uint8_t *key_buffer, uint32_t wrap_mode, uint8_t *wrap_iv_var) { - if ((key_buffer == NULL) || (key_buffer_size == 0) || (wrap_iv_var == NULL) - || ((wrap_mode != SL_SI91X_WRAP_IV_ECB_MODE) && (wrap_mode != SL_SI91X_WRAP_IV_CBC_MODE))) { - return PSA_ERROR_INVALID_ARGUMENT; - } psa_status_t status = PSA_SUCCESS; sl_status_t si91x_status = SL_STATUS_OK; sl_si91x_wrap_config_t wrap_config = { 0 }; - /* Fill the key info */ - /* We are passing plain key to get wrap key */ - wrap_config.key_type = SL_SI91X_TRANSPARENT_KEY; - wrap_config.key_size = key_buffer_size; - wrap_config.wrap_iv_mode = wrap_mode; - if (wrap_mode == SL_SI91X_WRAP_IV_CBC_MODE) { - memcpy(wrap_config.wrap_iv, wrap_iv_var, SL_SI91X_IV_SIZE); - } + status = sli_si91x_crypto_get_wrap_config_key_info(key_buffer, key_buffer_size, wrap_mode, wrap_iv_var, &wrap_config); + if (status != PSA_SUCCESS) { + return PSA_ERROR_INVALID_ARGUMENT; + } /* Get Random dwords of desired length */ si91x_status = sl_si91x_trng_get_random_num((uint32_t *)wrap_config.key_buffer, (wrap_config.key_size)); status = convert_si91x_error_code_to_psa_status(si91x_status); diff --git a/components/device/silabs/si91x/wireless/firmware_upgrade/firmware_upgradation.c b/components/device/silabs/si91x/wireless/firmware_upgrade/firmware_upgradation.c index f5544c097..6dac8da4a 100644 --- a/components/device/silabs/si91x/wireless/firmware_upgrade/firmware_upgradation.c +++ b/components/device/silabs/si91x/wireless/firmware_upgrade/firmware_upgradation.c @@ -29,14 +29,16 @@ ******************************************************/ // Macro to check if malloc failed #define VERIFY_MALLOC_AND_RETURN(ptr) \ - { \ + do { \ if (ptr == NULL) { \ return SL_STATUS_ALLOCATION_FAILED; \ } \ - } + } while (0) #define MIN(a, b) ((a) < (b) ? (a) : (b)) +#define IP_VERSION_6 BIT(1) + /****************************************************** * Global Variables ******************************************************/ @@ -54,9 +56,9 @@ extern bool device_initialized; * @return * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. ******************************************************************************/ -static sl_status_t sl_si91x_fwup(uint16_t type, uint8_t *content, uint16_t length); +static sl_status_t sl_si91x_fwup(uint16_t type, const uint8_t *content, uint16_t length); -static sl_status_t sl_si91x_fwup(uint16_t type, uint8_t *content, uint16_t length) +static sl_status_t sl_si91x_fwup(uint16_t type, const uint8_t *content, uint16_t length) { sl_status_t status = SL_STATUS_FAIL; sl_si91x_req_fwup_t fwup = { 0 }; @@ -78,7 +80,7 @@ static sl_status_t sl_si91x_fwup(uint16_t type, uint8_t *content, uint16_t lengt SI91X_WLAN_CMD_QUEUE, &fwup, sizeof(sl_si91x_req_fwup_t), - SL_SI91X_WAIT_FOR_COMMAND_SUCCESS, + SL_SI91X_WAIT_FOR_RESPONSE(5000), NULL, NULL); @@ -105,7 +107,7 @@ sl_status_t sl_si91x_fwup_abort() } sl_status_t sl_si91x_http_otaf(uint8_t type, - uint8_t flags, + uint16_t flags, uint8_t *ip_address, uint16_t port, uint8_t *resource, @@ -113,7 +115,7 @@ sl_status_t sl_si91x_http_otaf(uint8_t type, uint8_t *extended_header, uint8_t *user_name, uint8_t *password, - uint8_t *post_data, + const uint8_t *post_data, uint32_t post_data_length) { sl_status_t status = SL_STATUS_FAIL; @@ -121,16 +123,18 @@ sl_status_t sl_si91x_http_otaf(uint8_t type, uint32_t send_size = 0; uint16_t http_length = 0; uint16_t length = 0; - uint8_t https_enable = 0; + uint16_t https_enable = 0; uint8_t packet_identifier = 0; sl_si91x_http_client_request_t *packet_buffer = NULL; - uint16_t offset = 0, rem_length = 0, chunk_size = 0; + uint16_t offset = 0; + uint16_t rem_length = 0; + uint16_t chunk_size = 0; if (!device_initialized) { return SL_STATUS_NOT_INITIALIZED; } - if (flags & SL_IPV6) { + if (flags & IP_VERSION_6) { http_client.ip_version = SL_IPV6_VERSION; } else { http_client.ip_version = SL_IPV4_VERSION; @@ -153,10 +157,23 @@ sl_status_t sl_si91x_http_otaf(uint8_t type, https_enable |= SL_SI91X_TLS_V_1_1; } + if (flags & SL_SI91X_TLS_V_1_2) { + https_enable |= SL_SI91X_TLS_V_1_2; + } + // Set HTTP version 1.1 feature bit if (flags & SL_SI91X_HTTP_V_1_1) { https_enable |= SL_SI91X_HTTP_V_1_1; } + + if (flags & SL_SI91X_HTTPS_CERTIFICATE_INDEX_1) { + https_enable |= SL_SI91X_HTTPS_CERTIFICATE_INDEX_1; + } + + if (flags & SL_SI91X_HTTPS_CERTIFICATE_INDEX_2) { + https_enable |= SL_SI91X_HTTPS_CERTIFICATE_INDEX_2; + } + // Fill https features parameters http_client.https_enable = https_enable; @@ -165,12 +182,12 @@ sl_status_t sl_si91x_http_otaf(uint8_t type, memset(http_client.buffer, 0, sizeof(http_client.buffer)); // Fill username - length = MIN((sizeof(http_client.buffer) - 1), strlen((char *)user_name)); + length = (uint16_t)MIN((sizeof(http_client.buffer) - 1), strlen((char *)user_name)); memcpy(http_client.buffer, user_name, length); http_length += length + 1; // Fill password - length = MIN((sizeof(http_client.buffer) - 1 - http_length), strlen((char *)password)); + length = (uint16_t)MIN((sizeof(http_client.buffer) - 1 - http_length), strlen((char *)password)); memcpy(((http_client.buffer) + http_length), password, length); http_length += length + 1; @@ -180,23 +197,23 @@ sl_status_t sl_si91x_http_otaf(uint8_t type, } // Copy Host name - length = MIN((sizeof(http_client.buffer) - 1 - http_length), strlen((char *)host_name)); + length = (uint16_t)MIN((sizeof(http_client.buffer) - 1 - http_length), strlen((char *)host_name)); memcpy(((http_client.buffer) + http_length), host_name, length); http_length += length + 1; // Copy IP address - length = MIN((sizeof(http_client.buffer) - 1 - http_length), strlen((char *)ip_address)); + length = (uint16_t)MIN((sizeof(http_client.buffer) - 1 - http_length), strlen((char *)ip_address)); memcpy(((http_client.buffer) + http_length), ip_address, length); http_length += length + 1; // Copy URL resource - length = MIN((sizeof(http_client.buffer) - 1 - http_length), strlen((char *)resource)); + length = (uint16_t)MIN((sizeof(http_client.buffer) - 1 - http_length), strlen((char *)resource)); memcpy(((http_client.buffer) + http_length), resource, length); http_length += length + 1; // Copy Extended header if (extended_header != NULL) { - length = MIN((sizeof(http_client.buffer) - 1 - http_length), strlen((char *)extended_header)); + length = (uint16_t)MIN((sizeof(http_client.buffer) - 1 - http_length), strlen((char *)extended_header)); memcpy(((http_client.buffer) + http_length), extended_header, length); http_length += length; } @@ -264,4 +281,4 @@ sl_status_t sl_si91x_http_otaf(uint8_t type, } VERIFY_STATUS_AND_RETURN(status); return status; -} +} \ No newline at end of file diff --git a/components/device/silabs/si91x/wireless/firmware_upgrade/firmware_upgradation.h b/components/device/silabs/si91x/wireless/firmware_upgrade/firmware_upgradation.h index c2cc704b1..ca3e55a88 100644 --- a/components/device/silabs/si91x/wireless/firmware_upgrade/firmware_upgradation.h +++ b/components/device/silabs/si91x/wireless/firmware_upgrade/firmware_upgradation.h @@ -35,47 +35,52 @@ * \ingroup SI91X_FIRMWARE_UPDATE_FUNCTIONS * @{ */ -/***************************************************************************/ /** +/***************************************************************************/ +/** * @brief - * Post the HTTP data for the requested URL to HTTP server.This is a non-blocking API. + * Sends an HTTP request to a specified server URL with optional data and headers, + * and facilitates firmware downloads from the server. This API is non-blocking API. * @param[in] type - * Valid values are: 0 - HTTPGET, 1 - HTTPPOST + * Valid values are: 2 - HTTP_OTAF * @param[in] flags - * Select version and security: -* - * |Flags | Macro | Description | - * |:------|:----------------|:-----------------------------------------------------------------------| - * |BIT(0) | HTTPS_SUPPORT | Set this bit to enable HTTPS_SUPPORT to use HTTPS feature. | - * |BIT(1) | SSL_ENABLE | Set this bit to enable SSL feature. | - * |BIT(2) | SI91X_TLS_V_1_0 | Set this bit to support SSL TLS Version 1.0 if HTTPS is enabled. | - * |BIT(3) | IPV6 | Set this bit to enable IPv6, by default it is configured to IPv4. | - * |BIT(4) | SI91X_TLS_V_1_1 | Set this bit to support SSL_TLS Version 1.1 if HTTPS is enabled. | - * |BIT(5) | HTTP_POST_DATA | Set this bit to enable Http_post large data feature.| - * |BIT(6) | HTTP_V_1_1 | Set this bit to use HTTP version 1.1 | + * Configuration flags. See the table below for details. * @param[in] ip_address * Server IP address. * @param[in] port - * Port number. Default : 80 - HTTP, 443 - HTTPS + * Port number. Default: 80 - HTTP, 443 - HTTPS * @param[in] resource * Requested resource URL in string format. * @param[in] host_name * Host name. * @param[in] extended_header - * Extender header if present, after each header member append \r\c -* + * Extended header if present, each header member should end with \r\n. * @param[in] username * Username for server authentication. * @param[in] password * Password for server authentication. * @param[in] post_data - * HTTP data to be posted to server. + * HTTP data to be posted to the server. * @param[in] post_data_length - * HTTP data length to be posted to server. + * HTTP data length to be posted to the server. * @return * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + * + * @details + * The following table lists the flags that can be used with this function: + * + * | Flags | Macro | Description | + * |:-------|:------------------------------------|:-----------------------------------------------------------------------| + * | BIT(0) | HTTPS_SUPPORT | Set this bit to enable HTTPS_SUPPORT to use HTTPS feature. | + * | BIT(1) | IP_VERSION_6 | Set this bit to enable IPv6. By default, it is configured to IPv4. | + * | BIT(2) | SI91X_TLS_V_1_0 | Set this bit to support SSL TLS Version 1.0 if HTTPS is enabled. | + * | BIT(3) | SI91X_TLS_V_1_2 | Set this bit to support SSL TLS Version 1.2 if HTTPS is enabled. | + * | BIT(4) | SI91X_TLS_V_1_1 | Set this bit to support SSL_TLS Version 1.1 if HTTPS is enabled. | + * | BIT(6) | HTTP_V_1_1 | Set this bit to use HTTP version 1.1 | + * | BIT(9) | SL_SI91X_HTTPS_CERTIFICATE_INDEX_1 | Set this bit to specify index of SSL cert to be used for HTTPS. | + * | BIT(10) | SL_SI91X_HTTPS_CERTIFICATE_INDEX_2 | Set this bit to specify index of SSL cert to be used for HTTPS. ******************************************************************************/ sl_status_t sl_si91x_http_otaf(uint8_t type, - uint8_t flags, + uint16_t flags, uint8_t *ip_address, uint16_t port, uint8_t *resource, @@ -83,7 +88,7 @@ sl_status_t sl_si91x_http_otaf(uint8_t type, uint8_t *extended_header, uint8_t *user_name, uint8_t *password, - uint8_t *post_data, + const uint8_t *post_data, uint32_t post_data_length); /** @} */ diff --git a/components/device/silabs/si91x/wireless/host_mcu/efr32fg25/efx32_ncp_host.c b/components/device/silabs/si91x/wireless/host_mcu/efr32fg25/efx32_ncp_host.c index f79110def..0051d508c 100644 --- a/components/device/silabs/si91x/wireless/host_mcu/efr32fg25/efx32_ncp_host.c +++ b/components/device/silabs/si91x/wireless/host_mcu/efr32fg25/efx32_ncp_host.c @@ -39,7 +39,7 @@ static bool dma_callback(unsigned int channel, unsigned int sequenceNo, void *us unsigned int rx_ldma_channel; unsigned int tx_ldma_channel; -osMutexId_t spi_transfer_mutex = 0; +osMutexId_t spi_transfer_mutex = NULL; static uint32_t dummy_buffer; static uint8_t host_initialized = 0; @@ -141,7 +141,7 @@ sl_status_t sl_si91x_host_init(sl_si91x_host_init_configuration *config) transfer_done_semaphore = osSemaphoreNew(1, 0, NULL); } - if (spi_transfer_mutex == 0) { + if (spi_transfer_mutex == NULL) { spi_transfer_mutex = osMutexNew(NULL); } @@ -150,7 +150,7 @@ sl_status_t sl_si91x_host_init(sl_si91x_host_init_configuration *config) DMADRV_AllocateChannel(&tx_ldma_channel, NULL); // Start reset line low - GPIO_PinModeSet(RESET_PIN.port, RESET_PIN.pin, gpioModePushPull, 0); + GPIO_PinModeSet(RESET_PIN.port, RESET_PIN.pin, gpioModeWiredAnd, 0); // configure packet pending interrupt priority NVIC_SetPriority(GPIO_ODD_IRQn, PACKET_PENDING_INT_PRI); @@ -162,7 +162,12 @@ sl_status_t sl_si91x_host_init(sl_si91x_host_init_configuration *config) GPIO_PinModeSet(SLEEP_CONFIRM_PIN.port, SLEEP_CONFIRM_PIN.pin, gpioModeWiredOrPullDown, 1); GPIO_PinModeSet(WAKE_INDICATOR_PIN.port, WAKE_INDICATOR_PIN.pin, gpioModeWiredOrPullDown, 0); host_initialized = 1; + } else { + if (spi_transfer_mutex == NULL) { + spi_transfer_mutex = osMutexNew(NULL); + } } + return SL_STATUS_OK; } @@ -254,13 +259,12 @@ sl_status_t sl_si91x_host_spi_transfer(const void *tx_buffer, void *rx_buffer, u void sl_si91x_host_hold_in_reset(void) { - GPIO_PinModeSet(RESET_PIN.port, RESET_PIN.pin, gpioModePushPull, 1); GPIO_PinOutClear(RESET_PIN.port, RESET_PIN.pin); } void sl_si91x_host_release_from_reset(void) { - GPIO_PinModeSet(RESET_PIN.port, RESET_PIN.pin, gpioModeWiredOrPullDown, 1); + GPIO_PinOutSet(RESET_PIN.port, RESET_PIN.pin); } void sl_si91x_host_enable_bus_interrupt(void) diff --git a/components/device/silabs/si91x/wireless/host_mcu/efx32/efx32_ncp_host.c b/components/device/silabs/si91x/wireless/host_mcu/efx32/efx32_ncp_host.c index da3ce6bce..a5b200867 100644 --- a/components/device/silabs/si91x/wireless/host_mcu/efx32/efx32_ncp_host.c +++ b/components/device/silabs/si91x/wireless/host_mcu/efx32/efx32_ncp_host.c @@ -36,6 +36,16 @@ #define LDMA_MAX_TRANSFER_LENGTH 4096 #define LDMA_DESCRIPTOR_ARRAY_LENGTH (LDMA_MAX_TRANSFER_LENGTH / 2048) +#ifndef SL_SI91X_NCP_UART_BAUDRATE +// ToDo: This Macro is depricated and should be removed in upcoming releases. +// Keeping this macro functionality intact due to backward compatability. +#if SL_SI91X_UART_HIGH_SPEED_ENABLE == 1 +#define SL_SI91X_NCP_UART_BAUDRATE 921600 +#else +#define SL_SI91X_NCP_UART_BAUDRATE 115200 +#endif +#endif + #ifndef SL_NCP_UART_INTERFACE #include "spidrv.h" @@ -220,7 +230,14 @@ static void efx32_spi_init(void) NVIC_SetPriority(NCP_RX_IRQ, PACKET_PENDING_INT_PRI); GPIOINT_CallbackRegister(SI91X_NCP_INTERRUPT_PIN, gpio_interrupt); GPIO_PinModeSet(SI91X_NCP_INTERRUPT_PORT, SI91X_NCP_INTERRUPT_PIN, gpioModeInputPullFilter, 0); - GPIO_ExtIntConfig(SI91X_NCP_INTERRUPT_PORT, SI91X_NCP_INTERRUPT_PIN, SI91X_NCP_INTERRUPT_PIN, true, false, true); + + // Check if the boot option is set to LOAD_DEFAULT_NWP_FW_ACTIVE_LOW + if (init_config.boot_option == LOAD_DEFAULT_NWP_FW_ACTIVE_LOW) + // Configure the GPIO external interrupt for active low configuration + GPIO_ExtIntConfig(SI91X_NCP_INTERRUPT_PORT, SI91X_NCP_INTERRUPT_PIN, SI91X_NCP_INTERRUPT_PIN, false, true, true); + else + // Configure the GPIO external interrupt for active high configuration + GPIO_ExtIntConfig(SI91X_NCP_INTERRUPT_PORT, SI91X_NCP_INTERRUPT_PIN, SI91X_NCP_INTERRUPT_PIN, true, false, true); return; } @@ -278,8 +295,9 @@ uint32_t sl_si91x_host_get_wake_indicator(void) sl_status_t sl_si91x_host_init(sl_si91x_host_init_configuration *config) { - init_config.rx_irq = config->rx_irq; - init_config.rx_done = config->rx_done; + init_config.rx_irq = config->rx_irq; + init_config.rx_done = config->rx_done; + init_config.boot_option = config->boot_option; // Enable clock (not needed on xG21) CMU_ClockEnable(cmuClock_GPIO, true); @@ -299,7 +317,7 @@ sl_status_t sl_si91x_host_init(sl_si91x_host_init_configuration *config) #endif // Start reset line low - GPIO_PinModeSet(SI91X_NCP_RESET_PORT, SI91X_NCP_RESET_PIN, gpioModePushPull, 0); + GPIO_PinModeSet(SI91X_NCP_RESET_PORT, SI91X_NCP_RESET_PIN, gpioModeWiredAnd, 0); // Configure interrupt, sleep and wake confirmation pins GPIO_PinModeSet(SI91X_NCP_SLEEP_CONFIRM_PORT, SI91X_NCP_SLEEP_CONFIRM_PIN, gpioModeWiredOrPullDown, 1); @@ -319,7 +337,7 @@ sl_status_t sl_si91x_host_deinit(void) void sl_si91x_host_enable_high_speed_bus() { #ifdef SL_NCP_UART_INTERFACE - efx32_ncp_uart_init(921600, false); + efx32_ncp_uart_init(SL_SI91X_NCP_UART_BAUDRATE, false); #else //SPI_USART->CTRL_SET |= USART_CTRL_SMSDELAY | USART_CTRL_SSSEARLY; #endif @@ -445,7 +463,7 @@ void sl_si91x_host_flush_uart_rx(void) void sl_si91x_host_uart_enable_hardware_flow_control(void) { #ifdef SL_NCP_UART_INTERFACE - efx32_ncp_uart_init(921600, true); + efx32_ncp_uart_init(SL_SI91X_NCP_UART_BAUDRATE, true); #endif return; @@ -453,13 +471,12 @@ void sl_si91x_host_uart_enable_hardware_flow_control(void) void sl_si91x_host_hold_in_reset(void) { - GPIO_PinModeSet(SI91X_NCP_RESET_PORT, SI91X_NCP_RESET_PIN, gpioModePushPull, 1); GPIO_PinOutClear(SI91X_NCP_RESET_PORT, SI91X_NCP_RESET_PIN); } void sl_si91x_host_release_from_reset(void) { - GPIO_PinModeSet(SI91X_NCP_RESET_PORT, SI91X_NCP_RESET_PIN, gpioModeWiredOrPullDown, 1); + GPIO_PinOutSet(SI91X_NCP_RESET_PORT, SI91X_NCP_RESET_PIN); } void sl_si91x_host_enable_bus_interrupt(void) diff --git a/components/device/silabs/si91x/wireless/host_mcu/stm32/stm32_ncp_host.c b/components/device/silabs/si91x/wireless/host_mcu/stm32/stm32_ncp_host.c index c50f44c6f..bbaad48f2 100644 --- a/components/device/silabs/si91x/wireless/host_mcu/stm32/stm32_ncp_host.c +++ b/components/device/silabs/si91x/wireless/host_mcu/stm32/stm32_ncp_host.c @@ -69,7 +69,7 @@ static void MX_SPI1_Init(void) hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; hspi1.Init.NSS = SPI_NSS_HARD_OUTPUT; - hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_8; hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; hspi1.Init.TIMode = SPI_TIMODE_DISABLE; hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; @@ -223,6 +223,22 @@ sl_status_t sl_si91x_host_spi_transfer(const void *tx_buffer, void *rx_buffer, u void sl_si91x_host_enable_high_speed_bus() { + /* SPI1 parameter configuration*/ + hspi1.Instance = SPI1; + hspi1.Init.Mode = SPI_MODE_MASTER; + hspi1.Init.Direction = SPI_DIRECTION_2LINES; + hspi1.Init.DataSize = SPI_DATASIZE_8BIT; + hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; + hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; + hspi1.Init.NSS = SPI_NSS_HARD_OUTPUT; + hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; + hspi1.Init.TIMode = SPI_TIMODE_DISABLE; + hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + hspi1.Init.CRCPolynomial = 10; + if (HAL_SPI_Init(&hspi1) != HAL_OK) { + Error_Handler(); + } } void sl_si91x_host_enable_bus_interrupt(void) diff --git a/components/device/silabs/si91x/wireless/inc/mqtt/inc/si91x_mqtt_client_utility.h b/components/device/silabs/si91x/wireless/inc/mqtt/inc/si91x_mqtt_client_utility.h index 3213a926f..b84f0fe64 100644 --- a/components/device/silabs/si91x/wireless/inc/mqtt/inc/si91x_mqtt_client_utility.h +++ b/components/device/silabs/si91x/wireless/inc/mqtt/inc/si91x_mqtt_client_utility.h @@ -25,7 +25,7 @@ * @param client Client address that needs to be stored in context. * @param user_context user_context provided by user while calling API. * @param timeout timeout which determines if API needs to be executed in sync or async mode. - * @param si91x_mqtt_client_context_t** A double pointer to client context.This function allocate memory and initializes members if timeout is greater than 0 else pointer is initialized with null + * @param si91x_mqtt_client_context_t** A double pointer to client context.This function allocates memory and initializes members if timeout is greater than 0 else pointer is initialized with null. * @return return SL_STATUS_OK in case of success or appropriate status. */ sl_status_t sli_si91x_build_mqtt_sdk_context_if_async(sl_mqtt_client_event_t event, @@ -42,3 +42,15 @@ sl_status_t sli_si91x_build_mqtt_sdk_context_if_async(sl_mqtt_client_event_t eve * Note: client would be NULL if this function is called before sl_mqtt_client_init or after sl_mqtt_client_deint */ void sli_si91x_get_mqtt_client(sl_mqtt_client_t **client); + +/** + * Cleans up resources used by the MQTT client. + * + * This function is responsible for releasing any resources allocated to the MQTT client, + * ensuring a clean shutdown of the client instance. It should be called when the MQTT + * client is no longer needed, typically at the end of the application or before a restart + * of the MQTT client. + * + * Note: It is important to call this function to prevent resource leaks. + */ +void sli_mqtt_client_cleanup(); diff --git a/components/device/silabs/si91x/wireless/inc/sl_rsi_utility.h b/components/device/silabs/si91x/wireless/inc/sl_rsi_utility.h index da09d0f9b..bffe43a11 100644 --- a/components/device/silabs/si91x/wireless/inc/sl_rsi_utility.h +++ b/components/device/silabs/si91x/wireless/inc/sl_rsi_utility.h @@ -126,7 +126,7 @@ bool get_card_ready_required(); /*Function used to check void save_max_tx_power(uint8_t max_scan_tx_power, uint8_t max_join_tx_power); /*Function used to set the maximum transmission power*/ sl_wifi_max_tx_power_t get_max_tx_power(); /*Function used to get maximum transmission power*/ -void reset_max_tx_power(); /*Function used to set maximum transmission power to default value(31dBm) */ +void reset_max_tx_power(); /*Function used to set maximum transmission power to default value(31 dBm) */ void save_wifi_current_performance_profile( const sl_wifi_performance_profile_t *profile); /*Function used to set the current performance profile*/ @@ -156,11 +156,11 @@ sl_status_t convert_sl_wifi_to_sl_si91x_encryption( /********************************************************************************************* * @brief - * An utility function computes coex performance profile internally and converts into sl_si91x_power_save_request_t. + * A utility function computes coex performance profile internally and converts into sl_si91x_power_save_request_t. * @param profile - * performance profile which needs to be converted to its equivalent si91x_power_save_request structure. + * Performance profile which needs to be converted to its equivalent si91x_power_save_request structure. * @param power_save_request - * si91x specific structure that holds required configuration for the given performance profile. + * Si91x specific structure that holds required configuration for the given performance profile. * This is optional parameter. * @return coex_profile * Coex power profile @@ -212,7 +212,7 @@ void sl_si91x_get_efuse_data(sl_si91x_efuse_data_t *efuse_data); void sl_si91x_set_efuse_data(const sl_si91x_efuse_data_t *efuse_data); /** - * An utility function to convert dBm value to si91x specific power value + * A utility function to convert dBm value to si91x specific power value * @param wifi_max_tx_power which holds the join power value with dBm as units. * @return si91x power level */ @@ -314,8 +314,8 @@ sl_status_t sl_si91x_host_flush_nodes_from_queue(sl_si91x_queue_type_t queue, sl_si91x_node_free_function_t node_free_function); /* Function used to flush all the pending TX packets from the specified queue */ -sl_status_t sl_si91x_flush_queue_based_on_type(sl_si91x_queue_type_t queue, - sl_si91x_node_free_function_t node_free_function); +sl_status_t sli_si91x_flush_queue_based_on_type(sl_si91x_queue_type_t queue, + sl_si91x_node_free_function_t node_free_function); uint32_t sl_si91x_host_queue_status( sl_si91x_queue_type_t queue); /*Function used to check whether queue is empty or not*/ @@ -365,7 +365,7 @@ uint8_t sli_lmac_crc8_c(uint8_t crc8_din, uint8_t crc8_state, uint8_t end); * @return 6-bit Hash value * */ -uint8_t sli_multicast_mac_hash(uint8_t *mac); +uint8_t sli_multicast_mac_hash(const uint8_t *mac); /*==============================================*/ /** @@ -385,7 +385,7 @@ sl_status_t sl_si91x_boot_instruction(uint8_t type, uint16_t *data); * The @ref sl_si91x_bus_enable_high_speed() should be called only if the SPI clock frequency is more than 25 MHz. * @note * SPI initialization has to be done in low-speed mode only. - * After device SPI is configured this API is been used for high-speed mode (>25 MHz). + * After device SPI is configured, this API is used for high-speed mode (>25 MHz). * In addition to this API, the following API sl_si91x_host_enable_high_speed_bus has to be ported by the user to implement the host clock switch. * @return * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. @@ -406,7 +406,7 @@ void sl_si91x_ulp_wakeup_init(void); /*Function used to initialize SPI interface * @param type * It specifies type of credential. * @param cred - * Pointer to store the WiFi credential information of type [sl_wifi_credential_t](../wiseconnect-api-reference-guide-wi-fi/sl-wifi-credential-t) + * Pointer to store the wifi credential information of type [sl_wifi_credential_t](../wiseconnect-api-reference-guide-wi-fi/sl-wifi-credential-t) * @return sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. */ sl_status_t sl_si91x_host_get_credentials(sl_wifi_credential_id_t id, uint8_t type, sl_wifi_credential_t *cred); @@ -417,4 +417,20 @@ void sli_si91x_update_flash_command_status(bool flag); bool sli_si91x_is_sdk_ok_to_sleep(); +/** +* @addtogroup EXTERNAL_HOST_INTERFACE_FUNCTIONS +* @{ +*/ + +/** + * @brief Checks if the device is initialized. + * + * This function is used to verify if the device has been properly initialized. + * + * @return bool. Returns true if the device is initialized, false otherwise. + */ +bool sl_si91x_is_device_initialized(void); + +/** @} */ + #endif // _SL_RSI_UTILITY_H_ diff --git a/components/device/silabs/si91x/wireless/inc/sl_si91x_constants.h b/components/device/silabs/si91x/wireless/inc/sl_si91x_constants.h index 33bc658ce..adc9280f7 100644 --- a/components/device/silabs/si91x/wireless/inc/sl_si91x_constants.h +++ b/components/device/silabs/si91x/wireless/inc/sl_si91x_constants.h @@ -204,6 +204,11 @@ #define SL_SI91X_SIGNATURE_MAX_SIZE 128 #define SL_SI91X_ECDSA_MSG_MAX_SIZE 1000 +// NWP Configuration defines +#define SL_SI91X_XO_CTUNE_FROM_HOST BIT(0) +#define SL_SI91X_ENABLE_NWP_WDT_FROM_HOST BIT(1) +#define SL_SI91X_DISABLE_NWP_WDT_FROM_HOST BIT(2) + //***************************** Macros for Crypto End **********************************/ typedef struct { @@ -234,17 +239,17 @@ typedef enum { typedef enum { SL_SI91X_RETURN_IMMEDIATELY = 0, - SL_SI91X_WAIT_FOR_EVER = 1, SL_SI91X_WAIT_FOR_RESPONSE_BIT = (1 << 30), + SL_SI91X_WAIT_FOR_EVER = (1 << 31), SL_SI91X_WAIT_FOR_SYNC_SCAN_RESULTS = (SL_SI91X_WAIT_FOR_RESPONSE_BIT | 12000), SL_SI91X_WAIT_FOR_COMMAND_RESPONSE = (SL_SI91X_WAIT_FOR_RESPONSE_BIT | 1000), SL_SI91X_WAIT_FOR_SOCKET_ACCEPT_RESPONSE = (SL_SI91X_WAIT_FOR_RESPONSE_BIT | 5000), #ifdef SLI_SI91X_MCU_INTERFACE - SL_SI91X_WAIT_FOR_COMMAND_SUCCESS = (3000), + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS = 3000, #else - SL_SI91X_WAIT_FOR_COMMAND_SUCCESS = (1000), + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS = 1000, #endif - SL_SI91X_WAIT_FOR_DNS_RESOLUTION = (20000), + SL_SI91X_WAIT_FOR_DNS_RESOLUTION = 20000, } sl_si91x_wait_period_t; #define SL_SI91X_WAIT_FOR(x) (sl_si91x_wait_period_t)(x) @@ -265,11 +270,10 @@ typedef enum { /*====================================================*/ // Constant Defines // SPI Status -#define RSI_SPI_SUCCESS 0x58 -#define RSI_SPI_BUSY 0x54 -#define RSI_SPI_FAIL 0x52 -#define RSI_SUCCESS 0 -//#define RSI_ERROR_SPI_BUSY (-1) +#define RSI_SPI_SUCCESS 0x58 +#define RSI_SPI_BUSY 0x54 +#define RSI_SPI_FAIL 0x52 +#define RSI_SUCCESS 0 #define RSI_ERROR_BUFFER_FULL -3 // module buffer full error code #define RSI_ERROR_IN_SLEEP -4 // module in sleep error code @@ -430,7 +434,8 @@ typedef enum { RSI_COMMON_RSP_GET_RAM_DUMP = 0x92, RSI_COMMON_RSP_ASSERT = 0xE1, RSI_COMMON_RSP_SET_RTC_TIMER = 0xE9, - RSI_COMMON_RSP_GET_RTC_TIMER = 0xF2 + RSI_COMMON_RSP_GET_RTC_TIMER = 0xF2, + RSI_COMMON_RSP_SET_CONFIG = 0xBA #ifdef CONFIGURE_GPIO_FROM_HOST , RSI_COMMON_RSP_GPIO_CONFIG = 0x28 diff --git a/components/device/silabs/si91x/wireless/inc/sl_si91x_driver.h b/components/device/silabs/si91x/wireless/inc/sl_si91x_driver.h index b341b1a07..ad6490795 100644 --- a/components/device/silabs/si91x/wireless/inc/sl_si91x_driver.h +++ b/components/device/silabs/si91x/wireless/inc/sl_si91x_driver.h @@ -241,55 +241,37 @@ sl_status_t sl_si91x_wifi_set_certificate_index(uint8_t certificate_type, uint8_t certificate_index, const uint8_t *buffer, uint32_t certificate_length); - +/** \addtogroup SI91X_DRIVER_FUNCTIONS + * \ingroup SL_SI91X_API + * @{ */ /***************************************************************************/ /** * @brief - * Set the host rtc timer. This is a blocking API. + * Sets the Real Time Clock (RTC) of the module.This is a blocking API. * @param[in] timer - * @ref sl_si91x_module_rtc_time_t Pointer to fill RTC time. - * second --> seconds [0-59] - * minute --> minutes [0-59] - * hour --> hours since midnight [0-23] - * day --> day of the month [1-31] - * month --> months since January [0-11] - * year --> year since 1990. - * Weekday--> Weekday from Sunday to Saturday [1-7]. - * @note Hour is 24-hour format only (valid values are 0 to 23). - * Valid values for Month are 0 to 11 (January to December). + * Pointer to an @ref sl_si91x_module_rtc_time_t structure that contains the RTC time to be set. * @pre Pre-conditions: - * - - * @ref sl_si91x_driver_init() API needs to be called before this API + * - The [sl_wifi_init()](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) API must be called prior to this API. + * - The @ref SL_SI91X_CUSTOM_FEAT_RTC_FROM_HOST bit must be enabled in the @ref SI91X_CUSTOM_FEATURE_BITMAP during the [sl_wifi_init()](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) process. * @return * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + * @note + * Ensure that the Real-Time Clock (RTC) timer is configured to enable certificate validation. ******************************************************************************/ -sl_status_t sl_si91x_set_rtc_timer(sl_si91x_module_rtc_time_t *timer); +sl_status_t sl_si91x_set_rtc_timer(const sl_si91x_module_rtc_time_t *timer); /***************************************************************************/ /** * @brief - * Fetch current time from hardware Real Time Clock. This is a blocking API. + * Retrieves the current time from the module's Real Time Clock (RTC).This is a blocking API. * @param[out] response - * @ref sl_si91x_module_rtc_time_t Response of the requested command. - - - * @note Response parameters: - - - * * Pointer to fill RTC time. - * second --> seconds [0-59] - * minute --> minutes [0-59] - * hour --> hours since midnight [0-23] - * day --> day of the month [1-31] - * month --> months since January [0-11] - * year --> year since 1990. - * Weekday--> Weekday from Sunday to Saturday [1-7]. - * @note Hour is 24-hour format only (valid values are 0 to 23). - * Valid values for Month are 0 to 11 (January to December). + * Pointer to an @ref sl_si91x_module_rtc_time_t structure where the RTC's current time will be stored. * @pre Pre-conditions: - * - - * @ref sl_si91x_set_rtc_timer() API needs to be called before this API. - * @ref sl_si91x_driver_init() API needs to be called before this API also. + * - The @ref sl_si91x_set_rtc_timer() API must be called to set the RTC time before attempting to retrieve it. + * - The @ref SL_SI91X_CUSTOM_FEAT_RTC_FROM_HOST bit must be enabled in the @ref SI91X_CUSTOM_FEATURE_BITMAP during the [sl_wifi_init()](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) process to allow RTC time setting and retrieval from the host. * @return * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. ******************************************************************************/ sl_status_t sl_si91x_get_rtc_timer(sl_si91x_module_rtc_time_t *response); +/** @} */ /***************************************************************************/ /** * @brief @@ -319,7 +301,7 @@ sl_status_t sl_si91x_write_calibration_data(const si91x_calibration_data_t *data * @return * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. ******************************************************************************/ -sl_status_t sl_si91x_transmit_test_start(sl_si91x_request_tx_test_info_t *tx_test_info); +sl_status_t sl_si91x_transmit_test_start(const sl_si91x_request_tx_test_info_t *tx_test_info); /***************************************************************************/ /** * @brief * Stop the transmit test. This is a blocking API. @@ -446,7 +428,38 @@ sl_status_t sl_si91x_dpd_calibration(const sl_si91x_get_dpd_calib_data_t *dpd_ca * @return * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. *******************************************************************************/ -sl_status_t sl_si91x_efuse_read(sl_si91x_efuse_read_t *efuse_read, uint8_t *efuse_read_buf); +sl_status_t sl_si91x_efuse_read(const sl_si91x_efuse_read_t *efuse_read, uint8_t *efuse_read_buf); + +/***************************************************************************/ /** + * @brief + * Enable wireless radio. + * @pre Pre-conditions: + * - + * @ref sl_si91x_driver_init should be called before this API. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_status_t sl_si91x_enable_radio(void); + +/***************************************************************************/ /** + * @brief + * Disable wireless radio. + * @pre Pre-conditions: + * - + * @ref sl_si91x_driver_init should be called before this API. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_status_t sl_si91x_disable_radio(void); + +/***************************************************************************/ /** + * @brief + * Set specific Wi-Fi listen interval in low-power mode + * @param[in] listen_interval + * Wi-Fi Listen interval. + * @return none + *******************************************************************************/ +void sl_si91x_set_listen_interval(uint32_t listen_interval); /** @} */ @@ -500,28 +513,6 @@ sl_status_t sl_si91x_register_event_handler(sl_net_event_handler_t function); ******************************************************************************/ sl_status_t sl_si91x_default_handler(sl_net_event_t event, sl_wifi_buffer_t *buffer); -/***************************************************************************/ /** - * @brief - * Enable wireless radio. - * @pre Pre-conditions: - * - - * @ref sl_si91x_driver_init should be called before this API. - * @return - * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. - ******************************************************************************/ -sl_status_t sl_si91x_enable_radio(void); - -/***************************************************************************/ /** - * @brief - * Disable wireless radio. - * @pre Pre-conditions: - * - - * @ref sl_si91x_driver_init should be called before this API. - * @return - * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. - ******************************************************************************/ -sl_status_t sl_si91x_disable_radio(void); - /***************************************************************************/ /** * @brief * Set device power configuration. @@ -537,8 +528,6 @@ sl_status_t sl_si91x_disable_radio(void); ******************************************************************************/ sl_status_t sl_si91x_set_power_mode(sl_si91x_power_mode_t mode, const sl_si91x_power_configuration_t *config); -/** @} */ - /** \addtogroup SI91X_FIRMWARE_UPDATE_FROM_HOST_FUNCTIONS Firmware Update From Host * \ingroup SI91X_FIRMWARE_UPDATE_FUNCTIONS * @{ */ @@ -567,9 +556,14 @@ sl_status_t sl_si91x_fwup_load(uint8_t *content, uint16_t length); /***************************************************************************/ /** * @brief - * This API is used to abort the firmware update process on the SI91x device. This is a blocking API. + * This API is used to abort the firmware update process on the SiWx91x device. This is a blocking API. + * @pre Pre-conditions: + * - + * @ref sl_si91x_fwup_load should be called before this API. * @return * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + * @note Only after successful completion of firmware download using sl_si91x_fwup_load API, the user can call the sl_si91x_fwup_abort API. + * @note Ensure to call this abort API before performing a Soft / Hard reset of the SiWx91x device. if not called before soft/hard reset firmware update process won't be aborted. ******************************************************************************/ sl_status_t sl_si91x_fwup_abort(); /** @} */ @@ -593,9 +587,9 @@ sl_status_t sl_si91x_fwup_abort(); */ sl_status_t sl_si91x_m4_ta_secure_handshake(uint8_t sub_cmd_type, uint8_t input_len, - uint8_t *input_data, + const uint8_t *input_data, uint8_t output_len, - uint8_t *output_data); + const uint8_t *output_data); #endif /***************************************************************************/ /** @@ -657,7 +651,7 @@ sl_status_t sl_si91x_configure_timeout(sl_si91x_timeout_type_t timeout_type, uin * @note * This API should ONLY be called before [sl_wifi_init](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) and repeated call to this API will overwrite timeout values stored in SDK, will be applied on next call to [sl_wifi_init](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init). *******************************************************************************/ -void sl_si91x_set_timeout(sl_si91x_timeout_t *timeout_config); +void sl_si91x_set_timeout(const sl_si91x_timeout_t *timeout_config); /** @} */ @@ -720,7 +714,7 @@ sl_status_t sl_si91x_ota_firmware_upgradation(sl_ip_address_t server_ip, * @return sl_status_t. Refer to https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. ******************************************************************************/ sl_status_t sl_si91x_command_to_write_common_flash(uint32_t write_address, - uint8_t *write_data, + const uint8_t *write_data, uint16_t write_data_length, uint8_t flash_sector_erase_enable); @@ -748,15 +742,6 @@ sl_status_t sl_si91x_command_to_read_common_flash(uint32_t read_address, size_t ******************************************************************************/ sl_si91x_operation_mode_t get_opermode(void); -/***************************************************************************/ /** - * @brief - * Si91X specific set listen interval - * @param[in] listen_interval - * Wi-Fi Listen interval. - * @return none - *******************************************************************************/ -void sl_si91x_set_listen_interval(uint32_t listen_interval); - /***************************************************************************/ /** * @brief * Si91X specific get listen interval @@ -798,7 +783,7 @@ sl_status_t sl_si91x_get_ram_log(uint32_t address, uint32_t length); * @return sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. *******************************************************************************/ sl_status_t sl_si91x_driver_send_transceiver_data(sl_wifi_transceiver_tx_data_control_t *control, - uint8_t *payload, + const uint8_t *payload, uint16_t payload_len, uint32_t wait_time); @@ -866,3 +851,90 @@ sl_status_t sl_si91x_bl_upgrade_firmware(uint8_t *firmware_image, uint32_t fw_im sl_status_t sl_si91x_set_fast_fw_up(void); /** @} */ + +/** \addtogroup SL_SI91X_TYPES + * @{ */ +/// Firmware version information +typedef struct { + uint8_t chip_id; ///< Chip ID + uint8_t rom_id; ///< ROM ID + uint8_t major; ///< Major version number + uint8_t minor; ///< Minor version number + uint8_t security_version; ///< Security enabled or disabled + uint8_t patch_num; ///< Patch number + uint8_t customer_id; ///< Customer ID + uint16_t build_num; ///< Build number +} sl_si91x_firmware_version_t; + +/// NWP configuration structure +typedef struct { + /* configuration code. The possible values are: + * SL_SI91X_XO_CTUNE_FROM_HOST + * SL_SI91X_ENABLE_NWP_WDT_FROM_HOST + * SL_SI91X_DISABLE_NWP_WDT_FROM_HOST + */ + uint32_t code; + union { + uint8_t config_val; ///< config value as per the code selected above. + // Below structure is used in case of SL_SI91X_ENABLE_NWP_WDT_FROM_HOST + struct { + uint8_t wdt_timer_val; ///< timer values in seconds + uint8_t wdt_enable_in_ps; ///< enable WDT in power save + }; + } values; +} sl_si91x_nwp_configuration_t; + +/** @} */ + +/** \addtogroup SI91X_DRIVER_FUNCTIONS Core + * \ingroup SL_SI91X_API + * @{ */ + +/***************************************************************************/ /** + * @brief + * Get/retrieve the firmware version currently available on the SiWx91x device. This is a blocking API. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @param[out] version + * @ref sl_si91x_firmware_version_t object that contains the version string. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_status_t sl_si91x_get_firmware_version(sl_si91x_firmware_version_t *version); + +/***************************************************************************/ /** + * @brief + * Return the firmware image size from firmware image file, this is a non-blocking API. + * @param[in] buffer + * Buffer pointing to firmware image file. + * @param[out] fw_image_size + * Size of the firmware image passed in the input buffer param. The value returned in this param is valid only if this API returns SL_STATUS_OK(0). + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_status_t sl_si91x_get_firmware_size(void *buffer, uint32_t *fw_image_size); + +/***************************************************************************/ /** + * @brief + * Set configuration to NWP. The configuration value can be set based on the code element of sl_si91x_nwp_configuration_t structure. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @param[in] nwp_config + * Configuration as identified by @ref sl_si91x_nwp_configuration_t. + * Possible values for config.code are defined below: + * - For SL_SI91X_XO_CTUNE_FROM_HOST: + * - nwp_config.values.config_val is used to configure NWP's XO Ctune value. + * - For SL_SI91X_ENABLE_NWP_WDT_FROM_HOST: + * - nwp_config.values.wdt_timer_val is used to configure the NWP WDT ISR timer. Currently, the value for this timer is set to 32 seconds. + * - nwp_config.values.wdt_enable_in_ps is used to enable WDT in powersave. + * - For SL_SI91X_DISABLE_NWP_WDT_FROM_HOST: + * - Disables NWP WDT ISR timer. nwp_config.values.config_val is not utilized by the NWP. + * - All other values are NOT SUPPORTED. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_status_t sl_si91x_set_nwp_config_request(sl_si91x_nwp_configuration_t nwp_config); + +/** @} */ diff --git a/components/device/silabs/si91x/wireless/inc/sl_si91x_host_interface.h b/components/device/silabs/si91x/wireless/inc/sl_si91x_host_interface.h index d0fa4d0e2..27a851c05 100644 --- a/components/device/silabs/si91x/wireless/inc/sl_si91x_host_interface.h +++ b/components/device/silabs/si91x/wireless/inc/sl_si91x_host_interface.h @@ -43,6 +43,7 @@ typedef void (*sl_si91x_host_rx_done_handler)(void); typedef struct { sl_si91x_host_rx_irq_handler rx_irq; sl_si91x_host_rx_done_handler rx_done; + uint8_t boot_option; } sl_si91x_host_init_configuration; /** @@ -150,4 +151,4 @@ void sl_si91x_host_uart_enable_hardware_flow_control(void); /*Function to enable * @return true * @return false */ -bool sl_si91x_host_is_in_irq_context(void); \ No newline at end of file +bool sl_si91x_host_is_in_irq_context(void); diff --git a/components/device/silabs/si91x/wireless/inc/sl_si91x_protocol_types.h b/components/device/silabs/si91x/wireless/inc/sl_si91x_protocol_types.h index 55dd2ca56..3d9bab334 100644 --- a/components/device/silabs/si91x/wireless/inc/sl_si91x_protocol_types.h +++ b/components/device/silabs/si91x/wireless/inc/sl_si91x_protocol_types.h @@ -233,7 +233,7 @@ typedef struct { // Enable or disable set region from user: 1-take from user configuration,0-Take from Beacons uint8_t set_region_code_from_user_cmd; - // region code(1-US,2-EU,3-JP,4-World Domain,5-KR)*/ + // region code(1-US,2-EU,3-JP,4-World Domain,5-KR) uint8_t region_code; // module type (0- Without on board antenna, 1- With on board antenna) @@ -258,7 +258,7 @@ typedef struct { } sl_si91x_set_region_ap_request_t; // Scan command request structure -// channel: RF channel to scan, 0=All, 1-14 for 2.5GHz channels 1-14 +// channel: RF channel to scan, 0=All, 1-14 for 2.4GHz channels 1-14 typedef struct { uint8_t channel[4]; uint8_t ssid[RSI_SSID_LEN]; @@ -515,22 +515,15 @@ typedef struct { uint8_t content[SL_MAX_FWUP_CHUNK_SIZE]; } sl_si91x_req_fwup_t; -// RTC time from host -typedef struct { - // seconds [0-59] - uint32_t tm_sec; - // minutes [0-59] - uint32_t tm_min; - // hours since midnight [0-23] - uint32_t tm_hour; - // day of the month [1-31] - uint32_t tm_mday; - // months since January [0-11] - uint32_t tm_mon; - // year since 1990 - uint32_t tm_year; - // Weekday from Sunday to Saturday [1-7] - uint32_t tm_wday; +/// Si91x specific module RTC time +typedef struct { + uint32_t tm_sec; ///< Seconds [0-59] + uint32_t tm_min; ///< Minutes [0-59] + uint32_t tm_hour; ///< Hours since midnight [0-23] + uint32_t tm_mday; ///< Day of the month [1-31] + uint32_t tm_mon; ///< Months since January [0-11] + uint32_t tm_year; ///< Years since 1990 + uint32_t tm_wday; ///< Weekday from Sunday to Saturday [1-7] } sl_si91x_module_rtc_time_t; // wireless information @@ -551,8 +544,8 @@ typedef struct { // security type uint8_t sec_type; - // PSK - uint8_t psk[64]; + // PSK for AP mode, PMK for Client mode + uint8_t psk_pmk[64]; // uint8[4], Module IP Address uint8_t ipv4_address[4]; @@ -1135,6 +1128,27 @@ typedef struct { uint8_t ipv6_address[16]; } ip_address[SI91X_DNS_RESPONSE_MAX_ENTRIES]; } sl_si91x_dns_response_t; + +/** + * @brief DNS Server add request structure. + * + * This structure holds the information needed to add DNS servers, supporting both IPv4 and IPv6 addresses. + */ +typedef struct { + uint8_t ip_version[2]; ///< IP version value. The second byte is reserved for future use. + uint8_t dns_mode[2]; ///< DNS mode to use. The second byte is reserved for future use. + + union { + uint8_t primary_dns_ipv4[4]; ///< Primary DNS address in IPv4 format. + uint8_t primary_dns_ipv6[16]; ///< Primary DNS address in IPv6 format. + } sli_ip_address1; ///< Primary DNS address. + + union { + uint8_t secondary_dns_ipv4[4]; ///< Secondary DNS address in IPv4 format. + uint8_t secondary_dns_ipv6[16]; ///< Secondary DNS address in IPv6 format. + } sli_ip_address2; ///< Secondary DNS address. +} sli_dns_server_add_request_t; + // Structure for TCP ACK indication typedef struct { // Socket ID @@ -1166,31 +1180,6 @@ typedef struct { uint8_t read_timeout[2]; } sl_si91x_req_socket_read_t; -typedef struct { - // 2 bytes, the ip version of the ip address , 4 or 6 - uint16_t ip_version; - - // 2 bytes, the socket number associated with this read event - uint16_t socket_id; - - // 4 bytes, length of data received - uint32_t length; - - // 2 bytes, offset of data from start of buffer - uint16_t offset; - - // 2 bytes, port number of the device sending the data to us - uint16_t dest_port; - - union { - // 4 bytes, IPv4 Address of the device sending the data to us - uint8_t ipv4_address[4]; - - // 4 bytes, IPv6 Address of the device sending the data to us - uint8_t ipv6_address[16]; - } dest_ip_addr; -} si91x_rsp_socket_recv_t; - typedef struct { uint32_t tv_sec; /* Seconds */ uint32_t tv_usec; /* Microseconds */ @@ -1698,10 +1687,11 @@ typedef struct { } sl_si91x_efuse_read_t; typedef struct { - uint32_t max_retry_attempts; ///< Maximum number of retries before indicating join failure - uint32_t scan_interval; ///< Scan interval between each retry - uint32_t beacon_missed_count; ///< Number of missed beacons that will trigger rejoin - uint32_t first_time_retry_enable; ///< Retry enable or disable for first time joining + uint32_t max_retry_attempts; ///< Maximum number of retries before indicating join failure. + uint32_t scan_interval; ///< Scan interval between each retry. + uint32_t + beacon_missed_count; ///< Number of missed beacons that will trigger rejoin. Minimum value of beacon_missed_count is 40. + uint32_t first_time_retry_enable; ///< Retry enable or disable for first time joining. } sl_si91x_rejoin_params_t; /** \addtogroup SL_SI91X_TYPES diff --git a/components/device/silabs/si91x/wireless/inc/sl_si91x_types.h b/components/device/silabs/si91x/wireless/inc/sl_si91x_types.h index 979b902f2..225564c15 100644 --- a/components/device/silabs/si91x/wireless/inc/sl_si91x_types.h +++ b/components/device/silabs/si91x/wireless/inc/sl_si91x_types.h @@ -33,13 +33,13 @@ #include "sl_wifi_host_interface.h" #include -/// Flag to indicate that the response status of the command is expected +/// Flag to indicate that the response status of the command is expected. #define SI91X_PACKET_RESPONSE_STATUS (1 << 0) -/// Flag to indicate that the response packet of the command is expected +/// Flag to indicate that the response packet of the command is expected. #define SI91X_PACKET_RESPONSE_PACKET (1 << 1) -/// Flag to indicate that all the packet tx has to be suspended until the corresponding command response is received +/// Flag to indicate that all the packet tx has to be suspended until the corresponding command response is received. #define SI91X_PACKET_GLOBAL_QUEUE_BLOCK (1 << 3) /// Flag to indicate that host would receive the response from firmware in asynchronous manner. @@ -60,7 +60,7 @@ typedef enum { // SI91X command queue types // Note: The values of the command queue type should be // in sync with that of sl_si91x_command_type_t - SI91X_COMMON_CMD_QUEUE = 0, ///< SI91X common Command queue + SI91X_COMMON_CMD_QUEUE = 0, ///< SI91X Common Command queue SI91X_WLAN_CMD_QUEUE = 1, ///< SI91X Wireless LAN Command queue SI91X_NETWORK_CMD_QUEUE = 2, ///< SI91X Network Command queue SI91X_SOCKET_CMD_QUEUE = 3, ///< SI91X Socket Command queue @@ -68,7 +68,7 @@ typedef enum { SI91X_SOCKET_DATA_QUEUE = 5, ///< SI91X Socket Command queue // SI91X response queue types - SI91X_COMMON_RESPONSE_QUEUE = 6, ///< SI91X common Command response queue + SI91X_COMMON_RESPONSE_QUEUE = 6, ///< SI91X Common Command response queue SI91X_WLAN_RESPONSE_QUEUE = 7, ///< SI91X Wireless LAN Command response queue SI91X_NETWORK_RESPONSE_QUEUE = 8, ///< SI91X Network Command response queue SI91X_SOCKET_RESPONSE_QUEUE = 9, ///< SI91X Socket Command response queue @@ -91,12 +91,12 @@ typedef enum { * @{ * */ /// Si91x command types -/// Si91x band mode. +/// Si91x band mode /// @note Only 2.4 GHz currently supported. typedef enum { - SL_SI91X_WIFI_BAND_2_4GHZ = 0, ///< 2.4GHz WiFi band - SL_SI91X_WIFI_BAND_5GHZ = 1, ///< 5GHz WiFi band (not currently supported) - SL_SI91X_WIFI_DUAL_BAND = 2 ///< both 2.4GHz and 5GHZ WiFi band (not currently supported) + SL_SI91X_WIFI_BAND_2_4GHZ = 0, ///< 2.4 GHz WiFi band + SL_SI91X_WIFI_BAND_5GHZ = 1, ///< 5 GHz WiFi band (not currently supported) + SL_SI91X_WIFI_DUAL_BAND = 2 ///< Both 2.4 GHz and 5 GHZ WiFi band (not currently supported) } sl_si91x_band_mode_t; /// Si91x region code. @@ -106,18 +106,19 @@ typedef enum { US, ///< United States EU, ///< European Union JP, ///< Japan - WORLD_DOMAIN, ///< World wide domain + WORLD_DOMAIN, ///< Worldwide domain KR, ///< Korea - SG ///< Singapore (not currently supported) + SG, ///< Singapore (not currently supported) + IGNORE_REGION ///< Do not update region code during initialization } sl_si91x_region_code_t; /// Si91x Timeout types typedef enum { SL_SI91X_AUTHENTICATION_ASSOCIATION_TIMEOUT = 0, ///< Used for setting association and authentication timeout request in millisecs - SL_SI91X_CHANNEL_ACTIVE_SCAN_TIMEOUT, ///< Used for setting dwell time per channel in milli seconds during active scan + SL_SI91X_CHANNEL_ACTIVE_SCAN_TIMEOUT, ///< Used for setting dwell time per channel in milliseconds during active scan SL_SI91X_KEEP_ALIVE_TIMEOUT, ///< Used for setting WLAN keep alive time in seconds - SL_SI91X_CHANNEL_PASSIVE_SCAN_TIMEOUT ///< Used for setting dwell time per channel in milli seconds during passive scan + SL_SI91X_CHANNEL_PASSIVE_SCAN_TIMEOUT ///< Used for setting dwell time per channel in milliseconds during passive scan } sl_si91x_timeout_type_t; /// Si91x Wi-Fi VAP ID @@ -130,17 +131,17 @@ typedef enum { // Note: refer sl_wifi_device.h for complete bit map details /// Si91x boot configuration structure typedef struct { - uint16_t oper_mode; ///< operation mode, one of the values from @ref sl_si91x_operation_mode_t. - uint16_t coex_mode; ///< coex mode, one of the values from @ref sl_si91x_coex_mode_t. - uint32_t feature_bit_map; ///< Feature bit map, @ref SI91X_FEATURE_BITMAP - uint32_t tcp_ip_feature_bit_map; ///< TCP/IP feature bit map, @ref SI91X_TCP_IP_FEATURE_BITMAP - uint32_t custom_feature_bit_map; ///< Custom feature bit map, @ref SI91X_CUSTOM_FEATURE_BITMAP - uint32_t ext_custom_feature_bit_map; ///< Extended custom feature bit map, @ref SI91X_EXTENDED_CUSTOM_FEATURE_BITMAP - uint32_t bt_feature_bit_map; ///< BT featured bit map, @ref SI91X_BT_FEATURE_BITMAP - uint32_t ext_tcp_ip_feature_bit_map; ///< Extended tcp/ip feature bit map, @ref SI91X_EXTENDED_TCP_IP_FEATURE_BITMAP + uint16_t oper_mode; ///< operation mode, one of the values from @ref sl_si91x_operation_mode_t + uint16_t coex_mode; ///< coex mode, one of the values from @ref sl_si91x_coex_mode_t + uint32_t feature_bit_map; ///< Feature bitmap, @ref SI91X_FEATURE_BITMAP + uint32_t tcp_ip_feature_bit_map; ///< TCP/IP feature bitmap, @ref SI91X_TCP_IP_FEATURE_BITMAP + uint32_t custom_feature_bit_map; ///< Custom feature bitmap, @ref SI91X_CUSTOM_FEATURE_BITMAP + uint32_t ext_custom_feature_bit_map; ///< Extended custom feature bitmap, @ref SI91X_EXTENDED_CUSTOM_FEATURE_BITMAP + uint32_t bt_feature_bit_map; ///< BT featured bitmap, @ref SI91X_BT_FEATURE_BITMAP + uint32_t ext_tcp_ip_feature_bit_map; ///< Extended tcp/ip feature bitmap, @ref SI91X_EXTENDED_TCP_IP_FEATURE_BITMAP uint32_t ble_feature_bit_map; ///< BLE feature bitmap, @ref SI91X_BLE_FEATURE_BITMAP - uint32_t ble_ext_feature_bit_map; ///< BLE extended feature bit map, @ref SI91X_EXTENDED_BLE_CUSTOM_FEATURE_BITMAP - uint32_t config_feature_bit_map; ///< Config feature bit map, @ref SI91X_CONFIG_FEATURE_BITMAP + uint32_t ble_ext_feature_bit_map; ///< BLE extended feature bitmap, @ref SI91X_EXTENDED_BLE_CUSTOM_FEATURE_BITMAP + uint32_t config_feature_bit_map; ///< Config feature bitmap, @ref SI91X_CONFIG_FEATURE_BITMAP } sl_si91x_boot_configuration_t; /// Timeout Configuration Structure @@ -150,7 +151,7 @@ typedef struct { uint16_t auth_assoc_timeout_value; ///< Authentication and association timeout value. Default value of 300 millisecs is used when SL_WIFI_DEFAULT_AUTH_ASSOCIATION_TIMEOUT is passed. uint16_t - keep_alive_timeout_value; ///< Keep Alive Timeout value. Default value of 30 secs is used when SL_WIFI_DEFAULT_KEEP_ALIVE_TIMEOUT is passed + keep_alive_timeout_value; ///< Keep Alive Timeout value. Default value of 30 secs is used when SL_WIFI_DEFAULT_KEEP_ALIVE_TIMEOUT is passed. uint16_t passive_scan_timeout_value; ///