diff --git a/hw/amdc_revf.bd b/hw/amdc_revf.bd index 793f925a..7f78e398 100644 --- a/hw/amdc_revf.bd +++ b/hw/amdc_revf.bd @@ -2973,17 +2973,17 @@ "s00_data_fifo/M_AXI" ] }, - "auto_pc_to_s00_data_fifo": { - "interface_ports": [ - "s00_data_fifo/S_AXI", - "auto_pc/M_AXI" - ] - }, "s00_couplers_to_auto_pc": { "interface_ports": [ "S_AXI", "auto_pc/S_AXI" ] + }, + "auto_pc_to_s00_data_fifo": { + "interface_ports": [ + "s00_data_fifo/S_AXI", + "auto_pc/M_AXI" + ] } }, "nets": { @@ -5067,532 +5067,532 @@ } }, "interface_nets": { - "m28_couplers_to_ps7_0_axi_periph": { + "xbar_to_i00_couplers": { "interface_ports": [ - "M28_AXI", - "m28_couplers/M_AXI" + "xbar/M00_AXI", + "i00_couplers/S_AXI" ] }, - "m10_couplers_to_ps7_0_axi_periph": { + "i00_couplers_to_tier2_xbar_0": { "interface_ports": [ - "M10_AXI", - "m10_couplers/M_AXI" + "i00_couplers/M_AXI", + "tier2_xbar_0/S00_AXI" ] }, - "tier2_xbar_1_to_m09_couplers": { + "xbar_to_i01_couplers": { "interface_ports": [ - "tier2_xbar_1/M01_AXI", - "m09_couplers/S_AXI" + "xbar/M01_AXI", + "i01_couplers/S_AXI" ] }, - "tier2_xbar_1_to_m10_couplers": { + "i01_couplers_to_tier2_xbar_1": { "interface_ports": [ - "tier2_xbar_1/M02_AXI", - "m10_couplers/S_AXI" + "i01_couplers/M_AXI", + "tier2_xbar_1/S00_AXI" ] }, - "m11_couplers_to_ps7_0_axi_periph": { + "xbar_to_i02_couplers": { "interface_ports": [ - "M11_AXI", - "m11_couplers/M_AXI" + "xbar/M02_AXI", + "i02_couplers/S_AXI" ] }, - "tier2_xbar_1_to_m11_couplers": { + "xbar_to_i03_couplers": { "interface_ports": [ - "tier2_xbar_1/M03_AXI", - "m11_couplers/S_AXI" + "xbar/M03_AXI", + "i03_couplers/S_AXI" ] }, - "m12_couplers_to_ps7_0_axi_periph": { + "i02_couplers_to_tier2_xbar_2": { "interface_ports": [ - "M12_AXI", - "m12_couplers/M_AXI" + "i02_couplers/M_AXI", + "tier2_xbar_2/S00_AXI" ] }, - "tier2_xbar_1_to_m12_couplers": { + "i03_couplers_to_tier2_xbar_3": { "interface_ports": [ - "tier2_xbar_1/M04_AXI", - "m12_couplers/S_AXI" + "i03_couplers/M_AXI", + "tier2_xbar_3/S00_AXI" ] }, - "m13_couplers_to_ps7_0_axi_periph": { + "xbar_to_i04_couplers": { "interface_ports": [ - "M13_AXI", - "m13_couplers/M_AXI" + "xbar/M04_AXI", + "i04_couplers/S_AXI" ] }, - "tier2_xbar_1_to_m13_couplers": { + "i04_couplers_to_tier2_xbar_4": { "interface_ports": [ - "tier2_xbar_1/M05_AXI", - "m13_couplers/S_AXI" + "i04_couplers/M_AXI", + "tier2_xbar_4/S00_AXI" ] }, - "m14_couplers_to_ps7_0_axi_periph": { + "ps7_0_axi_periph_to_s00_couplers": { "interface_ports": [ - "M14_AXI", - "m14_couplers/M_AXI" + "S00_AXI", + "s00_couplers/S_AXI" ] }, - "m15_couplers_to_ps7_0_axi_periph": { + "m00_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "M15_AXI", - "m15_couplers/M_AXI" + "M00_AXI", + "m00_couplers/M_AXI" ] }, - "tier2_xbar_1_to_m14_couplers": { + "s00_couplers_to_xbar": { "interface_ports": [ - "tier2_xbar_1/M06_AXI", - "m14_couplers/S_AXI" + "s00_couplers/M_AXI", + "xbar/S00_AXI" ] }, - "m16_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_0_to_m00_couplers": { "interface_ports": [ - "M16_AXI", - "m16_couplers/M_AXI" + "tier2_xbar_0/M00_AXI", + "m00_couplers/S_AXI" ] }, - "tier2_xbar_1_to_m15_couplers": { + "m01_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_1/M07_AXI", - "m15_couplers/S_AXI" + "M01_AXI", + "m01_couplers/M_AXI" ] }, - "tier2_xbar_2_to_m16_couplers": { + "tier2_xbar_0_to_m01_couplers": { "interface_ports": [ - "tier2_xbar_2/M00_AXI", - "m16_couplers/S_AXI" + "tier2_xbar_0/M01_AXI", + "m01_couplers/S_AXI" ] }, - "m17_couplers_to_ps7_0_axi_periph": { + "m02_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "M17_AXI", - "m17_couplers/M_AXI" + "M02_AXI", + "m02_couplers/M_AXI" ] }, - "tier2_xbar_2_to_m17_couplers": { + "tier2_xbar_0_to_m02_couplers": { "interface_ports": [ - "tier2_xbar_2/M01_AXI", - "m17_couplers/S_AXI" + "tier2_xbar_0/M02_AXI", + "m02_couplers/S_AXI" ] }, - "m18_couplers_to_ps7_0_axi_periph": { + "m03_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "M18_AXI", - "m18_couplers/M_AXI" + "M03_AXI", + "m03_couplers/M_AXI" ] }, - "tier2_xbar_2_to_m18_couplers": { + "tier2_xbar_0_to_m03_couplers": { "interface_ports": [ - "tier2_xbar_2/M02_AXI", - "m18_couplers/S_AXI" + "tier2_xbar_0/M03_AXI", + "m03_couplers/S_AXI" ] }, - "m19_couplers_to_ps7_0_axi_periph": { + "m04_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "M19_AXI", - "m19_couplers/M_AXI" + "M04_AXI", + "m04_couplers/M_AXI" ] }, - "tier2_xbar_2_to_m19_couplers": { + "tier2_xbar_0_to_m04_couplers": { "interface_ports": [ - "tier2_xbar_2/M03_AXI", - "m19_couplers/S_AXI" + "tier2_xbar_0/M04_AXI", + "m04_couplers/S_AXI" ] }, - "m20_couplers_to_ps7_0_axi_periph": { + "m05_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "M20_AXI", - "m20_couplers/M_AXI" + "M05_AXI", + "m05_couplers/M_AXI" ] }, - "tier2_xbar_2_to_m20_couplers": { + "m06_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_2/M04_AXI", - "m20_couplers/S_AXI" + "M06_AXI", + "m06_couplers/M_AXI" ] }, - "m21_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_0_to_m05_couplers": { "interface_ports": [ - "M21_AXI", - "m21_couplers/M_AXI" + "tier2_xbar_0/M05_AXI", + "m05_couplers/S_AXI" ] }, - "tier2_xbar_2_to_m21_couplers": { + "tier2_xbar_3_to_m27_couplers": { "interface_ports": [ - "tier2_xbar_2/M05_AXI", - "m21_couplers/S_AXI" + "tier2_xbar_3/M03_AXI", + "m27_couplers/S_AXI" ] }, - "m22_couplers_to_ps7_0_axi_periph": { + "m28_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "M22_AXI", - "m22_couplers/M_AXI" + "M28_AXI", + "m28_couplers/M_AXI" ] }, - "m23_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_3_to_m28_couplers": { "interface_ports": [ - "M23_AXI", - "m23_couplers/M_AXI" + "tier2_xbar_3/M04_AXI", + "m28_couplers/S_AXI" ] }, - "tier2_xbar_2_to_m22_couplers": { + "m29_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_2/M06_AXI", - "m22_couplers/S_AXI" + "M29_AXI", + "m29_couplers/M_AXI" ] }, - "tier2_xbar_2_to_m23_couplers": { + "m30_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_2/M07_AXI", - "m23_couplers/S_AXI" + "M30_AXI", + "m30_couplers/M_AXI" ] }, - "m24_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_3_to_m29_couplers": { "interface_ports": [ - "M24_AXI", - "m24_couplers/M_AXI" + "tier2_xbar_3/M05_AXI", + "m29_couplers/S_AXI" ] }, - "tier2_xbar_3_to_m24_couplers": { + "tier2_xbar_3_to_m30_couplers": { "interface_ports": [ - "tier2_xbar_3/M00_AXI", - "m24_couplers/S_AXI" + "tier2_xbar_3/M06_AXI", + "m30_couplers/S_AXI" ] }, - "m25_couplers_to_ps7_0_axi_periph": { + "m31_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "M25_AXI", - "m25_couplers/M_AXI" + "M31_AXI", + "m31_couplers/M_AXI" ] }, - "tier2_xbar_3_to_m25_couplers": { + "m32_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_3/M01_AXI", - "m25_couplers/S_AXI" + "M32_AXI", + "m32_couplers/M_AXI" ] }, - "m26_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_3_to_m31_couplers": { "interface_ports": [ - "M26_AXI", - "m26_couplers/M_AXI" + "tier2_xbar_3/M07_AXI", + "m31_couplers/S_AXI" ] }, - "m27_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_4_to_m32_couplers": { "interface_ports": [ - "M27_AXI", - "m27_couplers/M_AXI" + "tier2_xbar_4/M00_AXI", + "m32_couplers/S_AXI" ] }, - "tier2_xbar_3_to_m26_couplers": { + "m33_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_3/M02_AXI", - "m26_couplers/S_AXI" + "M33_AXI", + "m33_couplers/M_AXI" ] }, - "tier2_xbar_3_to_m27_couplers": { + "m34_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_3/M03_AXI", - "m27_couplers/S_AXI" + "M34_AXI", + "m34_couplers/M_AXI" ] }, - "tier2_xbar_1_to_m08_couplers": { + "tier2_xbar_4_to_m33_couplers": { "interface_ports": [ - "tier2_xbar_1/M00_AXI", - "m08_couplers/S_AXI" + "tier2_xbar_4/M01_AXI", + "m33_couplers/S_AXI" ] }, - "m09_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_4_to_m34_couplers": { "interface_ports": [ - "M09_AXI", - "m09_couplers/M_AXI" + "tier2_xbar_4/M02_AXI", + "m34_couplers/S_AXI" ] }, - "m07_couplers_to_ps7_0_axi_periph": { + "m35_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "M07_AXI", - "m07_couplers/M_AXI" + "M35_AXI", + "m35_couplers/M_AXI" ] }, - "m08_couplers_to_ps7_0_axi_periph": { + "m36_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "M08_AXI", - "m08_couplers/M_AXI" + "M36_AXI", + "m36_couplers/M_AXI" ] }, - "tier2_xbar_0_to_m07_couplers": { + "tier2_xbar_4_to_m35_couplers": { "interface_ports": [ - "tier2_xbar_0/M07_AXI", - "m07_couplers/S_AXI" + "tier2_xbar_4/M03_AXI", + "m35_couplers/S_AXI" ] }, - "s00_couplers_to_xbar": { + "m37_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "s00_couplers/M_AXI", - "xbar/S00_AXI" + "M37_AXI", + "m37_couplers/M_AXI" ] }, - "ps7_0_axi_periph_to_s00_couplers": { + "tier2_xbar_4_to_m36_couplers": { "interface_ports": [ - "S00_AXI", - "s00_couplers/S_AXI" + "tier2_xbar_4/M04_AXI", + "m36_couplers/S_AXI" ] }, - "m00_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_4_to_m37_couplers": { "interface_ports": [ - "M00_AXI", - "m00_couplers/M_AXI" + "tier2_xbar_4/M05_AXI", + "m37_couplers/S_AXI" ] }, - "tier2_xbar_0_to_m00_couplers": { + "tier2_xbar_0_to_m06_couplers": { "interface_ports": [ - "tier2_xbar_0/M00_AXI", - "m00_couplers/S_AXI" + "tier2_xbar_0/M06_AXI", + "m06_couplers/S_AXI" ] }, - "m01_couplers_to_ps7_0_axi_periph": { + "m07_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "M01_AXI", - "m01_couplers/M_AXI" + "M07_AXI", + "m07_couplers/M_AXI" ] }, - "tier2_xbar_0_to_m01_couplers": { + "tier2_xbar_0_to_m07_couplers": { "interface_ports": [ - "tier2_xbar_0/M01_AXI", - "m01_couplers/S_AXI" + "tier2_xbar_0/M07_AXI", + "m07_couplers/S_AXI" ] }, - "m02_couplers_to_ps7_0_axi_periph": { + "m08_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "M02_AXI", - "m02_couplers/M_AXI" + "M08_AXI", + "m08_couplers/M_AXI" ] }, - "tier2_xbar_0_to_m02_couplers": { + "m09_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_0/M02_AXI", - "m02_couplers/S_AXI" + "M09_AXI", + "m09_couplers/M_AXI" ] }, - "m03_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_1_to_m08_couplers": { "interface_ports": [ - "M03_AXI", - "m03_couplers/M_AXI" + "tier2_xbar_1/M00_AXI", + "m08_couplers/S_AXI" ] }, - "m04_couplers_to_ps7_0_axi_periph": { + "m10_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "M04_AXI", - "m04_couplers/M_AXI" + "M10_AXI", + "m10_couplers/M_AXI" ] }, - "tier2_xbar_0_to_m03_couplers": { + "tier2_xbar_1_to_m09_couplers": { "interface_ports": [ - "tier2_xbar_0/M03_AXI", - "m03_couplers/S_AXI" + "tier2_xbar_1/M01_AXI", + "m09_couplers/S_AXI" ] }, - "tier2_xbar_0_to_m04_couplers": { + "m11_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_0/M04_AXI", - "m04_couplers/S_AXI" + "M11_AXI", + "m11_couplers/M_AXI" ] }, - "m05_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_1_to_m10_couplers": { "interface_ports": [ - "M05_AXI", - "m05_couplers/M_AXI" + "tier2_xbar_1/M02_AXI", + "m10_couplers/S_AXI" ] }, - "tier2_xbar_0_to_m05_couplers": { + "m12_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_0/M05_AXI", - "m05_couplers/S_AXI" + "M12_AXI", + "m12_couplers/M_AXI" ] }, - "m06_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_1_to_m11_couplers": { "interface_ports": [ - "M06_AXI", - "m06_couplers/M_AXI" + "tier2_xbar_1/M03_AXI", + "m11_couplers/S_AXI" ] }, - "tier2_xbar_0_to_m06_couplers": { + "tier2_xbar_1_to_m12_couplers": { "interface_ports": [ - "tier2_xbar_0/M06_AXI", - "m06_couplers/S_AXI" + "tier2_xbar_1/M04_AXI", + "m12_couplers/S_AXI" ] }, - "xbar_to_i00_couplers": { + "m13_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "xbar/M00_AXI", - "i00_couplers/S_AXI" + "M13_AXI", + "m13_couplers/M_AXI" ] }, - "xbar_to_i01_couplers": { + "m14_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "xbar/M01_AXI", - "i01_couplers/S_AXI" + "M14_AXI", + "m14_couplers/M_AXI" ] }, - "i00_couplers_to_tier2_xbar_0": { + "tier2_xbar_1_to_m13_couplers": { "interface_ports": [ - "i00_couplers/M_AXI", - "tier2_xbar_0/S00_AXI" + "tier2_xbar_1/M05_AXI", + "m13_couplers/S_AXI" ] }, - "i01_couplers_to_tier2_xbar_1": { + "tier2_xbar_1_to_m14_couplers": { "interface_ports": [ - "i01_couplers/M_AXI", - "tier2_xbar_1/S00_AXI" + "tier2_xbar_1/M06_AXI", + "m14_couplers/S_AXI" ] }, - "xbar_to_i02_couplers": { + "m15_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "xbar/M02_AXI", - "i02_couplers/S_AXI" + "M15_AXI", + "m15_couplers/M_AXI" ] }, - "i02_couplers_to_tier2_xbar_2": { + "m16_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "i02_couplers/M_AXI", - "tier2_xbar_2/S00_AXI" + "M16_AXI", + "m16_couplers/M_AXI" ] }, - "xbar_to_i03_couplers": { + "tier2_xbar_1_to_m15_couplers": { "interface_ports": [ - "xbar/M03_AXI", - "i03_couplers/S_AXI" + "tier2_xbar_1/M07_AXI", + "m15_couplers/S_AXI" ] }, - "i03_couplers_to_tier2_xbar_3": { + "tier2_xbar_2_to_m16_couplers": { "interface_ports": [ - "i03_couplers/M_AXI", - "tier2_xbar_3/S00_AXI" + "tier2_xbar_2/M00_AXI", + "m16_couplers/S_AXI" ] }, - "xbar_to_i04_couplers": { + "m17_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "xbar/M04_AXI", - "i04_couplers/S_AXI" + "M17_AXI", + "m17_couplers/M_AXI" ] }, - "i04_couplers_to_tier2_xbar_4": { + "tier2_xbar_2_to_m17_couplers": { "interface_ports": [ - "i04_couplers/M_AXI", - "tier2_xbar_4/S00_AXI" + "tier2_xbar_2/M01_AXI", + "m17_couplers/S_AXI" ] }, - "tier2_xbar_3_to_m28_couplers": { + "m18_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_3/M04_AXI", - "m28_couplers/S_AXI" + "M18_AXI", + "m18_couplers/M_AXI" ] }, - "m29_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_2_to_m18_couplers": { "interface_ports": [ - "M29_AXI", - "m29_couplers/M_AXI" + "tier2_xbar_2/M02_AXI", + "m18_couplers/S_AXI" ] }, - "tier2_xbar_3_to_m29_couplers": { + "m19_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_3/M05_AXI", - "m29_couplers/S_AXI" + "M19_AXI", + "m19_couplers/M_AXI" ] }, - "m30_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_2_to_m19_couplers": { "interface_ports": [ - "M30_AXI", - "m30_couplers/M_AXI" + "tier2_xbar_2/M03_AXI", + "m19_couplers/S_AXI" ] }, - "tier2_xbar_3_to_m30_couplers": { + "m20_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_3/M06_AXI", - "m30_couplers/S_AXI" + "M20_AXI", + "m20_couplers/M_AXI" ] }, - "m31_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_2_to_m20_couplers": { "interface_ports": [ - "M31_AXI", - "m31_couplers/M_AXI" + "tier2_xbar_2/M04_AXI", + "m20_couplers/S_AXI" ] }, - "tier2_xbar_3_to_m31_couplers": { + "m21_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_3/M07_AXI", - "m31_couplers/S_AXI" + "M21_AXI", + "m21_couplers/M_AXI" ] }, - "m32_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_2_to_m21_couplers": { "interface_ports": [ - "M32_AXI", - "m32_couplers/M_AXI" + "tier2_xbar_2/M05_AXI", + "m21_couplers/S_AXI" ] }, - "tier2_xbar_4_to_m32_couplers": { + "m22_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_4/M00_AXI", - "m32_couplers/S_AXI" + "M22_AXI", + "m22_couplers/M_AXI" ] }, - "m33_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_2_to_m22_couplers": { "interface_ports": [ - "M33_AXI", - "m33_couplers/M_AXI" + "tier2_xbar_2/M06_AXI", + "m22_couplers/S_AXI" ] }, - "m34_couplers_to_ps7_0_axi_periph": { + "m23_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "M34_AXI", - "m34_couplers/M_AXI" + "M23_AXI", + "m23_couplers/M_AXI" ] }, - "tier2_xbar_4_to_m33_couplers": { + "m24_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_4/M01_AXI", - "m33_couplers/S_AXI" + "M24_AXI", + "m24_couplers/M_AXI" ] }, - "m35_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_2_to_m23_couplers": { "interface_ports": [ - "M35_AXI", - "m35_couplers/M_AXI" + "tier2_xbar_2/M07_AXI", + "m23_couplers/S_AXI" ] }, - "tier2_xbar_4_to_m34_couplers": { + "m25_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_4/M02_AXI", - "m34_couplers/S_AXI" + "M25_AXI", + "m25_couplers/M_AXI" ] }, - "m36_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_3_to_m24_couplers": { "interface_ports": [ - "M36_AXI", - "m36_couplers/M_AXI" + "tier2_xbar_3/M00_AXI", + "m24_couplers/S_AXI" ] }, - "tier2_xbar_4_to_m35_couplers": { + "m26_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_4/M03_AXI", - "m35_couplers/S_AXI" + "M26_AXI", + "m26_couplers/M_AXI" ] }, - "tier2_xbar_4_to_m36_couplers": { + "tier2_xbar_3_to_m25_couplers": { "interface_ports": [ - "tier2_xbar_4/M04_AXI", - "m36_couplers/S_AXI" + "tier2_xbar_3/M01_AXI", + "m25_couplers/S_AXI" ] }, - "m37_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_3_to_m26_couplers": { "interface_ports": [ - "M37_AXI", - "m37_couplers/M_AXI" + "tier2_xbar_3/M02_AXI", + "m26_couplers/S_AXI" ] }, - "tier2_xbar_4_to_m37_couplers": { + "m27_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_4/M05_AXI", - "m37_couplers/S_AXI" + "M27_AXI", + "m27_couplers/M_AXI" ] } }, @@ -6189,10 +6189,16 @@ } }, "interface_nets": { - "Conn14": { + "Conn8": { "interface_ports": [ - "M14_AXI", - "ps7_0_axi_periph/M14_AXI" + "M07_AXI", + "ps7_0_axi_periph/M07_AXI" + ] + }, + "Conn11": { + "interface_ports": [ + "M10_AXI", + "ps7_0_axi_periph/M10_AXI" ] }, "Conn25": { @@ -6201,10 +6207,10 @@ "ps7_0_axi_periph/M25_AXI" ] }, - "ps7_0_axi_periph_M13_AXI": { + "Conn14": { "interface_ports": [ - "M13_AXI", - "ps7_0_axi_periph/M13_AXI" + "M14_AXI", + "ps7_0_axi_periph/M14_AXI" ] }, "Conn20": { @@ -6213,6 +6219,12 @@ "ps7_0_axi_periph/M20_AXI" ] }, + "ps7_0_axi_periph_M13_AXI": { + "interface_ports": [ + "M13_AXI", + "ps7_0_axi_periph/M13_AXI" + ] + }, "Conn24": { "interface_ports": [ "M24_AXI", @@ -6231,18 +6243,18 @@ "ps7_0_axi_periph/M06_AXI" ] }, - "Conn5": { - "interface_ports": [ - "M04_AXI", - "ps7_0_axi_periph/M04_AXI" - ] - }, "ps7_0_axi_periph_M29_AXI": { "interface_ports": [ "M29_AXI", "ps7_0_axi_periph/M29_AXI" ] }, + "Conn5": { + "interface_ports": [ + "M04_AXI", + "ps7_0_axi_periph/M04_AXI" + ] + }, "Conn4": { "interface_ports": [ "M03_AXI", @@ -6261,18 +6273,18 @@ "ps7_0_axi_periph/M35_AXI" ] }, - "ps7_0_axi_periph_M34_AXI": { - "interface_ports": [ - "M34_AXI", - "ps7_0_axi_periph/M34_AXI" - ] - }, "Conn12": { "interface_ports": [ "M11_AXI", "ps7_0_axi_periph/M11_AXI" ] }, + "ps7_0_axi_periph_M34_AXI": { + "interface_ports": [ + "M34_AXI", + "ps7_0_axi_periph/M34_AXI" + ] + }, "Conn15": { "interface_ports": [ "M15_AXI", @@ -6291,28 +6303,22 @@ "ps7_0_axi_periph/M36_AXI" ] }, - "ps7_0_axi_periph_M37_AXI": { - "interface_ports": [ - "M37_AXI", - "ps7_0_axi_periph/M37_AXI" - ] - }, "Conn29": { "interface_ports": [ "M33_AXI", "ps7_0_axi_periph/M33_AXI" ] }, - "Conn6": { + "ps7_0_axi_periph_M37_AXI": { "interface_ports": [ - "M05_AXI", - "ps7_0_axi_periph/M05_AXI" + "M37_AXI", + "ps7_0_axi_periph/M37_AXI" ] }, - "Conn3": { + "Conn6": { "interface_ports": [ - "M02_AXI", - "ps7_0_axi_periph/M02_AXI" + "M05_AXI", + "ps7_0_axi_periph/M05_AXI" ] }, "Conn19": { @@ -6321,6 +6327,12 @@ "ps7_0_axi_periph/M19_AXI" ] }, + "Conn3": { + "interface_ports": [ + "M02_AXI", + "ps7_0_axi_periph/M02_AXI" + ] + }, "Conn2": { "interface_ports": [ "M01_AXI", @@ -6339,28 +6351,22 @@ "ps7_0_axi_periph/M08_AXI" ] }, - "Conn16": { - "interface_ports": [ - "M16_AXI", - "ps7_0_axi_periph/M16_AXI" - ] - }, "Conn13": { "interface_ports": [ "M12_AXI", "ps7_0_axi_periph/M12_AXI" ] }, - "Conn23": { + "Conn16": { "interface_ports": [ - "M23_AXI", - "ps7_0_axi_periph/M23_AXI" + "M16_AXI", + "ps7_0_axi_periph/M16_AXI" ] }, - "Conn22": { + "Conn23": { "interface_ports": [ - "M22_AXI", - "ps7_0_axi_periph/M22_AXI" + "M23_AXI", + "ps7_0_axi_periph/M23_AXI" ] }, "processing_system7_0_M_AXI_GP0": { @@ -6375,22 +6381,16 @@ "ps7_0_axi_periph/M17_AXI" ] }, - "processing_system7_0_DDR": { - "interface_ports": [ - "DDR", - "processing_system7_0/DDR" - ] - }, - "Conn11": { + "Conn22": { "interface_ports": [ - "M10_AXI", - "ps7_0_axi_periph/M10_AXI" + "M22_AXI", + "ps7_0_axi_periph/M22_AXI" ] }, - "Conn8": { + "processing_system7_0_DDR": { "interface_ports": [ - "M07_AXI", - "ps7_0_axi_periph/M07_AXI" + "DDR", + "processing_system7_0/DDR" ] }, "Conn1": { @@ -6417,18 +6417,18 @@ "ps7_0_axi_periph/M09_AXI" ] }, - "Conn21": { - "interface_ports": [ - "M21_AXI", - "ps7_0_axi_periph/M21_AXI" - ] - }, "ps7_0_axi_periph_M30_AXI": { "interface_ports": [ "M30_AXI", "ps7_0_axi_periph/M30_AXI" ] }, + "Conn21": { + "interface_ports": [ + "M21_AXI", + "ps7_0_axi_periph/M21_AXI" + ] + }, "processing_system7_0_FIXED_IO": { "interface_ports": [ "FIXED_IO", @@ -6676,18 +6676,18 @@ } }, "interface_nets": { - "Conn1": { - "interface_ports": [ - "S00_AXI2", - "amdc_inv_status_mux_0/S00_AXI" - ] - }, "ps7_0_axi_periph_M06_AXI": { "interface_ports": [ "S00_AXI1", "amdc_pwm_mux_0/S00_AXI" ] }, + "Conn1": { + "interface_ports": [ + "S00_AXI2", + "amdc_inv_status_mux_0/S00_AXI" + ] + }, "ps7_0_axi_periph_M02_AXI": { "interface_ports": [ "S00_AXI", @@ -7752,22 +7752,16 @@ "amdc_gp3io_mux_0/S00_AXI" ] }, - "S00_AXI5_1": { - "interface_ports": [ - "S00_AXI5", - "amdc_gpio_direct_0/S00_AXI" - ] - }, "S00_AXI3_1": { "interface_ports": [ "S00_AXI3", "hier_ild1420_0/S00_AXI" ] }, - "S00_AXI1_1": { + "S00_AXI5_1": { "interface_ports": [ - "S00_AXI1", - "amdc_eddy_current_se_0/S00_AXI" + "S00_AXI5", + "amdc_gpio_direct_0/S00_AXI" ] }, "S00_AXI4_1": { @@ -7776,6 +7770,12 @@ "hier_ild1420_0/S00_AXI1" ] }, + "S00_AXI1_1": { + "interface_ports": [ + "S00_AXI1", + "amdc_eddy_current_se_0/S00_AXI" + ] + }, "S00_AXI6_1": { "interface_ports": [ "S00_AXI6", @@ -8273,16 +8273,16 @@ } }, "interface_nets": { - "S00_AXI3_1": { + "S00_AXI5_1": { "interface_ports": [ - "S00_AXI3", - "hier_ild1420_0/S00_AXI" + "S00_AXI5", + "amdc_gpio_direct_0/S00_AXI" ] }, - "S00_AXI6_1": { + "hier_ps_M48_AXI": { "interface_ports": [ - "S00_AXI6", - "amdc_amds_0/S00_AXI" + "S00_AXI", + "amdc_gp3io_mux_0/S00_AXI" ] }, "S00_AXI4_1": { @@ -8297,16 +8297,16 @@ "amdc_eddy_current_se_0/S00_AXI" ] }, - "S00_AXI5_1": { + "S00_AXI3_1": { "interface_ports": [ - "S00_AXI5", - "amdc_gpio_direct_0/S00_AXI" + "S00_AXI3", + "hier_ild1420_0/S00_AXI" ] }, - "hier_ps_M48_AXI": { + "S00_AXI6_1": { "interface_ports": [ - "S00_AXI", - "amdc_gp3io_mux_0/S00_AXI" + "S00_AXI6", + "amdc_amds_0/S00_AXI" ] } }, @@ -8616,17 +8616,17 @@ } }, "interface_nets": { - "hier_ps_M12_AXI": { - "interface_ports": [ - "S00_AXI", - "amdc_ild1420_0/S00_AXI" - ] - }, "hier_ps_M13_AXI": { "interface_ports": [ "S00_AXI1", "amdc_ild1420_1/S00_AXI" ] + }, + "hier_ps_M12_AXI": { + "interface_ports": [ + "S00_AXI", + "amdc_ild1420_0/S00_AXI" + ] } }, "nets": { @@ -8800,6 +8800,18 @@ } }, "interface_nets": { + "S00_AXI6_1": { + "interface_ports": [ + "S00_AXI6", + "amdc_amds_0/S00_AXI" + ] + }, + "S00_AXI5_1": { + "interface_ports": [ + "S00_AXI5", + "amdc_gpio_direct_0/S00_AXI" + ] + }, "S00_AXI1_1": { "interface_ports": [ "S00_AXI1", @@ -8812,28 +8824,16 @@ "hier_ild1420_0/S00_AXI" ] }, - "hier_ps_M48_AXI": { - "interface_ports": [ - "S00_AXI", - "amdc_gp3io_mux_0/S00_AXI" - ] - }, "S00_AXI4_1": { "interface_ports": [ "S00_AXI4", "hier_ild1420_0/S00_AXI1" ] }, - "S00_AXI5_1": { - "interface_ports": [ - "S00_AXI5", - "amdc_gpio_direct_0/S00_AXI" - ] - }, - "S00_AXI6_1": { + "hier_ps_M48_AXI": { "interface_ports": [ - "S00_AXI6", - "amdc_amds_0/S00_AXI" + "S00_AXI", + "amdc_gp3io_mux_0/S00_AXI" ] } }, @@ -9044,76 +9044,70 @@ "hier_ps/M20_AXI" ] }, - "hier_ps_M34_AXI1": { - "interface_ports": [ - "hier_ps/M34_AXI", - "hier_gpio_2/S00_AXI6" - ] - }, - "hier_ps_M37_AXI": { + "hier_ps_M29_AXI": { "interface_ports": [ - "amdc_dac_0/S00_AXI", - "hier_ps/M05_AXI" + "hier_ps/M29_AXI", + "hier_gpio_0/S00_AXI5" ] }, - "S00_AXI1_5": { + "S00_AXI_3": { "interface_ports": [ - "hier_gpio_3/S00_AXI1", - "hier_ps/M26_AXI" + "hier_gpio_1/S00_AXI", + "hier_ps/M14_AXI" ] }, - "S00_AXI3_1": { + "hier_ps_M33_AXI1": { "interface_ports": [ - "hier_gpio_0/S00_AXI3", - "hier_ps/M12_AXI" + "amdc_timing_manager_0/S00_AXI", + "hier_ps/M33_AXI" ] }, - "hier_ps_M36_AXI": { + "hier_ps_M37_AXI1": { "interface_ports": [ - "amdc_adc_0/S00_AXI", - "hier_ps/M04_AXI" + "hier_ps/M37_AXI", + "hier_gpio_3/S00_AXI6" ] }, - "S00_AXI_5": { + "S00_AXI3_4": { "interface_ports": [ - "hier_gpio_3/S00_AXI", - "hier_ps/M24_AXI" + "hier_gpio_3/S00_AXI3", + "hier_ps/M27_AXI" ] }, - "hier_ps_M32_AXI1": { + "S00_AXI3_3": { "interface_ports": [ - "hier_ps/M32_AXI", - "hier_gpio_3/S00_AXI5" + "hier_gpio_2/S00_AXI3", + "hier_ps/M22_AXI" ] }, - "S00_AXI1_2": { + "hier_ps_M36_AXI": { "interface_ports": [ - "hier_gpio_0/S00_AXI1", - "hier_ps/M11_AXI" + "amdc_adc_0/S00_AXI", + "hier_ps/M04_AXI" ] }, - "S00_AXI4_1": { + "hier_ps_M34_AXI": { "interface_ports": [ - "hier_gpio_0/S00_AXI4", - "hier_ps/M13_AXI" + "amdc_encoder_0/S00_AXI", + "hier_ps/M02_AXI" ] }, - "hier_ps_M29_AXI": { + "hier_ps_M30_AXI": { "interface_ports": [ - "hier_ps/M29_AXI", - "hier_gpio_0/S00_AXI5" + "hier_ps/M30_AXI", + "hier_gpio_1/S00_AXI5" ] }, - "S00_AXI4_3": { + "hier_ps_M36_AXI1": { "interface_ports": [ - "hier_gpio_2/S00_AXI4", - "hier_ps/M23_AXI" + "hier_ps/M36_AXI", + "hier_gpio_1/S00_AXI6" ] }, - "hier_ps_M34_AXI": { + "S00_AXI1_3": { "interface_ports": [ - "amdc_encoder_0/S00_AXI", - "hier_ps/M02_AXI" + "hier_gpio_1/S00_AXI1", + "hier_ps/M16_AXI" ] }, "S00_AXI4_2": { @@ -9122,112 +9116,106 @@ "hier_ps/M18_AXI" ] }, - "hier_ps_M37_AXI1": { - "interface_ports": [ - "hier_ps/M37_AXI", - "hier_gpio_3/S00_AXI6" - ] - }, - "S00_AXI3_4": { + "hier_ps_M35_AXI": { "interface_ports": [ - "hier_gpio_3/S00_AXI3", - "hier_ps/M27_AXI" + "amdc_leds_0/S00_AXI", + "hier_ps/M03_AXI" ] }, - "S00_AXI3_2": { + "S00_AXI4_4": { "interface_ports": [ - "hier_gpio_1/S00_AXI3", - "hier_ps/M17_AXI" + "hier_gpio_3/S00_AXI4", + "hier_ps/M28_AXI" ] }, - "hier_ps_M36_AXI1": { + "S00_AXI4_3": { "interface_ports": [ - "hier_ps/M36_AXI", - "hier_gpio_1/S00_AXI6" + "hier_gpio_2/S00_AXI4", + "hier_ps/M23_AXI" ] }, - "S00_AXI_3": { + "S00_AXI1_2": { "interface_ports": [ - "hier_gpio_1/S00_AXI", - "hier_ps/M14_AXI" + "hier_gpio_0/S00_AXI1", + "hier_ps/M11_AXI" ] }, - "S00_AXI1_1": { + "S00_AXI4_1": { "interface_ports": [ - "hier_powerstack/S00_AXI1", - "hier_ps/M07_AXI" + "hier_gpio_0/S00_AXI4", + "hier_ps/M13_AXI" ] }, - "hier_ps_M30_AXI": { + "S00_AXI_5": { "interface_ports": [ - "hier_ps/M30_AXI", - "hier_gpio_1/S00_AXI5" + "hier_gpio_3/S00_AXI", + "hier_ps/M24_AXI" ] }, - "hier_ps_M31_AXI": { + "S00_AXI1_5": { "interface_ports": [ - "hier_ps/M31_AXI", - "hier_gpio_2/S00_AXI5" + "hier_gpio_3/S00_AXI1", + "hier_ps/M26_AXI" ] }, - "hier_ps_M35_AXI": { + "hier_ps_M37_AXI": { "interface_ports": [ - "amdc_leds_0/S00_AXI", - "hier_ps/M03_AXI" + "amdc_dac_0/S00_AXI", + "hier_ps/M05_AXI" ] }, - "processing_system7_0_FIXED_IO": { + "S00_AXI3_1": { "interface_ports": [ - "FIXED_IO", - "hier_ps/FIXED_IO" + "hier_gpio_0/S00_AXI3", + "hier_ps/M12_AXI" ] }, - "S00_AXI3_3": { + "S00_AXI2_3": { "interface_ports": [ - "hier_gpio_2/S00_AXI3", - "hier_ps/M22_AXI" + "hier_gpio_1/S00_AXI2", + "hier_ps/M15_AXI" ] }, - "S00_AXI4_4": { + "hier_ps_M32_AXI1": { "interface_ports": [ - "hier_gpio_3/S00_AXI4", - "hier_ps/M28_AXI" + "hier_ps/M32_AXI", + "hier_gpio_3/S00_AXI5" ] }, - "hier_ps_M33_AXI1": { + "hier_ps_M31_AXI": { "interface_ports": [ - "amdc_timing_manager_0/S00_AXI", - "hier_ps/M33_AXI" + "hier_ps/M31_AXI", + "hier_gpio_2/S00_AXI5" ] }, - "S00_AXI1_3": { + "hier_ps_M34_AXI1": { "interface_ports": [ - "hier_gpio_1/S00_AXI1", - "hier_ps/M16_AXI" + "hier_ps/M34_AXI", + "hier_gpio_2/S00_AXI6" ] }, - "S00_AXI2_3": { + "S00_AXI1_1": { "interface_ports": [ - "hier_gpio_1/S00_AXI2", - "hier_ps/M15_AXI" + "hier_powerstack/S00_AXI1", + "hier_ps/M07_AXI" ] }, - "processing_system7_0_DDR": { + "processing_system7_0_FIXED_IO": { "interface_ports": [ - "DDR", - "hier_ps/DDR" + "FIXED_IO", + "hier_ps/FIXED_IO" ] }, - "S00_AXI2_1": { + "S00_AXI3_2": { "interface_ports": [ - "hier_powerstack/S00_AXI2", - "hier_ps/M08_AXI" + "hier_gpio_1/S00_AXI3", + "hier_ps/M17_AXI" ] }, - "S00_AXI_4": { + "processing_system7_0_DDR": { "interface_ports": [ - "hier_gpio_2/S00_AXI", - "hier_ps/M19_AXI" + "DDR", + "hier_ps/DDR" ] }, "S00_AXI_1": { @@ -9236,12 +9224,6 @@ "hier_ps/M06_AXI" ] }, - "S00_AXI2_5": { - "interface_ports": [ - "hier_gpio_3/S00_AXI2", - "hier_ps/M25_AXI" - ] - }, "S00_AXI1_4": { "interface_ports": [ "hier_gpio_2/S00_AXI1", @@ -9265,6 +9247,24 @@ "hier_gpio_0/S00_AXI2", "hier_ps/M10_AXI" ] + }, + "S00_AXI2_1": { + "interface_ports": [ + "hier_powerstack/S00_AXI2", + "hier_ps/M08_AXI" + ] + }, + "S00_AXI2_5": { + "interface_ports": [ + "hier_gpio_3/S00_AXI2", + "hier_ps/M25_AXI" + ] + }, + "S00_AXI_4": { + "interface_ports": [ + "hier_gpio_2/S00_AXI", + "hier_ps/M19_AXI" + ] } }, "nets": { diff --git a/ip_repo/amdc_timing_manager_1.0/README.md b/ip_repo/amdc_timing_manager_1.0/README.md index ba9455ac..434233c9 100644 --- a/ip_repo/amdc_timing_manager_1.0/README.md +++ b/ip_repo/amdc_timing_manager_1.0/README.md @@ -77,6 +77,7 @@ This IP is accessed via the AXI4-Lite register-based interface from the DSP. Thi | -- | -- | -- | | 0 | RESET_SCHED_ISR | Clears the hardware interrupt once it has been recieved by the processing system | | 1 | SCHED_SOURCE_MODE | Determines the source of the interrupt for the scheduler: legacy mode or timing manager-synchronized | +| 31 | SCHED_ISR | (READ-ONLY) The scheduler ISR interrupt signal directly from the timing manager, made available for debugging | ### ISR_TIME diff --git a/ip_repo/amdc_timing_manager_1.0/component.xml b/ip_repo/amdc_timing_manager_1.0/component.xml index 329a9df6..20ab6592 100644 --- a/ip_repo/amdc_timing_manager_1.0/component.xml +++ b/ip_repo/amdc_timing_manager_1.0/component.xml @@ -288,7 +288,7 @@ viewChecksum - 22a43c4b + acf7e706 @@ -304,7 +304,7 @@ viewChecksum - 22a43c4b + acf7e706 @@ -1176,8 +1176,8 @@ AXI_Peripheral amdc_timing_manager_v1.0 - 46 - 2024-06-19T20:23:24Z + 47 + 2024-08-05T18:33:28Z c:/Users/atolson3/Documents/AMDC/AMDC-Firmware/ip_repo/amdc_timing_manager_1.0 c:/Users/atolson3/Documents/AMDC/AMDC-Firmware/ip_repo/amdc_timing_manager_1.0 @@ -1784,13 +1784,18 @@ s:/School/WEMPEC/firmware-e/ip_repo/amdc_timing_manager_1.0 s:/School/WEMPEC/firmware-e/ip_repo/amdc_timing_manager_1.0 s:/School/WEMPEC/firmware-e/ip_repo/amdc_timing_manager_1.0 + s:/School/WEMPEC/firmware-amds/ip_repo/amdc_timing_manager_1.0 + s:/School/WEMPEC/firmware-amds/ip_repo/amdc_timing_manager_1.0 + s:/School/WEMPEC/firmware-amds/ip_repo/amdc_timing_manager_1.0 + s:/School/WEMPEC/firmware-amds/ip_repo/amdc_timing_manager_1.0 + s:/School/WEMPEC/firmware-amds/ip_repo/amdc_timing_manager_1.0 2019.1 - + diff --git a/ip_repo/amdc_timing_manager_1.0/hdl/amdc_timing_manager_v1_0_S00_AXI.v b/ip_repo/amdc_timing_manager_1.0/hdl/amdc_timing_manager_v1_0_S00_AXI.v index a9a4984a..45d2781f 100644 --- a/ip_repo/amdc_timing_manager_1.0/hdl/amdc_timing_manager_v1_0_S00_AXI.v +++ b/ip_repo/amdc_timing_manager_1.0/hdl/amdc_timing_manager_v1_0_S00_AXI.v @@ -530,7 +530,7 @@ 4'h2 : reg_data_out <= sensor_done_status; // Sensor Done Status 4'h3 : reg_data_out <= slv_reg3; // User Ratio 4'h4 : reg_data_out <= slv_reg4; // PWM Sync - 4'h5 : reg_data_out <= slv_reg5; // ISR + 4'h5 : reg_data_out <= {sched_isr,slv_reg5[30:0]}; // ISR - MSb is sched_isr from TM for debug 4'h6 : reg_data_out <= sched_tick_time; // Trigger timer 4'h7 : reg_data_out <= adc_enc_time_reg; // ADC & Encoder Times 4'h8 : reg_data_out <= amds_01_time_reg; // AMDS Times diff --git a/ip_repo/amdc_timing_manager_1.0/src/timing_manager.v b/ip_repo/amdc_timing_manager_1.0/src/timing_manager.v index 8f94ddae..139843e7 100644 --- a/ip_repo/amdc_timing_manager_1.0/src/timing_manager.v +++ b/ip_repo/amdc_timing_manager_1.0/src/timing_manager.v @@ -196,19 +196,15 @@ module timing_manager( // acquisition/conversion cycle (e.g. on the rising edge // of the all_done signal) ////////////////////////////////////////////////////////////////// + wire assert_sched_isr; + assign assert_sched_isr = sched_source_mode ? (sensors_enabled ? all_done_pe : (count == user_ratio)) : // sched_source_mode == 1, Timing Manager Mode + (count == user_ratio); // sched_source_mode == 0, Legacy Mode always @(posedge clk, negedge rst_n) begin if (!rst_n) sched_isr <= 0; else if (reset_sched_isr) sched_isr <= 0; - else if (~sched_source_mode & (count == user_ratio)) - // Legacy (mode 0) - sched_isr <= 1; - else if (sched_source_mode & ~sensors_enabled & (count == user_ratio)) - // Timing Manager (mode 1) with no sensors enabled - sched_isr <= 1; - else if (sched_source_mode & all_done_pe) - // Timing Manager (mode 1) after sensors are enabled + else if (assert_sched_isr) sched_isr <= 1; end diff --git a/sdk/app_cpu1/common/drv/timing_manager.c b/sdk/app_cpu1/common/drv/timing_manager.c index 2e022b4c..b73743cb 100644 --- a/sdk/app_cpu1/common/drv/timing_manager.c +++ b/sdk/app_cpu1/common/drv/timing_manager.c @@ -173,7 +173,7 @@ uint32_t timing_manager_get_trigger_count(void) * Specify the interrupt source of the scheduler ISR: * * Mode 0 uses the timing manager's 'trigger' signal, i.e. the control - * frequency based on the PWM carrier frequency and the user-specified PWM sub-ratio. + * frequency is based on the PWM carrier frequency and the user-specified PWM sub-ratio. * * Mode 1 uses the timing manager's 'all_done' signal, calling the scheduler * when all the sensors are done with acquisition. When no sensors are enabled, diff --git a/sdk/app_cpu1/common/sys/scheduler.c b/sdk/app_cpu1/common/sys/scheduler.c index d1132235..6af8d9ef 100644 --- a/sdk/app_cpu1/common/sys/scheduler.c +++ b/sdk/app_cpu1/common/sys/scheduler.c @@ -198,7 +198,7 @@ void scheduler_run(void) // due to the imprecision of converting FPGA time to double values in the C code. // Therefore, we will schedule the task if the difference between the // usec_since_last_run and the target interval is within the defined tolerance. - if ((usec_since_last_run - t->interval_usec) >= SCHEDULER_INTERVAL_TOLERANCE_USEC) { + if ((t->interval_usec - usec_since_last_run) <= SCHEDULER_INTERVAL_TOLERANCE_USEC) { // Time to run this task! task_stats_pre_task(&t->stats); diff --git a/sdk/app_cpu1/common/sys/scheduler.h b/sdk/app_cpu1/common/sys/scheduler.h index 32e33b71..77d016d9 100644 --- a/sdk/app_cpu1/common/sys/scheduler.h +++ b/sdk/app_cpu1/common/sys/scheduler.h @@ -14,13 +14,24 @@ #define USEC_TO_SEC(usec) (usec / USEC_IN_SEC) // Timing Threshold - 60ns -// Typically, the variance of the measured interval from the expected interval is -// no more than 20ns, but we'll use a tolerance of three times this for safety :) -// The tolerance value is negative, as the target interval is subtracted from -// the measured interval. If the former is larger than the latter, the subtraction -// result will be a negative value. The check to run the task then confirms -// that the difference is *less-negative* than this tolerance -#define SCHEDULER_INTERVAL_TOLERANCE_USEC (-0.06) +// When the scheduler checks to see if a task should be scheduled in scheduler_run(), +// the task's measured loop time is subtracted from the target loop time. If the former +// is larger than the latter, the result will be negative and obviously the task should be +// scheduled. However, it is possible with floating point numbers that the measured loop +// time will be *just less* than the target loop time, in which case the subtraction +// result will be a very small positive number. We still want the task to be run in this +// case, so instead of checking if the subtraction result is less than 0, we check that +// it is less than a very small positive variance value. Typically, this variance of the +// measured interval from the expected interval is no more than 20ns, but we'll use a +// tolerance of three times this for safety :) +// NOTE: this is with the default timing settings of 100 kHz PWM Carrier and +// a Timing Manager ratio of 10 events. For abnormal timing settings, the +// magnitude of the tolerance can be overridden in user_config.h +#ifndef USER_CONFIG_SCHEDULER_INTERVAL_TOLERANCE_USEC +#define SCHEDULER_INTERVAL_TOLERANCE_USEC (0.06) +#else +#define SCHEDULER_INTERVAL_TOLERANCE_USEC (USER_CONFIG_SCHEDULER_INTERVAL_TOLERANCE_USEC) +#endif // Callback into application when task is run: typedef void (*task_callback_t)(void *); diff --git a/sdk/app_cpu1/user/usr/user_config.h b/sdk/app_cpu1/user/usr/user_config.h index 1ec2d290..4faf19a8 100644 --- a/sdk/app_cpu1/user/usr/user_config.h +++ b/sdk/app_cpu1/user/usr/user_config.h @@ -49,4 +49,12 @@ // set to 1 for enabled, 0 for disabled #define USER_CONFIG_ENABLE_AMDS_SUPPORT (0) +// Scheduler Interval Tolerance Override +// as of AMDC Firmware v1.3, all timing variables for tasks (runtime, loop time, etc) +// are stored as double-precision floating point values, which have precision errors +// that require a margin of tolerance. sometimes non-default PWM frequency and/or +// timing manager ratios may necessitate un-commenting the following define to override +// the default tolerance in common/sys/scheduler.h +//#define USER_CONFIG_SCHEDULER_INTERVAL_TOLERANCE_USEC (0.15) + #endif // USER_CONFIG_H