From 193390bbdd171f8a50e47dcacb8d4805d693e011 Mon Sep 17 00:00:00 2001 From: dylad Date: Fri, 31 Jan 2025 10:24:34 +0100 Subject: [PATCH] cpu/sam3: optimize gpio ISR processing Signed-off-by: dylad --- cpu/sam3/periph/gpio.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/cpu/sam3/periph/gpio.c b/cpu/sam3/periph/gpio.c index 6253814094b4..b55179cbca0f 100644 --- a/cpu/sam3/periph/gpio.c +++ b/cpu/sam3/periph/gpio.c @@ -22,6 +22,7 @@ * @} */ +#include "bitarithm.h" #include "cpu.h" #include "periph/gpio.h" #include "periph_conf.h" @@ -313,11 +314,11 @@ static inline void isr_handler(Pio *port, int port_num) /* take interrupt flags only from pins which interrupt is enabled */ uint32_t status = (port->PIO_ISR & port->PIO_IMR); - for (int i = 0; i < 32; i++) { - if (status & ((uint32_t)1 << i)) { - int ctx = _ctx(port_num, i); - exti_ctx[ctx].cb(exti_ctx[ctx].arg); - } + while (status) { + uint8_t pin_number; + status = bitarithm_test_and_clear(status, &pin_number); + int ctx = _ctx(port_num, pin_number); + exti_ctx[ctx].cb(exti_ctx[ctx].arg); } cortexm_isr_end(); }