From 5b4389cf46acff8c9439456068ef0d9fae3ef34e Mon Sep 17 00:00:00 2001 From: Gunar Schorcht Date: Sat, 22 Feb 2020 01:31:42 +0100 Subject: [PATCH] cpu/esp32: update of ld script for littlefs* During the write access to the SPI flash, the IROM cache is not available and only code from the IRAM can be executed. Therefore, the code of file system implementations which access the SPI flash must reside in IRAM. --- cpu/esp32/ld/esp32.common.ld | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/cpu/esp32/ld/esp32.common.ld b/cpu/esp32/ld/esp32.common.ld index 9fafb736eff5..5959333557c3 100644 --- a/cpu/esp32/ld/esp32.common.ld +++ b/cpu/esp32/ld/esp32.common.ld @@ -101,11 +101,13 @@ SECTIONS *esp_idf_spi_flash.a:*(.literal .text .literal.* .text.*) /* parts of RIOT that should to run in IRAM */ *core.a:*(.literal .text .literal.* .text.*) + *littlefs.a:*(.literal .text .literal.* .text.*) + *littlefs2.a:*(.literal .text .literal.* .text.*) *spiffs_fs.a:*(.literal .text .literal.* .text.*) *spiffs.a:*(.literal .text .literal.* .text.*) *vfs.a:*(.literal .text .literal.* .text.*) - /* part of RIOT ports that should run in IRAM */ + /* part of the RIOT port that should run in IRAM */ *cpu.a:*(.literal .text .literal.* .text.*) *periph.a:*(.literal .text .literal.* .text.*) *mtd.a:**(.literal .text .literal.* .text.*)