Disable parallel build of Verilog-A modules

Parallel runs of admsXml can create a race to write the header files. See: https://github.com/Qucs/qucs/issues/545
Qucs · Oct 30, 2016 · 1c4811c · 1c4811c
1 parent 1702a18
commit 1c4811c
Showing 1 changed file with 4 additions and 0 deletions.
diff --git a/qucs-core/src/components/verilog/Makefile.am b/qucs-core/src/components/verilog/Makefile.am
@@ -33,6 +33,10 @@ XML_BUILD = \
   $(srcdir)/qucsMODULEcore.xml \
   $(srcdir)/qucsMODULEdefs.xml
 
+# Parallel runs of admsXml can create a race to write the header files
+# See: https://github.com/Qucs/qucs/issues/545
+.NOTPARALLEL:
+
 .va.cpp: $(XML_BUILD)
 	@for i in $(XML_BUILD); do \
 	  echo "$$i"; \