From 8d482b68d9d2d830b79b159f61ef281861b13bd1 Mon Sep 17 00:00:00 2001 From: "Christian, Glenn (DLSLtd,RAL,LSCI)" Date: Thu, 8 Aug 2024 11:26:14 +0100 Subject: [PATCH] Fix-up commit following merge --- apps/PandABrick.app.ini | 1 + modules/fmc_x4sfp/hdl/fmc_x4sfp_wrapper.vhd | 6 +++--- .../hdl_zynq/sfp_panda_sync_mgt_interface.vhd | 2 +- .../hdl_zynqmp/sfp_panda_sync_mgt_interface.vhd | 6 +++--- targets/PandABrick/PandABrick.target.ini | 2 +- targets/PandABrick/bd/panda_ps.tcl | 11 ++++++++--- targets/PandABrick/const/PandABrick-pins_impl.xdc | 2 +- targets/PandABrick/const/SFP1_pins.xdc | 8 ++++++++ targets/PandABrick/const/SFP_MGT_pins.xdc | 8 -------- targets/PandABrick/hdl/PandABrick_top.vhd | 10 +++++----- targets/xu5_st1/xu5_st1.target.ini | 3 +-- 11 files changed, 32 insertions(+), 27 deletions(-) create mode 100644 targets/PandABrick/const/SFP1_pins.xdc delete mode 100644 targets/PandABrick/const/SFP_MGT_pins.xdc diff --git a/apps/PandABrick.app.ini b/apps/PandABrick.app.ini index 8542f4254..a94297891 100644 --- a/apps/PandABrick.app.ini +++ b/apps/PandABrick.app.ini @@ -9,4 +9,5 @@ includes: common_soft_blocks.include.ini [SFP_SYNC] module: sfp_panda_sync ini: sfp_panda_sync_us.block.ini +site: sfp 1 diff --git a/modules/fmc_x4sfp/hdl/fmc_x4sfp_wrapper.vhd b/modules/fmc_x4sfp/hdl/fmc_x4sfp_wrapper.vhd index 8075a53da..34f8e4e37 100644 --- a/modules/fmc_x4sfp/hdl/fmc_x4sfp_wrapper.vhd +++ b/modules/fmc_x4sfp/hdl/fmc_x4sfp_wrapper.vhd @@ -5,7 +5,7 @@ use work.support.all; use work.top_defines.all; use work.interface_types.all; -entity fmc_x4sfp_top is +entity fmc_x4sfp_wrapper is port ( -- Clock and Reset clk_i : in std_logic; @@ -25,9 +25,9 @@ port ( write_ack_o : out std_logic; FMC : view FMC_Module ); -end fmc_x4sfp_top; +end fmc_x4sfp_wrapper; -architecture rtl of fmc_x4sfp_top is +architecture rtl of fmc_x4sfp_wrapper is signal FMC_PRSNT_DW : std_logic_vector(31 downto 0); diff --git a/modules/sfp_panda_sync/hdl_zynq/sfp_panda_sync_mgt_interface.vhd b/modules/sfp_panda_sync/hdl_zynq/sfp_panda_sync_mgt_interface.vhd index 9fbdab4d2..cad826df3 100644 --- a/modules/sfp_panda_sync/hdl_zynq/sfp_panda_sync_mgt_interface.vhd +++ b/modules/sfp_panda_sync/hdl_zynq/sfp_panda_sync_mgt_interface.vhd @@ -155,7 +155,7 @@ mgt_rst <= SYNC_RESET_i or init_rst; sfp_panda_sync_i : entity work.sfp_panda_sync port map( SYSCLK_IN => GTREFCLK_i, - SOFT_RESET_TX_IN => mgt_rst, + SOFT_RESET_TX_IN => init_rst, SOFT_RESET_RX_IN => mgt_rst, DONT_RESET_ON_DATA_ERROR_IN => '0', GT0_TX_FSM_RESET_DONE_OUT => GT0_TX_FSM_RESET_DONE, diff --git a/modules/sfp_panda_sync/hdl_zynqmp/sfp_panda_sync_mgt_interface.vhd b/modules/sfp_panda_sync/hdl_zynqmp/sfp_panda_sync_mgt_interface.vhd index 5d281baed..8002e8e7c 100644 --- a/modules/sfp_panda_sync/hdl_zynqmp/sfp_panda_sync_mgt_interface.vhd +++ b/modules/sfp_panda_sync/hdl_zynqmp/sfp_panda_sync_mgt_interface.vhd @@ -217,9 +217,9 @@ sfp_panda_sync_us_i : sfp_panda_sync_us gthtxn_out(0) => txn_o, gthtxp_out(0) => txp_o, gtpowergood_out => open, - rxbyteisaligned_out(0) => open, - rxbyterealign_out(0) => open, - rxcommadet_out(0) => open, + rxbyteisaligned_out => open, + rxbyterealign_out => open, + rxcommadet_out => open, rxctrl0_out => rxctrl0_int, -- K character detect rxctrl1_out => rxctrl1_int, -- Rx data disparity error rxctrl2_out => rxctrl2_int, -- Comma detect (per byte) diff --git a/targets/PandABrick/PandABrick.target.ini b/targets/PandABrick/PandABrick.target.ini index 74209bc50..5809ec0e4 100644 --- a/targets/PandABrick/PandABrick.target.ini +++ b/targets/PandABrick/PandABrick.target.ini @@ -2,7 +2,7 @@ # module. The config files for each carrier block can be found in # blocks/blockname [.] -io: sfp: 1, i, o +io: sfp: mgt, 1 options: pcap_std_dev [TTLIN] diff --git a/targets/PandABrick/bd/panda_ps.tcl b/targets/PandABrick/bd/panda_ps.tcl index b60f7aa22..573f3f3bc 100644 --- a/targets/PandABrick/bd/panda_ps.tcl +++ b/targets/PandABrick/bd/panda_ps.tcl @@ -195,6 +195,8 @@ proc create_root_design { parentCell } { # Create interface ports + set IIC_FPGA [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 IIC_FPGA ] + set M00_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M00_AXI ] set_property -dict [ list \ CONFIG.ADDR_WIDTH {32} \ @@ -776,7 +778,7 @@ MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#U CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {100.000000} \ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \ CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ {27.138} \ @@ -995,7 +997,8 @@ MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#U CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} \ CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 10 .. 11} \ CONFIG.PSU__I2C1__GRP_INT__ENABLE {0} \ - CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__I2C1__PERIPHERAL__IO {EMIO} \ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \ @@ -1036,6 +1039,7 @@ MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#U CONFIG.PSU__IRQ_P2F_GPIO__INT {0} \ CONFIG.PSU__IRQ_P2F_GPU__INT {0} \ CONFIG.PSU__IRQ_P2F_I2C0__INT {0} \ + CONFIG.PSU__IRQ_P2F_I2C1__INT {0} \ CONFIG.PSU__IRQ_P2F_LPD_APB__INT {0} \ CONFIG.PSU__IRQ_P2F_LPD_APM__INT {0} \ CONFIG.PSU__IRQ_P2F_LP_WDT__INT {0} \ @@ -1132,7 +1136,7 @@ SA:0xFF9A0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsyste \ CONFIG.PSU__PROTECTION__OCM_SEGMENTS {NONE} \ CONFIG.PSU__PROTECTION__PRESUBSYSTEMS {NONE} \ - CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;1|LPD;USB3_1;FF9E0000;FF9EFFFF;1|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;0|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;0|LPD;TTC2;FF130000;FF13FFFF;0|LPD;TTC1;FF120000;FF12FFFF;0|LPD;TTC0;FF110000;FF11FFFF;0|FPD;SWDT1;FD4D0000;FD4DFFFF;0|LPD;SWDT0;FF150000;FF15FFFF;0|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;0|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;0|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;1|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display\ + CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;1|LPD;USB3_1;FF9E0000;FF9EFFFF;1|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;0|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;0|LPD;TTC2;FF130000;FF13FFFF;0|LPD;TTC1;FF120000;FF12FFFF;0|LPD;TTC0;FF110000;FF11FFFF;0|FPD;SWDT1;FD4D0000;FD4DFFFF;0|LPD;SWDT0;FF150000;FF15FFFF;0|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;0|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;1|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display\ Port;FD4A0000;FD4AFFFF;0|FPD;DPDMA;FD4C0000;FD4CFFFF;0|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1}\ \ CONFIG.PSU__PROTECTION__SUBSYSTEMS {PMU Firmware:PMU|Secure Subsystem:} \ @@ -1285,6 +1289,7 @@ Port;FD4A0000;FD4AFFFF;0|FPD;DPDMA;FD4C0000;FD4CFFFF;0|FPD;DDR_XMPU5_CFG;FD05000 connect_bd_intf_net -intf_net S_AXI_HP1_1 [get_bd_intf_ports S_AXI_HP1] [get_bd_intf_pins smartconnect_1/S01_AXI] connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_ports M00_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI] connect_bd_intf_net -intf_net smartconnect_1_M00_AXI [get_bd_intf_pins smartconnect_1/M00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP0_FPD] + connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_IIC_1 [get_bd_intf_ports IIC_FPGA] [get_bd_intf_pins zynq_ultra_ps_e_0/IIC_1] connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_FPD [get_bd_intf_pins smartconnect_0/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_FPD] # Create port connections diff --git a/targets/PandABrick/const/PandABrick-pins_impl.xdc b/targets/PandABrick/const/PandABrick-pins_impl.xdc index 3991143f0..a0ebc012e 100644 --- a/targets/PandABrick/const/PandABrick-pins_impl.xdc +++ b/targets/PandABrick/const/PandABrick-pins_impl.xdc @@ -203,5 +203,5 @@ set_property -dict {PACKAGE_PIN AD12 IOSTANDARD LVCMOS18 } [get_ports {IO4_D7_ set_property PACKAGE_PIN V5 [get_ports mgtrefclk1_x0y1_n] set_property PACKAGE_PIN V6 [get_ports mgtrefclk1_x0y1_p] -set SFP_LOC GTHE4_CHANNEL_X0Y5 +set SFP1_LOC GTHE4_CHANNEL_X0Y5 diff --git a/targets/PandABrick/const/SFP1_pins.xdc b/targets/PandABrick/const/SFP1_pins.xdc new file mode 100644 index 000000000..bbcd3141a --- /dev/null +++ b/targets/PandABrick/const/SFP1_pins.xdc @@ -0,0 +1,8 @@ + +# Tx and Rx Pins... + +set_property PACKAGE_PIN V2 [get_ports ch1_gthrxp_in] +set_property PACKAGE_PIN V1 [get_ports ch1_gthrxn_in] +set_property PACKAGE_PIN U4 [get_ports ch1_gthtxp_out] +set_property PACKAGE_PIN U3 [get_ports ch1_gthtxn_out] + diff --git a/targets/PandABrick/const/SFP_MGT_pins.xdc b/targets/PandABrick/const/SFP_MGT_pins.xdc deleted file mode 100644 index 82775d878..000000000 --- a/targets/PandABrick/const/SFP_MGT_pins.xdc +++ /dev/null @@ -1,8 +0,0 @@ - -# Tx and Rx Pins... - -#set_property PACKAGE_PIN V2 [get_ports ch1_gthrxp_in] -#set_property PACKAGE_PIN V1 [get_ports ch1_gthrxn_in] -#set_property PACKAGE_PIN U4 [get_ports ch1_gthtxp_out] -#set_property PACKAGE_PIN U3 [get_ports ch1_gthtxn_out] - diff --git a/targets/PandABrick/hdl/PandABrick_top.vhd b/targets/PandABrick/hdl/PandABrick_top.vhd index 95ab817bf..3053f788b 100644 --- a/targets/PandABrick/hdl/PandABrick_top.vhd +++ b/targets/PandABrick/hdl/PandABrick_top.vhd @@ -20,14 +20,15 @@ use unisim.vcomponents.all; library work; use work.addr_defines.all; use work.top_defines.all; +use work.interface_types.all; entity PandABrick_top is generic ( - SIM : string := "FALSE"; AXI_ADDR_WIDTH : integer := 32; AXI_DATA_WIDTH : integer := 32; NUM_SFP : natural := 1; - NUM_FMC : natural := 0 + NUM_FMC : natural := 0; + MAX_NUM_FMC_MGT : natural := 0 ); port ( @@ -234,7 +235,7 @@ end component; -- signal declarations --------------------------------------------------------------------------------------------------- -constant NUM_MGT : natural := NUM_SFP + NUM_FMC_MGT; +constant NUM_MGT : natural := NUM_SFP + MAX_NUM_FMC_MGT; constant ENC_NUM : natural := 8; -- PS Block @@ -1526,7 +1527,6 @@ SFP_MGT.MGT_ARR(0).MAC_ADDR_WS <= '0'; --------------------------------------------------------------------------- softblocks_inst : entity work.soft_blocks -generic map( SIM => SIM) port map( FCLK_CLK0 => FCLK_CLK0, FCLK_RESET0 => FCLK_RESET0, @@ -1549,7 +1549,7 @@ port map( rdma_len => rdma_len, rdma_data => rdma_data, rdma_valid => rdma_valid, - SFP_MGT => SFP_MGT + SFP => SFP_MGT ); us_system_top_inst : entity work.us_system_top diff --git a/targets/xu5_st1/xu5_st1.target.ini b/targets/xu5_st1/xu5_st1.target.ini index 5da35d0aa..b8cb57c76 100644 --- a/targets/xu5_st1/xu5_st1.target.ini +++ b/targets/xu5_st1/xu5_st1.target.ini @@ -3,8 +3,7 @@ # blocks/blockname [.] io: fmc: 1 - fmc_mgt: mgt, 0 -additionalMGT: 4 + fmc_mgt: mgt, 4* [TTLIN] number: 1