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0051-Xtensa-Implemented-builtins-for-Xtensa-MAC16.patch
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0051-Xtensa-Implemented-builtins-for-Xtensa-MAC16.patch
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From 75de39fdcdeb68b4e4bdea92415e49c47ba05001 Mon Sep 17 00:00:00 2001
From: Andrei Safronov <safronov@espressif.com>
Date: Wed, 5 Apr 2023 00:59:03 +0300
Subject: [PATCH 051/158] [Xtensa] Implemented builtins for Xtensa MAC16
instructions.
---
clang/include/clang/Basic/BuiltinsXtensa.def | 127 +++++++
clang/include/clang/Basic/TargetBuiltins.h | 10 +
clang/lib/Basic/Targets/Xtensa.cpp | 11 +
clang/lib/Basic/Targets/Xtensa.h | 2 +-
llvm/include/llvm/IR/CMakeLists.txt | 1 +
llvm/include/llvm/IR/IntrinsicsXtensa.td | 251 ++++++++++++++
llvm/lib/IR/Function.cpp | 1 +
llvm/lib/Target/Xtensa/XtensaDSPInstrInfo.td | 175 ++++++++--
llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp | 257 +++++++++++++-
llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 262 ++++++++++++++
llvm/test/CodeGen/Xtensa/lit.local.cfg | 2 +
llvm/test/CodeGen/Xtensa/mac16_intrinsics.ll | 319 ++++++++++++++++++
.../secondary/llvm/include/llvm/IR/BUILD.gn | 5 +
13 files changed, 1388 insertions(+), 35 deletions(-)
create mode 100644 clang/include/clang/Basic/BuiltinsXtensa.def
create mode 100644 llvm/include/llvm/IR/IntrinsicsXtensa.td
create mode 100644 llvm/test/CodeGen/Xtensa/lit.local.cfg
create mode 100644 llvm/test/CodeGen/Xtensa/mac16_intrinsics.ll
diff --git a/clang/include/clang/Basic/BuiltinsXtensa.def b/clang/include/clang/Basic/BuiltinsXtensa.def
new file mode 100644
index 000000000000..47f75f1665b1
--- /dev/null
+++ b/clang/include/clang/Basic/BuiltinsXtensa.def
@@ -0,0 +1,127 @@
+//===-- BuiltinsXtensa.def - Xtensa Builtin function database ----*- C++ -*-==//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the Xtensa-specific builtin function database. Users of
+// this file must define the BUILTIN macro to make use of this information.
+//
+//===----------------------------------------------------------------------===//
+
+// The format of this database matches clang/Basic/Builtins.def.
+
+BUILTIN(__builtin_xtensa_umul_aa_ll, "vUiUi", "n")
+BUILTIN(__builtin_xtensa_umul_aa_lh, "vUiUi", "n")
+BUILTIN(__builtin_xtensa_umul_aa_hl, "vUiUi", "n")
+BUILTIN(__builtin_xtensa_umul_aa_hh, "vUiUi", "n")
+
+BUILTIN(__builtin_xtensa_mul_aa_ll, "vUiUi", "n")
+BUILTIN(__builtin_xtensa_mul_aa_lh, "vUiUi", "n")
+BUILTIN(__builtin_xtensa_mul_aa_hl, "vUiUi", "n")
+BUILTIN(__builtin_xtensa_mul_aa_hh, "vUiUi", "n")
+
+BUILTIN(__builtin_xtensa_mul_ad_ll, "vUiIUi", "n")
+BUILTIN(__builtin_xtensa_mul_ad_lh, "vUiIUi", "n")
+BUILTIN(__builtin_xtensa_mul_ad_hl, "vUiIUi", "n")
+BUILTIN(__builtin_xtensa_mul_ad_hh, "vUiIUi", "n")
+
+BUILTIN(__builtin_xtensa_mul_da_ll, "vIUiUi", "n")
+BUILTIN(__builtin_xtensa_mul_da_lh, "vIUiUi", "n")
+BUILTIN(__builtin_xtensa_mul_da_hl, "vIUiUi", "n")
+BUILTIN(__builtin_xtensa_mul_da_hh, "vIUiUi", "n")
+
+BUILTIN(__builtin_xtensa_mul_dd_ll, "vIUiIUi", "n")
+BUILTIN(__builtin_xtensa_mul_dd_lh, "vIUiIUi", "n")
+BUILTIN(__builtin_xtensa_mul_dd_hl, "vIUiIUi", "n")
+BUILTIN(__builtin_xtensa_mul_dd_hh, "vIUiIUi", "n")
+
+BUILTIN(__builtin_xtensa_mula_aa_ll, "vUiUi", "n")
+BUILTIN(__builtin_xtensa_mula_aa_lh, "vUiUi", "n")
+BUILTIN(__builtin_xtensa_mula_aa_hl, "vUiUi", "n")
+BUILTIN(__builtin_xtensa_mula_aa_hh, "vUiUi", "n")
+
+BUILTIN(__builtin_xtensa_mula_ad_ll, "vUiIUi", "n")
+BUILTIN(__builtin_xtensa_mula_ad_lh, "vUiIUi", "n")
+BUILTIN(__builtin_xtensa_mula_ad_hl, "vUiIUi", "n")
+BUILTIN(__builtin_xtensa_mula_ad_hh, "vUiIUi", "n")
+
+BUILTIN(__builtin_xtensa_mula_da_ll, "vIUiUi", "n")
+BUILTIN(__builtin_xtensa_mula_da_lh, "vIUiUi", "n")
+BUILTIN(__builtin_xtensa_mula_da_hl, "vIUiUi", "n")
+BUILTIN(__builtin_xtensa_mula_da_hh, "vIUiUi", "n")
+
+BUILTIN(__builtin_xtensa_mula_dd_ll, "vIUiIUi", "n")
+BUILTIN(__builtin_xtensa_mula_dd_lh, "vIUiIUi", "n")
+BUILTIN(__builtin_xtensa_mula_dd_hl, "vIUiIUi", "n")
+BUILTIN(__builtin_xtensa_mula_dd_hh, "vIUiIUi", "n")
+
+BUILTIN(__builtin_xtensa_muls_aa_ll, "vUiUi", "n")
+BUILTIN(__builtin_xtensa_muls_aa_lh, "vUiUi", "n")
+BUILTIN(__builtin_xtensa_muls_aa_hl, "vUiUi", "n")
+BUILTIN(__builtin_xtensa_muls_aa_hh, "vUiUi", "n")
+
+BUILTIN(__builtin_xtensa_muls_ad_ll, "vUiIUi", "n")
+BUILTIN(__builtin_xtensa_muls_ad_lh, "vUiIUi", "n")
+BUILTIN(__builtin_xtensa_muls_ad_hl, "vUiIUi", "n")
+BUILTIN(__builtin_xtensa_muls_ad_hh, "vUiIUi", "n")
+
+BUILTIN(__builtin_xtensa_muls_da_ll, "vIUiUi", "n")
+BUILTIN(__builtin_xtensa_muls_da_lh, "vIUiUi", "n")
+BUILTIN(__builtin_xtensa_muls_da_hl, "vIUiUi", "n")
+BUILTIN(__builtin_xtensa_muls_da_hh, "vIUiUi", "n")
+
+BUILTIN(__builtin_xtensa_muls_dd_ll, "vIUiIUi", "n")
+BUILTIN(__builtin_xtensa_muls_dd_lh, "vIUiIUi", "n")
+BUILTIN(__builtin_xtensa_muls_dd_hl, "vIUiIUi", "n")
+BUILTIN(__builtin_xtensa_muls_dd_hh, "vIUiIUi", "n")
+
+BUILTIN(__builtin_xtensa_mula_da_ll_lddec, "vIUii**IUii", "n")
+BUILTIN(__builtin_xtensa_mula_da_lh_lddec, "vIUii**IUii", "n")
+BUILTIN(__builtin_xtensa_mula_da_hl_lddec, "vIUii**IUii", "n")
+BUILTIN(__builtin_xtensa_mula_da_hh_lddec, "vIUii**IUii", "n")
+
+BUILTIN(__builtin_xtensa_mula_da_ll_ldinc, "vIUii**IUii", "n")
+BUILTIN(__builtin_xtensa_mula_da_lh_ldinc, "vIUii**IUii", "n")
+BUILTIN(__builtin_xtensa_mula_da_hl_ldinc, "vIUii**IUii", "n")
+BUILTIN(__builtin_xtensa_mula_da_hh_ldinc, "vIUii**IUii", "n")
+
+BUILTIN(__builtin_xtensa_mula_dd_ll_lddec, "vIUii**IUiIUi", "n")
+BUILTIN(__builtin_xtensa_mula_dd_lh_lddec, "vIUii**IUiIUi", "n")
+BUILTIN(__builtin_xtensa_mula_dd_hl_lddec, "vIUii**IUiIUi", "n")
+BUILTIN(__builtin_xtensa_mula_dd_hh_lddec, "vIUii**IUiIUi", "n")
+
+BUILTIN(__builtin_xtensa_mula_dd_ll_ldinc, "vIUii**IUiIUi", "n")
+BUILTIN(__builtin_xtensa_mula_dd_lh_ldinc, "vIUii**IUiIUi", "n")
+BUILTIN(__builtin_xtensa_mula_dd_hl_ldinc, "vIUii**IUiIUi", "n")
+BUILTIN(__builtin_xtensa_mula_dd_hh_ldinc, "vIUii**IUiIUi", "n")
+
+// Load operations
+
+BUILTIN(__builtin_xtensa_ldinc, "vIUii**", "n")
+BUILTIN(__builtin_xtensa_lddec, "vIUii**", "n")
+
+// WSR/RSR/XSR
+
+BUILTIN(__builtin_xtensa_wsr_acclo, "vUi", "n")
+BUILTIN(__builtin_xtensa_rsr_acclo, "Ui", "n")
+BUILTIN(__builtin_xtensa_xsr_acclo, "vUi*", "n")
+BUILTIN(__builtin_xtensa_wsr_acchi, "vUi", "n")
+BUILTIN(__builtin_xtensa_rsr_acchi, "Ui", "n")
+BUILTIN(__builtin_xtensa_xsr_acchi, "vUi*", "n")
+BUILTIN(__builtin_xtensa_wsr_m0, "vUi", "n")
+BUILTIN(__builtin_xtensa_rsr_m0, "Ui", "n")
+BUILTIN(__builtin_xtensa_xsr_m0, "vUi*", "n")
+BUILTIN(__builtin_xtensa_wsr_m1, "vUi", "n")
+BUILTIN(__builtin_xtensa_rsr_m1, "Ui", "n")
+BUILTIN(__builtin_xtensa_xsr_m1, "vUi*", "n")
+BUILTIN(__builtin_xtensa_wsr_m2, "vUi", "n")
+BUILTIN(__builtin_xtensa_rsr_m2, "Ui", "n")
+BUILTIN(__builtin_xtensa_xsr_m2, "vUi*", "n")
+BUILTIN(__builtin_xtensa_wsr_m3, "vUi", "n")
+BUILTIN(__builtin_xtensa_rsr_m3, "Ui", "n")
+BUILTIN(__builtin_xtensa_xsr_m3, "vUi*", "n")
+
+#undef BUILTIN
\ No newline at end of file
diff --git a/clang/include/clang/Basic/TargetBuiltins.h b/clang/include/clang/Basic/TargetBuiltins.h
index 2f94e839768c..6d8c28886ad6 100644
--- a/clang/include/clang/Basic/TargetBuiltins.h
+++ b/clang/include/clang/Basic/TargetBuiltins.h
@@ -347,6 +347,16 @@ namespace clang {
};
}
+ /// Xtensa builtins
+ namespace Xtensa {
+ enum {
+ LastTIBuiltin = clang::Builtin::FirstTSBuiltin - 1,
+#define BUILTIN(ID, TYPE, ATTRS) BI##ID,
+#include "clang/Basic/BuiltinsXtensa.def"
+ LastTSBuiltin
+ };
+ } // namespace Xtensa
+
static constexpr uint64_t LargestBuiltinID = std::max<uint64_t>(
{ARM::LastTSBuiltin, AArch64::LastTSBuiltin, BPF::LastTSBuiltin,
PPC::LastTSBuiltin, NVPTX::LastTSBuiltin, AMDGPU::LastTSBuiltin,
diff --git a/clang/lib/Basic/Targets/Xtensa.cpp b/clang/lib/Basic/Targets/Xtensa.cpp
index 270af0a05cfd..2fb0474801b6 100644
--- a/clang/lib/Basic/Targets/Xtensa.cpp
+++ b/clang/lib/Basic/Targets/Xtensa.cpp
@@ -20,6 +20,12 @@
using namespace clang;
using namespace clang::targets;
+const Builtin::Info XtensaTargetInfo::BuiltinInfo[] = {
+#define BUILTIN(ID, TYPE, ATTRS) \
+ {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
+#include "clang/Basic/BuiltinsXtensa.def"
+};
+
void XtensaTargetInfo::getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const {
Builder.defineMacro("__Xtensa__");
@@ -27,3 +33,8 @@ void XtensaTargetInfo::getTargetDefines(const LangOptions &Opts,
Builder.defineMacro("__XTENSA__");
Builder.defineMacro("__XTENSA_EL__");
}
+
+ArrayRef<Builtin::Info> XtensaTargetInfo::getTargetBuiltins() const {
+ return llvm::makeArrayRef(BuiltinInfo, clang::Xtensa::LastTSBuiltin -
+ Builtin::FirstTSBuiltin);
+}
diff --git a/clang/lib/Basic/Targets/Xtensa.h b/clang/lib/Basic/Targets/Xtensa.h
index 188b2dc803cc..981edf5cb280 100644
--- a/clang/lib/Basic/Targets/Xtensa.h
+++ b/clang/lib/Basic/Targets/Xtensa.h
@@ -53,7 +53,7 @@ public:
void getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const override;
- ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
+ ArrayRef<Builtin::Info> getTargetBuiltins() const override;
BuiltinVaListKind getBuiltinVaListKind() const override {
diff --git a/llvm/include/llvm/IR/CMakeLists.txt b/llvm/include/llvm/IR/CMakeLists.txt
index 468d663796ed..83e98c8fd7c9 100644
--- a/llvm/include/llvm/IR/CMakeLists.txt
+++ b/llvm/include/llvm/IR/CMakeLists.txt
@@ -21,5 +21,6 @@ tablegen(LLVM IntrinsicsS390.h -gen-intrinsic-enums -intrinsic-prefix=s390)
tablegen(LLVM IntrinsicsWebAssembly.h -gen-intrinsic-enums -intrinsic-prefix=wasm)
tablegen(LLVM IntrinsicsX86.h -gen-intrinsic-enums -intrinsic-prefix=x86)
tablegen(LLVM IntrinsicsXCore.h -gen-intrinsic-enums -intrinsic-prefix=xcore)
+tablegen(LLVM IntrinsicsXtensa.h -gen-intrinsic-enums -intrinsic-prefix=xtensa)
tablegen(LLVM IntrinsicsVE.h -gen-intrinsic-enums -intrinsic-prefix=ve)
add_public_tablegen_target(intrinsics_gen)
diff --git a/llvm/include/llvm/IR/IntrinsicsXtensa.td b/llvm/include/llvm/IR/IntrinsicsXtensa.td
new file mode 100644
index 000000000000..d7d25609b5d5
--- /dev/null
+++ b/llvm/include/llvm/IR/IntrinsicsXtensa.td
@@ -0,0 +1,251 @@
+//===- IntrinsicsXtensa.td - Defines Xtensa intrinsics -----*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines all of the Xtensa-specific intrinsics.
+//
+//===----------------------------------------------------------------------===//
+
+let TargetPrefix = "xtensa" in { // All intrinsics start with "llvm.xtensa.".
+
+def int_xtensa_umul_aa_ll: ClangBuiltin<"__builtin_xtensa_umul_aa_ll">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>;
+def int_xtensa_umul_aa_hl: ClangBuiltin<"__builtin_xtensa_umul_aa_hl">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>;
+def int_xtensa_umul_aa_lh: ClangBuiltin<"__builtin_xtensa_umul_aa_lh">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>;
+def int_xtensa_umul_aa_hh: ClangBuiltin<"__builtin_xtensa_umul_aa_hh">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>;
+
+def int_xtensa_mul_aa_ll: ClangBuiltin<"__builtin_xtensa_mul_aa_ll">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>;
+def int_xtensa_mul_aa_hl: ClangBuiltin<"__builtin_xtensa_mul_aa_hl">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>;
+def int_xtensa_mul_aa_lh: ClangBuiltin<"__builtin_xtensa_mul_aa_lh">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>;
+def int_xtensa_mul_aa_hh: ClangBuiltin<"__builtin_xtensa_mul_aa_hh">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>;
+
+def int_xtensa_mul_ad_ll: ClangBuiltin<"__builtin_xtensa_mul_ad_ll">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<1>>]>;
+def int_xtensa_mul_ad_hl: ClangBuiltin<"__builtin_xtensa_mul_ad_hl">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<1>>]>;
+def int_xtensa_mul_ad_lh: ClangBuiltin<"__builtin_xtensa_mul_ad_lh">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<1>>]>;
+def int_xtensa_mul_ad_hh: ClangBuiltin<"__builtin_xtensa_mul_ad_hh">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<1>>]>;
+
+def int_xtensa_mul_da_ll: ClangBuiltin<"__builtin_xtensa_mul_da_ll">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
+def int_xtensa_mul_da_hl: ClangBuiltin<"__builtin_xtensa_mul_da_hl">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
+def int_xtensa_mul_da_lh: ClangBuiltin<"__builtin_xtensa_mul_da_lh">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
+def int_xtensa_mul_da_hh: ClangBuiltin<"__builtin_xtensa_mul_da_hh">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
+
+def int_xtensa_mul_dd_ll: ClangBuiltin<"__builtin_xtensa_mul_dd_ll">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
+def int_xtensa_mul_dd_hl: ClangBuiltin<"__builtin_xtensa_mul_dd_hl">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
+def int_xtensa_mul_dd_lh: ClangBuiltin<"__builtin_xtensa_mul_dd_lh">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
+def int_xtensa_mul_dd_hh: ClangBuiltin<"__builtin_xtensa_mul_dd_hh">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
+
+def int_xtensa_mula_aa_ll: ClangBuiltin<"__builtin_xtensa_mula_aa_ll">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>;
+def int_xtensa_mula_aa_hl: ClangBuiltin<"__builtin_xtensa_mula_aa_hl">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>;
+def int_xtensa_mula_aa_lh: ClangBuiltin<"__builtin_xtensa_mula_aa_lh">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>;
+def int_xtensa_mula_aa_hh: ClangBuiltin<"__builtin_xtensa_mula_aa_hh">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>;
+
+def int_xtensa_mula_ad_ll: ClangBuiltin<"__builtin_xtensa_mula_ad_ll">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<1>>]>;
+def int_xtensa_mula_ad_hl: ClangBuiltin<"__builtin_xtensa_mula_ad_hl">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<1>>]>;
+def int_xtensa_mula_ad_lh: ClangBuiltin<"__builtin_xtensa_mula_ad_lh">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<1>>]>;
+def int_xtensa_mula_ad_hh: ClangBuiltin<"__builtin_xtensa_mula_ad_hh">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<1>>]>;
+
+def int_xtensa_mula_da_ll: ClangBuiltin<"__builtin_xtensa_mula_da_ll">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
+def int_xtensa_mula_da_hl: ClangBuiltin<"__builtin_xtensa_mula_da_hl">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
+def int_xtensa_mula_da_lh: ClangBuiltin<"__builtin_xtensa_mula_da_lh">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
+def int_xtensa_mula_da_hh: ClangBuiltin<"__builtin_xtensa_mula_da_hh">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
+
+def int_xtensa_mula_dd_ll: ClangBuiltin<"__builtin_xtensa_mula_dd_ll">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
+def int_xtensa_mula_dd_hl: ClangBuiltin<"__builtin_xtensa_mula_dd_hl">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
+def int_xtensa_mula_dd_lh: ClangBuiltin<"__builtin_xtensa_mula_dd_lh">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
+def int_xtensa_mula_dd_hh: ClangBuiltin<"__builtin_xtensa_mula_dd_hh">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
+
+def int_xtensa_muls_aa_ll: ClangBuiltin<"__builtin_xtensa_muls_aa_ll">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>;
+def int_xtensa_muls_aa_hl: ClangBuiltin<"__builtin_xtensa_muls_aa_hl">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>;
+def int_xtensa_muls_aa_lh: ClangBuiltin<"__builtin_xtensa_muls_aa_lh">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>;
+def int_xtensa_muls_aa_hh: ClangBuiltin<"__builtin_xtensa_muls_aa_hh">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>;
+
+def int_xtensa_muls_ad_ll: ClangBuiltin<"__builtin_xtensa_muls_ad_ll">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<1>>]>;
+def int_xtensa_muls_ad_hl: ClangBuiltin<"__builtin_xtensa_muls_ad_hl">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<1>>]>;
+def int_xtensa_muls_ad_lh: ClangBuiltin<"__builtin_xtensa_muls_ad_lh">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<1>>]>;
+def int_xtensa_muls_ad_hh: ClangBuiltin<"__builtin_xtensa_muls_ad_hh">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<1>>]>;
+
+def int_xtensa_muls_da_ll: ClangBuiltin<"__builtin_xtensa_muls_da_ll">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
+def int_xtensa_muls_da_hl: ClangBuiltin<"__builtin_xtensa_muls_da_hl">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
+def int_xtensa_muls_da_lh: ClangBuiltin<"__builtin_xtensa_muls_da_lh">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
+def int_xtensa_muls_da_hh: ClangBuiltin<"__builtin_xtensa_muls_da_hh">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
+
+def int_xtensa_muls_dd_ll: ClangBuiltin<"__builtin_xtensa_muls_dd_ll">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
+def int_xtensa_muls_dd_hl: ClangBuiltin<"__builtin_xtensa_muls_dd_hl">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
+def int_xtensa_muls_dd_lh: ClangBuiltin<"__builtin_xtensa_muls_dd_lh">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
+def int_xtensa_muls_dd_hh: ClangBuiltin<"__builtin_xtensa_muls_dd_hh">,
+ Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
+
+
+def int_xtensa_mula_da_ll_lddec: ClangBuiltin<"__builtin_xtensa_mula_da_ll_lddec">,
+ Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
+ [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>;
+def int_xtensa_mula_da_lh_lddec: ClangBuiltin<"__builtin_xtensa_mula_da_lh_lddec">,
+ Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
+ [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>;
+def int_xtensa_mula_da_hl_lddec: ClangBuiltin<"__builtin_xtensa_mula_da_hl_lddec">,
+ Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
+ [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>;
+def int_xtensa_mula_da_hh_lddec: ClangBuiltin<"__builtin_xtensa_mula_da_hh_lddec">,
+ Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
+ [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>;
+
+def int_xtensa_mula_da_ll_ldinc: ClangBuiltin<"__builtin_xtensa_mula_da_ll_ldinc">,
+ Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
+ [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>;
+def int_xtensa_mula_da_lh_ldinc: ClangBuiltin<"__builtin_xtensa_mula_da_lh_ldinc">,
+ Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
+ [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>;
+def int_xtensa_mula_da_hl_ldinc: ClangBuiltin<"__builtin_xtensa_mula_da_hl_ldinc">,
+ Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
+ [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>;
+def int_xtensa_mula_da_hh_ldinc: ClangBuiltin<"__builtin_xtensa_mula_da_hh_ldinc">,
+ Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
+ [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>;
+
+def int_xtensa_mula_dd_ll_lddec: ClangBuiltin<"__builtin_xtensa_mula_dd_ll_lddec">,
+ Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
+ [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>;
+def int_xtensa_mula_dd_lh_lddec: ClangBuiltin<"__builtin_xtensa_mula_dd_lh_lddec">,
+ Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
+ [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>;
+def int_xtensa_mula_dd_hl_lddec: ClangBuiltin<"__builtin_xtensa_mula_dd_hl_lddec">,
+ Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
+ [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>;
+def int_xtensa_mula_dd_hh_lddec: ClangBuiltin<"__builtin_xtensa_mula_dd_hh_lddec">,
+ Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
+ [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>;
+
+def int_xtensa_mula_dd_ll_ldinc: ClangBuiltin<"__builtin_xtensa_mula_dd_ll_ldinc">,
+ Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
+ [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>;
+def int_xtensa_mula_dd_lh_ldinc: ClangBuiltin<"__builtin_xtensa_mula_dd_lh_ldinc">,
+ Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
+ [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>;
+def int_xtensa_mula_dd_hl_ldinc: ClangBuiltin<"__builtin_xtensa_mula_dd_hl_ldinc">,
+ Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
+ [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>;
+def int_xtensa_mula_dd_hh_ldinc: ClangBuiltin<"__builtin_xtensa_mula_dd_hh_ldinc">,
+ Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
+ [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>;
+
+//===----------------------------------------------------------------------===//
+// Load operations
+
+def int_xtensa_lddec: ClangBuiltin<"__builtin_xtensa_lddec">,
+ Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty], [ImmArg<ArgIndex<0>>]>;
+
+def int_xtensa_ldinc: ClangBuiltin<"__builtin_xtensa_ldinc">,
+ Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty], [ImmArg<ArgIndex<0>>]>;
+
+//===----------------------------------------------------------------------===//
+// WSR/XSR/RSR
+
+def int_xtensa_wsr_acclo: ClangBuiltin<"__builtin_xtensa_wsr_acclo">,
+ Intrinsic<[], [llvm_i32_ty], []>;
+
+def int_xtensa_rsr_acclo: ClangBuiltin<"__builtin_xtensa_rsr_acclo">,
+ Intrinsic<[llvm_i32_ty], [], []>;
+
+def int_xtensa_xsr_acclo: ClangBuiltin<"__builtin_xtensa_xsr_acclo">,
+ Intrinsic<[], [llvm_ptr_ty], []>;
+
+def int_xtensa_wsr_acchi: ClangBuiltin<"__builtin_xtensa_wsr_acchi">,
+ Intrinsic<[], [llvm_i32_ty], []>;
+
+def int_xtensa_rsr_acchi: ClangBuiltin<"__builtin_xtensa_rsr_acchi">,
+ Intrinsic<[llvm_i32_ty], [], []>;
+
+def int_xtensa_xsr_acchi: ClangBuiltin<"__builtin_xtensa_xsr_acchi">,
+ Intrinsic<[], [llvm_ptr_ty], []>;
+
+def int_xtensa_wsr_m0: ClangBuiltin<"__builtin_xtensa_wsr_m0">,
+ Intrinsic<[], [llvm_i32_ty], []>;
+
+def int_xtensa_rsr_m0: ClangBuiltin<"__builtin_xtensa_rsr_m0">,
+ Intrinsic<[llvm_i32_ty]>;
+
+def int_xtensa_xsr_m0: ClangBuiltin<"__builtin_xtensa_xsr_m0">,
+ Intrinsic<[], [llvm_ptr_ty], []>;
+
+def int_xtensa_wsr_m1: ClangBuiltin<"__builtin_xtensa_wsr_m1">,
+ Intrinsic<[], [llvm_i32_ty], []>;
+
+def int_xtensa_rsr_m1: ClangBuiltin<"__builtin_xtensa_rsr_m1">,
+ Intrinsic<[llvm_i32_ty], [], []>;
+
+def int_xtensa_xsr_m1: ClangBuiltin<"__builtin_xtensa_xsr_m1">,
+ Intrinsic<[], [llvm_ptr_ty], []>;
+
+def int_xtensa_wsr_m2: ClangBuiltin<"__builtin_xtensa_wsr_m2">,
+ Intrinsic<[], [llvm_i32_ty], []>;
+
+def int_xtensa_rsr_m2: ClangBuiltin<"__builtin_xtensa_rsr_m2">,
+ Intrinsic<[llvm_i32_ty], [], []>;
+
+def int_xtensa_xsr_m2: ClangBuiltin<"__builtin_xtensa_xsr_m2">,
+ Intrinsic<[], [llvm_ptr_ty], []>;
+
+def int_xtensa_wsr_m3: ClangBuiltin<"__builtin_xtensa_wsr_m3">,
+ Intrinsic<[], [llvm_i32_ty], []>;
+
+def int_xtensa_rsr_m3: ClangBuiltin<"__builtin_xtensa_rsr_m3">,
+ Intrinsic<[llvm_i32_ty], [], []>;
+
+def int_xtensa_xsr_m3: ClangBuiltin<"__builtin_xtensa_xsr_m3">,
+ Intrinsic<[], [llvm_ptr_ty], []>;
+
+}
diff --git a/llvm/lib/IR/Function.cpp b/llvm/lib/IR/Function.cpp
index 677db46124e4..367c4f6af98a 100644
--- a/llvm/lib/IR/Function.cpp
+++ b/llvm/lib/IR/Function.cpp
@@ -47,6 +47,7 @@
#include "llvm/IR/IntrinsicsWebAssembly.h"
#include "llvm/IR/IntrinsicsX86.h"
#include "llvm/IR/IntrinsicsXCore.h"
+#include "llvm/IR/IntrinsicsXtensa.h"
#include "llvm/IR/LLVMContext.h"
#include "llvm/IR/MDBuilder.h"
#include "llvm/IR/Metadata.h"
diff --git a/llvm/lib/Target/Xtensa/XtensaDSPInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaDSPInstrInfo.td
index d80df4632064..aec66efd8d2f 100644
--- a/llvm/lib/Target/Xtensa/XtensaDSPInstrInfo.td
+++ b/llvm/lib/Target/Xtensa/XtensaDSPInstrInfo.td
@@ -13,29 +13,31 @@
//===----------------------------------------------------------------------===//
// Multiply
-class UMUL_AA<bits<4> oper1, string instrAsm>
+class UMUL_AA<bits<4> oper1, string instrAsm, SDPatternOperator opNode>
: RRR_Inst<0x04, oper1, 0x07, (outs), (ins AR:$s, AR:$t),
- instrAsm#"\t$s, $t", []>, Requires<[HasMAC16]> {
+ instrAsm#"\t$s, $t",
+ [(opNode AR:$s, AR:$t)]>, Requires<[HasMAC16]> {
let r = 0;
let Defs = [M1, M2, ACCLO, ACCHI];
}
-def UMUL_AA_LL : UMUL_AA<0x00, "umul.aa.ll">;
-def UMUL_AA_HL : UMUL_AA<0x01, "umul.aa.hl">;
-def UMUL_AA_LH : UMUL_AA<0x02, "umul.aa.lh">;
-def UMUL_AA_HH : UMUL_AA<0x03, "umul.aa.hh">;
+def UMUL_AA_LL : UMUL_AA<0x00, "umul.aa.ll", int_xtensa_umul_aa_ll>;
+def UMUL_AA_HL : UMUL_AA<0x01, "umul.aa.hl", int_xtensa_umul_aa_hl>;
+def UMUL_AA_LH : UMUL_AA<0x02, "umul.aa.lh", int_xtensa_umul_aa_lh>;
+def UMUL_AA_HH : UMUL_AA<0x03, "umul.aa.hh", int_xtensa_umul_aa_hh>;
-class MUL_AA<bits<4> oper1, string instrAsm>
+class MUL_AA<bits<4> oper1, string instrAsm, SDPatternOperator opNode>
: RRR_Inst<0x04, oper1, 0x07, (outs), (ins AR:$s, AR:$t),
- instrAsm#"\t$s, $t", []>, Requires<[HasMAC16]> {
+ instrAsm#"\t$s, $t",
+ [(opNode AR:$s, AR:$t)]>, Requires<[HasMAC16]> {
let r = 0;
let Defs = [M1, M2, ACCLO, ACCHI];
}
-def MUL_AA_LL : MUL_AA<0x04, "mul.aa.ll">;
-def MUL_AA_HL : MUL_AA<0x05, "mul.aa.hl">;
-def MUL_AA_LH : MUL_AA<0x06, "mul.aa.lh">;
-def MUL_AA_HH : MUL_AA<0x07, "mul.aa.hh">;
+def MUL_AA_LL : MUL_AA<0x04, "mul.aa.ll", int_xtensa_mul_aa_ll>;
+def MUL_AA_HL : MUL_AA<0x05, "mul.aa.hl", int_xtensa_mul_aa_hl>;
+def MUL_AA_LH : MUL_AA<0x06, "mul.aa.lh", int_xtensa_mul_aa_lh>;
+def MUL_AA_HH : MUL_AA<0x07, "mul.aa.hh", int_xtensa_mul_aa_hh>;
class MUL_AD<bits<4> oper1, string instrAsm>
: RRR_Inst<0x04, oper1, 0x03, (outs), (ins AR:$s, MR23:$y),
@@ -92,17 +94,18 @@ def MUL_DD_HL : MUL_DD<0x05, "mul.dd.hl">;
def MUL_DD_LH : MUL_DD<0x06, "mul.dd.lh">;
def MUL_DD_HH : MUL_DD<0x07, "mul.dd.hh">;
-class MULA_AA<bits<4> oper1, string instrAsm>
+class MULA_AA<bits<4> oper1, string instrAsm, SDPatternOperator opNode>
: RRR_Inst<0x04, oper1, 0x07, (outs), (ins AR:$s, AR:$t),
- instrAsm#"\t$s, $t", []>, Requires<[HasMAC16]> {
+ instrAsm#"\t$s, $t",
+ [(opNode AR:$s, AR:$t)]>, Requires<[HasMAC16]> {
let r = 0;
let Defs = [M1, M2, ACCLO, ACCHI];
}
-def MULA_AA_LL : MULA_AA<0x08, "mula.aa.ll">;
-def MULA_AA_HL : MULA_AA<0x09, "mula.aa.hl">;
-def MULA_AA_LH : MULA_AA<0x0A, "mula.aa.lh">;
-def MULA_AA_HH : MULA_AA<0x0B, "mula.aa.hh">;
+def MULA_AA_LL : MULA_AA<0x08, "mula.aa.ll", int_xtensa_mula_aa_ll>;
+def MULA_AA_HL : MULA_AA<0x09, "mula.aa.hl", int_xtensa_mula_aa_hl>;
+def MULA_AA_LH : MULA_AA<0x0A, "mula.aa.lh", int_xtensa_mula_aa_lh>;
+def MULA_AA_HH : MULA_AA<0x0B, "mula.aa.hh", int_xtensa_mula_aa_hh>;
class MULA_AD<bits<4> oper1, string instrAsm>
: RRR_Inst<0x04, oper1, 0x03, (outs), (ins AR:$s, MR23:$y),
@@ -165,18 +168,19 @@ def MULA_DD_HL : MULA_DD<0x09, "mula.dd.hl">;
def MULA_DD_LH : MULA_DD<0x0A, "mula.dd.lh">;
def MULA_DD_HH : MULA_DD<0x0B, "mula.dd.hh">;
-class MULS_AA<bits<4> oper1, string instrAsm>
+class MULS_AA<bits<4> oper1, string instrAsm, SDPatternOperator opNode>
: RRR_Inst<0x04, oper1, 0x07, (outs), (ins AR:$s, AR:$t),
- instrAsm#"\t$s, $t", []>, Requires<[HasMAC16]> {
+ instrAsm#"\t$s, $t",
+ [(opNode AR:$s, AR:$t)]>, Requires<[HasMAC16]> {
let r = 0;
let Uses = [ACCLO, ACCHI];
let Defs = [M1, M2, ACCLO, ACCHI];
}
-def MULS_AA_LL : MULS_AA<0x0C, "muls.aa.ll">;
-def MULS_AA_HL : MULS_AA<0x0D, "muls.aa.hl">;
-def MULS_AA_LH : MULS_AA<0x0E, "muls.aa.lh">;
-def MULS_AA_HH : MULS_AA<0x0F, "muls.aa.hh">;
+def MULS_AA_LL : MULS_AA<0x0C, "muls.aa.ll", int_xtensa_muls_aa_ll>;
+def MULS_AA_HL : MULS_AA<0x0D, "muls.aa.hl", int_xtensa_muls_aa_hl>;
+def MULS_AA_LH : MULS_AA<0x0E, "muls.aa.lh", int_xtensa_muls_aa_lh>;
+def MULS_AA_HH : MULS_AA<0x0F, "muls.aa.hh", int_xtensa_muls_aa_hh>;
class MULS_AD<bits<4> oper1, string instrAsm>
: RRR_Inst<0x04, oper1, 0x03, (outs), (ins AR:$s, MR23:$y),
@@ -262,6 +266,21 @@ def MULA_DA_HL_LDDEC : MULA_DA_LDDEC<0x09, "mula.da.hl.lddec">;
def MULA_DA_LH_LDDEC : MULA_DA_LDDEC<0x0A, "mula.da.lh.lddec">;
def MULA_DA_HH_LDDEC : MULA_DA_LDDEC<0x0B, "mula.da.hh.lddec">;
+let usesCustomInserter = 1, Predicates = [HasMAC16] in {
+ def MULA_DA_LL_LDDEC_P : Pseudo<(outs), (ins imm8:$mw, AR:$s, imm8:$mx, AR:$t),
+ "!xtensa_mula_da_ll_lddec_p, $mw, $s, $mx, $t",
+ [(int_xtensa_mula_da_ll_lddec timm:$mw, AR:$s, timm:$mx, AR:$t)]>;
+ def MULA_DA_HL_LDDEC_P : Pseudo<(outs), (ins imm8:$mw, AR:$s, imm8:$mx, AR:$t),
+ "!xtensa_mula_da_hl_lddec_p, $mw, $s, $mx, $t",
+ [(int_xtensa_mula_da_hl_lddec timm:$mw, AR:$s, timm:$mx, AR:$t)]>;
+ def MULA_DA_LH_LDDEC_P : Pseudo<(outs), (ins imm8:$mw, AR:$s, imm8:$mx, AR:$t),
+ "!xtensa_mula_da_lh_lddec_p, $mw, $s, $mx, $t",
+ [(int_xtensa_mula_da_lh_lddec timm:$mw, AR:$s, timm:$mx, AR:$t)]>;
+ def MULA_DA_HH_LDDEC_P : Pseudo<(outs), (ins imm8:$mw, AR:$s, imm8:$mx, AR:$t),
+ "!xtensa_mula_da_hh_lddec_p, $mw, $s, $mx, $t",
+ [(int_xtensa_mula_da_hh_lddec timm:$mw, AR:$s, timm:$mx, AR:$t)]>;
+}
+
class MULA_DA_LDINC<bits<4> oper1, string instrAsm>
: RRR_Inst<0x04, oper1, 0x04, (outs MR:$w, AR:$d), (ins AR:$s, MR:$x, AR:$t),
instrAsm#"\t $w, $s, $x, $t", []>, Requires<[HasMAC16]> {
@@ -277,10 +296,25 @@ class MULA_DA_LDINC<bits<4> oper1, string instrAsm>
let Defs = [M1, M2, ACCLO, ACCHI];
}
-def MULA_DA_LL_LDINC: MULA_DA_LDINC<0x08, "mula.da.ll.ldinc">;
-def MULA_DA_HL_LDINC: MULA_DA_LDINC<0x09, "mula.da.hl.ldinc">;
-def MULA_DA_LH_LDINC: MULA_DA_LDINC<0x0A, "mula.da.lh.ldinc">;
-def MULA_DA_HH_LDINC: MULA_DA_LDINC<0x0B, "mula.da.hh.ldinc">;
+def MULA_DA_LL_LDINC : MULA_DA_LDINC<0x08, "mula.da.ll.ldinc">;
+def MULA_DA_HL_LDINC : MULA_DA_LDINC<0x09, "mula.da.hl.ldinc">;
+def MULA_DA_LH_LDINC : MULA_DA_LDINC<0x0A, "mula.da.lh.ldinc">;
+def MULA_DA_HH_LDINC : MULA_DA_LDINC<0x0B, "mula.da.hh.ldinc">;
+
+let usesCustomInserter = 1, Predicates = [HasMAC16] in {
+ def MULA_DA_LL_LDINC_P : Pseudo<(outs), (ins imm8:$mw, AR:$s, imm8:$mx, AR:$t),
+ "!xtensa_mula_da_ll_ldinc_p, $mw, $s, $mx, $t",
+ [(int_xtensa_mula_da_ll_ldinc timm:$mw, AR:$s, timm:$mx, AR:$t)]>;
+ def MULA_DA_HL_LDINC_P : Pseudo<(outs), (ins imm8:$mw, AR:$s, imm8:$mx, AR:$t),
+ "!xtensa_mula_da_hl_ldinc_p, $mw, $s, $mx, $t",
+ [(int_xtensa_mula_da_hl_ldinc timm:$mw, AR:$s, timm:$mx, AR:$t)]>;
+ def MULA_DA_LH_LDINC_P : Pseudo<(outs), (ins imm8:$mw, AR:$s, imm8:$mx, AR:$t),
+ "!xtensa_mula_da_lh_ldinc_p, $mw, $s, $mx, $t",
+ [(int_xtensa_mula_da_lh_ldinc timm:$mw, AR:$s, timm:$mx, AR:$t)]>;
+ def MULA_DA_HH_LDINC_P : Pseudo<(outs), (ins imm8:$mw, AR:$s, imm8:$mx, AR:$t),
+ "!xtensa_mula_da_hh_ldinc_p, $mw, $s, $mx, $t",
+ [(int_xtensa_mula_da_hh_ldinc timm:$mw, AR:$s, timm:$mx, AR:$t)]>;
+}
class MULA_DD_LDDEC<bits<4> oper1, string instrAsm>
: RRR_Inst<0x04, oper1, 0x01, (outs MR:$w, AR:$d), (ins AR:$s, MR01:$x, MR23:$y),
@@ -306,6 +340,21 @@ def MULA_DD_HL_LDDEC : MULA_DD_LDDEC<0x09, "mula.dd.hl.lddec">;
def MULA_DD_LH_LDDEC : MULA_DD_LDDEC<0x0A, "mula.dd.lh.lddec">;
def MULA_DD_HH_LDDEC : MULA_DD_LDDEC<0x0B, "mula.dd.hh.lddec">;
+let usesCustomInserter = 1, Predicates = [HasMAC16] in {
+ def MULA_DD_LL_LDDEC_P : Pseudo<(outs), (ins imm8:$mw, AR:$s, imm8:$mx, imm8:$my),
+ "!xtensa_mula_dd_ll_lddec_p, $mw, $s, $mx, $my",
+ [(int_xtensa_mula_dd_ll_lddec timm:$mw, AR:$s, timm:$mx, timm:$my)]>;
+ def MULA_DD_HL_LDDEC_P : Pseudo<(outs), (ins imm8:$mw, AR:$s, imm8:$mx, imm8:$my),
+ "!xtensa_mula_dd_hl_lddec_p, $mw, $s, $mx, $my",
+ [(int_xtensa_mula_dd_hl_lddec timm:$mw, AR:$s, timm:$mx, timm:$my)]>;
+ def MULA_DD_LH_LDDEC_P : Pseudo<(outs), (ins imm8:$mw, AR:$s, imm8:$mx, imm8:$my),
+ "!xtensa_mula_dd_lh_lddec_p, $mw, $s, $mx, $my",
+ [(int_xtensa_mula_dd_lh_lddec timm:$mw, AR:$s, timm:$mx, timm:$my)]>;
+ def MULA_DD_HH_LDDEC_P : Pseudo<(outs), (ins imm8:$mw, AR:$s, imm8:$mx, imm8:$my),
+ "!xtensa_mula_dd_hh_lddec_p, $mw, $s, $mx, $my",
+ [(int_xtensa_mula_dd_hh_lddec timm:$mw, AR:$s, timm:$mx, timm:$my)]>;
+}
+
class MULA_DD_LDINC<bits<4> oper1, string instrAsm>
: RRR_Inst<0x04, oper1, 0x00, (outs MR:$w, AR:$d), (ins AR:$s, MR01:$x, MR23:$y),
instrAsm#"\t $w, $s, $x, $y", []>, Requires<[HasMAC16]> {
@@ -330,6 +379,21 @@ def MULA_DD_HL_LDINC : MULA_DD_LDINC<0x09, "mula.dd.hl.ldinc">;
def MULA_DD_LH_LDINC : MULA_DD_LDINC<0x0A, "mula.dd.lh.ldinc">;
def MULA_DD_HH_LDINC : MULA_DD_LDINC<0x0B, "mula.dd.hh.ldinc">;
+let usesCustomInserter = 1, Predicates = [HasMAC16] in {
+ def MULA_DD_LL_LDINC_P : Pseudo<(outs), (ins imm8:$mw, AR:$s, imm8:$mx, imm8:$my),
+ "!xtensa_mula_dd_ll_ldinc_p, $mw, $s, $mx, $my",
+ [(int_xtensa_mula_dd_ll_ldinc timm:$mw, AR:$s, timm:$mx, timm:$my)]>;
+ def MULA_DD_HL_LDINC_P : Pseudo<(outs), (ins imm8:$mw, AR:$s, imm8:$mx, imm8:$my),
+ "!xtensa_mula_dd_hl_ldinc_p, $mw, $s, $mx, $my",
+ [(int_xtensa_mula_dd_hl_ldinc timm:$mw, AR:$s, timm:$mx, timm:$my)]>;
+ def MULA_DD_LH_LDINC_P : Pseudo<(outs), (ins imm8:$mw, AR:$s, imm8:$mx, imm8:$my),
+ "!xtensa_mula_dd_lh_ldinc_p, $mw, $s, $mx, $my",
+ [(int_xtensa_mula_dd_lh_ldinc timm:$mw, AR:$s, timm:$mx, timm:$my)]>;
+ def MULA_DD_HH_LDINC_P : Pseudo<(outs), (ins imm8:$mw, AR:$s, imm8:$mx, imm8:$my),
+ "!xtensa_mula_dd_hh_ldinc_p, $mw, $s, $mx, $my",
+ [(int_xtensa_mula_dd_hh_ldinc timm:$mw, AR:$s, timm:$mx, timm:$my)]>;
+}
+
def LDDEC : RRR_Inst<0x04, 0x00, 0x09, (outs MR:$w, AR:$d), (ins AR:$s),
"lddec\t $w, $s", []>, Requires<[HasMAC16]> {
bits<2> w;
@@ -351,3 +415,58 @@ def LDINC : RRR_Inst<0x04, 0x00, 0x08, (outs MR:$w, AR:$d), (ins AR:$s),
let r{1-0} = w{1-0};
let t = 0;
}
+
+let usesCustomInserter = 1, Predicates = [HasMAC16] in {
+ def LDDEC_P : Pseudo<(outs), (ins imm8:$mw, AR:$s),
+ "!xtensa_lddec_p, $mw, $s",
+ [(int_xtensa_lddec timm:$mw, AR:$s)]>;
+ def LDINC_P : Pseudo<(outs), (ins imm8:$mw, AR:$s),
+ "!xtensa_ldinc_p, $mw, $s",
+ [(int_xtensa_ldinc timm:$mw, AR:$s)]>;
+}
+
+def : Pat<(i32 (int_xtensa_rsr_acclo)), (RSR ACCLO)>;
+def : Pat<(i32 (int_xtensa_rsr_acchi)), (RSR ACCHI)>;
+def : Pat<(i32 (int_xtensa_rsr_m0)), (RSR M0)>;
+def : Pat<(i32 (int_xtensa_rsr_m1)), (RSR M1)>;
+def : Pat<(i32 (int_xtensa_rsr_m2)), (RSR M2)>;
+def : Pat<(i32 (int_xtensa_rsr_m3)), (RSR M3)>;
+
+let usesCustomInserter = 1, Predicates = [HasMAC16] in {
+ def XSR_ACCLO_P : Pseudo<(outs), (ins AR:$s),
+ "!xtensa_xsr_acclo_p, $s",
+ [(int_xtensa_xsr_acclo AR:$s)]>;
+ def XSR_ACCHI_P : Pseudo<(outs), (ins AR:$s),
+ "!xtensa_xsr_acchi_p, $s",
+ [(int_xtensa_xsr_acchi AR:$s)]>;
+ def XSR_M0_P : Pseudo<(outs), (ins AR:$s),
+ "!xtensa_xsr_m0_p, $s",
+ [(int_xtensa_xsr_m0 AR:$s)]>;
+ def XSR_M1_P : Pseudo<(outs), (ins AR:$s),
+ "!xtensa_xsr_m1_p, $s",
+ [(int_xtensa_xsr_m1 AR:$s)]>;
+ def XSR_M2_P : Pseudo<(outs), (ins AR:$s),
+ "!xtensa_xsr_m2_p, $s",
+ [(int_xtensa_xsr_m2 AR:$s)]>;
+ def XSR_M3_P : Pseudo<(outs), (ins AR:$s),
+ "!xtensa_xsr_m3_p, $s",
+ [(int_xtensa_xsr_m3 AR:$s)]>;
+ def WSR_ACCLO_P : Pseudo<(outs), (ins AR:$s),
+ "!xtensa_wsr_acclo_p, $s",
+ [(int_xtensa_wsr_acclo AR:$s)]>;
+ def WSR_ACCHI_P : Pseudo<(outs), (ins AR:$s),
+ "!xtensa_wsr_acchi_p, $s",
+ [(int_xtensa_wsr_acchi AR:$s)]>;
+ def WSR_M0_P : Pseudo<(outs), (ins AR:$s),
+ "!xtensa_wsr_m0_p, $s",
+ [(int_xtensa_wsr_m0 AR:$s)]>;
+ def WSR_M1_P : Pseudo<(outs), (ins AR:$s),
+ "!xtensa_wsr_m1_p, $s",
+ [(int_xtensa_wsr_m1 AR:$s)]>;
+ def WSR_M2_P : Pseudo<(outs), (ins AR:$s),
+ "!xtensa_wsr_m2_p, $s",
+ [(int_xtensa_wsr_m2 AR:$s)]>;
+ def WSR_M3_P : Pseudo<(outs), (ins AR:$s),
+ "!xtensa_wsr_m3_p, $s",
+ [(int_xtensa_wsr_m3 AR:$s)]>;
+}
diff --git a/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp
index 54ff45a93a29..481cf3b8ce4a 100644
--- a/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp
@@ -14,6 +14,7 @@
#include "Xtensa.h"
#include "XtensaTargetMachine.h"
+#include "llvm/IR/IntrinsicsXtensa.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
@@ -131,14 +132,258 @@ FunctionPass *llvm::createXtensaISelDag(XtensaTargetMachine &TM,
}
void XtensaDAGToDAGISel::Select(SDNode *Node) {
+ unsigned Opcode = Node->getOpcode();
SDLoc DL(Node);
- // Dump information about the Node being selected
- LLVM_DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
+ const unsigned MRTable[] = {Xtensa::M0, Xtensa::M1, Xtensa::M2, Xtensa::M3};
- // If we have a custom node, we already have selected!
- if (Node->isMachineOpcode()) {
- LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
- return;
+ switch (Opcode) {
+ case ISD::INTRINSIC_VOID: {
+ unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
+ switch (IntNo) {
+ default:
+ break;
+ case Intrinsic::xtensa_mul_da_ll:
+ case Intrinsic::xtensa_mul_da_lh:
+ case Intrinsic::xtensa_mul_da_hl:
+ case Intrinsic::xtensa_mul_da_hh:
+ case Intrinsic::xtensa_mula_da_ll:
+ case Intrinsic::xtensa_mula_da_lh:
+ case Intrinsic::xtensa_mula_da_hl:
+ case Intrinsic::xtensa_mula_da_hh:
+ case Intrinsic::xtensa_muls_da_ll:
+ case Intrinsic::xtensa_muls_da_lh:
+ case Intrinsic::xtensa_muls_da_hl:
+ case Intrinsic::xtensa_muls_da_hh: {
+ SDValue ChainIn = Node->getOperand(0);
+ SDValue ValueMX = Node->getOperand(2);
+ SDValue ValueT = Node->getOperand(3);
+ unsigned OpCode;
+
+ switch (IntNo) {
+ case Intrinsic::xtensa_mul_da_ll:
+ OpCode = Xtensa::MUL_DA_LL;
+ break;
+ case Intrinsic::xtensa_mul_da_lh:
+ OpCode = Xtensa::MUL_DA_LH;
+ break;
+ case Intrinsic::xtensa_mul_da_hl:
+ OpCode = Xtensa::MUL_DA_HL;
+ break;
+ case Intrinsic::xtensa_mul_da_hh:
+ OpCode = Xtensa::MUL_DA_HH;
+ break;
+ case Intrinsic::xtensa_mula_da_ll:
+ OpCode = Xtensa::MULA_DA_LL;
+ break;
+ case Intrinsic::xtensa_mula_da_lh:
+ OpCode = Xtensa::MULA_DA_LH;
+ break;
+ case Intrinsic::xtensa_mula_da_hl:
+ OpCode = Xtensa::MULA_DA_HL;
+ break;
+ case Intrinsic::xtensa_mula_da_hh:
+ OpCode = Xtensa::MULA_DA_HH;
+ break;
+ case Intrinsic::xtensa_muls_da_ll:
+ OpCode = Xtensa::MULS_DA_LL;
+ break;
+ case Intrinsic::xtensa_muls_da_lh:
+ OpCode = Xtensa::MULS_DA_LH;
+ break;
+ case Intrinsic::xtensa_muls_da_hl:
+ OpCode = Xtensa::MULS_DA_HL;
+ break;
+ case Intrinsic::xtensa_muls_da_hh:
+ OpCode = Xtensa::MULS_DA_HH;
+ break;
+ }
+
+ uint64_t MXVal = 4;
+ if (ValueMX.getOpcode() == ISD::TargetConstant) {
+ MXVal = cast<ConstantSDNode>(ValueMX)->getZExtValue();
+ }
+
+ assert(
+ (MXVal < 2) &&
+ "Unexpected value of mul*_da* first argument, it must be m0 or m1");
+ unsigned MXReg = MRTable[MXVal];
+
+ const EVT MULAResTys[] = {MVT::Other};
+ SmallVector<SDValue, 2> MULAOps;
+ MULAOps.push_back(CurDAG->getRegister(MXReg, MVT::i32));
+ MULAOps.push_back(ValueT);
+ MULAOps.push_back(ChainIn);
+
+ SDNode *MULA = CurDAG->getMachineNode(OpCode, DL, MULAResTys, MULAOps);
+ ReplaceNode(Node, MULA);
+ return;
+ }
+ case Intrinsic::xtensa_mul_ad_ll:
+ case Intrinsic::xtensa_mul_ad_lh:
+ case Intrinsic::xtensa_mul_ad_hl:
+ case Intrinsic::xtensa_mul_ad_hh:
+ case Intrinsic::xtensa_mula_ad_ll:
+ case Intrinsic::xtensa_mula_ad_lh:
+ case Intrinsic::xtensa_mula_ad_hl:
+ case Intrinsic::xtensa_mula_ad_hh:
+ case Intrinsic::xtensa_muls_ad_ll:
+ case Intrinsic::xtensa_muls_ad_lh:
+ case Intrinsic::xtensa_muls_ad_hl:
+ case Intrinsic::xtensa_muls_ad_hh: {
+ SDValue ChainIn = Node->getOperand(0);
+ SDValue ValueS = Node->getOperand(2);
+ SDValue ValueMY = Node->getOperand(3);
+ unsigned OpCode;
+
+ switch (IntNo) {
+ case Intrinsic::xtensa_mul_ad_ll:
+ OpCode = Xtensa::MUL_AD_LL;
+ break;
+ case Intrinsic::xtensa_mul_ad_lh:
+ OpCode = Xtensa::MUL_AD_LH;
+ break;
+ case Intrinsic::xtensa_mul_ad_hl:
+ OpCode = Xtensa::MUL_AD_HL;
+ break;
+ case Intrinsic::xtensa_mul_ad_hh:
+ OpCode = Xtensa::MUL_AD_HH;
+ break;
+ case Intrinsic::xtensa_mula_ad_ll:
+ OpCode = Xtensa::MULA_AD_LL;
+ break;
+ case Intrinsic::xtensa_mula_ad_lh:
+ OpCode = Xtensa::MULA_AD_LH;
+ break;
+ case Intrinsic::xtensa_mula_ad_hl:
+ OpCode = Xtensa::MULA_AD_HL;
+ break;
+ case Intrinsic::xtensa_mula_ad_hh:
+ OpCode = Xtensa::MULA_AD_HH;
+ break;
+ case Intrinsic::xtensa_muls_ad_ll:
+ OpCode = Xtensa::MULS_AD_LL;
+ break;
+ case Intrinsic::xtensa_muls_ad_lh:
+ OpCode = Xtensa::MULS_AD_LH;
+ break;
+ case Intrinsic::xtensa_muls_ad_hl:
+ OpCode = Xtensa::MULS_AD_HL;
+ break;
+ case Intrinsic::xtensa_muls_ad_hh:
+ OpCode = Xtensa::MULS_AD_HH;
+ break;
+ }
+
+ uint64_t MYVal = 4;
+ if (ValueMY.getOpcode() == ISD::TargetConstant) {
+ MYVal = cast<ConstantSDNode>(ValueMY)->getZExtValue();
+ }
+
+ assert(
+ ((MYVal > 1) && (MYVal < 4)) &&
+ "Unexpected value of mul*_ad* second argument, it must be m2 or m3");
+ unsigned MYReg = MRTable[MYVal];
+
+ const EVT MULAResTys[] = {MVT::Other};
+ SmallVector<SDValue, 2> MULAOps;
+ MULAOps.push_back(ValueS);
+ MULAOps.push_back(CurDAG->getRegister(MYReg, MVT::i32));
+ MULAOps.push_back(ChainIn);
+
+ SDNode *MULA = CurDAG->getMachineNode(OpCode, DL, MULAResTys, MULAOps);
+ ReplaceNode(Node, MULA);
+ return;
+ }
+ case Intrinsic::xtensa_mul_dd_ll:
+ case Intrinsic::xtensa_mul_dd_lh:
+ case Intrinsic::xtensa_mul_dd_hl:
+ case Intrinsic::xtensa_mul_dd_hh:
+ case Intrinsic::xtensa_mula_dd_ll:
+ case Intrinsic::xtensa_mula_dd_lh:
+ case Intrinsic::xtensa_mula_dd_hl:
+ case Intrinsic::xtensa_mula_dd_hh:
+ case Intrinsic::xtensa_muls_dd_ll:
+ case Intrinsic::xtensa_muls_dd_lh:
+ case Intrinsic::xtensa_muls_dd_hl:
+ case Intrinsic::xtensa_muls_dd_hh: {
+ SDValue ChainIn = Node->getOperand(0);
+ SDValue ValueMX = Node->getOperand(2);
+ SDValue ValueMY = Node->getOperand(3);
+ unsigned OpCode;
+
+ switch (IntNo) {
+ case Intrinsic::xtensa_mul_dd_ll:
+ OpCode = Xtensa::MUL_DD_LL;
+ break;
+ case Intrinsic::xtensa_mul_dd_lh:
+ OpCode = Xtensa::MUL_DD_LH;
+ break;
+ case Intrinsic::xtensa_mul_dd_hl:
+ OpCode = Xtensa::MUL_DD_HL;
+ break;
+ case Intrinsic::xtensa_mul_dd_hh:
+ OpCode = Xtensa::MUL_DD_HH;
+ break;
+ case Intrinsic::xtensa_mula_dd_ll:
+ OpCode = Xtensa::MULA_DD_LL;
+ break;
+ case Intrinsic::xtensa_mula_dd_lh:
+ OpCode = Xtensa::MULA_DD_LH;
+ break;
+ case Intrinsic::xtensa_mula_dd_hl:
+ OpCode = Xtensa::MULA_DD_HL;
+ break;
+ case Intrinsic::xtensa_mula_dd_hh:
+ OpCode = Xtensa::MULA_DD_HH;
+ break;
+ case Intrinsic::xtensa_muls_dd_ll:
+ OpCode = Xtensa::MULS_DD_LL;
+ break;
+ case Intrinsic::xtensa_muls_dd_lh:
+ OpCode = Xtensa::MULS_DD_LH;
+ break;
+ case Intrinsic::xtensa_muls_dd_hl:
+ OpCode = Xtensa::MULS_DD_HL;
+ break;
+ case Intrinsic::xtensa_muls_dd_hh:
+ OpCode = Xtensa::MULS_DD_HH;
+ break;
+ }
+ uint64_t MXVal = 4;
+ if (ValueMX.getOpcode() == ISD::TargetConstant) {
+ MXVal = cast<ConstantSDNode>(ValueMX)->getZExtValue();
+ }
+
+ assert(
+ (MXVal < 2) &&