Transmission of High-Definition Multimedia Interface (HDMI) data streams to HDMI/DVI monitors via Spartan 6 FPGA
Implementation
For implementating the Project a new ISE WebPack project is created and all Verilog and VHDL files are added. These files together with other useful files (such as the . ucf file) are included. Then the project is synthesized and implemented. Bitstream file is downloaded to the FPGA board and tested. To test the design, we need to attach a monitor to the HDMI OUT (J2) port of the Atlys board. An HDMI monitor can be connected directly using an HDMI cable. To connect a DVI monitor,we need an HDMI to DVI converter
Output
We see the monitor display the coloured pattern as shown in above figure. The monitor shows the default colored pattern without any change in switching configurations. Using three DIP switches on the board (SW0, SW1, and SW3), the user is able to switch among different screen modes. Following test pattern are observed by selecting following switches which display 720p frames configurations :
- sw1 = 1, sw0 = 0
- sw2=1, sw1=0, sw0=0
Following test pattern are observed by selecting following switches which:
- sw2=0, sw1 = 0, sw0 = 1
