From a16d5b6bc06773c0c34a584219197424cc0453ae Mon Sep 17 00:00:00 2001
From: Kaveesha-98 <kaveesha.yalegama@gmail.com>
Date: Thu, 20 Apr 2023 13:58:50 +0530
Subject: [PATCH] commiting test changes

---
 .gitignore                                    |  11 +-
 src/main/resources/dCacheRegisters.v          |  15 +-
 src/main/scala/cache/dCache.scala             | 560 ++++++++----------
 src/main/scala/common/Fifo.scala              |   4 +-
 src/main/scala/common/configuration.scala     |   4 +-
 src/main/scala/common/ports.scala             |  24 +-
 src/main/scala/core.scala                     |  10 +-
 src/main/scala/coreTestbench.scala            |  31 +-
 src/main/scala/decode/constants.scala         |   2 +-
 src/main/scala/decode/decode.scala            | 106 ++--
 src/main/scala/exec/exec.scala                |  14 +-
 src/main/scala/fetch/fetch.scala              |   3 +-
 src/main/scala/memAccess/memAccess.scala      |  19 +-
 src/main/scala/rob/rob.scala                  |  53 +-
 .../testbench/assembly_programs/a-amoadd_d.s  | 108 ++++
 .../testbench/assembly_programs/a-amoadd_w.s  | 115 ++++
 .../testbench/assembly_programs/a-amoand_d.s  | 115 ++++
 .../testbench/assembly_programs/a-amoand_w.s  | 115 ++++
 .../testbench/assembly_programs/a-amomax_d.s  | 115 ++++
 .../testbench/assembly_programs/a-amomax_w.s  | 115 ++++
 .../testbench/assembly_programs/a-amomaxu_d.s | 115 ++++
 .../testbench/assembly_programs/a-amomaxu_w.s | 115 ++++
 .../testbench/assembly_programs/a-amomin_d.s  | 115 ++++
 .../testbench/assembly_programs/a-amomin_w.s  | 115 ++++
 .../testbench/assembly_programs/a-amominu_d.s | 115 ++++
 .../testbench/assembly_programs/a-amominu_w.s | 115 ++++
 .../testbench/assembly_programs/a-amoor_d.s   | 115 ++++
 .../testbench/assembly_programs/a-amoor_w.s   | 115 ++++
 .../testbench/assembly_programs/a-amoswap_d.s | 115 ++++
 .../testbench/assembly_programs/a-amoswap_w.s | 115 ++++
 .../testbench/assembly_programs/a-amoxor_d.s  | 115 ++++
 .../testbench/assembly_programs/a-amoxor_w.s  | 115 ++++
 .../testbench/assembly_programs/a-lrsc.s      | 167 ++++++
 .../testbench/assembly_programs/add.s         | 160 +++++
 .../testbench/assembly_programs/addi.s        | 146 +++++
 .../testbench/assembly_programs/addiw.s       | 146 +++++
 .../testbench/assembly_programs/addw.s        | 160 +++++
 .../testbench/assembly_programs/and.s         | 144 +++++
 .../testbench/assembly_programs/andi.s        | 130 ++++
 .../testbench/assembly_programs/auipc.s       | 114 ++++
 .../testbench/assembly_programs/beq.s         | 139 +++++
 .../testbench/assembly_programs/bge.s         | 142 +++++
 .../testbench/assembly_programs/bgeu.s        | 142 +++++
 .../testbench/assembly_programs/blt.s         | 139 +++++
 .../testbench/assembly_programs/bltu.s        | 139 +++++
 .../testbench/assembly_programs/bne.s         | 139 +++++
 .../testbench/assembly_programs/jal.s         | 125 ++++
 .../testbench/assembly_programs/jalr.s        | 152 +++++
 .../testbench/assembly_programs/lb.s          | 167 ++++++
 .../testbench/assembly_programs/lbu.s         | 167 ++++++
 .../testbench/assembly_programs/ld.s          | 167 ++++++
 .../testbench/assembly_programs/lh.s          | 167 ++++++
 .../testbench/assembly_programs/lhu.s         | 167 ++++++
 .../testbench/assembly_programs/lui.s         | 111 ++++
 .../testbench/assembly_programs/lw.s          | 167 ++++++
 .../testbench/assembly_programs/lwu.s         | 167 ++++++
 .../testbench/assembly_programs/or.s          | 144 +++++
 .../testbench/assembly_programs/ori.s         | 130 ++++
 .../testbench/assembly_programs/sb.s          | 164 +++++
 .../testbench/assembly_programs/sd.s          | 160 +++++
 .../testbench/assembly_programs/sh.s          | 164 +++++
 .../testbench/assembly_programs/sll.s         | 171 ++++++
 .../testbench/assembly_programs/slli.s        | 149 +++++
 .../testbench/assembly_programs/slliw.s       | 150 +++++
 .../testbench/assembly_programs/sllw.s        | 172 ++++++
 .../testbench/assembly_programs/slt.s         | 159 +++++
 .../testbench/assembly_programs/slti.s        | 145 +++++
 .../testbench/assembly_programs/sltiu.s       | 145 +++++
 .../testbench/assembly_programs/sltu.s        | 159 +++++
 .../testbench/assembly_programs/sra.s         | 165 ++++++
 .../testbench/assembly_programs/srai.s        | 143 +++++
 .../testbench/assembly_programs/sraiw.s       | 153 +++++
 .../testbench/assembly_programs/sraw.s        | 172 ++++++
 .../testbench/assembly_programs/srl.s         | 168 ++++++
 .../testbench/assembly_programs/srli.s        | 146 +++++
 .../testbench/assembly_programs/srliw.s       | 150 +++++
 .../testbench/assembly_programs/srlw.s        | 172 ++++++
 .../testbench/assembly_programs/sub.s         | 158 +++++
 .../testbench/assembly_programs/subw.s        | 158 +++++
 .../testbench/assembly_programs/sw.s          | 160 +++++
 .../testbench/assembly_programs/xor.s         | 144 +++++
 .../testbench/assembly_programs/xori.s        | 130 ++++
 .../testbench/create-tests-programs.sh        |  24 +
 verilator-tests/testbench/output.hex          |   2 +-
 .../testbench/programs/binary_to_text.c       |  30 +
 verilator-tests/testbench/programs/compile.sh |  12 +
 verilator-tests/testbench/programs/hello.c    |  15 +
 verilator-tests/testbench/programs/init.s     |   4 +
 verilator-tests/testbench/programs/virt.ld    |   5 +
 verilator-tests/testbench/test-run.sh         |   2 +-
 verilator-tests/testbench/testbenchtest.cpp   | 102 ++--
 verilator-tests/testbench/tests.txt           |  68 +++
 verilog_srcs/dCacheRegisters.v                |  80 +++
 verilog_srcs/iCacheRegisters.v                |  67 +++
 verilog_srcs/tb.v                             |  75 +++
 95 files changed, 10515 insertions(+), 485 deletions(-)
 create mode 100644 verilator-tests/testbench/assembly_programs/a-amoadd_d.s
 create mode 100644 verilator-tests/testbench/assembly_programs/a-amoadd_w.s
 create mode 100644 verilator-tests/testbench/assembly_programs/a-amoand_d.s
 create mode 100644 verilator-tests/testbench/assembly_programs/a-amoand_w.s
 create mode 100644 verilator-tests/testbench/assembly_programs/a-amomax_d.s
 create mode 100644 verilator-tests/testbench/assembly_programs/a-amomax_w.s
 create mode 100644 verilator-tests/testbench/assembly_programs/a-amomaxu_d.s
 create mode 100644 verilator-tests/testbench/assembly_programs/a-amomaxu_w.s
 create mode 100644 verilator-tests/testbench/assembly_programs/a-amomin_d.s
 create mode 100644 verilator-tests/testbench/assembly_programs/a-amomin_w.s
 create mode 100644 verilator-tests/testbench/assembly_programs/a-amominu_d.s
 create mode 100644 verilator-tests/testbench/assembly_programs/a-amominu_w.s
 create mode 100644 verilator-tests/testbench/assembly_programs/a-amoor_d.s
 create mode 100644 verilator-tests/testbench/assembly_programs/a-amoor_w.s
 create mode 100644 verilator-tests/testbench/assembly_programs/a-amoswap_d.s
 create mode 100644 verilator-tests/testbench/assembly_programs/a-amoswap_w.s
 create mode 100644 verilator-tests/testbench/assembly_programs/a-amoxor_d.s
 create mode 100644 verilator-tests/testbench/assembly_programs/a-amoxor_w.s
 create mode 100644 verilator-tests/testbench/assembly_programs/a-lrsc.s
 create mode 100644 verilator-tests/testbench/assembly_programs/add.s
 create mode 100644 verilator-tests/testbench/assembly_programs/addi.s
 create mode 100644 verilator-tests/testbench/assembly_programs/addiw.s
 create mode 100644 verilator-tests/testbench/assembly_programs/addw.s
 create mode 100644 verilator-tests/testbench/assembly_programs/and.s
 create mode 100644 verilator-tests/testbench/assembly_programs/andi.s
 create mode 100644 verilator-tests/testbench/assembly_programs/auipc.s
 create mode 100644 verilator-tests/testbench/assembly_programs/beq.s
 create mode 100644 verilator-tests/testbench/assembly_programs/bge.s
 create mode 100644 verilator-tests/testbench/assembly_programs/bgeu.s
 create mode 100644 verilator-tests/testbench/assembly_programs/blt.s
 create mode 100644 verilator-tests/testbench/assembly_programs/bltu.s
 create mode 100644 verilator-tests/testbench/assembly_programs/bne.s
 create mode 100644 verilator-tests/testbench/assembly_programs/jal.s
 create mode 100644 verilator-tests/testbench/assembly_programs/jalr.s
 create mode 100644 verilator-tests/testbench/assembly_programs/lb.s
 create mode 100644 verilator-tests/testbench/assembly_programs/lbu.s
 create mode 100644 verilator-tests/testbench/assembly_programs/ld.s
 create mode 100644 verilator-tests/testbench/assembly_programs/lh.s
 create mode 100644 verilator-tests/testbench/assembly_programs/lhu.s
 create mode 100644 verilator-tests/testbench/assembly_programs/lui.s
 create mode 100644 verilator-tests/testbench/assembly_programs/lw.s
 create mode 100644 verilator-tests/testbench/assembly_programs/lwu.s
 create mode 100644 verilator-tests/testbench/assembly_programs/or.s
 create mode 100644 verilator-tests/testbench/assembly_programs/ori.s
 create mode 100644 verilator-tests/testbench/assembly_programs/sb.s
 create mode 100644 verilator-tests/testbench/assembly_programs/sd.s
 create mode 100644 verilator-tests/testbench/assembly_programs/sh.s
 create mode 100644 verilator-tests/testbench/assembly_programs/sll.s
 create mode 100644 verilator-tests/testbench/assembly_programs/slli.s
 create mode 100644 verilator-tests/testbench/assembly_programs/slliw.s
 create mode 100644 verilator-tests/testbench/assembly_programs/sllw.s
 create mode 100644 verilator-tests/testbench/assembly_programs/slt.s
 create mode 100644 verilator-tests/testbench/assembly_programs/slti.s
 create mode 100644 verilator-tests/testbench/assembly_programs/sltiu.s
 create mode 100644 verilator-tests/testbench/assembly_programs/sltu.s
 create mode 100644 verilator-tests/testbench/assembly_programs/sra.s
 create mode 100644 verilator-tests/testbench/assembly_programs/srai.s
 create mode 100644 verilator-tests/testbench/assembly_programs/sraiw.s
 create mode 100644 verilator-tests/testbench/assembly_programs/sraw.s
 create mode 100644 verilator-tests/testbench/assembly_programs/srl.s
 create mode 100644 verilator-tests/testbench/assembly_programs/srli.s
 create mode 100644 verilator-tests/testbench/assembly_programs/srliw.s
 create mode 100644 verilator-tests/testbench/assembly_programs/srlw.s
 create mode 100644 verilator-tests/testbench/assembly_programs/sub.s
 create mode 100644 verilator-tests/testbench/assembly_programs/subw.s
 create mode 100644 verilator-tests/testbench/assembly_programs/sw.s
 create mode 100644 verilator-tests/testbench/assembly_programs/xor.s
 create mode 100644 verilator-tests/testbench/assembly_programs/xori.s
 create mode 100644 verilator-tests/testbench/create-tests-programs.sh
 create mode 100644 verilator-tests/testbench/programs/binary_to_text.c
 create mode 100644 verilator-tests/testbench/programs/compile.sh
 create mode 100644 verilator-tests/testbench/programs/hello.c
 create mode 100644 verilator-tests/testbench/programs/init.s
 create mode 100644 verilator-tests/testbench/programs/virt.ld
 create mode 100644 verilator-tests/testbench/tests.txt
 create mode 100644 verilog_srcs/dCacheRegisters.v
 create mode 100644 verilog_srcs/iCacheRegisters.v
 create mode 100644 verilog_srcs/tb.v

diff --git a/.gitignore b/.gitignore
index 41ffe29..60b3bab 100644
--- a/.gitignore
+++ b/.gitignore
@@ -19,4 +19,13 @@ cpu-test/cpuTestbench
 verilator-tests/dCache/dCache
 verilator-tests/testbench/testbench
 .fuse_hidden0000465a000000ff
-verilator-tests/testbench/binToHex
\ No newline at end of file
+verilator-tests/testbench/binToHex
+verilator-tests/testbench/target_texts
+verilator-tests/testbench/objectfiles
+verilator-tests/testbench/elffiles
+verilator-tests/testbench/dumps
+verilator-tests/testbench/programs/build
+!vivado/riscv_rob/riscv_rob.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v
+!vivado/riscv_rob/riscv_rob.srcs/sources_1/imports/FYP-18-RISCV-Core/*.v
+!vivado/riscv_rob/riscv_rob.srcs/sim_1/tb.v
+!verilog_srcs/*.v
\ No newline at end of file
diff --git a/src/main/resources/dCacheRegisters.v b/src/main/resources/dCacheRegisters.v
index 871f2b3..b47e93b 100644
--- a/src/main/resources/dCacheRegisters.v
+++ b/src/main/resources/dCacheRegisters.v
@@ -6,9 +6,9 @@ module dCacheRegisters #(
   localparam block_size = 1 << double_word_offset_width // double words per block
 ) (
   input [31:0] address,
-  output [63:0] byte_aligned_data,
-  output [tag_width-1: 0] tag,
-  output tag_valid,
+  output reg [63:0] byte_aligned_data,
+  output reg [tag_width-1: 0] tag,
+  output reg tag_valid,
   input [line_width-1:0] write_line_index,
   input [64*block_size - 1:0] write_block,
   input [tag_width-1: 0] write_tag,
@@ -20,9 +20,14 @@ module dCacheRegisters #(
   reg [tag_width-1:0] tags [cache_depth-1:0];
   reg validBits [cache_depth-1:0];
 
-  assign byte_aligned_data = cache[address[line_width+double_word_offset_width+3-1:double_word_offset_width+3]][address[double_word_offset_width-1 + 3:3]];
+  always @(posedge clock) begin
+    byte_aligned_data <= cache[address[line_width+double_word_offset_width+3-1:double_word_offset_width+3]][address[double_word_offset_width-1 + 3:3]];
+    tag <= tags[address[line_width+double_word_offset_width+3-1:double_word_offset_width+3]];
+    tag_valid <= validBits[address[line_width+double_word_offset_width+3-1:double_word_offset_width+3]];
+  end 
+  /* assign byte_aligned_data = cache[address[line_width+double_word_offset_width+3-1:double_word_offset_width+3]][address[double_word_offset_width-1 + 3:3]];
   assign tag = tags[address[line_width+double_word_offset_width+3-1:double_word_offset_width+3]];
-  assign tag_valid = validBits[address[line_width+double_word_offset_width+3-1:double_word_offset_width+3]];
+  assign tag_valid = validBits[address[line_width+double_word_offset_width+3-1:double_word_offset_width+3]]; */
 
   always @(posedge clock) begin
     if (reset) begin
diff --git a/src/main/scala/cache/dCache.scala b/src/main/scala/cache/dCache.scala
index 7c9a039..03fa3a4 100644
--- a/src/main/scala/cache/dCache.scala
+++ b/src/main/scala/cache/dCache.scala
@@ -24,7 +24,6 @@ import chisel3.experimental.IO
 import pipeline.ports._
 import pipeline.configuration.coreConfiguration._
 import pipeline.memAccess.AXI
-import os.write
 
 class dCacheRegisters extends BlackBox(
   Map("double_word_offset_width " -> dCacheDoubleWordOffsetWidth,
@@ -65,7 +64,7 @@ class dCache extends Module {
       val robAddr = UInt(robAddrWidth.W)
     })
   })
-  val lowLevelAXI = IO(new AXI)
+  val lowLevelMem = IO(new AXI)
   val cleanCaches = IO(new composableInterface)
   val cachesCleaned = IO(new composableInterface)
 
@@ -75,47 +74,9 @@ class dCache extends Module {
   cache.io.clock := clock
   cache.io.reset := reset
 
-  // element that updates cache for writes, atomics and miss-handling
-  val updateCacheBlock = RegInit((new Bundle {
-    val valid = Bool()
-    val block = UInt((dCacheBlockSize*64).W)
-    val index = UInt(dCacheLineWidth.W)
-    val tag   = UInt(dCacheTagWidth.W)
-    val mask = UInt(dCacheBlockSize.W)
-  }).Lit(
-    _.valid -> false.B,
-    _.block -> 0.U,
-    _.index -> 0.U,
-    _.tag   -> 0.U,
-    _.mask -> 0.U
-  ))
-
-  cache.io.write_in := updateCacheBlock.valid
-  cache.io.write_block := updateCacheBlock.block
-  cache.io.write_line_index := updateCacheBlock.index
-  cache.io.write_tag := updateCacheBlock.tag
-  cache.io.write_mask := updateCacheBlock.mask
-
-  /**
-    * servicing - combinationally connected to cached memory and is immediately
-    * serviced.
-    * 
-    * When there the cache is not in stall (servicing atomics, stores or handling 
-    * cache miss) all requests are stored in cacheReqs(servicing) and serviced 
-    * immeditely.
-    * 
-    * After handling miss the request in cacheReqs(servicing) is transfered to 
-    * cacheReqs(waiting) and the request that resulted in the miss is loaded in to
-    * cacheReqs(servicing).
-    * 
-    * If the new request from pipeline cannot be serviced in the next cycle, it is
-    * then loaded to cacheReqs(buffered). Once loaded the module will not be ready 
-    * for more requests from pipeline until the request in cacheReqs(buffered) is
-    * cleared.
-    */
-  val servicing :: buffered :: waiting :: Nil = Enum(3)
-  // cache requests are buffered in these registers
-  val cacheReqs = RegInit(VecInit(Seq.fill(3)(RegInit((new Bundle {
+  
+  val next :: buffered :: servicing :: Nil = Enum(3)
+  val requests = RegInit(VecInit(Seq.fill(3)(RegInit((new Bundle {
     val valid = Bool()
     val address = UInt(64.W)
     val writeData = UInt(64.W)
@@ -129,303 +90,288 @@ class dCache extends Module {
     _.robAddr -> 0.U
   )))))
 
-  cache.io.address := cacheReqs(servicing).address 
-
-  // response from cache lookup stored here
-  val lookupResponse = RegInit((new Bundle {
+  val results = RegInit(VecInit(Seq.fill(2)(RegInit((new Bundle {
     val valid = Bool()
     val address = UInt(64.W)
-    val writeData = UInt(64.W)
-    val instruction = UInt(32.W)
-    val robAddr = UInt(robAddrWidth.W)
     val byteAlignedData = UInt(64.W)
     val tag = UInt(dCacheTagWidth.W)
     val tagValid = Bool()
+    val instruction = UInt(32.W)
+    val writeData = UInt(64.W)
+    val robAddr = UInt(robAddrWidth.W)
   }).Lit(
     _.valid -> false.B,
     _.address -> 0.U,
-    _.writeData -> 0.U,
-    _.instruction -> 0.U,
-    _.robAddr -> 0.U,
     _.byteAlignedData -> 0.U,
     _.tag -> 0.U,
-    _.tagValid -> false.B
+    _.tagValid -> false.B,
+    _.instruction -> 0.U,
+    _.writeData -> 0.U,
+    _.robAddr -> 0.U
+  )))))
+
+  val cacheFill = RegInit((new Bundle {
+    val valid = Bool()
+    val block = UInt((dCacheBlockSize*64).W)
+    val mask = UInt((1 << dCacheDoubleWordOffsetWidth).W)
+  }).Lit(
+    _.valid -> false.B,
+    _.block -> 0.U,
+    _.mask -> 0.U
   ))
 
-  val arvalid, rready, awvalid, wvalid, bready, wlast = RegInit(false.B)
-  val writeData = Reg(UInt(64.W))
-  val newCacheBlock = Reg(UInt((64*dCacheBlockSize).W))
-
-  // reads are only done to handle misses
-  lowLevelAXI.ARADDR  := Cat(lookupResponse.address(31, 3+dCacheDoubleWordOffsetWidth), 0.U((3+dCacheDoubleWordOffsetWidth).W))
-  lowLevelAXI.ARBURST := 1.U
-  lowLevelAXI.ARCACHE := 2.U
-  lowLevelAXI.ARID    := 0.U
-  lowLevelAXI.ARLEN   := (dCacheBlockSize*2 - 1).U // axi is 32 bits wide
-  lowLevelAXI.ARLOCK  := 0.U
-  lowLevelAXI.ARPROT  := 0.U
-  lowLevelAXI.ARQOS   := 0.U
-  lowLevelAXI.ARSIZE  := 2.U
-  lowLevelAXI.ARVALID := arvalid
-
-  lowLevelAXI.RREADY := rready
-
-  lowLevelAXI.AWADDR  := lookupResponse.address
-  lowLevelAXI.AWBURST := 1.U
-  lowLevelAXI.AWCACHE := 2.U
-  lowLevelAXI.AWID    := 0.U
-  lowLevelAXI.AWLEN   := Mux(lookupResponse.instruction(13, 12) === 3.U, 1.U, 0.U)
-  lowLevelAXI.AWLOCK  := 0.U
-  lowLevelAXI.AWPROT  := 0.U
-  lowLevelAXI.AWQOS   := 0.U
-  lowLevelAXI.AWSIZE  := Mux(lookupResponse.instruction(13, 12) === 3.U, 2.U, lookupResponse.instruction(13, 12))
-  lowLevelAXI.AWVALID := awvalid
-
-  def AXI_MASK(offset: UInt) =
-    VecInit(1.U, 3.U, 15.U, 15.U)(offset)
-
-  lowLevelAXI.WDATA   := writeData(31, 0)
-  lowLevelAXI.WLAST   := wlast
-  lowLevelAXI.WSTRB   := AXI_MASK(lookupResponse.instruction(13, 12)) << lookupResponse.address(1, 0)
-  lowLevelAXI.WVALID  := wvalid
-
-  lowLevelAXI.BREADY := bready
-
-  val semaphoreSet = RegInit((new Bundle {
-    val valid           = Bool()
-    val address         = UInt(32.W) // physical memory is 32bits wide
-    val reservationSet  = UInt(64.W)
-    val funct3          = UInt(3.W)
+  val reservation = RegInit((new Bundle {
+    val free = Bool()
+    val set = UInt(64.W)
+    val wasDouble = Bool()
+    val address = UInt(64.W)
   }).Lit(
-    _.valid           -> false.B,
-    _.address         -> 0.U,
-    _.reservationSet  -> 0.U,
-    _.funct3          -> 0.U
+    _.free -> true.B
   ))
 
-  val atomicComplete = RegInit(false.B)
-
-  val cacheHit = lookupResponse.tagValid && (lookupResponse.tag === (lookupResponse.address >> (32 - dCacheTagWidth)))
-  pipelineMemAccess.req.ready := !cacheReqs(buffered).valid
-
-  def isStoreConditional(instruction: UInt) = 
-    (instruction(31, 27) === 3.U) && (instruction(6, 2) === "b01011".U)
-
-  // normal stores do not drive a response to pipeline of core
-  pipelineMemAccess.resp.valid := lookupResponse.valid && cacheHit && ((lookupResponse.instruction(6, 2) === 0.U) || ((lookupResponse.instruction(6, 2) === "b01011".U) && atomicComplete))
-
-  val storeConditionalSuccess = (
-    semaphoreSet.valid && // make sure that there was a LR.* before the current SC.*
-    semaphoreSet.address === lookupResponse.address && // make sure SC.* targets same address as latest LR.*
-    semaphoreSet.funct3 === lookupResponse.instruction(14,12) && // make sure SC.* is the same width as latest LR.*
-    // making sure reservation set is valid(data values has not been changed since last LR.*)
-    Mux(semaphoreSet.funct3 === 3.U, semaphoreSet.reservationSet === lookupResponse.byteAlignedData, 
-    (semaphoreSet.address(2).asBool && (semaphoreSet.reservationSet(63, 32) === lookupResponse.byteAlignedData(63, 32))) || 
-    (!semaphoreSet.address(2).asBool && (semaphoreSet.reservationSet(31, 0) === lookupResponse.byteAlignedData(31, 0))))
-  ) 
-
-  pipelineMemAccess.resp.bits.byteAlignedData := Mux(
-    isStoreConditional(lookupResponse.instruction), Mux(storeConditionalSuccess, 0.U, 1.U << lookupResponse.address(2, 0)), // handling data returns on SC.*
-    lookupResponse.byteAlignedData
-  )
-  pipelineMemAccess.resp.bits.address := lookupResponse.address
-  pipelineMemAccess.resp.bits.funct3 := lookupResponse.instruction(14, 12)
-  pipelineMemAccess.resp.bits.robAddr := lookupResponse.robAddr
+  // processing instruction that modifies memory
+  val processingMod = Seq(requests(servicing), results(next), results(buffered)).map(i => i.valid && (i.instruction(6,2) =/= 0.U)).reduce(_ || _)
+  val cacheMissed = !(results(next).tagValid && (results(next).address >> (32-dCacheTagWidth)) === results(next).tag) && results(next).valid 
+  val arvalid, rready = RegInit(false.B)
+  val awvalid, wvalid, bready, wlast = RegInit(false.B) 
   
-  val waitToFinish = RegInit(false.B)
-
-  pipelineMemAccess.req.ready := !cacheReqs(buffered).valid && !waitToFinish
-
-  cleanCaches.ready := !waitToFinish
-
-  cachesCleaned.ready := waitToFinish
-
-  val responseStalled = lookupResponse.valid && (
-    (lookupResponse.instruction(6, 2) === "b0100".U && !updateCacheBlock.valid) || // for stores after lookup it must be written to cache after commiting it to memory
-    (lookupResponse.instruction(6, 2) =/= "b0100".U && !pipelineMemAccess.resp.valid) || // wait for atomics to be finished, misses to be handled
-    (lookupResponse.instruction(6, 2) =/= "b0100".U && pipelineMemAccess.resp.valid && !pipelineMemAccess.resp.ready)
-  )
-
-  // filling cacheReqs(servicing)
-  when(!responseStalled) {
-    when(lookupResponse.valid && !cacheHit && updateCacheBlock.valid) {
-      // after fetching the missed cache block and writing it to cache, the
-      // the request that resulted in the miss is reloaded
-      cacheReqs(servicing).valid        := true.B
-      cacheReqs(servicing).address      := lookupResponse.address
-      cacheReqs(servicing).writeData    := lookupResponse.writeData
-      cacheReqs(servicing).instruction  := lookupResponse.instruction
-      cacheReqs(servicing).robAddr      := lookupResponse.robAddr
-    }.elsewhen(cacheReqs(waiting).valid) {
-      // after handling the request that resulted in a cache miss, the next 
-      // oldest request is serviced next
-      cacheReqs(servicing) := cacheReqs(waiting)
-    }.elsewhen(cacheReqs(buffered).valid) {
-      // the instruction which got buffered because the response was stalled is given
-      // priority next
-      cacheReqs(servicing) := cacheReqs(buffered)
-    }.otherwise {
-      // getting a new instruction to serve
-      cacheReqs(servicing).valid        := (pipelineMemAccess.req.ready && pipelineMemAccess.req.valid)
-      cacheReqs(servicing).address      := pipelineMemAccess.req.bits.address
-      cacheReqs(servicing).writeData    := pipelineMemAccess.req.bits.writeData
-      cacheReqs(servicing).instruction  := pipelineMemAccess.req.bits.instruction
-      cacheReqs(servicing).robAddr      := pipelineMemAccess.req.bits.robAddr
+  val writeMask = VecInit(1.U, 3.U, 15.U, 255.U)(results(next).instruction(13, 12))
+  val alignedMask = writeMask << results(next).address(2,0)
+  val alignedWriteData = results(next).writeData << (VecInit.tabulate(8)(i => (i*8).U)(results(next).address(2, 0)))
+  val dataPostMod = {
+    val atom32 = {
+      val src1 = Mux(results(next).address(2).asBool, results(next).byteAlignedData(63, 32), results(next).byteAlignedData(31, 0))
+      val src2 = results(next).writeData(31, 0)
+
+      val mod = VecInit.tabulate(8)(i => i match {
+        case 0 => Mux(results(next).instruction(27).asBool, src2, src1 + src2)
+        case 1 => src1 ^ src2
+        case 2 => src1 | src2
+        case 3 => src1 & src2
+        case 4 => Mux(src1.asSInt < src2.asSInt, src1, src2)
+        case 5 => Mux(src1.asSInt < src2.asSInt, src2, src1)
+        case 6 => Mux(src1 < src2, src1, src2)
+        case 7 => Mux(src1 < src2, src2, src1)
+      })(results(next).instruction(31, 29))
+      
+      Cat((Seq.tabulate(2)(i => 
+        Mux(results(next).address(2) === i.U, mod, results(next).byteAlignedData(31 + 32*i, 32*i))  
+      )).reverse)
+    }
+
+    val atom64 = {
+      val src1 = results(next).byteAlignedData
+      val src2 = results(next).writeData
+
+      VecInit.tabulate(8)(i => i match {
+        case 0 => Mux(results(next).instruction(27).asBool, src2, src1 + src2)
+        case 1 => src1 ^ src2
+        case 2 => src1 | src2
+        case 3 => src1 & src2
+        case 4 => Mux(src1.asSInt < src2.asSInt, src1, src2)
+        case 5 => Mux(src1.asSInt < src2.asSInt, src2, src1)
+        case 6 => Mux(src1 < src2, src1, src2)
+        case 7 => Mux(src1 < src2, src2, src1)
+      })(results(next).instruction(31, 29))
     }
-  }.elsewhen(updateCacheBlock.valid && (updateCacheBlock.mask === "hff".U)) {
-    cacheReqs(servicing).valid        := true.B
-    cacheReqs(servicing).address      := lookupResponse.address
-    cacheReqs(servicing).writeData    := lookupResponse.writeData
-    cacheReqs(servicing).instruction  := lookupResponse.instruction
-    cacheReqs(servicing).robAddr      := lookupResponse.robAddr
-  }.elsewhen(!cacheReqs(servicing).valid) {
-    cacheReqs(servicing).valid        := (pipelineMemAccess.req.ready && pipelineMemAccess.req.valid)
-    cacheReqs(servicing).address      := pipelineMemAccess.req.bits.address
-    cacheReqs(servicing).writeData    := pipelineMemAccess.req.bits.writeData
-    cacheReqs(servicing).instruction  := pipelineMemAccess.req.bits.instruction
-    cacheReqs(servicing).robAddr      := pipelineMemAccess.req.bits.robAddr
+
+    val modData = Mux(results(next).instruction(2).asBool, Mux(results(next).instruction(12).asBool, atom64, atom32), alignedWriteData)
+
+    Cat((Seq.tabulate(8)(i => Mux(alignedMask(i).asBool, modData(7 + 8*i, 8*i), results(next).byteAlignedData(7 + 8*i, 8*i)))).reverse)
   }
 
-  // filling cacheReqs(buffered)
-  when(!responseStalled && !cacheReqs(waiting).valid) {
-    // servicing the buffered request
-    cacheReqs(buffered).valid := false.B
-  }.elsewhen(responseStalled && cacheReqs(servicing).valid && !cacheReqs(buffered).valid) {
-    // new request has to be buffered
-    cacheReqs(buffered).valid        := (pipelineMemAccess.req.ready && pipelineMemAccess.req.valid)
-    cacheReqs(buffered).address      := pipelineMemAccess.req.bits.address
-    cacheReqs(buffered).writeData    := pipelineMemAccess.req.bits.writeData
-    cacheReqs(buffered).instruction  := pipelineMemAccess.req.bits.instruction
-    cacheReqs(buffered).robAddr      := pipelineMemAccess.req.bits.robAddr
+  when(lowLevelMem.RREADY && lowLevelMem.RVALID) { 
+    cacheFill.block := Cat(lowLevelMem.RDATA, cacheFill.block(64*dCacheBlockSize-1, 32)) 
+    cacheFill.mask := ~(0.U((1<<dCacheDoubleWordOffsetWidth).W))
+  }.elsewhen(results(next).valid && !cacheMissed && !awvalid && !wvalid && !bready && (results(next).instruction(6,2) =/= 0.U)) {
+    cacheFill.block := dataPostMod << VecInit.tabulate(dCacheBlockSize)(i => (64*i).U)(results(next).address(dCacheDoubleWordOffsetWidth+3,3)) 
+    cacheFill.mask := 1.U(dCacheBlockSize.W) << (results(next).address(dCacheDoubleWordOffsetWidth+3-1,3))
   }
 
-  // filling cacheReqs(waiting)
-  when(lookupResponse.valid && updateCacheBlock.valid && (updateCacheBlock.mask === "hff".U)) {
-    // caches updated and the request is being reloaded to reservice
-    cacheReqs(waiting) := cacheReqs(servicing)
-  }.elsewhen(!responseStalled) {
-    // request is being moved to cacheReqs(servicing)
-    cacheReqs(waiting).valid := false.B
+  when(!arvalid) { arvalid := cacheMissed && !rready && !cacheFill.valid } 
+  .otherwise { arvalid := !(lowLevelMem.ARVALID && lowLevelMem.ARREADY) }
+
+  when(!rready) { rready := (lowLevelMem.ARVALID && lowLevelMem.ARREADY) }
+  .otherwise { rready := !(lowLevelMem.RLAST && lowLevelMem.RREADY && lowLevelMem.RVALID) }
+
+  /* when(!cacheFill.valid) { cacheFill.valid := lowLevelMem.RLAST && lowLevelMem.RREADY && lowLevelMem.RVALID }
+  .otherwise { cacheFill.valid := results(next).valid && !cacheMissed && !awvalid && !wvalid && !bready && (results(next).instruction(6,2) =/= 0.U) }
+ */
+  val scPass = !reservation.free && (reservation.address === results(next).address) && (reservation.wasDouble === results(next).instruction(12).asBool) && Mux(reservation.wasDouble, reservation.set === results(next).byteAlignedData, Mux(results(next).address(2).asBool, results(next).byteAlignedData(63, 32) === reservation.set(63, 32), results(next).byteAlignedData(31, 0) === reservation.set(31, 0))) 
+  val scSuccess = (Cat(results(next).instruction(28, 27), results(next).instruction(3, 2)) =/= "b1111".U) || scPass
+  cacheFill.valid := (results(next).valid && !cacheMissed && !awvalid && !wvalid && !bready && (results(next).instruction(6,2) =/= 0.U) && (Cat(results(next).instruction(28, 27), results(next).instruction(3, 2)) =/= "b1011".U) && scSuccess) || (lowLevelMem.RLAST && lowLevelMem.RREADY && lowLevelMem.RVALID)
+
+  when(results(next).instruction(3, 2) === 3.U && results(next).valid && results(next).instruction(28).asBool) {
+    when(results(next).instruction(27).asBool) {
+      reservation.free := true.B
+    }.otherwise {
+      reservation.free := false.B
+      reservation.address := results(next).address
+      reservation.set := results(next).byteAlignedData
+      reservation.wasDouble := results(next).instruction(12).asBool
+    }
   }
 
-  // handling lookup response
-  when(!responseStalled){
-    // lookupResponse only changes iff !responseStalled
-    lookupResponse.valid := cacheReqs(servicing).valid
-    lookupResponse.address := cacheReqs(servicing).address
-    lookupResponse.writeData := cacheReqs(servicing).writeData
-    lookupResponse.instruction := cacheReqs(servicing).instruction
-    lookupResponse.robAddr := cacheReqs(servicing).robAddr
-    lookupResponse.byteAlignedData := cache.io.byte_aligned_data
-    lookupResponse.tag := cache.io.tag
-    lookupResponse.tagValid := cache.io.tag_valid
-  }.elsewhen(updateCacheBlock.valid) {
-    lookupResponse.valid := false.B
+  Seq(awvalid, wvalid)
+  .zip(Seq(lowLevelMem.AWREADY, (lowLevelMem.WREADY && lowLevelMem.WLAST)))
+  .foreach{ case (ctrlReg, cond) => ctrlReg := Mux(ctrlReg, !cond, results(next).valid && !cacheMissed && !awvalid && !wvalid && !bready && (results(next).instruction(6,2) =/= 0.U) && (Cat(results(next).instruction(28, 27), results(next).instruction(3, 2)) =/= "b1011".U) && scSuccess) }
+  /* when(!awvalid) { awvalid := results(next).valid && !cacheMissed && !awvalid && !wvalid && !bready && (results(next).instruction(6,2) =/= 0.U)}
+  .otherwise { awvalid := !lowLevelMem.AWREADY } */
+
+  when(!bready){
+    switch(Cat(awvalid.asUInt, wvalid.asUInt)){
+      is("b11".U) { bready := (lowLevelMem.AWREADY && lowLevelMem.WREADY && lowLevelMem.WLAST) }
+      is("b10".U) { bready := lowLevelMem.AWREADY }
+      is("b01".U) { bready := (lowLevelMem.WREADY && lowLevelMem.WLAST) }
+    }
+  }.otherwise{ bready := !lowLevelMem.BVALID }
+
+  when(results(next).valid && !cacheMissed && !awvalid && !wvalid && !bready && (results(next).instruction(6,2) =/= 0.U)) {
+    wlast := (results(next).instruction(13,12) =/= 3.U)
+  }.elsewhen(wlast) { wlast := !(lowLevelMem.WVALID && lowLevelMem.WREADY) }
+  .otherwise { wlast := (lowLevelMem.WVALID && lowLevelMem.WREADY) }
+
+  val writeData = Reg(UInt(64.W))
+  val wstrb = Reg(UInt(8.W))
+  when(results(next).valid && results(next).instruction(6, 2) =/= 0.U && !wvalid) { 
+    writeData := Mux(results(next).address(2).asBool, Cat(0.U(32.W), dataPostMod(63, 32)), dataPostMod) 
+    wstrb := Mux(results(next).address(2).asBool, Cat(0.U(4.W), alignedMask(7,4)), alignedMask)
+  }.elsewhen(lowLevelMem.WVALID && lowLevelMem.WREADY) { 
+    writeData := Cat(0.U(32.W), writeData(63, 32)) 
+    wstrb := Cat(0.U(4.W), wstrb(7,4))
   }
 
-  val blockFetched = RegInit(false.B)
-  // carrying out mem reads for cachemisses
-  // sending read request
-  arvalid := Mux(arvalid, !lowLevelAXI.ARREADY, (lookupResponse.valid && !cacheHit && !rready && !blockFetched && !updateCacheBlock.valid))
-  // getting the data
-  rready := Mux(rready, !(lowLevelAXI.RVALID && lowLevelAXI.RLAST), (lowLevelAXI.ARVALID && lowLevelAXI.ARREADY))
-  
-  blockFetched := Mux(blockFetched, updateCacheBlock.valid, (lowLevelAXI.RREADY && lowLevelAXI.RVALID && lowLevelAXI.RLAST))
-
-  // organizing the fetched data
-  when(lowLevelAXI.RVALID && lowLevelAXI.RREADY) { newCacheBlock := Cat(newCacheBlock(64*dCacheBlockSize-33, 0), lowLevelAXI.RDATA) }
-
-  // commiting writes(and atmoics) to system memory
-  val writeInProgress = RegInit(false.B)
-  // writes are initiated only for stores(both normal and conditional) and atmoics
-  val initiateWrite = (lookupResponse.valid && cacheHit && (lookupResponse.instruction(6, 2)=/=0.U && lookupResponse.instruction(31, 27)=/=2.U)) && !atomicComplete && !writeInProgress
-  awvalid := Mux(awvalid, !lowLevelAXI.AWREADY, initiateWrite && !writeInProgress && !updateCacheBlock.valid)
-  bready := Mux(bready, !lowLevelAXI.BVALID, initiateWrite && !writeInProgress && !updateCacheBlock.valid)
-  wvalid := Mux(wvalid, !(lowLevelAXI.WREADY && lowLevelAXI.WLAST), initiateWrite && !writeInProgress && !updateCacheBlock.valid)
-  when(initiateWrite && writeInProgress) { wlast := lookupResponse.instruction(13, 12) =/= 3.U }
-  .elsewhen(lowLevelAXI.WREADY && lowLevelAXI.WVALID) { wlast := !wlast }
-  writeInProgress := Mux(writeInProgress, (awvalid || wvalid || bready), initiateWrite)
-
-  val modifiedData = {
-    val atmoicW = Cat(Seq.tabulate(2)(i => {
-      val original = lookupResponse.byteAlignedData(31 + 32*i, 32*i)
-      val rs2      = writeData(31, 0)
-      Mux(lookupResponse.address(2) =/= i.U, original, Mux(lookupResponse.instruction(27).asBool, rs2, 
-        VecInit.tabulate(8)(i => i match {
-          case 0 => original + rs2
-          case 1 => original ^ rs2
-          case 2 => original | rs2
-          case 3 => original & rs2
-          case 4 => Mux(original.asSInt < rs2.asSInt, original, rs2)
-          case 5 => Mux(original.asSInt < rs2.asSInt, rs2, original)
-          case 6 => Mux(original < rs2, original, rs2)
-          case 7 => Mux(original < rs2, rs2, original)
-        })(lookupResponse.instruction(31, 29))
-      ))
-    }).reverse)
-
-    val atomicD = {
-      val original = lookupResponse.byteAlignedData
-      val rs2      = writeData
-
-      Mux(lookupResponse.instruction(27).asBool, rs2, 
-      VecInit.tabulate(8)(i => i match {
-        case 0 => original + rs2
-        case 1 => original ^ rs2
-        case 2 => original | rs2
-        case 3 => original & rs2
-        case 4 => Mux(original.asSInt < rs2.asSInt, original, rs2)
-        case 5 => Mux(original.asSInt < rs2.asSInt, rs2, original)
-        case 6 => Mux(original < rs2, original, rs2)
-        case 7 => Mux(original < rs2, rs2, original)
-      })(lookupResponse.instruction(31, 29))
-    )}
-
-    val storeMask = VecInit(1.U, 3.U, 15.U, 255.U)(lookupResponse.instruction(13, 12)) << lookupResponse.address(2, 0)
-    val rs2Align = lookupResponse.writeData << VecInit(Seq.tabulate(8)(_*8).map{_.U})(lookupResponse.address(2, 0))
-    val postStore = Cat(Seq.tabulate(8)(i => Mux(storeMask(i).asBool, rs2Align(7+8*i, 8*i), lookupResponse.byteAlignedData(7+8*i, 8*i))).reverse)
-
-    Mux(lookupResponse.instruction(6,2) === "b01000".U, postStore, Mux(lookupResponse.instruction(12).asBool, atomicD, atmoicW))
+  cache.io.write_block := cacheFill.block
+  cache.io.write_in := cacheFill.valid
+  cache.io.write_line_index := results(next).address(dCacheLineWidth + dCacheDoubleWordOffsetWidth + 3, dCacheDoubleWordOffsetWidth + 3)
+  cache.io.write_tag := results(next).address(31, dCacheLineWidth + dCacheDoubleWordOffsetWidth + 3)
+  cache.io.write_mask := cacheFill.mask
+  cache.io.clock := clock
+  cache.io.reset := reset
+
+  val cacheStalled = cacheMissed || (pipelineMemAccess.resp.valid && !pipelineMemAccess.resp.ready)
+  when((!cacheMissed && (pipelineMemAccess.resp.ready || results(next).instruction(6, 2) =/= 0.U)) || !results(next).valid) {
+    when(results(buffered).valid) { results(next) := results(buffered) }
+    .elsewhen(results(next).valid && results(next).instruction(6, 2) =/= 0.U) {
+
+      results(next).valid := !(lowLevelMem.BVALID && lowLevelMem.BREADY) || results(next).instruction(3, 2) === 3.U
+      when(results(next).instruction(3, 2) === 3.U && scSuccess && (Cat(results(next).instruction(28, 27), results(next).instruction(3, 2)) =/= "b1011".U)){
+        results(next).instruction := Mux((lowLevelMem.BVALID && lowLevelMem.BREADY), results(next).instruction, Cat(results(next).instruction(31, 7), 3.U(7.W)))
+        when((Cat(results(next).instruction(28, 27), results(next).instruction(3, 2)) === "b1111".U)) {
+          results(next).byteAlignedData := 0.U
+        }
+      }.elsewhen(results(next).instruction(3, 2) === 3.U) {
+        results(next).instruction := Cat(results(next).instruction(31, 7), 3.U(7.W))
+        when((Cat(results(next).instruction(28, 27), results(next).instruction(3, 2)) === "b1111".U)) {
+          results(next).byteAlignedData := Cat(0.U(31.W), 1.U & results(next).instruction(12), 0.U(31.W), 1.U)
+        }
+      }
+
+    }.otherwise {
+      results(next).valid := requests(servicing).valid
+      results(next).address := requests(servicing).address
+      results(next).instruction := requests(servicing).instruction
+      results(next).tag := cache.io.tag
+      results(next).tagValid := cache.io.tag_valid
+      results(next).byteAlignedData := cache.io.byte_aligned_data
+      results(next).robAddr := requests(servicing).robAddr
+      results(next).writeData := requests(servicing).writeData
+    }
+  }.elsewhen(cacheMissed && cacheFill.valid) {
+    results(next).byteAlignedData := (VecInit.tabulate(1 << dCacheDoubleWordOffsetWidth)(i => cacheFill.block(63 + 64*i, 64*i)))(results(next).address(dCacheDoubleWordOffsetWidth+3, 3))
+    results(next).tag := results(next).address(32, 32 - dCacheTagWidth)
+    results(next).tagValid := true.B
   }
-  val writeOffset = (lookupResponse.address >> 3)(2, 0)
-
-  // updating cache after handling cache miss and for stores and atomics
-  when(lookupResponse.valid && !cacheHit && blockFetched) {
-    updateCacheBlock.valid := true.B
-    updateCacheBlock.block := newCacheBlock
-    updateCacheBlock.index := lookupResponse.address >> (3+dCacheDoubleWordOffsetWidth)
-    updateCacheBlock.tag   := lookupResponse.address >> (32 - dCacheTagWidth)
-    updateCacheBlock.mask := ((1 << dCacheBlockSize)-1).U
-  }.elsewhen(lookupResponse.valid && cacheHit && writeInProgress && !(awvalid || wvalid || bready) && !atomicComplete) {
-    updateCacheBlock.valid := true.B
-    updateCacheBlock.block := Cat(Seq.tabulate(1<<dCacheDoubleWordOffsetWidth)(i => Mux(i.U === writeOffset, modifiedData, 0.U(64.W))).reverse)
-    updateCacheBlock.index := lookupResponse.address >> (3+dCacheDoubleWordOffsetWidth)
-    updateCacheBlock.tag   := lookupResponse.address >> (32 - dCacheTagWidth)
-    updateCacheBlock.mask := Cat(Seq.tabulate(1<<dCacheDoubleWordOffsetWidth)(_.U === writeOffset).reverse)
-  }.otherwise {
-    updateCacheBlock.valid := false.B
+
+  when(!results(buffered).valid) {
+    results(buffered).valid := requests(servicing).valid && results(next).valid && (cacheMissed || !pipelineMemAccess.resp.ready)
+    results(buffered).address := requests(servicing).address
+    results(buffered).instruction := requests(servicing).instruction
+    results(buffered).tag := cache.io.tag
+    results(buffered).tagValid := cache.io.tag_valid
+    results(buffered).byteAlignedData := cache.io.byte_aligned_data
+    results(buffered).robAddr := requests(servicing).robAddr
+    results(buffered).writeData := requests(servicing).writeData
+  }.elsewhen(cacheMissed && cacheFill.valid && (results(next).address(31, iCacheOffsetWidth + 2) === results(buffered).address(31, iCacheOffsetWidth + 2))) {
+    results(buffered).byteAlignedData := (VecInit.tabulate(1 << dCacheDoubleWordOffsetWidth)(i => cacheFill.block(63 + 64*i, 64*i)))(results(buffered).address(dCacheDoubleWordOffsetWidth+3, 3))
+    results(buffered).tag := results(next).address(iCacheTagWidth + iCacheLineWidth + iCacheOffsetWidth + 2, iCacheLineWidth + iCacheOffsetWidth + 2)
+    results(buffered).tagValid := true.B
+  }.elsewhen(!cacheStalled) {
+    results(buffered).valid := false.B
   }
 
-  when(initiateWrite && !writeInProgress) { writeData := Mux(lookupResponse.address(2).asBool, Cat(0.U(32.W), modifiedData(63, 32)), modifiedData) }
-  .elsewhen(lowLevelAXI.WREADY && lowLevelAXI.WVALID) { writeData := (writeData >> 32) }
+  when(!results(buffered).valid) {
+    requests(servicing) := requests(next)
+    requests(servicing).valid := !cacheStalled && requests(next).valid && !processingMod
+  }.otherwise {
+    requests(servicing).valid := false.B
+  }
 
-  def responseAtomic(instruction: UInt) = (instruction(6,2) === "b01011".U)
+  when(((!cacheStalled && !results(buffered).valid && !processingMod) || !requests(next).valid)) {
+    when(requests(buffered).valid) { requests(next) := requests(buffered) }
+    .otherwise {
+      requests(next).valid := (pipelineMemAccess.req.ready && pipelineMemAccess.req.valid)
+      requests(next).address := pipelineMemAccess.req.bits.address
+      requests(next).instruction := pipelineMemAccess.req.bits.instruction
+      requests(next).robAddr := pipelineMemAccess.req.bits.robAddr
+      requests(next).writeData := pipelineMemAccess.req.bits.writeData
+    }
+  }
 
-  // completing atmoics
-  atomicComplete := Mux(atomicComplete, !(pipelineMemAccess.resp.ready && pipelineMemAccess.resp.valid), (responseAtomic(lookupResponse.instruction) && updateCacheBlock.valid))
+  when(!requests(buffered).valid) {
+    requests(buffered).valid := (cacheStalled || results(buffered).valid) && (pipelineMemAccess.req.ready && pipelineMemAccess.req.valid) && requests(next).valid && processingMod
+    requests(buffered).address := pipelineMemAccess.req.bits.address
+    requests(buffered).instruction := pipelineMemAccess.req.bits.instruction
+    requests(buffered).robAddr := pipelineMemAccess.req.bits.robAddr
+    requests(buffered).writeData := pipelineMemAccess.req.bits.writeData
 
-  def isLoadReserved(instruction: UInt) = (instruction(6,2) === "b01011".U && instruction(31, 27) === "b00010".U)
-  // getting reservation set
-  when(isLoadReserved(lookupResponse.instruction) && lookupResponse.valid) {
-    semaphoreSet.valid := true.B
-    semaphoreSet.address := lookupResponse.address
-    semaphoreSet.funct3 := lookupResponse.instruction(14,12)
-    semaphoreSet.reservationSet := lookupResponse.byteAlignedData
-  }.elsewhen(isStoreConditional(lookupResponse.instruction) && lookupResponse.valid) {
-    semaphoreSet.valid := false.B
+  }.otherwise {
+    requests(buffered).valid := (!cacheStalled && !results(buffered).valid)
   }
 
-  // waiting to clean cache
+  pipelineMemAccess.resp.valid := !cacheMissed && results(next).valid && (results(next).instruction(6,2) === 0.U)
+  pipelineMemAccess.resp.bits.address := results(next).address
+  pipelineMemAccess.resp.bits.byteAlignedData := results(next).byteAlignedData
+  pipelineMemAccess.resp.bits.funct3 := results(next).instruction(14, 12)
+  pipelineMemAccess.resp.bits.robAddr := results(next).robAddr
+
+  pipelineMemAccess.req.ready := !requests(buffered).valid
+
+  cache.io.address := requests(next).address
+
+  lowLevelMem.ARADDR := Cat(results(next).address(31, 3+dCacheDoubleWordOffsetWidth), 0.U((3+dCacheDoubleWordOffsetWidth).W))
+  lowLevelMem.ARBURST := 1.U
+  lowLevelMem.ARCACHE := 2.U
+  lowLevelMem.ARID := 0.U
+  lowLevelMem.ARLEN := (dCacheBlockSize*2 - 1).U
+  lowLevelMem.ARLOCK := 0.U
+  lowLevelMem.ARPROT := 0.U
+  lowLevelMem.ARQOS := 0.U
+  lowLevelMem.ARSIZE := 2.U
+  lowLevelMem.ARVALID := arvalid
+
+  lowLevelMem.RREADY := rready
+
+  lowLevelMem.AWADDR := results(next).address
+  lowLevelMem.AWBURST := 1.U
+  lowLevelMem.AWCACHE := 2.U
+  lowLevelMem.AWID := 0.U
+  lowLevelMem.AWLEN := (results(next).instruction(13,12) === 3.U).asUInt
+  lowLevelMem.AWLOCK := 0.U
+  lowLevelMem.AWPROT := 0.U
+  lowLevelMem.AWQOS := 0.U
+  lowLevelMem.AWSIZE := 2.U
+  lowLevelMem.AWVALID := awvalid
+
+  lowLevelMem.WDATA := writeData(31, 0)
+  lowLevelMem.WLAST := wlast
+  lowLevelMem.WSTRB := wstrb
+  lowLevelMem.WVALID := wvalid
+
+  lowLevelMem.BREADY := bready
+
+  cachesCleaned.ready := false.B
+  cleanCaches.ready := false.B
 }
 
 object dCache extends App {
diff --git a/src/main/scala/common/Fifo.scala b/src/main/scala/common/Fifo.scala
index f45933f..7199290 100644
--- a/src/main/scala/common/Fifo.scala
+++ b/src/main/scala/common/Fifo.scala
@@ -93,7 +93,7 @@ class randomAccessFifo[T <: Data ]( gen: T, depth: Int) extends Fifo(gen:
   }
 
   io.deq.bits := memReg(readPtr)
-  io.enq.ready := !fullReg
+  io.enq.ready := !fullReg | (io.deq.valid & io.deq.ready)
   io.deq.valid := !emptyReg
   //printf(p"$io\n")
 }
@@ -136,7 +136,7 @@ class regFifo[T <: Data ]( gen: T, depth: Int) extends Fifo(gen:
   }
 
   io.deq.bits := memReg(readPtr)
-  io.enq.ready := !fullReg
+  io.enq.ready := !fullReg | (io.deq.valid & io.deq.ready)
   io.deq.valid := !emptyReg
   //printf(p"$io\n")
 }
diff --git a/src/main/scala/common/configuration.scala b/src/main/scala/common/configuration.scala
index a0963c3..6cc405b 100644
--- a/src/main/scala/common/configuration.scala
+++ b/src/main/scala/common/configuration.scala
@@ -15,8 +15,8 @@ import chisel3.experimental.IO
 
 object coreConfiguration {
     val robAddrWidth = 3
-    val ramBaseAddress = 0x00100000
-    val ramHighAddress = 0x1FFFFFFF
+    val ramBaseAddress = 0x0000000000100000L
+    val ramHighAddress = 0x000000001FFFFFFFL
     val iCacheOffsetWidth = 2
     val iCacheLineWidth = 6
     val iCacheTagWidth = 32 - iCacheLineWidth - iCacheOffsetWidth - 2
diff --git a/src/main/scala/common/ports.scala b/src/main/scala/common/ports.scala
index ae0dff9..d92d4fb 100644
--- a/src/main/scala/common/ports.scala
+++ b/src/main/scala/common/ports.scala
@@ -154,8 +154,8 @@ class pullCommitFrmRob extends composableInterface {
   val robAddr       = Input(UInt(robAddrWidth.W))
   val rdAddr        = Input(UInt(5.W))
   val writeBackData = Input(UInt(64.W)) // mtval when exceptionOccured
-  /* Additional wires when exception handling is added
-  val execptionOccured  = Input(Bool())
+  //Additional wires when exception handling is added
+  /* val execptionOccured  = Input(Bool())
   val mcause            = Input(UInt(64.W))
   val mepc              = Input(UInt(64.W)) */
 } 
@@ -169,9 +169,10 @@ class pullCommitFrmRob extends composableInterface {
 class commitInstruction extends composableInterface {
   val robAddr       = Output(UInt(robAddrWidth.W))
   val rdAddr        = Output(UInt(5.W))
+  val opcode = Output(UInt(7.W))
   val writeBackData = Output(UInt(64.W)) // mtval when exceptionOccured
-  /* Additional wires when exception handling is added
-  val execptionOccured  = Output(Bool())
+  // Additional wires when exception handling is added
+  /* val execptionOccured  = Output(Bool())
   val mcause            = Output(UInt(64.W))
   val mepc              = Output(UInt(64.W)) */
 } 
@@ -228,8 +229,8 @@ class robAllocate extends composableInterface {
     val value = Output(UInt(64.W))
     val robAddr = Input(UInt(robAddrWidth.W))
   }
-  /* Wire added to handle exceptions
-  val pc = Input(UInt(32.W)) // to provide mepc when exception are reported */
+  //Wire added to handle exceptions
+  //val pc = Input(UInt(32.W)) // to provide mepc when exception are reported
 }
 
 /**
@@ -302,8 +303,8 @@ val instruction = Input(UInt(32.W))
 class pushExecResultToRob extends composableInterface {
   val robAddr     = Output(UInt(robAddrWidth.W))
   val execResult  = Output(UInt(64.W)) // mtval when exceptionOccured
-  /* Additional wires when exception handling is added
-  val execptionOccured  = Output(Bool())
+  // Additional wires when exception handling is added
+  /* val execptionOccured  = Output(Bool())
   val mcause            = Output(UInt(64.W))
   val mepc              = Output(UInt(64.W)) */
 }
@@ -316,10 +317,9 @@ class pushExecResultToRob extends composableInterface {
 class pullExecResultToRob extends composableInterface {
   val robAddr     = Input(UInt(robAddrWidth.W))
   val execResult  = Input(UInt(64.W)) // mtval when exceptionOccured
-  /* Additional wires when exception handling is added
-  val execptionOccured  = Input(Bool())
-  val mcause            = Input(UInt(64.W))
-  val mepc              = Input(UInt(64.W)) */
+  // Additional wires when exception handling is added
+  /* val execeptionOccured  = Input(Bool())
+  val mcause            = Input(UInt(64.W)) */
 }
 /*******************************************************************/
 
diff --git a/src/main/scala/core.scala b/src/main/scala/core.scala
index 61f425c..a35b44f 100644
--- a/src/main/scala/core.scala
+++ b/src/main/scala/core.scala
@@ -58,8 +58,8 @@ class core extends Module {
     _ := (decode.writeBackResult.ready && rob.commit.ready)
   )
   // these connections are incorrect an need to be fixed
-  decode.writeBackResult.rdAddr := rob.commit.rd
-  decode.writeBackResult.writeBackData := rob.commit.value  
+  decode.writeBackResult.rdAddr := rob.commit.rdAddr
+  decode.writeBackResult.writeBackData := rob.commit.writeBackData
   decode.writeBackResult.robAddr := rob.commit.robAddr
   // opcode is left dangling for the moment
 
@@ -109,12 +109,12 @@ class core extends Module {
   Seq(rob.fromMem.fired, memAccess.toRob.fired).foreach(
     _ := (rob.fromMem.ready && memAccess.toRob.ready)
   )
-  rob.fromMem.execResult := memAccess.toRob.writeBackData
+  rob.fromMem.writeBackData := memAccess.toRob.writeBackData
   rob.fromMem.robAddr := memAccess.toRob.robAddr
   
   val dcache = Module(new pipeline.memAccess.cache.dCache)
-  val dPort = IO(dcache.lowLevelAXI.cloneType)
-  dPort <> dcache.lowLevelAXI
+  val dPort = IO(dcache.lowLevelMem.cloneType)
+  dPort <> dcache.lowLevelMem
 
   memAccess.dCache <> dcache.pipelineMemAccess
 
diff --git a/src/main/scala/coreTestbench.scala b/src/main/scala/coreTestbench.scala
index 1eae225..fcb11f3 100644
--- a/src/main/scala/coreTestbench.scala
+++ b/src/main/scala/coreTestbench.scala
@@ -68,6 +68,30 @@ class testbench extends Module {
     //Mux(ports(servicing).RVALID && ports(servicing).RREADY && (serviceState === reading), mem.read(readRequest.address + 4.U + i.U), mem.read(readRequest.address + i.U))
   ).reverse)
 
+  val wready, bvalid = RegInit(false.B)
+  val awready = RegInit(true.B)
+  val waddr = Reg(UInt(32.W))
+
+  when(programRunning) {
+    when(ports(data).AWVALID && ports(data).AWREADY) { waddr <= ports(data).AWADDR }
+    .elsewhen(ports(data).WREADY && ports(data).WVALID) { waddr <= waddr + 4.U }
+
+    when(awready) { awready := !ports(data).AWVALID }
+    .otherwise { awready := (ports(data).BVALID && ports(data).BREADY) }
+
+    when(wready) { wready := !(ports(data).WVALID && ports(data).WLAST) }
+    .otherwise { wready := ports(data).AWVALID && ports(data).AWREADY }
+
+    when(bvalid) { bvalid := !ports(data).BREADY }
+    .otherwise { bvalid := ports(data).WLAST && ports(data).WVALID && ports(data).WREADY }
+
+    when(ports(data).WVALID && ports(data).WREADY) {
+      (0 until 4).foreach( i => {
+        when(ports(data).WSTRB(i).asBool) { mem.write(waddr + i.U, ports(data).WDATA(7 + 8*i, 8*i)) }
+      })
+    }
+  }
+
   Seq(inst, data).foreach( interface => {
     ports(interface).ARREADY := ((serviceState === waiting) && (servicing === interface) && programRunning)
     ports(interface).RVALID := ((serviceState === reading) && (servicing === interface))
@@ -82,6 +106,11 @@ class testbench extends Module {
     ports(interface).BVALID := false.B
     ports(interface).BRESP := 0.U
   })
+  ports(data).AWREADY := awready
+  ports(data).WREADY := wready
+  ports(data).BID := 0.U
+  ports(data).BVALID := bvalid
+  ports(data).BRESP := 0.U
 
   val testResult = RegInit((new Bundle {
     val valid = Bool()
@@ -98,7 +127,7 @@ class testbench extends Module {
   dut.peripheral.WREADY := wreadyP
   dut.peripheral.BVALID := bvalidP
 
-  when(dut.peripheral.AWVALID && dut.peripheral.AWVALID) { awreadyP := false.B }
+  when(dut.peripheral.AWVALID && dut.peripheral.AWREADY) { awreadyP := false.B }
   .elsewhen(dut.peripheral.BVALID && dut.peripheral.BREADY) { awreadyP := true.B }
 
   when(dut.peripheral.AWVALID && dut.peripheral.AWREADY) { wreadyP := true.B }
diff --git a/src/main/scala/decode/constants.scala b/src/main/scala/decode/constants.scala
index 62f143b..13899e2 100644
--- a/src/main/scala/decode/constants.scala
+++ b/src/main/scala/decode/constants.scala
@@ -33,5 +33,5 @@ object constants {
   val rdWidth = 5
   val opcodeWidth = 7
 
-  val initialPC = "h7ffffffc"       // h80000000 - 4
+  val initialPC = "h000ffffc"       // h80000000 - 4
 }
diff --git a/src/main/scala/decode/decode.scala b/src/main/scala/decode/decode.scala
index f99f491..d2e2dca 100644
--- a/src/main/scala/decode/decode.scala
+++ b/src/main/scala/decode/decode.scala
@@ -118,11 +118,11 @@ class decode extends Module {
   ))
   val isFetchBranch = WireDefault(false.B)            /** Branch instruction in fetchIssueBuffer */
 
-//  val isCSR        = WireDefault(false.B)
-//  val waitToCommit = WireDefault(false.B)
-//  val csrDone      = RegInit(false.B)
-//  val issueRobBuff = RegInit(0.U(robAddrWidth.W))
-//  val commitRobBuf = RegInit(0.U(robAddrWidth.W))
+  val isCSR        = WireDefault(false.B)
+  val waitToCommit = WireDefault(false.B)
+  val csrDone      = RegInit(false.B)
+  val issueRobBuff = RegInit(0.U(robAddrWidth.W))
+  val commitRobBuf = RegInit(0.U(robAddrWidth.W))
 
   /** Initializing states for the FSMs for fetch buffer and decode buffer */
   val emptyState :: fullState :: Nil = Enum(2)        /** States of FSM */
@@ -212,13 +212,13 @@ class decode extends Module {
   val robFile = Reg(Vec(regCount, UInt(robAddrWidth.W)))
 
   /** Setting rs1 properties */
-  when(opcode === auipc.U || opcode === jump.U || opcode === jumpr.U) {
+  when(opcode === auipc.U || opcode === jump.U) {
     rs1.data         := pc
     rs1.robAddr      := 0.U
     valid.rs1Data    := true.B
     valid.rs1RobAddr := false.B
   }
-  when(opcode === load.U || opcode === store.U || opcode === rops.U || opcode === iops.U || opcode === rops32.U || opcode === iops32.U || opcode === cjump.U) {
+  when(opcode === load.U || opcode === store.U || opcode === rops.U || opcode === iops.U || opcode === rops32.U || opcode === iops32.U || opcode === cjump.U || opcode === jumpr.U || opcode === amos.U) {
     rs1.data         := registerFile(rs1Addr)
     rs1.robAddr      := robFile(rs1Addr)
     when(stateRegDecodeBuf === fullState) {                                                                   /** Check dependencies in adjacent instrucitons */
@@ -231,7 +231,13 @@ class decode extends Module {
   }
 
   /** Setting rs2 properties */
-  when(opcode === jumpr.U || opcode === jump.U) {
+  when(opcode === jumpr.U) {
+    rs2.data         := pc
+    rs2.robAddr      := 0.U
+    valid.rs2Data    := true.B
+    valid.rs2RobAddr := false.B
+  }
+  when(opcode === jump.U) {
     rs2.data         := 4.U
     rs2.robAddr      := 0.U
     valid.rs2Data    := true.B
@@ -256,7 +262,7 @@ class decode extends Module {
   }
 
   /** Setting rs2 properties for store instructions */
-  when(opcode === store.U) {
+  when(opcode === store.U || opcode === amos.U) {
     write.data         := registerFile(rs2Addr)
     write.robAddr      := robFile(rs2Addr)
     when(stateRegDecodeBuf === fullState) {                                                                   /** Check dependencies in adjacent instrucitons */
@@ -275,7 +281,7 @@ class decode extends Module {
       validBit(writeBackResult.rdAddr)    := 1.U
       robValidBit(writeBackResult.rdAddr) := 0.U
     }
-//    commitRobBuf           := writeBackResult.robAddr
+    commitRobBuf           := writeBackResult.robAddr
   }
   
   /** Rob File writing and deasserting valid bit for rd */
@@ -284,7 +290,7 @@ class decode extends Module {
       robFile(decodeIssueBuffer.instruction(11,7))     := toExec.robAddr
       robValidBit(decodeIssueBuffer.instruction(11,7)) := 1.U
       validBit(decodeIssueBuffer.instruction(11,7))    := 0.U
-//      issueRobBuff                                     := toExec.robAddr
+      issueRobBuff                                     := toExec.robAddr
     }
   }
 
@@ -308,11 +314,11 @@ class decode extends Module {
       }
     }
     is(fullState) {
-      when(stalled /* || (isCSR && !csrDone)*/) {
+      when(stalled || (isCSR && !csrDone)) {
         validOutFetchBuf := false.B
         readyOutFetchBuf := false.B
       } otherwise {
-        validOutFetchBuf := true.B /* !csrDone */
+        validOutFetchBuf := !csrDone
         when(readyOutDecodeBuf) {
           readyOutFetchBuf := true.B
           when(!fromFetch.fired || fromFetch.pc =/= fromFetch.expected.pc) {
@@ -390,47 +396,47 @@ class decode extends Module {
 
   /** CSR handling */
   /**--------------------------------------------------------------------------------------------------------------------*/
-//  isCSR := (opcode === system.U) && (fun3 === "b001".U || fun3 === "b010".U || fun3 === "b011".U || fun3 === "b101".U || fun3 === "b110".U || fun3 === "b111".U)
-//  waitToCommit := isCSR && (issueRobBuff =/= commitRobBuf) && !csrDone
-//
-//  val csrFile = RegInit(VecInit(Seq.fill(csrRegCount)(0.U(64.W))))
-//
-//  when(isCSR && !waitToCommit) {
-//    val csrReadData  = csrFile(immediate)
-//    val csrWriteData = registerFile(rs1Addr)
-//    val csrWriteImmediate = rs1Addr & "h0000_0000_0000_001f".U
-//    registerFile(writeBackResult.rdAddr) := csrReadData
-//    switch(fun3) {
-//      is("b001".U) {
-//        csrFile(immediate) := csrWriteData
-//      }
-//      is("b010".U) {
-//        csrFile(immediate) := csrReadData | csrWriteData
-//      }
-//      is("b011".U) {
-//        csrFile(immediate) := csrReadData & (~csrWriteData)
-//      }
-//      is("b101".U) {
-//        csrFile(immediate) := csrWriteImmediate
-//      }
-//      is("b110".U) {
-//        csrFile(immediate) := csrReadData | csrWriteImmediate
-//      }
-//      is("b111".U) {
-//        csrFile(immediate) := csrReadData & (~csrWriteImmediate)
-//      }
-//    }
-//    csrDone := true.B
-//  }
-//
-//  when(csrDone && fromFetch.fired && fromFetch.pc === fromFetch.expected.pc) {
-//    csrDone := false.B
-//  }
+  /* isCSR := (opcode === system.U) && (fun3 === "b001".U || fun3 === "b010".U || fun3 === "b011".U || fun3 === "b101".U || fun3 === "b110".U || fun3 === "b111".U)
+  waitToCommit := isCSR && (issueRobBuff =/= commitRobBuf) && !csrDone
+
+  val csrFile = RegInit(VecInit(Seq.fill(csrRegCount)(0.U(64.W))))
+
+  when(isCSR && !waitToCommit) {
+    val csrReadData  = csrFile(immediate)
+    val csrWriteData = registerFile(rs1Addr)
+    val csrWriteImmediate = rs1Addr & "h0000_0000_0000_001f".U
+    registerFile(writeBackResult.rdAddr) := csrReadData
+    switch(fun3) {
+      is("b001".U) {
+        csrFile(immediate) := csrWriteData
+      }
+      is("b010".U) {
+        csrFile(immediate) := csrReadData | csrWriteData
+      }
+      is("b011".U) {
+        csrFile(immediate) := csrReadData & (~csrWriteData)
+      }
+      is("b101".U) {
+        csrFile(immediate) := csrWriteImmediate
+      }
+      is("b110".U) {
+        csrFile(immediate) := csrReadData | csrWriteImmediate
+      }
+      is("b111".U) {
+        csrFile(immediate) := csrReadData & (~csrWriteImmediate)
+      }
+    }
+    csrDone := true.B
+  }
 
+  when(csrDone && fromFetch.fired && fromFetch.pc === fromFetch.expected.pc) {
+    csrDone := false.B
+  }
+ */
 
   /**--------------------------------------------------------------------------------------------------------------------*/
 }
 
 object DecodeUnit extends App{
   emitVerilog(new decode())
-}
+}
\ No newline at end of file
diff --git a/src/main/scala/exec/exec.scala b/src/main/scala/exec/exec.scala
index 33c23f3..d957a08 100644
--- a/src/main/scala/exec/exec.scala
+++ b/src/main/scala/exec/exec.scala
@@ -66,7 +66,7 @@ class exec extends Module {
     _.instruction -> 0.U
   ))
   val passToMem = RegInit(false.B)
-  toRob.ready := robPushBuffer.waiting && (robPushBuffer.instruction(6, 2) =/= "b00000".U)
+  toRob.ready := robPushBuffer.waiting && (robPushBuffer.instruction(6, 2) =/= "b00000".U && robPushBuffer.instruction(6, 2) =/= "b01011".U)
   toRob.robAddr := robPushBuffer.robAddr
   toRob.execResult := robPushBuffer.execResult
 
@@ -178,9 +178,9 @@ class exec extends Module {
     // possible place for resource optimization
     VecInit.tabulate(7)(i => i match {
       case 0 => (src1 + src2) // address calculation for memory access
-      case 1 => (src1 + src2) // jal link address
+      case 1 => (src2 + 4.U) // jal link address
       case 2 => (src1 + src2) //(63, 0) // filler
-      case 3 => (src1 + src2) //(63, 0) jalr link address
+      case 3 => Mux(instruction(6).asBool, (src1 + src2), src1) //(63, 0) jalr link address
       case 4 => arithmetic64 // (63, 0) op-imm, op
       case 5 => (src2 + Mux(instruction(5).asBool, 0.U, src1)) // (63, 0) // lui and auipc
       case 6 => arithmetic32 // op-32, op-imm-32
@@ -198,16 +198,16 @@ class exec extends Module {
 
   when(robPushBuffer.waiting) {
     // condition to deassert waiting(if true it has keep on waiting)
-    robPushBuffer.waiting := !toRob.fired || (!bufferedEntries(0).free && (bufferedEntries(0).instruction(6, 2) =/= BitPat("b00000")) && updateCurrentEntry)
+    robPushBuffer.waiting := !toRob.fired || (!bufferedEntries(0).free && (bufferedEntries(0).instruction(6, 2) =/= BitPat("b00000") && bufferedEntries(0).instruction(6, 2) =/= BitPat("b01011")) && (!passToMem || toMemory.fired))
   }.otherwise {
     // asserting waiting
-    robPushBuffer.waiting := !bufferedEntries(0).free && (bufferedEntries(0).instruction(6, 2) =/= BitPat("b00000") && updateCurrentEntry)
+    robPushBuffer.waiting := !bufferedEntries(0).free && ((bufferedEntries(0).instruction(6, 2) =/= BitPat("b00000") && bufferedEntries(0).instruction(6, 2) =/= BitPat("b01011")) && updateCurrentEntry)
   }
 
   when(passToMem) {
-    passToMem := !toMemory.fired || bufferedEntries(0).free || (bufferedEntries(0).instruction(6, 2) =/= BitPat("b0?000") && updateCurrentEntry)
+    passToMem := !toMemory.fired || (!bufferedEntries(0).free && (bufferedEntries(0).instruction(6, 2) === BitPat("b0?0??")) && (!robPushBuffer.waiting || toRob.fired))
   }.otherwise {
-    passToMem := !bufferedEntries(0).free && (bufferedEntries(0).instruction(6, 2) === BitPat("b0?000") && updateCurrentEntry)
+    passToMem := !bufferedEntries(0).free && (bufferedEntries(0).instruction(6, 2) === BitPat("b0?0??") && updateCurrentEntry)
   }
 }
 
diff --git a/src/main/scala/fetch/fetch.scala b/src/main/scala/fetch/fetch.scala
index 96132e8..4aaf257 100644
--- a/src/main/scala/fetch/fetch.scala
+++ b/src/main/scala/fetch/fetch.scala
@@ -1,4 +1,5 @@
 import pipeline.fifo._
+import pipeline.ports._
 
 
 import chisel3._
@@ -69,7 +70,7 @@ class fetch(val fifo_size: Int) extends Module {
     */
 
   //register defs
-  val PC = RegInit(0.U(64.W))
+  val PC = RegInit("h00100000".U(64.W))
   val redirect_bit= RegInit(0.U(1.W))
   val handle_fenceI= RegInit(0.U(1.W))
   val clear_cache_req= RegInit(0.U(1.W))
diff --git a/src/main/scala/memAccess/memAccess.scala b/src/main/scala/memAccess/memAccess.scala
index 27452a6..eb53a0c 100644
--- a/src/main/scala/memAccess/memAccess.scala
+++ b/src/main/scala/memAccess/memAccess.scala
@@ -273,12 +273,13 @@ class memAccess extends Module{
 
   // peripheral request served
   when(peripheralRequestServed && (responseBuffers(0).free || peripheralRequest.instruction(5).asBool)) { peripheralRequest.free := true.B }
-  val cacheResponseJustified = dCache.resp.bits.byteAlignedData >> dCache.resp.bits.address(2, 0)
+  val cacheResponseJustified = dCache.resp.bits.byteAlignedData >> VecInit.tabulate(8)(i => (8*i).U)(dCache.resp.bits.address(2, 0))
 
   // filling the response buffers
-  when(toRob.fired && !responseBuffers(0).free) {
+  when(responseBuffers(0).free || toRob.fired) {
     // current response in responseBuffers is full
     // buffered response is given priority
+    responseBuffers(0).free := false.B
     when(!responseBuffers(1).free) {
       // clearing buffered response
       responseBuffers(0) := responseBuffers(1)
@@ -323,6 +324,20 @@ class memAccess extends Module{
 
   // after commiting all requests to memory, wait for next access
   when(cleanAllCacheLines.ready && cleanAllCacheLines.fired) { waitingAllReqToFinish := false.B }
+
+  when(reqBuffer.free) {
+    reqBuffer.free := !(fromPipeline.fired && ((entryType === peripheral && !peripheralRequest.free) || (entryType === dramAccess && !dCache.req.ready)))
+    reqBuffer.entryType := entryType
+    reqBuffer.address := fromPipeline.address
+    reqBuffer.instruction := fromPipeline.instruction
+    reqBuffer.robAddr := fromPipeline.robAddr
+    reqBuffer.writeData := fromPipeline.writeData
+  }.otherwise {
+    switch(reqBuffer.entryType){
+      is(peripheral) { reqBuffer.free := peripheralRequest.free }
+      is(dram) { reqBuffer.free := dCache.req.ready }
+    }
+  }
 }
 
 object memAccess extends App {
diff --git a/src/main/scala/rob/rob.scala b/src/main/scala/rob/rob.scala
index 6c5ddc3..0366ad0 100644
--- a/src/main/scala/rob/rob.scala
+++ b/src/main/scala/rob/rob.scala
@@ -10,33 +10,6 @@ import pipeline.ports._
 import pipeline.configuration.coreConfiguration._
 import pipeline.fifo._
 
-class robAllocate extends composableInterface {
-  val instOpcode = Input(UInt(7.W))
-  val robAddr = Output(UInt(robAddrWidth.W))
-  val rd = Input(UInt(5.W))
-  val fwdrs1 = new Bundle {
-    val valid = Output(Bool())
-    val value = Output(UInt(64.W))
-    val robAddr = Input(UInt(robAddrWidth.W))
-  }
-  val fwdrs2 = new Bundle {
-    val valid = Output(Bool())
-    val value = Output(UInt(64.W))
-    val robAddr = Input(UInt(robAddrWidth.W))
-  }
-}
-
-class commitInstruction extends composableInterface{
-  val rd = Output(UInt(5.W))
-  val value = Output(UInt(64.W))
-  val opcode = Output(UInt(7.W))
-  val robAddr = Output(UInt(robAddrWidth.W))
-}
-
-class pullResultsToRob extends composableInterface {
-  val robAddr     = Input(UInt(robAddrWidth.W))
-  val execResult  = Input(UInt(64.W))
-}
 
 class rob extends Module {
   // defining ports
@@ -44,9 +17,9 @@ class rob extends Module {
 
   val fromDecode = IO(new robAllocate)
 
-  val fromExec = IO(new pullResultsToRob)
+  val fromExec = IO(new pullExecResultToRob)
 
-  val fromMem = IO(new pullResultsToRob)
+  val fromMem = IO(new pullMemResultToRob)
 
   val commit = IO(new commitInstruction)
 
@@ -54,15 +27,15 @@ class rob extends Module {
   // logic starts here
 
   // results fifo
-  // value(64 bits) | ready to commit (1 bit)
-  val results = Module(new randomAccessFifo(UInt(65.W),scala.math.pow(2,robAddrWidth).asInstanceOf[Int]))
+  // exception occured(1bit) | mcause(64 bits) | value(64 bits) | ready to commit (1 bit)
+  val results = Module(new randomAccessFifo(UInt(130.W),scala.math.pow(2,robAddrWidth).asInstanceOf[Int]))
   fromDecode.robAddr := results.addr
   results.io.enq.bits := 0.U
 
   // ordinary fifo
-  // opcode | rd
-  val fifo = Module(new regFifo(UInt(12.W), scala.math.pow(2, robAddrWidth).asInstanceOf[Int]))
-  fifo.io.enq.bits := Cat(fromDecode.instOpcode,fromDecode.rd)
+  // pc | opcode | rd
+  val fifo = Module(new regFifo(UInt(76.W), scala.math.pow(2, robAddrWidth).asInstanceOf[Int]))
+  fifo.io.enq.bits := Cat(0.U,Cat(fromDecode.instOpcode,fromDecode.rd))
   fifo.io.enq.valid := fromDecode.fired
 
   fromDecode.ready := results.io.enq.ready & fifo.io.enq.ready
@@ -78,17 +51,17 @@ class rob extends Module {
   fromDecode.fwdrs2.valid := results.forward2.data(0)
 
   // fence ready
-  carryOutFence.ready := !results.io.deq.valid
+  carryOutFence.ready := false.B //!results.io.deq.valid 
 
   // write results from exec
   fromExec.ready := true.B //results.io.deq.valid
-  results.writeportexec.data := Cat(fromExec.execResult,1.U(1.W))
+  results.writeportexec.data := Cat(0.U,Cat(fromExec.execResult,1.U(1.W)))
   results.writeportexec.addr := fromExec.robAddr
   results.writeportexec.valid := fromExec.fired
 
   // write results from mem
   fromMem.ready := results.io.deq.valid
-  results.writeportmem.data := Cat(fromMem.execResult, 1.U(1.W))
+  results.writeportmem.data := Cat(fromMem.writeBackData, 1.U(1.W))
   results.writeportmem.addr := fromMem.robAddr
   results.writeportmem.valid := fromMem.fired
 
@@ -111,8 +84,8 @@ class rob extends Module {
   }
 
   commit.ready := commitResultReady
-  commit.value := commitResult.value
-  commit.rd := commitResult.rd
+  commit.writeBackData := commitResult.value
+  commit.rdAddr := commitResult.rd
   commit.opcode := commitResult.opcode
   results.io.deq.ready := !commitResultReady && results.io.deq.bits(0).asBool
   fifo.io.deq.ready := !commitResultReady && results.io.deq.bits(0).asBool
@@ -129,6 +102,6 @@ class rob extends Module {
 
 }
 
-object Verilog extends App {
+object robVerilog extends App {
   (new chisel3.stage.ChiselStage).emitVerilog(new rob)
 }
diff --git a/verilator-tests/testbench/assembly_programs/a-amoadd_d.s b/verilator-tests/testbench/assembly_programs/a-amoadd_d.s
new file mode 100644
index 0000000..1c52aa2
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/a-amoadd_d.s
@@ -0,0 +1,108 @@
+#*****************************************************************************
+# amoadd_d.S
+#-----------------------------------------------------------------------------
+
+# Test amoadd.d instruction.
+
+
+# 1 "/home/kaveesha/riscv-tests/env/p/riscv_test.h" 1
+
+
+
+
+
+# 1 "/home/kaveesha/riscv-tests/env/p/../encoding.h" 1
+# 7 "/home/kaveesha/riscv-tests/env/p/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ua/amoadd_d.S" 2
+# 1 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ua/amoadd_d.S" 2
+
+.macro init; .endm
+.section .text.init; 
+
+_start: j test_2
+
+  test_2: li gp, 2; li a0, 0xffffffff80000000; li a1, 0xfffffffffffff800; la a3, amo_operand; sd a0, 0(a3); amoadd.d a4, a1, 0(a3);; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne a4, x7, fail;
+
+
+
+
+
+
+
+  test_3: li gp, 3; ld a5, 0(a3); li x7, ((0xffffffff7ffff800) & ((1 << (64 - 1) << 1) - 1)); bne a5, x7, fail;
+
+  # try again after a cache miss
+  test_4: li gp, 4; amoadd.d a4, a1, 0(a3);; li x7, ((0xffffffff7ffff800) & ((1 << (64 - 1) << 1) - 1)); bne a4, x7, fail;
+
+
+
+  test_5: li gp, 5; ld a5, 0(a3); li x7, ((0xffffffff7ffff000) & ((1 << (64 - 1) << 1) - 1)); bne a5, x7, fail;
+
+  bne x0, gp, pass; fail:   1: beqz gp, 1b; sll gp, gp, 1; or gp, gp, 1; li a7, 93; addi a0, gp, 0; sb a0, -1(zero); pass:   li gp, 1; li a7, 93; li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .size tohost, 8; .align 6; .global fromhost; fromhost: .dword 0; .size fromhost, 8; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+.align 4; .global end_signature; end_signature:
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
diff --git a/verilator-tests/testbench/assembly_programs/a-amoadd_w.s b/verilator-tests/testbench/assembly_programs/a-amoadd_w.s
new file mode 100644
index 0000000..c03c9d0
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/a-amoadd_w.s
@@ -0,0 +1,115 @@
+# 0 "../../riscv-tests/isa/rv64ua/amoadd_w.S"
+# 0 "<built-in>"
+# 0 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ua/amoadd_w.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoadd_w.S
+#-----------------------------------------------------------------------------
+
+# Test amoadd.w instruction.
+
+
+# 1 "/home/kaveesha/riscv-tests/env/p/riscv_test.h" 1
+
+
+
+
+
+# 1 "/home/kaveesha/riscv-tests/env/p/../encoding.h" 1
+# 7 "/home/kaveesha/riscv-tests/env/p/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ua/amoadd_w.S" 2
+# 1 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ua/amoadd_w.S" 2
+
+.macro init; .endm
+.section .text.init; 
+
+_start: j test_2
+
+  test_2: li gp, 2; li a0, 0xffffffff80000000; li a1, 0xfffffffffffff800; la a3, amo_operand; sw a0, 0(a3); amoadd.w a4, a1, 0(a3);; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne a4, x7, fail;
+
+
+
+
+
+
+
+  test_3: li gp, 3; lw a5, 0(a3); li x7, ((0x000000007ffff800) & ((1 << (64 - 1) << 1) - 1)); bne a5, x7, fail;
+
+  # try again after a cache miss
+  test_4: li gp, 4; li a1, 0xffffffff80000000; amoadd.w a4, a1, 0(a3);; li x7, ((0x000000007ffff800) & ((1 << (64 - 1) << 1) - 1)); bne a4, x7, fail;
+
+
+
+
+  test_5: li gp, 5; lw a5, 0(a3); li x7, ((0xfffffffffffff800) & ((1 << (64 - 1) << 1) - 1)); bne a5, x7, fail;
+
+  bne x0, gp, pass; fail:   1: beqz gp, 1b; sll gp, gp, 1; or gp, gp, 1; li a7, 93; addi a0, gp, 0; sb a0, -1(zero); pass:   li gp, 1; li a7, 93; li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .size tohost, 8; .align 6; .global fromhost; fromhost: .dword 0; .size fromhost, 8; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+.align 4; .global end_signature; end_signature:
+
+    .bss
+    .align 3
+amo_operand:
+    .dword 0
diff --git a/verilator-tests/testbench/assembly_programs/a-amoand_d.s b/verilator-tests/testbench/assembly_programs/a-amoand_d.s
new file mode 100644
index 0000000..2657523
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/a-amoand_d.s
@@ -0,0 +1,115 @@
+# 0 "../../riscv-tests/isa/rv64ua/amoand_d.S"
+# 0 "<built-in>"
+# 0 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ua/amoand_d.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoand_d.S
+#-----------------------------------------------------------------------------
+
+# Test amoand.d instruction.
+
+
+# 1 "/home/kaveesha/riscv-tests/env/p/riscv_test.h" 1
+
+
+
+
+
+# 1 "/home/kaveesha/riscv-tests/env/p/../encoding.h" 1
+# 7 "/home/kaveesha/riscv-tests/env/p/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ua/amoand_d.S" 2
+# 1 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ua/amoand_d.S" 2
+
+.macro init; .endm
+.section .text.init; 
+
+_start: j test_2
+
+  test_2: li gp, 2; li a0, 0xffffffff80000000; li a1, 0xfffffffffffff800; la a3, amo_operand; sd a0, 0(a3); amoand.d a4, a1, 0(a3);; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne a4, x7, fail;
+
+
+
+
+
+
+
+  test_3: li gp, 3; ld a5, 0(a3); li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne a5, x7, fail;
+
+  # try again after a cache miss
+  test_4: li gp, 4; li a1, 0x0000000080000000; amoand.d a4, a1, 0(a3);; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne a4, x7, fail;
+
+
+
+
+  test_5: li gp, 5; ld a5, 0(a3); li x7, ((0x0000000080000000) & ((1 << (64 - 1) << 1) - 1)); bne a5, x7, fail;
+
+  bne x0, gp, pass; fail:   1: beqz gp, 1b; sll gp, gp, 1; or gp, gp, 1; li a7, 93; addi a0, gp, 0; sb a0, -1(zero); pass:   li gp, 1; li a7, 93; li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .size tohost, 8; .align 6; .global fromhost; fromhost: .dword 0; .size fromhost, 8; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+.align 4; .global end_signature; end_signature:
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
diff --git a/verilator-tests/testbench/assembly_programs/a-amoand_w.s b/verilator-tests/testbench/assembly_programs/a-amoand_w.s
new file mode 100644
index 0000000..9f19b10
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/a-amoand_w.s
@@ -0,0 +1,115 @@
+# 0 "../../riscv-tests/isa/rv64ua/amoand_w.S"
+# 0 "<built-in>"
+# 0 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ua/amoand_w.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoand.w.S
+#-----------------------------------------------------------------------------
+
+# Test amoand.w instruction.
+
+
+# 1 "/home/kaveesha/riscv-tests/env/p/riscv_test.h" 1
+
+
+
+
+
+# 1 "/home/kaveesha/riscv-tests/env/p/../encoding.h" 1
+# 7 "/home/kaveesha/riscv-tests/env/p/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ua/amoand_w.S" 2
+# 1 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ua/amoand_w.S" 2
+
+.macro init; .endm
+.section .text.init; 
+
+_start: j test_2
+
+  test_2: li gp, 2; li a0, 0xffffffff80000000; li a1, 0xfffffffffffff800; la a3, amo_operand; sw a0, 0(a3); amoand.w a4, a1, 0(a3);; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne a4, x7, fail;
+
+
+
+
+
+
+
+  test_3: li gp, 3; lw a5, 0(a3); li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne a5, x7, fail;
+
+  # try again after a cache miss
+  test_4: li gp, 4; li a1, 0x0000000080000000; amoand.w a4, a1, 0(a3);; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne a4, x7, fail;
+
+
+
+
+  test_5: li gp, 5; lw a5, 0(a3); li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne a5, x7, fail;
+
+  bne x0, gp, pass; fail:   1: beqz gp, 1b; sll gp, gp, 1; or gp, gp, 1; li a7, 93; addi a0, gp, 0; sb a0, -1(zero); pass:   li gp, 1; li a7, 93; li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .size tohost, 8; .align 6; .global fromhost; fromhost: .dword 0; .size fromhost, 8; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+.align 4; .global end_signature; end_signature:
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
diff --git a/verilator-tests/testbench/assembly_programs/a-amomax_d.s b/verilator-tests/testbench/assembly_programs/a-amomax_d.s
new file mode 100644
index 0000000..3f0873f
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/a-amomax_d.s
@@ -0,0 +1,115 @@
+# 0 "../../riscv-tests/isa/rv64ua/amomax_d.S"
+# 0 "<built-in>"
+# 0 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ua/amomax_d.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amomax_d.S
+#-----------------------------------------------------------------------------
+
+# Test amomax.d instruction.
+
+
+# 1 "/home/kaveesha/riscv-tests/env/p/riscv_test.h" 1
+
+
+
+
+
+# 1 "/home/kaveesha/riscv-tests/env/p/../encoding.h" 1
+# 7 "/home/kaveesha/riscv-tests/env/p/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ua/amomax_d.S" 2
+# 1 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ua/amomax_d.S" 2
+
+.macro init; .endm
+.section .text.init; 
+
+_start: j test_2
+
+  test_2: li gp, 2; li a0, 0xffffffff80000000; li a1, 0xfffffffffffff800; la a3, amo_operand; sd a0, 0(a3); amomax.d a4, a1, 0(a3);; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne a4, x7, fail;
+
+
+
+
+
+
+
+  test_3: li gp, 3; ld a5, 0(a3); li x7, ((0xfffffffffffff800) & ((1 << (64 - 1) << 1) - 1)); bne a5, x7, fail;
+
+  test_4: li gp, 4; li a1, 1; sd x0, 0(a3); amomax.d a4, a1, 0(a3);; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne a4, x7, fail;
+
+
+
+
+
+  test_5: li gp, 5; ld a5, 0(a3); li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne a5, x7, fail;
+
+  bne x0, gp, pass; fail:   1: beqz gp, 1b; sll gp, gp, 1; or gp, gp, 1; li a7, 93; addi a0, gp, 0; sb a0, -1(zero); pass:   li gp, 1; li a7, 93; li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .size tohost, 8; .align 6; .global fromhost; fromhost: .dword 0; .size fromhost, 8; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+.align 4; .global end_signature; end_signature:
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
diff --git a/verilator-tests/testbench/assembly_programs/a-amomax_w.s b/verilator-tests/testbench/assembly_programs/a-amomax_w.s
new file mode 100644
index 0000000..a4ed5c4
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/a-amomax_w.s
@@ -0,0 +1,115 @@
+# 0 "../../riscv-tests/isa/rv64ua/amomax_w.S"
+# 0 "<built-in>"
+# 0 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ua/amomax_w.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amomax_d.S
+#-----------------------------------------------------------------------------
+
+# Test amomax.w instruction.
+
+
+# 1 "/home/kaveesha/riscv-tests/env/p/riscv_test.h" 1
+
+
+
+
+
+# 1 "/home/kaveesha/riscv-tests/env/p/../encoding.h" 1
+# 7 "/home/kaveesha/riscv-tests/env/p/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ua/amomax_w.S" 2
+# 1 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ua/amomax_w.S" 2
+
+.macro init; .endm
+.section .text.init; 
+
+_start: j test_2
+
+  test_2: li gp, 2; li a0, 0xffffffff80000000; li a1, 0xfffffffffffff800; la a3, amo_operand; sw a0, 0(a3); amomax.w a4, a1, 0(a3);; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne a4, x7, fail;
+
+
+
+
+
+
+
+  test_3: li gp, 3; lw a5, 0(a3); li x7, ((0xfffffffffffff800) & ((1 << (64 - 1) << 1) - 1)); bne a5, x7, fail;
+
+  test_4: li gp, 4; li a1, 1; sw x0, 0(a3); amomax.w a4, a1, 0(a3);; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne a4, x7, fail;
+
+
+
+
+
+  test_5: li gp, 5; lw a5, 0(a3); li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne a5, x7, fail;
+
+  bne x0, gp, pass; fail:   1: beqz gp, 1b; sll gp, gp, 1; or gp, gp, 1; li a7, 93; addi a0, gp, 0; sb a0, -1(zero); pass:   li gp, 1; li a7, 93; li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .size tohost, 8; .align 6; .global fromhost; fromhost: .dword 0; .size fromhost, 8; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+.align 4; .global end_signature; end_signature:
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
diff --git a/verilator-tests/testbench/assembly_programs/a-amomaxu_d.s b/verilator-tests/testbench/assembly_programs/a-amomaxu_d.s
new file mode 100644
index 0000000..5bb6958
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/a-amomaxu_d.s
@@ -0,0 +1,115 @@
+# 0 "../../riscv-tests/isa/rv64ua/amomaxu_d.S"
+# 0 "<built-in>"
+# 0 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ua/amomaxu_d.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amomaxu_d.S
+#-----------------------------------------------------------------------------
+
+# Test amomaxu.d instruction.
+
+
+# 1 "/home/kaveesha/riscv-tests/env/p/riscv_test.h" 1
+
+
+
+
+
+# 1 "/home/kaveesha/riscv-tests/env/p/../encoding.h" 1
+# 7 "/home/kaveesha/riscv-tests/env/p/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ua/amomaxu_d.S" 2
+# 1 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ua/amomaxu_d.S" 2
+
+.macro init; .endm
+.section .text.init; 
+
+_start: j test_2
+
+  test_2: li gp, 2; li a0, 0xffffffff80000000; li a1, 0xfffffffffffff800; la a3, amo_operand; sd a0, 0(a3); amomaxu.d a4, a1, 0(a3);; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne a4, x7, fail;
+
+
+
+
+
+
+
+  test_3: li gp, 3; ld a5, 0(a3); li x7, ((0xfffffffffffff800) & ((1 << (64 - 1) << 1) - 1)); bne a5, x7, fail;
+
+  test_4: li gp, 4; li a1, 0xffffffffffffffff; sd x0, 0(a3); amomaxu.d a4, a1, 0(a3);; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne a4, x7, fail;
+
+
+
+
+
+  test_5: li gp, 5; ld a5, 0(a3); li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne a5, x7, fail;
+
+  bne x0, gp, pass; fail:   1: beqz gp, 1b; sll gp, gp, 1; or gp, gp, 1; li a7, 93; addi a0, gp, 0; sb a0, -1(zero); pass:   li gp, 1; li a7, 93; li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .size tohost, 8; .align 6; .global fromhost; fromhost: .dword 0; .size fromhost, 8; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+.align 4; .global end_signature; end_signature:
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
diff --git a/verilator-tests/testbench/assembly_programs/a-amomaxu_w.s b/verilator-tests/testbench/assembly_programs/a-amomaxu_w.s
new file mode 100644
index 0000000..cf6870c
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/a-amomaxu_w.s
@@ -0,0 +1,115 @@
+# 0 "../../riscv-tests/isa/rv64ua/amomaxu_w.S"
+# 0 "<built-in>"
+# 0 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ua/amomaxu_w.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amomaxu_d.S
+#-----------------------------------------------------------------------------
+
+# Test amomaxu.w instruction.
+
+
+# 1 "/home/kaveesha/riscv-tests/env/p/riscv_test.h" 1
+
+
+
+
+
+# 1 "/home/kaveesha/riscv-tests/env/p/../encoding.h" 1
+# 7 "/home/kaveesha/riscv-tests/env/p/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ua/amomaxu_w.S" 2
+# 1 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ua/amomaxu_w.S" 2
+
+.macro init; .endm
+.section .text.init; 
+
+_start: j test_2
+
+  test_2: li gp, 2; li a0, 0xffffffff80000000; li a1, 0xfffffffffffff800; la a3, amo_operand; sw a0, 0(a3); amomaxu.w a4, a1, 0(a3);; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne a4, x7, fail;
+
+
+
+
+
+
+
+  test_3: li gp, 3; lw a5, 0(a3); li x7, ((0xfffffffffffff800) & ((1 << (64 - 1) << 1) - 1)); bne a5, x7, fail;
+
+  test_4: li gp, 4; li a1, 0xffffffffffffffff; sw x0, 0(a3); amomaxu.w a4, a1, 0(a3);; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne a4, x7, fail;
+
+
+
+
+
+  test_5: li gp, 5; lw a5, 0(a3); li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne a5, x7, fail;
+
+  bne x0, gp, pass; fail:   1: beqz gp, 1b; sll gp, gp, 1; or gp, gp, 1; li a7, 93; addi a0, gp, 0; sb a0, -1(zero); pass:   li gp, 1; li a7, 93; li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .size tohost, 8; .align 6; .global fromhost; fromhost: .dword 0; .size fromhost, 8; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+.align 4; .global end_signature; end_signature:
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
diff --git a/verilator-tests/testbench/assembly_programs/a-amomin_d.s b/verilator-tests/testbench/assembly_programs/a-amomin_d.s
new file mode 100644
index 0000000..9f68e63
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/a-amomin_d.s
@@ -0,0 +1,115 @@
+# 0 "../../riscv-tests/isa/rv64ua/amomin_d.S"
+# 0 "<built-in>"
+# 0 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ua/amomin_d.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amomin_d.S
+#-----------------------------------------------------------------------------
+
+# Test amomin.d instruction.
+
+
+# 1 "/home/kaveesha/riscv-tests/env/p/riscv_test.h" 1
+
+
+
+
+
+# 1 "/home/kaveesha/riscv-tests/env/p/../encoding.h" 1
+# 7 "/home/kaveesha/riscv-tests/env/p/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ua/amomin_d.S" 2
+# 1 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ua/amomin_d.S" 2
+
+.macro init; .endm
+.section .text.init; 
+
+_start: j test_2
+
+  test_2: li gp, 2; li a0, 0xffffffff80000000; li a1, 0xfffffffffffff800; la a3, amo_operand; sd a0, 0(a3); amomin.d a4, a1, 0(a3);; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne a4, x7, fail;
+
+
+
+
+
+
+
+  test_3: li gp, 3; ld a5, 0(a3); li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne a5, x7, fail;
+
+  test_4: li gp, 4; li a1, 0xffffffffffffffff; sd x0, 0(a3); amomin.d a4, a1, 0(a3);; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne a4, x7, fail;
+
+
+
+
+
+  test_5: li gp, 5; ld a5, 0(a3); li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne a5, x7, fail;
+
+  bne x0, gp, pass; fail:   1: beqz gp, 1b; sll gp, gp, 1; or gp, gp, 1; li a7, 93; addi a0, gp, 0; sb a0, -1(zero); pass:   li gp, 1; li a7, 93; li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .size tohost, 8; .align 6; .global fromhost; fromhost: .dword 0; .size fromhost, 8; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+.align 4; .global end_signature; end_signature:
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
diff --git a/verilator-tests/testbench/assembly_programs/a-amomin_w.s b/verilator-tests/testbench/assembly_programs/a-amomin_w.s
new file mode 100644
index 0000000..c9c09ed
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/a-amomin_w.s
@@ -0,0 +1,115 @@
+# 0 "../../riscv-tests/isa/rv64ua/amomin_w.S"
+# 0 "<built-in>"
+# 0 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ua/amomin_w.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amomin_d.S
+#-----------------------------------------------------------------------------
+
+# Test amomin.w instruction.
+
+
+# 1 "/home/kaveesha/riscv-tests/env/p/riscv_test.h" 1
+
+
+
+
+
+# 1 "/home/kaveesha/riscv-tests/env/p/../encoding.h" 1
+# 7 "/home/kaveesha/riscv-tests/env/p/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ua/amomin_w.S" 2
+# 1 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ua/amomin_w.S" 2
+
+.macro init; .endm
+.section .text.init; 
+
+_start: j test_2
+
+  test_2: li gp, 2; li a0, 0xffffffff80000000; li a1, 0xfffffffffffff800; la a3, amo_operand; sw a0, 0(a3); amomin.w a4, a1, 0(a3);; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne a4, x7, fail;
+
+
+
+
+
+
+
+  test_3: li gp, 3; lw a5, 0(a3); li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne a5, x7, fail;
+
+  test_4: li gp, 4; li a1, 0xffffffffffffffff; sw x0, 0(a3); amomin.w a4, a1, 0(a3);; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne a4, x7, fail;
+
+
+
+
+
+  test_5: li gp, 5; lw a5, 0(a3); li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne a5, x7, fail;
+
+  bne x0, gp, pass; fail:   1: beqz gp, 1b; sll gp, gp, 1; or gp, gp, 1; li a7, 93; addi a0, gp, 0; sb a0, -1(zero); pass:   li gp, 1; li a7, 93; li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .size tohost, 8; .align 6; .global fromhost; fromhost: .dword 0; .size fromhost, 8; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+.align 4; .global end_signature; end_signature:
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
diff --git a/verilator-tests/testbench/assembly_programs/a-amominu_d.s b/verilator-tests/testbench/assembly_programs/a-amominu_d.s
new file mode 100644
index 0000000..a39082a
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/a-amominu_d.s
@@ -0,0 +1,115 @@
+# 0 "../../riscv-tests/isa/rv64ua/amominu_d.S"
+# 0 "<built-in>"
+# 0 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ua/amominu_d.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amominu_d.S
+#-----------------------------------------------------------------------------
+
+# Test amominu.d instruction.
+
+
+# 1 "/home/kaveesha/riscv-tests/env/p/riscv_test.h" 1
+
+
+
+
+
+# 1 "/home/kaveesha/riscv-tests/env/p/../encoding.h" 1
+# 7 "/home/kaveesha/riscv-tests/env/p/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ua/amominu_d.S" 2
+# 1 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ua/amominu_d.S" 2
+
+.macro init; .endm
+.section .text.init; 
+
+_start: j test_2
+
+  test_2: li gp, 2; li a0, 0xffffffff80000000; li a1, 0xfffffffffffff800; la a3, amo_operand; sd a0, 0(a3); amominu.d a4, a1, 0(a3);; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne a4, x7, fail;
+
+
+
+
+
+
+
+  test_3: li gp, 3; ld a5, 0(a3); li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne a5, x7, fail;
+
+  test_4: li gp, 4; li a1, 0xffffffffffffffff; sd x0, 0(a3); amominu.d a4, a1, 0(a3);; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne a4, x7, fail;
+
+
+
+
+
+  test_5: li gp, 5; ld a5, 0(a3); li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne a5, x7, fail;
+
+  bne x0, gp, pass; fail:   1: beqz gp, 1b; sll gp, gp, 1; or gp, gp, 1; li a7, 93; addi a0, gp, 0; sb a0, -1(zero); pass:   li gp, 1; li a7, 93; li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .size tohost, 8; .align 6; .global fromhost; fromhost: .dword 0; .size fromhost, 8; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+.align 4; .global end_signature; end_signature:
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
diff --git a/verilator-tests/testbench/assembly_programs/a-amominu_w.s b/verilator-tests/testbench/assembly_programs/a-amominu_w.s
new file mode 100644
index 0000000..0118c7c
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/a-amominu_w.s
@@ -0,0 +1,115 @@
+# 0 "../../riscv-tests/isa/rv64ua/amominu_w.S"
+# 0 "<built-in>"
+# 0 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ua/amominu_w.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amominu_d.S
+#-----------------------------------------------------------------------------
+
+# Test amominu.w instruction.
+
+
+# 1 "/home/kaveesha/riscv-tests/env/p/riscv_test.h" 1
+
+
+
+
+
+# 1 "/home/kaveesha/riscv-tests/env/p/../encoding.h" 1
+# 7 "/home/kaveesha/riscv-tests/env/p/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ua/amominu_w.S" 2
+# 1 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ua/amominu_w.S" 2
+
+.macro init; .endm
+.section .text.init; 
+
+_start: j test_2
+
+  test_2: li gp, 2; li a0, 0xffffffff80000000; li a1, 0xfffffffffffff800; la a3, amo_operand; sw a0, 0(a3); amominu.w a4, a1, 0(a3);; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne a4, x7, fail;
+
+
+
+
+
+
+
+  test_3: li gp, 3; lw a5, 0(a3); li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne a5, x7, fail;
+
+  test_4: li gp, 4; li a1, 0xffffffffffffffff; sw x0, 0(a3); amominu.w a4, a1, 0(a3);; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne a4, x7, fail;
+
+
+
+
+
+  test_5: li gp, 5; lw a5, 0(a3); li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne a5, x7, fail;
+
+  bne x0, gp, pass; fail:   1: beqz gp, 1b; sll gp, gp, 1; or gp, gp, 1; li a7, 93; addi a0, gp, 0; sb a0, -1(zero); pass:   li gp, 1; li a7, 93; li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .size tohost, 8; .align 6; .global fromhost; fromhost: .dword 0; .size fromhost, 8; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+.align 4; .global end_signature; end_signature:
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
diff --git a/verilator-tests/testbench/assembly_programs/a-amoor_d.s b/verilator-tests/testbench/assembly_programs/a-amoor_d.s
new file mode 100644
index 0000000..301c07c
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/a-amoor_d.s
@@ -0,0 +1,115 @@
+# 0 "../../riscv-tests/isa/rv64ua/amoor_d.S"
+# 0 "<built-in>"
+# 0 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ua/amoor_d.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoor_d.S
+#-----------------------------------------------------------------------------
+
+# Test amoor.d instruction.
+
+
+# 1 "/home/kaveesha/riscv-tests/env/p/riscv_test.h" 1
+
+
+
+
+
+# 1 "/home/kaveesha/riscv-tests/env/p/../encoding.h" 1
+# 7 "/home/kaveesha/riscv-tests/env/p/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ua/amoor_d.S" 2
+# 1 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ua/amoor_d.S" 2
+
+.macro init; .endm
+.section .text.init; 
+
+_start: j test_2
+
+  test_2: li gp, 2; li a0, 0xffffffff80000000; li a1, 0xfffffffffffff800; la a3, amo_operand; sd a0, 0(a3); amoor.d a4, a1, 0(a3);; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne a4, x7, fail;
+
+
+
+
+
+
+
+  test_3: li gp, 3; ld a5, 0(a3); li x7, ((0xfffffffffffff800) & ((1 << (64 - 1) << 1) - 1)); bne a5, x7, fail;
+
+  # try again after a cache miss
+  test_4: li gp, 4; li a1, 1; amoor.d a4, a1, 0(a3);; li x7, ((0xfffffffffffff800) & ((1 << (64 - 1) << 1) - 1)); bne a4, x7, fail;
+
+
+
+
+  test_5: li gp, 5; ld a5, 0(a3); li x7, ((0xfffffffffffff801) & ((1 << (64 - 1) << 1) - 1)); bne a5, x7, fail;
+
+  bne x0, gp, pass; fail:   1: beqz gp, 1b; sll gp, gp, 1; or gp, gp, 1; li a7, 93; addi a0, gp, 0; sb a0, -1(zero); pass:   li gp, 1; li a7, 93; li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .size tohost, 8; .align 6; .global fromhost; fromhost: .dword 0; .size fromhost, 8; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+.align 4; .global end_signature; end_signature:
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
diff --git a/verilator-tests/testbench/assembly_programs/a-amoor_w.s b/verilator-tests/testbench/assembly_programs/a-amoor_w.s
new file mode 100644
index 0000000..867da6a
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/a-amoor_w.s
@@ -0,0 +1,115 @@
+# 0 "../../riscv-tests/isa/rv64ua/amoor_w.S"
+# 0 "<built-in>"
+# 0 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ua/amoor_w.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoor.w.S
+#-----------------------------------------------------------------------------
+
+# Test amoor.w instruction.
+
+
+# 1 "/home/kaveesha/riscv-tests/env/p/riscv_test.h" 1
+
+
+
+
+
+# 1 "/home/kaveesha/riscv-tests/env/p/../encoding.h" 1
+# 7 "/home/kaveesha/riscv-tests/env/p/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ua/amoor_w.S" 2
+# 1 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ua/amoor_w.S" 2
+
+.macro init; .endm
+.section .text.init; 
+
+_start: j test_2
+
+  test_2: li gp, 2; li a0, 0xffffffff80000000; li a1, 0xfffffffffffff800; la a3, amo_operand; sw a0, 0(a3); amoor.w a4, a1, 0(a3);; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne a4, x7, fail;
+
+
+
+
+
+
+
+  test_3: li gp, 3; lw a5, 0(a3); li x7, ((0xfffffffffffff800) & ((1 << (64 - 1) << 1) - 1)); bne a5, x7, fail;
+
+  # try again after a cache miss
+  test_4: li gp, 4; li a1, 1; amoor.w a4, a1, 0(a3);; li x7, ((0xfffffffffffff800) & ((1 << (64 - 1) << 1) - 1)); bne a4, x7, fail;
+
+
+
+
+  test_5: li gp, 5; lw a5, 0(a3); li x7, ((0xfffffffffffff801) & ((1 << (64 - 1) << 1) - 1)); bne a5, x7, fail;
+
+  bne x0, gp, pass; fail:   1: beqz gp, 1b; sll gp, gp, 1; or gp, gp, 1; li a7, 93; addi a0, gp, 0; sb a0, -1(zero); pass:   li gp, 1; li a7, 93; li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .size tohost, 8; .align 6; .global fromhost; fromhost: .dword 0; .size fromhost, 8; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+.align 4; .global end_signature; end_signature:
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
diff --git a/verilator-tests/testbench/assembly_programs/a-amoswap_d.s b/verilator-tests/testbench/assembly_programs/a-amoswap_d.s
new file mode 100644
index 0000000..75bccb3
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/a-amoswap_d.s
@@ -0,0 +1,115 @@
+# 0 "../../riscv-tests/isa/rv64ua/amoswap_d.S"
+# 0 "<built-in>"
+# 0 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ua/amoswap_d.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoswap.d.S
+#-----------------------------------------------------------------------------
+
+# Test amoswap.d instruction.
+
+
+# 1 "/home/kaveesha/riscv-tests/env/p/riscv_test.h" 1
+
+
+
+
+
+# 1 "/home/kaveesha/riscv-tests/env/p/../encoding.h" 1
+# 7 "/home/kaveesha/riscv-tests/env/p/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ua/amoswap_d.S" 2
+# 1 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ua/amoswap_d.S" 2
+
+.macro init; .endm
+.section .text.init; 
+
+_start: j test_2
+
+  test_2: li gp, 2; li a0, 0xffffffff80000000; li a1, 0xfffffffffffff800; la a3, amo_operand; sd a0, 0(a3); amoswap.d a4, a1, 0(a3);; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne a4, x7, fail;
+
+
+
+
+
+
+
+  test_3: li gp, 3; ld a5, 0(a3); li x7, ((0xfffffffffffff800) & ((1 << (64 - 1) << 1) - 1)); bne a5, x7, fail;
+
+  # try again after a cache miss
+  test_4: li gp, 4; li a1, 0x0000000080000000; amoswap.d a4, a1, 0(a3);; li x7, ((0xfffffffffffff800) & ((1 << (64 - 1) << 1) - 1)); bne a4, x7, fail;
+
+
+
+
+  test_5: li gp, 5; ld a5, 0(a3); li x7, ((0x0000000080000000) & ((1 << (64 - 1) << 1) - 1)); bne a5, x7, fail;
+
+  bne x0, gp, pass; fail:   1: beqz gp, 1b; sll gp, gp, 1; or gp, gp, 1; li a7, 93; addi a0, gp, 0; sb a0, -1(zero); pass:   li gp, 1; li a7, 93; li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .size tohost, 8; .align 6; .global fromhost; fromhost: .dword 0; .size fromhost, 8; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+.align 4; .global end_signature; end_signature:
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
diff --git a/verilator-tests/testbench/assembly_programs/a-amoswap_w.s b/verilator-tests/testbench/assembly_programs/a-amoswap_w.s
new file mode 100644
index 0000000..eb8229f
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/a-amoswap_w.s
@@ -0,0 +1,115 @@
+# 0 "../../riscv-tests/isa/rv64ua/amoswap_w.S"
+# 0 "<built-in>"
+# 0 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ua/amoswap_w.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoswap_w.S
+#-----------------------------------------------------------------------------
+
+# Test amoswap.w instruction.
+
+
+# 1 "/home/kaveesha/riscv-tests/env/p/riscv_test.h" 1
+
+
+
+
+
+# 1 "/home/kaveesha/riscv-tests/env/p/../encoding.h" 1
+# 7 "/home/kaveesha/riscv-tests/env/p/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ua/amoswap_w.S" 2
+# 1 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ua/amoswap_w.S" 2
+
+.macro init; .endm
+.section .text.init; 
+
+_start: j test_2
+
+  test_2: li gp, 2; li a0, 0xffffffff80000000; li a1, 0xfffffffffffff800; la a3, amo_operand; sw a0, 0(a3); amoswap.w a4, a1, 0(a3);; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne a4, x7, fail;
+
+
+
+
+
+
+
+  test_3: li gp, 3; lw a5, 0(a3); li x7, ((0xfffffffffffff800) & ((1 << (64 - 1) << 1) - 1)); bne a5, x7, fail;
+
+  # try again after a cache miss
+  test_4: li gp, 4; li a1, 0x0000000080000000; amoswap.w a4, a1, 0(a3);; li x7, ((0xfffffffffffff800) & ((1 << (64 - 1) << 1) - 1)); bne a4, x7, fail;
+
+
+
+
+  test_5: li gp, 5; lw a5, 0(a3); li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne a5, x7, fail;
+
+  bne x0, gp, pass; fail:   1: beqz gp, 1b; sll gp, gp, 1; or gp, gp, 1; li a7, 93; addi a0, gp, 0; sb a0, -1(zero); pass:   li gp, 1; li a7, 93; li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .size tohost, 8; .align 6; .global fromhost; fromhost: .dword 0; .size fromhost, 8; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+.align 4; .global end_signature; end_signature:
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
diff --git a/verilator-tests/testbench/assembly_programs/a-amoxor_d.s b/verilator-tests/testbench/assembly_programs/a-amoxor_d.s
new file mode 100644
index 0000000..896ebf2
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/a-amoxor_d.s
@@ -0,0 +1,115 @@
+# 0 "../../riscv-tests/isa/rv64ua/amoxor_d.S"
+# 0 "<built-in>"
+# 0 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ua/amoxor_d.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoxor_d.S
+#-----------------------------------------------------------------------------
+
+# Test amoxor.d instruction.
+
+
+# 1 "/home/kaveesha/riscv-tests/env/p/riscv_test.h" 1
+
+
+
+
+
+# 1 "/home/kaveesha/riscv-tests/env/p/../encoding.h" 1
+# 7 "/home/kaveesha/riscv-tests/env/p/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ua/amoxor_d.S" 2
+# 1 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ua/amoxor_d.S" 2
+
+.macro init; .endm
+.section .text.init; 
+
+_start: j test_2
+
+  test_2: li gp, 2; li a0, 0xffffffff80000000; li a1, 0xfffffffffffff800; la a3, amo_operand; sd a0, 0(a3); amoxor.d a4, a1, 0(a3);; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne a4, x7, fail;
+
+
+
+
+
+
+
+  test_3: li gp, 3; ld a5, 0(a3); li x7, ((0x000000007ffff800) & ((1 << (64 - 1) << 1) - 1)); bne a5, x7, fail;
+
+  # try again after a cache miss
+  test_4: li gp, 4; li a1, 1; amoxor.d a4, a1, 0(a3);; li x7, ((0x000000007ffff800) & ((1 << (64 - 1) << 1) - 1)); bne a4, x7, fail;
+
+
+
+
+  test_5: li gp, 5; ld a5, 0(a3); li x7, ((0x000000007ffff801) & ((1 << (64 - 1) << 1) - 1)); bne a5, x7, fail;
+
+  bne x0, gp, pass; fail:   1: beqz gp, 1b; sll gp, gp, 1; or gp, gp, 1; li a7, 93; addi a0, gp, 0; sb a0, -1(zero); pass:   li gp, 1; li a7, 93; li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .size tohost, 8; .align 6; .global fromhost; fromhost: .dword 0; .size fromhost, 8; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+.align 4; .global end_signature; end_signature:
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
diff --git a/verilator-tests/testbench/assembly_programs/a-amoxor_w.s b/verilator-tests/testbench/assembly_programs/a-amoxor_w.s
new file mode 100644
index 0000000..c0016e5
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/a-amoxor_w.s
@@ -0,0 +1,115 @@
+# 0 "../../riscv-tests/isa/rv64ua/amoxor_w.S"
+# 0 "<built-in>"
+# 0 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ua/amoxor_w.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoxor_w.S
+#-----------------------------------------------------------------------------
+
+# Test amoxor.w instruction.
+
+
+# 1 "/home/kaveesha/riscv-tests/env/p/riscv_test.h" 1
+
+
+
+
+
+# 1 "/home/kaveesha/riscv-tests/env/p/../encoding.h" 1
+# 7 "/home/kaveesha/riscv-tests/env/p/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ua/amoxor_w.S" 2
+# 1 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ua/amoxor_w.S" 2
+
+.macro init; .endm
+.section .text.init; 
+
+_start: j test_2
+
+  test_2: li gp, 2; li a0, 0xffffffff80000000; li a1, 0xfffffffffffff800; la a3, amo_operand; sw a0, 0(a3); amoxor.w a4, a1, 0(a3);; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne a4, x7, fail;
+
+
+
+
+
+
+
+  test_3: li gp, 3; lw a5, 0(a3); li x7, ((0x7ffff800) & ((1 << (64 - 1) << 1) - 1)); bne a5, x7, fail;
+
+  # try again after a cache miss
+  test_4: li gp, 4; li a1, 0xc0000001; amoxor.w a4, a1, 0(a3);; li x7, ((0x7ffff800) & ((1 << (64 - 1) << 1) - 1)); bne a4, x7, fail;
+
+
+
+
+  test_5: li gp, 5; lw a5, 0(a3); li x7, ((0xffffffffbffff801) & ((1 << (64 - 1) << 1) - 1)); bne a5, x7, fail;
+
+  bne x0, gp, pass; fail:   1: beqz gp, 1b; sll gp, gp, 1; or gp, gp, 1; li a7, 93; addi a0, gp, 0; sb a0, -1(zero); pass:   li gp, 1; li a7, 93; li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .size tohost, 8; .align 6; .global fromhost; fromhost: .dword 0; .size fromhost, 8; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+.align 4; .global end_signature; end_signature:
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
diff --git a/verilator-tests/testbench/assembly_programs/a-lrsc.s b/verilator-tests/testbench/assembly_programs/a-lrsc.s
new file mode 100644
index 0000000..f7060c8
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/a-lrsc.s
@@ -0,0 +1,167 @@
+# 0 "../../riscv-tests/isa/rv64ua/lrsc.S"
+# 0 "<built-in>"
+# 0 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ua/lrsc.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# lrsr.S
+#-----------------------------------------------------------------------------
+
+# Test LR/SC instructions.
+
+
+# 1 "/home/kaveesha/riscv-tests/env/p/riscv_test.h" 1
+
+
+
+
+
+# 1 "/home/kaveesha/riscv-tests/env/p/../encoding.h" 1
+# 7 "/home/kaveesha/riscv-tests/env/p/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ua/lrsc.S" 2
+# 1 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "/home/kaveesha/riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ua/lrsc.S" 2
+
+.macro init; .endm
+.section .text.init; 
+
+
+
+ # get a unique core id
+_start: la a0, coreid
+li a1, 1
+amoadd.w a2, a1, (a0)
+
+# for now, only run this on core 0
+1:li a3, 1
+bgeu a2, a3, 1b
+
+1: lw a1, (a0)
+bltu a1, a3, 1b
+
+# make sure that sc without a reservation fails.
+test_2: li gp, 2; la a0, foo; li a5, 0xdeadbeef; sc.w a4, a5, (a0);; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne a4, x7, fail;
+
+
+
+
+
+ # make sure the failing sc did not commit into memory
+test_3: li gp, 3; lw a4, foo;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne a4, x7, fail;
+
+
+
+
+ # Disable test case 4 for now. It assumes a <1K reservation granule, when
+# in reality any size granule is valid. After discussion in issue #315,
+# decided to simply disable the test for now.
+# (See https:
+
+## make sure that sc with the wrong reservation fails.
+## TODO is this actually mandatory behavior?
+#test_4: li gp, 4; # la a0, foo; # la a1, fooTest3; # lr.w a1, (a1); # sc.w a4, a1, (a0); #; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne a4, x7, fail;
+# 57 "../../riscv-tests/isa/rv64ua/lrsc.S"
+ # have each core add its coreid+1 to foo 1024 times
+la a0, foo
+li a1, 1<<5
+addi a2, a2, 1
+1: lr.w a4, (a0)
+add a4, a4, a2
+sc.w a4, a4, (a0)
+bnez a4, 1b
+add a1, a1, -1
+bnez a1, 1b
+
+# wait for all cores to finish
+la a0, barrier
+li a1, 1
+amoadd.w x0, a1, (a0)
+1: lw a1, (a0)
+blt a1, a3, 1b
+
+# expected result is 512*ncores*(ncores+1)
+test_5: li gp, 5; lw a0, foo; slli a1, a3, 5 -1; 1:sub a0, a0, a1; addi a3, a3, -1; bgez a3, 1b; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne a0, x7, fail;
+
+
+
+
+
+
+
+ # make sure that sc-after-successful-sc fails.
+test_6: li gp, 6; la a0, foo; 1:lr.w a1, (a0); sc.w a1, x0, (a0); bnez a1, 1b; sc.w a1, x0, (a0); li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne a1, x7, fail;
+
+
+
+
+
+
+
+bne x0, gp, pass; fail: 1: beqz gp, 1b; sll gp, gp, 1; or gp, gp, 1; li a7, 93; addi a0, gp, 0; sb a0, -1(zero); pass: li gp, 1; li a7, 93; li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .size tohost, 8; .align 6; .global fromhost; fromhost: .dword 0; .size fromhost, 8; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+coreid: .word 0
+barrier: .word 0
+foo: .word 0
+.skip 1024
+fooTest3: .word 0
+.align 4; .global end_signature; end_signature:
diff --git a/verilator-tests/testbench/assembly_programs/add.s b/verilator-tests/testbench/assembly_programs/add.s
new file mode 100644
index 0000000..6e4a7c6
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/add.s
@@ -0,0 +1,160 @@
+# 1 "../../riscv-tests/isa/rv64ui/add.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/add.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# add.S
+#-----------------------------------------------------------------------------
+
+# Test add instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/add.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/add.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  test_2: li gp, 2; li x1, ((0x00000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x00000000) & ((1 << (64 - 1) << 1) - 1)); add x14, x1, x2;; li x7, ((0x00000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_3: li gp, 3; li x1, ((0x00000001) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x00000001) & ((1 << (64 - 1) << 1) - 1)); add x14, x1, x2;; li x7, ((0x00000002) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_4: li gp, 4; li x1, ((0x00000003) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x00000007) & ((1 << (64 - 1) << 1) - 1)); add x14, x1, x2;; li x7, ((0x0000000a) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_5: li gp, 5; li x1, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffff8000) & ((1 << (64 - 1) << 1) - 1)); add x14, x1, x2;; li x7, ((0xffffffffffff8000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_6: li gp, 6; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x00000000) & ((1 << (64 - 1) << 1) - 1)); add x14, x1, x2;; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_7: li gp, 7; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffff8000) & ((1 << (64 - 1) << 1) - 1)); add x14, x1, x2;; li x7, ((0xffffffff7fff8000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_8: li gp, 8; li x1, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0000000000007fff) & ((1 << (64 - 1) << 1) - 1)); add x14, x1, x2;; li x7, ((0x0000000000007fff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_9: li gp, 9; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); add x14, x1, x2;; li x7, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_10: li gp, 10; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0000000000007fff) & ((1 << (64 - 1) << 1) - 1)); add x14, x1, x2;; li x7, ((0x0000000080007ffe) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_11: li gp, 11; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0000000000007fff) & ((1 << (64 - 1) << 1) - 1)); add x14, x1, x2;; li x7, ((0xffffffff80007fff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_12: li gp, 12; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffff8000) & ((1 << (64 - 1) << 1) - 1)); add x14, x1, x2;; li x7, ((0x000000007fff7fff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_13: li gp, 13; li x1, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); add x14, x1, x2;; li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_14: li gp, 14; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); add x14, x1, x2;; li x7, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_15: li gp, 15; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); add x14, x1, x2;; li x7, ((0xfffffffffffffffe) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_16: li gp, 16; li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); add x14, x1, x2;; li x7, ((0x0000000080000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  test_17: li gp, 17; li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); add x1, x1, x2;; li x7, ((24) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_18: li gp, 18; li x1, ((14) & ((1 << (64 - 1) << 1) - 1)); li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); add x2, x1, x2;; li x7, ((25) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_19: li gp, 19; li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); add x1, x1, x1;; li x7, ((26) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_20: li gp, 20; li x4, 0; 1: li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); add x14, x1, x2; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((24) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_21: li gp, 21; li x4, 0; 1: li x1, ((14) & ((1 << (64 - 1) << 1) - 1)); li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); add x14, x1, x2; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((25) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_22: li gp, 22; li x4, 0; 1: li x1, ((15) & ((1 << (64 - 1) << 1) - 1)); li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); add x14, x1, x2; nop; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((26) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+
+  test_23: li gp, 23; li x4, 0; 1: li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); add x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((24) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_24: li gp, 24; li x4, 0; 1: li x1, ((14) & ((1 << (64 - 1) << 1) - 1)); li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); nop; add x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((25) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_25: li gp, 25; li x4, 0; 1: li x1, ((15) & ((1 << (64 - 1) << 1) - 1)); li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); nop; nop; add x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((26) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_26: li gp, 26; li x4, 0; 1: li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); nop; li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); add x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((24) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_27: li gp, 27; li x4, 0; 1: li x1, ((14) & ((1 << (64 - 1) << 1) - 1)); nop; li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); nop; add x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((25) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_28: li gp, 28; li x4, 0; 1: li x1, ((15) & ((1 << (64 - 1) << 1) - 1)); nop; nop; li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); add x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((26) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_29: li gp, 29; li x4, 0; 1: li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); add x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((24) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_30: li gp, 30; li x4, 0; 1: li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); li x1, ((14) & ((1 << (64 - 1) << 1) - 1)); nop; add x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((25) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_31: li gp, 31; li x4, 0; 1: li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); li x1, ((15) & ((1 << (64 - 1) << 1) - 1)); nop; nop; add x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((26) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_32: li gp, 32; li x4, 0; 1: li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); nop; li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); add x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((24) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_33: li gp, 33; li x4, 0; 1: li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); nop; li x1, ((14) & ((1 << (64 - 1) << 1) - 1)); nop; add x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((25) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_34: li gp, 34; li x4, 0; 1: li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); nop; nop; li x1, ((15) & ((1 << (64 - 1) << 1) - 1)); add x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((26) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_35: li gp, 35; li x1, ((15) & ((1 << (64 - 1) << 1) - 1)); add x2, x0, x1;; li x7, ((15) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_36: li gp, 36; li x1, ((32) & ((1 << (64 - 1) << 1) - 1)); add x2, x1, x0;; li x7, ((32) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_37: li gp, 37; add x1, x0, x0;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_38: li gp, 38; li x1, ((16) & ((1 << (64 - 1) << 1) - 1)); li x2, ((30) & ((1 << (64 - 1) << 1) - 1)); add x0, x1, x2;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x0, x7, fail;;
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+
diff --git a/verilator-tests/testbench/assembly_programs/addi.s b/verilator-tests/testbench/assembly_programs/addi.s
new file mode 100644
index 0000000..a2c391a
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/addi.s
@@ -0,0 +1,146 @@
+# 1 "../../riscv-tests/isa/rv64ui/addi.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/addi.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# addi.S
+#-----------------------------------------------------------------------------
+
+# Test addi instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/addi.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/addi.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  test_2: li gp, 2; li x1, ((0x00000000) & ((1 << (64 - 1) << 1) - 1)); addi x14, x1, ((0x000) | (-(((0x000) >> 11) & 1) << 11));; li x7, ((0x00000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_3: li gp, 3; li x1, ((0x00000001) & ((1 << (64 - 1) << 1) - 1)); addi x14, x1, ((0x001) | (-(((0x001) >> 11) & 1) << 11));; li x7, ((0x00000002) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_4: li gp, 4; li x1, ((0x00000003) & ((1 << (64 - 1) << 1) - 1)); addi x14, x1, ((0x007) | (-(((0x007) >> 11) & 1) << 11));; li x7, ((0x0000000a) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_5: li gp, 5; li x1, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); addi x14, x1, ((0x800) | (-(((0x800) >> 11) & 1) << 11));; li x7, ((0xfffffffffffff800) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_6: li gp, 6; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); addi x14, x1, ((0x000) | (-(((0x000) >> 11) & 1) << 11));; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_7: li gp, 7; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); addi x14, x1, ((0x800) | (-(((0x800) >> 11) & 1) << 11));; li x7, ((0xffffffff7ffff800) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_8: li gp, 8; li x1, ((0x00000000) & ((1 << (64 - 1) << 1) - 1)); addi x14, x1, ((0x7ff) | (-(((0x7ff) >> 11) & 1) << 11));; li x7, ((0x00000000000007ff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_9: li gp, 9; li x1, ((0x7fffffff) & ((1 << (64 - 1) << 1) - 1)); addi x14, x1, ((0x000) | (-(((0x000) >> 11) & 1) << 11));; li x7, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_10: li gp, 10; li x1, ((0x7fffffff) & ((1 << (64 - 1) << 1) - 1)); addi x14, x1, ((0x7ff) | (-(((0x7ff) >> 11) & 1) << 11));; li x7, ((0x00000000800007fe) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_11: li gp, 11; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); addi x14, x1, ((0x7ff) | (-(((0x7ff) >> 11) & 1) << 11));; li x7, ((0xffffffff800007ff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_12: li gp, 12; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); addi x14, x1, ((0x800) | (-(((0x800) >> 11) & 1) << 11));; li x7, ((0x000000007ffff7ff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_13: li gp, 13; li x1, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); addi x14, x1, ((0xfff) | (-(((0xfff) >> 11) & 1) << 11));; li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_14: li gp, 14; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); addi x14, x1, ((0x001) | (-(((0x001) >> 11) & 1) << 11));; li x7, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_15: li gp, 15; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); addi x14, x1, ((0xfff) | (-(((0xfff) >> 11) & 1) << 11));; li x7, ((0xfffffffffffffffe) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_16: li gp, 16; li x1, ((0x7fffffff) & ((1 << (64 - 1) << 1) - 1)); addi x14, x1, ((0x001) | (-(((0x001) >> 11) & 1) << 11));; li x7, ((0x0000000080000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  test_17: li gp, 17; li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); addi x1, x1, ((11) | (-(((11) >> 11) & 1) << 11));; li x7, ((24) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_18: li gp, 18; li x4, 0; 1: li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); addi x14, x1, ((11) | (-(((11) >> 11) & 1) << 11)); addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((24) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_19: li gp, 19; li x4, 0; 1: li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); addi x14, x1, ((10) | (-(((10) >> 11) & 1) << 11)); nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((23) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_20: li gp, 20; li x4, 0; 1: li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); addi x14, x1, ((9) | (-(((9) >> 11) & 1) << 11)); nop; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((22) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+
+  test_21: li gp, 21; li x4, 0; 1: li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); addi x14, x1, ((11) | (-(((11) >> 11) & 1) << 11)); addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((24) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_22: li gp, 22; li x4, 0; 1: li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); nop; addi x14, x1, ((10) | (-(((10) >> 11) & 1) << 11)); addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((23) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_23: li gp, 23; li x4, 0; 1: li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); nop; nop; addi x14, x1, ((9) | (-(((9) >> 11) & 1) << 11)); addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((22) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_24: li gp, 24; addi x1, x0, ((32) | (-(((32) >> 11) & 1) << 11));; li x7, ((32) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_25: li gp, 25; li x1, ((33) & ((1 << (64 - 1) << 1) - 1)); addi x0, x1, ((50) | (-(((50) >> 11) & 1) << 11));; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x0, x7, fail;;
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+
diff --git a/verilator-tests/testbench/assembly_programs/addiw.s b/verilator-tests/testbench/assembly_programs/addiw.s
new file mode 100644
index 0000000..6e93105
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/addiw.s
@@ -0,0 +1,146 @@
+# 1 "../../riscv-tests/isa/rv64ui/addiw.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/addiw.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# addiw.S
+#-----------------------------------------------------------------------------
+
+# Test addiw instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/addiw.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/addiw.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  test_2: li gp, 2; li x1, ((0x00000000) & ((1 << (64 - 1) << 1) - 1)); addiw x14, x1, ((0x000) | (-(((0x000) >> 11) & 1) << 11));; li x7, ((0x00000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_3: li gp, 3; li x1, ((0x00000001) & ((1 << (64 - 1) << 1) - 1)); addiw x14, x1, ((0x001) | (-(((0x001) >> 11) & 1) << 11));; li x7, ((0x00000002) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_4: li gp, 4; li x1, ((0x00000003) & ((1 << (64 - 1) << 1) - 1)); addiw x14, x1, ((0x007) | (-(((0x007) >> 11) & 1) << 11));; li x7, ((0x0000000a) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_5: li gp, 5; li x1, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); addiw x14, x1, ((0x800) | (-(((0x800) >> 11) & 1) << 11));; li x7, ((0xfffffffffffff800) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_6: li gp, 6; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); addiw x14, x1, ((0x000) | (-(((0x000) >> 11) & 1) << 11));; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_7: li gp, 7; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); addiw x14, x1, ((0x800) | (-(((0x800) >> 11) & 1) << 11));; li x7, ((0x000000007ffff800) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_8: li gp, 8; li x1, ((0x00000000) & ((1 << (64 - 1) << 1) - 1)); addiw x14, x1, ((0x7ff) | (-(((0x7ff) >> 11) & 1) << 11));; li x7, ((0x00000000000007ff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_9: li gp, 9; li x1, ((0x7fffffff) & ((1 << (64 - 1) << 1) - 1)); addiw x14, x1, ((0x000) | (-(((0x000) >> 11) & 1) << 11));; li x7, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_10: li gp, 10; li x1, ((0x7fffffff) & ((1 << (64 - 1) << 1) - 1)); addiw x14, x1, ((0x7ff) | (-(((0x7ff) >> 11) & 1) << 11));; li x7, ((0xffffffff800007fe) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_11: li gp, 11; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); addiw x14, x1, ((0x7ff) | (-(((0x7ff) >> 11) & 1) << 11));; li x7, ((0xffffffff800007ff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_12: li gp, 12; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); addiw x14, x1, ((0x800) | (-(((0x800) >> 11) & 1) << 11));; li x7, ((0x000000007ffff7ff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_13: li gp, 13; li x1, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); addiw x14, x1, ((0xfff) | (-(((0xfff) >> 11) & 1) << 11));; li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_14: li gp, 14; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); addiw x14, x1, ((0x001) | (-(((0x001) >> 11) & 1) << 11));; li x7, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_15: li gp, 15; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); addiw x14, x1, ((0xfff) | (-(((0xfff) >> 11) & 1) << 11));; li x7, ((0xfffffffffffffffe) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_16: li gp, 16; li x1, ((0x7fffffff) & ((1 << (64 - 1) << 1) - 1)); addiw x14, x1, ((0x001) | (-(((0x001) >> 11) & 1) << 11));; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  test_17: li gp, 17; li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); addiw x1, x1, ((11) | (-(((11) >> 11) & 1) << 11));; li x7, ((24) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_18: li gp, 18; li x4, 0; 1: li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); addiw x14, x1, ((11) | (-(((11) >> 11) & 1) << 11)); addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((24) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_19: li gp, 19; li x4, 0; 1: li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); addiw x14, x1, ((10) | (-(((10) >> 11) & 1) << 11)); nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((23) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_20: li gp, 20; li x4, 0; 1: li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); addiw x14, x1, ((9) | (-(((9) >> 11) & 1) << 11)); nop; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((22) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+
+  test_21: li gp, 21; li x4, 0; 1: li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); addiw x14, x1, ((11) | (-(((11) >> 11) & 1) << 11)); addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((24) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_22: li gp, 22; li x4, 0; 1: li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); nop; addiw x14, x1, ((10) | (-(((10) >> 11) & 1) << 11)); addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((23) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_23: li gp, 23; li x4, 0; 1: li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); nop; nop; addiw x14, x1, ((9) | (-(((9) >> 11) & 1) << 11)); addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((22) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_24: li gp, 24; addiw x1, x0, ((32) | (-(((32) >> 11) & 1) << 11));; li x7, ((32) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_25: li gp, 25; li x1, ((33) & ((1 << (64 - 1) << 1) - 1)); addiw x0, x1, ((50) | (-(((50) >> 11) & 1) << 11));; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x0, x7, fail;;
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+
diff --git a/verilator-tests/testbench/assembly_programs/addw.s b/verilator-tests/testbench/assembly_programs/addw.s
new file mode 100644
index 0000000..ab930be
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/addw.s
@@ -0,0 +1,160 @@
+# 1 "../../riscv-tests/isa/rv64ui/addw.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/addw.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# addw.S
+#-----------------------------------------------------------------------------
+
+# Test addw instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/addw.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/addw.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  test_2: li gp, 2; li x1, ((0x00000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x00000000) & ((1 << (64 - 1) << 1) - 1)); addw x14, x1, x2;; li x7, ((0x00000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_3: li gp, 3; li x1, ((0x00000001) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x00000001) & ((1 << (64 - 1) << 1) - 1)); addw x14, x1, x2;; li x7, ((0x00000002) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_4: li gp, 4; li x1, ((0x00000003) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x00000007) & ((1 << (64 - 1) << 1) - 1)); addw x14, x1, x2;; li x7, ((0x0000000a) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_5: li gp, 5; li x1, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffff8000) & ((1 << (64 - 1) << 1) - 1)); addw x14, x1, x2;; li x7, ((0xffffffffffff8000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_6: li gp, 6; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x00000000) & ((1 << (64 - 1) << 1) - 1)); addw x14, x1, x2;; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_7: li gp, 7; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffff8000) & ((1 << (64 - 1) << 1) - 1)); addw x14, x1, x2;; li x7, ((0x000000007fff8000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_8: li gp, 8; li x1, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0000000000007fff) & ((1 << (64 - 1) << 1) - 1)); addw x14, x1, x2;; li x7, ((0x0000000000007fff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_9: li gp, 9; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); addw x14, x1, x2;; li x7, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_10: li gp, 10; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0000000000007fff) & ((1 << (64 - 1) << 1) - 1)); addw x14, x1, x2;; li x7, ((0xffffffff80007ffe) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_11: li gp, 11; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0000000000007fff) & ((1 << (64 - 1) << 1) - 1)); addw x14, x1, x2;; li x7, ((0xffffffff80007fff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_12: li gp, 12; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffff8000) & ((1 << (64 - 1) << 1) - 1)); addw x14, x1, x2;; li x7, ((0x000000007fff7fff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_13: li gp, 13; li x1, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); addw x14, x1, x2;; li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_14: li gp, 14; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); addw x14, x1, x2;; li x7, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_15: li gp, 15; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); addw x14, x1, x2;; li x7, ((0xfffffffffffffffe) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_16: li gp, 16; li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); addw x14, x1, x2;; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  test_17: li gp, 17; li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); addw x1, x1, x2;; li x7, ((24) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_18: li gp, 18; li x1, ((14) & ((1 << (64 - 1) << 1) - 1)); li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); addw x2, x1, x2;; li x7, ((25) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_19: li gp, 19; li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); addw x1, x1, x1;; li x7, ((26) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_20: li gp, 20; li x4, 0; 1: li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); addw x14, x1, x2; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((24) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_21: li gp, 21; li x4, 0; 1: li x1, ((14) & ((1 << (64 - 1) << 1) - 1)); li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); addw x14, x1, x2; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((25) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_22: li gp, 22; li x4, 0; 1: li x1, ((15) & ((1 << (64 - 1) << 1) - 1)); li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); addw x14, x1, x2; nop; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((26) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+
+  test_23: li gp, 23; li x4, 0; 1: li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); addw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((24) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_24: li gp, 24; li x4, 0; 1: li x1, ((14) & ((1 << (64 - 1) << 1) - 1)); li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); nop; addw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((25) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_25: li gp, 25; li x4, 0; 1: li x1, ((15) & ((1 << (64 - 1) << 1) - 1)); li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); nop; nop; addw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((26) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_26: li gp, 26; li x4, 0; 1: li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); nop; li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); addw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((24) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_27: li gp, 27; li x4, 0; 1: li x1, ((14) & ((1 << (64 - 1) << 1) - 1)); nop; li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); nop; addw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((25) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_28: li gp, 28; li x4, 0; 1: li x1, ((15) & ((1 << (64 - 1) << 1) - 1)); nop; nop; li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); addw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((26) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_29: li gp, 29; li x4, 0; 1: li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); addw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((24) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_30: li gp, 30; li x4, 0; 1: li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); li x1, ((14) & ((1 << (64 - 1) << 1) - 1)); nop; addw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((25) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_31: li gp, 31; li x4, 0; 1: li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); li x1, ((15) & ((1 << (64 - 1) << 1) - 1)); nop; nop; addw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((26) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_32: li gp, 32; li x4, 0; 1: li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); nop; li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); addw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((24) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_33: li gp, 33; li x4, 0; 1: li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); nop; li x1, ((14) & ((1 << (64 - 1) << 1) - 1)); nop; addw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((25) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_34: li gp, 34; li x4, 0; 1: li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); nop; nop; li x1, ((15) & ((1 << (64 - 1) << 1) - 1)); addw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((26) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_35: li gp, 35; li x1, ((15) & ((1 << (64 - 1) << 1) - 1)); addw x2, x0, x1;; li x7, ((15) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_36: li gp, 36; li x1, ((32) & ((1 << (64 - 1) << 1) - 1)); addw x2, x1, x0;; li x7, ((32) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_37: li gp, 37; addw x1, x0, x0;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_38: li gp, 38; li x1, ((16) & ((1 << (64 - 1) << 1) - 1)); li x2, ((30) & ((1 << (64 - 1) << 1) - 1)); addw x0, x1, x2;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x0, x7, fail;;
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+
diff --git a/verilator-tests/testbench/assembly_programs/and.s b/verilator-tests/testbench/assembly_programs/and.s
new file mode 100644
index 0000000..bcabcbb
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/and.s
@@ -0,0 +1,144 @@
+# 1 "../../riscv-tests/isa/rv64ui/and.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/and.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# and.S
+#-----------------------------------------------------------------------------
+
+# Test and instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/and.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/and.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Logical tests
+  #-------------------------------------------------------------
+
+  test_2: li gp, 2; li x1, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0f0f0f0f) & ((1 << (64 - 1) << 1) - 1)); and x14, x1, x2;; li x7, ((0x0f000f00) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_3: li gp, 3; li x1, ((0x0ff00ff0) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xf0f0f0f0) & ((1 << (64 - 1) << 1) - 1)); and x14, x1, x2;; li x7, ((0x00f000f0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_4: li gp, 4; li x1, ((0x00ff00ff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0f0f0f0f) & ((1 << (64 - 1) << 1) - 1)); and x14, x1, x2;; li x7, ((0x000f000f) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_5: li gp, 5; li x1, ((0xf00ff00f) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xf0f0f0f0) & ((1 << (64 - 1) << 1) - 1)); and x14, x1, x2;; li x7, ((0xf000f000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  test_6: li gp, 6; li x1, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0f0f0f0f) & ((1 << (64 - 1) << 1) - 1)); and x1, x1, x2;; li x7, ((0x0f000f00) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_7: li gp, 7; li x1, ((0x0ff00ff0) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xf0f0f0f0) & ((1 << (64 - 1) << 1) - 1)); and x2, x1, x2;; li x7, ((0x00f000f0) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_8: li gp, 8; li x1, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); and x1, x1, x1;; li x7, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_9: li gp, 9; li x4, 0; 1: li x1, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0f0f0f0f) & ((1 << (64 - 1) << 1) - 1)); and x14, x1, x2; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0f000f00) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_10: li gp, 10; li x4, 0; 1: li x1, ((0x0ff00ff0) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xf0f0f0f0) & ((1 << (64 - 1) << 1) - 1)); and x14, x1, x2; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x00f000f0) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_11: li gp, 11; li x4, 0; 1: li x1, ((0x00ff00ff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0f0f0f0f) & ((1 << (64 - 1) << 1) - 1)); and x14, x1, x2; nop; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x000f000f) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+
+  test_12: li gp, 12; li x4, 0; 1: li x1, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0f0f0f0f) & ((1 << (64 - 1) << 1) - 1)); and x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0f000f00) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_13: li gp, 13; li x4, 0; 1: li x1, ((0x0ff00ff0) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xf0f0f0f0) & ((1 << (64 - 1) << 1) - 1)); nop; and x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x00f000f0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_14: li gp, 14; li x4, 0; 1: li x1, ((0x00ff00ff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0f0f0f0f) & ((1 << (64 - 1) << 1) - 1)); nop; nop; and x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x000f000f) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_15: li gp, 15; li x4, 0; 1: li x1, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); nop; li x2, ((0x0f0f0f0f) & ((1 << (64 - 1) << 1) - 1)); and x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0f000f00) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_16: li gp, 16; li x4, 0; 1: li x1, ((0x0ff00ff0) & ((1 << (64 - 1) << 1) - 1)); nop; li x2, ((0xf0f0f0f0) & ((1 << (64 - 1) << 1) - 1)); nop; and x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x00f000f0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_17: li gp, 17; li x4, 0; 1: li x1, ((0x00ff00ff) & ((1 << (64 - 1) << 1) - 1)); nop; nop; li x2, ((0x0f0f0f0f) & ((1 << (64 - 1) << 1) - 1)); and x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x000f000f) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_18: li gp, 18; li x4, 0; 1: li x2, ((0x0f0f0f0f) & ((1 << (64 - 1) << 1) - 1)); li x1, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); and x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0f000f00) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_19: li gp, 19; li x4, 0; 1: li x2, ((0xf0f0f0f0) & ((1 << (64 - 1) << 1) - 1)); li x1, ((0x0ff00ff0) & ((1 << (64 - 1) << 1) - 1)); nop; and x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x00f000f0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_20: li gp, 20; li x4, 0; 1: li x2, ((0x0f0f0f0f) & ((1 << (64 - 1) << 1) - 1)); li x1, ((0x00ff00ff) & ((1 << (64 - 1) << 1) - 1)); nop; nop; and x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x000f000f) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_21: li gp, 21; li x4, 0; 1: li x2, ((0x0f0f0f0f) & ((1 << (64 - 1) << 1) - 1)); nop; li x1, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); and x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0f000f00) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_22: li gp, 22; li x4, 0; 1: li x2, ((0xf0f0f0f0) & ((1 << (64 - 1) << 1) - 1)); nop; li x1, ((0x0ff00ff0) & ((1 << (64 - 1) << 1) - 1)); nop; and x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x00f000f0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_23: li gp, 23; li x4, 0; 1: li x2, ((0x0f0f0f0f) & ((1 << (64 - 1) << 1) - 1)); nop; nop; li x1, ((0x00ff00ff) & ((1 << (64 - 1) << 1) - 1)); and x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x000f000f) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_24: li gp, 24; li x1, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); and x2, x0, x1;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_25: li gp, 25; li x1, ((0x00ff00ff) & ((1 << (64 - 1) << 1) - 1)); and x2, x1, x0;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_26: li gp, 26; and x1, x0, x0;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_27: li gp, 27; li x1, ((0x11111111) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x22222222) & ((1 << (64 - 1) << 1) - 1)); and x0, x1, x2;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x0, x7, fail;;
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+
diff --git a/verilator-tests/testbench/assembly_programs/andi.s b/verilator-tests/testbench/assembly_programs/andi.s
new file mode 100644
index 0000000..d3ac3e0
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/andi.s
@@ -0,0 +1,130 @@
+# 1 "../../riscv-tests/isa/rv64ui/andi.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/andi.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# andi.S
+#-----------------------------------------------------------------------------
+
+# Test andi instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/andi.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/andi.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Logical tests
+  #-------------------------------------------------------------
+
+  test_2: li gp, 2; li x1, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); andi x14, x1, ((0xf0f) | (-(((0xf0f) >> 11) & 1) << 11));; li x7, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_3: li gp, 3; li x1, ((0x0ff00ff0) & ((1 << (64 - 1) << 1) - 1)); andi x14, x1, ((0x0f0) | (-(((0x0f0) >> 11) & 1) << 11));; li x7, ((0x000000f0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_4: li gp, 4; li x1, ((0x00ff00ff) & ((1 << (64 - 1) << 1) - 1)); andi x14, x1, ((0x70f) | (-(((0x70f) >> 11) & 1) << 11));; li x7, ((0x0000000f) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_5: li gp, 5; li x1, ((0xf00ff00f) & ((1 << (64 - 1) << 1) - 1)); andi x14, x1, ((0x0f0) | (-(((0x0f0) >> 11) & 1) << 11));; li x7, ((0x00000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  test_6: li gp, 6; li x1, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); andi x1, x1, ((0x0f0) | (-(((0x0f0) >> 11) & 1) << 11));; li x7, ((0x00000000) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_7: li gp, 7; li x4, 0; 1: li x1, ((0x0ff00ff0) & ((1 << (64 - 1) << 1) - 1)); andi x14, x1, ((0x70f) | (-(((0x70f) >> 11) & 1) << 11)); addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x00000700) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_8: li gp, 8; li x4, 0; 1: li x1, ((0x00ff00ff) & ((1 << (64 - 1) << 1) - 1)); andi x14, x1, ((0x0f0) | (-(((0x0f0) >> 11) & 1) << 11)); nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x000000f0) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_9: li gp, 9; li x4, 0; 1: li x1, ((0xf00ff00f) & ((1 << (64 - 1) << 1) - 1)); andi x14, x1, ((0xf0f) | (-(((0xf0f) >> 11) & 1) << 11)); nop; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xf00ff00f) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+
+  test_10: li gp, 10; li x4, 0; 1: li x1, ((0x0ff00ff0) & ((1 << (64 - 1) << 1) - 1)); andi x14, x1, ((0x70f) | (-(((0x70f) >> 11) & 1) << 11)); addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x00000700) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_11: li gp, 11; li x4, 0; 1: li x1, ((0x00ff00ff) & ((1 << (64 - 1) << 1) - 1)); nop; andi x14, x1, ((0x0f0) | (-(((0x0f0) >> 11) & 1) << 11)); addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x000000f0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_12: li gp, 12; li x4, 0; 1: li x1, ((0xf00ff00f) & ((1 << (64 - 1) << 1) - 1)); nop; nop; andi x14, x1, ((0x70f) | (-(((0x70f) >> 11) & 1) << 11)); addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000f) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_13: li gp, 13; andi x1, x0, ((0x0f0) | (-(((0x0f0) >> 11) & 1) << 11));; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_14: li gp, 14; li x1, ((0x00ff00ff) & ((1 << (64 - 1) << 1) - 1)); andi x0, x1, ((0x70f) | (-(((0x70f) >> 11) & 1) << 11));; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x0, x7, fail;;
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+
diff --git a/verilator-tests/testbench/assembly_programs/auipc.s b/verilator-tests/testbench/assembly_programs/auipc.s
new file mode 100644
index 0000000..8a5ce22
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/auipc.s
@@ -0,0 +1,114 @@
+# 1 "../../riscv-tests/isa/rv64ui/auipc.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/auipc.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# auipc.S
+#-----------------------------------------------------------------------------
+
+# Test auipc instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/auipc.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/auipc.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  test_2: li gp, 2; .align 3; lla a0, 1f + 10000; jal a1, 1f; 1: sub a0, a0, a1;; li x7, ((10000) & ((1 << (64 - 1) << 1) - 1)); bne a0, x7, fail;
+
+
+
+
+
+
+  test_3: li gp, 3; .align 3; lla a0, 1f - 10000; jal a1, 1f; 1: sub a0, a0, a1;; li x7, ((-10000) & ((1 << (64 - 1) << 1) - 1)); bne a0, x7, fail;
+
+
+
+
+
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+
diff --git a/verilator-tests/testbench/assembly_programs/beq.s b/verilator-tests/testbench/assembly_programs/beq.s
new file mode 100644
index 0000000..4f0ee52
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/beq.s
@@ -0,0 +1,139 @@
+# 1 "../../riscv-tests/isa/rv64ui/beq.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/beq.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# beq.S
+#-----------------------------------------------------------------------------
+
+# Test beq instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/beq.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/beq.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Branch tests
+  #-------------------------------------------------------------
+
+  # Each test checks both forward and backward branches
+
+  test_2: li gp, 2; li x1, 0; li x2, 0; beq x1, x2, 2f; bne x0, gp, fail; 1: bne x0, gp, 3f; 2: beq x1, x2, 1b; bne x0, gp, fail; 3:;
+  test_3: li gp, 3; li x1, 1; li x2, 1; beq x1, x2, 2f; bne x0, gp, fail; 1: bne x0, gp, 3f; 2: beq x1, x2, 1b; bne x0, gp, fail; 3:;
+  test_4: li gp, 4; li x1, -1; li x2, -1; beq x1, x2, 2f; bne x0, gp, fail; 1: bne x0, gp, 3f; 2: beq x1, x2, 1b; bne x0, gp, fail; 3:;
+
+  test_5: li gp, 5; li x1, 0; li x2, 1; beq x1, x2, 1f; bne x0, gp, 2f; 1: bne x0, gp, fail; 2: beq x1, x2, 1b; 3:;
+  test_6: li gp, 6; li x1, 1; li x2, 0; beq x1, x2, 1f; bne x0, gp, 2f; 1: bne x0, gp, fail; 2: beq x1, x2, 1b; 3:;
+  test_7: li gp, 7; li x1, -1; li x2, 1; beq x1, x2, 1f; bne x0, gp, 2f; 1: bne x0, gp, fail; 2: beq x1, x2, 1b; 3:;
+  test_8: li gp, 8; li x1, 1; li x2, -1; beq x1, x2, 1f; bne x0, gp, 2f; 1: bne x0, gp, fail; 2: beq x1, x2, 1b; 3:;
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_9: li gp, 9; li x4, 0; 1: li x1, 0; li x2, -1; beq x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_10: li gp, 10; li x4, 0; 1: li x1, 0; li x2, -1; nop; beq x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_11: li gp, 11; li x4, 0; 1: li x1, 0; li x2, -1; nop; nop; beq x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_12: li gp, 12; li x4, 0; 1: li x1, 0; nop; li x2, -1; beq x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_13: li gp, 13; li x4, 0; 1: li x1, 0; nop; li x2, -1; nop; beq x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_14: li gp, 14; li x4, 0; 1: li x1, 0; nop; nop; li x2, -1; beq x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+
+  test_15: li gp, 15; li x4, 0; 1: li x1, 0; li x2, -1; beq x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_16: li gp, 16; li x4, 0; 1: li x1, 0; li x2, -1; nop; beq x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_17: li gp, 17; li x4, 0; 1: li x1, 0; li x2, -1; nop; nop; beq x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_18: li gp, 18; li x4, 0; 1: li x1, 0; nop; li x2, -1; beq x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_19: li gp, 19; li x4, 0; 1: li x1, 0; nop; li x2, -1; nop; beq x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_20: li gp, 20; li x4, 0; 1: li x1, 0; nop; nop; li x2, -1; beq x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+
+  #-------------------------------------------------------------
+  # Test delay slot instructions not executed nor bypassed
+  #-------------------------------------------------------------
+
+  test_21: li gp, 21; li x1, 1; beq x0, x0, 1f; addi x1, x1, 1; addi x1, x1, 1; addi x1, x1, 1; addi x1, x1, 1; 1: addi x1, x1, 1; addi x1, x1, 1;; li x7, ((3) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;
+# 64 "../../riscv-tests/isa/rv64ui/beq.S"
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+
diff --git a/verilator-tests/testbench/assembly_programs/bge.s b/verilator-tests/testbench/assembly_programs/bge.s
new file mode 100644
index 0000000..40cc296
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/bge.s
@@ -0,0 +1,142 @@
+# 1 "../../riscv-tests/isa/rv64ui/bge.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/bge.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# bge.S
+#-----------------------------------------------------------------------------
+
+# Test bge instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/bge.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/bge.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Branch tests
+  #-------------------------------------------------------------
+
+  # Each test checks both forward and backward branches
+
+  test_2: li gp, 2; li x1, 0; li x2, 0; bge x1, x2, 2f; bne x0, gp, fail; 1: bne x0, gp, 3f; 2: bge x1, x2, 1b; bne x0, gp, fail; 3:;
+  test_3: li gp, 3; li x1, 1; li x2, 1; bge x1, x2, 2f; bne x0, gp, fail; 1: bne x0, gp, 3f; 2: bge x1, x2, 1b; bne x0, gp, fail; 3:;
+  test_4: li gp, 4; li x1, -1; li x2, -1; bge x1, x2, 2f; bne x0, gp, fail; 1: bne x0, gp, 3f; 2: bge x1, x2, 1b; bne x0, gp, fail; 3:;
+  test_5: li gp, 5; li x1, 1; li x2, 0; bge x1, x2, 2f; bne x0, gp, fail; 1: bne x0, gp, 3f; 2: bge x1, x2, 1b; bne x0, gp, fail; 3:;
+  test_6: li gp, 6; li x1, 1; li x2, -1; bge x1, x2, 2f; bne x0, gp, fail; 1: bne x0, gp, 3f; 2: bge x1, x2, 1b; bne x0, gp, fail; 3:;
+  test_7: li gp, 7; li x1, -1; li x2, -2; bge x1, x2, 2f; bne x0, gp, fail; 1: bne x0, gp, 3f; 2: bge x1, x2, 1b; bne x0, gp, fail; 3:;
+
+  test_8: li gp, 8; li x1, 0; li x2, 1; bge x1, x2, 1f; bne x0, gp, 2f; 1: bne x0, gp, fail; 2: bge x1, x2, 1b; 3:;
+  test_9: li gp, 9; li x1, -1; li x2, 1; bge x1, x2, 1f; bne x0, gp, 2f; 1: bne x0, gp, fail; 2: bge x1, x2, 1b; 3:;
+  test_10: li gp, 10; li x1, -2; li x2, -1; bge x1, x2, 1f; bne x0, gp, 2f; 1: bne x0, gp, fail; 2: bge x1, x2, 1b; 3:;
+  test_11: li gp, 11; li x1, -2; li x2, 1; bge x1, x2, 1f; bne x0, gp, 2f; 1: bne x0, gp, fail; 2: bge x1, x2, 1b; 3:;
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_12: li gp, 12; li x4, 0; 1: li x1, -1; li x2, 0; bge x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_13: li gp, 13; li x4, 0; 1: li x1, -1; li x2, 0; nop; bge x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_14: li gp, 14; li x4, 0; 1: li x1, -1; li x2, 0; nop; nop; bge x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_15: li gp, 15; li x4, 0; 1: li x1, -1; nop; li x2, 0; bge x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_16: li gp, 16; li x4, 0; 1: li x1, -1; nop; li x2, 0; nop; bge x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_17: li gp, 17; li x4, 0; 1: li x1, -1; nop; nop; li x2, 0; bge x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+
+  test_18: li gp, 18; li x4, 0; 1: li x1, -1; li x2, 0; bge x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_19: li gp, 19; li x4, 0; 1: li x1, -1; li x2, 0; nop; bge x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_20: li gp, 20; li x4, 0; 1: li x1, -1; li x2, 0; nop; nop; bge x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_21: li gp, 21; li x4, 0; 1: li x1, -1; nop; li x2, 0; bge x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_22: li gp, 22; li x4, 0; 1: li x1, -1; nop; li x2, 0; nop; bge x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_23: li gp, 23; li x4, 0; 1: li x1, -1; nop; nop; li x2, 0; bge x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+
+  #-------------------------------------------------------------
+  # Test delay slot instructions not executed nor bypassed
+  #-------------------------------------------------------------
+
+  test_24: li gp, 24; li x1, 1; bge x1, x0, 1f; addi x1, x1, 1; addi x1, x1, 1; addi x1, x1, 1; addi x1, x1, 1; 1: addi x1, x1, 1; addi x1, x1, 1;; li x7, ((3) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;
+# 67 "../../riscv-tests/isa/rv64ui/bge.S"
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+
diff --git a/verilator-tests/testbench/assembly_programs/bgeu.s b/verilator-tests/testbench/assembly_programs/bgeu.s
new file mode 100644
index 0000000..7768a65
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/bgeu.s
@@ -0,0 +1,142 @@
+# 1 "../../riscv-tests/isa/rv64ui/bgeu.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/bgeu.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# bgeu.S
+#-----------------------------------------------------------------------------
+
+# Test bgeu instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/bgeu.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/bgeu.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Branch tests
+  #-------------------------------------------------------------
+
+  # Each test checks both forward and backward branches
+
+  test_2: li gp, 2; li x1, 0x00000000; li x2, 0x00000000; bgeu x1, x2, 2f; bne x0, gp, fail; 1: bne x0, gp, 3f; 2: bgeu x1, x2, 1b; bne x0, gp, fail; 3:;
+  test_3: li gp, 3; li x1, 0x00000001; li x2, 0x00000001; bgeu x1, x2, 2f; bne x0, gp, fail; 1: bne x0, gp, 3f; 2: bgeu x1, x2, 1b; bne x0, gp, fail; 3:;
+  test_4: li gp, 4; li x1, 0xffffffff; li x2, 0xffffffff; bgeu x1, x2, 2f; bne x0, gp, fail; 1: bne x0, gp, 3f; 2: bgeu x1, x2, 1b; bne x0, gp, fail; 3:;
+  test_5: li gp, 5; li x1, 0x00000001; li x2, 0x00000000; bgeu x1, x2, 2f; bne x0, gp, fail; 1: bne x0, gp, 3f; 2: bgeu x1, x2, 1b; bne x0, gp, fail; 3:;
+  test_6: li gp, 6; li x1, 0xffffffff; li x2, 0xfffffffe; bgeu x1, x2, 2f; bne x0, gp, fail; 1: bne x0, gp, 3f; 2: bgeu x1, x2, 1b; bne x0, gp, fail; 3:;
+  test_7: li gp, 7; li x1, 0xffffffff; li x2, 0x00000000; bgeu x1, x2, 2f; bne x0, gp, fail; 1: bne x0, gp, 3f; 2: bgeu x1, x2, 1b; bne x0, gp, fail; 3:;
+
+  test_8: li gp, 8; li x1, 0x00000000; li x2, 0x00000001; bgeu x1, x2, 1f; bne x0, gp, 2f; 1: bne x0, gp, fail; 2: bgeu x1, x2, 1b; 3:;
+  test_9: li gp, 9; li x1, 0xfffffffe; li x2, 0xffffffff; bgeu x1, x2, 1f; bne x0, gp, 2f; 1: bne x0, gp, fail; 2: bgeu x1, x2, 1b; 3:;
+  test_10: li gp, 10; li x1, 0x00000000; li x2, 0xffffffff; bgeu x1, x2, 1f; bne x0, gp, 2f; 1: bne x0, gp, fail; 2: bgeu x1, x2, 1b; 3:;
+  test_11: li gp, 11; li x1, 0x7fffffff; li x2, 0x80000000; bgeu x1, x2, 1f; bne x0, gp, 2f; 1: bne x0, gp, fail; 2: bgeu x1, x2, 1b; 3:;
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_12: li gp, 12; li x4, 0; 1: li x1, 0xefffffff; li x2, 0xf0000000; bgeu x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_13: li gp, 13; li x4, 0; 1: li x1, 0xefffffff; li x2, 0xf0000000; nop; bgeu x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_14: li gp, 14; li x4, 0; 1: li x1, 0xefffffff; li x2, 0xf0000000; nop; nop; bgeu x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_15: li gp, 15; li x4, 0; 1: li x1, 0xefffffff; nop; li x2, 0xf0000000; bgeu x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_16: li gp, 16; li x4, 0; 1: li x1, 0xefffffff; nop; li x2, 0xf0000000; nop; bgeu x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_17: li gp, 17; li x4, 0; 1: li x1, 0xefffffff; nop; nop; li x2, 0xf0000000; bgeu x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+
+  test_18: li gp, 18; li x4, 0; 1: li x1, 0xefffffff; li x2, 0xf0000000; bgeu x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_19: li gp, 19; li x4, 0; 1: li x1, 0xefffffff; li x2, 0xf0000000; nop; bgeu x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_20: li gp, 20; li x4, 0; 1: li x1, 0xefffffff; li x2, 0xf0000000; nop; nop; bgeu x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_21: li gp, 21; li x4, 0; 1: li x1, 0xefffffff; nop; li x2, 0xf0000000; bgeu x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_22: li gp, 22; li x4, 0; 1: li x1, 0xefffffff; nop; li x2, 0xf0000000; nop; bgeu x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_23: li gp, 23; li x4, 0; 1: li x1, 0xefffffff; nop; nop; li x2, 0xf0000000; bgeu x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+
+  #-------------------------------------------------------------
+  # Test delay slot instructions not executed nor bypassed
+  #-------------------------------------------------------------
+
+  test_24: li gp, 24; li x1, 1; bgeu x1, x0, 1f; addi x1, x1, 1; addi x1, x1, 1; addi x1, x1, 1; addi x1, x1, 1; 1: addi x1, x1, 1; addi x1, x1, 1;; li x7, ((3) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;
+# 67 "../../riscv-tests/isa/rv64ui/bgeu.S"
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+
diff --git a/verilator-tests/testbench/assembly_programs/blt.s b/verilator-tests/testbench/assembly_programs/blt.s
new file mode 100644
index 0000000..96e50a1
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/blt.s
@@ -0,0 +1,139 @@
+# 1 "../../riscv-tests/isa/rv64ui/blt.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/blt.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# blt.S
+#-----------------------------------------------------------------------------
+
+# Test blt instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/blt.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/blt.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Branch tests
+  #-------------------------------------------------------------
+
+  # Each test checks both forward and backward branches
+
+  test_2: li gp, 2; li x1, 0; li x2, 1; blt x1, x2, 2f; bne x0, gp, fail; 1: bne x0, gp, 3f; 2: blt x1, x2, 1b; bne x0, gp, fail; 3:;
+  test_3: li gp, 3; li x1, -1; li x2, 1; blt x1, x2, 2f; bne x0, gp, fail; 1: bne x0, gp, 3f; 2: blt x1, x2, 1b; bne x0, gp, fail; 3:;
+  test_4: li gp, 4; li x1, -2; li x2, -1; blt x1, x2, 2f; bne x0, gp, fail; 1: bne x0, gp, 3f; 2: blt x1, x2, 1b; bne x0, gp, fail; 3:;
+
+  test_5: li gp, 5; li x1, 1; li x2, 0; blt x1, x2, 1f; bne x0, gp, 2f; 1: bne x0, gp, fail; 2: blt x1, x2, 1b; 3:;
+  test_6: li gp, 6; li x1, 1; li x2, -1; blt x1, x2, 1f; bne x0, gp, 2f; 1: bne x0, gp, fail; 2: blt x1, x2, 1b; 3:;
+  test_7: li gp, 7; li x1, -1; li x2, -2; blt x1, x2, 1f; bne x0, gp, 2f; 1: bne x0, gp, fail; 2: blt x1, x2, 1b; 3:;
+  test_8: li gp, 8; li x1, 1; li x2, -2; blt x1, x2, 1f; bne x0, gp, 2f; 1: bne x0, gp, fail; 2: blt x1, x2, 1b; 3:;
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_9: li gp, 9; li x4, 0; 1: li x1, 0; li x2, -1; blt x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_10: li gp, 10; li x4, 0; 1: li x1, 0; li x2, -1; nop; blt x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_11: li gp, 11; li x4, 0; 1: li x1, 0; li x2, -1; nop; nop; blt x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_12: li gp, 12; li x4, 0; 1: li x1, 0; nop; li x2, -1; blt x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_13: li gp, 13; li x4, 0; 1: li x1, 0; nop; li x2, -1; nop; blt x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_14: li gp, 14; li x4, 0; 1: li x1, 0; nop; nop; li x2, -1; blt x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+
+  test_15: li gp, 15; li x4, 0; 1: li x1, 0; li x2, -1; blt x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_16: li gp, 16; li x4, 0; 1: li x1, 0; li x2, -1; nop; blt x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_17: li gp, 17; li x4, 0; 1: li x1, 0; li x2, -1; nop; nop; blt x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_18: li gp, 18; li x4, 0; 1: li x1, 0; nop; li x2, -1; blt x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_19: li gp, 19; li x4, 0; 1: li x1, 0; nop; li x2, -1; nop; blt x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_20: li gp, 20; li x4, 0; 1: li x1, 0; nop; nop; li x2, -1; blt x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+
+  #-------------------------------------------------------------
+  # Test delay slot instructions not executed nor bypassed
+  #-------------------------------------------------------------
+
+  test_21: li gp, 21; li x1, 1; blt x0, x1, 1f; addi x1, x1, 1; addi x1, x1, 1; addi x1, x1, 1; addi x1, x1, 1; 1: addi x1, x1, 1; addi x1, x1, 1;; li x7, ((3) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;
+# 64 "../../riscv-tests/isa/rv64ui/blt.S"
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+
diff --git a/verilator-tests/testbench/assembly_programs/bltu.s b/verilator-tests/testbench/assembly_programs/bltu.s
new file mode 100644
index 0000000..5a98bf8
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/bltu.s
@@ -0,0 +1,139 @@
+# 1 "../../riscv-tests/isa/rv64ui/bltu.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/bltu.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# bltu.S
+#-----------------------------------------------------------------------------
+
+# Test bltu instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/bltu.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/bltu.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Branch tests
+  #-------------------------------------------------------------
+
+  # Each test checks both forward and backward branches
+
+  test_2: li gp, 2; li x1, 0x00000000; li x2, 0x00000001; bltu x1, x2, 2f; bne x0, gp, fail; 1: bne x0, gp, 3f; 2: bltu x1, x2, 1b; bne x0, gp, fail; 3:;
+  test_3: li gp, 3; li x1, 0xfffffffe; li x2, 0xffffffff; bltu x1, x2, 2f; bne x0, gp, fail; 1: bne x0, gp, 3f; 2: bltu x1, x2, 1b; bne x0, gp, fail; 3:;
+  test_4: li gp, 4; li x1, 0x00000000; li x2, 0xffffffff; bltu x1, x2, 2f; bne x0, gp, fail; 1: bne x0, gp, 3f; 2: bltu x1, x2, 1b; bne x0, gp, fail; 3:;
+
+  test_5: li gp, 5; li x1, 0x00000001; li x2, 0x00000000; bltu x1, x2, 1f; bne x0, gp, 2f; 1: bne x0, gp, fail; 2: bltu x1, x2, 1b; 3:;
+  test_6: li gp, 6; li x1, 0xffffffff; li x2, 0xfffffffe; bltu x1, x2, 1f; bne x0, gp, 2f; 1: bne x0, gp, fail; 2: bltu x1, x2, 1b; 3:;
+  test_7: li gp, 7; li x1, 0xffffffff; li x2, 0x00000000; bltu x1, x2, 1f; bne x0, gp, 2f; 1: bne x0, gp, fail; 2: bltu x1, x2, 1b; 3:;
+  test_8: li gp, 8; li x1, 0x80000000; li x2, 0x7fffffff; bltu x1, x2, 1f; bne x0, gp, 2f; 1: bne x0, gp, fail; 2: bltu x1, x2, 1b; 3:;
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_9: li gp, 9; li x4, 0; 1: li x1, 0xf0000000; li x2, 0xefffffff; bltu x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_10: li gp, 10; li x4, 0; 1: li x1, 0xf0000000; li x2, 0xefffffff; nop; bltu x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_11: li gp, 11; li x4, 0; 1: li x1, 0xf0000000; li x2, 0xefffffff; nop; nop; bltu x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_12: li gp, 12; li x4, 0; 1: li x1, 0xf0000000; nop; li x2, 0xefffffff; bltu x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_13: li gp, 13; li x4, 0; 1: li x1, 0xf0000000; nop; li x2, 0xefffffff; nop; bltu x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_14: li gp, 14; li x4, 0; 1: li x1, 0xf0000000; nop; nop; li x2, 0xefffffff; bltu x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+
+  test_15: li gp, 15; li x4, 0; 1: li x1, 0xf0000000; li x2, 0xefffffff; bltu x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_16: li gp, 16; li x4, 0; 1: li x1, 0xf0000000; li x2, 0xefffffff; nop; bltu x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_17: li gp, 17; li x4, 0; 1: li x1, 0xf0000000; li x2, 0xefffffff; nop; nop; bltu x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_18: li gp, 18; li x4, 0; 1: li x1, 0xf0000000; nop; li x2, 0xefffffff; bltu x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_19: li gp, 19; li x4, 0; 1: li x1, 0xf0000000; nop; li x2, 0xefffffff; nop; bltu x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_20: li gp, 20; li x4, 0; 1: li x1, 0xf0000000; nop; nop; li x2, 0xefffffff; bltu x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+
+  #-------------------------------------------------------------
+  # Test delay slot instructions not executed nor bypassed
+  #-------------------------------------------------------------
+
+  test_21: li gp, 21; li x1, 1; bltu x0, x1, 1f; addi x1, x1, 1; addi x1, x1, 1; addi x1, x1, 1; addi x1, x1, 1; 1: addi x1, x1, 1; addi x1, x1, 1;; li x7, ((3) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;
+# 64 "../../riscv-tests/isa/rv64ui/bltu.S"
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+
diff --git a/verilator-tests/testbench/assembly_programs/bne.s b/verilator-tests/testbench/assembly_programs/bne.s
new file mode 100644
index 0000000..c8a29cf
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/bne.s
@@ -0,0 +1,139 @@
+# 1 "../../riscv-tests/isa/rv64ui/bne.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/bne.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# bne.S
+#-----------------------------------------------------------------------------
+
+# Test bne instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/bne.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/bne.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Branch tests
+  #-------------------------------------------------------------
+
+  # Each test checks both forward and backward branches
+
+  test_2: li gp, 2; li x1, 0; li x2, 1; bne x1, x2, 2f; bne x0, gp, fail; 1: bne x0, gp, 3f; 2: bne x1, x2, 1b; bne x0, gp, fail; 3:;
+  test_3: li gp, 3; li x1, 1; li x2, 0; bne x1, x2, 2f; bne x0, gp, fail; 1: bne x0, gp, 3f; 2: bne x1, x2, 1b; bne x0, gp, fail; 3:;
+  test_4: li gp, 4; li x1, -1; li x2, 1; bne x1, x2, 2f; bne x0, gp, fail; 1: bne x0, gp, 3f; 2: bne x1, x2, 1b; bne x0, gp, fail; 3:;
+  test_5: li gp, 5; li x1, 1; li x2, -1; bne x1, x2, 2f; bne x0, gp, fail; 1: bne x0, gp, 3f; 2: bne x1, x2, 1b; bne x0, gp, fail; 3:;
+
+  test_6: li gp, 6; li x1, 0; li x2, 0; bne x1, x2, 1f; bne x0, gp, 2f; 1: bne x0, gp, fail; 2: bne x1, x2, 1b; 3:;
+  test_7: li gp, 7; li x1, 1; li x2, 1; bne x1, x2, 1f; bne x0, gp, 2f; 1: bne x0, gp, fail; 2: bne x1, x2, 1b; 3:;
+  test_8: li gp, 8; li x1, -1; li x2, -1; bne x1, x2, 1f; bne x0, gp, 2f; 1: bne x0, gp, fail; 2: bne x1, x2, 1b; 3:;
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_9: li gp, 9; li x4, 0; 1: li x1, 0; li x2, 0; bne x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_10: li gp, 10; li x4, 0; 1: li x1, 0; li x2, 0; nop; bne x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_11: li gp, 11; li x4, 0; 1: li x1, 0; li x2, 0; nop; nop; bne x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_12: li gp, 12; li x4, 0; 1: li x1, 0; nop; li x2, 0; bne x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_13: li gp, 13; li x4, 0; 1: li x1, 0; nop; li x2, 0; nop; bne x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_14: li gp, 14; li x4, 0; 1: li x1, 0; nop; nop; li x2, 0; bne x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+
+  test_15: li gp, 15; li x4, 0; 1: li x1, 0; li x2, 0; bne x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_16: li gp, 16; li x4, 0; 1: li x1, 0; li x2, 0; nop; bne x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_17: li gp, 17; li x4, 0; 1: li x1, 0; li x2, 0; nop; nop; bne x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_18: li gp, 18; li x4, 0; 1: li x1, 0; nop; li x2, 0; bne x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_19: li gp, 19; li x4, 0; 1: li x1, 0; nop; li x2, 0; nop; bne x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_20: li gp, 20; li x4, 0; 1: li x1, 0; nop; nop; li x2, 0; bne x1, x2, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+
+  #-------------------------------------------------------------
+  # Test delay slot instructions not executed nor bypassed
+  #-------------------------------------------------------------
+
+  test_21: li gp, 21; li x1, 1; bne x1, x0, 1f; addi x1, x1, 1; addi x1, x1, 1; addi x1, x1, 1; addi x1, x1, 1; 1: addi x1, x1, 1; addi x1, x1, 1;; li x7, ((3) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;
+# 64 "../../riscv-tests/isa/rv64ui/bne.S"
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+
diff --git a/verilator-tests/testbench/assembly_programs/jal.s b/verilator-tests/testbench/assembly_programs/jal.s
new file mode 100644
index 0000000..390b358
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/jal.s
@@ -0,0 +1,125 @@
+# 1 "../../riscv-tests/isa/rv64ui/jal.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/jal.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# jal.S
+#-----------------------------------------------------------------------------
+
+# Test jal instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/jal.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/jal.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Test 2: Basic test
+  #-------------------------------------------------------------
+
+test_2:
+  li gp, 2
+  li ra, 0
+
+  jal x4, target_2
+linkaddr_2:
+  nop
+  nop
+
+  j fail
+
+target_2:
+  la x2, linkaddr_2
+  bne x2, x4, fail
+
+  #-------------------------------------------------------------
+  # Test delay slot instructions not executed nor bypassed
+  #-------------------------------------------------------------
+
+  test_3: li gp, 3; li ra, 1; jal x0, 1f; addi ra, ra, 1; addi ra, ra, 1; addi ra, ra, 1; addi ra, ra, 1; 1: addi ra, ra, 1; addi ra, ra, 1;; li x7, ((3) & ((1 << (64 - 1) << 1) - 1)); bne ra, x7, fail;
+# 50 "../../riscv-tests/isa/rv64ui/jal.S"
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+
diff --git a/verilator-tests/testbench/assembly_programs/jalr.s b/verilator-tests/testbench/assembly_programs/jalr.s
new file mode 100644
index 0000000..924e56d
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/jalr.s
@@ -0,0 +1,152 @@
+# 1 "../../riscv-tests/isa/rv64ui/jalr.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/jalr.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# jalr.S
+#-----------------------------------------------------------------------------
+
+# Test jalr instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/jalr.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/jalr.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Test 2: Basic test
+  #-------------------------------------------------------------
+
+test_2:
+  li gp, 2
+  li t0, 0
+  la t1, target_2
+
+  jalr t0, t1, 0
+linkaddr_2:
+  j fail
+
+target_2:
+  la t1, linkaddr_2
+  bne t0, t1, fail
+
+  #-------------------------------------------------------------
+  # Test 3: Basic test2, rs = rd
+  #-------------------------------------------------------------
+
+test_3:
+  li gp, 3
+  la t0, target_3
+
+  jalr t0, t0, 0
+linkaddr_3:
+  j fail
+
+target_3:
+  la t1, linkaddr_3
+  bne t0, t1, fail
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_4: li gp, 4; li x4, 0; 1: la x6, 2f; jalr x13, x6, 0; bne x0, gp, fail; 2: addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_5: li gp, 5; li x4, 0; 1: la x6, 2f; nop; jalr x13, x6, 0; bne x0, gp, fail; 2: addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_6: li gp, 6; li x4, 0; 1: la x6, 2f; nop; nop; jalr x13, x6, 0; bne x0, gp, fail; 2: addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+
+  #-------------------------------------------------------------
+  # Test delay slot instructions not executed nor bypassed
+  #-------------------------------------------------------------
+
+  .option push
+  .align 2
+  .option norvc
+  test_7: li gp, 7; li t0, 1; la t1, 1f; jr t1, -4; addi t0, t0, 1; addi t0, t0, 1; addi t0, t0, 1; addi t0, t0, 1; 1: addi t0, t0, 1; addi t0, t0, 1;; li x7, ((4) & ((1 << (64 - 1) << 1) - 1)); bne t0, x7, fail;
+# 75 "../../riscv-tests/isa/rv64ui/jalr.S"
+  .option pop
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+
diff --git a/verilator-tests/testbench/assembly_programs/lb.s b/verilator-tests/testbench/assembly_programs/lb.s
new file mode 100644
index 0000000..bce1181
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/lb.s
@@ -0,0 +1,167 @@
+# 1 "../../riscv-tests/isa/rv64ui/lb.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/lb.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# lb.S
+#-----------------------------------------------------------------------------
+
+# Test lb instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/lb.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/lb.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  test_2: li gp, 2; li x15, 0xffffffffffffffff; la x1, tdat; lb x14, 0(x1);; li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_3: li gp, 3; li x15, 0x0000000000000000; la x1, tdat; lb x14, 1(x1);; li x7, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_4: li gp, 4; li x15, 0xfffffffffffffff0; la x1, tdat; lb x14, 2(x1);; li x7, ((0xfffffffffffffff0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_5: li gp, 5; li x15, 0x000000000000000f; la x1, tdat; lb x14, 3(x1);; li x7, ((0x000000000000000f) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  # Test with negative offset
+
+  test_6: li gp, 6; li x15, 0xffffffffffffffff; la x1, tdat4; lb x14, -3(x1);; li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_7: li gp, 7; li x15, 0x0000000000000000; la x1, tdat4; lb x14, -2(x1);; li x7, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_8: li gp, 8; li x15, 0xfffffffffffffff0; la x1, tdat4; lb x14, -1(x1);; li x7, ((0xfffffffffffffff0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_9: li gp, 9; li x15, 0x000000000000000f; la x1, tdat4; lb x14, 0(x1);; li x7, ((0x000000000000000f) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  # Test with a negative base
+
+  test_10: li gp, 10; la x1, tdat; addi x1, x1, -32; lb x5, 32(x1);; li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne x5, x7, fail;
+
+
+
+
+
+  # Test with unaligned base
+
+  test_11: li gp, 11; la x1, tdat; addi x1, x1, -6; lb x5, 7(x1);; li x7, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); bne x5, x7, fail;
+
+
+
+
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_12: li gp, 12; li x4, 0; 1: la x1, tdat2; lb x14, 1(x1); addi x6, x14, 0; li x7, 0xfffffffffffffff0; bne x6, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;;
+  test_13: li gp, 13; li x4, 0; 1: la x1, tdat3; lb x14, 1(x1); nop; addi x6, x14, 0; li x7, 0x000000000000000f; bne x6, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;;
+  test_14: li gp, 14; li x4, 0; 1: la x1, tdat1; lb x14, 1(x1); nop; nop; addi x6, x14, 0; li x7, 0x0000000000000000; bne x6, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;;
+
+  test_15: li gp, 15; li x4, 0; 1: la x1, tdat2; lb x14, 1(x1); li x7, 0xfffffffffffffff0; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_16: li gp, 16; li x4, 0; 1: la x1, tdat3; nop; lb x14, 1(x1); li x7, 0x000000000000000f; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_17: li gp, 17; li x4, 0; 1: la x1, tdat1; nop; nop; lb x14, 1(x1); li x7, 0x0000000000000000; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+
+  #-------------------------------------------------------------
+  # Test write-after-write hazard
+  #-------------------------------------------------------------
+
+  test_18: li gp, 18; la x5, tdat; lb x2, 0(x5); li x2, 2;; li x7, ((2) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;
+
+
+
+
+
+  test_19: li gp, 19; la x5, tdat; lb x2, 0(x5); nop; li x2, 2;; li x7, ((2) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;
+
+
+
+
+
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+tdat:
+tdat1: .byte 0xff
+tdat2: .byte 0x00
+tdat3: .byte 0xf0
+tdat4: .byte 0x0f
+
+
diff --git a/verilator-tests/testbench/assembly_programs/lbu.s b/verilator-tests/testbench/assembly_programs/lbu.s
new file mode 100644
index 0000000..38cac0a
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/lbu.s
@@ -0,0 +1,167 @@
+# 1 "../../riscv-tests/isa/rv64ui/lbu.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/lbu.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# lbu.S
+#-----------------------------------------------------------------------------
+
+# Test lbu instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/lbu.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/lbu.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  test_2: li gp, 2; li x15, 0x00000000000000ff; la x1, tdat; lbu x14, 0(x1);; li x7, ((0x00000000000000ff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_3: li gp, 3; li x15, 0x0000000000000000; la x1, tdat; lbu x14, 1(x1);; li x7, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_4: li gp, 4; li x15, 0x00000000000000f0; la x1, tdat; lbu x14, 2(x1);; li x7, ((0x00000000000000f0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_5: li gp, 5; li x15, 0x000000000000000f; la x1, tdat; lbu x14, 3(x1);; li x7, ((0x000000000000000f) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  # Test with negative offset
+
+  test_6: li gp, 6; li x15, 0x00000000000000ff; la x1, tdat4; lbu x14, -3(x1);; li x7, ((0x00000000000000ff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_7: li gp, 7; li x15, 0x0000000000000000; la x1, tdat4; lbu x14, -2(x1);; li x7, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_8: li gp, 8; li x15, 0x00000000000000f0; la x1, tdat4; lbu x14, -1(x1);; li x7, ((0x00000000000000f0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_9: li gp, 9; li x15, 0x000000000000000f; la x1, tdat4; lbu x14, 0(x1);; li x7, ((0x000000000000000f) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  # Test with a negative base
+
+  test_10: li gp, 10; la x1, tdat; addi x1, x1, -32; lbu x5, 32(x1);; li x7, ((0x00000000000000ff) & ((1 << (64 - 1) << 1) - 1)); bne x5, x7, fail;
+
+
+
+
+
+  # Test with unaligned base
+
+  test_11: li gp, 11; la x1, tdat; addi x1, x1, -6; lbu x5, 7(x1);; li x7, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); bne x5, x7, fail;
+
+
+
+
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_12: li gp, 12; li x4, 0; 1: la x1, tdat2; lbu x14, 1(x1); addi x6, x14, 0; li x7, 0x00000000000000f0; bne x6, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;;
+  test_13: li gp, 13; li x4, 0; 1: la x1, tdat3; lbu x14, 1(x1); nop; addi x6, x14, 0; li x7, 0x000000000000000f; bne x6, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;;
+  test_14: li gp, 14; li x4, 0; 1: la x1, tdat1; lbu x14, 1(x1); nop; nop; addi x6, x14, 0; li x7, 0x0000000000000000; bne x6, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;;
+
+  test_15: li gp, 15; li x4, 0; 1: la x1, tdat2; lbu x14, 1(x1); li x7, 0x00000000000000f0; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_16: li gp, 16; li x4, 0; 1: la x1, tdat3; nop; lbu x14, 1(x1); li x7, 0x000000000000000f; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_17: li gp, 17; li x4, 0; 1: la x1, tdat1; nop; nop; lbu x14, 1(x1); li x7, 0x0000000000000000; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+
+  #-------------------------------------------------------------
+  # Test write-after-write hazard
+  #-------------------------------------------------------------
+
+  test_18: li gp, 18; la x5, tdat; lbu x2, 0(x5); li x2, 2;; li x7, ((2) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;
+
+
+
+
+
+  test_19: li gp, 19; la x5, tdat; lbu x2, 0(x5); nop; li x2, 2;; li x7, ((2) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;
+
+
+
+
+
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+tdat:
+tdat1: .byte 0xff
+tdat2: .byte 0x00
+tdat3: .byte 0xf0
+tdat4: .byte 0x0f
+
+
diff --git a/verilator-tests/testbench/assembly_programs/ld.s b/verilator-tests/testbench/assembly_programs/ld.s
new file mode 100644
index 0000000..9780bfd
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/ld.s
@@ -0,0 +1,167 @@
+# 1 "../../riscv-tests/isa/rv64ui/ld.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/ld.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# ld.S
+#-----------------------------------------------------------------------------
+
+# Test ld instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/ld.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/ld.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  test_2: li gp, 2; li x15, 0x00ff00ff00ff00ff; la x1, tdat; ld x14, 0(x1);; li x7, ((0x00ff00ff00ff00ff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_3: li gp, 3; li x15, 0xff00ff00ff00ff00; la x1, tdat; ld x14, 8(x1);; li x7, ((0xff00ff00ff00ff00) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_4: li gp, 4; li x15, 0x0ff00ff00ff00ff0; la x1, tdat; ld x14, 16(x1);; li x7, ((0x0ff00ff00ff00ff0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_5: li gp, 5; li x15, 0xf00ff00ff00ff00f; la x1, tdat; ld x14, 24(x1);; li x7, ((0xf00ff00ff00ff00f) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  # Test with negative offset
+
+  test_6: li gp, 6; li x15, 0x00ff00ff00ff00ff; la x1, tdat4; ld x14, -24(x1);; li x7, ((0x00ff00ff00ff00ff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_7: li gp, 7; li x15, 0xff00ff00ff00ff00; la x1, tdat4; ld x14, -16(x1);; li x7, ((0xff00ff00ff00ff00) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_8: li gp, 8; li x15, 0x0ff00ff00ff00ff0; la x1, tdat4; ld x14, -8(x1);; li x7, ((0x0ff00ff00ff00ff0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_9: li gp, 9; li x15, 0xf00ff00ff00ff00f; la x1, tdat4; ld x14, 0(x1);; li x7, ((0xf00ff00ff00ff00f) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  # Test with a negative base
+
+  test_10: li gp, 10; la x1, tdat; addi x1, x1, -32; ld x5, 32(x1);; li x7, ((0x00ff00ff00ff00ff) & ((1 << (64 - 1) << 1) - 1)); bne x5, x7, fail;
+
+
+
+
+
+  # Test with unaligned base
+
+  test_11: li gp, 11; la x1, tdat; addi x1, x1, -3; ld x5, 11(x1);; li x7, ((0xff00ff00ff00ff00) & ((1 << (64 - 1) << 1) - 1)); bne x5, x7, fail;
+
+
+
+
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_12: li gp, 12; li x4, 0; 1: la x1, tdat2; ld x14, 8(x1); addi x6, x14, 0; li x7, 0x0ff00ff00ff00ff0; bne x6, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;;
+  test_13: li gp, 13; li x4, 0; 1: la x1, tdat3; ld x14, 8(x1); nop; addi x6, x14, 0; li x7, 0xf00ff00ff00ff00f; bne x6, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;;
+  test_14: li gp, 14; li x4, 0; 1: la x1, tdat1; ld x14, 8(x1); nop; nop; addi x6, x14, 0; li x7, 0xff00ff00ff00ff00; bne x6, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;;
+
+  test_15: li gp, 15; li x4, 0; 1: la x1, tdat2; ld x14, 8(x1); li x7, 0x0ff00ff00ff00ff0; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_16: li gp, 16; li x4, 0; 1: la x1, tdat3; nop; ld x14, 8(x1); li x7, 0xf00ff00ff00ff00f; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_17: li gp, 17; li x4, 0; 1: la x1, tdat1; nop; nop; ld x14, 8(x1); li x7, 0xff00ff00ff00ff00; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+
+  #-------------------------------------------------------------
+  # Test write-after-write hazard
+  #-------------------------------------------------------------
+
+  test_18: li gp, 18; la x5, tdat; ld x2, 0(x5); li x2, 2;; li x7, ((2) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;
+
+
+
+
+
+  test_19: li gp, 19; la x5, tdat; ld x2, 0(x5); nop; li x2, 2;; li x7, ((2) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;
+
+
+
+
+
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+tdat:
+tdat1: .dword 0x00ff00ff00ff00ff
+tdat2: .dword 0xff00ff00ff00ff00
+tdat3: .dword 0x0ff00ff00ff00ff0
+tdat4: .dword 0xf00ff00ff00ff00f
+
+
diff --git a/verilator-tests/testbench/assembly_programs/lh.s b/verilator-tests/testbench/assembly_programs/lh.s
new file mode 100644
index 0000000..3f4d315
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/lh.s
@@ -0,0 +1,167 @@
+# 1 "../../riscv-tests/isa/rv64ui/lh.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/lh.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# lh.S
+#-----------------------------------------------------------------------------
+
+# Test lh instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/lh.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/lh.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  test_2: li gp, 2; li x15, 0x00000000000000ff; la x1, tdat; lh x14, 0(x1);; li x7, ((0x00000000000000ff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_3: li gp, 3; li x15, 0xffffffffffffff00; la x1, tdat; lh x14, 2(x1);; li x7, ((0xffffffffffffff00) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_4: li gp, 4; li x15, 0x0000000000000ff0; la x1, tdat; lh x14, 4(x1);; li x7, ((0x0000000000000ff0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_5: li gp, 5; li x15, 0xfffffffffffff00f; la x1, tdat; lh x14, 6(x1);; li x7, ((0xfffffffffffff00f) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  # Test with negative offset
+
+  test_6: li gp, 6; li x15, 0x00000000000000ff; la x1, tdat4; lh x14, -6(x1);; li x7, ((0x00000000000000ff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_7: li gp, 7; li x15, 0xffffffffffffff00; la x1, tdat4; lh x14, -4(x1);; li x7, ((0xffffffffffffff00) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_8: li gp, 8; li x15, 0x0000000000000ff0; la x1, tdat4; lh x14, -2(x1);; li x7, ((0x0000000000000ff0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_9: li gp, 9; li x15, 0xfffffffffffff00f; la x1, tdat4; lh x14, 0(x1);; li x7, ((0xfffffffffffff00f) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  # Test with a negative base
+
+  test_10: li gp, 10; la x1, tdat; addi x1, x1, -32; lh x5, 32(x1);; li x7, ((0x00000000000000ff) & ((1 << (64 - 1) << 1) - 1)); bne x5, x7, fail;
+
+
+
+
+
+  # Test with unaligned base
+
+  test_11: li gp, 11; la x1, tdat; addi x1, x1, -5; lh x5, 7(x1);; li x7, ((0xffffffffffffff00) & ((1 << (64 - 1) << 1) - 1)); bne x5, x7, fail;
+
+
+
+
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_12: li gp, 12; li x4, 0; 1: la x1, tdat2; lh x14, 2(x1); addi x6, x14, 0; li x7, 0x0000000000000ff0; bne x6, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;;
+  test_13: li gp, 13; li x4, 0; 1: la x1, tdat3; lh x14, 2(x1); nop; addi x6, x14, 0; li x7, 0xfffffffffffff00f; bne x6, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;;
+  test_14: li gp, 14; li x4, 0; 1: la x1, tdat1; lh x14, 2(x1); nop; nop; addi x6, x14, 0; li x7, 0xffffffffffffff00; bne x6, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;;
+
+  test_15: li gp, 15; li x4, 0; 1: la x1, tdat2; lh x14, 2(x1); li x7, 0x0000000000000ff0; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_16: li gp, 16; li x4, 0; 1: la x1, tdat3; nop; lh x14, 2(x1); li x7, 0xfffffffffffff00f; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_17: li gp, 17; li x4, 0; 1: la x1, tdat1; nop; nop; lh x14, 2(x1); li x7, 0xffffffffffffff00; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+
+  #-------------------------------------------------------------
+  # Test write-after-write hazard
+  #-------------------------------------------------------------
+
+  test_18: li gp, 18; la x5, tdat; lh x2, 0(x5); li x2, 2;; li x7, ((2) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;
+
+
+
+
+
+  test_19: li gp, 19; la x5, tdat; lh x2, 0(x5); nop; li x2, 2;; li x7, ((2) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;
+
+
+
+
+
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+tdat:
+tdat1: .half 0x00ff
+tdat2: .half 0xff00
+tdat3: .half 0x0ff0
+tdat4: .half 0xf00f
+
+
diff --git a/verilator-tests/testbench/assembly_programs/lhu.s b/verilator-tests/testbench/assembly_programs/lhu.s
new file mode 100644
index 0000000..2c20d17
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/lhu.s
@@ -0,0 +1,167 @@
+# 1 "../../riscv-tests/isa/rv64ui/lhu.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/lhu.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# lhu.S
+#-----------------------------------------------------------------------------
+
+# Test lhu instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/lhu.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/lhu.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  test_2: li gp, 2; li x15, 0x00000000000000ff; la x1, tdat; lhu x14, 0(x1);; li x7, ((0x00000000000000ff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_3: li gp, 3; li x15, 0x000000000000ff00; la x1, tdat; lhu x14, 2(x1);; li x7, ((0x000000000000ff00) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_4: li gp, 4; li x15, 0x0000000000000ff0; la x1, tdat; lhu x14, 4(x1);; li x7, ((0x0000000000000ff0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_5: li gp, 5; li x15, 0x000000000000f00f; la x1, tdat; lhu x14, 6(x1);; li x7, ((0x000000000000f00f) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  # Test with negative offset
+
+  test_6: li gp, 6; li x15, 0x00000000000000ff; la x1, tdat4; lhu x14, -6(x1);; li x7, ((0x00000000000000ff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_7: li gp, 7; li x15, 0x000000000000ff00; la x1, tdat4; lhu x14, -4(x1);; li x7, ((0x000000000000ff00) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_8: li gp, 8; li x15, 0x0000000000000ff0; la x1, tdat4; lhu x14, -2(x1);; li x7, ((0x0000000000000ff0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_9: li gp, 9; li x15, 0x000000000000f00f; la x1, tdat4; lhu x14, 0(x1);; li x7, ((0x000000000000f00f) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  # Test with a negative base
+
+  test_10: li gp, 10; la x1, tdat; addi x1, x1, -32; lhu x5, 32(x1);; li x7, ((0x00000000000000ff) & ((1 << (64 - 1) << 1) - 1)); bne x5, x7, fail;
+
+
+
+
+
+  # Test with unaligned base
+
+  test_11: li gp, 11; la x1, tdat; addi x1, x1, -5; lhu x5, 7(x1);; li x7, ((0x000000000000ff00) & ((1 << (64 - 1) << 1) - 1)); bne x5, x7, fail;
+
+
+
+
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_12: li gp, 12; li x4, 0; 1: la x1, tdat2; lhu x14, 2(x1); addi x6, x14, 0; li x7, 0x0000000000000ff0; bne x6, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;;
+  test_13: li gp, 13; li x4, 0; 1: la x1, tdat3; lhu x14, 2(x1); nop; addi x6, x14, 0; li x7, 0x000000000000f00f; bne x6, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;;
+  test_14: li gp, 14; li x4, 0; 1: la x1, tdat1; lhu x14, 2(x1); nop; nop; addi x6, x14, 0; li x7, 0x000000000000ff00; bne x6, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;;
+
+  test_15: li gp, 15; li x4, 0; 1: la x1, tdat2; lhu x14, 2(x1); li x7, 0x0000000000000ff0; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_16: li gp, 16; li x4, 0; 1: la x1, tdat3; nop; lhu x14, 2(x1); li x7, 0x000000000000f00f; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_17: li gp, 17; li x4, 0; 1: la x1, tdat1; nop; nop; lhu x14, 2(x1); li x7, 0x000000000000ff00; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+
+  #-------------------------------------------------------------
+  # Test write-after-write hazard
+  #-------------------------------------------------------------
+
+  test_18: li gp, 18; la x5, tdat; lhu x2, 0(x5); li x2, 2;; li x7, ((2) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;
+
+
+
+
+
+  test_19: li gp, 19; la x5, tdat; lhu x2, 0(x5); nop; li x2, 2;; li x7, ((2) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;
+
+
+
+
+
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+tdat:
+tdat1: .half 0x00ff
+tdat2: .half 0xff00
+tdat3: .half 0x0ff0
+tdat4: .half 0xf00f
+
+
diff --git a/verilator-tests/testbench/assembly_programs/lui.s b/verilator-tests/testbench/assembly_programs/lui.s
new file mode 100644
index 0000000..028165e
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/lui.s
@@ -0,0 +1,111 @@
+# 1 "../../riscv-tests/isa/rv64ui/lui.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/lui.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# lui.S
+#-----------------------------------------------------------------------------
+
+# Test lui instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/lui.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/lui.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  test_2: li gp, 2; lui x1, 0x00000; li x7, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_3: li gp, 3; lui x1, 0xfffff;sra x1,x1,1; li x7, ((0xfffffffffffff800) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_4: li gp, 4; lui x1, 0x7ffff;sra x1,x1,20; li x7, ((0x00000000000007ff) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_5: li gp, 5; lui x1, 0x80000;sra x1,x1,20; li x7, ((0xfffffffffffff800) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+
+  test_6: li gp, 6; lui x0, 0x80000; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x0, x7, fail;;
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+
diff --git a/verilator-tests/testbench/assembly_programs/lw.s b/verilator-tests/testbench/assembly_programs/lw.s
new file mode 100644
index 0000000..017b40d
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/lw.s
@@ -0,0 +1,167 @@
+# 1 "../../riscv-tests/isa/rv64ui/lw.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/lw.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# lw.S
+#-----------------------------------------------------------------------------
+
+# Test lw instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/lw.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/lw.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  test_2: li gp, 2; li x15, 0x0000000000ff00ff; la x1, tdat; lw x14, 0(x1);; li x7, ((0x0000000000ff00ff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_3: li gp, 3; li x15, 0xffffffffff00ff00; la x1, tdat; lw x14, 4(x1);; li x7, ((0xffffffffff00ff00) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_4: li gp, 4; li x15, 0x000000000ff00ff0; la x1, tdat; lw x14, 8(x1);; li x7, ((0x000000000ff00ff0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_5: li gp, 5; li x15, 0xfffffffff00ff00f; la x1, tdat; lw x14, 12(x1);; li x7, ((0xfffffffff00ff00f) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  # Test with negative offset
+
+  test_6: li gp, 6; li x15, 0x0000000000ff00ff; la x1, tdat4; lw x14, -12(x1);; li x7, ((0x0000000000ff00ff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_7: li gp, 7; li x15, 0xffffffffff00ff00; la x1, tdat4; lw x14, -8(x1);; li x7, ((0xffffffffff00ff00) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_8: li gp, 8; li x15, 0x000000000ff00ff0; la x1, tdat4; lw x14, -4(x1);; li x7, ((0x000000000ff00ff0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_9: li gp, 9; li x15, 0xfffffffff00ff00f; la x1, tdat4; lw x14, 0(x1);; li x7, ((0xfffffffff00ff00f) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  # Test with a negative base
+
+  test_10: li gp, 10; la x1, tdat; addi x1, x1, -32; lw x5, 32(x1);; li x7, ((0x0000000000ff00ff) & ((1 << (64 - 1) << 1) - 1)); bne x5, x7, fail;
+
+
+
+
+
+  # Test with unaligned base
+
+  test_11: li gp, 11; la x1, tdat; addi x1, x1, -3; lw x5, 7(x1);; li x7, ((0xffffffffff00ff00) & ((1 << (64 - 1) << 1) - 1)); bne x5, x7, fail;
+
+
+
+
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_12: li gp, 12; li x4, 0; 1: la x1, tdat2; lw x14, 4(x1); addi x6, x14, 0; li x7, 0x000000000ff00ff0; bne x6, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;;
+  test_13: li gp, 13; li x4, 0; 1: la x1, tdat3; lw x14, 4(x1); nop; addi x6, x14, 0; li x7, 0xfffffffff00ff00f; bne x6, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;;
+  test_14: li gp, 14; li x4, 0; 1: la x1, tdat1; lw x14, 4(x1); nop; nop; addi x6, x14, 0; li x7, 0xffffffffff00ff00; bne x6, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;;
+
+  test_15: li gp, 15; li x4, 0; 1: la x1, tdat2; lw x14, 4(x1); li x7, 0x000000000ff00ff0; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_16: li gp, 16; li x4, 0; 1: la x1, tdat3; nop; lw x14, 4(x1); li x7, 0xfffffffff00ff00f; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_17: li gp, 17; li x4, 0; 1: la x1, tdat1; nop; nop; lw x14, 4(x1); li x7, 0xffffffffff00ff00; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+
+  #-------------------------------------------------------------
+  # Test write-after-write hazard
+  #-------------------------------------------------------------
+
+  test_18: li gp, 18; la x5, tdat; lw x2, 0(x5); li x2, 2;; li x7, ((2) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;
+
+
+
+
+
+  test_19: li gp, 19; la x5, tdat; lw x2, 0(x5); nop; li x2, 2;; li x7, ((2) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;
+
+
+
+
+
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+tdat:
+tdat1: .word 0x00ff00ff
+tdat2: .word 0xff00ff00
+tdat3: .word 0x0ff00ff0
+tdat4: .word 0xf00ff00f
+
+
diff --git a/verilator-tests/testbench/assembly_programs/lwu.s b/verilator-tests/testbench/assembly_programs/lwu.s
new file mode 100644
index 0000000..5177e3a
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/lwu.s
@@ -0,0 +1,167 @@
+# 1 "../../riscv-tests/isa/rv64ui/lwu.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/lwu.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# lwu.S
+#-----------------------------------------------------------------------------
+
+# Test lwu instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/lwu.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/lwu.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  test_2: li gp, 2; li x15, 0x0000000000ff00ff; la x1, tdat; lwu x14, 0(x1);; li x7, ((0x0000000000ff00ff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_3: li gp, 3; li x15, 0x00000000ff00ff00; la x1, tdat; lwu x14, 4(x1);; li x7, ((0x00000000ff00ff00) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_4: li gp, 4; li x15, 0x000000000ff00ff0; la x1, tdat; lwu x14, 8(x1);; li x7, ((0x000000000ff00ff0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_5: li gp, 5; li x15, 0x00000000f00ff00f; la x1, tdat; lwu x14, 12(x1);; li x7, ((0x00000000f00ff00f) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  # Test with negative offset
+
+  test_6: li gp, 6; li x15, 0x0000000000ff00ff; la x1, tdat4; lwu x14, -12(x1);; li x7, ((0x0000000000ff00ff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_7: li gp, 7; li x15, 0x00000000ff00ff00; la x1, tdat4; lwu x14, -8(x1);; li x7, ((0x00000000ff00ff00) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_8: li gp, 8; li x15, 0x000000000ff00ff0; la x1, tdat4; lwu x14, -4(x1);; li x7, ((0x000000000ff00ff0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_9: li gp, 9; li x15, 0x00000000f00ff00f; la x1, tdat4; lwu x14, 0(x1);; li x7, ((0x00000000f00ff00f) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  # Test with a negative base
+
+  test_10: li gp, 10; la x1, tdat; addi x1, x1, -32; lwu x5, 32(x1);; li x7, ((0x0000000000ff00ff) & ((1 << (64 - 1) << 1) - 1)); bne x5, x7, fail;
+
+
+
+
+
+  # Test with unaligned base
+
+  test_11: li gp, 11; la x1, tdat; addi x1, x1, -3; lwu x5, 7(x1);; li x7, ((0x00000000ff00ff00) & ((1 << (64 - 1) << 1) - 1)); bne x5, x7, fail;
+
+
+
+
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_12: li gp, 12; li x4, 0; 1: la x1, tdat2; lwu x14, 4(x1); addi x6, x14, 0; li x7, 0x000000000ff00ff0; bne x6, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;;
+  test_13: li gp, 13; li x4, 0; 1: la x1, tdat3; lwu x14, 4(x1); nop; addi x6, x14, 0; li x7, 0x00000000f00ff00f; bne x6, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;;
+  test_14: li gp, 14; li x4, 0; 1: la x1, tdat1; lwu x14, 4(x1); nop; nop; addi x6, x14, 0; li x7, 0x00000000ff00ff00; bne x6, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;;
+
+  test_15: li gp, 15; li x4, 0; 1: la x1, tdat2; lwu x14, 4(x1); li x7, 0x000000000ff00ff0; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_16: li gp, 16; li x4, 0; 1: la x1, tdat3; nop; lwu x14, 4(x1); li x7, 0x00000000f00ff00f; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_17: li gp, 17; li x4, 0; 1: la x1, tdat1; nop; nop; lwu x14, 4(x1); li x7, 0x00000000ff00ff00; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+
+  #-------------------------------------------------------------
+  # Test write-after-write hazard
+  #-------------------------------------------------------------
+
+  test_18: li gp, 18; la x5, tdat; lwu x2, 0(x5); li x2, 2;; li x7, ((2) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;
+
+
+
+
+
+  test_19: li gp, 19; la x5, tdat; lwu x2, 0(x5); nop; li x2, 2;; li x7, ((2) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;
+
+
+
+
+
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+tdat:
+tdat1: .word 0x00ff00ff
+tdat2: .word 0xff00ff00
+tdat3: .word 0x0ff00ff0
+tdat4: .word 0xf00ff00f
+
+
diff --git a/verilator-tests/testbench/assembly_programs/or.s b/verilator-tests/testbench/assembly_programs/or.s
new file mode 100644
index 0000000..1bdbdec
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/or.s
@@ -0,0 +1,144 @@
+# 1 "../../riscv-tests/isa/rv64ui/or.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/or.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# or.S
+#-----------------------------------------------------------------------------
+
+# Test or instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/or.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/or.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Logical tests
+  #-------------------------------------------------------------
+
+  test_2: li gp, 2; li x1, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0f0f0f0f) & ((1 << (64 - 1) << 1) - 1)); or x14, x1, x2;; li x7, ((0xff0fff0f) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_3: li gp, 3; li x1, ((0x0ff00ff0) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xf0f0f0f0) & ((1 << (64 - 1) << 1) - 1)); or x14, x1, x2;; li x7, ((0xfff0fff0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_4: li gp, 4; li x1, ((0x00ff00ff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0f0f0f0f) & ((1 << (64 - 1) << 1) - 1)); or x14, x1, x2;; li x7, ((0x0fff0fff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_5: li gp, 5; li x1, ((0xf00ff00f) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xf0f0f0f0) & ((1 << (64 - 1) << 1) - 1)); or x14, x1, x2;; li x7, ((0xf0fff0ff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  test_6: li gp, 6; li x1, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0f0f0f0f) & ((1 << (64 - 1) << 1) - 1)); or x1, x1, x2;; li x7, ((0xff0fff0f) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_7: li gp, 7; li x1, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0f0f0f0f) & ((1 << (64 - 1) << 1) - 1)); or x2, x1, x2;; li x7, ((0xff0fff0f) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_8: li gp, 8; li x1, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); or x1, x1, x1;; li x7, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_9: li gp, 9; li x4, 0; 1: li x1, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0f0f0f0f) & ((1 << (64 - 1) << 1) - 1)); or x14, x1, x2; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xff0fff0f) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_10: li gp, 10; li x4, 0; 1: li x1, ((0x0ff00ff0) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xf0f0f0f0) & ((1 << (64 - 1) << 1) - 1)); or x14, x1, x2; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xfff0fff0) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_11: li gp, 11; li x4, 0; 1: li x1, ((0x00ff00ff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0f0f0f0f) & ((1 << (64 - 1) << 1) - 1)); or x14, x1, x2; nop; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0fff0fff) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+
+  test_12: li gp, 12; li x4, 0; 1: li x1, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0f0f0f0f) & ((1 << (64 - 1) << 1) - 1)); or x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xff0fff0f) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_13: li gp, 13; li x4, 0; 1: li x1, ((0x0ff00ff0) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xf0f0f0f0) & ((1 << (64 - 1) << 1) - 1)); nop; or x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xfff0fff0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_14: li gp, 14; li x4, 0; 1: li x1, ((0x00ff00ff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0f0f0f0f) & ((1 << (64 - 1) << 1) - 1)); nop; nop; or x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0fff0fff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_15: li gp, 15; li x4, 0; 1: li x1, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); nop; li x2, ((0x0f0f0f0f) & ((1 << (64 - 1) << 1) - 1)); or x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xff0fff0f) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_16: li gp, 16; li x4, 0; 1: li x1, ((0x0ff00ff0) & ((1 << (64 - 1) << 1) - 1)); nop; li x2, ((0xf0f0f0f0) & ((1 << (64 - 1) << 1) - 1)); nop; or x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xfff0fff0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_17: li gp, 17; li x4, 0; 1: li x1, ((0x00ff00ff) & ((1 << (64 - 1) << 1) - 1)); nop; nop; li x2, ((0x0f0f0f0f) & ((1 << (64 - 1) << 1) - 1)); or x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0fff0fff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_18: li gp, 18; li x4, 0; 1: li x2, ((0x0f0f0f0f) & ((1 << (64 - 1) << 1) - 1)); li x1, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); or x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xff0fff0f) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_19: li gp, 19; li x4, 0; 1: li x2, ((0xf0f0f0f0) & ((1 << (64 - 1) << 1) - 1)); li x1, ((0x0ff00ff0) & ((1 << (64 - 1) << 1) - 1)); nop; or x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xfff0fff0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_20: li gp, 20; li x4, 0; 1: li x2, ((0x0f0f0f0f) & ((1 << (64 - 1) << 1) - 1)); li x1, ((0x00ff00ff) & ((1 << (64 - 1) << 1) - 1)); nop; nop; or x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0fff0fff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_21: li gp, 21; li x4, 0; 1: li x2, ((0x0f0f0f0f) & ((1 << (64 - 1) << 1) - 1)); nop; li x1, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); or x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xff0fff0f) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_22: li gp, 22; li x4, 0; 1: li x2, ((0xf0f0f0f0) & ((1 << (64 - 1) << 1) - 1)); nop; li x1, ((0x0ff00ff0) & ((1 << (64 - 1) << 1) - 1)); nop; or x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xfff0fff0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_23: li gp, 23; li x4, 0; 1: li x2, ((0x0f0f0f0f) & ((1 << (64 - 1) << 1) - 1)); nop; nop; li x1, ((0x00ff00ff) & ((1 << (64 - 1) << 1) - 1)); or x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0fff0fff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_24: li gp, 24; li x1, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); or x2, x0, x1;; li x7, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_25: li gp, 25; li x1, ((0x00ff00ff) & ((1 << (64 - 1) << 1) - 1)); or x2, x1, x0;; li x7, ((0x00ff00ff) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_26: li gp, 26; or x1, x0, x0;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_27: li gp, 27; li x1, ((0x11111111) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x22222222) & ((1 << (64 - 1) << 1) - 1)); or x0, x1, x2;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x0, x7, fail;;
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+
diff --git a/verilator-tests/testbench/assembly_programs/ori.s b/verilator-tests/testbench/assembly_programs/ori.s
new file mode 100644
index 0000000..7016d0a
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/ori.s
@@ -0,0 +1,130 @@
+# 1 "../../riscv-tests/isa/rv64ui/ori.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/ori.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# ori.S
+#-----------------------------------------------------------------------------
+
+# Test ori instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/ori.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/ori.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Logical tests
+  #-------------------------------------------------------------
+
+  test_2: li gp, 2; li x1, ((0xffffffffff00ff00) & ((1 << (64 - 1) << 1) - 1)); ori x14, x1, ((0xf0f) | (-(((0xf0f) >> 11) & 1) << 11));; li x7, ((0xffffffffffffff0f) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_3: li gp, 3; li x1, ((0x000000000ff00ff0) & ((1 << (64 - 1) << 1) - 1)); ori x14, x1, ((0x0f0) | (-(((0x0f0) >> 11) & 1) << 11));; li x7, ((0x000000000ff00ff0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_4: li gp, 4; li x1, ((0x0000000000ff00ff) & ((1 << (64 - 1) << 1) - 1)); ori x14, x1, ((0x70f) | (-(((0x70f) >> 11) & 1) << 11));; li x7, ((0x0000000000ff07ff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_5: li gp, 5; li x1, ((0xfffffffff00ff00f) & ((1 << (64 - 1) << 1) - 1)); ori x14, x1, ((0x0f0) | (-(((0x0f0) >> 11) & 1) << 11));; li x7, ((0xfffffffff00ff0ff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  test_6: li gp, 6; li x1, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); ori x1, x1, ((0x0f0) | (-(((0x0f0) >> 11) & 1) << 11));; li x7, ((0xff00fff0) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_7: li gp, 7; li x4, 0; 1: li x1, ((0x000000000ff00ff0) & ((1 << (64 - 1) << 1) - 1)); ori x14, x1, ((0x0f0) | (-(((0x0f0) >> 11) & 1) << 11)); addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x000000000ff00ff0) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_8: li gp, 8; li x4, 0; 1: li x1, ((0x0000000000ff00ff) & ((1 << (64 - 1) << 1) - 1)); ori x14, x1, ((0x70f) | (-(((0x70f) >> 11) & 1) << 11)); nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000ff07ff) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_9: li gp, 9; li x4, 0; 1: li x1, ((0xfffffffff00ff00f) & ((1 << (64 - 1) << 1) - 1)); ori x14, x1, ((0x0f0) | (-(((0x0f0) >> 11) & 1) << 11)); nop; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xfffffffff00ff0ff) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+
+  test_10: li gp, 10; li x4, 0; 1: li x1, ((0x000000000ff00ff0) & ((1 << (64 - 1) << 1) - 1)); ori x14, x1, ((0x0f0) | (-(((0x0f0) >> 11) & 1) << 11)); addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x000000000ff00ff0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_11: li gp, 11; li x4, 0; 1: li x1, ((0x0000000000ff00ff) & ((1 << (64 - 1) << 1) - 1)); nop; ori x14, x1, ((0xf0f) | (-(((0xf0f) >> 11) & 1) << 11)); addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_12: li gp, 12; li x4, 0; 1: li x1, ((0xfffffffff00ff00f) & ((1 << (64 - 1) << 1) - 1)); nop; nop; ori x14, x1, ((0x0f0) | (-(((0x0f0) >> 11) & 1) << 11)); addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xfffffffff00ff0ff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_13: li gp, 13; ori x1, x0, ((0x0f0) | (-(((0x0f0) >> 11) & 1) << 11));; li x7, ((0x0f0) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_14: li gp, 14; li x1, ((0x00ff00ff) & ((1 << (64 - 1) << 1) - 1)); ori x0, x1, ((0x70f) | (-(((0x70f) >> 11) & 1) << 11));; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x0, x7, fail;;
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+
diff --git a/verilator-tests/testbench/assembly_programs/sb.s b/verilator-tests/testbench/assembly_programs/sb.s
new file mode 100644
index 0000000..89702c4
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/sb.s
@@ -0,0 +1,164 @@
+# 1 "../../riscv-tests/isa/rv64ui/sb.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/sb.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sb.S
+#-----------------------------------------------------------------------------
+
+# Test sb instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/sb.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/sb.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  test_2: li gp, 2; la x1, tdat; li x2, 0xffffffffffffffaa; la x15, 7f; sb x2, 0(x1); lb x14, 0(x1); j 8f; 7: mv x14, x2; 8:; li x7, ((0xffffffffffffffaa) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_3: li gp, 3; la x1, tdat; li x2, 0x0000000000000000; la x15, 7f; sb x2, 1(x1); lb x14, 1(x1); j 8f; 7: mv x14, x2; 8:; li x7, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_4: li gp, 4; la x1, tdat; li x2, 0xffffffffffffefa0; la x15, 7f; sb x2, 2(x1); lh x14, 2(x1); j 8f; 7: mv x14, x2; 8:; li x7, ((0xffffffffffffefa0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_5: li gp, 5; la x1, tdat; li x2, 0x000000000000000a; la x15, 7f; sb x2, 3(x1); lb x14, 3(x1); j 8f; 7: mv x14, x2; 8:; li x7, ((0x000000000000000a) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  # Test with negative offset
+
+  test_6: li gp, 6; la x1, tdat8; li x2, 0xffffffffffffffaa; la x15, 7f; sb x2, -3(x1); lb x14, -3(x1); j 8f; 7: mv x14, x2; 8:; li x7, ((0xffffffffffffffaa) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_7: li gp, 7; la x1, tdat8; li x2, 0x0000000000000000; la x15, 7f; sb x2, -2(x1); lb x14, -2(x1); j 8f; 7: mv x14, x2; 8:; li x7, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_8: li gp, 8; la x1, tdat8; li x2, 0xffffffffffffffa0; la x15, 7f; sb x2, -1(x1); lb x14, -1(x1); j 8f; 7: mv x14, x2; 8:; li x7, ((0xffffffffffffffa0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_9: li gp, 9; la x1, tdat8; li x2, 0x000000000000000a; la x15, 7f; sb x2, 0(x1); lb x14, 0(x1); j 8f; 7: mv x14, x2; 8:; li x7, ((0x000000000000000a) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  # Test with a negative base
+
+  test_10: li gp, 10; la x1, tdat9; li x2, 0x12345678; addi x4, x1, -32; sb x2, 32(x4); lb x5, 0(x1);; li x7, ((0x78) & ((1 << (64 - 1) << 1) - 1)); bne x5, x7, fail;
+
+
+
+
+
+
+
+  # Test with unaligned base
+
+  test_11: li gp, 11; la x1, tdat9; li x2, 0x00003098; addi x1, x1, -6; sb x2, 7(x1); la x4, tdat10; lb x5, 0(x4);; li x7, ((0xffffffffffffff98) & ((1 << (64 - 1) << 1) - 1)); bne x5, x7, fail;
+# 53 "../../riscv-tests/isa/rv64ui/sb.S"
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_12: li gp, 12; li x4, 0; 1: li x1, 0xffffffffffffffdd; la x2, tdat; sb x1, 0(x2); lb x14, 0(x2); li x7, 0xffffffffffffffdd; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_13: li gp, 13; li x4, 0; 1: li x1, 0xffffffffffffffcd; la x2, tdat; nop; sb x1, 1(x2); lb x14, 1(x2); li x7, 0xffffffffffffffcd; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_14: li gp, 14; li x4, 0; 1: li x1, 0xffffffffffffffcc; la x2, tdat; nop; nop; sb x1, 2(x2); lb x14, 2(x2); li x7, 0xffffffffffffffcc; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_15: li gp, 15; li x4, 0; 1: li x1, 0xffffffffffffffbc; nop; la x2, tdat; sb x1, 3(x2); lb x14, 3(x2); li x7, 0xffffffffffffffbc; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_16: li gp, 16; li x4, 0; 1: li x1, 0xffffffffffffffbb; nop; la x2, tdat; nop; sb x1, 4(x2); lb x14, 4(x2); li x7, 0xffffffffffffffbb; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_17: li gp, 17; li x4, 0; 1: li x1, 0xffffffffffffffab; nop; nop; la x2, tdat; sb x1, 5(x2); lb x14, 5(x2); li x7, 0xffffffffffffffab; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+
+  test_18: li gp, 18; li x4, 0; 1: la x2, tdat; li x1, 0x33; sb x1, 0(x2); lb x14, 0(x2); li x7, 0x33; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_19: li gp, 19; li x4, 0; 1: la x2, tdat; li x1, 0x23; nop; sb x1, 1(x2); lb x14, 1(x2); li x7, 0x23; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_20: li gp, 20; li x4, 0; 1: la x2, tdat; li x1, 0x22; nop; nop; sb x1, 2(x2); lb x14, 2(x2); li x7, 0x22; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_21: li gp, 21; li x4, 0; 1: la x2, tdat; nop; li x1, 0x12; sb x1, 3(x2); lb x14, 3(x2); li x7, 0x12; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_22: li gp, 22; li x4, 0; 1: la x2, tdat; nop; li x1, 0x11; nop; sb x1, 4(x2); lb x14, 4(x2); li x7, 0x11; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_23: li gp, 23; li x4, 0; 1: la x2, tdat; nop; nop; li x1, 0x01; sb x1, 5(x2); lb x14, 5(x2); li x7, 0x01; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+
+  li a0, 0xef
+  la a1, tdat
+  sb a0, 3(a1)
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+tdat:
+tdat1: .byte 0xef
+tdat2: .byte 0xef
+tdat3: .byte 0xef
+tdat4: .byte 0xef
+tdat5: .byte 0xef
+tdat6: .byte 0xef
+tdat7: .byte 0xef
+tdat8: .byte 0xef
+tdat9: .byte 0xef
+tdat10: .byte 0xef
+
+
diff --git a/verilator-tests/testbench/assembly_programs/sd.s b/verilator-tests/testbench/assembly_programs/sd.s
new file mode 100644
index 0000000..efd5783
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/sd.s
@@ -0,0 +1,160 @@
+# 1 "../../riscv-tests/isa/rv64ui/sd.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/sd.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sd.S
+#-----------------------------------------------------------------------------
+
+# Test sd instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/sd.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/sd.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  test_2: li gp, 2; la x1, tdat; li x2, 0x00aa00aa00aa00aa; la x15, 7f; sd x2, 0(x1); ld x14, 0(x1); j 8f; 7: mv x14, x2; 8:; li x7, ((0x00aa00aa00aa00aa) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_3: li gp, 3; la x1, tdat; li x2, 0xaa00aa00aa00aa00; la x15, 7f; sd x2, 8(x1); ld x14, 8(x1); j 8f; 7: mv x14, x2; 8:; li x7, ((0xaa00aa00aa00aa00) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_4: li gp, 4; la x1, tdat; li x2, 0x0aa00aa00aa00aa0; la x15, 7f; sd x2, 16(x1); ld x14, 16(x1); j 8f; 7: mv x14, x2; 8:; li x7, ((0x0aa00aa00aa00aa0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_5: li gp, 5; la x1, tdat; li x2, 0xa00aa00aa00aa00a; la x15, 7f; sd x2, 24(x1); ld x14, 24(x1); j 8f; 7: mv x14, x2; 8:; li x7, ((0xa00aa00aa00aa00a) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  # Test with negative offset
+
+  test_6: li gp, 6; la x1, tdat8; li x2, 0x00aa00aa00aa00aa; la x15, 7f; sd x2, -24(x1); ld x14, -24(x1); j 8f; 7: mv x14, x2; 8:; li x7, ((0x00aa00aa00aa00aa) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_7: li gp, 7; la x1, tdat8; li x2, 0xaa00aa00aa00aa00; la x15, 7f; sd x2, -16(x1); ld x14, -16(x1); j 8f; 7: mv x14, x2; 8:; li x7, ((0xaa00aa00aa00aa00) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_8: li gp, 8; la x1, tdat8; li x2, 0x0aa00aa00aa00aa0; la x15, 7f; sd x2, -8(x1); ld x14, -8(x1); j 8f; 7: mv x14, x2; 8:; li x7, ((0x0aa00aa00aa00aa0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_9: li gp, 9; la x1, tdat8; li x2, 0xa00aa00aa00aa00a; la x15, 7f; sd x2, 0(x1); ld x14, 0(x1); j 8f; 7: mv x14, x2; 8:; li x7, ((0xa00aa00aa00aa00a) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  # Test with a negative base
+
+  test_10: li gp, 10; la x1, tdat9; li x2, 0x1234567812345678; addi x4, x1, -32; sd x2, 32(x4); ld x5, 0(x1);; li x7, ((0x1234567812345678) & ((1 << (64 - 1) << 1) - 1)); bne x5, x7, fail;
+
+
+
+
+
+
+
+  # Test with unaligned base
+
+  test_11: li gp, 11; la x1, tdat9; li x2, 0x5821309858213098; addi x1, x1, -3; sd x2, 11(x1); la x4, tdat10; ld x5, 0(x4);; li x7, ((0x5821309858213098) & ((1 << (64 - 1) << 1) - 1)); bne x5, x7, fail;
+# 53 "../../riscv-tests/isa/rv64ui/sd.S"
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_12: li gp, 12; li x4, 0; 1: li x1, 0xabbccdd; la x2, tdat; sd x1, 0(x2); ld x14, 0(x2); li x7, 0xabbccdd; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_13: li gp, 13; li x4, 0; 1: li x1, 0xaabbccd; la x2, tdat; nop; sd x1, 8(x2); ld x14, 8(x2); li x7, 0xaabbccd; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_14: li gp, 14; li x4, 0; 1: li x1, 0xdaabbcc; la x2, tdat; nop; nop; sd x1, 16(x2); ld x14, 16(x2); li x7, 0xdaabbcc; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_15: li gp, 15; li x4, 0; 1: li x1, 0xddaabbc; nop; la x2, tdat; sd x1, 24(x2); ld x14, 24(x2); li x7, 0xddaabbc; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_16: li gp, 16; li x4, 0; 1: li x1, 0xcddaabb; nop; la x2, tdat; nop; sd x1, 32(x2); ld x14, 32(x2); li x7, 0xcddaabb; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_17: li gp, 17; li x4, 0; 1: li x1, 0xccddaab; nop; nop; la x2, tdat; sd x1, 40(x2); ld x14, 40(x2); li x7, 0xccddaab; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+
+  test_18: li gp, 18; li x4, 0; 1: la x2, tdat; li x1, 0x00112233; sd x1, 0(x2); ld x14, 0(x2); li x7, 0x00112233; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_19: li gp, 19; li x4, 0; 1: la x2, tdat; li x1, 0x30011223; nop; sd x1, 8(x2); ld x14, 8(x2); li x7, 0x30011223; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_20: li gp, 20; li x4, 0; 1: la x2, tdat; li x1, 0x33001122; nop; nop; sd x1, 16(x2); ld x14, 16(x2); li x7, 0x33001122; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_21: li gp, 21; li x4, 0; 1: la x2, tdat; nop; li x1, 0x23300112; sd x1, 24(x2); ld x14, 24(x2); li x7, 0x23300112; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_22: li gp, 22; li x4, 0; 1: la x2, tdat; nop; li x1, 0x22330011; nop; sd x1, 32(x2); ld x14, 32(x2); li x7, 0x22330011; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_23: li gp, 23; li x4, 0; 1: la x2, tdat; nop; nop; li x1, 0x12233001; sd x1, 40(x2); ld x14, 40(x2); li x7, 0x12233001; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+tdat:
+tdat1: .dword 0xdeadbeefdeadbeef
+tdat2: .dword 0xdeadbeefdeadbeef
+tdat3: .dword 0xdeadbeefdeadbeef
+tdat4: .dword 0xdeadbeefdeadbeef
+tdat5: .dword 0xdeadbeefdeadbeef
+tdat6: .dword 0xdeadbeefdeadbeef
+tdat7: .dword 0xdeadbeefdeadbeef
+tdat8: .dword 0xdeadbeefdeadbeef
+tdat9: .dword 0xdeadbeefdeadbeef
+tdat10: .dword 0xdeadbeefdeadbeef
+
+
diff --git a/verilator-tests/testbench/assembly_programs/sh.s b/verilator-tests/testbench/assembly_programs/sh.s
new file mode 100644
index 0000000..74c66c7
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/sh.s
@@ -0,0 +1,164 @@
+# 1 "../../riscv-tests/isa/rv64ui/sh.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/sh.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sh.S
+#-----------------------------------------------------------------------------
+
+# Test sh instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/sh.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/sh.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  test_2: li gp, 2; la x1, tdat; li x2, 0x00000000000000aa; la x15, 7f; sh x2, 0(x1); lh x14, 0(x1); j 8f; 7: mv x14, x2; 8:; li x7, ((0x00000000000000aa) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_3: li gp, 3; la x1, tdat; li x2, 0xffffffffffffaa00; la x15, 7f; sh x2, 2(x1); lh x14, 2(x1); j 8f; 7: mv x14, x2; 8:; li x7, ((0xffffffffffffaa00) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_4: li gp, 4; la x1, tdat; li x2, 0xffffffffbeef0aa0; la x15, 7f; sh x2, 4(x1); lw x14, 4(x1); j 8f; 7: mv x14, x2; 8:; li x7, ((0xffffffffbeef0aa0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_5: li gp, 5; la x1, tdat; li x2, 0xffffffffffffa00a; la x15, 7f; sh x2, 6(x1); lh x14, 6(x1); j 8f; 7: mv x14, x2; 8:; li x7, ((0xffffffffffffa00a) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  # Test with negative offset
+
+  test_6: li gp, 6; la x1, tdat8; li x2, 0x00000000000000aa; la x15, 7f; sh x2, -6(x1); lh x14, -6(x1); j 8f; 7: mv x14, x2; 8:; li x7, ((0x00000000000000aa) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_7: li gp, 7; la x1, tdat8; li x2, 0xffffffffffffaa00; la x15, 7f; sh x2, -4(x1); lh x14, -4(x1); j 8f; 7: mv x14, x2; 8:; li x7, ((0xffffffffffffaa00) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_8: li gp, 8; la x1, tdat8; li x2, 0x0000000000000aa0; la x15, 7f; sh x2, -2(x1); lh x14, -2(x1); j 8f; 7: mv x14, x2; 8:; li x7, ((0x0000000000000aa0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_9: li gp, 9; la x1, tdat8; li x2, 0xffffffffffffa00a; la x15, 7f; sh x2, 0(x1); lh x14, 0(x1); j 8f; 7: mv x14, x2; 8:; li x7, ((0xffffffffffffa00a) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  # Test with a negative base
+
+  test_10: li gp, 10; la x1, tdat9; li x2, 0x12345678; addi x4, x1, -32; sh x2, 32(x4); lh x5, 0(x1);; li x7, ((0x5678) & ((1 << (64 - 1) << 1) - 1)); bne x5, x7, fail;
+
+
+
+
+
+
+
+  # Test with unaligned base
+
+  test_11: li gp, 11; la x1, tdat9; li x2, 0x00003098; addi x1, x1, -5; sh x2, 7(x1); la x4, tdat10; lh x5, 0(x4);; li x7, ((0x3098) & ((1 << (64 - 1) << 1) - 1)); bne x5, x7, fail;
+# 53 "../../riscv-tests/isa/rv64ui/sh.S"
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_12: li gp, 12; li x4, 0; 1: li x1, 0xffffffffffffccdd; la x2, tdat; sh x1, 0(x2); lh x14, 0(x2); li x7, 0xffffffffffffccdd; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_13: li gp, 13; li x4, 0; 1: li x1, 0xffffffffffffbccd; la x2, tdat; nop; sh x1, 2(x2); lh x14, 2(x2); li x7, 0xffffffffffffbccd; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_14: li gp, 14; li x4, 0; 1: li x1, 0xffffffffffffbbcc; la x2, tdat; nop; nop; sh x1, 4(x2); lh x14, 4(x2); li x7, 0xffffffffffffbbcc; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_15: li gp, 15; li x4, 0; 1: li x1, 0xffffffffffffabbc; nop; la x2, tdat; sh x1, 6(x2); lh x14, 6(x2); li x7, 0xffffffffffffabbc; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_16: li gp, 16; li x4, 0; 1: li x1, 0xffffffffffffaabb; nop; la x2, tdat; nop; sh x1, 8(x2); lh x14, 8(x2); li x7, 0xffffffffffffaabb; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_17: li gp, 17; li x4, 0; 1: li x1, 0xffffffffffffdaab; nop; nop; la x2, tdat; sh x1, 10(x2); lh x14, 10(x2); li x7, 0xffffffffffffdaab; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+
+  test_18: li gp, 18; li x4, 0; 1: la x2, tdat; li x1, 0x2233; sh x1, 0(x2); lh x14, 0(x2); li x7, 0x2233; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_19: li gp, 19; li x4, 0; 1: la x2, tdat; li x1, 0x1223; nop; sh x1, 2(x2); lh x14, 2(x2); li x7, 0x1223; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_20: li gp, 20; li x4, 0; 1: la x2, tdat; li x1, 0x1122; nop; nop; sh x1, 4(x2); lh x14, 4(x2); li x7, 0x1122; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_21: li gp, 21; li x4, 0; 1: la x2, tdat; nop; li x1, 0x0112; sh x1, 6(x2); lh x14, 6(x2); li x7, 0x0112; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_22: li gp, 22; li x4, 0; 1: la x2, tdat; nop; li x1, 0x0011; nop; sh x1, 8(x2); lh x14, 8(x2); li x7, 0x0011; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_23: li gp, 23; li x4, 0; 1: la x2, tdat; nop; nop; li x1, 0x3001; sh x1, 10(x2); lh x14, 10(x2); li x7, 0x3001; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+
+  li a0, 0xbeef
+  la a1, tdat
+  sh a0, 6(a1)
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+tdat:
+tdat1: .half 0xbeef
+tdat2: .half 0xbeef
+tdat3: .half 0xbeef
+tdat4: .half 0xbeef
+tdat5: .half 0xbeef
+tdat6: .half 0xbeef
+tdat7: .half 0xbeef
+tdat8: .half 0xbeef
+tdat9: .half 0xbeef
+tdat10: .half 0xbeef
+
+
diff --git a/verilator-tests/testbench/assembly_programs/sll.s b/verilator-tests/testbench/assembly_programs/sll.s
new file mode 100644
index 0000000..91dd2f1
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/sll.s
@@ -0,0 +1,171 @@
+# 1 "../../riscv-tests/isa/rv64ui/sll.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/sll.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sll.S
+#-----------------------------------------------------------------------------
+
+# Test sll instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/sll.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/sll.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  test_2: li gp, 2; li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0) & ((1 << (64 - 1) << 1) - 1)); sll x14, x1, x2;; li x7, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_3: li gp, 3; li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); li x2, ((1) & ((1 << (64 - 1) << 1) - 1)); sll x14, x1, x2;; li x7, ((0x0000000000000002) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_4: li gp, 4; li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); sll x14, x1, x2;; li x7, ((0x0000000000000080) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_5: li gp, 5; li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); sll x14, x1, x2;; li x7, ((0x0000000000004000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_6: li gp, 6; li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); sll x14, x1, x2;; li x7, ((0x0000000080000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_7: li gp, 7; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0) & ((1 << (64 - 1) << 1) - 1)); sll x14, x1, x2;; li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_8: li gp, 8; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((1) & ((1 << (64 - 1) << 1) - 1)); sll x14, x1, x2;; li x7, ((0xfffffffffffffffe) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_9: li gp, 9; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); sll x14, x1, x2;; li x7, ((0xffffffffffffff80) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_10: li gp, 10; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); sll x14, x1, x2;; li x7, ((0xffffffffffffc000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_11: li gp, 11; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); sll x14, x1, x2;; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_12: li gp, 12; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0) & ((1 << (64 - 1) << 1) - 1)); sll x14, x1, x2;; li x7, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_13: li gp, 13; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); li x2, ((1) & ((1 << (64 - 1) << 1) - 1)); sll x14, x1, x2;; li x7, ((0x0000000042424242) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_14: li gp, 14; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); sll x14, x1, x2;; li x7, ((0x0000001090909080) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_15: li gp, 15; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); sll x14, x1, x2;; li x7, ((0x0000084848484000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_16: li gp, 16; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); sll x14, x1, x2;; li x7, ((0x1090909080000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  # Verify that shifts only use bottom six(rv64) or five(rv32) bits
+
+  test_17: li gp, 17; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffffffc0) & ((1 << (64 - 1) << 1) - 1)); sll x14, x1, x2;; li x7, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_18: li gp, 18; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffffffc1) & ((1 << (64 - 1) << 1) - 1)); sll x14, x1, x2;; li x7, ((0x0000000042424242) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_19: li gp, 19; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffffffc7) & ((1 << (64 - 1) << 1) - 1)); sll x14, x1, x2;; li x7, ((0x0000001090909080) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_20: li gp, 20; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffffffce) & ((1 << (64 - 1) << 1) - 1)); sll x14, x1, x2;; li x7, ((0x0000084848484000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+
+  test_21: li gp, 21; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); sll x14, x1, x2;; li x7, ((0x8000000000000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_50: li gp, 50; li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); li x2, ((63) & ((1 << (64 - 1) << 1) - 1)); sll x14, x1, x2;; li x7, ((0x8000000000000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_51: li gp, 51; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((39) & ((1 << (64 - 1) << 1) - 1)); sll x14, x1, x2;; li x7, ((0xffffff8000000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_52: li gp, 52; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); li x2, ((43) & ((1 << (64 - 1) << 1) - 1)); sll x14, x1, x2;; li x7, ((0x0909080000000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  test_22: li gp, 22; li x1, ((0x00000001) & ((1 << (64 - 1) << 1) - 1)); li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); sll x1, x1, x2;; li x7, ((0x00000080) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_23: li gp, 23; li x1, ((0x00000001) & ((1 << (64 - 1) << 1) - 1)); li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); sll x2, x1, x2;; li x7, ((0x00004000) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_24: li gp, 24; li x1, ((3) & ((1 << (64 - 1) << 1) - 1)); sll x1, x1, x1;; li x7, ((24) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_25: li gp, 25; li x4, 0; 1: li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); sll x14, x1, x2; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000000080) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_26: li gp, 26; li x4, 0; 1: li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); sll x14, x1, x2; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000004000) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_27: li gp, 27; li x4, 0; 1: li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); sll x14, x1, x2; nop; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000080000000) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+
+  test_28: li gp, 28; li x4, 0; 1: li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); sll x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000000080) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_29: li gp, 29; li x4, 0; 1: li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); nop; sll x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000004000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_30: li gp, 30; li x4, 0; 1: li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); nop; nop; sll x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000080000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_31: li gp, 31; li x4, 0; 1: li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); nop; li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); sll x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000000080) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_32: li gp, 32; li x4, 0; 1: li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); nop; li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); nop; sll x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000004000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_33: li gp, 33; li x4, 0; 1: li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); nop; nop; li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); sll x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000080000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_34: li gp, 34; li x4, 0; 1: li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); sll x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000000080) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_35: li gp, 35; li x4, 0; 1: li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); nop; sll x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000004000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_36: li gp, 36; li x4, 0; 1: li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); nop; nop; sll x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000080000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_37: li gp, 37; li x4, 0; 1: li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); nop; li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); sll x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000000080) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_38: li gp, 38; li x4, 0; 1: li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); nop; li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); nop; sll x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000004000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_39: li gp, 39; li x4, 0; 1: li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); nop; nop; li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); sll x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000080000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_40: li gp, 40; li x1, ((15) & ((1 << (64 - 1) << 1) - 1)); sll x2, x0, x1;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_41: li gp, 41; li x1, ((32) & ((1 << (64 - 1) << 1) - 1)); sll x2, x1, x0;; li x7, ((32) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_42: li gp, 42; sll x1, x0, x0;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_43: li gp, 43; li x1, ((1024) & ((1 << (64 - 1) << 1) - 1)); li x2, ((2048) & ((1 << (64 - 1) << 1) - 1)); sll x0, x1, x2;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x0, x7, fail;;
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+
diff --git a/verilator-tests/testbench/assembly_programs/slli.s b/verilator-tests/testbench/assembly_programs/slli.s
new file mode 100644
index 0000000..5519dd9
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/slli.s
@@ -0,0 +1,149 @@
+# 1 "../../riscv-tests/isa/rv64ui/slli.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/slli.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# slli.S
+#-----------------------------------------------------------------------------
+
+# Test slli instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/slli.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/slli.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  test_2: li gp, 2; li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); slli x14, x1, ((0) | (-(((0) >> 11) & 1) << 11));; li x7, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_3: li gp, 3; li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); slli x14, x1, ((1) | (-(((1) >> 11) & 1) << 11));; li x7, ((0x0000000000000002) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_4: li gp, 4; li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); slli x14, x1, ((7) | (-(((7) >> 11) & 1) << 11));; li x7, ((0x0000000000000080) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_5: li gp, 5; li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); slli x14, x1, ((14) | (-(((14) >> 11) & 1) << 11));; li x7, ((0x0000000000004000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_6: li gp, 6; li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); slli x14, x1, ((31) | (-(((31) >> 11) & 1) << 11));; li x7, ((0x0000000080000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_7: li gp, 7; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); slli x14, x1, ((0) | (-(((0) >> 11) & 1) << 11));; li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_8: li gp, 8; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); slli x14, x1, ((1) | (-(((1) >> 11) & 1) << 11));; li x7, ((0xfffffffffffffffe) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_9: li gp, 9; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); slli x14, x1, ((7) | (-(((7) >> 11) & 1) << 11));; li x7, ((0xffffffffffffff80) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_10: li gp, 10; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); slli x14, x1, ((14) | (-(((14) >> 11) & 1) << 11));; li x7, ((0xffffffffffffc000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_11: li gp, 11; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); slli x14, x1, ((31) | (-(((31) >> 11) & 1) << 11));; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_12: li gp, 12; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); slli x14, x1, ((0) | (-(((0) >> 11) & 1) << 11));; li x7, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_13: li gp, 13; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); slli x14, x1, ((1) | (-(((1) >> 11) & 1) << 11));; li x7, ((0x0000000042424242) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_14: li gp, 14; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); slli x14, x1, ((7) | (-(((7) >> 11) & 1) << 11));; li x7, ((0x0000001090909080) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_15: li gp, 15; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); slli x14, x1, ((14) | (-(((14) >> 11) & 1) << 11));; li x7, ((0x0000084848484000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_16: li gp, 16; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); slli x14, x1, ((31) | (-(((31) >> 11) & 1) << 11));; li x7, ((0x1090909080000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+
+  test_50: li gp, 50; li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); slli x14, x1, ((63) | (-(((63) >> 11) & 1) << 11));; li x7, ((0x8000000000000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_51: li gp, 51; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); slli x14, x1, ((39) | (-(((39) >> 11) & 1) << 11));; li x7, ((0xffffff8000000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_52: li gp, 52; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); slli x14, x1, ((43) | (-(((43) >> 11) & 1) << 11));; li x7, ((0x0909080000000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  test_17: li gp, 17; li x1, ((0x00000001) & ((1 << (64 - 1) << 1) - 1)); slli x1, x1, ((7) | (-(((7) >> 11) & 1) << 11));; li x7, ((0x00000080) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_18: li gp, 18; li x4, 0; 1: li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); slli x14, x1, ((7) | (-(((7) >> 11) & 1) << 11)); addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000000080) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_19: li gp, 19; li x4, 0; 1: li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); slli x14, x1, ((14) | (-(((14) >> 11) & 1) << 11)); nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000004000) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_20: li gp, 20; li x4, 0; 1: li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); slli x14, x1, ((31) | (-(((31) >> 11) & 1) << 11)); nop; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000080000000) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+
+  test_21: li gp, 21; li x4, 0; 1: li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); slli x14, x1, ((7) | (-(((7) >> 11) & 1) << 11)); addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000000080) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_22: li gp, 22; li x4, 0; 1: li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); nop; slli x14, x1, ((14) | (-(((14) >> 11) & 1) << 11)); addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000004000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_23: li gp, 23; li x4, 0; 1: li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); nop; nop; slli x14, x1, ((31) | (-(((31) >> 11) & 1) << 11)); addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000080000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_24: li gp, 24; slli x1, x0, ((31) | (-(((31) >> 11) & 1) << 11));; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_25: li gp, 25; li x1, ((33) & ((1 << (64 - 1) << 1) - 1)); slli x0, x1, ((20) | (-(((20) >> 11) & 1) << 11));; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x0, x7, fail;;
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+
diff --git a/verilator-tests/testbench/assembly_programs/slliw.s b/verilator-tests/testbench/assembly_programs/slliw.s
new file mode 100644
index 0000000..891e762
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/slliw.s
@@ -0,0 +1,150 @@
+# 1 "../../riscv-tests/isa/rv64ui/slliw.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/slliw.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# slliw.S
+#-----------------------------------------------------------------------------
+
+# Test slliw instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/slliw.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/slliw.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  test_2: li gp, 2; li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); slliw x14, x1, ((0) | (-(((0) >> 11) & 1) << 11));; li x7, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_3: li gp, 3; li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); slliw x14, x1, ((1) | (-(((1) >> 11) & 1) << 11));; li x7, ((0x0000000000000002) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_4: li gp, 4; li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); slliw x14, x1, ((7) | (-(((7) >> 11) & 1) << 11));; li x7, ((0x0000000000000080) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_5: li gp, 5; li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); slliw x14, x1, ((14) | (-(((14) >> 11) & 1) << 11));; li x7, ((0x0000000000004000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_6: li gp, 6; li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); slliw x14, x1, ((31) | (-(((31) >> 11) & 1) << 11));; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_7: li gp, 7; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); slliw x14, x1, ((0) | (-(((0) >> 11) & 1) << 11));; li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_8: li gp, 8; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); slliw x14, x1, ((1) | (-(((1) >> 11) & 1) << 11));; li x7, ((0xfffffffffffffffe) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_9: li gp, 9; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); slliw x14, x1, ((7) | (-(((7) >> 11) & 1) << 11));; li x7, ((0xffffffffffffff80) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_10: li gp, 10; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); slliw x14, x1, ((14) | (-(((14) >> 11) & 1) << 11));; li x7, ((0xffffffffffffc000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_11: li gp, 11; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); slliw x14, x1, ((31) | (-(((31) >> 11) & 1) << 11));; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_12: li gp, 12; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); slliw x14, x1, ((0) | (-(((0) >> 11) & 1) << 11));; li x7, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_13: li gp, 13; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); slliw x14, x1, ((1) | (-(((1) >> 11) & 1) << 11));; li x7, ((0x0000000042424242) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_14: li gp, 14; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); slliw x14, x1, ((7) | (-(((7) >> 11) & 1) << 11));; li x7, ((0xffffffff90909080) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_15: li gp, 15; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); slliw x14, x1, ((14) | (-(((14) >> 11) & 1) << 11));; li x7, ((0x0000000048484000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_16: li gp, 16; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); slliw x14, x1, ((31) | (-(((31) >> 11) & 1) << 11));; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  # Verify that shifts ignore top 32 (using true 64-bit values)
+
+  test_44: li gp, 44; li x1, ((0xffffffff12345678) & ((1 << (64 - 1) << 1) - 1)); slliw x14, x1, ((0) | (-(((0) >> 11) & 1) << 11));; li x7, ((0x0000000012345678) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_45: li gp, 45; li x1, ((0xffffffff12345678) & ((1 << (64 - 1) << 1) - 1)); slliw x14, x1, ((4) | (-(((4) >> 11) & 1) << 11));; li x7, ((0x0000000023456780) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_46: li gp, 46; li x1, ((0x0000000092345678) & ((1 << (64 - 1) << 1) - 1)); slliw x14, x1, ((0) | (-(((0) >> 11) & 1) << 11));; li x7, ((0xffffffff92345678) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_47: li gp, 47; li x1, ((0x0000000099345678) & ((1 << (64 - 1) << 1) - 1)); slliw x14, x1, ((4) | (-(((4) >> 11) & 1) << 11));; li x7, ((0xffffffff93456780) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  test_17: li gp, 17; li x1, ((0x00000001) & ((1 << (64 - 1) << 1) - 1)); slliw x1, x1, ((7) | (-(((7) >> 11) & 1) << 11));; li x7, ((0x00000080) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_18: li gp, 18; li x4, 0; 1: li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); slliw x14, x1, ((7) | (-(((7) >> 11) & 1) << 11)); addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000000080) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_19: li gp, 19; li x4, 0; 1: li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); slliw x14, x1, ((14) | (-(((14) >> 11) & 1) << 11)); nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000004000) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_20: li gp, 20; li x4, 0; 1: li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); slliw x14, x1, ((31) | (-(((31) >> 11) & 1) << 11)); nop; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+
+  test_21: li gp, 21; li x4, 0; 1: li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); slliw x14, x1, ((7) | (-(((7) >> 11) & 1) << 11)); addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000000080) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_22: li gp, 22; li x4, 0; 1: li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); nop; slliw x14, x1, ((14) | (-(((14) >> 11) & 1) << 11)); addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000004000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_23: li gp, 23; li x4, 0; 1: li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); nop; nop; slliw x14, x1, ((31) | (-(((31) >> 11) & 1) << 11)); addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_24: li gp, 24; slliw x1, x0, ((31) | (-(((31) >> 11) & 1) << 11));; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_25: li gp, 25; li x1, ((31) & ((1 << (64 - 1) << 1) - 1)); slliw x0, x1, ((28) | (-(((28) >> 11) & 1) << 11));; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x0, x7, fail;;
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+
diff --git a/verilator-tests/testbench/assembly_programs/sllw.s b/verilator-tests/testbench/assembly_programs/sllw.s
new file mode 100644
index 0000000..4370433
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/sllw.s
@@ -0,0 +1,172 @@
+# 1 "../../riscv-tests/isa/rv64ui/sllw.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/sllw.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sllw.S
+#-----------------------------------------------------------------------------
+
+# Test sllw instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/sllw.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/sllw.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  test_2: li gp, 2; li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0) & ((1 << (64 - 1) << 1) - 1)); sllw x14, x1, x2;; li x7, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_3: li gp, 3; li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); li x2, ((1) & ((1 << (64 - 1) << 1) - 1)); sllw x14, x1, x2;; li x7, ((0x0000000000000002) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_4: li gp, 4; li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); sllw x14, x1, x2;; li x7, ((0x0000000000000080) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_5: li gp, 5; li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); sllw x14, x1, x2;; li x7, ((0x0000000000004000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_6: li gp, 6; li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); sllw x14, x1, x2;; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_7: li gp, 7; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0) & ((1 << (64 - 1) << 1) - 1)); sllw x14, x1, x2;; li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_8: li gp, 8; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((1) & ((1 << (64 - 1) << 1) - 1)); sllw x14, x1, x2;; li x7, ((0xfffffffffffffffe) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_9: li gp, 9; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); sllw x14, x1, x2;; li x7, ((0xffffffffffffff80) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_10: li gp, 10; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); sllw x14, x1, x2;; li x7, ((0xffffffffffffc000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_11: li gp, 11; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); sllw x14, x1, x2;; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_12: li gp, 12; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0) & ((1 << (64 - 1) << 1) - 1)); sllw x14, x1, x2;; li x7, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_13: li gp, 13; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); li x2, ((1) & ((1 << (64 - 1) << 1) - 1)); sllw x14, x1, x2;; li x7, ((0x0000000042424242) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_14: li gp, 14; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); sllw x14, x1, x2;; li x7, ((0xffffffff90909080) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_15: li gp, 15; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); sllw x14, x1, x2;; li x7, ((0x0000000048484000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_16: li gp, 16; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); sllw x14, x1, x2;; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  # Verify that shifts only use bottom five bits
+
+  test_17: li gp, 17; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffffffe0) & ((1 << (64 - 1) << 1) - 1)); sllw x14, x1, x2;; li x7, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_18: li gp, 18; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffffffe1) & ((1 << (64 - 1) << 1) - 1)); sllw x14, x1, x2;; li x7, ((0x0000000042424242) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_19: li gp, 19; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffffffe7) & ((1 << (64 - 1) << 1) - 1)); sllw x14, x1, x2;; li x7, ((0xffffffff90909080) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_20: li gp, 20; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffffffee) & ((1 << (64 - 1) << 1) - 1)); sllw x14, x1, x2;; li x7, ((0x0000000048484000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_21: li gp, 21; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); sllw x14, x1, x2;; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  # Verify that shifts ignore top 32 (using true 64-bit values)
+
+  test_44: li gp, 44; li x1, ((0xffffffff12345678) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0) & ((1 << (64 - 1) << 1) - 1)); sllw x14, x1, x2;; li x7, ((0x0000000012345678) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_45: li gp, 45; li x1, ((0xffffffff12345678) & ((1 << (64 - 1) << 1) - 1)); li x2, ((4) & ((1 << (64 - 1) << 1) - 1)); sllw x14, x1, x2;; li x7, ((0x0000000023456780) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_46: li gp, 46; li x1, ((0x0000000092345678) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0) & ((1 << (64 - 1) << 1) - 1)); sllw x14, x1, x2;; li x7, ((0xffffffff92345678) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_47: li gp, 47; li x1, ((0x0000000099345678) & ((1 << (64 - 1) << 1) - 1)); li x2, ((4) & ((1 << (64 - 1) << 1) - 1)); sllw x14, x1, x2;; li x7, ((0xffffffff93456780) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  test_22: li gp, 22; li x1, ((0x00000001) & ((1 << (64 - 1) << 1) - 1)); li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); sllw x1, x1, x2;; li x7, ((0x00000080) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_23: li gp, 23; li x1, ((0x00000001) & ((1 << (64 - 1) << 1) - 1)); li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); sllw x2, x1, x2;; li x7, ((0x00004000) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_24: li gp, 24; li x1, ((3) & ((1 << (64 - 1) << 1) - 1)); sllw x1, x1, x1;; li x7, ((24) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_25: li gp, 25; li x4, 0; 1: li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); sllw x14, x1, x2; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000000080) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_26: li gp, 26; li x4, 0; 1: li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); sllw x14, x1, x2; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000004000) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_27: li gp, 27; li x4, 0; 1: li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); sllw x14, x1, x2; nop; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+
+  test_28: li gp, 28; li x4, 0; 1: li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); sllw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000000080) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_29: li gp, 29; li x4, 0; 1: li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); nop; sllw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000004000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_30: li gp, 30; li x4, 0; 1: li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); nop; nop; sllw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_31: li gp, 31; li x4, 0; 1: li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); nop; li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); sllw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000000080) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_32: li gp, 32; li x4, 0; 1: li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); nop; li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); nop; sllw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000004000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_33: li gp, 33; li x4, 0; 1: li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); nop; nop; li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); sllw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_34: li gp, 34; li x4, 0; 1: li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); sllw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000000080) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_35: li gp, 35; li x4, 0; 1: li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); nop; sllw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000004000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_36: li gp, 36; li x4, 0; 1: li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); nop; nop; sllw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_37: li gp, 37; li x4, 0; 1: li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); nop; li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); sllw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000000080) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_38: li gp, 38; li x4, 0; 1: li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); nop; li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); nop; sllw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000004000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_39: li gp, 39; li x4, 0; 1: li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); nop; nop; li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); sllw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_40: li gp, 40; li x1, ((15) & ((1 << (64 - 1) << 1) - 1)); sllw x2, x0, x1;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_41: li gp, 41; li x1, ((32) & ((1 << (64 - 1) << 1) - 1)); sllw x2, x1, x0;; li x7, ((32) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_42: li gp, 42; sllw x1, x0, x0;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_43: li gp, 43; li x1, ((1024) & ((1 << (64 - 1) << 1) - 1)); li x2, ((2048) & ((1 << (64 - 1) << 1) - 1)); sllw x0, x1, x2;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x0, x7, fail;;
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+
diff --git a/verilator-tests/testbench/assembly_programs/slt.s b/verilator-tests/testbench/assembly_programs/slt.s
new file mode 100644
index 0000000..1e74177
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/slt.s
@@ -0,0 +1,159 @@
+# 1 "../../riscv-tests/isa/rv64ui/slt.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/slt.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# slt.S
+#-----------------------------------------------------------------------------
+
+# Test slt instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/slt.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/slt.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  test_2: li gp, 2; li x1, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); slt x14, x1, x2;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_3: li gp, 3; li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); slt x14, x1, x2;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_4: li gp, 4; li x1, ((0x0000000000000003) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0000000000000007) & ((1 << (64 - 1) << 1) - 1)); slt x14, x1, x2;; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_5: li gp, 5; li x1, ((0x0000000000000007) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0000000000000003) & ((1 << (64 - 1) << 1) - 1)); slt x14, x1, x2;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_6: li gp, 6; li x1, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffff8000) & ((1 << (64 - 1) << 1) - 1)); slt x14, x1, x2;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_7: li gp, 7; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); slt x14, x1, x2;; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_8: li gp, 8; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffff8000) & ((1 << (64 - 1) << 1) - 1)); slt x14, x1, x2;; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_9: li gp, 9; li x1, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0000000000007fff) & ((1 << (64 - 1) << 1) - 1)); slt x14, x1, x2;; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_10: li gp, 10; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); slt x14, x1, x2;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_11: li gp, 11; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0000000000007fff) & ((1 << (64 - 1) << 1) - 1)); slt x14, x1, x2;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_12: li gp, 12; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0000000000007fff) & ((1 << (64 - 1) << 1) - 1)); slt x14, x1, x2;; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_13: li gp, 13; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffff8000) & ((1 << (64 - 1) << 1) - 1)); slt x14, x1, x2;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_14: li gp, 14; li x1, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); slt x14, x1, x2;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_15: li gp, 15; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); slt x14, x1, x2;; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_16: li gp, 16; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); slt x14, x1, x2;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  test_17: li gp, 17; li x1, ((14) & ((1 << (64 - 1) << 1) - 1)); li x2, ((13) & ((1 << (64 - 1) << 1) - 1)); slt x1, x1, x2;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_18: li gp, 18; li x1, ((11) & ((1 << (64 - 1) << 1) - 1)); li x2, ((13) & ((1 << (64 - 1) << 1) - 1)); slt x2, x1, x2;; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_19: li gp, 19; li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); slt x1, x1, x1;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_20: li gp, 20; li x4, 0; 1: li x1, ((11) & ((1 << (64 - 1) << 1) - 1)); li x2, ((13) & ((1 << (64 - 1) << 1) - 1)); slt x14, x1, x2; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_21: li gp, 21; li x4, 0; 1: li x1, ((14) & ((1 << (64 - 1) << 1) - 1)); li x2, ((13) & ((1 << (64 - 1) << 1) - 1)); slt x14, x1, x2; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_22: li gp, 22; li x4, 0; 1: li x1, ((12) & ((1 << (64 - 1) << 1) - 1)); li x2, ((13) & ((1 << (64 - 1) << 1) - 1)); slt x14, x1, x2; nop; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+
+  test_23: li gp, 23; li x4, 0; 1: li x1, ((14) & ((1 << (64 - 1) << 1) - 1)); li x2, ((13) & ((1 << (64 - 1) << 1) - 1)); slt x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_24: li gp, 24; li x4, 0; 1: li x1, ((11) & ((1 << (64 - 1) << 1) - 1)); li x2, ((13) & ((1 << (64 - 1) << 1) - 1)); nop; slt x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_25: li gp, 25; li x4, 0; 1: li x1, ((15) & ((1 << (64 - 1) << 1) - 1)); li x2, ((13) & ((1 << (64 - 1) << 1) - 1)); nop; nop; slt x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_26: li gp, 26; li x4, 0; 1: li x1, ((10) & ((1 << (64 - 1) << 1) - 1)); nop; li x2, ((13) & ((1 << (64 - 1) << 1) - 1)); slt x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_27: li gp, 27; li x4, 0; 1: li x1, ((16) & ((1 << (64 - 1) << 1) - 1)); nop; li x2, ((13) & ((1 << (64 - 1) << 1) - 1)); nop; slt x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_28: li gp, 28; li x4, 0; 1: li x1, ((9) & ((1 << (64 - 1) << 1) - 1)); nop; nop; li x2, ((13) & ((1 << (64 - 1) << 1) - 1)); slt x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_29: li gp, 29; li x4, 0; 1: li x2, ((13) & ((1 << (64 - 1) << 1) - 1)); li x1, ((17) & ((1 << (64 - 1) << 1) - 1)); slt x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_30: li gp, 30; li x4, 0; 1: li x2, ((13) & ((1 << (64 - 1) << 1) - 1)); li x1, ((8) & ((1 << (64 - 1) << 1) - 1)); nop; slt x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_31: li gp, 31; li x4, 0; 1: li x2, ((13) & ((1 << (64 - 1) << 1) - 1)); li x1, ((18) & ((1 << (64 - 1) << 1) - 1)); nop; nop; slt x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_32: li gp, 32; li x4, 0; 1: li x2, ((13) & ((1 << (64 - 1) << 1) - 1)); nop; li x1, ((7) & ((1 << (64 - 1) << 1) - 1)); slt x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_33: li gp, 33; li x4, 0; 1: li x2, ((13) & ((1 << (64 - 1) << 1) - 1)); nop; li x1, ((19) & ((1 << (64 - 1) << 1) - 1)); nop; slt x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_34: li gp, 34; li x4, 0; 1: li x2, ((13) & ((1 << (64 - 1) << 1) - 1)); nop; nop; li x1, ((6) & ((1 << (64 - 1) << 1) - 1)); slt x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_35: li gp, 35; li x1, ((-1) & ((1 << (64 - 1) << 1) - 1)); slt x2, x0, x1;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_36: li gp, 36; li x1, ((-1) & ((1 << (64 - 1) << 1) - 1)); slt x2, x1, x0;; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_37: li gp, 37; slt x1, x0, x0;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_38: li gp, 38; li x1, ((16) & ((1 << (64 - 1) << 1) - 1)); li x2, ((30) & ((1 << (64 - 1) << 1) - 1)); slt x0, x1, x2;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x0, x7, fail;;
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+
diff --git a/verilator-tests/testbench/assembly_programs/slti.s b/verilator-tests/testbench/assembly_programs/slti.s
new file mode 100644
index 0000000..f3a0bd4
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/slti.s
@@ -0,0 +1,145 @@
+# 1 "../../riscv-tests/isa/rv64ui/slti.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/slti.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# slti.S
+#-----------------------------------------------------------------------------
+
+# Test slti instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/slti.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/slti.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  test_2: li gp, 2; li x1, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); slti x14, x1, ((0x000) | (-(((0x000) >> 11) & 1) << 11));; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_3: li gp, 3; li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); slti x14, x1, ((0x001) | (-(((0x001) >> 11) & 1) << 11));; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_4: li gp, 4; li x1, ((0x0000000000000003) & ((1 << (64 - 1) << 1) - 1)); slti x14, x1, ((0x007) | (-(((0x007) >> 11) & 1) << 11));; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_5: li gp, 5; li x1, ((0x0000000000000007) & ((1 << (64 - 1) << 1) - 1)); slti x14, x1, ((0x003) | (-(((0x003) >> 11) & 1) << 11));; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_6: li gp, 6; li x1, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); slti x14, x1, ((0x800) | (-(((0x800) >> 11) & 1) << 11));; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_7: li gp, 7; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); slti x14, x1, ((0x000) | (-(((0x000) >> 11) & 1) << 11));; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_8: li gp, 8; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); slti x14, x1, ((0x800) | (-(((0x800) >> 11) & 1) << 11));; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_9: li gp, 9; li x1, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); slti x14, x1, ((0x7ff) | (-(((0x7ff) >> 11) & 1) << 11));; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_10: li gp, 10; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); slti x14, x1, ((0x000) | (-(((0x000) >> 11) & 1) << 11));; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_11: li gp, 11; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); slti x14, x1, ((0x7ff) | (-(((0x7ff) >> 11) & 1) << 11));; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_12: li gp, 12; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); slti x14, x1, ((0x7ff) | (-(((0x7ff) >> 11) & 1) << 11));; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_13: li gp, 13; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); slti x14, x1, ((0x800) | (-(((0x800) >> 11) & 1) << 11));; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_14: li gp, 14; li x1, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); slti x14, x1, ((0xfff) | (-(((0xfff) >> 11) & 1) << 11));; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_15: li gp, 15; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); slti x14, x1, ((0x001) | (-(((0x001) >> 11) & 1) << 11));; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_16: li gp, 16; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); slti x14, x1, ((0xfff) | (-(((0xfff) >> 11) & 1) << 11));; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  test_17: li gp, 17; li x1, ((11) & ((1 << (64 - 1) << 1) - 1)); slti x1, x1, ((13) | (-(((13) >> 11) & 1) << 11));; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_18: li gp, 18; li x4, 0; 1: li x1, ((15) & ((1 << (64 - 1) << 1) - 1)); slti x14, x1, ((10) | (-(((10) >> 11) & 1) << 11)); addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_19: li gp, 19; li x4, 0; 1: li x1, ((10) & ((1 << (64 - 1) << 1) - 1)); slti x14, x1, ((16) | (-(((16) >> 11) & 1) << 11)); nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_20: li gp, 20; li x4, 0; 1: li x1, ((16) & ((1 << (64 - 1) << 1) - 1)); slti x14, x1, ((9) | (-(((9) >> 11) & 1) << 11)); nop; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+
+  test_21: li gp, 21; li x4, 0; 1: li x1, ((11) & ((1 << (64 - 1) << 1) - 1)); slti x14, x1, ((15) | (-(((15) >> 11) & 1) << 11)); addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_22: li gp, 22; li x4, 0; 1: li x1, ((17) & ((1 << (64 - 1) << 1) - 1)); nop; slti x14, x1, ((8) | (-(((8) >> 11) & 1) << 11)); addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_23: li gp, 23; li x4, 0; 1: li x1, ((12) & ((1 << (64 - 1) << 1) - 1)); nop; nop; slti x14, x1, ((14) | (-(((14) >> 11) & 1) << 11)); addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_24: li gp, 24; slti x1, x0, ((0xfff) | (-(((0xfff) >> 11) & 1) << 11));; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_25: li gp, 25; li x1, ((0x00ff00ff) & ((1 << (64 - 1) << 1) - 1)); slti x0, x1, ((0xfff) | (-(((0xfff) >> 11) & 1) << 11));; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x0, x7, fail;;
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+
diff --git a/verilator-tests/testbench/assembly_programs/sltiu.s b/verilator-tests/testbench/assembly_programs/sltiu.s
new file mode 100644
index 0000000..d05caa2
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/sltiu.s
@@ -0,0 +1,145 @@
+# 1 "../../riscv-tests/isa/rv64ui/sltiu.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/sltiu.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sltiu.S
+#-----------------------------------------------------------------------------
+
+# Test sltiu instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/sltiu.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/sltiu.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  test_2: li gp, 2; li x1, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); sltiu x14, x1, ((0x000) | (-(((0x000) >> 11) & 1) << 11));; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_3: li gp, 3; li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); sltiu x14, x1, ((0x001) | (-(((0x001) >> 11) & 1) << 11));; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_4: li gp, 4; li x1, ((0x0000000000000003) & ((1 << (64 - 1) << 1) - 1)); sltiu x14, x1, ((0x007) | (-(((0x007) >> 11) & 1) << 11));; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_5: li gp, 5; li x1, ((0x0000000000000007) & ((1 << (64 - 1) << 1) - 1)); sltiu x14, x1, ((0x003) | (-(((0x003) >> 11) & 1) << 11));; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_6: li gp, 6; li x1, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); sltiu x14, x1, ((0x800) | (-(((0x800) >> 11) & 1) << 11));; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_7: li gp, 7; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); sltiu x14, x1, ((0x000) | (-(((0x000) >> 11) & 1) << 11));; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_8: li gp, 8; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); sltiu x14, x1, ((0x800) | (-(((0x800) >> 11) & 1) << 11));; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_9: li gp, 9; li x1, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); sltiu x14, x1, ((0x7ff) | (-(((0x7ff) >> 11) & 1) << 11));; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_10: li gp, 10; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); sltiu x14, x1, ((0x000) | (-(((0x000) >> 11) & 1) << 11));; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_11: li gp, 11; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); sltiu x14, x1, ((0x7ff) | (-(((0x7ff) >> 11) & 1) << 11));; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_12: li gp, 12; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); sltiu x14, x1, ((0x7ff) | (-(((0x7ff) >> 11) & 1) << 11));; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_13: li gp, 13; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); sltiu x14, x1, ((0x800) | (-(((0x800) >> 11) & 1) << 11));; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_14: li gp, 14; li x1, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); sltiu x14, x1, ((0xfff) | (-(((0xfff) >> 11) & 1) << 11));; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_15: li gp, 15; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); sltiu x14, x1, ((0x001) | (-(((0x001) >> 11) & 1) << 11));; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_16: li gp, 16; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); sltiu x14, x1, ((0xfff) | (-(((0xfff) >> 11) & 1) << 11));; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  test_17: li gp, 17; li x1, ((11) & ((1 << (64 - 1) << 1) - 1)); sltiu x1, x1, ((13) | (-(((13) >> 11) & 1) << 11));; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_18: li gp, 18; li x4, 0; 1: li x1, ((15) & ((1 << (64 - 1) << 1) - 1)); sltiu x14, x1, ((10) | (-(((10) >> 11) & 1) << 11)); addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_19: li gp, 19; li x4, 0; 1: li x1, ((10) & ((1 << (64 - 1) << 1) - 1)); sltiu x14, x1, ((16) | (-(((16) >> 11) & 1) << 11)); nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_20: li gp, 20; li x4, 0; 1: li x1, ((16) & ((1 << (64 - 1) << 1) - 1)); sltiu x14, x1, ((9) | (-(((9) >> 11) & 1) << 11)); nop; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+
+  test_21: li gp, 21; li x4, 0; 1: li x1, ((11) & ((1 << (64 - 1) << 1) - 1)); sltiu x14, x1, ((15) | (-(((15) >> 11) & 1) << 11)); addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_22: li gp, 22; li x4, 0; 1: li x1, ((17) & ((1 << (64 - 1) << 1) - 1)); nop; sltiu x14, x1, ((8) | (-(((8) >> 11) & 1) << 11)); addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_23: li gp, 23; li x4, 0; 1: li x1, ((12) & ((1 << (64 - 1) << 1) - 1)); nop; nop; sltiu x14, x1, ((14) | (-(((14) >> 11) & 1) << 11)); addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_24: li gp, 24; sltiu x1, x0, ((0xfff) | (-(((0xfff) >> 11) & 1) << 11));; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_25: li gp, 25; li x1, ((0x00ff00ff) & ((1 << (64 - 1) << 1) - 1)); sltiu x0, x1, ((0xfff) | (-(((0xfff) >> 11) & 1) << 11));; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x0, x7, fail;;
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+
diff --git a/verilator-tests/testbench/assembly_programs/sltu.s b/verilator-tests/testbench/assembly_programs/sltu.s
new file mode 100644
index 0000000..7ad9849
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/sltu.s
@@ -0,0 +1,159 @@
+# 1 "../../riscv-tests/isa/rv64ui/sltu.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/sltu.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sltu.S
+#-----------------------------------------------------------------------------
+
+# Test sltu instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/sltu.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/sltu.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  test_2: li gp, 2; li x1, ((0x00000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x00000000) & ((1 << (64 - 1) << 1) - 1)); sltu x14, x1, x2;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_3: li gp, 3; li x1, ((0x00000001) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x00000001) & ((1 << (64 - 1) << 1) - 1)); sltu x14, x1, x2;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_4: li gp, 4; li x1, ((0x00000003) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x00000007) & ((1 << (64 - 1) << 1) - 1)); sltu x14, x1, x2;; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_5: li gp, 5; li x1, ((0x00000007) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x00000003) & ((1 << (64 - 1) << 1) - 1)); sltu x14, x1, x2;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_6: li gp, 6; li x1, ((0x00000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffff8000) & ((1 << (64 - 1) << 1) - 1)); sltu x14, x1, x2;; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_7: li gp, 7; li x1, ((0x80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x00000000) & ((1 << (64 - 1) << 1) - 1)); sltu x14, x1, x2;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_8: li gp, 8; li x1, ((0x80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffff8000) & ((1 << (64 - 1) << 1) - 1)); sltu x14, x1, x2;; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_9: li gp, 9; li x1, ((0x00000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x00007fff) & ((1 << (64 - 1) << 1) - 1)); sltu x14, x1, x2;; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_10: li gp, 10; li x1, ((0x7fffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x00000000) & ((1 << (64 - 1) << 1) - 1)); sltu x14, x1, x2;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_11: li gp, 11; li x1, ((0x7fffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x00007fff) & ((1 << (64 - 1) << 1) - 1)); sltu x14, x1, x2;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_12: li gp, 12; li x1, ((0x80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x00007fff) & ((1 << (64 - 1) << 1) - 1)); sltu x14, x1, x2;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_13: li gp, 13; li x1, ((0x7fffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffff8000) & ((1 << (64 - 1) << 1) - 1)); sltu x14, x1, x2;; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_14: li gp, 14; li x1, ((0x00000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffff) & ((1 << (64 - 1) << 1) - 1)); sltu x14, x1, x2;; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_15: li gp, 15; li x1, ((0xffffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x00000001) & ((1 << (64 - 1) << 1) - 1)); sltu x14, x1, x2;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_16: li gp, 16; li x1, ((0xffffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffff) & ((1 << (64 - 1) << 1) - 1)); sltu x14, x1, x2;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  test_17: li gp, 17; li x1, ((14) & ((1 << (64 - 1) << 1) - 1)); li x2, ((13) & ((1 << (64 - 1) << 1) - 1)); sltu x1, x1, x2;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_18: li gp, 18; li x1, ((11) & ((1 << (64 - 1) << 1) - 1)); li x2, ((13) & ((1 << (64 - 1) << 1) - 1)); sltu x2, x1, x2;; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_19: li gp, 19; li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); sltu x1, x1, x1;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_20: li gp, 20; li x4, 0; 1: li x1, ((11) & ((1 << (64 - 1) << 1) - 1)); li x2, ((13) & ((1 << (64 - 1) << 1) - 1)); sltu x14, x1, x2; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_21: li gp, 21; li x4, 0; 1: li x1, ((14) & ((1 << (64 - 1) << 1) - 1)); li x2, ((13) & ((1 << (64 - 1) << 1) - 1)); sltu x14, x1, x2; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_22: li gp, 22; li x4, 0; 1: li x1, ((12) & ((1 << (64 - 1) << 1) - 1)); li x2, ((13) & ((1 << (64 - 1) << 1) - 1)); sltu x14, x1, x2; nop; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+
+  test_23: li gp, 23; li x4, 0; 1: li x1, ((14) & ((1 << (64 - 1) << 1) - 1)); li x2, ((13) & ((1 << (64 - 1) << 1) - 1)); sltu x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_24: li gp, 24; li x4, 0; 1: li x1, ((11) & ((1 << (64 - 1) << 1) - 1)); li x2, ((13) & ((1 << (64 - 1) << 1) - 1)); nop; sltu x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_25: li gp, 25; li x4, 0; 1: li x1, ((15) & ((1 << (64 - 1) << 1) - 1)); li x2, ((13) & ((1 << (64 - 1) << 1) - 1)); nop; nop; sltu x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_26: li gp, 26; li x4, 0; 1: li x1, ((10) & ((1 << (64 - 1) << 1) - 1)); nop; li x2, ((13) & ((1 << (64 - 1) << 1) - 1)); sltu x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_27: li gp, 27; li x4, 0; 1: li x1, ((16) & ((1 << (64 - 1) << 1) - 1)); nop; li x2, ((13) & ((1 << (64 - 1) << 1) - 1)); nop; sltu x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_28: li gp, 28; li x4, 0; 1: li x1, ((9) & ((1 << (64 - 1) << 1) - 1)); nop; nop; li x2, ((13) & ((1 << (64 - 1) << 1) - 1)); sltu x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_29: li gp, 29; li x4, 0; 1: li x2, ((13) & ((1 << (64 - 1) << 1) - 1)); li x1, ((17) & ((1 << (64 - 1) << 1) - 1)); sltu x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_30: li gp, 30; li x4, 0; 1: li x2, ((13) & ((1 << (64 - 1) << 1) - 1)); li x1, ((8) & ((1 << (64 - 1) << 1) - 1)); nop; sltu x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_31: li gp, 31; li x4, 0; 1: li x2, ((13) & ((1 << (64 - 1) << 1) - 1)); li x1, ((18) & ((1 << (64 - 1) << 1) - 1)); nop; nop; sltu x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_32: li gp, 32; li x4, 0; 1: li x2, ((13) & ((1 << (64 - 1) << 1) - 1)); nop; li x1, ((7) & ((1 << (64 - 1) << 1) - 1)); sltu x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_33: li gp, 33; li x4, 0; 1: li x2, ((13) & ((1 << (64 - 1) << 1) - 1)); nop; li x1, ((19) & ((1 << (64 - 1) << 1) - 1)); nop; sltu x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_34: li gp, 34; li x4, 0; 1: li x2, ((13) & ((1 << (64 - 1) << 1) - 1)); nop; nop; li x1, ((6) & ((1 << (64 - 1) << 1) - 1)); sltu x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_35: li gp, 35; li x1, ((-1) & ((1 << (64 - 1) << 1) - 1)); sltu x2, x0, x1;; li x7, ((1) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_36: li gp, 36; li x1, ((-1) & ((1 << (64 - 1) << 1) - 1)); sltu x2, x1, x0;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_37: li gp, 37; sltu x1, x0, x0;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_38: li gp, 38; li x1, ((16) & ((1 << (64 - 1) << 1) - 1)); li x2, ((30) & ((1 << (64 - 1) << 1) - 1)); sltu x0, x1, x2;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x0, x7, fail;;
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+
diff --git a/verilator-tests/testbench/assembly_programs/sra.s b/verilator-tests/testbench/assembly_programs/sra.s
new file mode 100644
index 0000000..aa6fce9
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/sra.s
@@ -0,0 +1,165 @@
+# 1 "../../riscv-tests/isa/rv64ui/sra.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/sra.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sra.S
+#-----------------------------------------------------------------------------
+
+# Test sra instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/sra.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/sra.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  test_2: li gp, 2; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0) & ((1 << (64 - 1) << 1) - 1)); sra x14, x1, x2;; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_3: li gp, 3; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((1) & ((1 << (64 - 1) << 1) - 1)); sra x14, x1, x2;; li x7, ((0xffffffffc0000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_4: li gp, 4; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); sra x14, x1, x2;; li x7, ((0xffffffffff000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_5: li gp, 5; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); sra x14, x1, x2;; li x7, ((0xfffffffffffe0000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_6: li gp, 6; li x1, ((0xffffffff80000001) & ((1 << (64 - 1) << 1) - 1)); li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); sra x14, x1, x2;; li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_7: li gp, 7; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0) & ((1 << (64 - 1) << 1) - 1)); sra x14, x1, x2;; li x7, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_8: li gp, 8; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((1) & ((1 << (64 - 1) << 1) - 1)); sra x14, x1, x2;; li x7, ((0x000000003fffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_9: li gp, 9; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); sra x14, x1, x2;; li x7, ((0x0000000000ffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_10: li gp, 10; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); sra x14, x1, x2;; li x7, ((0x000000000001ffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_11: li gp, 11; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); sra x14, x1, x2;; li x7, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_12: li gp, 12; li x1, ((0xffffffff81818181) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0) & ((1 << (64 - 1) << 1) - 1)); sra x14, x1, x2;; li x7, ((0xffffffff81818181) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_13: li gp, 13; li x1, ((0xffffffff81818181) & ((1 << (64 - 1) << 1) - 1)); li x2, ((1) & ((1 << (64 - 1) << 1) - 1)); sra x14, x1, x2;; li x7, ((0xffffffffc0c0c0c0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_14: li gp, 14; li x1, ((0xffffffff81818181) & ((1 << (64 - 1) << 1) - 1)); li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); sra x14, x1, x2;; li x7, ((0xffffffffff030303) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_15: li gp, 15; li x1, ((0xffffffff81818181) & ((1 << (64 - 1) << 1) - 1)); li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); sra x14, x1, x2;; li x7, ((0xfffffffffffe0606) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_16: li gp, 16; li x1, ((0xffffffff81818181) & ((1 << (64 - 1) << 1) - 1)); li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); sra x14, x1, x2;; li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  # Verify that shifts only use bottom six(rv64) or five(rv32) bits
+
+  test_17: li gp, 17; li x1, ((0xffffffff81818181) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffffffc0) & ((1 << (64 - 1) << 1) - 1)); sra x14, x1, x2;; li x7, ((0xffffffff81818181) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_18: li gp, 18; li x1, ((0xffffffff81818181) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffffffc1) & ((1 << (64 - 1) << 1) - 1)); sra x14, x1, x2;; li x7, ((0xffffffffc0c0c0c0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_19: li gp, 19; li x1, ((0xffffffff81818181) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffffffc7) & ((1 << (64 - 1) << 1) - 1)); sra x14, x1, x2;; li x7, ((0xffffffffff030303) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_20: li gp, 20; li x1, ((0xffffffff81818181) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffffffce) & ((1 << (64 - 1) << 1) - 1)); sra x14, x1, x2;; li x7, ((0xfffffffffffe0606) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_21: li gp, 21; li x1, ((0xffffffff81818181) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); sra x14, x1, x2;; li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  test_22: li gp, 22; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); sra x1, x1, x2;; li x7, ((0xffffffffff000000) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_23: li gp, 23; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); sra x2, x1, x2;; li x7, ((0xfffffffffffe0000) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_24: li gp, 24; li x1, ((7) & ((1 << (64 - 1) << 1) - 1)); sra x1, x1, x1;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_25: li gp, 25; li x4, 0; 1: li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); sra x14, x1, x2; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xffffffffff000000) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_26: li gp, 26; li x4, 0; 1: li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); sra x14, x1, x2; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xfffffffffffe0000) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_27: li gp, 27; li x4, 0; 1: li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); sra x14, x1, x2; nop; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+
+  test_28: li gp, 28; li x4, 0; 1: li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); sra x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xffffffffff000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_29: li gp, 29; li x4, 0; 1: li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); nop; sra x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xfffffffffffe0000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_30: li gp, 30; li x4, 0; 1: li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); nop; nop; sra x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_31: li gp, 31; li x4, 0; 1: li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); nop; li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); sra x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xffffffffff000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_32: li gp, 32; li x4, 0; 1: li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); nop; li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); nop; sra x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xfffffffffffe0000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_33: li gp, 33; li x4, 0; 1: li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); nop; nop; li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); sra x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_34: li gp, 34; li x4, 0; 1: li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); sra x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xffffffffff000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_35: li gp, 35; li x4, 0; 1: li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); nop; sra x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xfffffffffffe0000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_36: li gp, 36; li x4, 0; 1: li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); nop; nop; sra x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_37: li gp, 37; li x4, 0; 1: li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); nop; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); sra x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xffffffffff000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_38: li gp, 38; li x4, 0; 1: li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); nop; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); nop; sra x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xfffffffffffe0000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_39: li gp, 39; li x4, 0; 1: li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); nop; nop; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); sra x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_40: li gp, 40; li x1, ((15) & ((1 << (64 - 1) << 1) - 1)); sra x2, x0, x1;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_41: li gp, 41; li x1, ((32) & ((1 << (64 - 1) << 1) - 1)); sra x2, x1, x0;; li x7, ((32) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_42: li gp, 42; sra x1, x0, x0;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_43: li gp, 43; li x1, ((1024) & ((1 << (64 - 1) << 1) - 1)); li x2, ((2048) & ((1 << (64 - 1) << 1) - 1)); sra x0, x1, x2;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x0, x7, fail;;
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+
diff --git a/verilator-tests/testbench/assembly_programs/srai.s b/verilator-tests/testbench/assembly_programs/srai.s
new file mode 100644
index 0000000..f1b8f84
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/srai.s
@@ -0,0 +1,143 @@
+# 1 "../../riscv-tests/isa/rv64ui/srai.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/srai.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# srai.S
+#-----------------------------------------------------------------------------
+
+# Test srai instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/srai.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/srai.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  test_2: li gp, 2; li x1, ((0xffffff8000000000) & ((1 << (64 - 1) << 1) - 1)); srai x14, x1, ((0) | (-(((0) >> 11) & 1) << 11));; li x7, ((0xffffff8000000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_3: li gp, 3; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); srai x14, x1, ((1) | (-(((1) >> 11) & 1) << 11));; li x7, ((0xffffffffc0000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_4: li gp, 4; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); srai x14, x1, ((7) | (-(((7) >> 11) & 1) << 11));; li x7, ((0xffffffffff000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_5: li gp, 5; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); srai x14, x1, ((14) | (-(((14) >> 11) & 1) << 11));; li x7, ((0xfffffffffffe0000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_6: li gp, 6; li x1, ((0xffffffff80000001) & ((1 << (64 - 1) << 1) - 1)); srai x14, x1, ((31) | (-(((31) >> 11) & 1) << 11));; li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_7: li gp, 7; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); srai x14, x1, ((0) | (-(((0) >> 11) & 1) << 11));; li x7, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_8: li gp, 8; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); srai x14, x1, ((1) | (-(((1) >> 11) & 1) << 11));; li x7, ((0x000000003fffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_9: li gp, 9; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); srai x14, x1, ((7) | (-(((7) >> 11) & 1) << 11));; li x7, ((0x0000000000ffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_10: li gp, 10; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); srai x14, x1, ((14) | (-(((14) >> 11) & 1) << 11));; li x7, ((0x000000000001ffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_11: li gp, 11; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); srai x14, x1, ((31) | (-(((31) >> 11) & 1) << 11));; li x7, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_12: li gp, 12; li x1, ((0xffffffff81818181) & ((1 << (64 - 1) << 1) - 1)); srai x14, x1, ((0) | (-(((0) >> 11) & 1) << 11));; li x7, ((0xffffffff81818181) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_13: li gp, 13; li x1, ((0xffffffff81818181) & ((1 << (64 - 1) << 1) - 1)); srai x14, x1, ((1) | (-(((1) >> 11) & 1) << 11));; li x7, ((0xffffffffc0c0c0c0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_14: li gp, 14; li x1, ((0xffffffff81818181) & ((1 << (64 - 1) << 1) - 1)); srai x14, x1, ((7) | (-(((7) >> 11) & 1) << 11));; li x7, ((0xffffffffff030303) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_15: li gp, 15; li x1, ((0xffffffff81818181) & ((1 << (64 - 1) << 1) - 1)); srai x14, x1, ((14) | (-(((14) >> 11) & 1) << 11));; li x7, ((0xfffffffffffe0606) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_16: li gp, 16; li x1, ((0xffffffff81818181) & ((1 << (64 - 1) << 1) - 1)); srai x14, x1, ((31) | (-(((31) >> 11) & 1) << 11));; li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  test_17: li gp, 17; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); srai x1, x1, ((7) | (-(((7) >> 11) & 1) << 11));; li x7, ((0xffffffffff000000) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_18: li gp, 18; li x4, 0; 1: li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); srai x14, x1, ((7) | (-(((7) >> 11) & 1) << 11)); addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xffffffffff000000) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_19: li gp, 19; li x4, 0; 1: li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); srai x14, x1, ((14) | (-(((14) >> 11) & 1) << 11)); nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xfffffffffffe0000) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_20: li gp, 20; li x4, 0; 1: li x1, ((0xffffffff80000001) & ((1 << (64 - 1) << 1) - 1)); srai x14, x1, ((31) | (-(((31) >> 11) & 1) << 11)); nop; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+
+  test_21: li gp, 21; li x4, 0; 1: li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); srai x14, x1, ((7) | (-(((7) >> 11) & 1) << 11)); addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xffffffffff000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_22: li gp, 22; li x4, 0; 1: li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); nop; srai x14, x1, ((14) | (-(((14) >> 11) & 1) << 11)); addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xfffffffffffe0000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_23: li gp, 23; li x4, 0; 1: li x1, ((0xffffffff80000001) & ((1 << (64 - 1) << 1) - 1)); nop; nop; srai x14, x1, ((31) | (-(((31) >> 11) & 1) << 11)); addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_24: li gp, 24; srai x1, x0, ((4) | (-(((4) >> 11) & 1) << 11));; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_25: li gp, 25; li x1, ((33) & ((1 << (64 - 1) << 1) - 1)); srai x0, x1, ((10) | (-(((10) >> 11) & 1) << 11));; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x0, x7, fail;;
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+
diff --git a/verilator-tests/testbench/assembly_programs/sraiw.s b/verilator-tests/testbench/assembly_programs/sraiw.s
new file mode 100644
index 0000000..4a312f7
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/sraiw.s
@@ -0,0 +1,153 @@
+# 1 "../../riscv-tests/isa/rv64ui/sraiw.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/sraiw.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sraiw.S
+#-----------------------------------------------------------------------------
+
+# Test sraiw instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/sraiw.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/sraiw.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  test_2: li gp, 2; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); sraiw x14, x1, ((0) | (-(((0) >> 11) & 1) << 11));; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_3: li gp, 3; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); sraiw x14, x1, ((1) | (-(((1) >> 11) & 1) << 11));; li x7, ((0xffffffffc0000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_4: li gp, 4; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); sraiw x14, x1, ((7) | (-(((7) >> 11) & 1) << 11));; li x7, ((0xffffffffff000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_5: li gp, 5; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); sraiw x14, x1, ((14) | (-(((14) >> 11) & 1) << 11));; li x7, ((0xfffffffffffe0000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_6: li gp, 6; li x1, ((0xffffffff80000001) & ((1 << (64 - 1) << 1) - 1)); sraiw x14, x1, ((31) | (-(((31) >> 11) & 1) << 11));; li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_7: li gp, 7; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); sraiw x14, x1, ((0) | (-(((0) >> 11) & 1) << 11));; li x7, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_8: li gp, 8; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); sraiw x14, x1, ((1) | (-(((1) >> 11) & 1) << 11));; li x7, ((0x000000003fffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_9: li gp, 9; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); sraiw x14, x1, ((7) | (-(((7) >> 11) & 1) << 11));; li x7, ((0x0000000000ffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_10: li gp, 10; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); sraiw x14, x1, ((14) | (-(((14) >> 11) & 1) << 11));; li x7, ((0x000000000001ffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_11: li gp, 11; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); sraiw x14, x1, ((31) | (-(((31) >> 11) & 1) << 11));; li x7, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_12: li gp, 12; li x1, ((0xffffffff81818181) & ((1 << (64 - 1) << 1) - 1)); sraiw x14, x1, ((0) | (-(((0) >> 11) & 1) << 11));; li x7, ((0xffffffff81818181) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_13: li gp, 13; li x1, ((0xffffffff81818181) & ((1 << (64 - 1) << 1) - 1)); sraiw x14, x1, ((1) | (-(((1) >> 11) & 1) << 11));; li x7, ((0xffffffffc0c0c0c0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_14: li gp, 14; li x1, ((0xffffffff81818181) & ((1 << (64 - 1) << 1) - 1)); sraiw x14, x1, ((7) | (-(((7) >> 11) & 1) << 11));; li x7, ((0xffffffffff030303) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_15: li gp, 15; li x1, ((0xffffffff81818181) & ((1 << (64 - 1) << 1) - 1)); sraiw x14, x1, ((14) | (-(((14) >> 11) & 1) << 11));; li x7, ((0xfffffffffffe0606) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_16: li gp, 16; li x1, ((0xffffffff81818181) & ((1 << (64 - 1) << 1) - 1)); sraiw x14, x1, ((31) | (-(((31) >> 11) & 1) << 11));; li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  # Verify that shifts ignore top 32 (using true 64-bit values)
+
+  test_44: li gp, 44; li x1, ((0xffffffff12345678) & ((1 << (64 - 1) << 1) - 1)); sraiw x14, x1, ((0) | (-(((0) >> 11) & 1) << 11));; li x7, ((0x0000000012345678) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_45: li gp, 45; li x1, ((0xffffffff12345678) & ((1 << (64 - 1) << 1) - 1)); sraiw x14, x1, ((4) | (-(((4) >> 11) & 1) << 11));; li x7, ((0x0000000001234567) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_46: li gp, 46; li x1, ((0x0000000092345678) & ((1 << (64 - 1) << 1) - 1)); sraiw x14, x1, ((0) | (-(((0) >> 11) & 1) << 11));; li x7, ((0xffffffff92345678) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_47: li gp, 47; li x1, ((0x0000000092345678) & ((1 << (64 - 1) << 1) - 1)); sraiw x14, x1, ((4) | (-(((4) >> 11) & 1) << 11));; li x7, ((0xfffffffff9234567) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  test_17: li gp, 17; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); sraiw x1, x1, ((7) | (-(((7) >> 11) & 1) << 11));; li x7, ((0xffffffffff000000) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_18: li gp, 18; li x4, 0; 1: li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); sraiw x14, x1, ((7) | (-(((7) >> 11) & 1) << 11)); addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xffffffffff000000) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_19: li gp, 19; li x4, 0; 1: li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); sraiw x14, x1, ((14) | (-(((14) >> 11) & 1) << 11)); nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xfffffffffffe0000) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_20: li gp, 20; li x4, 0; 1: li x1, ((0xffffffff80000001) & ((1 << (64 - 1) << 1) - 1)); sraiw x14, x1, ((31) | (-(((31) >> 11) & 1) << 11)); nop; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+
+  test_21: li gp, 21; li x4, 0; 1: li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); sraiw x14, x1, ((7) | (-(((7) >> 11) & 1) << 11)); addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xffffffffff000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_22: li gp, 22; li x4, 0; 1: li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); nop; sraiw x14, x1, ((14) | (-(((14) >> 11) & 1) << 11)); addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xfffffffffffe0000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_23: li gp, 23; li x4, 0; 1: li x1, ((0xffffffff80000001) & ((1 << (64 - 1) << 1) - 1)); nop; nop; sraiw x14, x1, ((31) | (-(((31) >> 11) & 1) << 11)); addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_24: li gp, 24; sraiw x1, x0, ((31) | (-(((31) >> 11) & 1) << 11));; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_25: li gp, 25; li x1, ((31) & ((1 << (64 - 1) << 1) - 1)); sraiw x0, x1, ((28) | (-(((28) >> 11) & 1) << 11));; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x0, x7, fail;;
+
+  test_26: li gp, 26; li x1, ((0x00e0000000000000) & ((1 << (64 - 1) << 1) - 1)); sraiw x14, x1, ((28) | (-(((28) >> 11) & 1) << 11));; li x7, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;
+  test_27: li gp, 27; li x1, ((0x00000000f0000000) & ((1 << (64 - 1) << 1) - 1)); sraiw x14, x1, ((4) | (-(((4) >> 11) & 1) << 11));; li x7, ((0xffffffffff000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+
diff --git a/verilator-tests/testbench/assembly_programs/sraw.s b/verilator-tests/testbench/assembly_programs/sraw.s
new file mode 100644
index 0000000..85c89d2
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/sraw.s
@@ -0,0 +1,172 @@
+# 1 "../../riscv-tests/isa/rv64ui/sraw.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/sraw.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sraw.S
+#-----------------------------------------------------------------------------
+
+# Test sraw instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/sraw.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/sraw.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  test_2: li gp, 2; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0) & ((1 << (64 - 1) << 1) - 1)); sraw x14, x1, x2;; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_3: li gp, 3; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((1) & ((1 << (64 - 1) << 1) - 1)); sraw x14, x1, x2;; li x7, ((0xffffffffc0000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_4: li gp, 4; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); sraw x14, x1, x2;; li x7, ((0xffffffffff000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_5: li gp, 5; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); sraw x14, x1, x2;; li x7, ((0xfffffffffffe0000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_6: li gp, 6; li x1, ((0xffffffff80000001) & ((1 << (64 - 1) << 1) - 1)); li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); sraw x14, x1, x2;; li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_7: li gp, 7; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0) & ((1 << (64 - 1) << 1) - 1)); sraw x14, x1, x2;; li x7, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_8: li gp, 8; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((1) & ((1 << (64 - 1) << 1) - 1)); sraw x14, x1, x2;; li x7, ((0x000000003fffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_9: li gp, 9; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); sraw x14, x1, x2;; li x7, ((0x0000000000ffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_10: li gp, 10; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); sraw x14, x1, x2;; li x7, ((0x000000000001ffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_11: li gp, 11; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); sraw x14, x1, x2;; li x7, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_12: li gp, 12; li x1, ((0xffffffff81818181) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0) & ((1 << (64 - 1) << 1) - 1)); sraw x14, x1, x2;; li x7, ((0xffffffff81818181) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_13: li gp, 13; li x1, ((0xffffffff81818181) & ((1 << (64 - 1) << 1) - 1)); li x2, ((1) & ((1 << (64 - 1) << 1) - 1)); sraw x14, x1, x2;; li x7, ((0xffffffffc0c0c0c0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_14: li gp, 14; li x1, ((0xffffffff81818181) & ((1 << (64 - 1) << 1) - 1)); li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); sraw x14, x1, x2;; li x7, ((0xffffffffff030303) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_15: li gp, 15; li x1, ((0xffffffff81818181) & ((1 << (64 - 1) << 1) - 1)); li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); sraw x14, x1, x2;; li x7, ((0xfffffffffffe0606) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_16: li gp, 16; li x1, ((0xffffffff81818181) & ((1 << (64 - 1) << 1) - 1)); li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); sraw x14, x1, x2;; li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  # Verify that shifts only use bottom five bits
+
+  test_17: li gp, 17; li x1, ((0xffffffff81818181) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffffffe0) & ((1 << (64 - 1) << 1) - 1)); sraw x14, x1, x2;; li x7, ((0xffffffff81818181) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_18: li gp, 18; li x1, ((0xffffffff81818181) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffffffe1) & ((1 << (64 - 1) << 1) - 1)); sraw x14, x1, x2;; li x7, ((0xffffffffc0c0c0c0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_19: li gp, 19; li x1, ((0xffffffff81818181) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffffffe7) & ((1 << (64 - 1) << 1) - 1)); sraw x14, x1, x2;; li x7, ((0xffffffffff030303) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_20: li gp, 20; li x1, ((0xffffffff81818181) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffffffee) & ((1 << (64 - 1) << 1) - 1)); sraw x14, x1, x2;; li x7, ((0xfffffffffffe0606) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_21: li gp, 21; li x1, ((0xffffffff81818181) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); sraw x14, x1, x2;; li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  # Verify that shifts ignore top 32 (using true 64-bit values)
+
+  test_44: li gp, 44; li x1, ((0xffffffff12345678) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0) & ((1 << (64 - 1) << 1) - 1)); sraw x14, x1, x2;; li x7, ((0x0000000012345678) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_45: li gp, 45; li x1, ((0xffffffff12345678) & ((1 << (64 - 1) << 1) - 1)); li x2, ((4) & ((1 << (64 - 1) << 1) - 1)); sraw x14, x1, x2;; li x7, ((0x0000000001234567) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_46: li gp, 46; li x1, ((0x0000000092345678) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0) & ((1 << (64 - 1) << 1) - 1)); sraw x14, x1, x2;; li x7, ((0xffffffff92345678) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_47: li gp, 47; li x1, ((0x0000000092345678) & ((1 << (64 - 1) << 1) - 1)); li x2, ((4) & ((1 << (64 - 1) << 1) - 1)); sraw x14, x1, x2;; li x7, ((0xfffffffff9234567) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  test_22: li gp, 22; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); sraw x1, x1, x2;; li x7, ((0xffffffffff000000) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_23: li gp, 23; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); sraw x2, x1, x2;; li x7, ((0xfffffffffffe0000) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_24: li gp, 24; li x1, ((7) & ((1 << (64 - 1) << 1) - 1)); sraw x1, x1, x1;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_25: li gp, 25; li x4, 0; 1: li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); sraw x14, x1, x2; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xffffffffff000000) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_26: li gp, 26; li x4, 0; 1: li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); sraw x14, x1, x2; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xfffffffffffe0000) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_27: li gp, 27; li x4, 0; 1: li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); sraw x14, x1, x2; nop; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+
+  test_28: li gp, 28; li x4, 0; 1: li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); sraw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xffffffffff000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_29: li gp, 29; li x4, 0; 1: li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); nop; sraw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xfffffffffffe0000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_30: li gp, 30; li x4, 0; 1: li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); nop; nop; sraw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_31: li gp, 31; li x4, 0; 1: li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); nop; li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); sraw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xffffffffff000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_32: li gp, 32; li x4, 0; 1: li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); nop; li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); nop; sraw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xfffffffffffe0000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_33: li gp, 33; li x4, 0; 1: li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); nop; nop; li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); sraw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_34: li gp, 34; li x4, 0; 1: li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); sraw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xffffffffff000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_35: li gp, 35; li x4, 0; 1: li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); nop; sraw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xfffffffffffe0000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_36: li gp, 36; li x4, 0; 1: li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); nop; nop; sraw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_37: li gp, 37; li x4, 0; 1: li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); nop; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); sraw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xffffffffff000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_38: li gp, 38; li x4, 0; 1: li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); nop; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); nop; sraw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xfffffffffffe0000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_39: li gp, 39; li x4, 0; 1: li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); nop; nop; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); sraw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_40: li gp, 40; li x1, ((15) & ((1 << (64 - 1) << 1) - 1)); sraw x2, x0, x1;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_41: li gp, 41; li x1, ((32) & ((1 << (64 - 1) << 1) - 1)); sraw x2, x1, x0;; li x7, ((32) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_42: li gp, 42; sraw x1, x0, x0;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_43: li gp, 43; li x1, ((1024) & ((1 << (64 - 1) << 1) - 1)); li x2, ((2048) & ((1 << (64 - 1) << 1) - 1)); sraw x0, x1, x2;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x0, x7, fail;;
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+
diff --git a/verilator-tests/testbench/assembly_programs/srl.s b/verilator-tests/testbench/assembly_programs/srl.s
new file mode 100644
index 0000000..664c530
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/srl.s
@@ -0,0 +1,168 @@
+# 1 "../../riscv-tests/isa/rv64ui/srl.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/srl.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# srl.S
+#-----------------------------------------------------------------------------
+
+# Test srl instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/srl.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/srl.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+
+
+
+  test_2: li gp, 2; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0) & ((1 << (64 - 1) << 1) - 1)); srl x14, x1, x2;; li x7, ((((0xffffffff80000000) & ((1 << (64 -1) << 1) - 1)) >> (0)) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_3: li gp, 3; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((1) & ((1 << (64 - 1) << 1) - 1)); srl x14, x1, x2;; li x7, ((((0xffffffff80000000) & ((1 << (64 -1) << 1) - 1)) >> (1)) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_4: li gp, 4; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); srl x14, x1, x2;; li x7, ((((0xffffffff80000000) & ((1 << (64 -1) << 1) - 1)) >> (7)) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_5: li gp, 5; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); srl x14, x1, x2;; li x7, ((((0xffffffff80000000) & ((1 << (64 -1) << 1) - 1)) >> (14)) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_6: li gp, 6; li x1, ((0xffffffff80000001) & ((1 << (64 - 1) << 1) - 1)); li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); srl x14, x1, x2;; li x7, ((((0xffffffff80000001) & ((1 << (64 -1) << 1) - 1)) >> (31)) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_7: li gp, 7; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0) & ((1 << (64 - 1) << 1) - 1)); srl x14, x1, x2;; li x7, ((((0xffffffffffffffff) & ((1 << (64 -1) << 1) - 1)) >> (0)) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_8: li gp, 8; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((1) & ((1 << (64 - 1) << 1) - 1)); srl x14, x1, x2;; li x7, ((((0xffffffffffffffff) & ((1 << (64 -1) << 1) - 1)) >> (1)) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_9: li gp, 9; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); srl x14, x1, x2;; li x7, ((((0xffffffffffffffff) & ((1 << (64 -1) << 1) - 1)) >> (7)) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_10: li gp, 10; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); srl x14, x1, x2;; li x7, ((((0xffffffffffffffff) & ((1 << (64 -1) << 1) - 1)) >> (14)) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_11: li gp, 11; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); srl x14, x1, x2;; li x7, ((((0xffffffffffffffff) & ((1 << (64 -1) << 1) - 1)) >> (31)) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_12: li gp, 12; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0) & ((1 << (64 - 1) << 1) - 1)); srl x14, x1, x2;; li x7, ((((0x0000000021212121) & ((1 << (64 -1) << 1) - 1)) >> (0)) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_13: li gp, 13; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); li x2, ((1) & ((1 << (64 - 1) << 1) - 1)); srl x14, x1, x2;; li x7, ((((0x0000000021212121) & ((1 << (64 -1) << 1) - 1)) >> (1)) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_14: li gp, 14; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); srl x14, x1, x2;; li x7, ((((0x0000000021212121) & ((1 << (64 -1) << 1) - 1)) >> (7)) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_15: li gp, 15; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); srl x14, x1, x2;; li x7, ((((0x0000000021212121) & ((1 << (64 -1) << 1) - 1)) >> (14)) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_16: li gp, 16; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); srl x14, x1, x2;; li x7, ((((0x0000000021212121) & ((1 << (64 -1) << 1) - 1)) >> (31)) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  # Verify that shifts only use bottom six(rv64) or five(rv32) bits
+
+  test_17: li gp, 17; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffffffc0) & ((1 << (64 - 1) << 1) - 1)); srl x14, x1, x2;; li x7, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_18: li gp, 18; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffffffc1) & ((1 << (64 - 1) << 1) - 1)); srl x14, x1, x2;; li x7, ((0x0000000010909090) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_19: li gp, 19; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffffffc7) & ((1 << (64 - 1) << 1) - 1)); srl x14, x1, x2;; li x7, ((0x0000000000424242) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_20: li gp, 20; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffffffce) & ((1 << (64 - 1) << 1) - 1)); srl x14, x1, x2;; li x7, ((0x0000000000008484) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_21: li gp, 21; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); srl x14, x1, x2;; li x7, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  test_22: li gp, 22; li x1, ((0x80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); srl x1, x1, x2;; li x7, ((0x01000000) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_23: li gp, 23; li x1, ((0x80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); srl x2, x1, x2;; li x7, ((0x00020000) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_24: li gp, 24; li x1, ((7) & ((1 << (64 - 1) << 1) - 1)); srl x1, x1, x1;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_25: li gp, 25; li x4, 0; 1: li x1, ((0x80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); srl x14, x1, x2; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x01000000) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_26: li gp, 26; li x4, 0; 1: li x1, ((0x80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); srl x14, x1, x2; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x00020000) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_27: li gp, 27; li x4, 0; 1: li x1, ((0x80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); srl x14, x1, x2; nop; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x00000001) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+
+  test_28: li gp, 28; li x4, 0; 1: li x1, ((0x80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); srl x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x01000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_29: li gp, 29; li x4, 0; 1: li x1, ((0x80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); nop; srl x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x00020000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_30: li gp, 30; li x4, 0; 1: li x1, ((0x80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); nop; nop; srl x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x00000001) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_31: li gp, 31; li x4, 0; 1: li x1, ((0x80000000) & ((1 << (64 - 1) << 1) - 1)); nop; li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); srl x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x01000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_32: li gp, 32; li x4, 0; 1: li x1, ((0x80000000) & ((1 << (64 - 1) << 1) - 1)); nop; li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); nop; srl x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x00020000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_33: li gp, 33; li x4, 0; 1: li x1, ((0x80000000) & ((1 << (64 - 1) << 1) - 1)); nop; nop; li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); srl x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x00000001) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_34: li gp, 34; li x4, 0; 1: li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); li x1, ((0x80000000) & ((1 << (64 - 1) << 1) - 1)); srl x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x01000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_35: li gp, 35; li x4, 0; 1: li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); li x1, ((0x80000000) & ((1 << (64 - 1) << 1) - 1)); nop; srl x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x00020000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_36: li gp, 36; li x4, 0; 1: li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); li x1, ((0x80000000) & ((1 << (64 - 1) << 1) - 1)); nop; nop; srl x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x00000001) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_37: li gp, 37; li x4, 0; 1: li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); nop; li x1, ((0x80000000) & ((1 << (64 - 1) << 1) - 1)); srl x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x01000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_38: li gp, 38; li x4, 0; 1: li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); nop; li x1, ((0x80000000) & ((1 << (64 - 1) << 1) - 1)); nop; srl x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x00020000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_39: li gp, 39; li x4, 0; 1: li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); nop; nop; li x1, ((0x80000000) & ((1 << (64 - 1) << 1) - 1)); srl x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x00000001) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_40: li gp, 40; li x1, ((15) & ((1 << (64 - 1) << 1) - 1)); srl x2, x0, x1;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_41: li gp, 41; li x1, ((32) & ((1 << (64 - 1) << 1) - 1)); srl x2, x1, x0;; li x7, ((32) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_42: li gp, 42; srl x1, x0, x0;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_43: li gp, 43; li x1, ((1024) & ((1 << (64 - 1) << 1) - 1)); li x2, ((2048) & ((1 << (64 - 1) << 1) - 1)); srl x0, x1, x2;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x0, x7, fail;;
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+
diff --git a/verilator-tests/testbench/assembly_programs/srli.s b/verilator-tests/testbench/assembly_programs/srli.s
new file mode 100644
index 0000000..71ad750
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/srli.s
@@ -0,0 +1,146 @@
+# 1 "../../riscv-tests/isa/rv64ui/srli.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/srli.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# srli.S
+#-----------------------------------------------------------------------------
+
+# Test srli instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/srli.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/srli.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+
+
+
+  test_2: li gp, 2; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); srli x14, x1, ((0) | (-(((0) >> 11) & 1) << 11));; li x7, ((((0xffffffff80000000) & ((1 << (64 -1) << 1) - 1)) >> (0)) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_3: li gp, 3; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); srli x14, x1, ((1) | (-(((1) >> 11) & 1) << 11));; li x7, ((((0xffffffff80000000) & ((1 << (64 -1) << 1) - 1)) >> (1)) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_4: li gp, 4; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); srli x14, x1, ((7) | (-(((7) >> 11) & 1) << 11));; li x7, ((((0xffffffff80000000) & ((1 << (64 -1) << 1) - 1)) >> (7)) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_5: li gp, 5; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); srli x14, x1, ((14) | (-(((14) >> 11) & 1) << 11));; li x7, ((((0xffffffff80000000) & ((1 << (64 -1) << 1) - 1)) >> (14)) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_6: li gp, 6; li x1, ((0xffffffff80000001) & ((1 << (64 - 1) << 1) - 1)); srli x14, x1, ((31) | (-(((31) >> 11) & 1) << 11));; li x7, ((((0xffffffff80000001) & ((1 << (64 -1) << 1) - 1)) >> (31)) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_7: li gp, 7; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); srli x14, x1, ((0) | (-(((0) >> 11) & 1) << 11));; li x7, ((((0xffffffffffffffff) & ((1 << (64 -1) << 1) - 1)) >> (0)) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_8: li gp, 8; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); srli x14, x1, ((1) | (-(((1) >> 11) & 1) << 11));; li x7, ((((0xffffffffffffffff) & ((1 << (64 -1) << 1) - 1)) >> (1)) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_9: li gp, 9; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); srli x14, x1, ((7) | (-(((7) >> 11) & 1) << 11));; li x7, ((((0xffffffffffffffff) & ((1 << (64 -1) << 1) - 1)) >> (7)) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_10: li gp, 10; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); srli x14, x1, ((14) | (-(((14) >> 11) & 1) << 11));; li x7, ((((0xffffffffffffffff) & ((1 << (64 -1) << 1) - 1)) >> (14)) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_11: li gp, 11; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); srli x14, x1, ((31) | (-(((31) >> 11) & 1) << 11));; li x7, ((((0xffffffffffffffff) & ((1 << (64 -1) << 1) - 1)) >> (31)) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_12: li gp, 12; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); srli x14, x1, ((0) | (-(((0) >> 11) & 1) << 11));; li x7, ((((0x0000000021212121) & ((1 << (64 -1) << 1) - 1)) >> (0)) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_13: li gp, 13; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); srli x14, x1, ((1) | (-(((1) >> 11) & 1) << 11));; li x7, ((((0x0000000021212121) & ((1 << (64 -1) << 1) - 1)) >> (1)) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_14: li gp, 14; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); srli x14, x1, ((7) | (-(((7) >> 11) & 1) << 11));; li x7, ((((0x0000000021212121) & ((1 << (64 -1) << 1) - 1)) >> (7)) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_15: li gp, 15; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); srli x14, x1, ((14) | (-(((14) >> 11) & 1) << 11));; li x7, ((((0x0000000021212121) & ((1 << (64 -1) << 1) - 1)) >> (14)) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_16: li gp, 16; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); srli x14, x1, ((31) | (-(((31) >> 11) & 1) << 11));; li x7, ((((0x0000000021212121) & ((1 << (64 -1) << 1) - 1)) >> (31)) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  test_17: li gp, 17; li x1, ((0x80000000) & ((1 << (64 - 1) << 1) - 1)); srli x1, x1, ((7) | (-(((7) >> 11) & 1) << 11));; li x7, ((0x01000000) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_18: li gp, 18; li x4, 0; 1: li x1, ((0x80000000) & ((1 << (64 - 1) << 1) - 1)); srli x14, x1, ((7) | (-(((7) >> 11) & 1) << 11)); addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x01000000) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_19: li gp, 19; li x4, 0; 1: li x1, ((0x80000000) & ((1 << (64 - 1) << 1) - 1)); srli x14, x1, ((14) | (-(((14) >> 11) & 1) << 11)); nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x00020000) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_20: li gp, 20; li x4, 0; 1: li x1, ((0x80000001) & ((1 << (64 - 1) << 1) - 1)); srli x14, x1, ((31) | (-(((31) >> 11) & 1) << 11)); nop; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x00000001) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+
+  test_21: li gp, 21; li x4, 0; 1: li x1, ((0x80000000) & ((1 << (64 - 1) << 1) - 1)); srli x14, x1, ((7) | (-(((7) >> 11) & 1) << 11)); addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x01000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_22: li gp, 22; li x4, 0; 1: li x1, ((0x80000000) & ((1 << (64 - 1) << 1) - 1)); nop; srli x14, x1, ((14) | (-(((14) >> 11) & 1) << 11)); addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x00020000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_23: li gp, 23; li x4, 0; 1: li x1, ((0x80000001) & ((1 << (64 - 1) << 1) - 1)); nop; nop; srli x14, x1, ((31) | (-(((31) >> 11) & 1) << 11)); addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x00000001) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_24: li gp, 24; srli x1, x0, ((4) | (-(((4) >> 11) & 1) << 11));; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_25: li gp, 25; li x1, ((33) & ((1 << (64 - 1) << 1) - 1)); srli x0, x1, ((10) | (-(((10) >> 11) & 1) << 11));; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x0, x7, fail;;
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+
diff --git a/verilator-tests/testbench/assembly_programs/srliw.s b/verilator-tests/testbench/assembly_programs/srliw.s
new file mode 100644
index 0000000..fd96797
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/srliw.s
@@ -0,0 +1,150 @@
+# 1 "../../riscv-tests/isa/rv64ui/srliw.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/srliw.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# srliw.S
+#-----------------------------------------------------------------------------
+
+# Test srliw instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/srliw.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/srliw.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  test_2: li gp, 2; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); srliw x14, x1, ((0) | (-(((0) >> 11) & 1) << 11));; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_3: li gp, 3; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); srliw x14, x1, ((1) | (-(((1) >> 11) & 1) << 11));; li x7, ((0x0000000040000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_4: li gp, 4; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); srliw x14, x1, ((7) | (-(((7) >> 11) & 1) << 11));; li x7, ((0x0000000001000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_5: li gp, 5; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); srliw x14, x1, ((14) | (-(((14) >> 11) & 1) << 11));; li x7, ((0x0000000000020000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_6: li gp, 6; li x1, ((0xffffffff80000001) & ((1 << (64 - 1) << 1) - 1)); srliw x14, x1, ((31) | (-(((31) >> 11) & 1) << 11));; li x7, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_7: li gp, 7; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); srliw x14, x1, ((0) | (-(((0) >> 11) & 1) << 11));; li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_8: li gp, 8; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); srliw x14, x1, ((1) | (-(((1) >> 11) & 1) << 11));; li x7, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_9: li gp, 9; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); srliw x14, x1, ((7) | (-(((7) >> 11) & 1) << 11));; li x7, ((0x0000000001ffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_10: li gp, 10; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); srliw x14, x1, ((14) | (-(((14) >> 11) & 1) << 11));; li x7, ((0x000000000003ffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_11: li gp, 11; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); srliw x14, x1, ((31) | (-(((31) >> 11) & 1) << 11));; li x7, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_12: li gp, 12; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); srliw x14, x1, ((0) | (-(((0) >> 11) & 1) << 11));; li x7, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_13: li gp, 13; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); srliw x14, x1, ((1) | (-(((1) >> 11) & 1) << 11));; li x7, ((0x0000000010909090) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_14: li gp, 14; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); srliw x14, x1, ((7) | (-(((7) >> 11) & 1) << 11));; li x7, ((0x0000000000424242) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_15: li gp, 15; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); srliw x14, x1, ((14) | (-(((14) >> 11) & 1) << 11));; li x7, ((0x0000000000008484) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_16: li gp, 16; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); srliw x14, x1, ((31) | (-(((31) >> 11) & 1) << 11));; li x7, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  # Verify that shifts ignore top 32 (using true 64-bit values)
+
+  test_44: li gp, 44; li x1, ((0xffffffff12345678) & ((1 << (64 - 1) << 1) - 1)); srliw x14, x1, ((0) | (-(((0) >> 11) & 1) << 11));; li x7, ((0x0000000012345678) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_45: li gp, 45; li x1, ((0xffffffff12345678) & ((1 << (64 - 1) << 1) - 1)); srliw x14, x1, ((4) | (-(((4) >> 11) & 1) << 11));; li x7, ((0x0000000001234567) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_46: li gp, 46; li x1, ((0x0000000092345678) & ((1 << (64 - 1) << 1) - 1)); srliw x14, x1, ((0) | (-(((0) >> 11) & 1) << 11));; li x7, ((0xffffffff92345678) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_47: li gp, 47; li x1, ((0x0000000092345678) & ((1 << (64 - 1) << 1) - 1)); srliw x14, x1, ((4) | (-(((4) >> 11) & 1) << 11));; li x7, ((0x0000000009234567) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  test_17: li gp, 17; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); srliw x1, x1, ((7) | (-(((7) >> 11) & 1) << 11));; li x7, ((0x0000000001000000) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_18: li gp, 18; li x4, 0; 1: li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); srliw x14, x1, ((7) | (-(((7) >> 11) & 1) << 11)); addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000001000000) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_19: li gp, 19; li x4, 0; 1: li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); srliw x14, x1, ((14) | (-(((14) >> 11) & 1) << 11)); nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000020000) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_20: li gp, 20; li x4, 0; 1: li x1, ((0xffffffff80000001) & ((1 << (64 - 1) << 1) - 1)); srliw x14, x1, ((31) | (-(((31) >> 11) & 1) << 11)); nop; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+
+  test_21: li gp, 21; li x4, 0; 1: li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); srliw x14, x1, ((7) | (-(((7) >> 11) & 1) << 11)); addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000001000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_22: li gp, 22; li x4, 0; 1: li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); nop; srliw x14, x1, ((14) | (-(((14) >> 11) & 1) << 11)); addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000020000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_23: li gp, 23; li x4, 0; 1: li x1, ((0xffffffff80000001) & ((1 << (64 - 1) << 1) - 1)); nop; nop; srliw x14, x1, ((31) | (-(((31) >> 11) & 1) << 11)); addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_24: li gp, 24; srliw x1, x0, ((31) | (-(((31) >> 11) & 1) << 11));; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_25: li gp, 25; li x1, ((31) & ((1 << (64 - 1) << 1) - 1)); srliw x0, x1, ((28) | (-(((28) >> 11) & 1) << 11));; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x0, x7, fail;;
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+
diff --git a/verilator-tests/testbench/assembly_programs/srlw.s b/verilator-tests/testbench/assembly_programs/srlw.s
new file mode 100644
index 0000000..78a8d7f
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/srlw.s
@@ -0,0 +1,172 @@
+# 1 "../../riscv-tests/isa/rv64ui/srlw.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/srlw.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# srlw.S
+#-----------------------------------------------------------------------------
+
+# Test srlw instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/srlw.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/srlw.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  test_2: li gp, 2; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0) & ((1 << (64 - 1) << 1) - 1)); srlw x14, x1, x2;; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_3: li gp, 3; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((1) & ((1 << (64 - 1) << 1) - 1)); srlw x14, x1, x2;; li x7, ((0x0000000040000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_4: li gp, 4; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); srlw x14, x1, x2;; li x7, ((0x0000000001000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_5: li gp, 5; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); srlw x14, x1, x2;; li x7, ((0x0000000000020000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_6: li gp, 6; li x1, ((0xffffffff80000001) & ((1 << (64 - 1) << 1) - 1)); li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); srlw x14, x1, x2;; li x7, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_7: li gp, 7; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0) & ((1 << (64 - 1) << 1) - 1)); srlw x14, x1, x2;; li x7, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_8: li gp, 8; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((1) & ((1 << (64 - 1) << 1) - 1)); srlw x14, x1, x2;; li x7, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_9: li gp, 9; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); srlw x14, x1, x2;; li x7, ((0x0000000001ffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_10: li gp, 10; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); srlw x14, x1, x2;; li x7, ((0x000000000003ffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_11: li gp, 11; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); srlw x14, x1, x2;; li x7, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_12: li gp, 12; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0) & ((1 << (64 - 1) << 1) - 1)); srlw x14, x1, x2;; li x7, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_13: li gp, 13; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); li x2, ((1) & ((1 << (64 - 1) << 1) - 1)); srlw x14, x1, x2;; li x7, ((0x0000000010909090) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_14: li gp, 14; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); srlw x14, x1, x2;; li x7, ((0x0000000000424242) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_15: li gp, 15; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); srlw x14, x1, x2;; li x7, ((0x0000000000008484) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_16: li gp, 16; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); srlw x14, x1, x2;; li x7, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  # Verify that shifts only use bottom five bits
+
+  test_17: li gp, 17; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffffffe0) & ((1 << (64 - 1) << 1) - 1)); srlw x14, x1, x2;; li x7, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_18: li gp, 18; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffffffe1) & ((1 << (64 - 1) << 1) - 1)); srlw x14, x1, x2;; li x7, ((0x0000000010909090) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_19: li gp, 19; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffffffe7) & ((1 << (64 - 1) << 1) - 1)); srlw x14, x1, x2;; li x7, ((0x0000000000424242) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_20: li gp, 20; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffffffee) & ((1 << (64 - 1) << 1) - 1)); srlw x14, x1, x2;; li x7, ((0x0000000000008484) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_21: li gp, 21; li x1, ((0x0000000021212121) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); srlw x14, x1, x2;; li x7, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  # Verify that shifts ignore top 32 (using true 64-bit values)
+
+  test_44: li gp, 44; li x1, ((0xffffffff12345678) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0) & ((1 << (64 - 1) << 1) - 1)); srlw x14, x1, x2;; li x7, ((0x0000000012345678) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_45: li gp, 45; li x1, ((0xffffffff12345678) & ((1 << (64 - 1) << 1) - 1)); li x2, ((4) & ((1 << (64 - 1) << 1) - 1)); srlw x14, x1, x2;; li x7, ((0x0000000001234567) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_46: li gp, 46; li x1, ((0x0000000092345678) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0) & ((1 << (64 - 1) << 1) - 1)); srlw x14, x1, x2;; li x7, ((0xffffffff92345678) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_47: li gp, 47; li x1, ((0x0000000092345678) & ((1 << (64 - 1) << 1) - 1)); li x2, ((4) & ((1 << (64 - 1) << 1) - 1)); srlw x14, x1, x2;; li x7, ((0x0000000009234567) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  test_22: li gp, 22; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); srlw x1, x1, x2;; li x7, ((0x0000000001000000) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_23: li gp, 23; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); srlw x2, x1, x2;; li x7, ((0x0000000000020000) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_24: li gp, 24; li x1, ((7) & ((1 << (64 - 1) << 1) - 1)); srlw x1, x1, x1;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_25: li gp, 25; li x4, 0; 1: li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); srlw x14, x1, x2; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000001000000) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_26: li gp, 26; li x4, 0; 1: li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); srlw x14, x1, x2; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000020000) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_27: li gp, 27; li x4, 0; 1: li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); srlw x14, x1, x2; nop; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+
+  test_28: li gp, 28; li x4, 0; 1: li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); srlw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000001000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_29: li gp, 29; li x4, 0; 1: li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); nop; srlw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000020000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_30: li gp, 30; li x4, 0; 1: li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); nop; nop; srlw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_31: li gp, 31; li x4, 0; 1: li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); nop; li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); srlw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000001000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_32: li gp, 32; li x4, 0; 1: li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); nop; li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); nop; srlw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000020000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_33: li gp, 33; li x4, 0; 1: li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); nop; nop; li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); srlw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_34: li gp, 34; li x4, 0; 1: li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); srlw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000001000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_35: li gp, 35; li x4, 0; 1: li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); nop; srlw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000020000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_36: li gp, 36; li x4, 0; 1: li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); nop; nop; srlw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_37: li gp, 37; li x4, 0; 1: li x2, ((7) & ((1 << (64 - 1) << 1) - 1)); nop; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); srlw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000001000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_38: li gp, 38; li x4, 0; 1: li x2, ((14) & ((1 << (64 - 1) << 1) - 1)); nop; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); nop; srlw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000020000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_39: li gp, 39; li x4, 0; 1: li x2, ((31) & ((1 << (64 - 1) << 1) - 1)); nop; nop; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); srlw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_40: li gp, 40; li x1, ((15) & ((1 << (64 - 1) << 1) - 1)); srlw x2, x0, x1;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_41: li gp, 41; li x1, ((32) & ((1 << (64 - 1) << 1) - 1)); srlw x2, x1, x0;; li x7, ((32) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_42: li gp, 42; srlw x1, x0, x0;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_43: li gp, 43; li x1, ((1024) & ((1 << (64 - 1) << 1) - 1)); li x2, ((2048) & ((1 << (64 - 1) << 1) - 1)); srlw x0, x1, x2;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x0, x7, fail;;
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+
diff --git a/verilator-tests/testbench/assembly_programs/sub.s b/verilator-tests/testbench/assembly_programs/sub.s
new file mode 100644
index 0000000..4552b2d
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/sub.s
@@ -0,0 +1,158 @@
+# 1 "../../riscv-tests/isa/rv64ui/sub.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/sub.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sub.S
+#-----------------------------------------------------------------------------
+
+# Test sub instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/sub.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/sub.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  test_2: li gp, 2; li x1, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); sub x14, x1, x2;; li x7, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_3: li gp, 3; li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); sub x14, x1, x2;; li x7, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_4: li gp, 4; li x1, ((0x0000000000000003) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0000000000000007) & ((1 << (64 - 1) << 1) - 1)); sub x14, x1, x2;; li x7, ((0xfffffffffffffffc) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_5: li gp, 5; li x1, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffff8000) & ((1 << (64 - 1) << 1) - 1)); sub x14, x1, x2;; li x7, ((0x0000000000008000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_6: li gp, 6; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); sub x14, x1, x2;; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_7: li gp, 7; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffff8000) & ((1 << (64 - 1) << 1) - 1)); sub x14, x1, x2;; li x7, ((0xffffffff80008000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_8: li gp, 8; li x1, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0000000000007fff) & ((1 << (64 - 1) << 1) - 1)); sub x14, x1, x2;; li x7, ((0xffffffffffff8001) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_9: li gp, 9; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); sub x14, x1, x2;; li x7, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_10: li gp, 10; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0000000000007fff) & ((1 << (64 - 1) << 1) - 1)); sub x14, x1, x2;; li x7, ((0x000000007fff8000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_11: li gp, 11; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0000000000007fff) & ((1 << (64 - 1) << 1) - 1)); sub x14, x1, x2;; li x7, ((0xffffffff7fff8001) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_12: li gp, 12; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffff8000) & ((1 << (64 - 1) << 1) - 1)); sub x14, x1, x2;; li x7, ((0x0000000080007fff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_13: li gp, 13; li x1, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); sub x14, x1, x2;; li x7, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_14: li gp, 14; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); sub x14, x1, x2;; li x7, ((0xfffffffffffffffe) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_15: li gp, 15; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); sub x14, x1, x2;; li x7, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  test_16: li gp, 16; li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); sub x1, x1, x2;; li x7, ((2) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_17: li gp, 17; li x1, ((14) & ((1 << (64 - 1) << 1) - 1)); li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); sub x2, x1, x2;; li x7, ((3) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_18: li gp, 18; li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); sub x1, x1, x1;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_19: li gp, 19; li x4, 0; 1: li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); sub x14, x1, x2; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((2) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_20: li gp, 20; li x4, 0; 1: li x1, ((14) & ((1 << (64 - 1) << 1) - 1)); li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); sub x14, x1, x2; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((3) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_21: li gp, 21; li x4, 0; 1: li x1, ((15) & ((1 << (64 - 1) << 1) - 1)); li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); sub x14, x1, x2; nop; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((4) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+
+  test_22: li gp, 22; li x4, 0; 1: li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); sub x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((2) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_23: li gp, 23; li x4, 0; 1: li x1, ((14) & ((1 << (64 - 1) << 1) - 1)); li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); nop; sub x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((3) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_24: li gp, 24; li x4, 0; 1: li x1, ((15) & ((1 << (64 - 1) << 1) - 1)); li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); nop; nop; sub x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((4) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_25: li gp, 25; li x4, 0; 1: li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); nop; li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); sub x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((2) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_26: li gp, 26; li x4, 0; 1: li x1, ((14) & ((1 << (64 - 1) << 1) - 1)); nop; li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); nop; sub x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((3) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_27: li gp, 27; li x4, 0; 1: li x1, ((15) & ((1 << (64 - 1) << 1) - 1)); nop; nop; li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); sub x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((4) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_28: li gp, 28; li x4, 0; 1: li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); sub x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((2) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_29: li gp, 29; li x4, 0; 1: li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); li x1, ((14) & ((1 << (64 - 1) << 1) - 1)); nop; sub x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((3) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_30: li gp, 30; li x4, 0; 1: li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); li x1, ((15) & ((1 << (64 - 1) << 1) - 1)); nop; nop; sub x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((4) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_31: li gp, 31; li x4, 0; 1: li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); nop; li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); sub x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((2) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_32: li gp, 32; li x4, 0; 1: li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); nop; li x1, ((14) & ((1 << (64 - 1) << 1) - 1)); nop; sub x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((3) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_33: li gp, 33; li x4, 0; 1: li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); nop; nop; li x1, ((15) & ((1 << (64 - 1) << 1) - 1)); sub x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((4) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_34: li gp, 34; li x1, ((-15) & ((1 << (64 - 1) << 1) - 1)); sub x2, x0, x1;; li x7, ((15) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_35: li gp, 35; li x1, ((32) & ((1 << (64 - 1) << 1) - 1)); sub x2, x1, x0;; li x7, ((32) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_36: li gp, 36; sub x1, x0, x0;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_37: li gp, 37; li x1, ((16) & ((1 << (64 - 1) << 1) - 1)); li x2, ((30) & ((1 << (64 - 1) << 1) - 1)); sub x0, x1, x2;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x0, x7, fail;;
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+
diff --git a/verilator-tests/testbench/assembly_programs/subw.s b/verilator-tests/testbench/assembly_programs/subw.s
new file mode 100644
index 0000000..cc97632
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/subw.s
@@ -0,0 +1,158 @@
+# 1 "../../riscv-tests/isa/rv64ui/subw.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/subw.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# subw.S
+#-----------------------------------------------------------------------------
+
+# Test subw instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/subw.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/subw.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  test_2: li gp, 2; li x1, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); subw x14, x1, x2;; li x7, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_3: li gp, 3; li x1, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); subw x14, x1, x2;; li x7, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_4: li gp, 4; li x1, ((0x0000000000000003) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0000000000000007) & ((1 << (64 - 1) << 1) - 1)); subw x14, x1, x2;; li x7, ((0xfffffffffffffffc) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_5: li gp, 5; li x1, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffff8000) & ((1 << (64 - 1) << 1) - 1)); subw x14, x1, x2;; li x7, ((0x0000000000008000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_6: li gp, 6; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); subw x14, x1, x2;; li x7, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_7: li gp, 7; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffff8000) & ((1 << (64 - 1) << 1) - 1)); subw x14, x1, x2;; li x7, ((0xffffffff80008000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_8: li gp, 8; li x1, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0000000000007fff) & ((1 << (64 - 1) << 1) - 1)); subw x14, x1, x2;; li x7, ((0xffffffffffff8001) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_9: li gp, 9; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); subw x14, x1, x2;; li x7, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_10: li gp, 10; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0000000000007fff) & ((1 << (64 - 1) << 1) - 1)); subw x14, x1, x2;; li x7, ((0x000000007fff8000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_11: li gp, 11; li x1, ((0xffffffff80000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0000000000007fff) & ((1 << (64 - 1) << 1) - 1)); subw x14, x1, x2;; li x7, ((0x000000007fff8001) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_12: li gp, 12; li x1, ((0x000000007fffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffff8000) & ((1 << (64 - 1) << 1) - 1)); subw x14, x1, x2;; li x7, ((0xffffffff80007fff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_13: li gp, 13; li x1, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); subw x14, x1, x2;; li x7, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_14: li gp, 14; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0000000000000001) & ((1 << (64 - 1) << 1) - 1)); subw x14, x1, x2;; li x7, ((0xfffffffffffffffe) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_15: li gp, 15; li x1, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xffffffffffffffff) & ((1 << (64 - 1) << 1) - 1)); subw x14, x1, x2;; li x7, ((0x0000000000000000) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  test_16: li gp, 16; li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); subw x1, x1, x2;; li x7, ((2) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_17: li gp, 17; li x1, ((14) & ((1 << (64 - 1) << 1) - 1)); li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); subw x2, x1, x2;; li x7, ((3) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_18: li gp, 18; li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); subw x1, x1, x1;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_19: li gp, 19; li x4, 0; 1: li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); subw x14, x1, x2; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((2) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_20: li gp, 20; li x4, 0; 1: li x1, ((14) & ((1 << (64 - 1) << 1) - 1)); li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); subw x14, x1, x2; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((3) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_21: li gp, 21; li x4, 0; 1: li x1, ((15) & ((1 << (64 - 1) << 1) - 1)); li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); subw x14, x1, x2; nop; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((4) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+
+  test_22: li gp, 22; li x4, 0; 1: li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); subw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((2) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_23: li gp, 23; li x4, 0; 1: li x1, ((14) & ((1 << (64 - 1) << 1) - 1)); li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); nop; subw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((3) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_24: li gp, 24; li x4, 0; 1: li x1, ((15) & ((1 << (64 - 1) << 1) - 1)); li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); nop; nop; subw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((4) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_25: li gp, 25; li x4, 0; 1: li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); nop; li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); subw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((2) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_26: li gp, 26; li x4, 0; 1: li x1, ((14) & ((1 << (64 - 1) << 1) - 1)); nop; li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); nop; subw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((3) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_27: li gp, 27; li x4, 0; 1: li x1, ((15) & ((1 << (64 - 1) << 1) - 1)); nop; nop; li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); subw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((4) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_28: li gp, 28; li x4, 0; 1: li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); subw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((2) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_29: li gp, 29; li x4, 0; 1: li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); li x1, ((14) & ((1 << (64 - 1) << 1) - 1)); nop; subw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((3) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_30: li gp, 30; li x4, 0; 1: li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); li x1, ((15) & ((1 << (64 - 1) << 1) - 1)); nop; nop; subw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((4) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_31: li gp, 31; li x4, 0; 1: li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); nop; li x1, ((13) & ((1 << (64 - 1) << 1) - 1)); subw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((2) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_32: li gp, 32; li x4, 0; 1: li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); nop; li x1, ((14) & ((1 << (64 - 1) << 1) - 1)); nop; subw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((3) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_33: li gp, 33; li x4, 0; 1: li x2, ((11) & ((1 << (64 - 1) << 1) - 1)); nop; nop; li x1, ((15) & ((1 << (64 - 1) << 1) - 1)); subw x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((4) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_34: li gp, 34; li x1, ((-15) & ((1 << (64 - 1) << 1) - 1)); subw x2, x0, x1;; li x7, ((15) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_35: li gp, 35; li x1, ((32) & ((1 << (64 - 1) << 1) - 1)); subw x2, x1, x0;; li x7, ((32) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_36: li gp, 36; subw x1, x0, x0;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_37: li gp, 37; li x1, ((16) & ((1 << (64 - 1) << 1) - 1)); li x2, ((30) & ((1 << (64 - 1) << 1) - 1)); subw x0, x1, x2;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x0, x7, fail;;
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+
diff --git a/verilator-tests/testbench/assembly_programs/sw.s b/verilator-tests/testbench/assembly_programs/sw.s
new file mode 100644
index 0000000..7e780c5
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/sw.s
@@ -0,0 +1,160 @@
+# 1 "../../riscv-tests/isa/rv64ui/sw.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/sw.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sw.S
+#-----------------------------------------------------------------------------
+
+# Test sw instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/sw.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/sw.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  test_2: li gp, 2; la x1, tdat; li x2, 0x0000000000aa00aa; la x15, 7f; sw x2, 0(x1); lw x14, 0(x1); j 8f; 7: mv x14, x2; 8:; li x7, ((0x0000000000aa00aa) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_3: li gp, 3; la x1, tdat; li x2, 0xffffffffaa00aa00; la x15, 7f; sw x2, 4(x1); lw x14, 4(x1); j 8f; 7: mv x14, x2; 8:; li x7, ((0xffffffffaa00aa00) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_4: li gp, 4; la x1, tdat; li x2, 0x000000000aa00aa0; la x15, 7f; sw x2, 8(x1); lw x14, 8(x1); j 8f; 7: mv x14, x2; 8:; li x7, ((0x000000000aa00aa0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_5: li gp, 5; la x1, tdat; li x2, 0xffffffffa00aa00a; la x15, 7f; sw x2, 12(x1); lw x14, 12(x1); j 8f; 7: mv x14, x2; 8:; li x7, ((0xffffffffa00aa00a) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  # Test with negative offset
+
+  test_6: li gp, 6; la x1, tdat8; li x2, 0x0000000000aa00aa; la x15, 7f; sw x2, -12(x1); lw x14, -12(x1); j 8f; 7: mv x14, x2; 8:; li x7, ((0x0000000000aa00aa) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_7: li gp, 7; la x1, tdat8; li x2, 0xffffffffaa00aa00; la x15, 7f; sw x2, -8(x1); lw x14, -8(x1); j 8f; 7: mv x14, x2; 8:; li x7, ((0xffffffffaa00aa00) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_8: li gp, 8; la x1, tdat8; li x2, 0x000000000aa00aa0; la x15, 7f; sw x2, -4(x1); lw x14, -4(x1); j 8f; 7: mv x14, x2; 8:; li x7, ((0x000000000aa00aa0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_9: li gp, 9; la x1, tdat8; li x2, 0xffffffffa00aa00a; la x15, 7f; sw x2, 0(x1); lw x14, 0(x1); j 8f; 7: mv x14, x2; 8:; li x7, ((0xffffffffa00aa00a) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  # Test with a negative base
+
+  test_10: li gp, 10; la x1, tdat9; li x2, 0x12345678; addi x4, x1, -32; sw x2, 32(x4); lw x5, 0(x1);; li x7, ((0x12345678) & ((1 << (64 - 1) << 1) - 1)); bne x5, x7, fail;
+
+
+
+
+
+
+
+  # Test with unaligned base
+
+  test_11: li gp, 11; la x1, tdat9; li x2, 0x58213098; addi x1, x1, -3; sw x2, 7(x1); la x4, tdat10; lw x5, 0(x4);; li x7, ((0x58213098) & ((1 << (64 - 1) << 1) - 1)); bne x5, x7, fail;
+# 53 "../../riscv-tests/isa/rv64ui/sw.S"
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_12: li gp, 12; li x4, 0; 1: li x1, 0xffffffffaabbccdd; la x2, tdat; sw x1, 0(x2); lw x14, 0(x2); li x7, 0xffffffffaabbccdd; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_13: li gp, 13; li x4, 0; 1: li x1, 0xffffffffdaabbccd; la x2, tdat; nop; sw x1, 4(x2); lw x14, 4(x2); li x7, 0xffffffffdaabbccd; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_14: li gp, 14; li x4, 0; 1: li x1, 0xffffffffddaabbcc; la x2, tdat; nop; nop; sw x1, 8(x2); lw x14, 8(x2); li x7, 0xffffffffddaabbcc; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_15: li gp, 15; li x4, 0; 1: li x1, 0xffffffffcddaabbc; nop; la x2, tdat; sw x1, 12(x2); lw x14, 12(x2); li x7, 0xffffffffcddaabbc; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_16: li gp, 16; li x4, 0; 1: li x1, 0xffffffffccddaabb; nop; la x2, tdat; nop; sw x1, 16(x2); lw x14, 16(x2); li x7, 0xffffffffccddaabb; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_17: li gp, 17; li x4, 0; 1: li x1, 0xffffffffbccddaab; nop; nop; la x2, tdat; sw x1, 20(x2); lw x14, 20(x2); li x7, 0xffffffffbccddaab; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+
+  test_18: li gp, 18; li x4, 0; 1: la x2, tdat; li x1, 0x00112233; sw x1, 0(x2); lw x14, 0(x2); li x7, 0x00112233; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_19: li gp, 19; li x4, 0; 1: la x2, tdat; li x1, 0x30011223; nop; sw x1, 4(x2); lw x14, 4(x2); li x7, 0x30011223; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_20: li gp, 20; li x4, 0; 1: la x2, tdat; li x1, 0x33001122; nop; nop; sw x1, 8(x2); lw x14, 8(x2); li x7, 0x33001122; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_21: li gp, 21; li x4, 0; 1: la x2, tdat; nop; li x1, 0x23300112; sw x1, 12(x2); lw x14, 12(x2); li x7, 0x23300112; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_22: li gp, 22; li x4, 0; 1: la x2, tdat; nop; li x1, 0x22330011; nop; sw x1, 16(x2); lw x14, 16(x2); li x7, 0x22330011; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+  test_23: li gp, 23; li x4, 0; 1: la x2, tdat; nop; nop; li x1, 0x12233001; sw x1, 20(x2); lw x14, 20(x2); li x7, 0x12233001; bne x14, x7, fail; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b;
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+tdat:
+tdat1: .word 0xdeadbeef
+tdat2: .word 0xdeadbeef
+tdat3: .word 0xdeadbeef
+tdat4: .word 0xdeadbeef
+tdat5: .word 0xdeadbeef
+tdat6: .word 0xdeadbeef
+tdat7: .word 0xdeadbeef
+tdat8: .word 0xdeadbeef
+tdat9: .word 0xdeadbeef
+tdat10: .word 0xdeadbeef
+
+
diff --git a/verilator-tests/testbench/assembly_programs/xor.s b/verilator-tests/testbench/assembly_programs/xor.s
new file mode 100644
index 0000000..b396f75
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/xor.s
@@ -0,0 +1,144 @@
+# 1 "../../riscv-tests/isa/rv64ui/xor.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/xor.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# xor.S
+#-----------------------------------------------------------------------------
+
+# Test xor instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/xor.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/xor.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Logical tests
+  #-------------------------------------------------------------
+
+  test_2: li gp, 2; li x1, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0f0f0f0f) & ((1 << (64 - 1) << 1) - 1)); xor x14, x1, x2;; li x7, ((0xf00ff00f) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_3: li gp, 3; li x1, ((0x0ff00ff0) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xf0f0f0f0) & ((1 << (64 - 1) << 1) - 1)); xor x14, x1, x2;; li x7, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_4: li gp, 4; li x1, ((0x00ff00ff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0f0f0f0f) & ((1 << (64 - 1) << 1) - 1)); xor x14, x1, x2;; li x7, ((0x0ff00ff0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_5: li gp, 5; li x1, ((0xf00ff00f) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xf0f0f0f0) & ((1 << (64 - 1) << 1) - 1)); xor x14, x1, x2;; li x7, ((0x00ff00ff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  test_6: li gp, 6; li x1, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0f0f0f0f) & ((1 << (64 - 1) << 1) - 1)); xor x1, x1, x2;; li x7, ((0xf00ff00f) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_7: li gp, 7; li x1, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0f0f0f0f) & ((1 << (64 - 1) << 1) - 1)); xor x2, x1, x2;; li x7, ((0xf00ff00f) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_8: li gp, 8; li x1, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); xor x1, x1, x1;; li x7, ((0x00000000) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_9: li gp, 9; li x4, 0; 1: li x1, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0f0f0f0f) & ((1 << (64 - 1) << 1) - 1)); xor x14, x1, x2; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xf00ff00f) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_10: li gp, 10; li x4, 0; 1: li x1, ((0x0ff00ff0) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xf0f0f0f0) & ((1 << (64 - 1) << 1) - 1)); xor x14, x1, x2; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_11: li gp, 11; li x4, 0; 1: li x1, ((0x00ff00ff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0f0f0f0f) & ((1 << (64 - 1) << 1) - 1)); xor x14, x1, x2; nop; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0ff00ff0) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+
+  test_12: li gp, 12; li x4, 0; 1: li x1, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0f0f0f0f) & ((1 << (64 - 1) << 1) - 1)); xor x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xf00ff00f) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_13: li gp, 13; li x4, 0; 1: li x1, ((0x0ff00ff0) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0xf0f0f0f0) & ((1 << (64 - 1) << 1) - 1)); nop; xor x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_14: li gp, 14; li x4, 0; 1: li x1, ((0x00ff00ff) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x0f0f0f0f) & ((1 << (64 - 1) << 1) - 1)); nop; nop; xor x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0ff00ff0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_15: li gp, 15; li x4, 0; 1: li x1, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); nop; li x2, ((0x0f0f0f0f) & ((1 << (64 - 1) << 1) - 1)); xor x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xf00ff00f) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_16: li gp, 16; li x4, 0; 1: li x1, ((0x0ff00ff0) & ((1 << (64 - 1) << 1) - 1)); nop; li x2, ((0xf0f0f0f0) & ((1 << (64 - 1) << 1) - 1)); nop; xor x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_17: li gp, 17; li x4, 0; 1: li x1, ((0x00ff00ff) & ((1 << (64 - 1) << 1) - 1)); nop; nop; li x2, ((0x0f0f0f0f) & ((1 << (64 - 1) << 1) - 1)); xor x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0ff00ff0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_18: li gp, 18; li x4, 0; 1: li x2, ((0x0f0f0f0f) & ((1 << (64 - 1) << 1) - 1)); li x1, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); xor x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xf00ff00f) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_19: li gp, 19; li x4, 0; 1: li x2, ((0xf0f0f0f0) & ((1 << (64 - 1) << 1) - 1)); li x1, ((0x0ff00ff0) & ((1 << (64 - 1) << 1) - 1)); nop; xor x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_20: li gp, 20; li x4, 0; 1: li x2, ((0x0f0f0f0f) & ((1 << (64 - 1) << 1) - 1)); li x1, ((0x00ff00ff) & ((1 << (64 - 1) << 1) - 1)); nop; nop; xor x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0ff00ff0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_21: li gp, 21; li x4, 0; 1: li x2, ((0x0f0f0f0f) & ((1 << (64 - 1) << 1) - 1)); nop; li x1, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); xor x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xf00ff00f) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_22: li gp, 22; li x4, 0; 1: li x2, ((0xf0f0f0f0) & ((1 << (64 - 1) << 1) - 1)); nop; li x1, ((0x0ff00ff0) & ((1 << (64 - 1) << 1) - 1)); nop; xor x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_23: li gp, 23; li x4, 0; 1: li x2, ((0x0f0f0f0f) & ((1 << (64 - 1) << 1) - 1)); nop; nop; li x1, ((0x00ff00ff) & ((1 << (64 - 1) << 1) - 1)); xor x14, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0ff00ff0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_24: li gp, 24; li x1, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); xor x2, x0, x1;; li x7, ((0xff00ff00) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_25: li gp, 25; li x1, ((0x00ff00ff) & ((1 << (64 - 1) << 1) - 1)); xor x2, x1, x0;; li x7, ((0x00ff00ff) & ((1 << (64 - 1) << 1) - 1)); bne x2, x7, fail;;
+  test_26: li gp, 26; xor x1, x0, x0;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_27: li gp, 27; li x1, ((0x11111111) & ((1 << (64 - 1) << 1) - 1)); li x2, ((0x22222222) & ((1 << (64 - 1) << 1) - 1)); xor x0, x1, x2;; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x0, x7, fail;;
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+
diff --git a/verilator-tests/testbench/assembly_programs/xori.s b/verilator-tests/testbench/assembly_programs/xori.s
new file mode 100644
index 0000000..a914bbb
--- /dev/null
+++ b/verilator-tests/testbench/assembly_programs/xori.s
@@ -0,0 +1,130 @@
+# 1 "../../riscv-tests/isa/rv64ui/xori.S"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "../../riscv-tests/isa/rv64ui/xori.S"
+# See LICENSE for license details.
+
+#*****************************************************************************
+# xori.S
+#-----------------------------------------------------------------------------
+
+# Test xori instruction.
+
+
+# 1 "../../riscv-tests/env/v/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/riscv_test.h" 1
+
+
+
+
+
+# 1 "../../riscv-tests/env/v/../p/../encoding.h" 1
+# 7 "../../riscv-tests/env/v/../p/riscv_test.h" 2
+# 7 "../../riscv-tests/env/v/riscv_test.h" 2
+# 11 "../../riscv-tests/isa/rv64ui/xori.S" 2
+# 1 "../../riscv-tests/isa/macros/scalar/test_macros.h" 1
+
+
+
+
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+# 20 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+# 36 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+# 92 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+# 120 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+# 214 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+# 347 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+# 376 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+# 735 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in gp)
+#-----------------------------------------------------------------------
+# 747 "../../riscv-tests/isa/macros/scalar/test_macros.h"
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+# 12 "../../riscv-tests/isa/rv64ui/xori.S" 2
+
+.macro init; .endm
+.text; .global _start
+
+_start:
+	j test_2
+
+  #-------------------------------------------------------------
+  # Logical tests
+  #-------------------------------------------------------------
+
+  test_2: li gp, 2; li x1, ((0x0000000000ff0f00) & ((1 << (64 - 1) << 1) - 1)); xori x14, x1, ((0xf0f) | (-(((0xf0f) >> 11) & 1) << 11));; li x7, ((0xffffffffff00f00f) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_3: li gp, 3; li x1, ((0x000000000ff00ff0) & ((1 << (64 - 1) << 1) - 1)); xori x14, x1, ((0x0f0) | (-(((0x0f0) >> 11) & 1) << 11));; li x7, ((0x000000000ff00f00) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_4: li gp, 4; li x1, ((0x0000000000ff08ff) & ((1 << (64 - 1) << 1) - 1)); xori x14, x1, ((0x70f) | (-(((0x70f) >> 11) & 1) << 11));; li x7, ((0x0000000000ff0ff0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_5: li gp, 5; li x1, ((0xfffffffff00ff00f) & ((1 << (64 - 1) << 1) - 1)); xori x14, x1, ((0x0f0) | (-(((0x0f0) >> 11) & 1) << 11));; li x7, ((0xfffffffff00ff0ff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  test_6: li gp, 6; li x1, ((0xffffffffff00f700) & ((1 << (64 - 1) << 1) - 1)); xori x1, x1, ((0x70f) | (-(((0x70f) >> 11) & 1) << 11));; li x7, ((0xffffffffff00f00f) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+
+   #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  test_7: li gp, 7; li x4, 0; 1: li x1, ((0x000000000ff00ff0) & ((1 << (64 - 1) << 1) - 1)); xori x14, x1, ((0x0f0) | (-(((0x0f0) >> 11) & 1) << 11)); addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x000000000ff00f00) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_8: li gp, 8; li x4, 0; 1: li x1, ((0x0000000000ff08ff) & ((1 << (64 - 1) << 1) - 1)); xori x14, x1, ((0x70f) | (-(((0x70f) >> 11) & 1) << 11)); nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000ff0ff0) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+  test_9: li gp, 9; li x4, 0; 1: li x1, ((0xfffffffff00ff00f) & ((1 << (64 - 1) << 1) - 1)); xori x14, x1, ((0x0f0) | (-(((0x0f0) >> 11) & 1) << 11)); nop; nop; addi x6, x14, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xfffffffff00ff0ff) & ((1 << (64 - 1) << 1) - 1)); bne x6, x7, fail;;
+
+  test_10: li gp, 10; li x4, 0; 1: li x1, ((0x000000000ff00ff0) & ((1 << (64 - 1) << 1) - 1)); xori x14, x1, ((0x0f0) | (-(((0x0f0) >> 11) & 1) << 11)); addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x000000000ff00f00) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_11: li gp, 11; li x4, 0; 1: li x1, ((0x0000000000ff0fff) & ((1 << (64 - 1) << 1) - 1)); nop; xori x14, x1, ((0x00f) | (-(((0x00f) >> 11) & 1) << 11)); addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0x0000000000ff0ff0) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+  test_12: li gp, 12; li x4, 0; 1: li x1, ((0xfffffffff00ff00f) & ((1 << (64 - 1) << 1) - 1)); nop; nop; xori x14, x1, ((0x0f0) | (-(((0x0f0) >> 11) & 1) << 11)); addi x4, x4, 1; li x5, 2; bne x4, x5, 1b; li x7, ((0xfffffffff00ff0ff) & ((1 << (64 - 1) << 1) - 1)); bne x14, x7, fail;;
+
+  test_13: li gp, 13; xori x1, x0, ((0x0f0) | (-(((0x0f0) >> 11) & 1) << 11));; li x7, ((0x0f0) & ((1 << (64 - 1) << 1) - 1)); bne x1, x7, fail;;
+  test_14: li gp, 14; li x1, ((0x00ff00ff) & ((1 << (64 - 1) << 1) - 1)); xori x0, x1, ((0x70f) | (-(((0x70f) >> 11) & 1) << 11));; li x7, ((0) & ((1 << (64 - 1) << 1) - 1)); bne x0, x7, fail;;
+
+  bne x0, gp, pass; fail: sll a0, gp, 1; 1:beqz a0, 1b; or a0, a0, 1; sb a0, -1(zero);; pass: li a0, 1; sb a0, -1(zero)
+
+unimp
+
+  .data
+ .pushsection .tohost,"aw",@progbits; .align 6; .global tohost; tohost: .dword 0; .align 6; .global fromhost; fromhost: .dword 0; .popsection; .align 4; .global begin_signature; begin_signature:
+
+ 
+
+
diff --git a/verilator-tests/testbench/create-tests-programs.sh b/verilator-tests/testbench/create-tests-programs.sh
new file mode 100644
index 0000000..00f6da2
--- /dev/null
+++ b/verilator-tests/testbench/create-tests-programs.sh
@@ -0,0 +1,24 @@
+#! /bin/sh
+rm -r objectfiles
+rm -r elffiles
+rm -r dumps
+rm -r target_texts
+mkdir objectfiles
+for file in assembly_programs/*.s; do
+  $1-as "$file" -o objectfiles/`basename "$file" ".s"`.o
+done
+
+mkdir elffiles
+for file in objectfiles/*.o; do
+  $1-ld -Tvirt.ld "$file" -o elffiles/`basename "$file" ".o"`
+done
+
+mkdir dumps
+for file in elffiles/*; do
+  $1-objdump -S "$file" > dumps/`basename "$file"`.dump
+done
+
+mkdir target_texts
+for file in elffiles/*; do
+  $1-objcopy -O binary "$file" target_texts/`basename "$file"`.text
+done
\ No newline at end of file
diff --git a/verilator-tests/testbench/output.hex b/verilator-tests/testbench/output.hex
index 58dac46..71e8d59 100644
--- a/verilator-tests/testbench/output.hex
+++ b/verilator-tests/testbench/output.hex
@@ -1,2 +1,2 @@
 @0
-6f 00 40 00 93 01 20 00 93 00 00 00 13 01 00 00 33 87 20 00 93 03 00 00 63 10 77 4e 93 01 30 00 93 00 10 00 13 01 10 00 33 87 20 00 93 03 20 00 63 14 77 4c 93 01 40 00 93 00 30 00 13 01 70 00 33 87 20 00 93 03 a0 00 63 18 77 4a 93 01 50 00 93 00 00 00 37 81 ff ff 33 87 20 00 b7 83 ff ff 63 1c 77 48 93 01 60 00 b7 00 00 80 13 01 00 00 33 87 20 00 b7 03 00 80 63 10 77 48 93 01 70 00 b7 00 00 80 37 81 ff ff 33 87 20 00 b7 03 ff ff 9b 83 f3 ff 93 93 f3 00 63 10 77 46 93 01 80 00 93 00 00 00 37 81 00 00 1b 01 f1 ff 33 87 20 00 b7 83 00 00 9b 83 f3 ff 63 10 77 44 93 01 90 00 b7 00 00 80 9b 80 f0 ff 13 01 00 00 33 87 20 00 b7 03 00 80 9b 83 f3 ff 63 10 77 42 93 01 a0 00 b7 00 00 80 9b 80 f0 ff 37 81 00 00 1b 01 f1 ff 33 87 20 00 b7 03 01 00 9b 83 13 00 93 93 f3 00 93 83 e3 ff 63 1a 77 3e 93 01 b0 00 b7 00 00 80 37 81 00 00 1b 01 f1 ff 33 87 20 00 b7 83 00 80 9b 83 f3 ff 63 1a 77 3c 93 01 c0 00 b7 00 00 80 9b 80 f0 ff 37 81 ff ff 33 87 20 00 b7 83 ff 7f 9b 83 f3 ff 63 1a 77 3a 93 01 d0 00 93 00 00 00 13 01 f0 ff 33 87 20 00 93 03 f0 ff 63 1e 77 38 93 01 e0 00 93 00 f0 ff 13 01 10 00 33 87 20 00 93 03 00 00 63 12 77 38 93 01 f0 00 93 00 f0 ff 13 01 f0 ff 33 87 20 00 93 03 e0 ff 63 16 77 36 93 01 00 01 93 00 10 00 37 01 00 80 1b 01 f1 ff 33 87 20 00 9b 03 10 00 93 93 f3 01 63 16 77 34 93 01 10 01 93 00 d0 00 13 01 b0 00 b3 80 20 00 93 03 80 01 63 9a 70 32 93 01 20 01 93 00 e0 00 13 01 b0 00 33 81 20 00 93 03 90 01 63 1e 71 30 93 01 30 01 93 00 d0 00 b3 80 10 00 93 03 a0 01 63 94 70 30 93 01 40 01 13 02 00 00 93 00 d0 00 13 01 b0 00 33 87 20 00 13 03 07 00 13 02 12 00 93 02 20 00 e3 14 52 fe 93 03 80 01 63 1e 73 2c 93 01 50 01 13 02 00 00 93 00 e0 00 13 01 b0 00 33 87 20 00 13 00 00 00 13 03 07 00 13 02 12 00 93 02 20 00 e3 12 52 fe 93 03 90 01 63 16 73 2a 93 01 60 01 13 02 00 00 93 00 f0 00 13 01 b0 00 33 87 20 00 13 00 00 00 13 00 00 00 13 03 07 00 13 02 12 00 93 02 20 00 e3 10 52 fe 93 03 a0 01 63 1c 73 26 93 01 70 01 13 02 00 00 93 00 d0 00 13 01 b0 00 33 87 20 00 13 02 12 00 93 02 20 00 e3 16 52 fe 93 03 80 01 63 18 77 24 93 01 80 01 13 02 00 00 93 00 e0 00 13 01 b0 00 13 00 00 00 33 87 20 00 13 02 12 00 93 02 20 00 e3 14 52 fe 93 03 90 01 63 12 77 22 93 01 90 01 13 02 00 00 93 00 f0 00 13 01 b0 00 13 00 00 00 13 00 00 00 33 87 20 00 13 02 12 00 93 02 20 00 e3 12 52 fe 93 03 a0 01 63 1a 77 1e 93 01 a0 01 13 02 00 00 93 00 d0 00 13 00 00 00 13 01 b0 00 33 87 20 00 13 02 12 00 93 02 20 00 e3 14 52 fe 93 03 80 01 63 14 77 1c 93 01 b0 01 13 02 00 00 93 00 e0 00 13 00 00 00 13 01 b0 00 13 00 00 00 33 87 20 00 13 02 12 00 93 02 20 00 e3 12 52 fe 93 03 90 01 63 1c 77 18 93 01 c0 01 13 02 00 00 93 00 f0 00 13 00 00 00 13 00 00 00 13 01 b0 00 33 87 20 00 13 02 12 00 93 02 20 00 e3 12 52 fe 93 03 a0 01 63 14 77 16 93 01 d0 01 13 02 00 00 13 01 b0 00 93 00 d0 00 33 87 20 00 13 02 12 00 93 02 20 00 e3 16 52 fe 93 03 80 01 63 10 77 14 93 01 e0 01 13 02 00 00 13 01 b0 00 93 00 e0 00 13 00 00 00 33 87 20 00 13 02 12 00 93 02 20 00 e3 14 52 fe 93 03 90 01 63 1a 77 10 93 01 f0 01 13 02 00 00 13 01 b0 00 93 00 f0 00 13 00 00 00 13 00 00 00 33 87 20 00 13 02 12 00 93 02 20 00 e3 12 52 fe 93 03 a0 01 63 12 77 0e 93 01 00 02 13 02 00 00 13 01 b0 00 13 00 00 00 93 00 d0 00 33 87 20 00 13 02 12 00 93 02 20 00 e3 14 52 fe 93 03 80 01 63 1c 77 0a 93 01 10 02 13 02 00 00 13 01 b0 00 13 00 00 00 93 00 e0 00 13 00 00 00 33 87 20 00 13 02 12 00 93 02 20 00 e3 12 52 fe 93 03 90 01 63 14 77 08 93 01 20 02 13 02 00 00 13 01 b0 00 13 00 00 00 13 00 00 00 93 00 f0 00 33 87 20 00 13 02 12 00 93 02 20 00 e3 12 52 fe 93 03 a0 01 63 1c 77 04 93 01 30 02 93 00 f0 00 33 01 10 00 93 03 f0 00 63 12 71 04 93 01 40 02 93 00 00 02 33 81 00 00 93 03 00 02 63 18 71 02 93 01 50 02 b3 00 00 00 93 03 00 00 63 90 70 02 93 01 60 02 93 00 00 01 13 01 e0 01 33 80 20 00 93 03 00 00 63 14 70 00 63 1a 30 00 13 95 11 00 63 00 05 00 13 65 15 00 a3 0f a0 fe 13 05 10 00 a3 0f a0 fe 73 10 00 c0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
\ No newline at end of file
+93 00 00 00 37 01 20 00 6f 00 40 00 13 01 01 fc 23 3c 81 02 13 04 01 04 b7 07 10 00 93 87 07 0a 03 b7 07 00 23 34 e4 fc 03 a7 87 00 23 28 e4 fc 83 d7 c7 00 23 1a f4 fc b7 07 00 0e 93 87 37 10 93 97 47 00 23 30 f4 fe b7 07 00 38 93 87 b7 40 93 97 27 00 23 3c f4 fc 23 26 04 fe 6f 00 c0 02 83 27 c4 fe 93 87 07 ff b3 87 87 00 83 c7 87 fd 1b 87 07 00 83 37 04 fe 23 a0 e7 00 83 27 c4 fe 9b 87 17 00 23 26 f4 fe 83 27 c4 fe 1b 87 07 00 93 07 c0 00 e3 d6 e7 fc 6f f0 1f fc 00 00 00 00 48 65 6c 6c 6f 20 77 6f 72 6c 64 21 0a 00 
\ No newline at end of file
diff --git a/verilator-tests/testbench/programs/binary_to_text.c b/verilator-tests/testbench/programs/binary_to_text.c
new file mode 100644
index 0000000..75ada8f
--- /dev/null
+++ b/verilator-tests/testbench/programs/binary_to_text.c
@@ -0,0 +1,30 @@
+#include <stdio.h>
+
+int main(int argc, char* argv[]) {
+    if (argc < 3) {
+        printf("Usage: %s input_file output_file\n", argv[0]);
+        return 1;
+    }
+    
+    FILE* input_file = fopen(argv[1], "rb");
+    if (input_file == NULL) {
+        printf("Error opening input file\n");
+        return 1;
+    }
+    
+    FILE* output_file = fopen(argv[2], "w");
+    if (output_file == NULL) {
+        printf("Error opening output file\n");
+        fclose(input_file);
+        return 1;
+    }
+    
+    int byte;
+    while ((byte = fgetc(input_file)) != EOF) {
+        fprintf(output_file, "0x%02X,", byte);
+    }
+    
+    fclose(input_file);
+    fclose(output_file);
+    return 0;
+}
diff --git a/verilator-tests/testbench/programs/compile.sh b/verilator-tests/testbench/programs/compile.sh
new file mode 100644
index 0000000..46bbe91
--- /dev/null
+++ b/verilator-tests/testbench/programs/compile.sh
@@ -0,0 +1,12 @@
+#! /bin/sh
+rm -r build
+mkdir build
+cd build
+$1-gcc -march=rv64g ../hello.c -save-temps
+$1-as a-hello.s -o a-hello.o
+$1-as ../init.s -o init.o
+$1-ld -T../virt.ld init.o a-hello.o -o a-hello
+$1-objcopy -O binary a-hello a-hello.bin
+$1-objdump -D a-hello > a.hello.dump
+gcc ../binary_to_text.c -o binary_to_text
+./binary_to_text a-hello.bin a-hello.txt
diff --git a/verilator-tests/testbench/programs/hello.c b/verilator-tests/testbench/programs/hello.c
new file mode 100644
index 0000000..d1fecc5
--- /dev/null
+++ b/verilator-tests/testbench/programs/hello.c
@@ -0,0 +1,15 @@
+int main()
+{
+  char prompt[] = "Hello world!\n";
+  int *uart = 0xe0001030;
+  int *uart_status = 0xe000102c;
+  
+  while(1) {
+    while(!((*uart_status)&8))
+      ;
+
+    for(int i = 0; i < 13; i++)
+      *uart = (int) prompt[i];
+  }
+  return 0;
+}
\ No newline at end of file
diff --git a/verilator-tests/testbench/programs/init.s b/verilator-tests/testbench/programs/init.s
new file mode 100644
index 0000000..5eed1d9
--- /dev/null
+++ b/verilator-tests/testbench/programs/init.s
@@ -0,0 +1,4 @@
+_start:
+li ra, 0
+li sp, 0x00200000
+j main
diff --git a/verilator-tests/testbench/programs/virt.ld b/verilator-tests/testbench/programs/virt.ld
new file mode 100644
index 0000000..e0d968c
--- /dev/null
+++ b/verilator-tests/testbench/programs/virt.ld
@@ -0,0 +1,5 @@
+SECTIONS
+{
+  . = 0x00100000;
+  .text : { *(.text) }
+}
diff --git a/verilator-tests/testbench/test-run.sh b/verilator-tests/testbench/test-run.sh
index 46373d4..66640bb 100755
--- a/verilator-tests/testbench/test-run.sh
+++ b/verilator-tests/testbench/test-run.sh
@@ -32,4 +32,4 @@ g++ -I /usr/share/verilator/include -I obj_dir /usr/share/verilator/include/veri
 
 ./testbench
 
-gtkwave testbench_trace.vcd
\ No newline at end of file
+#gtkwave testbench_trace.vcd
\ No newline at end of file
diff --git a/verilator-tests/testbench/testbenchtest.cpp b/verilator-tests/testbench/testbenchtest.cpp
index a15c685..d49bfab 100644
--- a/verilator-tests/testbench/testbenchtest.cpp
+++ b/verilator-tests/testbench/testbenchtest.cpp
@@ -35,61 +35,69 @@ int main(int argc, char **argv){
 
 	// Call commandArgs first!
 	Verilated::commandArgs(argc, argv);
+
+	//vector<string> tests;
+	ifstream infile("tests.txt");
 	
-	//Instantiate our design
-	Vtestbench *tb = new Vtestbench;
-	
-	Verilated::traceEverOn(true);
-	VerilatedVcdC* tfp = new VerilatedVcdC;
-	tb->trace(tfp, 99);
-	tfp->open("testbench_trace.vcd");
-	
-	tb -> reset = 0;
-	for(int i = 0; i < 5; i++){
-		tick(++tickcount, tb, tfp);
-	}
+	string test;
 
-	tb -> reset = 1;
-	tb -> programRunning = 0;
-	tb -> programLoader_valid = 0;
-	for(int i = 0; i < 8; i++){
-		tick(++tickcount, tb, tfp);
-	}
+	while (getline(infile, test)) {
+		//Instantiate our design
+		Vtestbench *tb = new Vtestbench;
+		
+		Verilated::traceEverOn(true);
+		VerilatedVcdC* tfp = new VerilatedVcdC;
+		tb->trace(tfp, 99);
+		tfp->open(("waveforms/wavefrom_" + test + ".vcd").c_str());
+		
+		tb -> reset = 0;
+		for(int i = 0; i < 5; i++){
+			tick(++tickcount, tb, tfp);
+		}
 
-	tb -> reset = 0;
-	for(int i = 0; i < 5; i++){
-		tick(++tickcount, tb, tfp);
-	}
+		tb -> reset = 1;
+		tb -> programRunning = 0;
+		tb -> programLoader_valid = 0;
+		for(int i = 0; i < 8; i++){
+			tick(++tickcount, tb, tfp);
+		}
 
-	ifstream input("add.text", ios::binary);
+		tb -> reset = 0;
+		for(int i = 0; i < 5; i++){
+			tick(++tickcount, tb, tfp);
+		}
 
-	vector<unsigned char> buffer(istreambuf_iterator<char>(input), {});
+		ifstream input(("target_texts/" + test + ".text"), ios::binary);
+		printf("Running test for %s: ", test.c_str());
 
-	//cout << buffer.size() << endl;
-	tb -> programLoader_valid = 1;
-	for (int i = 0; i < buffer.size(); i++) {
-		tb -> programLoader_byte = buffer.at(i);
-		//cout << buffer.at(i)&255 << endl;
-		tick(++tickcount, tb, tfp);
-	}
-	tb -> programLoader_valid = 0;
-	tb -> programRunning = 1;
-	for(int i = 0; i < 4000; i++){
-		if(tb -> results_valid) {
-			if(tb -> results_result == 1) {
-				printf("Test successful \n");
-			}else {
-				printf("Program failed at: %d \n", (tb -> results_result) >> 1);
-			}
-			// finishing the last store operation
-			for (int i = 0; i < 100; i++) {
-				tick(++tickcount, tb, tfp);
+		vector<unsigned char> buffer(istreambuf_iterator<char>(input), {});
+
+		//cout << buffer.size() << endl;
+		tb -> programLoader_valid = 1;
+		for (int i = 0; i < buffer.size(); i++) {
+			tb -> programLoader_byte = buffer.at(i);
+			//cout << buffer.at(i)&255 << endl;
+			tick(++tickcount, tb, tfp);
+		}
+		tb -> programLoader_valid = 0;
+		tb -> programRunning = 1;
+		for(int i = 0; i < 5000; i++){
+			if(tb -> results_valid) {
+				if(tb -> results_result == 1) {
+					printf("Test successful \n");
+				}else {
+					printf("Program failed at: %d \n", (tb -> results_result) >> 1);
+				}
+				// finishing the last store operation
+				/* for (int i = 0; i < 100; i++) {
+					tick(++tickcount, tb, tfp);
+				} */
+				break;
 			}
-			return 0;
+			tick(++tickcount, tb, tfp);
 		}
-		tick(++tickcount, tb, tfp);
+		if (tb -> results_result == 0)
+			printf("Timeout\n");
 	}
-
-	printf("Timeout\n");
 }
 
diff --git a/verilator-tests/testbench/tests.txt b/verilator-tests/testbench/tests.txt
new file mode 100644
index 0000000..1219ce1
--- /dev/null
+++ b/verilator-tests/testbench/tests.txt
@@ -0,0 +1,68 @@
+addi
+addiw
+add
+addw
+andi
+and
+auipc
+beq
+bge
+bgeu
+blt
+bltu
+bne
+jalr
+jal
+lb
+lbu
+ld
+lh
+lhu
+lui
+lw
+lwu
+ori
+or
+sb
+sd
+sh
+slli
+slliw
+sll
+sllw
+slti
+sltiu
+slt
+sltu
+srai
+sraiw
+sra
+sraw
+srli
+srliw
+srl
+srlw
+sub
+subw
+sw
+xori
+xor
+a-amoadd_d
+a-amoadd_w
+a-amoand_d
+a-amoand_w
+a-amomax_d
+a-amomaxu_d
+a-amomaxu_w
+a-amomax_w
+a-amomin_d
+a-amominu_d
+a-amominu_w
+a-amomin_w
+a-amoor_d
+a-amoor_w
+a-amoswap_d
+a-amoswap_w
+a-amoxor_d
+a-amoxor_w
+a-lrsc
\ No newline at end of file
diff --git a/verilog_srcs/dCacheRegisters.v b/verilog_srcs/dCacheRegisters.v
new file mode 100644
index 0000000..8589457
--- /dev/null
+++ b/verilog_srcs/dCacheRegisters.v
@@ -0,0 +1,80 @@
+module dCacheRegisters #(
+  parameter double_word_offset_width = 3, // 2^double_word_offset_width of double words per block
+  parameter line_width = 6, // 2^line_wdith of cache lines per set
+  localparam tag_width = 32 - double_word_offset_width -3 - line_width, //  
+  localparam cache_depth = 1 << line_width,
+  localparam block_size = 1 << double_word_offset_width // double words per block
+) (
+  input [31:0] address,
+  output [63:0] byte_aligned_data,
+  output [tag_width-1: 0] tag,
+  output reg tag_valid,
+  input [line_width-1:0] write_line_index,
+  input [64*block_size - 1:0] write_block,
+  input [tag_width-1: 0] write_tag,
+  input [block_size-1:0] write_mask,
+  input reset, write_in, clock
+);
+    wire [127:0] read_out;
+    wire [63:0] wea = write_in ? { {8{write_mask[7]}}, {8{write_mask[6]}}, {8{write_mask[5]}}, {8{write_mask[4]}}, {8{write_mask[3]}}, {8{write_mask[2]}}, {8{write_mask[1]}}, {8{write_mask[0]}}} : 64'b0;
+    reg old_address_3;
+    
+    always@(posedge clock)
+        old_address_3 <= address[3];
+
+    blk_d_cache d_cache(
+    .clka(clock),
+    .wea(wea),
+    .addra(write_line_index),
+    .dina(write_block),
+    .clkb(clock),
+    .addrb(address[11:4]),
+    .doutb(read_out)
+  );
+  
+  //assign byte_aligned_data = address[3] ? read_out[127:64] : read_out[63:0];
+  assign byte_aligned_data = old_address_3 ? read_out[127:64] : read_out[63:0];
+  
+  blk_d_cache_tags d_cache_tags(
+      .clka(clock),
+      .wea(write_in),
+      .addra(write_line_index),
+      .dina(write_tag),
+      .clkb(clock),
+      .addrb(address[11:6]),
+      .doutb(tag)
+    );
+    
+    reg [63:0] valid_bits;
+    always@(posedge clock) begin
+        if (reset) valid_bits <= 64'b0;
+        else if (write_in) valid_bits[write_line_index] <= 1'b1;
+        tag_valid <= valid_bits[address[11:6]];
+    end
+//  reg [63:0] cache [cache_depth-1:0][block_size-1:0];
+//  reg [tag_width-1:0] tags [cache_depth-1:0];
+//  reg validBits [cache_depth-1:0];
+
+//  assign byte_aligned_data = cache[address[line_width+double_word_offset_width+3-1:double_word_offset_width+3]][address[double_word_offset_width-1 + 3:3]];
+//  assign tag = tags[address[line_width+double_word_offset_width+3-1:double_word_offset_width+3]];
+//  assign tag_valid = validBits[address[line_width+double_word_offset_width+3-1:double_word_offset_width+3]];
+
+//    integer i, j;
+//  always @(posedge clock) begin
+//    if (reset) begin
+//      for (i = 0; i < cache_depth; i=i+1) begin
+//        validBits[i] <= 1'b0;
+//      end
+//    end else if (write_in) begin
+//      // partial writes only occur for blocks already in cache
+//      for (j = 0; j < block_size; j=j+1) begin
+//        if (write_mask[j])begin
+//          cache[write_line_index][j] <= write_block[64*j +: 64];
+//        end
+//      end
+//      validBits[write_line_index] <= 1'b1;
+//      tags[write_line_index] <= write_tag;
+//    end
+//  end
+
+endmodule
\ No newline at end of file
diff --git a/verilog_srcs/iCacheRegisters.v b/verilog_srcs/iCacheRegisters.v
new file mode 100644
index 0000000..78c3ba1
--- /dev/null
+++ b/verilog_srcs/iCacheRegisters.v
@@ -0,0 +1,67 @@
+module iCacheRegisters #(
+  parameter offset_width = 2, // 2^offset_width of instructions per block
+  parameter line_width = 6, // 2^line_width of cache lines per set
+  localparam tag_width = 32 - offset_width - line_width - 2, //  
+  localparam cache_depth = 1 << line_width,
+  localparam block_size = 1 << offset_width
+) (
+  input [31:0] address,
+  output [31:0] instruction,
+  output [tag_width-1: 0] tag,
+  output reg tag_valid,
+  input [line_width-1:0] write_line_index,
+  input [32*block_size - 1:0] write_block,
+  input [tag_width-1: 0] write_tag,
+  input reset, write_in, clock, invalidate_all
+);
+
+  blk_mem_gen_0 i_cache(
+    .clka(clock),
+    .wea(write_in),
+    .addra(write_line_index),
+    .dina(write_block),
+    .clkb(clock),
+    .addrb(address[9:2]),
+    .doutb(instruction)
+  );
+  
+  blk_i_cache_tags i_cache_tags(
+      .clka(clock),
+      .wea(write_in),
+      .addra(write_line_index),
+      .dina(write_tag),
+      .clkb(clock),
+      .addrb(address[9:4]),
+      .doutb(tag)
+    );
+    
+    reg [63:0] valid_bits;
+        always@(posedge clock)
+            if (reset || invalidate_all) valid_bits <= 64'b0;
+            else if (write_in) valid_bits[write_line_index] <= 1'b1;
+            
+    always@(posedge clock) tag_valid <= valid_bits[address[9:4]];
+
+//  reg [31:0] cache [cache_depth-1:0][block_size-1:0];
+//  reg [tag_width-1:0] tags [cache_depth-1:0];
+//  reg validBits [cache_depth-1:0];
+
+//  assign instruction = cache[address[line_width+offset_width+2-1:offset_width+2]][address[offset_width+2-1:2]];
+//  assign tag = tags[address[line_width+offset_width+2-1:offset_width+2]];
+//  assign tag_valid = validBits[address[line_width+offset_width+2-1:offset_width+2]];
+//    integer i, j;
+//  always @(posedge clock) begin
+//    if (reset || invalidate_all) begin
+//      for (i = 0; i < cache_depth; i=i+1) begin
+//        validBits[i] <= 1'b0;
+//      end
+//    end else if (write_in) begin
+//      for (j = 0; j < block_size; j=j+1) begin
+//        cache[write_line_index][j] <= write_block[32*j +: 32];
+//      end
+//      validBits[write_line_index] <= 1'b1;
+//      tags[write_line_index] <= write_tag;
+//    end
+//  end
+
+endmodule
\ No newline at end of file
diff --git a/verilog_srcs/tb.v b/verilog_srcs/tb.v
new file mode 100644
index 0000000..70589a2
--- /dev/null
+++ b/verilog_srcs/tb.v
@@ -0,0 +1,75 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 04/10/2023 09:10:21 AM
+// Design Name: 
+// Module Name: tb
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module tb();
+    // clock and resets
+    reg clock, reset;
+    reg        programLoader_valid;
+    //wire  [7:0] programLoader_byte;
+    reg        programRunning;
+    wire       results_valid;
+    wire [7:0] results_result;
+    
+    reg [7:0] mem [0:1930];
+    
+    initial begin
+        $readmemh("/mnt/AE06F37906F3413F/University/GitHub/FYP-18-RISCV-Core/verilator-tests/testbench/output.hex", mem); // read bytes from file and store in register array
+    end
+    
+    reg [11:0] mem_index;
+    wire [7:0] programLoader_byte = mem[mem_index];
+    
+    initial begin
+        clock = 1'b0;
+        forever #5 clock = ~clock;
+    end
+    
+    testbench testbench_0(
+        .clock(clock),
+        .reset(reset),
+        .programLoader_valid(programLoader_valid),
+        .programLoader_byte(programLoader_byte),
+        .programRunning(programRunning),
+        .results_valid(results_valid),
+        .results_result(results_result)
+    );
+    
+    initial begin
+        $dumpfile("dump.vcd"); $dumpvars(0, testbench_0);
+        reset = 1'b0;
+        programLoader_valid = 1'b0;
+        mem_index = 12'd0;
+        programRunning = 1'b0;
+        repeat(5)@(posedge clock);
+        #5 reset = 1'b1;
+        repeat(8)@(posedge clock);
+        #5 reset = 1'b0;
+        repeat(1)@(posedge clock);
+        #5 programLoader_valid = 1'b1;
+        repeat(1930) #10 mem_index = mem_index + 1;
+        #5 programLoader_valid = 1'b0;
+        repeat(5)@(posedge clock);
+        #1 programRunning = 1'b1;
+        repeat(5000)@(posedge clock);
+        #1 programRunning = 1'b0;
+    end
+endmodule