diff --git a/Makefile b/Makefile index 85c26f4dd..442d9fe50 100644 --- a/Makefile +++ b/Makefile @@ -83,7 +83,7 @@ occamy_system_download_sw: # In ESAT Server; this procedure will only inject the make -C ./target/fpga/sw download_sw open_terminal: # It opens ttyUSB1 without locking it, and set baudrate at 1Mbps - $(shell minicom -D /dev/ttyUSB1 -b 1000000 -o) + $(info "shell minicom -D /dev/ttyUSB1 -b 1000000 -o") # FPGA Workflow (with no Xilinx IP - tapeout configuration) # Please be attention that in this configuration, injecting any binary files by Xilinx Vivado are not possible anymore; please use JTAG or embedded bootrom to load the binary diff --git a/target/fpga/openocd_configs/digilent-HS2.cfg b/target/fpga/openocd_configs/digilent-HS2.cfg deleted file mode 100644 index 6eb33ca35..000000000 --- a/target/fpga/openocd_configs/digilent-HS2.cfg +++ /dev/null @@ -1,33 +0,0 @@ -# Copyright 2021 ETH Zurich and University of Bologna. -# Solderpad Hardware License, Version 0.51, see LICENSE for details. -# SPDX-License-Identifier: SHL-0.51 - -adapter driver ftdi -adapter speed 2000 -transport select jtag - -# FTF232 -ftdi_vid_pid 0x0403 0x6014 -# If more than one FTDI is connected we -# can use the serial to differentiate. -ftdi_channel 0 -ftdi_serial 210249AEC334 -ftdi_layout_init 0x00e8 0x60eb - -set _CHIPNAME riscv -jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20002001 - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME riscv -chain-position $_TARGETNAME - -riscv set_ir idcode 0x9249 -riscv set_ir dtmcs 0x22924 -riscv set_ir dmi 0x23924 - -# Try enabling address translation (only works for newer versions) -#if { [catch {riscv set_enable_virtual on} ] } { -# echo "Warning: This version of OpenOCD does not support address translation. To debug on virtual addresses, please update to the latest version." } - -telnet_port disabled -tcl_port disabled -gdb_port 3334 \ No newline at end of file diff --git a/target/fpga/openocd_configs/vcu128-1.cfg b/target/fpga/openocd_configs/vcu128-1.cfg deleted file mode 100644 index fcd01dbcd..000000000 --- a/target/fpga/openocd_configs/vcu128-1.cfg +++ /dev/null @@ -1,33 +0,0 @@ -# Copyright 2021 ETH Zurich and University of Bologna. -# Solderpad Hardware License, Version 0.51, see LICENSE for details. -# SPDX-License-Identifier: SHL-0.51 - -adapter driver ftdi -adapter speed 2000 -transport select jtag - -# FTF232 -ftdi_vid_pid 0x0403 0x6011 -# If more than one FTDI is connected we -# can use the serial to differentiate. -ftdi_serial 091847100576 -ftdi_layout_init 0x0008 0x05eb - - -set _CHIPNAME riscv -jtag newtap $_CHIPNAME cpu -irlen 18 -expected-id 0x14B79093 - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME riscv -chain-position $_TARGETNAME - -riscv set_ir idcode 0x9249 -riscv set_ir dtmcs 0x22924 -riscv set_ir dmi 0x23924 - -# Try enabling address translation (only works for newer versions) -#if { [catch {riscv set_enable_virtual on} ] } { -# echo "Warning: This version of OpenOCD does not support address translation. To debug on virtual addresses, please update to the latest version." } - -telnet_port disabled -tcl_port disabled -gdb_port 3334 \ No newline at end of file diff --git a/target/fpga/openocd_configs/vcu128-2.cfg b/target/fpga/openocd_configs/vcu128-2.cfg deleted file mode 100644 index b5c566fd5..000000000 --- a/target/fpga/openocd_configs/vcu128-2.cfg +++ /dev/null @@ -1,33 +0,0 @@ -# Copyright 2021 ETH Zurich and University of Bologna. -# Solderpad Hardware License, Version 0.51, see LICENSE for details. -# SPDX-License-Identifier: SHL-0.51 - -adapter driver ftdi -adapter speed 2000 -transport select jtag - -# FTF232 -ftdi_vid_pid 0x0403 0x6011 -# If more than one FTDI is connected we -# can use the serial to differentiate. -ftdi_serial 091847100638 -ftdi_layout_init 0x0008 0x05eb - - -set _CHIPNAME riscv -jtag newtap $_CHIPNAME cpu -irlen 18 -expected-id 0x14B79093 - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME riscv -chain-position $_TARGETNAME - -riscv set_ir idcode 0x9249 -riscv set_ir dtmcs 0x22924 -riscv set_ir dmi 0x23924 - -# Try enabling address translation (only works for newer versions) -#if { [catch {riscv set_enable_virtual on} ] } { -# echo "Warning: This version of OpenOCD does not support address translation. To debug on virtual addresses, please update to the latest version." } - -telnet_port disabled -tcl_port disabled -gdb_port 3334 \ No newline at end of file diff --git a/target/fpga/sw/Makefile b/target/fpga/sw/Makefile index a95484f95..9be869d94 100644 --- a/target/fpga/sw/Makefile +++ b/target/fpga/sw/Makefile @@ -10,6 +10,12 @@ APP ?= $(TARGET)/sim/sw/host/apps/hello_world/build/hello_world.elf BIN2JTAG ?= $(ROOT)/util/bin2jtag.py BIN_VERIFY ?= $(ROOT)/util/bin2jtag_only_verify.py +CVA6_GCC_ROOT = /tools/riscv/bin +RISCV_CC = $(CVA6_GCC_ROOT)/riscv64-unknown-elf-gcc +RISCV_OBJCOPY = $(CVA6_GCC_ROOT)/riscv64-unknown-elf-objcopy +RISCV_OBJDUMP = $(CVA6_GCC_ROOT)/riscv64-unknown-elf-objdump +RISCV_READELF = $(CVA6_GCC_ROOT)/riscv64-unknown-elf-readelf + .PHONY: sw download_sw clean verify_sw sw: bootrom.tcl app.tcl app_verify.tcl @@ -21,7 +27,7 @@ bootrom.tcl: $(BOOTROM) $(BIN2JTAG) -c32 -b 0 -d hw_axi_1 $< > $@ app.bin: - riscv64-unknown-elf-objcopy -O binary $(APP) $@ + $(RISCV_OBJCOPY) -O binary $(APP) $@ app.tcl: app.bin $(BIN2JTAG) -c32 -b 80000000 -d hw_axi_2 $< > $@ diff --git a/target/fpga/sw/send_uart.sh b/target/fpga/sw/send_uart.sh index 902660cb6..1e88a21a7 100755 --- a/target/fpga/sw/send_uart.sh +++ b/target/fpga/sw/send_uart.sh @@ -11,10 +11,10 @@ else FILE=$1 fi - stty -F /dev/ttyUSB1 cs8 1000000 ignbrk -brkint -imaxbel -opost -onlcr -isig -icanon -iexten -echo -echoe -echok -echoctl -echoke noflsh -ixon crtscts + stty -F /dev/ttyUSB3 cs8 1000000 ignbrk -brkint -imaxbel -opost -onlcr -isig -icanon -iexten -echo -echoe -echok -echoctl -echoke noflsh -ixon crtscts - echo -n 2 > /dev/ttyUSB1 + echo -n 2 > /dev/ttyUSB3 - sx -k "$FILE" < /dev/ttyUSB1 > /dev/ttyUSB1 + sx -k "$FILE" < /dev/ttyUSB3 > /dev/ttyUSB3 fi diff --git a/target/fpga_chip/jtag/app/Makefile b/target/fpga_chip/jtag/app/Makefile new file mode 100644 index 000000000..90db14fab --- /dev/null +++ b/target/fpga_chip/jtag/app/Makefile @@ -0,0 +1,23 @@ +MKFILE_PATH := $(abspath $(lastword $(MAKEFILE_LIST))) +MKFILE_DIR := $(dir $(MKFILE_PATH)) +TARGET := $(MKFILE_DIR)../../.. +ROOT := ${MKFILE_DIR}../../../.. + +APP ?= $(TARGET)/sim/sw/host/apps/hello_world/build/hello_world.elf + +CVA6_GCC_ROOT = /tools/riscv/bin +RISCV_CC = $(CVA6_GCC_ROOT)/riscv64-unknown-elf-gcc +RISCV_OBJCOPY = $(CVA6_GCC_ROOT)/riscv64-unknown-elf-objcopy +RISCV_OBJDUMP = $(CVA6_GCC_ROOT)/riscv64-unknown-elf-objdump +RISCV_READELF = $(CVA6_GCC_ROOT)/riscv64-unknown-elf-readelf + +.PHONY: download_sw + +app.bin: + $(RISCV_OBJCOPY) -O binary $(APP) $@ + +download_sw: + ${VIVADO} -mode batch -source download_sw.tcl + +clean: + @rm -f app.bin diff --git a/target/fpga_chip/jtag/openocd_configs/download_bin.cfg b/target/fpga_chip/jtag/openocd_configs/download_bin.cfg new file mode 100644 index 000000000..d29c1f567 --- /dev/null +++ b/target/fpga_chip/jtag/openocd_configs/download_bin.cfg @@ -0,0 +1 @@ +load_image /users/micas/ydeng/Desktop/SNAX/HeMAiA/target/fpga_chip/jtag/app/app.bin 0x80000000 diff --git a/target/fpga_chip/jtag/openocd_configs/hemaia_vcu128.cfg b/target/fpga_chip/jtag/openocd_configs/hemaia_vcu128.cfg new file mode 100644 index 000000000..c9cf6945b --- /dev/null +++ b/target/fpga_chip/jtag/openocd_configs/hemaia_vcu128.cfg @@ -0,0 +1,27 @@ +# Copyright 2021 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 + +adapter driver ftdi +adapter speed 2000 +transport select jtag + +# FT4232 +ftdi vid_pid 0x0403 0x6011 +adapter serial FT80Z5JA +ftdi layout_init 0x0808 0x0b0b +ftdi channel 1 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20002001 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME + +riscv.cpu riscv set_ir idcode 0x9249 +# riscv.cpu riscv set_ir dtmcs 0x22924 +# riscv.cpu riscv set_ir dmi 0x23924 + +tcl port disabled +gdb port 3334 +telnet_port 4444 diff --git a/target/fpga_chip/jtag/openocd_configs/hemaia_vpk180.cfg b/target/fpga_chip/jtag/openocd_configs/hemaia_vpk180.cfg new file mode 100644 index 000000000..5238f0f39 --- /dev/null +++ b/target/fpga_chip/jtag/openocd_configs/hemaia_vpk180.cfg @@ -0,0 +1,27 @@ +# Copyright 2021 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 + +adapter driver ftdi +adapter speed 2000 +transport select jtag + +# FT4232 +ftdi vid_pid 0x0403 0x6011 +adapter serial FT80Z5JA +ftdi layout_init 0x0808 0x0b0b +ftdi channel 0 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20002001 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME + +riscv.cpu riscv set_ir idcode 0x9249 +# riscv.cpu riscv set_ir dtmcs 0x22924 +# riscv.cpu riscv set_ir dmi 0x23924 + +tcl port disabled +gdb port 3334 +telnet_port 4444