From 71556eef9ca990b9bb06ad3b767d2854c754ce0e Mon Sep 17 00:00:00 2001 From: Yunhao Deng Date: Wed, 28 Aug 2024 19:45:36 +0200 Subject: [PATCH] Floating address on quadrant + remove snitch's tlb + remove inter-quadrant xbar (#22) * Remove tile_id; add chip_id in the occamy_pkg * Bug Fix * Bug Fix * Floating address for quadrant * Disable TLB inside quadrant * Remove inter-quadrant xbar --- hw/occamy/occamy_pkg.sv.tpl | 4 +- hw/occamy/occamy_quadrant_s1.sv.tpl | 25 ++--- hw/occamy/occamy_quadrant_s1_ctrl.sv.tpl | 9 +- hw/occamy/occamy_soc.sv.tpl | 28 ++---- .../occamy_quadrant_s1_reg.hjson.tpl | 5 +- .../cfg/cluster_cfg/snax_KUL_cluster.hjson | 2 +- .../cluster_cfg/snax_KUL_xdma_cluster.hjson | 2 +- .../cluster_cfg/snax_minimal_cluster.hjson | 2 +- .../cfg/cluster_cfg/snax_xdma_cluster.hjson | 2 +- .../cfg/occamy_cfg/snax_two_clusters.hjson | 38 ++++---- .../sim/sw/device/runtime/src/putchar_chip.c | 2 +- util/occamygen/occamygen.py | 95 +++++++------------ 12 files changed, 89 insertions(+), 125 deletions(-) diff --git a/hw/occamy/occamy_pkg.sv.tpl b/hw/occamy/occamy_pkg.sv.tpl index f113d6e02..8106e107c 100644 --- a/hw/occamy/occamy_pkg.sv.tpl +++ b/hw/occamy/occamy_pkg.sv.tpl @@ -97,7 +97,9 @@ package ${name}_pkg; localparam logic [15:0] PartNum = 2; localparam logic [31:0] IDCode = (dm::DbgVersion013 << 28) | (PartNum << 12) | 32'h1; - typedef logic [5:0] tile_id_t; + + localparam int unsigned ChipIdWidth = ${hemaia_multichip["chip_id_width"]}; + typedef logic [ChipIdWidth-1:0] chip_id_t; typedef logic [AddrWidth-1:0] addr_t; typedef logic [NarrowUserWidth-1:0] user_narrow_t; diff --git a/hw/occamy/occamy_quadrant_s1.sv.tpl b/hw/occamy/occamy_quadrant_s1.sv.tpl index 30b5200e9..ffeb5a443 100644 --- a/hw/occamy/occamy_quadrant_s1.sv.tpl +++ b/hw/occamy/occamy_quadrant_s1.sv.tpl @@ -35,7 +35,7 @@ module ${name}_quadrant_s1 input logic clk_i, input logic rst_ni, input logic test_mode_i, - input tile_id_t tile_id_i, + input chip_id_t chip_id_i, input logic [NrCoresS1Quadrant-1:0] meip_i, input logic [NrCoresS1Quadrant-1:0] mtip_i, input logic [NrCoresS1Quadrant-1:0] msip_i, @@ -44,18 +44,21 @@ module ${name}_quadrant_s1 input ${soc_narrow_xbar.in_s1_quadrant_0.rsp_type()} quadrant_narrow_out_rsp_i, input ${soc_narrow_xbar.out_s1_quadrant_0.req_type()} quadrant_narrow_in_req_i, output ${soc_narrow_xbar.out_s1_quadrant_0.rsp_type()} quadrant_narrow_in_rsp_o, - output ${quadrant_inter_xbar.in_quadrant_0.req_type()} quadrant_wide_out_req_o, - input ${quadrant_inter_xbar.in_quadrant_0.rsp_type()} quadrant_wide_out_rsp_i, - input ${quadrant_inter_xbar.out_quadrant_0.req_type()} quadrant_wide_in_req_i, - output ${quadrant_inter_xbar.out_quadrant_0.rsp_type()} quadrant_wide_in_rsp_o, + output ${soc_wide_xbar.in_quadrant_0.req_type()} quadrant_wide_out_req_o, + input ${soc_wide_xbar.in_quadrant_0.rsp_type()} quadrant_wide_out_rsp_i, + input ${soc_wide_xbar.out_quadrant_0.req_type()} quadrant_wide_in_req_i, + output ${soc_wide_xbar.out_quadrant_0.rsp_type()} quadrant_wide_in_rsp_o, // SRAM configuration input sram_cfg_quadrant_t sram_cfg_i ); // Calculate cluster base address based on `tile id`. + addr_t cluster_base_offset; + assign cluster_base_offset = {chip_id_i, ClusterBaseOffset[AddrWidth-ChipIdWidth-1:0]}; + addr_t [${nr_clusters-1}:0] cluster_base_addr; % for i in range(nr_clusters): - assign cluster_base_addr[${i}] = ClusterBaseOffset + tile_id_i * NrClustersS1Quadrant * ClusterAddressSpace + ${i} * ClusterAddressSpace; + assign cluster_base_addr[${i}] = cluster_base_offset + ${i} * ClusterAddressSpace; %endfor // Define types for IOTLBs @@ -65,7 +68,7 @@ module ${name}_quadrant_s1 logic clk_quadrant, rst_quadrant_n; logic [3:0] isolate, isolated; logic ro_enable, ro_flush_valid, ro_flush_ready; - logic [${ro_cache_regions-1}:0][${quadrant_inter_xbar.in_quadrant_0.aw-1}:0] ro_start_addr, ro_end_addr; + logic [${ro_cache_regions-1}:0][${soc_wide_xbar.in_quadrant_0.aw-1}:0] ro_start_addr, ro_end_addr; %if narrow_tlb_cfg: logic narrow_tlb_enable; tlb_entry_t [${narrow_tlb_entries-1}:0] narrow_tlb_entries; @@ -154,7 +157,7 @@ module ${name}_quadrant_s1 .isolate(context, "isolate[3]", "wide_cluster_out_isolate", isolated="isolated[3]", atop_support=False, to_clk="clk_i", to_rst="rst_ni", use_to_clk_rst=True, num_pending=wide_trans) \ .cut(context, cuts_wideiwc_with_wideout) #// Assert correct outgoing ID widths - assert quadrant_inter_xbar.in_quadrant_0.iw == wide_cluster_out_cut.iw, "S1 Quadrant and SoC IW mismatches." + assert soc_wide_xbar.in_quadrant_0.iw == wide_cluster_out_cut.iw, "S1 Quadrant and SoC IW mismatches." %> assign quadrant_wide_out_req_o = ${wide_cluster_out_cut.req_name()}; @@ -164,7 +167,7 @@ module ${name}_quadrant_s1 // Wide In + IW Converter // //////////////////////////// <% - quadrant_inter_xbar.out_quadrant_0 \ + soc_wide_xbar.out_quadrant_0 \ .copy(name="wide_cluster_in_iwc") \ .declare(context) \ .cut(context, cuts_wideiwc_with_wideout) \ @@ -185,7 +188,7 @@ module ${name}_quadrant_s1 .clk_i, .rst_ni, .test_mode_i, - .tile_id_i, + .chip_id_i, .clk_quadrant_o (clk_quadrant), .rst_quadrant_no (rst_quadrant_n), .isolate_o (isolate), @@ -228,7 +231,7 @@ module ${name}_quadrant_s1 %> logic [9:0] hart_base_id_${i}; - assign hart_base_id_${i} = HartIdOffset + tile_id_i * NrCoresS1Quadrant + NrCoresClusterOffset[${i}]; + assign hart_base_id_${i} = HartIdOffset + NrCoresClusterOffset[${i}]; ${cluster_name}_wrapper i_${name}_cluster_${i} ( .clk_i (clk_quadrant), diff --git a/hw/occamy/occamy_quadrant_s1_ctrl.sv.tpl b/hw/occamy/occamy_quadrant_s1_ctrl.sv.tpl index 8d4e5e12c..a38f58d97 100644 --- a/hw/occamy/occamy_quadrant_s1_ctrl.sv.tpl +++ b/hw/occamy/occamy_quadrant_s1_ctrl.sv.tpl @@ -19,8 +19,7 @@ module ${name}_quadrant_s1_ctrl input logic clk_i, input logic rst_ni, input logic test_mode_i, - - input tile_id_t tile_id_i, + input chip_id_t chip_id_i, // Quadrant clock and reset output logic clk_quadrant_o, @@ -33,8 +32,8 @@ module ${name}_quadrant_s1_ctrl output logic ro_flush_valid_o, input logic ro_flush_ready_i, - output logic [${ro_cache_regions-1}:0][${quadrant_inter_xbar.in_quadrant_0.aw-1}:0] ro_start_addr_o, - output logic [${ro_cache_regions-1}:0][${quadrant_inter_xbar.in_quadrant_0.aw-1}:0] ro_end_addr_o, + output logic [${ro_cache_regions-1}:0][${soc_wide_xbar.in_quadrant_0.aw-1}:0] ro_start_addr_o, + output logic [${ro_cache_regions-1}:0][${soc_wide_xbar.in_quadrant_0.aw-1}:0] ro_end_addr_o, // Upward (SoC) narrow ports output ${soc_narrow_xbar.in_s1_quadrant_0.req_type()} soc_out_req_o, @@ -61,7 +60,7 @@ module ${name}_quadrant_s1_ctrl // Upper half of quadrant space reserved for internal use (same size as for all clusters) addr_t [0:0] internal_xbar_base_addr; - assign internal_xbar_base_addr = '{S1QuadrantCfgBaseOffset + tile_id_i * S1QuadrantCfgAddressSpace}; + assign internal_xbar_base_addr = {chip_id_i, S1QuadrantCfgBaseOffset[AddrWidth-ChipIdWidth-1:0]}; // Controller crossbar: shims off for access to internal space ${module} diff --git a/hw/occamy/occamy_soc.sv.tpl b/hw/occamy/occamy_soc.sv.tpl index 75cedf88f..aaf530596 100644 --- a/hw/occamy/occamy_soc.sv.tpl +++ b/hw/occamy/occamy_soc.sv.tpl @@ -10,8 +10,8 @@ <% cuts_narrow_to_quad = occamy_cfg["cuts"]["narrow_to_quad"] cuts_quad_to_narrow = occamy_cfg["cuts"]["quad_to_narrow"] - cuts_quad_to_inter = occamy_cfg["cuts"]["quad_to_inter"] - cuts_inter_to_quad = occamy_cfg["cuts"]["inter_to_quad"] + cuts_wide_to_quad = occamy_cfg["cuts"]["wide_to_quad"] + cuts_quad_to_wide = occamy_cfg["cuts"]["quad_to_wide"] cuts_narrow_to_cva6 = occamy_cfg["cuts"]["narrow_to_cva6"] cuts_narrow_conv_to_spm_narrow_pre = occamy_cfg["cuts"]["narrow_conv_to_spm_narrow_pre"] cuts_narrow_conv_to_spm_narrow = occamy_cfg["cuts"]["narrow_conv_to_spm_narrow"] @@ -77,26 +77,12 @@ module ${name}_soc // Crossbars // /////////////// - addr_t [${nr_s1_quadrants-1}:0] s1_quadrant_base_addr, s1_quadrant_cfg_base_addr; - % for i in range(nr_s1_quadrants): - assign s1_quadrant_base_addr[${i}] = ClusterBaseOffset + ${i} * S1QuadrantAddressSpace; - assign s1_quadrant_cfg_base_addr[${i}] = S1QuadrantCfgBaseOffset + ${i} * S1QuadrantCfgAddressSpace; - % endfor - - // Crossbars ${module} /////////////////////////////////// // Connections between crossbars // /////////////////////////////////// <% - #// inter xbar -> wide xbar & wide xbar -> inter xbar - quadrant_inter_xbar.out_wide_xbar \ - .change_iw(context, soc_wide_xbar.iw, "inter_to_wide_iw_conv_{}".format(i), max_txns_per_id=txns_wide_and_inter) \ - .cut(context, cuts_wide_and_inter, name="inter_to_wide_cut_{}".format(i), to=soc_wide_xbar.in_quadrant_inter_xbar) - soc_wide_xbar.out_quadrant_inter_xbar \ - .cut(context, cuts_wide_and_inter, name="wide_to_inter_cut_{}".format(i)) \ - .change_iw(context, quadrant_inter_xbar.iw, "wide_to_inter_iw_conv_{}".format(i), to=quadrant_inter_xbar.in_wide_xbar, max_txns_per_id=txns_wide_and_inter) #// narrow xbar -> wide xbar & wide xbar -> narrow xbar soc_narrow_xbar.out_soc_wide \ .atomic_adapter(context, max_trans=max_atomics_wide, user_as_id=1, user_id_msb=soc_narrow_xbar.out_soc_wide.uw-1, user_id_lsb=0, n_cuts= cuts_withing_atomic_adapter_narrow_wide, name="soc_narrow_wide_amo_adapter") \ @@ -143,18 +129,18 @@ module ${name}_soc narrow_in = soc_narrow_xbar.__dict__["out_s1_quadrant_{}".format(i)].cut(context, cuts_narrow_to_quad, name="narrow_in_{}".format(i)) narrow_out = soc_narrow_xbar.__dict__["in_s1_quadrant_{}".format(i)].copy(name="narrow_out_{}".format(i)).declare(context) narrow_out.cut(context, cuts_quad_to_narrow, name="narrow_out_cut_{}".format(i), to=soc_narrow_xbar.__dict__["in_s1_quadrant_{}".format(i)]) - #// inter xbar -> quad & quad -> pre xbar - wide_in = quadrant_inter_xbar.__dict__["out_quadrant_{}".format(i)].cut(context, cuts_inter_to_quad, name="wide_in_{}".format(i)) + #// wide xbar -> quad & quad -> wide xbar + wide_in = soc_wide_xbar.__dict__["out_quadrant_{}".format(i)].cut(context, cuts_wide_to_quad, name="wide_in_{}".format(i)) #//wide_out = quadrant_pre_xbars[i].in_quadrant.copy(name="wide_out_{}".format(i)).declare(context) - wide_out = quadrant_inter_xbar.__dict__["in_quadrant_{}".format(i)].copy(name="wide_out_{}".format(i)).declare(context) - wide_out.cut(context, cuts_quad_to_inter, name="wide_out_cut_{}".format(i), to=quadrant_inter_xbar.__dict__["in_quadrant_{}".format(i)]) + wide_out = soc_wide_xbar.__dict__["in_quadrant_{}".format(i)].copy(name="wide_out_{}".format(i)).declare(context) + wide_out.cut(context, cuts_quad_to_wide, name="wide_out_cut_{}".format(i), to=soc_wide_xbar.__dict__["in_quadrant_{}".format(i)]) %>\ ${name}_quadrant_s1 i_${name}_quadrant_s1_${i} ( .clk_i (clk_i), .rst_ni (rst_ni), .test_mode_i (test_mode_i), - .tile_id_i (6'd${i}), + .chip_id_i (8'b0), // Temporary solution as the Chip ID is not provided yet .meip_i ('0), .mtip_i (mtip_i[${lower_core + nr_cores_s1_quadrant - 1}:${lower_core}]), .msip_i (msip_i[${lower_core + nr_cores_s1_quadrant - 1}:${lower_core}]), diff --git a/hw/occamy/quadrant_s1_ctrl/occamy_quadrant_s1_reg.hjson.tpl b/hw/occamy/quadrant_s1_ctrl/occamy_quadrant_s1_reg.hjson.tpl index e92a3fd3b..8029cbecc 100644 --- a/hw/occamy/quadrant_s1_ctrl/occamy_quadrant_s1_reg.hjson.tpl +++ b/hw/occamy/quadrant_s1_ctrl/occamy_quadrant_s1_reg.hjson.tpl @@ -122,6 +122,7 @@ % endfor % for i, t in enumerate(("narrow", "wide")): +% if "{}_tlb_cfg".format(t) in occamy_cfg["s1_quadrant"]: // Start ${t} TLB fields at regular offset { skipto: "${hex(0x800*(1+i))}" } % for e in range(occamy_cfg["s1_quadrant"]["{}_tlb_cfg".format(t)].get("l1_num_entries", 1)): @@ -186,9 +187,7 @@ }, { reserved: 1 } % endfor +% endif % endfor - - - ] } diff --git a/target/rtl/cfg/cluster_cfg/snax_KUL_cluster.hjson b/target/rtl/cfg/cluster_cfg/snax_KUL_cluster.hjson index d63895b1b..af9bd96ec 100644 --- a/target/rtl/cfg/cluster_cfg/snax_KUL_cluster.hjson +++ b/target/rtl/cfg/cluster_cfg/snax_KUL_cluster.hjson @@ -17,7 +17,7 @@ cluster_base_hartid: 1, addr_width: 48, data_width: 64, - user_width: 5, + user_width: 3, tcdm: { size: 512, // 128K -> 512K banks: 32, diff --git a/target/rtl/cfg/cluster_cfg/snax_KUL_xdma_cluster.hjson b/target/rtl/cfg/cluster_cfg/snax_KUL_xdma_cluster.hjson index 7d4bd8471..c0d630f7b 100644 --- a/target/rtl/cfg/cluster_cfg/snax_KUL_xdma_cluster.hjson +++ b/target/rtl/cfg/cluster_cfg/snax_KUL_xdma_cluster.hjson @@ -17,7 +17,7 @@ cluster_base_hartid: 1, addr_width: 48, data_width: 64, - user_width: 5, + user_width: 3, tcdm: { size: 512, // 128K -> 512K banks: 32, diff --git a/target/rtl/cfg/cluster_cfg/snax_minimal_cluster.hjson b/target/rtl/cfg/cluster_cfg/snax_minimal_cluster.hjson index 659d4b7ea..940879561 100644 --- a/target/rtl/cfg/cluster_cfg/snax_minimal_cluster.hjson +++ b/target/rtl/cfg/cluster_cfg/snax_minimal_cluster.hjson @@ -7,7 +7,7 @@ cluster_base_hartid: 1, addr_width: 48, data_width: 64, - user_width: 5, // clog2(total number of clusters) + user_width: 3, // clog2(total number of clusters) tcdm: { size: 128, // 128 kiB banks: 32, diff --git a/target/rtl/cfg/cluster_cfg/snax_xdma_cluster.hjson b/target/rtl/cfg/cluster_cfg/snax_xdma_cluster.hjson index a615ea19a..89f3ec0a1 100644 --- a/target/rtl/cfg/cluster_cfg/snax_xdma_cluster.hjson +++ b/target/rtl/cfg/cluster_cfg/snax_xdma_cluster.hjson @@ -7,7 +7,7 @@ cluster_base_hartid: 1, addr_width: 48, data_width: 64, - user_width: 5, // clog2(total number of clusters) + user_width: 3, // clog2(total number of clusters) tcdm: { size: 128, // 128 kiB banks: 32, diff --git a/target/rtl/cfg/occamy_cfg/snax_two_clusters.hjson b/target/rtl/cfg/occamy_cfg/snax_two_clusters.hjson index 7cd0b92fa..d252f74eb 100755 --- a/target/rtl/cfg/occamy_cfg/snax_two_clusters.hjson +++ b/target/rtl/cfg/occamy_cfg/snax_two_clusters.hjson @@ -1,7 +1,12 @@ { - // Remote CFG + // Remote CFG, about to be removed + is_remote_quadrant: false, remote_quadrants: [], + // Multi-chip configuration + hemaia_multichip: { + chip_id_width: 8 + } addr_width: 48, data_width: 64, // XBARs @@ -24,10 +29,8 @@ cuts: { narrow_to_quad: 3, quad_to_narrow: 3, - quad_to_pre: 1, - pre_to_inter: 1, - quad_to_inter: 1, - inter_to_quad: 3, + wide_to_quad: 3, + quad_to_wide: 3, narrow_to_cva6: 2, narrow_conv_to_spm_narrow_pre: 2, narrow_conv_to_spm_narrow: 1, @@ -74,7 +77,7 @@ rmq: 4, }, narrow_xbar_slv_id_width: 4, - narrow_xbar_user_width: 5, // clog2(total number of clusters) + narrow_xbar_user_width: 3, // clog2(total number of clusters) nr_s1_quadrant: 1, s1_quadrant: { // number of pending transactions on the narrow/wide network @@ -88,16 +91,17 @@ max_trans: 32, address_regions: 4, } - narrow_tlb_cfg: { - max_trans: 32, - l1_num_entries: 8, - l1_cut_ax: true, - } - wide_tlb_cfg: { - max_trans: 32, - l1_num_entries: 8, - l1_cut_ax: true, - } + // TLB is disabled + // narrow_tlb_cfg: { + // max_trans: 32, + // l1_num_entries: 8, + // l1_cut_ax: true, + // } + // wide_tlb_cfg: { + // max_trans: 32, + // l1_num_entries: 8, + // l1_cut_ax: true, + // } wide_xbar: { max_slv_trans: 32, max_mst_trans: 32, @@ -110,7 +114,7 @@ fall_through: false, }, narrow_xbar_slv_id_width: 4, - narrow_xbar_user_width: 5, // clog2(total number of clusters) + narrow_xbar_user_width: 3, // clog2(total number of clusters) cfg_base_addr: 184549376, // 0x0b000000 cfg_base_offset: 65536 // 0x10000 }, diff --git a/target/sim/sw/device/runtime/src/putchar_chip.c b/target/sim/sw/device/runtime/src/putchar_chip.c index 9fa062ce8..30b21761f 100644 --- a/target/sim/sw/device/runtime/src/putchar_chip.c +++ b/target/sim/sw/device/runtime/src/putchar_chip.c @@ -11,4 +11,4 @@ void _putchar(char character) { }; write_reg_u8(UART_THR, character); -} \ No newline at end of file +} diff --git a/util/occamygen/occamygen.py b/util/occamygen/occamygen.py index 3508264ab..c38d69294 100755 --- a/util/occamygen/occamygen.py +++ b/util/occamygen/occamygen.py @@ -119,7 +119,7 @@ def am_connect_soc_narrow_xbar(am, am_soc_narrow_xbar, occamy_cfg): occamy_cfg["sys_idma_cfg"]["address"]).attach_to(am_soc_narrow_xbar) return am_spm_narrow, am_sys_idma_cfg -def am_connect_soc_wide_xbar(am, am_soc_wide_xbar, occamy_cfg): +def am_connect_soc_wide_xbar_mem(am, am_soc_wide_xbar, occamy_cfg): # Connect wide SPM to Wide AXI am_spm_wide = am.new_leaf( "spm_wide", @@ -132,7 +132,7 @@ def am_connect_soc_wide_xbar(am, am_soc_wide_xbar, occamy_cfg): occamy_cfg["wide_zero_mem"]["address"]).attach_to(am_soc_wide_xbar) return am_spm_wide, am_wide_zero_mem -def am_connect_quad_xbar(am,am_soc_narrow_xbar,am_wide_xbar_quadrant_s1,am_narrow_xbar_quadrant_s1,occamy_cfg,cluster_generators): +def am_connect_soc_wide_xbar_quad(am,am_soc_narrow_xbar,am_wide_xbar_quadrant_s1,am_narrow_xbar_quadrant_s1,occamy_cfg,cluster_generators): ############################## # AM: Quadrants and Clusters # ############################## @@ -272,13 +272,7 @@ def get_top_kwargs(occamy_cfg,cluster_generators, soc_axi_lite_narrow_periph_xba } return top_kwargs - - - - - - -def get_soc_kwargs(occamy_cfg,cluster_generators,soc_narrow_xbar,soc_wide_xbar, quadrant_inter_xbar, util, name): +def get_soc_kwargs(occamy_cfg,cluster_generators,soc_narrow_xbar,soc_wide_xbar,util, name): core_per_cluster_list = [cluster_generator.cfg["nr_cores"] for cluster_generator in cluster_generators] nr_cores_quadrant = sum(core_per_cluster_list) nr_s1_quadrants = occamy_cfg["nr_s1_quadrant"] @@ -290,15 +284,11 @@ def get_soc_kwargs(occamy_cfg,cluster_generators,soc_narrow_xbar,soc_wide_xbar, "soc_wide_xbar": soc_wide_xbar, "cores": nr_s1_quadrants * nr_cores_quadrant + 1, "nr_s1_quadrants": nr_s1_quadrants, - "quadrant_inter_xbar": quadrant_inter_xbar, "nr_cores_quadrant": nr_cores_quadrant } return soc_kwargs - - - -def get_quadrant_ctrl_kwargs(occamy_cfg,quadrant_inter_xbar, soc_narrow_xbar,quadrant_s1_ctrl_xbars,quadrant_s1_ctrl_mux, name): +def get_quadrant_ctrl_kwargs(occamy_cfg, soc_wide_xbar, soc_narrow_xbar,quadrant_s1_ctrl_xbars,quadrant_s1_ctrl_mux, name): ro_cache_cfg = occamy_cfg["s1_quadrant"].get("ro_cache_cfg", {}) ro_cache_regions = ro_cache_cfg.get("address_regions", 1) narrow_tlb_cfg = occamy_cfg["s1_quadrant"].get("narrow_tlb_cfg", {}) @@ -314,7 +304,7 @@ def get_quadrant_ctrl_kwargs(occamy_cfg,quadrant_inter_xbar, soc_narrow_xbar,qua "narrow_tlb_entries": narrow_tlb_entries, "wide_tlb_cfg": wide_tlb_cfg, "wide_tlb_entries": wide_tlb_entries, - "quadrant_inter_xbar": quadrant_inter_xbar, + "soc_wide_xbar": soc_wide_xbar, "soc_narrow_xbar": soc_narrow_xbar, "quadrant_s1_ctrl_xbars": quadrant_s1_ctrl_xbars, "quadrant_s1_ctrl_mux": quadrant_s1_ctrl_mux @@ -324,7 +314,7 @@ def get_quadrant_ctrl_kwargs(occamy_cfg,quadrant_inter_xbar, soc_narrow_xbar,qua -def get_quadrant_kwargs(occamy_cfg,cluster_generators,soc_narrow_xbar,quadrant_inter_xbar, wide_xbar_quadrant_s1, narrow_xbar_quadrant_s1, name): +def get_quadrant_kwargs(occamy_cfg,cluster_generators,soc_wide_xbar,soc_narrow_xbar, wide_xbar_quadrant_s1, narrow_xbar_quadrant_s1, name): cluster_cfgs = list() nr_clusters = len(occamy_cfg["clusters"]) for i in range(nr_clusters): @@ -333,11 +323,10 @@ def get_quadrant_kwargs(occamy_cfg,cluster_generators,soc_narrow_xbar,quadrant_i "name": name, "occamy_cfg": occamy_cfg, "cluster_cfgs": cluster_cfgs, + "soc_wide_xbar": soc_wide_xbar, "soc_narrow_xbar": soc_narrow_xbar, - "quadrant_inter_xbar": quadrant_inter_xbar, "wide_xbar_quadrant_s1": wide_xbar_quadrant_s1, "narrow_xbar_quadrant_s1": narrow_xbar_quadrant_s1 - } return quadrant_kwargs @@ -394,7 +383,8 @@ def get_pkg_kwargs(occamy_cfg,cluster_generators, name): "cluster_base_addr": util.to_sv_hex(cluster_cfg["cluster_base_addr"]), "cluster_base_offset": util.to_sv_hex(cluster_cfg["cluster_base_offset"]), "quad_cfg_base_addr": util.to_sv_hex(occamy_cfg["s1_quadrant"]["cfg_base_addr"]), - "quad_cfg_base_offset": util.to_sv_hex(occamy_cfg["s1_quadrant"]["cfg_base_offset"]) + "quad_cfg_base_offset": util.to_sv_hex(occamy_cfg["s1_quadrant"]["cfg_base_offset"]), + "hemaia_multichip": occamy_cfg["hemaia_multichip"] } return pkg_kwargs @@ -642,7 +632,7 @@ def main(): # Quadrant inter crossbar address map: - am_quadrant_inter_xbar = am.new_node("am_quadrant_inter_xbar") + # am_quadrant_inter_xbar = am.new_node("am_quadrant_inter_xbar") # Quadrant crossbar address map am_wide_xbar_quadrant_s1 = list() @@ -662,21 +652,20 @@ def main(): am_axi_lite_narrow_peripherals, am_bootrom, am_clint = am_connect_soc_lite_narrow_periph_xbar(am, am_soc_axi_lite_narrow_periph_xbar, occamy_cfg) am_spm_narrow,am_sys_idma_cfg = am_connect_soc_narrow_xbar(am, am_soc_narrow_xbar, occamy_cfg) - am_spm_wide,am_wide_zero_mem = am_connect_soc_wide_xbar(am,am_soc_wide_xbar,occamy_cfg) - - am_clusters = am_connect_quad_xbar(am,am_soc_narrow_xbar,am_wide_xbar_quadrant_s1,am_narrow_xbar_quadrant_s1,occamy_cfg,cluster_generators) + am_spm_wide,am_wide_zero_mem = am_connect_soc_wide_xbar_mem(am,am_soc_wide_xbar,occamy_cfg) + am_clusters = am_connect_soc_wide_xbar_quad(am,am_soc_narrow_xbar,am_wide_xbar_quadrant_s1,am_narrow_xbar_quadrant_s1,occamy_cfg,cluster_generators) # Then we connect between xbars # Connect quadrants AXI xbar for i in range(nr_s1_quadrants): am_narrow_xbar_quadrant_s1[i].attach(am_wide_xbar_quadrant_s1[i]) am_soc_narrow_xbar.attach(am_narrow_xbar_quadrant_s1[i]) - am_quadrant_inter_xbar.attach(am_wide_xbar_quadrant_s1[i]) + am_soc_wide_xbar.attach(am_wide_xbar_quadrant_s1[i]) # Connect quadrant inter xbar - am_soc_wide_xbar.attach(am_quadrant_inter_xbar) - am_quadrant_inter_xbar.attach(am_soc_wide_xbar) + # am_soc_wide_xbar.attach(am_quadrant_inter_xbar) + # am_quadrant_inter_xbar.attach(am_soc_wide_xbar) # Connect narrow xbar am_soc_narrow_xbar.attach(am_soc_axi_lite_periph_xbar) @@ -741,36 +730,13 @@ def main(): # add bootrom and clint seperately soc_axi_lite_narrow_periph_xbar.add_output_entry("bootrom", am_bootrom) soc_axi_lite_narrow_periph_xbar.add_output_entry("clint", am_clint) - quadrant_inter_xbar = solder.AxiXbar( - 48, - 512, - occamy_cfg["quadrant_inter_xbar_slv_id_width_no_rocache"] + ( - 1 if occamy_cfg["s1_quadrant"].get("ro_cache_cfg") else 0), - name="quadrant_inter_xbar", - clk="clk_i", - rst="rst_ni", - max_slv_trans=occamy_cfg["quadrant_inter_xbar"]["max_slv_trans"], - max_mst_trans=occamy_cfg["quadrant_inter_xbar"]["max_mst_trans"], - fall_through=occamy_cfg["quadrant_inter_xbar"]["fall_through"], - no_loopback=True, - atop_support=False, - context="soc", - node=am_quadrant_inter_xbar) - # Default port: soc wide xbar - quadrant_inter_xbar.add_output_entry("wide_xbar", am_soc_wide_xbar) - quadrant_inter_xbar.add_input("wide_xbar") - for i in range(nr_s1_quadrants): - # Default route passes HBI through quadrant 0 - # --> mask this route, forcing it through default wide xbar - quadrant_inter_xbar.add_output_entry("quadrant_{}".format(i), - am_wide_xbar_quadrant_s1[i]) - quadrant_inter_xbar.add_input("quadrant_{}".format(i)) soc_wide_xbar = solder.AxiXbar( 48, 512, # This is the cleanest solution minimizing ID width conversions - quadrant_inter_xbar.iw, + occamy_cfg["quadrant_inter_xbar_slv_id_width_no_rocache"] + ( + 1 if occamy_cfg["s1_quadrant"].get("ro_cache_cfg") else 0), name="soc_wide_xbar", clk="clk_i", rst="rst_ni", @@ -782,13 +748,18 @@ def main(): context="soc", node=am_soc_wide_xbar) - soc_wide_xbar.add_output_entry("quadrant_inter_xbar", am_quadrant_inter_xbar) soc_wide_xbar.add_output_entry("soc_narrow", am_soc_narrow_xbar) - soc_wide_xbar.add_input("quadrant_inter_xbar") soc_wide_xbar.add_input("soc_narrow") soc_wide_xbar.add_input("sys_idma_mst") soc_wide_xbar.add_output_entry("spm_wide", am_spm_wide) soc_wide_xbar.add_output_entry("wide_zero_mem", am_wide_zero_mem) + for i in range(nr_s1_quadrants): + # Default route passes HBI through quadrant 0 + # --> mask this route, forcing it through default wide xbar + soc_wide_xbar.add_output_entry("quadrant_{}".format(i), + am_wide_xbar_quadrant_s1[i]) + soc_wide_xbar.add_input("quadrant_{}".format(i)) + ################### # SoC Narrow Xbar # ################### @@ -808,11 +779,12 @@ def main(): node=am_soc_narrow_xbar) for i in range(nr_s1_quadrants): - soc_narrow_xbar.add_output_symbolic_multi("s1_quadrant_{}".format(i), - [("s1_quadrant_base_addr", - "S1QuadrantAddressSpace"), - ("s1_quadrant_cfg_base_addr", - "S1QuadrantCfgAddressSpace")]) + # soc_narrow_xbar.add_output_symbolic_multi("s1_quadrant_{}".format(i), + # [("s1_quadrant_base_addr", + # "S1QuadrantAddressSpace"), + # ("s1_quadrant_cfg_base_addr", + # "S1QuadrantCfgAddressSpace")]) + soc_narrow_xbar.add_output_entry("s1_quadrant_{}".format(i),am_narrow_xbar_quadrant_s1[i]) soc_narrow_xbar.add_input("s1_quadrant_{}".format(i)) soc_narrow_xbar.add_input("cva6") @@ -940,7 +912,6 @@ def main(): "name": args.name, "soc_narrow_xbar": soc_narrow_xbar, "soc_wide_xbar": soc_wide_xbar, - "quadrant_inter_xbar": quadrant_inter_xbar, "quadrant_s1_ctrl_xbars": quadrant_s1_ctrl_xbars, "quadrant_s1_ctrl_mux": quadrant_s1_ctrl_mux, "wide_xbar_quadrant_s1": wide_xbar_quadrant_s1, @@ -970,7 +941,7 @@ def main(): # SoC (fully synchronous) # ########################### if args.soc_sv: - soc_kwargs = get_soc_kwargs(occamy_cfg,cluster_generators,soc_narrow_xbar,soc_wide_xbar, quadrant_inter_xbar, util, args.name) + soc_kwargs = get_soc_kwargs(occamy_cfg,cluster_generators,soc_narrow_xbar,soc_wide_xbar, util, args.name) write_template(args.soc_sv, outdir, module=solder.code_module['soc'], @@ -980,7 +951,7 @@ def main(): # S1 Quadrant controller # ########################## if args.quadrant_s1_ctrl: - quadrant_ctrl_kwargs = get_quadrant_ctrl_kwargs(occamy_cfg,quadrant_inter_xbar, soc_narrow_xbar,quadrant_s1_ctrl_xbars, quadrant_s1_ctrl_mux, args.name) + quadrant_ctrl_kwargs = get_quadrant_ctrl_kwargs(occamy_cfg, soc_wide_xbar, soc_narrow_xbar,quadrant_s1_ctrl_xbars, quadrant_s1_ctrl_mux, args.name) write_template(args.quadrant_s1_ctrl, outdir, module=solder.code_module['quadrant_s1_ctrl'], @@ -989,7 +960,7 @@ def main(): # S1 Quadrant # ############### if args.quadrant_s1: - quadrant_kwargs = get_quadrant_kwargs(occamy_cfg, cluster_generators, soc_narrow_xbar, quadrant_inter_xbar, wide_xbar_quadrant_s1, narrow_xbar_quadrant_s1, args.name) + quadrant_kwargs = get_quadrant_kwargs(occamy_cfg, cluster_generators, soc_wide_xbar, soc_narrow_xbar, wide_xbar_quadrant_s1, narrow_xbar_quadrant_s1, args.name) if nr_s1_quadrants > 0: write_template(args.quadrant_s1, outdir,