From 34c79b07cb485d6c494b3189d080bb1f3fa386cd Mon Sep 17 00:00:00 2001 From: Yunhao Deng Date: Sat, 2 Nov 2024 16:46:59 +0100 Subject: [PATCH] Sync PR#66-67 (#78) * Remove all cluster_cfg and directly use one from snax (#66) * Update hemaia_minimal.hjson (#67) --------- Co-authored-by: Fanchen Kong <100082872+Konste11ation@users.noreply.github.com> --- .github/workflows/ci.yml | 4 +- Makefile | 2 +- README.md | 28 +-- target/rtl/Makefile | 4 +- target/rtl/cfg/.gitignore | 2 +- .../cfg/cluster_cfg/snax_KUL_cluster.hjson | 236 ------------------ .../cluster_cfg/snax_KUL_xdma_cluster.hjson | 202 --------------- .../cfg/cluster_cfg/snax_alu_cluster.hjson | 169 ------------- .../cfg/cluster_cfg/snax_cgra_cluster.hjson | 170 ------------- .../cfg/cluster_cfg/snax_dimc_cluster.hjson | 171 ------------- .../cluster_cfg/snax_hypercorex_cluster.hjson | 177 ------------- .../cluster_cfg/snax_minimal_cluster.hjson | 107 -------- target/rtl/cfg/{occamy_cfg => }/hemaia.hjson | 0 .../cfg/{occamy_cfg => }/hemaia_minimal.hjson | 4 +- .../cfg/{occamy_cfg => }/hemaia_tapeout.hjson | 0 .../hemaia_two_clusters.hjson | 0 target/tapeout/Makefile | 4 +- util/hemaia/util.py | 4 +- util/occamygen/occamygen.py | 2 +- 19 files changed, 27 insertions(+), 1259 deletions(-) delete mode 100644 target/rtl/cfg/cluster_cfg/snax_KUL_cluster.hjson delete mode 100644 target/rtl/cfg/cluster_cfg/snax_KUL_xdma_cluster.hjson delete mode 100644 target/rtl/cfg/cluster_cfg/snax_alu_cluster.hjson delete mode 100644 target/rtl/cfg/cluster_cfg/snax_cgra_cluster.hjson delete mode 100644 target/rtl/cfg/cluster_cfg/snax_dimc_cluster.hjson delete mode 100644 target/rtl/cfg/cluster_cfg/snax_hypercorex_cluster.hjson delete mode 100644 target/rtl/cfg/cluster_cfg/snax_minimal_cluster.hjson rename target/rtl/cfg/{occamy_cfg => }/hemaia.hjson (100%) rename target/rtl/cfg/{occamy_cfg => }/hemaia_minimal.hjson (94%) rename target/rtl/cfg/{occamy_cfg => }/hemaia_tapeout.hjson (100%) rename target/rtl/cfg/{occamy_cfg => }/hemaia_two_clusters.hjson (100%) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 021c1e16a..3d0ad63d1 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -48,10 +48,10 @@ jobs: - name: Compile SW run: | echo "Compiling SW" - make sw CFG_OVERRIDE=target/sw/cfg/occamy_cfg/hemaia.hjson -j$(nproc) + make sw CFG_OVERRIDE=target/sw/cfg/hemaia.hjson -j$(nproc) - name: Compile RTL run: | - make rtl CFG_OVERRIDE=target/rtl/cfg/occamy_cfg/hemaia.hjson + make rtl CFG_OVERRIDE=target/rtl/cfg/hemaia.hjson - name: Compile Verilator Binary run: | make occamy_system_vlt -j$(nproc) diff --git a/Makefile b/Makefile index 9a3fb58c4..2a8d802a5 100644 --- a/Makefile +++ b/Makefile @@ -7,7 +7,7 @@ MKFILE_PATH := $(abspath $(lastword $(MAKEFILE_LIST))) MKFILE_DIR := $(dir $(MKFILE_PATH)) -CFG_OVERRIDE ?= target/rtl/cfg/occamy_cfg/hemaia.hjson +CFG_OVERRIDE ?= target/rtl/cfg/hemaia.hjson CFG = $(realpath $(CFG_OVERRIDE)) clean: diff --git a/README.md b/README.md index 299a54b20..af03c38f7 100644 --- a/README.md +++ b/README.md @@ -40,10 +40,10 @@ The following files are released under Solderpad v0.51 (`SHL-0.51`) see `hw/LICE ### Option 1: Occamy configuration on VCU128 (Bootrom and DRAM from Xilinx IP) ```makefile -@ Occamy Docker: make bootrom -@ Occamy Docker: make sw -@ Occamy Docker: make -C target/fpga/sw [APP=???] (Which binary file you want to use) -@ SNAX Docker: make rtl CFG_OVERRIDE=target/rtl/cfg/occamy_cfg/hemaia.hjson (Can be modified to other configurations) +@ SNAX Docker: make bootrom CFG_OVERRIDE=target/rtl/cfg/... +@ SNAX Docker: make sw +@ SNAX Docker: make -C target/fpga/sw [APP=???] (Which binary file you want to use) +@ SNAX Docker: make rtl CFG_OVERRIDE=target/rtl/cfg/...hjson @ SNAX Docker: make occamy_system_vivado_preparation @ Barnard3: make occamy_system_vcu128 @ Barnard3: make occamy_system_vcu128_gui @@ -52,10 +52,10 @@ The following files are released under Solderpad v0.51 (`SHL-0.51`) see `hw/LICE ### Option 2: HeMAiA configuration on VPK180 (Tapeout configuration, everything is internal) ```makefile -@ Occamy Docker: make bootrom -@ Occamy Docker: make sw -@ Occamy Docker: make -C target/fpga/sw [APP=???] (Which binary file you want to use) -@ SNAX Docker: make rtl CFG_OVERRIDE=target/rtl/cfg/occamy_cfg/hemaia.hjson (Can be modified to other configurations) +@ SNAX Docker: make bootrom CFG_OVERRIDE=target/rtl/cfg/...hjson +@ SNAX Docker: make sw CFG_OVERRIDE=target/rtl/cfg/...hjson +@ SNAX Docker: make -C target/fpga/sw [APP=???] (Which binary file you want to use) +@ SNAX Docker: make rtl CFG_OVERRIDE=target/rtl/cfg/...hjson @ SNAX Docker: make hemaia_system_vivado_preparation @ Barnard3: make hemaia_system_vivado TARGET_PLATFORM={vpk180, vcu128} @ Barnard3: make hemaia_system_vivado_gui @@ -65,9 +65,9 @@ The following files are released under Solderpad v0.51 (`SHL-0.51`) see `hw/LICE ### Option 1: Simulate with Verilator ```makefile -@ Occamy Docker: make bootrom -@ Occamy Docker: make sw -@ SNAX Docker: make rtl CFG_OVERRIDE=target/rtl/cfg/occamy_cfg/hemaia.hjson (Can be modified to other configurations) +@ SNAX Docker: make bootrom CFG_OVERRIDE=target/rtl/cfg/...hjson +@ SNAX Docker: make sw CFG_OVERRIDE=target/rtl/cfg/...hjson +@ SNAX Docker: make rtl CFG_OVERRIDE=target/rtl/cfg/...hjson @ SNAX Docker: make occamy_system_vlt @ SNAX Docker: target/sim/bin/occamy_top.vlt [Elf location] [--vcd] ``` @@ -75,9 +75,9 @@ The following files are released under Solderpad v0.51 (`SHL-0.51`) see `hw/LICE ### Option 2: Simulate with Questasim ```makefile -@ Occamy Docker: make bootrom -@ Occamy Docker: make sw -@ SNAX Docker: make rtl CFG_OVERRIDE=target/rtl/cfg/occamy_cfg/hemaia.hjson (Can be modified to other configurations) +@ SNAX Docker: make bootrom CFG_OVERRIDE=target/rtl/cfg/...hjson +@ SNAX Docker: make sw CFG_OVERRIDE=target/rtl/cfg/...hjson +@ SNAX Docker: make rtl CFG_OVERRIDE=target/rtl/cfg/...hjson @ SNAX Docker: make occamy_system_vsim_preparation @ Barnard3: make occamy_system_vsim @ Barnard3: target/sim/bin/occamy_top.vsim[.gui] [Elf location] diff --git a/target/rtl/Makefile b/target/rtl/Makefile index 1436bc5b5..985a2faa0 100644 --- a/target/rtl/Makefile +++ b/target/rtl/Makefile @@ -53,12 +53,12 @@ PLICGEN = $(SOURCE_PLIC_DIR)/util/reg_rv_plic.py # (LRU) config, all targets depending on the configuration file have # to be rebuilt. This file is used to express this condition as a # prerequisite for other rules. -CFG = $(TARGET_RTL)/cfg/occamy_cfg/lru.hjson +CFG = $(TARGET_RTL)/cfg/lru.hjson $(CFG): FORCE @# If the LRU config file doesn't exist, we use the default config. @if [ ! -e $@ ] ; then \ - DEFAULT_CFG="$(TARGET_RTL)/cfg/occamy_cfg/hemaia.hjson"; \ + DEFAULT_CFG="$(TARGET_RTL)/cfg/hemaia.hjson"; \ echo "Using default config file: $$DEFAULT_CFG"; \ cp $$DEFAULT_CFG $@; \ fi diff --git a/target/rtl/cfg/.gitignore b/target/rtl/cfg/.gitignore index 266a26b82..8cb42d683 100644 --- a/target/rtl/cfg/.gitignore +++ b/target/rtl/cfg/.gitignore @@ -1 +1 @@ -occamy_cfg/lru.hjson \ No newline at end of file +/lru.hjson diff --git a/target/rtl/cfg/cluster_cfg/snax_KUL_cluster.hjson b/target/rtl/cfg/cluster_cfg/snax_KUL_cluster.hjson deleted file mode 100644 index 3f7036ad0..000000000 --- a/target/rtl/cfg/cluster_cfg/snax_KUL_cluster.hjson +++ /dev/null @@ -1,236 +0,0 @@ -// Copyright 2023 ETH Zurich and University of Bologna. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -// Cluster configuration for a simple testbench system. -{ - nr_s1_quadrant: 1, - s1_quadrant: { - nr_clusters: 1, - }, - - cluster: { - name: "snax_KUL_cluster", - bender_target: ["snax_KUL_cluster"], - boot_addr: 4096, // 0x1000 - cluster_base_addr: 268435456, // 0x1000_0000 - cluster_base_offset: 1048576, // 256KB -> 1MB - cluster_base_hartid: 1, - addr_width: 48, - data_width: 64, - user_width: 3, - tcdm: { - size: 128, // 128K -> 512K - banks: 32, - }, - cluster_periph_size: 64, // kB - zero_mem_size: 64, // kB - dma_data_width: 512, - dma_axi_req_fifo_depth: 16, - dma_req_fifo_depth: 8, - snax_custom_tcdm_assign: { - snax_enable_assign_tcdm_idx: true, - snax_narrow_assign_start_idx: [0,56], - snax_narrow_assign_end_idx: [7,71], - snax_wide_assign_start_idx: [8], - snax_wide_assign_end_idx: [55], - }, - // AXI bandwidth switcher - use_ax_bw_converter: false, - converted_axi_bandwidth: 256, - - // Additional parameters for Occamy Integration - narrow_trans: 4, - wide_trans: 32, - dma_user_width: 1, - // We don't need Snitch debugging in Occamy - enable_debug: false, - // We don't need Snitch (core-internal) virtual memory support - vm_support: false, - // Memory configuration inputs - sram_cfg_expose: true, - sram_cfg_fields: { - ema: 3, - emaw: 2, - emas: 1 - }, - - // Timing parameters - timing: { - lat_comp_fp32: 3, - lat_comp_fp64: 3, - lat_comp_fp16: 2, - lat_comp_fp16_alt: 2, - lat_comp_fp8: 1, - lat_comp_fp8_alt: 1, - lat_noncomp: 1, - lat_conv: 1, - lat_sdotp: 2, - fpu_pipe_config: "BEFORE" - narrow_xbar_latency: "CUT_ALL_PORTS", - wide_xbar_latency: "CUT_ALL_PORTS", - // Isolate the core. - register_core_req: true, - register_core_rsp: true, - register_offload_req: true, - register_offload_rsp: true - }, - hives: [ - // Hive 0 - { - icache: { - size: 8, // total instruction cache size in kByte - sets: 2, // number of ways - cacheline: 256 // word size in bits - }, - cores: [ - { $ref: "#/snax_streamer_gemmX_core_template" }, - { $ref: "#/snax_data_reshuffler_core_template" }, - { $ref: "#/dma_core_template" }, - ] - } - ] - }, - dram: { - // 0x8000_0000 - address: 2147483648, - // 0x8000_0000 - length: 2147483648 - }, - peripherals: { - clint: { - // 0xffff_0000 - address: 4294901760, - // 0x0000_1000 - length: 4096 - }, - }, - // Templates. - snax_streamer_gemmX_core_template: { - isa: "rv32ima", - xssr: false, - xfrep: false, - xdma: false, - xf16: false, - xf16alt: false, - xf8: false, - xf8alt: false, - xfdotp: false, - xfvec: false, - snax_acc_cfg: { - snax_acc_name: "snax_streamer_gemmX", - bender_target: ["snax_gemmX"], - snax_narrow_tcdm_ports: 8, - snax_wide_tcdm_ports: 48, - snax_num_rw_csr: 10, - snax_num_ro_csr: 2, - snax_gemmx_mesh_row: 8, - snax_gemmx_tile_size: 8, - snax_gemmx_mesh_col: 8, - with_pipeline: true, - snax_streamer_cfg: {$ref: "#/snax_streamer_gemmX_streamer_template" } - }, - snax_use_custom_ports: false, - num_int_outstanding_loads: 1, - num_int_outstanding_mem: 4, - num_fp_outstanding_loads: 4, - num_fp_outstanding_mem: 4, - num_sequencer_instructions: 16, - num_dtlb_entries: 1, - num_itlb_entries: 1 - }, - // Templates. - snax_data_reshuffler_core_template: { - isa: "rv32ima", - xssr: false, - xfrep: false, - xdma: false, - xf16: false, - xf16alt: false, - xf8: false, - xf8alt: false, - xfdotp: false, - xfvec: false, - snax_acc_cfg: { - snax_acc_name: "snax_data_reshuffler", - bender_target: ["snax_data_reshuffler"], - snax_narrow_tcdm_ports: 16, - snax_num_rw_csr: 2, - snax_num_ro_csr: 2, - snax_streamer_cfg: {$ref: "#/snax_data_reshuffler_streamer_template" } - }, - snax_use_custom_ports: false, - num_int_outstanding_loads: 1, - num_int_outstanding_mem: 4, - num_fp_outstanding_loads: 4, - num_fp_outstanding_mem: 4, - num_sequencer_instructions: 16, - num_dtlb_entries: 1, - num_itlb_entries: 1 - }, - dma_core_template: { - isa: "rv32ima", - xdma: true - xssr: false - xfrep: false - xf16: false, - xf16alt: false, - xf8: false, - xf8alt: false, - xfdotp: false, - xfvec: false, - num_int_outstanding_loads: 1, - num_int_outstanding_mem: 4, - num_fp_outstanding_loads: 4, - num_fp_outstanding_mem: 4, - num_sequencer_instructions: 16, - num_dtlb_entries: 1, - num_itlb_entries: 1 - }, - // SNAX Streamer Templates - snax_streamer_gemmX_streamer_template :{ - - data_reader_params: { - spatial_bounds: [[8], [8]], - temporal_dim: [6, 3], - num_channel: [8, 8], - fifo_depth: [2, 2], - }, - - data_writer_params:{ - spatial_bounds: [[8]], - temporal_dim: [3], - num_channel: [8], - fifo_depth: [2], - }, - - data_reader_writer_params:{ - spatial_bounds: [[32], [32]], - temporal_dim: [3, 3], - num_channel: [32, 32], - fifo_depth: [2, 2], - }, - - snax_library_name: "gemmx", - }, - // SNAX Streamer Templates - snax_data_reshuffler_streamer_template :{ - - data_reader_params: { - spatial_bounds: [[8]], - temporal_dim: [5], - num_channel: [8], - fifo_depth: [2], - }, - - data_writer_params:{ - spatial_bounds: [[8]], - temporal_dim: [3], - num_channel: [8], - fifo_depth: [2], - }, - - snax_library_name: "data-reshuffler", - - } -} diff --git a/target/rtl/cfg/cluster_cfg/snax_KUL_xdma_cluster.hjson b/target/rtl/cfg/cluster_cfg/snax_KUL_xdma_cluster.hjson deleted file mode 100644 index 330a2e564..000000000 --- a/target/rtl/cfg/cluster_cfg/snax_KUL_xdma_cluster.hjson +++ /dev/null @@ -1,202 +0,0 @@ -// Copyright 2023 ETH Zurich and University of Bologna. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -// Cluster configuration for a simple testbench system. -{ - nr_s1_quadrant: 1, - s1_quadrant: { - nr_clusters: 1, - }, - - cluster: { - name: "snax_KUL_xdma_cluster", - bender_target: ["snax_KUL_xdma_cluster"], - boot_addr: 4096, // 0x1000 - cluster_base_addr: 268435456, // 0x1000_0000 - cluster_base_offset: 1048576, // 256KB -> 1MB - cluster_base_hartid: 1, - addr_width: 48, - data_width: 64, - user_width: 3, - tcdm: { - size: 128, // 128K -> 512K - banks: 32, - }, - cluster_periph_size: 64, // kB - zero_mem_size: 64, // kB - dma_data_width: 512, - dma_axi_req_fifo_depth: 16, - dma_req_fifo_depth: 8, - snax_custom_tcdm_assign: { - snax_enable_assign_tcdm_idx: true, - snax_narrow_assign_start_idx: [0,56], - snax_narrow_assign_end_idx: [7,71], - snax_wide_assign_start_idx: [8], - snax_wide_assign_end_idx: [55], - }, - // AXI bandwidth switcher - use_ax_bw_converter: false, - converted_axi_bandwidth: 256, - - // Additional parameters for Occamy Integration - narrow_trans: 4, - wide_trans: 32, - dma_user_width: 1, - // We don't need Snitch debugging in Occamy - enable_debug: false, - // We don't need Snitch (core-internal) virtual memory support - vm_support: false, - // Memory configuration inputs - sram_cfg_expose: true, - sram_cfg_fields: { - ema: 3, - emaw: 2, - emas: 1 - }, - - // Timing parameters - timing: { - lat_comp_fp32: 3, - lat_comp_fp64: 3, - lat_comp_fp16: 2, - lat_comp_fp16_alt: 2, - lat_comp_fp8: 1, - lat_comp_fp8_alt: 1, - lat_noncomp: 1, - lat_conv: 1, - lat_sdotp: 2, - fpu_pipe_config: "BEFORE" - narrow_xbar_latency: "CUT_ALL_PORTS", - wide_xbar_latency: "CUT_ALL_PORTS", - // Isolate the core. - register_core_req: true, - register_core_rsp: true, - register_offload_req: true, - register_offload_rsp: true - }, - hives: [ - // Hive 0 - { - icache: { - size: 8, // total instruction cache size in kByte - sets: 2, // number of ways - cacheline: 256 // word size in bits - }, - cores: [ - { $ref: "#/snax_streamer_gemmX_core_template" }, - { $ref: "#/dma_core_template" }, - ] - } - ] - }, - dram: { - // 0x8000_0000 - address: 2147483648, - // 0x8000_0000 - length: 2147483648 - }, - peripherals: { - clint: { - // 0xffff_0000 - address: 4294901760, - // 0x0000_1000 - length: 4096 - }, - }, - // GeMM Core Templates. - snax_streamer_gemmX_core_template: { - isa: "rv32ima", - xssr: false, - xfrep: false, - xdma: false, - xf16: false, - xf16alt: false, - xf8: false, - xf8alt: false, - xfdotp: false, - xfvec: false, - snax_acc_cfg: { - snax_acc_name: "snax_streamer_gemmX", - bender_target: ["snax_gemmX"], - snax_narrow_tcdm_ports: 8, - snax_wide_tcdm_ports: 48, - snax_num_rw_csr: 19, - snax_num_ro_csr: 2, - snax_gemmx_mesh_row: 8, - snax_gemmx_tile_size: 8, - snax_gemmx_mesh_col: 8, - with_pipeline: true, - snax_streamer_cfg: {$ref: "#/snax_streamer_gemmX_streamer_template" } - }, - snax_use_custom_ports: false, - num_int_outstanding_loads: 1, - num_int_outstanding_mem: 4, - num_fp_outstanding_loads: 4, - num_fp_outstanding_mem: 4, - num_sequencer_instructions: 16, - num_dtlb_entries: 1, - num_itlb_entries: 1 - }, - // DMA + XDMA Core Template. - dma_core_template: { - isa: "rv32ima", - snax_xdma_cfg: { - bender_target: ["snax_KUL_xdma_cluster_xdma"], - reader_buffer: 4, - writer_buffer: 4, - reader_agu_spatial_bounds: "8", - reader_agu_temporal_dimension: 6, - writer_agu_spatial_bounds: "8", - writer_agu_temporal_dimension: 6, - HasTransposer: 3, - HasVerilogMemset: 1, - HasMaxPool: 2 - } - xdma: true - xssr: false - xfrep: false - xf16: false, - xf16alt: false, - xf8: false, - xf8alt: false, - xfdotp: false, - xfvec: false, - num_int_outstanding_loads: 1, - num_int_outstanding_mem: 4, - num_fp_outstanding_loads: 4, - num_fp_outstanding_mem: 4, - num_sequencer_instructions: 16, - num_dtlb_entries: 1, - num_itlb_entries: 1 - }, - // SNAX Streamer Templates - snax_streamer_gemmX_streamer_template :{ - - data_reader_params: { - spatial_bounds: [[8], [8]], - temporal_dim: [6, 3], - num_channel: [8, 8], - fifo_depth: [2, 2], - }, - - data_writer_params:{ - spatial_bounds: [[8]], - temporal_dim: [3], - num_channel: [8], - fifo_depth: [2], - }, - - data_reader_writer_params:{ - spatial_bounds: [[32], [32]], - temporal_dim: [3, 3], - num_channel: [32, 32], - fifo_depth: [2, 2], - configurable_channel: [1, 0], - }, - - has_transpose: true, - - snax_library_name: "gemmx", - } -} diff --git a/target/rtl/cfg/cluster_cfg/snax_alu_cluster.hjson b/target/rtl/cfg/cluster_cfg/snax_alu_cluster.hjson deleted file mode 100644 index 26fa414c4..000000000 --- a/target/rtl/cfg/cluster_cfg/snax_alu_cluster.hjson +++ /dev/null @@ -1,169 +0,0 @@ -// Copyright 2023 ETH Zurich and University of Bologna. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -// Cluster configuration for a simple testbench system. -{ - nr_s1_quadrant: 1, - s1_quadrant: { - nr_clusters: 1, - }, - - cluster: { - name: "snax_alu_cluster", - bender_target: ["snax_alu_cluster"], - boot_addr: 4096, // 0x1000 - cluster_base_addr: 268435456, // 0x1000_0000 - cluster_base_offset: 1048576, // 256KB -> 1MB - cluster_base_hartid: 1, - addr_width: 48, - data_width: 64, - user_width: 3, - tcdm: { - size: 128, // 128K -> 512K - banks: 32, - }, - cluster_periph_size: 64, // kB - zero_mem_size: 64, // kB - dma_data_width: 512, - dma_axi_req_fifo_depth: 16, - dma_req_fifo_depth: 8, - // AXI bandwidth switcher - use_ax_bw_converter: false, - converted_axi_bandwidth: 256, - - // Additional parameters for Occamy Integration - narrow_trans: 4, - wide_trans: 32, - dma_user_width: 1, - // We don't need Snitch debugging in Occamy - enable_debug: false, - // We don't need Snitch (core-internal) virtual memory support - vm_support: false, - // Memory configuration inputs - sram_cfg_expose: true, - sram_cfg_fields: { - ema: 3, - emaw: 2, - emas: 1 - }, - - // Timing parameters - timing: { - lat_comp_fp32: 3, - lat_comp_fp64: 3, - lat_comp_fp16: 2, - lat_comp_fp16_alt: 2, - lat_comp_fp8: 1, - lat_comp_fp8_alt: 1, - lat_noncomp: 1, - lat_conv: 1, - lat_sdotp: 2, - fpu_pipe_config: "BEFORE" - narrow_xbar_latency: "CUT_ALL_PORTS", - wide_xbar_latency: "CUT_ALL_PORTS", - // Isolate the core. - register_core_req: true, - register_core_rsp: true, - register_offload_req: true, - register_offload_rsp: true - }, - hives: [ - // Hive 0 - { - icache: { - size: 8, // total instruction cache size in kByte - sets: 2, // number of ways - cacheline: 256 // word size in bits - }, - cores: [ - { $ref: "#/snax_alu_core_template" }, - { $ref: "#/dma_core_template" }, - ] - } - ] - }, - dram: { - // 0x8000_0000 - address: 2147483648, - // 0x8000_0000 - length: 2147483648 - }, - peripherals: { - clint: { - // 0xffff_0000 - address: 4294901760, - // 0x0000_1000 - length: 4096 - }, - }, - // SNAX Accelerator Core Templates - snax_alu_core_template: { - isa: "rv32ima", - xssr: false, - xfrep: false, - xdma: false, - xf16: false, - xf16alt: false, - xf8: false, - xf8alt: false, - xfdotp: false, - xfvec: false, - snax_acc_cfg: { - snax_acc_name: "snax_alu", - bender_target: ["snax_alu"], - snax_narrow_tcdm_ports: 12, - snax_num_rw_csr: 3, - snax_num_ro_csr: 2, - snax_streamer_cfg: {$ref: "#/snax_alu_streamer_template" } - }, - snax_use_custom_ports: false, - num_int_outstanding_loads: 1, - num_int_outstanding_mem: 4, - num_fp_outstanding_loads: 4, - num_fp_outstanding_mem: 4, - num_sequencer_instructions: 16, - num_dtlb_entries: 1, - num_itlb_entries: 1, - // Enable division/square root unit - // Xdiv_sqrt: true, - }, - dma_core_template: { - isa: "rv32ima", - xdma: true - xssr: false - xfrep: false - xf16: false, - xf16alt: false, - xf8: false, - xf8alt: false, - xfdotp: false, - xfvec: false, - num_int_outstanding_loads: 1, - num_int_outstanding_mem: 4, - num_fp_outstanding_loads: 4, - num_fp_outstanding_mem: 4, - num_sequencer_instructions: 16, - num_dtlb_entries: 1, - num_itlb_entries: 1 - }, - // SNAX Streamer Templates - snax_alu_streamer_template :{ - - data_reader_params: { - spatial_bounds: [[4], [4]], - temporal_dim: [1, 1], - num_channel: [4, 4], - fifo_depth: [8, 8], - }, - - data_writer_params:{ - spatial_bounds: [[4]], - temporal_dim: [1], - num_channel: [4], - fifo_depth: [8], - }, - - snax_library_name: "snax-alu", - } -} diff --git a/target/rtl/cfg/cluster_cfg/snax_cgra_cluster.hjson b/target/rtl/cfg/cluster_cfg/snax_cgra_cluster.hjson deleted file mode 100644 index ca3653f76..000000000 --- a/target/rtl/cfg/cluster_cfg/snax_cgra_cluster.hjson +++ /dev/null @@ -1,170 +0,0 @@ -// Copyright 2024 KU Leuven. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -// Cluster configuration for a simple testbench system. -{ - nr_s1_quadrant: 1, - s1_quadrant: { - nr_clusters: 1, - }, - - cluster: { - name: "snax_cgra_cluster", - bender_target: ["snax_cgra_cluster"], - boot_addr: 4096, // 0x1000 - cluster_base_addr: 268435456, // 0x1000_0000 - cluster_base_offset: 1048576, // 256KB -> 1MB - cluster_base_hartid: 1, - addr_width: 48, - data_width: 64, - user_width: 3, - tcdm: { - size: 128, - banks: 32, - }, - cluster_periph_size: 64, // kB - zero_mem_size: 64, // kB - dma_data_width: 512, - dma_axi_req_fifo_depth: 3, - dma_req_fifo_depth: 3, - - // Additional parameters for Hemaia integration - narrow_trans: 4, - wide_trans: 32, - dma_user_width: 1, - // We don't need Snitch debugging in Hemaia - enable_debug: false, - // We don't need Snitch (core-internal) virtual memory support - vm_support: false, - // Memory configuration inputs - sram_cfg_expose: true, - sram_cfg_fields: { - ema: 3, - emaw: 2, - emas: 1 - }, - - // Timing parameters - timing: { - lat_comp_fp32: 3, - lat_comp_fp64: 3, - lat_comp_fp16: 2, - lat_comp_fp16_alt: 2, - lat_comp_fp8: 1, - lat_comp_fp8_alt: 1, - lat_noncomp: 1, - lat_conv: 1, - lat_sdotp: 2, - fpu_pipe_config: "BEFORE" - narrow_xbar_latency: "CUT_ALL_PORTS", - wide_xbar_latency: "CUT_ALL_PORTS", - // Isolate the core. - register_core_req: true, - register_core_rsp: true, - register_offload_req: true, - register_offload_rsp: true, - register_ext_narrow: true, - register_ext_wide: true, - }, - hives: [ - // Hive 0 - { - icache: { - size: 8, // total instruction cache size in kByte - sets: 2, // number of ways - cacheline: 256 // word size in bits - }, - cores: [ - { $ref: "#/snax_cgra_core_template" }, - { $ref: "#/dma_core_template" }, - ] - } - ] - }, - dram: { - // 0x8000_0000 - address: 2147483648, - // 0x8000_0000 - length: 2147483648 - }, - peripherals: { - clint: { - // 0xffff_0000 - address: 4294901760, - // 0x0000_1000 - length: 4096 - }, - }, - // SNAX Accelerator Core Templates - snax_cgra_core_template: { - isa: "rv32ima", - xssr: false, - xfrep: false, - xdma: false, - xf16: false, - xf16alt: false, - xf8: false, - xf8alt: false, - xfdotp: false, - xfvec: false, - snax_acc_cfg: { - snax_acc_name: "snax_cgra", - bender_target: ["cgra"], - snax_narrow_tcdm_ports: 16, - snax_num_rw_csr: 1, - snax_num_ro_csr: 4, - snax_streamer_cfg: {$ref: "#/snax_cgra_streamer_template" } - }, - snax_use_custom_ports: false, - num_int_outstanding_loads: 1, - num_int_outstanding_mem: 4, - num_fp_outstanding_loads: 4, - num_fp_outstanding_mem: 4, - num_sequencer_instructions: 16, - num_dtlb_entries: 1, - num_itlb_entries: 1, - // Enable division/square root unit - // Xdiv_sqrt: true, - }, - dma_core_template: { - isa: "rv32ima", - // Xdiv_sqrt: true, - # isa: "rv32ema", - xdma: true - xssr: false - xfrep: false - xf16: false, - xf16alt: false, - xf8: false, - xf8alt: false, - xfdotp: false, - xfvec: false, - num_int_outstanding_loads: 1, - num_int_outstanding_mem: 4, - num_fp_outstanding_loads: 4, - num_fp_outstanding_mem: 4, - num_sequencer_instructions: 16, - num_dtlb_entries: 1, - num_itlb_entries: 1, - } - // SNAX Streamer Templates - snax_cgra_streamer_template :{ - - data_reader_params: { - spatial_bounds: [[1], [1], [1], [1], [1], [1], [1], [1]], - temporal_dim: [2, 2, 2, 2, 2, 2, 2, 2], - num_channel: [1, 1, 1, 1, 1, 1, 1, 1], - fifo_depth: [8, 8, 8, 8, 8, 8, 8, 8], - }, - - data_writer_params: { - spatial_bounds: [[1], [1], [1], [1], [1], [1], [1], [1]], - temporal_dim: [2, 2, 2, 2, 2, 2, 2, 2], - num_channel: [1, 1, 1, 1, 1, 1, 1, 1], - fifo_depth: [8, 8, 8, 8, 8, 8, 8, 8], - }, - - snax_library_name: "snax-cgra", - } -} diff --git a/target/rtl/cfg/cluster_cfg/snax_dimc_cluster.hjson b/target/rtl/cfg/cluster_cfg/snax_dimc_cluster.hjson deleted file mode 100644 index 90517b6e9..000000000 --- a/target/rtl/cfg/cluster_cfg/snax_dimc_cluster.hjson +++ /dev/null @@ -1,171 +0,0 @@ -// Copyright 2024 KU Leuven. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -// Cluster configuration for a simple testbench system. -{ - nr_s1_quadrant: 1, - s1_quadrant: { - nr_clusters: 1, - }, - - cluster: { - name: "snax_dimc_cluster", - bender_target: ["snax_dimc_cluster"], - boot_addr: 4096, // 0x1000 - cluster_base_addr: 268435456, // 0x1000_0000 - cluster_base_offset: 1048576, // 256KB -> 1MB - cluster_base_hartid: 1, - addr_width: 48, - data_width: 64, - user_width: 3, - tcdm: { - size: 128, - banks: 32, - }, - cluster_periph_size: 64, // kB - zero_mem_size: 64, // kB - dma_data_width: 512, - dma_axi_req_fifo_depth: 16, - dma_req_fifo_depth: 8, - - // Additional parameters for Hemaia integration - narrow_trans: 4, - wide_trans: 32, - dma_user_width: 1, - // We don't need Snitch debugging in Hemaia - enable_debug: false, - // We don't need Snitch (core-internal) virtual memory support - vm_support: false, - // Memory configuration inputs - sram_cfg_expose: true, - sram_cfg_fields: { - ema: 3, - emaw: 2, - emas: 1 - }, - // Timing parameters - timing: { - lat_comp_fp32: 3, - lat_comp_fp64: 3, - lat_comp_fp16: 2, - lat_comp_fp16_alt: 2, - lat_comp_fp8: 1, - lat_comp_fp8_alt: 1, - lat_noncomp: 1, - lat_conv: 1, - lat_sdotp: 2, - fpu_pipe_config: "BEFORE" - narrow_xbar_latency: "CUT_ALL_PORTS", - wide_xbar_latency: "CUT_ALL_PORTS", - // Isolate the core. - register_core_req: true, - register_core_rsp: true, - register_offload_req: true, - register_offload_rsp: true, - register_ext_narrow: true, - register_ext_wide: true, - }, - hives: [ - // Hive 0 - { - icache: { - size: 8, // total instruction cache size in kByte - sets: 2, // number of ways - cacheline: 256 // word size in bits - }, - cores: [ - { $ref: "#/snax_dimc_core_template" }, - { $ref: "#/dma_core_template" }, - ] - } - ] - }, - dram: { - // 0x8000_0000 - address: 2147483648, - // 0x8000_0000 - length: 2147483648 - }, - peripherals: { - clint: { - // 0xffff_0000 - address: 4294901760, - // 0x0000_1000 - length: 4096 - }, - }, - // SNAX Accelerator Core Templates - snax_dimc_core_template: { - isa: "rv32ima", - xssr: false, - xfrep: false, - xdma: false, - xf16: false, - xf16alt: false, - xf8: false, - xf8alt: false, - xfdotp: false, - xfvec: false, - snax_acc_cfg: { - snax_acc_name: "snax_dimc", - bender_target: ["dimc"], - snax_wide_tcdm_ports: 40, - snax_num_rw_csr: 8, - snax_num_ro_csr: 0, - snax_disable_csr_manager: true, - snax_streamer_cfg: {$ref: "#/snax_dimc_streamer_template" } - }, - snax_use_custom_ports: false, - num_int_outstanding_loads: 1, - num_int_outstanding_mem: 4, - num_fp_outstanding_loads: 4, - num_fp_outstanding_mem: 4, - num_sequencer_instructions: 16, - num_dtlb_entries: 1, - num_itlb_entries: 1, - // Enable division/square root unit - // Xdiv_sqrt: true, - }, - dma_core_template: { - isa: "rv32ima", - // Xdiv_sqrt: true, - # isa: "rv32ema", - xdma: true - xssr: false - xfrep: false - xf16: false, - xf16alt: false, - xf8: false, - xf8alt: false, - xfdotp: false, - xfvec: false, - num_int_outstanding_loads: 1, - num_int_outstanding_mem: 4, - num_fp_outstanding_loads: 4, - num_fp_outstanding_mem: 4, - num_sequencer_instructions: 16, - num_dtlb_entries: 1, - num_itlb_entries: 1, - } - // SNAX Streamer Templates - snax_dimc_streamer_template :{ - - data_reader_params: { - spatial_bounds: [[8], [8], [8], [8]], - temporal_dim: [2, 2, 2, 2], - num_channel: [8, 8, 8, 8], - fifo_depth: [4, 4, 4, 4], - }, - - data_writer_params:{ - spatial_bounds: [[8]], - temporal_dim: [2], - num_channel: [8], - fifo_depth: [4], - }, - - snax_library_name: "dimc", - - } -} diff --git a/target/rtl/cfg/cluster_cfg/snax_hypercorex_cluster.hjson b/target/rtl/cfg/cluster_cfg/snax_hypercorex_cluster.hjson deleted file mode 100644 index fd7cca817..000000000 --- a/target/rtl/cfg/cluster_cfg/snax_hypercorex_cluster.hjson +++ /dev/null @@ -1,177 +0,0 @@ -// Copyright 2023 ETH Zurich and University of Bologna. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -// Cluster configuration for a simple testbench system. -{ - nr_s1_quadrant: 1, - s1_quadrant: { - nr_clusters: 1, - }, - - cluster: { - name: "snax_hypercorex_cluster", - bender_target: ["snax_hypercorex_cluster"], - boot_addr: 4096, // 0x1000 - cluster_base_addr: 268435456, // 0x1000_0000 - cluster_base_offset: 1048576, // 256KB -> 1MB - cluster_base_hartid: 1, - addr_width: 48, - data_width: 64, - user_width: 3, - tcdm: { - size: 128, // 128K -> 512K - banks: 32, - }, - cluster_periph_size: 64, // kB - zero_mem_size: 64, // kB - dma_data_width: 512, - dma_axi_req_fifo_depth: 16, - dma_req_fifo_depth: 8, - // SNAX custom cluster TCDM assignment - snax_custom_tcdm_assign: { - snax_enable_assign_tcdm_idx: true, - snax_narrow_assign_start_idx: [0,26], - snax_narrow_assign_end_idx: [1,26], - snax_wide_assign_start_idx: [2,27], - snax_wide_assign_end_idx: [25,34], - }, - // AXI bandwidth switcher - use_ax_bw_converter: false, - converted_axi_bandwidth: 256, - - // Additional parameters for Occamy Integration - narrow_trans: 4, - wide_trans: 32, - dma_user_width: 1, - // We don't need Snitch debugging in Occamy - enable_debug: false, - // We don't need Snitch (core-internal) virtual memory support - vm_support: false, - // Memory configuration inputs - sram_cfg_expose: true, - sram_cfg_fields: { - ema: 3, - emaw: 2, - emas: 1 - }, - - // Timing parameters - timing: { - lat_comp_fp32: 3, - lat_comp_fp64: 3, - lat_comp_fp16: 2, - lat_comp_fp16_alt: 2, - lat_comp_fp8: 1, - lat_comp_fp8_alt: 1, - lat_noncomp: 1, - lat_conv: 1, - lat_sdotp: 2, - fpu_pipe_config: "BEFORE" - narrow_xbar_latency: "CUT_ALL_PORTS", - wide_xbar_latency: "CUT_ALL_PORTS", - // Isolate the core. - register_core_req: true, - register_core_rsp: true, - register_offload_req: true, - register_offload_rsp: true - }, - hives: [ - // Hive 0 - { - icache: { - size: 8, // total instruction cache size in kByte - sets: 2, // number of ways - cacheline: 256 // word size in bits - }, - cores: [ - { $ref: "#/snax_hypercorex_core_template" }, - { $ref: "#/dma_core_template" }, - ] - } - ] - }, - dram: { - // 0x8000_0000 - address: 2147483648, - // 0x8000_0000 - length: 2147483648 - }, - peripherals: { - clint: { - // 0xffff_0000 - address: 4294901760, - // 0x0000_1000 - length: 4096 - }, - }, - // SNAX Accelerator Core Templates - snax_hypercorex_core_template: { - isa: "rv32ima", - xssr: false, - xfrep: false, - xdma: false, - xf16: false, - xf16alt: false, - xf8: false, - xf8alt: false, - xfdotp: false, - xfvec: false, - snax_acc_cfg: { - snax_acc_name: "snax_hypercorex", - bender_target: ["hypercorex"], - snax_narrow_tcdm_ports: 3, - snax_wide_tcdm_ports: 32, - snax_disable_csr_manager: true, - snax_streamer_cfg: {$ref: "#/snax_hypercorex_streamer_template" } - }, - snax_use_custom_ports: false, - num_int_outstanding_loads: 1, - num_int_outstanding_mem: 4, - num_fp_outstanding_loads: 4, - num_fp_outstanding_mem: 4, - num_sequencer_instructions: 16, - num_dtlb_entries: 1, - num_itlb_entries: 1, - // Enable division/square root unit - // Xdiv_sqrt: true, - }, - dma_core_template: { - isa: "rv32ima", - xdma: true - xssr: false - xfrep: false - xf16: false, - xf16alt: false, - xf8: false, - xf8alt: false, - xfdotp: false, - xfvec: false, - num_int_outstanding_loads: 1, - num_int_outstanding_mem: 4, - num_fp_outstanding_loads: 4, - num_fp_outstanding_mem: 4, - num_sequencer_instructions: 16, - num_dtlb_entries: 1, - num_itlb_entries: 1 - }, - // SNAX Streamer Templates - snax_hypercorex_streamer_template :{ - - data_reader_params: { - spatial_bounds: [[1], [1], [8], [8], [8]], - temporal_dim: [2, 2, 2, 2, 2], - num_channel: [1, 1, 8, 8, 8], - fifo_depth: [4, 4, 4, 4, 4], - }, - - data_writer_params:{ - spatial_bounds: [[1], [8]], - temporal_dim: [2, 2], - num_channel: [1, 8], - fifo_depth: [4, 4], - }, - - snax_library_name: "hypercorex", - } -} diff --git a/target/rtl/cfg/cluster_cfg/snax_minimal_cluster.hjson b/target/rtl/cfg/cluster_cfg/snax_minimal_cluster.hjson deleted file mode 100644 index a8c1a3ae4..000000000 --- a/target/rtl/cfg/cluster_cfg/snax_minimal_cluster.hjson +++ /dev/null @@ -1,107 +0,0 @@ -{ - cluster: { - name: "snax_minimal_cluster" - bender_target: ["snax_minimal_cluster"], - boot_addr: 4096, // 0x1000 - cluster_base_addr: 268435456, // 0x10000000 - cluster_base_offset: 262144 // 0x40000 - cluster_base_hartid: 1, - addr_width: 48, - data_width: 64, - user_width: 3, // clog2(total number of clusters) - tcdm: { - size: 128, // 128 kiB - banks: 32, - }, - cluster_periph_size: 64, // kB - zero_mem_size: 64, // kB - dma_data_width: 512, - dma_axi_req_fifo_depth: 16, - dma_req_fifo_depth: 8, - narrow_trans: 4, - wide_trans: 32, - dma_user_width: 1, - // We don't need Snitch debugging in Occamy - enable_debug: false, - // We don't need Snitch (core-internal) virtual memory support - vm_support: false, - // Memory configuration inputs - sram_cfg_expose: true, - sram_cfg_fields: { - ema: 3, - emaw: 2, - emas: 1 - }, - // Timing parameters - timing: { - lat_comp_fp32: 2, - lat_comp_fp64: 3, - lat_comp_fp16: 1, - lat_comp_fp16_alt: 1, - lat_comp_fp8: 1, - lat_comp_fp8_alt: 1, - lat_noncomp: 1, - lat_conv: 2, - lat_sdotp: 3, - fpu_pipe_config: "BEFORE" - narrow_xbar_latency: "CUT_ALL_PORTS", - wide_xbar_latency: "CUT_ALL_PORTS", - // Isolate the core. - register_core_req: true, - register_core_rsp: true, - register_offload_req: true, - register_offload_rsp: true, - register_fpu_req: true, - register_ext_narrow: false, - register_ext_wide: false - }, - hives: [ - // Hive 0 - { - icache: { - size: 8, // total instruction cache size in kByte - sets: 2, // number of ways - cacheline: 256 // word size in bits - }, - cores: [ - { $ref: "#/dma_core_template" } - ] - } - ], - }, - dram: { - // 0x8000_0000 - address: 2147483648, - // 0x8000_0000 - length: 2147483648 - }, - peripherals: { - clint: { - // 0xffff_0000 - address: 4294901760, - // 0x0000_1000 - length: 4096 - }, - }, - - dma_core_template: { - isa: "rv32ima", - xdma: true, - xssr: false, - xfrep: false - xf16: false, - xf16alt: false, - xf8: false, - xf8alt: false, - xfdotp: false, - xfvec: false, - num_int_outstanding_loads: 1, - num_int_outstanding_mem: 4, - num_fp_outstanding_loads: 4, - num_fp_outstanding_mem: 4, - num_sequencer_instructions: 16, - num_dtlb_entries: 1, - num_itlb_entries: 1, - }, - -} diff --git a/target/rtl/cfg/occamy_cfg/hemaia.hjson b/target/rtl/cfg/hemaia.hjson similarity index 100% rename from target/rtl/cfg/occamy_cfg/hemaia.hjson rename to target/rtl/cfg/hemaia.hjson diff --git a/target/rtl/cfg/occamy_cfg/hemaia_minimal.hjson b/target/rtl/cfg/hemaia_minimal.hjson similarity index 94% rename from target/rtl/cfg/occamy_cfg/hemaia_minimal.hjson rename to target/rtl/cfg/hemaia_minimal.hjson index a31d278b8..9fa801c94 100755 --- a/target/rtl/cfg/occamy_cfg/hemaia_minimal.hjson +++ b/target/rtl/cfg/hemaia_minimal.hjson @@ -79,7 +79,7 @@ rmq: 4, }, narrow_xbar_slv_id_width: 4, - narrow_xbar_user_width: 5, // clog2(total number of clusters) + narrow_xbar_user_width: 3, // clog2(total number of clusters) nr_s1_quadrant: 1, s1_quadrant: { // number of pending transactions on the narrow/wide network @@ -105,7 +105,7 @@ fall_through: false, }, narrow_xbar_slv_id_width: 4, - narrow_xbar_user_width: 5, // clog2(total number of clusters) + narrow_xbar_user_width: 3, // clog2(total number of clusters) cfg_base_addr: 184549376, // 0x0b000000 cfg_base_offset: 65536 // 0x10000 }, diff --git a/target/rtl/cfg/occamy_cfg/hemaia_tapeout.hjson b/target/rtl/cfg/hemaia_tapeout.hjson similarity index 100% rename from target/rtl/cfg/occamy_cfg/hemaia_tapeout.hjson rename to target/rtl/cfg/hemaia_tapeout.hjson diff --git a/target/rtl/cfg/occamy_cfg/hemaia_two_clusters.hjson b/target/rtl/cfg/hemaia_two_clusters.hjson similarity index 100% rename from target/rtl/cfg/occamy_cfg/hemaia_two_clusters.hjson rename to target/rtl/cfg/hemaia_two_clusters.hjson diff --git a/target/tapeout/Makefile b/target/tapeout/Makefile index a7b79591a..1b8adeb29 100644 --- a/target/tapeout/Makefile +++ b/target/tapeout/Makefile @@ -24,12 +24,12 @@ TARGET_RTL ?= $(ROOT)/target/rtl # (LRU) config, all targets depending on the configuration file have # to be rebuilt. This file is used to express this condition as a # prerequisite for other rules. -CFG = $(TARGET_RTL)/cfg/occamy_cfg/lru.hjson +CFG = $(TARGET_RTL)/cfg/lru.hjson $(CFG): FORCE @# If the LRU config file doesn't exist, we use the default config. @if [ ! -e $@ ] ; then \ - DEFAULT_CFG="$(TARGET_RTL)/cfg/occamy_cfg/hemaia.hjson"; \ + DEFAULT_CFG="$(TARGET_RTL)/cfg/hemaia.hjson"; \ echo "Using default config file: $$DEFAULT_CFG"; \ cp $$DEFAULT_CFG $@; \ fi diff --git a/util/hemaia/util.py b/util/hemaia/util.py index 3a279b1a1..f6f226891 100755 --- a/util/hemaia/util.py +++ b/util/hemaia/util.py @@ -36,7 +36,7 @@ def hemaia_util(): parser.add_argument( "--cfg_path", type=str, - default="../../target/rtl/cfg/occamy_cfg/lru.hjson", + default="../../target/rtl/cfg/lru.hjson", help="Path to the hemaia json file", ) @@ -76,7 +76,7 @@ def hemaia_util(): cluster_cfg_paths = [] for cluster in clusters: cluster_cfg_path = os.path.dirname(parsed_args.cfg_path) + \ - "/../cluster_cfg/" + cluster + ".hjson" + "/../../../deps/snitch_cluster/target/snitch_cluster/cfg/" + cluster + ".hjson" cluster_cfg_paths.append(cluster_cfg_path) cluster_cfgs.append(get_config(cluster_cfg_path)) else: diff --git a/util/occamygen/occamygen.py b/util/occamygen/occamygen.py index cfdf3ac17..9b1dceb55 100755 --- a/util/occamygen/occamygen.py +++ b/util/occamygen/occamygen.py @@ -164,7 +164,7 @@ def main(): # The name in the ["clusters"] corresponds to the file names in occamy/target/rtl/cfg/cluster_cfg # And each cluster is stores in cluster generator - cluster_cfg_dir = occamy_root / "target/rtl/cfg/cluster_cfg" + cluster_cfg_dir = occamy_root / "deps/snitch_cluster/target/snitch_cluster/cfg" cluster_generators = occamy.get_cluster_generators(occamy_cfg, cluster_cfg_dir) # Each cluster will be generated seperately # The generated file's name is specified in the ["name"] field of each cluster's cfg file