From 76253e638226d7b398985348061179e8989c46b3 Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Thu, 12 Dec 2024 18:30:43 +0100 Subject: [PATCH] Regenerate intrinsics --- src/intrinsic/archs.rs | 1903 +++++----------------------------------- 1 file changed, 204 insertions(+), 1699 deletions(-) diff --git a/src/intrinsic/archs.rs b/src/intrinsic/archs.rs index b8d1cde1d5d..85090bf01e8 100644 --- a/src/intrinsic/archs.rs +++ b/src/intrinsic/archs.rs @@ -1,35 +1,6 @@ // File generated by `rustc_codegen_gcc/tools/generate_intrinsics.py` // DO NOT EDIT IT! match name { - // AMDGPU - "llvm.AMDGPU.div.fixup.f32" => "__builtin_amdgpu_div_fixup", - "llvm.AMDGPU.div.fixup.f64" => "__builtin_amdgpu_div_fixup", - "llvm.AMDGPU.div.fixup.v2f64" => "__builtin_amdgpu_div_fixup", - "llvm.AMDGPU.div.fixup.v4f32" => "__builtin_amdgpu_div_fixup", - "llvm.AMDGPU.div.fmas.f32" => "__builtin_amdgpu_div_fmas", - "llvm.AMDGPU.div.fmas.f64" => "__builtin_amdgpu_div_fmas", - "llvm.AMDGPU.div.fmas.v2f64" => "__builtin_amdgpu_div_fmas", - "llvm.AMDGPU.div.fmas.v4f32" => "__builtin_amdgpu_div_fmas", - "llvm.AMDGPU.ldexp.f32" => "__builtin_amdgpu_ldexp", - "llvm.AMDGPU.ldexp.f64" => "__builtin_amdgpu_ldexp", - "llvm.AMDGPU.ldexp.v2f64" => "__builtin_amdgpu_ldexp", - "llvm.AMDGPU.ldexp.v4f32" => "__builtin_amdgpu_ldexp", - "llvm.AMDGPU.rcp.f32" => "__builtin_amdgpu_rcp", - "llvm.AMDGPU.rcp.f64" => "__builtin_amdgpu_rcp", - "llvm.AMDGPU.rcp.v2f64" => "__builtin_amdgpu_rcp", - "llvm.AMDGPU.rcp.v4f32" => "__builtin_amdgpu_rcp", - "llvm.AMDGPU.rsq.clamped.f32" => "__builtin_amdgpu_rsq_clamped", - "llvm.AMDGPU.rsq.clamped.f64" => "__builtin_amdgpu_rsq_clamped", - "llvm.AMDGPU.rsq.clamped.v2f64" => "__builtin_amdgpu_rsq_clamped", - "llvm.AMDGPU.rsq.clamped.v4f32" => "__builtin_amdgpu_rsq_clamped", - "llvm.AMDGPU.rsq.f32" => "__builtin_amdgpu_rsq", - "llvm.AMDGPU.rsq.f64" => "__builtin_amdgpu_rsq", - "llvm.AMDGPU.rsq.v2f64" => "__builtin_amdgpu_rsq", - "llvm.AMDGPU.rsq.v4f32" => "__builtin_amdgpu_rsq", - "llvm.AMDGPU.trig.preop.f32" => "__builtin_amdgpu_trig_preop", - "llvm.AMDGPU.trig.preop.f64" => "__builtin_amdgpu_trig_preop", - "llvm.AMDGPU.trig.preop.v2f64" => "__builtin_amdgpu_trig_preop", - "llvm.AMDGPU.trig.preop.v4f32" => "__builtin_amdgpu_trig_preop", // aarch64 "llvm.aarch64.chkfeat" => "__builtin_arm_chkfeat", "llvm.aarch64.dmb" => "__builtin_arm_dmb", @@ -244,8 +215,6 @@ match name { "llvm.arm.ldcl" => "__builtin_arm_ldcl", "llvm.arm.mcr" => "__builtin_arm_mcr", "llvm.arm.mcr2" => "__builtin_arm_mcr2", - "llvm.arm.mcrr" => "__builtin_arm_mcrr", - "llvm.arm.mcrr2" => "__builtin_arm_mcrr2", "llvm.arm.mrc" => "__builtin_arm_mrc", "llvm.arm.mrc2" => "__builtin_arm_mrc2", "llvm.arm.qadd" => "__builtin_arm_qadd", @@ -302,7 +271,6 @@ match name { "llvm.arm.stcl" => "__builtin_arm_stcl", "llvm.arm.sxtab16" => "__builtin_arm_sxtab16", "llvm.arm.sxtb16" => "__builtin_arm_sxtb16", - "llvm.arm.thread.pointer" => "__builtin_thread_pointer", "llvm.arm.uadd16" => "__builtin_arm_uadd16", "llvm.arm.uadd8" => "__builtin_arm_uadd8", "llvm.arm.uasx" => "__builtin_arm_uasx", @@ -340,8 +308,6 @@ match name { "llvm.bpf.preserve.field.info" => "__builtin_bpf_preserve_field_info", "llvm.bpf.preserve.type.info" => "__builtin_bpf_preserve_type_info", "llvm.bpf.pseudo" => "__builtin_bpf_pseudo", - // cuda - "llvm.cuda.syncthreads" => "__syncthreads", // dx "llvm.dx.create.handle" => "__builtin_hlsl_create_handle", // hexagon @@ -644,19 +610,10 @@ match name { "llvm.hexagon.F2.dfcmpge" => "__builtin_HEXAGON_F2_dfcmpge", "llvm.hexagon.F2.dfcmpgt" => "__builtin_HEXAGON_F2_dfcmpgt", "llvm.hexagon.F2.dfcmpuo" => "__builtin_HEXAGON_F2_dfcmpuo", - "llvm.hexagon.F2.dffixupd" => "__builtin_HEXAGON_F2_dffixupd", - "llvm.hexagon.F2.dffixupn" => "__builtin_HEXAGON_F2_dffixupn", - "llvm.hexagon.F2.dffixupr" => "__builtin_HEXAGON_F2_dffixupr", - "llvm.hexagon.F2.dffma" => "__builtin_HEXAGON_F2_dffma", - "llvm.hexagon.F2.dffma.lib" => "__builtin_HEXAGON_F2_dffma_lib", - "llvm.hexagon.F2.dffma.sc" => "__builtin_HEXAGON_F2_dffma_sc", - "llvm.hexagon.F2.dffms" => "__builtin_HEXAGON_F2_dffms", - "llvm.hexagon.F2.dffms.lib" => "__builtin_HEXAGON_F2_dffms_lib", "llvm.hexagon.F2.dfimm.n" => "__builtin_HEXAGON_F2_dfimm_n", "llvm.hexagon.F2.dfimm.p" => "__builtin_HEXAGON_F2_dfimm_p", "llvm.hexagon.F2.dfmax" => "__builtin_HEXAGON_F2_dfmax", "llvm.hexagon.F2.dfmin" => "__builtin_HEXAGON_F2_dfmin", - "llvm.hexagon.F2.dfmpy" => "__builtin_HEXAGON_F2_dfmpy", "llvm.hexagon.F2.dfmpyfix" => "__builtin_HEXAGON_F2_dfmpyfix", "llvm.hexagon.F2.dfmpyhh" => "__builtin_HEXAGON_F2_dfmpyhh", "llvm.hexagon.F2.dfmpylh" => "__builtin_HEXAGON_F2_dfmpylh", @@ -1083,7 +1040,6 @@ match name { "llvm.hexagon.S2.asr.r.vw" => "__builtin_HEXAGON_S2_asr_r_vw", "llvm.hexagon.S2.brev" => "__builtin_HEXAGON_S2_brev", "llvm.hexagon.S2.brevp" => "__builtin_HEXAGON_S2_brevp", - "llvm.hexagon.S2.cabacencbin" => "__builtin_HEXAGON_S2_cabacencbin", "llvm.hexagon.S2.cl0" => "__builtin_HEXAGON_S2_cl0", "llvm.hexagon.S2.cl0p" => "__builtin_HEXAGON_S2_cl0p", "llvm.hexagon.S2.cl1" => "__builtin_HEXAGON_S2_cl1", @@ -1252,7 +1208,6 @@ match name { "llvm.hexagon.S6.vsplatrbp" => "__builtin_HEXAGON_S6_vsplatrbp", "llvm.hexagon.S6.vtrunehb.ppp" => "__builtin_HEXAGON_S6_vtrunehb_ppp", "llvm.hexagon.S6.vtrunohb.ppp" => "__builtin_HEXAGON_S6_vtrunohb_ppp", - "llvm.hexagon.SI.to.SXTHI.asrh" => "__builtin_SI_to_SXTHI_asrh", "llvm.hexagon.V6.extractw" => "__builtin_HEXAGON_V6_extractw", "llvm.hexagon.V6.extractw.128B" => "__builtin_HEXAGON_V6_extractw_128B", "llvm.hexagon.V6.hi" => "__builtin_HEXAGON_V6_hi", @@ -1572,9 +1527,9 @@ match name { "llvm.hexagon.V6.vdd0" => "__builtin_HEXAGON_V6_vdd0", "llvm.hexagon.V6.vdd0.128B" => "__builtin_HEXAGON_V6_vdd0_128B", "llvm.hexagon.V6.vdealb" => "__builtin_HEXAGON_V6_vdealb", - "llvm.hexagon.V6.vdealb.128B" => "__builtin_HEXAGON_V6_vdealb_128B", "llvm.hexagon.V6.vdealb4w" => "__builtin_HEXAGON_V6_vdealb4w", "llvm.hexagon.V6.vdealb4w.128B" => "__builtin_HEXAGON_V6_vdealb4w_128B", + "llvm.hexagon.V6.vdealb.128B" => "__builtin_HEXAGON_V6_vdealb_128B", "llvm.hexagon.V6.vdealh" => "__builtin_HEXAGON_V6_vdealh", "llvm.hexagon.V6.vdealh.128B" => "__builtin_HEXAGON_V6_vdealh_128B", "llvm.hexagon.V6.vdealvdd" => "__builtin_HEXAGON_V6_vdealvdd", @@ -1763,14 +1718,6 @@ match name { "llvm.hexagon.V6.vlsrwv.128B" => "__builtin_HEXAGON_V6_vlsrwv_128B", "llvm.hexagon.V6.vlut4" => "__builtin_HEXAGON_V6_vlut4", "llvm.hexagon.V6.vlut4.128B" => "__builtin_HEXAGON_V6_vlut4_128B", - "llvm.hexagon.V6.vlutb" => "__builtin_HEXAGON_V6_vlutb", - "llvm.hexagon.V6.vlutb.128B" => "__builtin_HEXAGON_V6_vlutb_128B", - "llvm.hexagon.V6.vlutb.acc" => "__builtin_HEXAGON_V6_vlutb_acc", - "llvm.hexagon.V6.vlutb.acc.128B" => "__builtin_HEXAGON_V6_vlutb_acc_128B", - "llvm.hexagon.V6.vlutb.dv" => "__builtin_HEXAGON_V6_vlutb_dv", - "llvm.hexagon.V6.vlutb.dv.128B" => "__builtin_HEXAGON_V6_vlutb_dv_128B", - "llvm.hexagon.V6.vlutb.dv.acc" => "__builtin_HEXAGON_V6_vlutb_dv_acc", - "llvm.hexagon.V6.vlutb.dv.acc.128B" => "__builtin_HEXAGON_V6_vlutb_dv_acc_128B", "llvm.hexagon.V6.vlutvvb" => "__builtin_HEXAGON_V6_vlutvvb", "llvm.hexagon.V6.vlutvvb.128B" => "__builtin_HEXAGON_V6_vlutvvb_128B", "llvm.hexagon.V6.vlutvvb.nm" => "__builtin_HEXAGON_V6_vlutvvb_nm", @@ -2246,17 +2193,6 @@ match name { "llvm.hexagon.Y6.dmresume" => "__builtin_HEXAGON_Y6_dmresume", "llvm.hexagon.Y6.dmstart" => "__builtin_HEXAGON_Y6_dmstart", "llvm.hexagon.Y6.dmwait" => "__builtin_HEXAGON_Y6_dmwait", - "llvm.hexagon.brev.ldb" => "__builtin_brev_ldb", - "llvm.hexagon.brev.ldd" => "__builtin_brev_ldd", - "llvm.hexagon.brev.ldh" => "__builtin_brev_ldh", - "llvm.hexagon.brev.ldub" => "__builtin_brev_ldub", - "llvm.hexagon.brev.lduh" => "__builtin_brev_lduh", - "llvm.hexagon.brev.ldw" => "__builtin_brev_ldw", - "llvm.hexagon.brev.stb" => "__builtin_brev_stb", - "llvm.hexagon.brev.std" => "__builtin_brev_std", - "llvm.hexagon.brev.sth" => "__builtin_brev_sth", - "llvm.hexagon.brev.sthhi" => "__builtin_brev_sthhi", - "llvm.hexagon.brev.stw" => "__builtin_brev_stw", "llvm.hexagon.circ.ldb" => "__builtin_circ_ldb", "llvm.hexagon.circ.ldd" => "__builtin_circ_ldd", "llvm.hexagon.circ.ldh" => "__builtin_circ_ldh", @@ -2268,7 +2204,6 @@ match name { "llvm.hexagon.circ.sth" => "__builtin_circ_sth", "llvm.hexagon.circ.sthhi" => "__builtin_circ_sthhi", "llvm.hexagon.circ.stw" => "__builtin_circ_stw", - "llvm.hexagon.mm256i.vaddw" => "__builtin__mm256i_vaddw", "llvm.hexagon.prefetch" => "__builtin_HEXAGON_prefetch", "llvm.hexagon.vmemcpy" => "__builtin_hexagon_vmemcpy", "llvm.hexagon.vmemset" => "__builtin_hexagon_vmemset", @@ -2771,14 +2706,14 @@ match name { "llvm.loongarch.lasx.xvpickod.d" => "__builtin_lasx_xvpickod_d", "llvm.loongarch.lasx.xvpickod.h" => "__builtin_lasx_xvpickod_h", "llvm.loongarch.lasx.xvpickod.w" => "__builtin_lasx_xvpickod_w", - "llvm.loongarch.lasx.xvpickve.d" => "__builtin_lasx_xvpickve_d", - "llvm.loongarch.lasx.xvpickve.d.f" => "__builtin_lasx_xvpickve_d_f", - "llvm.loongarch.lasx.xvpickve.w" => "__builtin_lasx_xvpickve_w", - "llvm.loongarch.lasx.xvpickve.w.f" => "__builtin_lasx_xvpickve_w_f", "llvm.loongarch.lasx.xvpickve2gr.d" => "__builtin_lasx_xvpickve2gr_d", "llvm.loongarch.lasx.xvpickve2gr.du" => "__builtin_lasx_xvpickve2gr_du", "llvm.loongarch.lasx.xvpickve2gr.w" => "__builtin_lasx_xvpickve2gr_w", "llvm.loongarch.lasx.xvpickve2gr.wu" => "__builtin_lasx_xvpickve2gr_wu", + "llvm.loongarch.lasx.xvpickve.d" => "__builtin_lasx_xvpickve_d", + "llvm.loongarch.lasx.xvpickve.d.f" => "__builtin_lasx_xvpickve_d_f", + "llvm.loongarch.lasx.xvpickve.w" => "__builtin_lasx_xvpickve_w", + "llvm.loongarch.lasx.xvpickve.w.f" => "__builtin_lasx_xvpickve_w_f", "llvm.loongarch.lasx.xvrepl128vei.b" => "__builtin_lasx_xvrepl128vei_b", "llvm.loongarch.lasx.xvrepl128vei.d" => "__builtin_lasx_xvrepl128vei_d", "llvm.loongarch.lasx.xvrepl128vei.h" => "__builtin_lasx_xvrepl128vei_h", @@ -2791,15 +2726,15 @@ match name { "llvm.loongarch.lasx.xvrepli.d" => "__builtin_lasx_xvrepli_d", "llvm.loongarch.lasx.xvrepli.h" => "__builtin_lasx_xvrepli_h", "llvm.loongarch.lasx.xvrepli.w" => "__builtin_lasx_xvrepli_w", - "llvm.loongarch.lasx.xvreplve.b" => "__builtin_lasx_xvreplve_b", - "llvm.loongarch.lasx.xvreplve.d" => "__builtin_lasx_xvreplve_d", - "llvm.loongarch.lasx.xvreplve.h" => "__builtin_lasx_xvreplve_h", - "llvm.loongarch.lasx.xvreplve.w" => "__builtin_lasx_xvreplve_w", "llvm.loongarch.lasx.xvreplve0.b" => "__builtin_lasx_xvreplve0_b", "llvm.loongarch.lasx.xvreplve0.d" => "__builtin_lasx_xvreplve0_d", "llvm.loongarch.lasx.xvreplve0.h" => "__builtin_lasx_xvreplve0_h", "llvm.loongarch.lasx.xvreplve0.q" => "__builtin_lasx_xvreplve0_q", "llvm.loongarch.lasx.xvreplve0.w" => "__builtin_lasx_xvreplve0_w", + "llvm.loongarch.lasx.xvreplve.b" => "__builtin_lasx_xvreplve_b", + "llvm.loongarch.lasx.xvreplve.d" => "__builtin_lasx_xvreplve_d", + "llvm.loongarch.lasx.xvreplve.h" => "__builtin_lasx_xvreplve_h", + "llvm.loongarch.lasx.xvreplve.w" => "__builtin_lasx_xvreplve_w", "llvm.loongarch.lasx.xvrotr.b" => "__builtin_lasx_xvrotr_b", "llvm.loongarch.lasx.xvrotr.d" => "__builtin_lasx_xvrotr_d", "llvm.loongarch.lasx.xvrotr.h" => "__builtin_lasx_xvrotr_h", @@ -2832,14 +2767,14 @@ match name { "llvm.loongarch.lasx.xvseqi.d" => "__builtin_lasx_xvseqi_d", "llvm.loongarch.lasx.xvseqi.h" => "__builtin_lasx_xvseqi_h", "llvm.loongarch.lasx.xvseqi.w" => "__builtin_lasx_xvseqi_w", - "llvm.loongarch.lasx.xvshuf.b" => "__builtin_lasx_xvshuf_b", - "llvm.loongarch.lasx.xvshuf.d" => "__builtin_lasx_xvshuf_d", - "llvm.loongarch.lasx.xvshuf.h" => "__builtin_lasx_xvshuf_h", - "llvm.loongarch.lasx.xvshuf.w" => "__builtin_lasx_xvshuf_w", "llvm.loongarch.lasx.xvshuf4i.b" => "__builtin_lasx_xvshuf4i_b", "llvm.loongarch.lasx.xvshuf4i.d" => "__builtin_lasx_xvshuf4i_d", "llvm.loongarch.lasx.xvshuf4i.h" => "__builtin_lasx_xvshuf4i_h", "llvm.loongarch.lasx.xvshuf4i.w" => "__builtin_lasx_xvshuf4i_w", + "llvm.loongarch.lasx.xvshuf.b" => "__builtin_lasx_xvshuf_b", + "llvm.loongarch.lasx.xvshuf.d" => "__builtin_lasx_xvshuf_d", + "llvm.loongarch.lasx.xvshuf.h" => "__builtin_lasx_xvshuf_h", + "llvm.loongarch.lasx.xvshuf.w" => "__builtin_lasx_xvshuf_w", "llvm.loongarch.lasx.xvsigncov.b" => "__builtin_lasx_xvsigncov_b", "llvm.loongarch.lasx.xvsigncov.d" => "__builtin_lasx_xvsigncov_d", "llvm.loongarch.lasx.xvsigncov.h" => "__builtin_lasx_xvsigncov_h", @@ -3554,14 +3489,14 @@ match name { "llvm.loongarch.lsx.vseqi.d" => "__builtin_lsx_vseqi_d", "llvm.loongarch.lsx.vseqi.h" => "__builtin_lsx_vseqi_h", "llvm.loongarch.lsx.vseqi.w" => "__builtin_lsx_vseqi_w", - "llvm.loongarch.lsx.vshuf.b" => "__builtin_lsx_vshuf_b", - "llvm.loongarch.lsx.vshuf.d" => "__builtin_lsx_vshuf_d", - "llvm.loongarch.lsx.vshuf.h" => "__builtin_lsx_vshuf_h", - "llvm.loongarch.lsx.vshuf.w" => "__builtin_lsx_vshuf_w", "llvm.loongarch.lsx.vshuf4i.b" => "__builtin_lsx_vshuf4i_b", "llvm.loongarch.lsx.vshuf4i.d" => "__builtin_lsx_vshuf4i_d", "llvm.loongarch.lsx.vshuf4i.h" => "__builtin_lsx_vshuf4i_h", "llvm.loongarch.lsx.vshuf4i.w" => "__builtin_lsx_vshuf4i_w", + "llvm.loongarch.lsx.vshuf.b" => "__builtin_lsx_vshuf_b", + "llvm.loongarch.lsx.vshuf.d" => "__builtin_lsx_vshuf_d", + "llvm.loongarch.lsx.vshuf.h" => "__builtin_lsx_vshuf_h", + "llvm.loongarch.lsx.vshuf.w" => "__builtin_lsx_vshuf_w", "llvm.loongarch.lsx.vsigncov.b" => "__builtin_lsx_vsigncov_b", "llvm.loongarch.lsx.vsigncov.d" => "__builtin_lsx_vsigncov_d", "llvm.loongarch.lsx.vsigncov.h" => "__builtin_lsx_vsigncov_h", @@ -4447,8 +4382,6 @@ match name { // nvvm "llvm.nvvm.abs.bf16" => "__nvvm_abs_bf16", "llvm.nvvm.abs.bf16x2" => "__nvvm_abs_bf16x2", - "llvm.nvvm.abs.i" => "__nvvm_abs_i", - "llvm.nvvm.abs.ll" => "__nvvm_abs_ll", "llvm.nvvm.activemask" => "__nvvm_activemask", "llvm.nvvm.add.rm.d" => "__nvvm_add_rm_d", "llvm.nvvm.add.rm.f" => "__nvvm_add_rm_f", @@ -4465,27 +4398,22 @@ match name { "llvm.nvvm.bar.sync" => "__nvvm_bar_sync", "llvm.nvvm.bar.warp.sync" => "__nvvm_bar_warp_sync", "llvm.nvvm.barrier" => "__nvvm_bar", - "llvm.nvvm.barrier.n" => "__nvvm_bar_n", - "llvm.nvvm.barrier.sync" => "__nvvm_barrier_sync", - "llvm.nvvm.barrier.sync.cnt" => "__nvvm_barrier_sync_cnt", "llvm.nvvm.barrier0" => "__syncthreads", - // [DUPLICATE]: "llvm.nvvm.barrier0" => "__nvvm_bar0", "llvm.nvvm.barrier0.and" => "__nvvm_bar0_and", "llvm.nvvm.barrier0.or" => "__nvvm_bar0_or", "llvm.nvvm.barrier0.popc" => "__nvvm_bar0_popc", + "llvm.nvvm.barrier.n" => "__nvvm_bar_n", + "llvm.nvvm.barrier.sync" => "__nvvm_barrier_sync", + "llvm.nvvm.barrier.sync.cnt" => "__nvvm_barrier_sync_cnt", "llvm.nvvm.bf2h.rn" => "__nvvm_bf2h_rn", "llvm.nvvm.bf2h.rn.ftz" => "__nvvm_bf2h_rn_ftz", "llvm.nvvm.bitcast.d2ll" => "__nvvm_bitcast_d2ll", "llvm.nvvm.bitcast.f2i" => "__nvvm_bitcast_f2i", "llvm.nvvm.bitcast.i2f" => "__nvvm_bitcast_i2f", "llvm.nvvm.bitcast.ll2d" => "__nvvm_bitcast_ll2d", - "llvm.nvvm.brev32" => "__nvvm_brev32", - "llvm.nvvm.brev64" => "__nvvm_brev64", "llvm.nvvm.ceil.d" => "__nvvm_ceil_d", "llvm.nvvm.ceil.f" => "__nvvm_ceil_f", "llvm.nvvm.ceil.ftz.f" => "__nvvm_ceil_ftz_f", - "llvm.nvvm.clz.i" => "__nvvm_clz_i", - "llvm.nvvm.clz.ll" => "__nvvm_clz_ll", "llvm.nvvm.cos.approx.f" => "__nvvm_cos_approx_f", "llvm.nvvm.cos.approx.ftz.f" => "__nvvm_cos_approx_ftz_f", "llvm.nvvm.cp.async.commit.group" => "__nvvm_cp_async_commit_group", @@ -4535,18 +4463,10 @@ match name { "llvm.nvvm.div.rz.d" => "__nvvm_div_rz_d", "llvm.nvvm.div.rz.f" => "__nvvm_div_rz_f", "llvm.nvvm.div.rz.ftz.f" => "__nvvm_div_rz_ftz_f", - "llvm.nvvm.e4m3x2.to.f16x2.rn" => "__nvvm_e4m3x2_to_f16x2_rn", - "llvm.nvvm.e4m3x2.to.f16x2.rn.relu" => "__nvvm_e4m3x2_to_f16x2_rn_relu", - "llvm.nvvm.e5m2x2.to.f16x2.rn" => "__nvvm_e5m2x2_to_f16x2_rn", - "llvm.nvvm.e5m2x2.to.f16x2.rn.relu" => "__nvvm_e5m2x2_to_f16x2_rn_relu", "llvm.nvvm.ex2.approx.d" => "__nvvm_ex2_approx_d", "llvm.nvvm.ex2.approx.f" => "__nvvm_ex2_approx_f", "llvm.nvvm.ex2.approx.ftz.f" => "__nvvm_ex2_approx_ftz_f", "llvm.nvvm.exit" => "__nvvm_exit", - "llvm.nvvm.f16x2.to.e4m3x2.rn" => "__nvvm_f16x2_to_e4m3x2_rn", - "llvm.nvvm.f16x2.to.e4m3x2.rn.relu" => "__nvvm_f16x2_to_e4m3x2_rn_relu", - "llvm.nvvm.f16x2.to.e5m2x2.rn" => "__nvvm_f16x2_to_e5m2x2_rn", - "llvm.nvvm.f16x2.to.e5m2x2.rn.relu" => "__nvvm_f16x2_to_e5m2x2_rn_relu", "llvm.nvvm.f2bf16.rn" => "__nvvm_f2bf16_rn", "llvm.nvvm.f2bf16.rn.relu" => "__nvvm_f2bf16_rn_relu", "llvm.nvvm.f2bf16.rz" => "__nvvm_f2bf16_rz", @@ -4589,10 +4509,6 @@ match name { "llvm.nvvm.fabs.d" => "__nvvm_fabs_d", "llvm.nvvm.fabs.f" => "__nvvm_fabs_f", "llvm.nvvm.fabs.ftz.f" => "__nvvm_fabs_ftz_f", - "llvm.nvvm.ff.to.e4m3x2.rn" => "__nvvm_ff_to_e4m3x2_rn", - "llvm.nvvm.ff.to.e4m3x2.rn.relu" => "__nvvm_ff_to_e4m3x2_rn_relu", - "llvm.nvvm.ff.to.e5m2x2.rn" => "__nvvm_ff_to_e5m2x2_rn", - "llvm.nvvm.ff.to.e5m2x2.rn.relu" => "__nvvm_ff_to_e5m2x2_rn_relu", "llvm.nvvm.ff2bf16x2.rn" => "__nvvm_ff2bf16x2_rn", "llvm.nvvm.ff2bf16x2.rn.relu" => "__nvvm_ff2bf16x2_rn_relu", "llvm.nvvm.ff2bf16x2.rz" => "__nvvm_ff2bf16x2_rz", @@ -4679,7 +4595,6 @@ match name { "llvm.nvvm.fmin.xorsign.abs.bf16x2" => "__nvvm_fmin_xorsign_abs_bf16x2", "llvm.nvvm.fmin.xorsign.abs.f" => "__nvvm_fmin_xorsign_abs_f", "llvm.nvvm.fns" => "__nvvm_fns", - "llvm.nvvm.h2f" => "__nvvm_h2f", "llvm.nvvm.i2d.rm" => "__nvvm_i2d_rm", "llvm.nvvm.i2d.rn" => "__nvvm_i2d_rn", "llvm.nvvm.i2d.rp" => "__nvvm_i2d_rp", @@ -4709,10 +4624,6 @@ match name { "llvm.nvvm.lohi.i2d" => "__nvvm_lohi_i2d", "llvm.nvvm.match.any.sync.i32" => "__nvvm_match_any_sync_i32", "llvm.nvvm.match.any.sync.i64" => "__nvvm_match_any_sync_i64", - "llvm.nvvm.max.i" => "__nvvm_max_i", - "llvm.nvvm.max.ll" => "__nvvm_max_ll", - "llvm.nvvm.max.ui" => "__nvvm_max_ui", - "llvm.nvvm.max.ull" => "__nvvm_max_ull", "llvm.nvvm.mbarrier.arrive" => "__nvvm_mbarrier_arrive", "llvm.nvvm.mbarrier.arrive.drop" => "__nvvm_mbarrier_arrive_drop", "llvm.nvvm.mbarrier.arrive.drop.noComplete" => "__nvvm_mbarrier_arrive_drop_noComplete", @@ -4731,10 +4642,8 @@ match name { "llvm.nvvm.membar.cta" => "__nvvm_membar_cta", "llvm.nvvm.membar.gl" => "__nvvm_membar_gl", "llvm.nvvm.membar.sys" => "__nvvm_membar_sys", - "llvm.nvvm.min.i" => "__nvvm_min_i", - "llvm.nvvm.min.ll" => "__nvvm_min_ll", - "llvm.nvvm.min.ui" => "__nvvm_min_ui", - "llvm.nvvm.min.ull" => "__nvvm_min_ull", + "llvm.nvvm.mul24.i" => "__nvvm_mul24_i", + "llvm.nvvm.mul24.ui" => "__nvvm_mul24_ui", "llvm.nvvm.mul.rm.d" => "__nvvm_mul_rm_d", "llvm.nvvm.mul.rm.f" => "__nvvm_mul_rm_f", "llvm.nvvm.mul.rm.ftz.f" => "__nvvm_mul_rm_ftz_f", @@ -4747,8 +4656,6 @@ match name { "llvm.nvvm.mul.rz.d" => "__nvvm_mul_rz_d", "llvm.nvvm.mul.rz.f" => "__nvvm_mul_rz_f", "llvm.nvvm.mul.rz.ftz.f" => "__nvvm_mul_rz_ftz_f", - "llvm.nvvm.mul24.i" => "__nvvm_mul24_i", - "llvm.nvvm.mul24.ui" => "__nvvm_mul24_ui", "llvm.nvvm.mulhi.i" => "__nvvm_mulhi_i", "llvm.nvvm.mulhi.ll" => "__nvvm_mulhi_ll", "llvm.nvvm.mulhi.s" => "__nvvm_mulhi_s", @@ -4758,8 +4665,6 @@ match name { "llvm.nvvm.nanosleep" => "__nvvm_nanosleep", "llvm.nvvm.neg.bf16" => "__nvvm_neg_bf16", "llvm.nvvm.neg.bf16x2" => "__nvvm_neg_bf16x2", - "llvm.nvvm.popc.i" => "__nvvm_popc_i", - "llvm.nvvm.popc.ll" => "__nvvm_popc_ll", "llvm.nvvm.prmt" => "__nvvm_prmt", "llvm.nvvm.rcp.approx.ftz.d" => "__nvvm_rcp_approx_ftz_d", "llvm.nvvm.rcp.approx.ftz.f" => "__nvvm_rcp_approx_ftz_f", @@ -4776,9 +4681,7 @@ match name { "llvm.nvvm.rcp.rz.f" => "__nvvm_rcp_rz_f", "llvm.nvvm.rcp.rz.ftz.f" => "__nvvm_rcp_rz_ftz_f", "llvm.nvvm.read.ptx.sreg.clock" => "__nvvm_read_ptx_sreg_clock", - // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.clock" => "__nvvm_read_ptx_sreg_", "llvm.nvvm.read.ptx.sreg.clock64" => "__nvvm_read_ptx_sreg_clock64", - // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.clock64" => "__nvvm_read_ptx_sreg_", "llvm.nvvm.read.ptx.sreg.ctaid.w" => "__nvvm_read_ptx_sreg_ctaid_w", "llvm.nvvm.read.ptx.sreg.ctaid.x" => "__nvvm_read_ptx_sreg_ctaid_x", "llvm.nvvm.read.ptx.sreg.ctaid.y" => "__nvvm_read_ptx_sreg_ctaid_y", @@ -4817,49 +4720,33 @@ match name { "llvm.nvvm.read.ptx.sreg.envreg9" => "__nvvm_read_ptx_sreg_envreg9", "llvm.nvvm.read.ptx.sreg.globaltimer" => "__nvvm_read_ptx_sreg_globaltimer", "llvm.nvvm.read.ptx.sreg.gridid" => "__nvvm_read_ptx_sreg_gridid", - // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.gridid" => "__nvvm_read_ptx_sreg_", "llvm.nvvm.read.ptx.sreg.laneid" => "__nvvm_read_ptx_sreg_laneid", - // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.laneid" => "__nvvm_read_ptx_sreg_", "llvm.nvvm.read.ptx.sreg.lanemask.eq" => "__nvvm_read_ptx_sreg_lanemask_eq", - // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.lanemask.eq" => "__nvvm_read_ptx_sreg_", "llvm.nvvm.read.ptx.sreg.lanemask.ge" => "__nvvm_read_ptx_sreg_lanemask_ge", - // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.lanemask.ge" => "__nvvm_read_ptx_sreg_", "llvm.nvvm.read.ptx.sreg.lanemask.gt" => "__nvvm_read_ptx_sreg_lanemask_gt", - // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.lanemask.gt" => "__nvvm_read_ptx_sreg_", "llvm.nvvm.read.ptx.sreg.lanemask.le" => "__nvvm_read_ptx_sreg_lanemask_le", - // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.lanemask.le" => "__nvvm_read_ptx_sreg_", "llvm.nvvm.read.ptx.sreg.lanemask.lt" => "__nvvm_read_ptx_sreg_lanemask_lt", - // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.lanemask.lt" => "__nvvm_read_ptx_sreg_", "llvm.nvvm.read.ptx.sreg.nctaid.w" => "__nvvm_read_ptx_sreg_nctaid_w", "llvm.nvvm.read.ptx.sreg.nctaid.x" => "__nvvm_read_ptx_sreg_nctaid_x", "llvm.nvvm.read.ptx.sreg.nctaid.y" => "__nvvm_read_ptx_sreg_nctaid_y", "llvm.nvvm.read.ptx.sreg.nctaid.z" => "__nvvm_read_ptx_sreg_nctaid_z", "llvm.nvvm.read.ptx.sreg.nsmid" => "__nvvm_read_ptx_sreg_nsmid", - // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.nsmid" => "__nvvm_read_ptx_sreg_", "llvm.nvvm.read.ptx.sreg.ntid.w" => "__nvvm_read_ptx_sreg_ntid_w", "llvm.nvvm.read.ptx.sreg.ntid.x" => "__nvvm_read_ptx_sreg_ntid_x", "llvm.nvvm.read.ptx.sreg.ntid.y" => "__nvvm_read_ptx_sreg_ntid_y", "llvm.nvvm.read.ptx.sreg.ntid.z" => "__nvvm_read_ptx_sreg_ntid_z", "llvm.nvvm.read.ptx.sreg.nwarpid" => "__nvvm_read_ptx_sreg_nwarpid", - // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.nwarpid" => "__nvvm_read_ptx_sreg_", "llvm.nvvm.read.ptx.sreg.pm0" => "__nvvm_read_ptx_sreg_pm0", - // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.pm0" => "__nvvm_read_ptx_sreg_", "llvm.nvvm.read.ptx.sreg.pm1" => "__nvvm_read_ptx_sreg_pm1", - // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.pm1" => "__nvvm_read_ptx_sreg_", "llvm.nvvm.read.ptx.sreg.pm2" => "__nvvm_read_ptx_sreg_pm2", - // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.pm2" => "__nvvm_read_ptx_sreg_", "llvm.nvvm.read.ptx.sreg.pm3" => "__nvvm_read_ptx_sreg_pm3", - // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.pm3" => "__nvvm_read_ptx_sreg_", "llvm.nvvm.read.ptx.sreg.smid" => "__nvvm_read_ptx_sreg_smid", - // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.smid" => "__nvvm_read_ptx_sreg_", "llvm.nvvm.read.ptx.sreg.tid.w" => "__nvvm_read_ptx_sreg_tid_w", "llvm.nvvm.read.ptx.sreg.tid.x" => "__nvvm_read_ptx_sreg_tid_x", "llvm.nvvm.read.ptx.sreg.tid.y" => "__nvvm_read_ptx_sreg_tid_y", "llvm.nvvm.read.ptx.sreg.tid.z" => "__nvvm_read_ptx_sreg_tid_z", "llvm.nvvm.read.ptx.sreg.warpid" => "__nvvm_read_ptx_sreg_warpid", - // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.warpid" => "__nvvm_read_ptx_sreg_", "llvm.nvvm.read.ptx.sreg.warpsize" => "__nvvm_read_ptx_sreg_warpsize", - // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.warpsize" => "__nvvm_read_ptx_sreg_", "llvm.nvvm.redux.sync.add" => "__nvvm_redux_sync_add", "llvm.nvvm.redux.sync.and" => "__nvvm_redux_sync_and", "llvm.nvvm.redux.sync.max" => "__nvvm_redux_sync_max", @@ -5176,8 +5063,6 @@ match name { // ppc "llvm.ppc.addex" => "__builtin_ppc_addex", "llvm.ppc.addf128.round.to.odd" => "__builtin_addf128_round_to_odd", - "llvm.ppc.addg6s" => "__builtin_addg6s", - "llvm.ppc.addg6sd" => "__builtin_ppc_addg6s", "llvm.ppc.altivec.crypto.vcipher" => "__builtin_altivec_crypto_vcipher", "llvm.ppc.altivec.crypto.vcipherlast" => "__builtin_altivec_crypto_vcipherlast", "llvm.ppc.altivec.crypto.vncipher" => "__builtin_altivec_crypto_vncipher", @@ -5475,10 +5360,6 @@ match name { "llvm.ppc.bcdsub" => "__builtin_ppc_bcdsub", "llvm.ppc.bcdsub.p" => "__builtin_ppc_bcdsub_p", "llvm.ppc.bpermd" => "__builtin_bpermd", - "llvm.ppc.cbcdtd" => "__builtin_cbcdtd", - "llvm.ppc.cbcdtdd" => "__builtin_ppc_cbcdtd", - "llvm.ppc.cdtbcd" => "__builtin_cdtbcd", - "llvm.ppc.cdtbcdd" => "__builtin_ppc_cdtbcd", "llvm.ppc.cfuged" => "__builtin_cfuged", "llvm.ppc.cmpeqb" => "__builtin_ppc_cmpeqb", "llvm.ppc.cmprb" => "__builtin_ppc_cmprb", @@ -5561,89 +5442,6 @@ match name { "llvm.ppc.pack.longdouble" => "__builtin_pack_longdouble", "llvm.ppc.pdepd" => "__builtin_pdepd", "llvm.ppc.pextd" => "__builtin_pextd", - "llvm.ppc.qpx.qvfabs" => "__builtin_qpx_qvfabs", - "llvm.ppc.qpx.qvfadd" => "__builtin_qpx_qvfadd", - "llvm.ppc.qpx.qvfadds" => "__builtin_qpx_qvfadds", - "llvm.ppc.qpx.qvfcfid" => "__builtin_qpx_qvfcfid", - "llvm.ppc.qpx.qvfcfids" => "__builtin_qpx_qvfcfids", - "llvm.ppc.qpx.qvfcfidu" => "__builtin_qpx_qvfcfidu", - "llvm.ppc.qpx.qvfcfidus" => "__builtin_qpx_qvfcfidus", - "llvm.ppc.qpx.qvfcmpeq" => "__builtin_qpx_qvfcmpeq", - "llvm.ppc.qpx.qvfcmpgt" => "__builtin_qpx_qvfcmpgt", - "llvm.ppc.qpx.qvfcmplt" => "__builtin_qpx_qvfcmplt", - "llvm.ppc.qpx.qvfcpsgn" => "__builtin_qpx_qvfcpsgn", - "llvm.ppc.qpx.qvfctid" => "__builtin_qpx_qvfctid", - "llvm.ppc.qpx.qvfctidu" => "__builtin_qpx_qvfctidu", - "llvm.ppc.qpx.qvfctiduz" => "__builtin_qpx_qvfctiduz", - "llvm.ppc.qpx.qvfctidz" => "__builtin_qpx_qvfctidz", - "llvm.ppc.qpx.qvfctiw" => "__builtin_qpx_qvfctiw", - "llvm.ppc.qpx.qvfctiwu" => "__builtin_qpx_qvfctiwu", - "llvm.ppc.qpx.qvfctiwuz" => "__builtin_qpx_qvfctiwuz", - "llvm.ppc.qpx.qvfctiwz" => "__builtin_qpx_qvfctiwz", - "llvm.ppc.qpx.qvflogical" => "__builtin_qpx_qvflogical", - "llvm.ppc.qpx.qvfmadd" => "__builtin_qpx_qvfmadd", - "llvm.ppc.qpx.qvfmadds" => "__builtin_qpx_qvfmadds", - "llvm.ppc.qpx.qvfmsub" => "__builtin_qpx_qvfmsub", - "llvm.ppc.qpx.qvfmsubs" => "__builtin_qpx_qvfmsubs", - "llvm.ppc.qpx.qvfmul" => "__builtin_qpx_qvfmul", - "llvm.ppc.qpx.qvfmuls" => "__builtin_qpx_qvfmuls", - "llvm.ppc.qpx.qvfnabs" => "__builtin_qpx_qvfnabs", - "llvm.ppc.qpx.qvfneg" => "__builtin_qpx_qvfneg", - "llvm.ppc.qpx.qvfnmadd" => "__builtin_qpx_qvfnmadd", - "llvm.ppc.qpx.qvfnmadds" => "__builtin_qpx_qvfnmadds", - "llvm.ppc.qpx.qvfnmsub" => "__builtin_qpx_qvfnmsub", - "llvm.ppc.qpx.qvfnmsubs" => "__builtin_qpx_qvfnmsubs", - "llvm.ppc.qpx.qvfperm" => "__builtin_qpx_qvfperm", - "llvm.ppc.qpx.qvfre" => "__builtin_qpx_qvfre", - "llvm.ppc.qpx.qvfres" => "__builtin_qpx_qvfres", - "llvm.ppc.qpx.qvfrim" => "__builtin_qpx_qvfrim", - "llvm.ppc.qpx.qvfrin" => "__builtin_qpx_qvfrin", - "llvm.ppc.qpx.qvfrip" => "__builtin_qpx_qvfrip", - "llvm.ppc.qpx.qvfriz" => "__builtin_qpx_qvfriz", - "llvm.ppc.qpx.qvfrsp" => "__builtin_qpx_qvfrsp", - "llvm.ppc.qpx.qvfrsqrte" => "__builtin_qpx_qvfrsqrte", - "llvm.ppc.qpx.qvfrsqrtes" => "__builtin_qpx_qvfrsqrtes", - "llvm.ppc.qpx.qvfsel" => "__builtin_qpx_qvfsel", - "llvm.ppc.qpx.qvfsub" => "__builtin_qpx_qvfsub", - "llvm.ppc.qpx.qvfsubs" => "__builtin_qpx_qvfsubs", - "llvm.ppc.qpx.qvftstnan" => "__builtin_qpx_qvftstnan", - "llvm.ppc.qpx.qvfxmadd" => "__builtin_qpx_qvfxmadd", - "llvm.ppc.qpx.qvfxmadds" => "__builtin_qpx_qvfxmadds", - "llvm.ppc.qpx.qvfxmul" => "__builtin_qpx_qvfxmul", - "llvm.ppc.qpx.qvfxmuls" => "__builtin_qpx_qvfxmuls", - "llvm.ppc.qpx.qvfxxcpnmadd" => "__builtin_qpx_qvfxxcpnmadd", - "llvm.ppc.qpx.qvfxxcpnmadds" => "__builtin_qpx_qvfxxcpnmadds", - "llvm.ppc.qpx.qvfxxmadd" => "__builtin_qpx_qvfxxmadd", - "llvm.ppc.qpx.qvfxxmadds" => "__builtin_qpx_qvfxxmadds", - "llvm.ppc.qpx.qvfxxnpmadd" => "__builtin_qpx_qvfxxnpmadd", - "llvm.ppc.qpx.qvfxxnpmadds" => "__builtin_qpx_qvfxxnpmadds", - "llvm.ppc.qpx.qvgpci" => "__builtin_qpx_qvgpci", - "llvm.ppc.qpx.qvlfcd" => "__builtin_qpx_qvlfcd", - "llvm.ppc.qpx.qvlfcda" => "__builtin_qpx_qvlfcda", - "llvm.ppc.qpx.qvlfcs" => "__builtin_qpx_qvlfcs", - "llvm.ppc.qpx.qvlfcsa" => "__builtin_qpx_qvlfcsa", - "llvm.ppc.qpx.qvlfd" => "__builtin_qpx_qvlfd", - "llvm.ppc.qpx.qvlfda" => "__builtin_qpx_qvlfda", - "llvm.ppc.qpx.qvlfiwa" => "__builtin_qpx_qvlfiwa", - "llvm.ppc.qpx.qvlfiwaa" => "__builtin_qpx_qvlfiwaa", - "llvm.ppc.qpx.qvlfiwz" => "__builtin_qpx_qvlfiwz", - "llvm.ppc.qpx.qvlfiwza" => "__builtin_qpx_qvlfiwza", - "llvm.ppc.qpx.qvlfs" => "__builtin_qpx_qvlfs", - "llvm.ppc.qpx.qvlfsa" => "__builtin_qpx_qvlfsa", - "llvm.ppc.qpx.qvlpcld" => "__builtin_qpx_qvlpcld", - "llvm.ppc.qpx.qvlpcls" => "__builtin_qpx_qvlpcls", - "llvm.ppc.qpx.qvlpcrd" => "__builtin_qpx_qvlpcrd", - "llvm.ppc.qpx.qvlpcrs" => "__builtin_qpx_qvlpcrs", - "llvm.ppc.qpx.qvstfcd" => "__builtin_qpx_qvstfcd", - "llvm.ppc.qpx.qvstfcda" => "__builtin_qpx_qvstfcda", - "llvm.ppc.qpx.qvstfcs" => "__builtin_qpx_qvstfcs", - "llvm.ppc.qpx.qvstfcsa" => "__builtin_qpx_qvstfcsa", - "llvm.ppc.qpx.qvstfd" => "__builtin_qpx_qvstfd", - "llvm.ppc.qpx.qvstfda" => "__builtin_qpx_qvstfda", - "llvm.ppc.qpx.qvstfiw" => "__builtin_qpx_qvstfiw", - "llvm.ppc.qpx.qvstfiwa" => "__builtin_qpx_qvstfiwa", - "llvm.ppc.qpx.qvstfs" => "__builtin_qpx_qvstfs", - "llvm.ppc.qpx.qvstfsa" => "__builtin_qpx_qvstfsa", "llvm.ppc.readflm" => "__builtin_readflm", "llvm.ppc.rlwimi" => "__builtin_ppc_rlwimi", "llvm.ppc.rlwnm" => "__builtin_ppc_rlwnm", @@ -5751,25 +5549,6 @@ match name { "llvm.ppc.vsx.xxinsertw" => "__builtin_vsx_xxinsertw", "llvm.ppc.vsx.xxleqv" => "__builtin_vsx_xxleqv", "llvm.ppc.vsx.xxpermx" => "__builtin_vsx_xxpermx", - // ptx - "llvm.ptx.bar.sync" => "__builtin_ptx_bar_sync", - "llvm.ptx.read.clock" => "__builtin_ptx_read_clock", - "llvm.ptx.read.clock64" => "__builtin_ptx_read_clock64", - "llvm.ptx.read.gridid" => "__builtin_ptx_read_gridid", - "llvm.ptx.read.laneid" => "__builtin_ptx_read_laneid", - "llvm.ptx.read.lanemask.eq" => "__builtin_ptx_read_lanemask_eq", - "llvm.ptx.read.lanemask.ge" => "__builtin_ptx_read_lanemask_ge", - "llvm.ptx.read.lanemask.gt" => "__builtin_ptx_read_lanemask_gt", - "llvm.ptx.read.lanemask.le" => "__builtin_ptx_read_lanemask_le", - "llvm.ptx.read.lanemask.lt" => "__builtin_ptx_read_lanemask_lt", - "llvm.ptx.read.nsmid" => "__builtin_ptx_read_nsmid", - "llvm.ptx.read.nwarpid" => "__builtin_ptx_read_nwarpid", - "llvm.ptx.read.pm0" => "__builtin_ptx_read_pm0", - "llvm.ptx.read.pm1" => "__builtin_ptx_read_pm1", - "llvm.ptx.read.pm2" => "__builtin_ptx_read_pm2", - "llvm.ptx.read.pm3" => "__builtin_ptx_read_pm3", - "llvm.ptx.read.smid" => "__builtin_ptx_read_smid", - "llvm.ptx.read.warpid" => "__builtin_ptx_read_warpid", // r600 "llvm.r600.group.barrier" => "__builtin_r600_group_barrier", "llvm.r600.implicitarg.ptr" => "__builtin_r600_implicitarg_ptr", @@ -6888,12 +6667,12 @@ match name { "llvm.ve.vl.vgtunc.vvssml" => "__builtin_ve_vl_vgtunc_vvssml", "llvm.ve.vl.vgtunc.vvssmvl" => "__builtin_ve_vl_vgtunc_vvssmvl", "llvm.ve.vl.vgtunc.vvssvl" => "__builtin_ve_vl_vgtunc_vvssvl", - "llvm.ve.vl.vld.vssl" => "__builtin_ve_vl_vld_vssl", - "llvm.ve.vl.vld.vssvl" => "__builtin_ve_vl_vld_vssvl", "llvm.ve.vl.vld2d.vssl" => "__builtin_ve_vl_vld2d_vssl", "llvm.ve.vl.vld2d.vssvl" => "__builtin_ve_vl_vld2d_vssvl", "llvm.ve.vl.vld2dnc.vssl" => "__builtin_ve_vl_vld2dnc_vssl", "llvm.ve.vl.vld2dnc.vssvl" => "__builtin_ve_vl_vld2dnc_vssvl", + "llvm.ve.vl.vld.vssl" => "__builtin_ve_vl_vld_vssl", + "llvm.ve.vl.vld.vssvl" => "__builtin_ve_vl_vld_vssvl", "llvm.ve.vl.vldl2dsx.vssl" => "__builtin_ve_vl_vldl2dsx_vssl", "llvm.ve.vl.vldl2dsx.vssvl" => "__builtin_ve_vl_vldl2dsx_vssvl", "llvm.ve.vl.vldl2dsxnc.vssl" => "__builtin_ve_vl_vldl2dsxnc_vssl", @@ -6912,12 +6691,12 @@ match name { "llvm.ve.vl.vldlzxnc.vssvl" => "__builtin_ve_vl_vldlzxnc_vssvl", "llvm.ve.vl.vldnc.vssl" => "__builtin_ve_vl_vldnc_vssl", "llvm.ve.vl.vldnc.vssvl" => "__builtin_ve_vl_vldnc_vssvl", - "llvm.ve.vl.vldu.vssl" => "__builtin_ve_vl_vldu_vssl", - "llvm.ve.vl.vldu.vssvl" => "__builtin_ve_vl_vldu_vssvl", "llvm.ve.vl.vldu2d.vssl" => "__builtin_ve_vl_vldu2d_vssl", "llvm.ve.vl.vldu2d.vssvl" => "__builtin_ve_vl_vldu2d_vssvl", "llvm.ve.vl.vldu2dnc.vssl" => "__builtin_ve_vl_vldu2dnc_vssl", "llvm.ve.vl.vldu2dnc.vssvl" => "__builtin_ve_vl_vldu2dnc_vssvl", + "llvm.ve.vl.vldu.vssl" => "__builtin_ve_vl_vldu_vssl", + "llvm.ve.vl.vldu.vssvl" => "__builtin_ve_vl_vldu_vssvl", "llvm.ve.vl.vldunc.vssl" => "__builtin_ve_vl_vldunc_vssl", "llvm.ve.vl.vldunc.vssvl" => "__builtin_ve_vl_vldunc_vssvl", "llvm.ve.vl.vldz.vvl" => "__builtin_ve_vl_vldz_vvl", @@ -7134,8 +6913,6 @@ match name { "llvm.ve.vl.vsrl.vvvl" => "__builtin_ve_vl_vsrl_vvvl", "llvm.ve.vl.vsrl.vvvmvl" => "__builtin_ve_vl_vsrl_vvvmvl", "llvm.ve.vl.vsrl.vvvvl" => "__builtin_ve_vl_vsrl_vvvvl", - "llvm.ve.vl.vst.vssl" => "__builtin_ve_vl_vst_vssl", - "llvm.ve.vl.vst.vssml" => "__builtin_ve_vl_vst_vssml", "llvm.ve.vl.vst2d.vssl" => "__builtin_ve_vl_vst2d_vssl", "llvm.ve.vl.vst2d.vssml" => "__builtin_ve_vl_vst2d_vssml", "llvm.ve.vl.vst2dnc.vssl" => "__builtin_ve_vl_vst2dnc_vssl", @@ -7144,8 +6921,8 @@ match name { "llvm.ve.vl.vst2dncot.vssml" => "__builtin_ve_vl_vst2dncot_vssml", "llvm.ve.vl.vst2dot.vssl" => "__builtin_ve_vl_vst2dot_vssl", "llvm.ve.vl.vst2dot.vssml" => "__builtin_ve_vl_vst2dot_vssml", - "llvm.ve.vl.vstl.vssl" => "__builtin_ve_vl_vstl_vssl", - "llvm.ve.vl.vstl.vssml" => "__builtin_ve_vl_vstl_vssml", + "llvm.ve.vl.vst.vssl" => "__builtin_ve_vl_vst_vssl", + "llvm.ve.vl.vst.vssml" => "__builtin_ve_vl_vst_vssml", "llvm.ve.vl.vstl2d.vssl" => "__builtin_ve_vl_vstl2d_vssl", "llvm.ve.vl.vstl2d.vssml" => "__builtin_ve_vl_vstl2d_vssml", "llvm.ve.vl.vstl2dnc.vssl" => "__builtin_ve_vl_vstl2dnc_vssl", @@ -7154,6 +6931,8 @@ match name { "llvm.ve.vl.vstl2dncot.vssml" => "__builtin_ve_vl_vstl2dncot_vssml", "llvm.ve.vl.vstl2dot.vssl" => "__builtin_ve_vl_vstl2dot_vssl", "llvm.ve.vl.vstl2dot.vssml" => "__builtin_ve_vl_vstl2dot_vssml", + "llvm.ve.vl.vstl.vssl" => "__builtin_ve_vl_vstl_vssl", + "llvm.ve.vl.vstl.vssml" => "__builtin_ve_vl_vstl_vssml", "llvm.ve.vl.vstlnc.vssl" => "__builtin_ve_vl_vstlnc_vssl", "llvm.ve.vl.vstlnc.vssml" => "__builtin_ve_vl_vstlnc_vssml", "llvm.ve.vl.vstlncot.vssl" => "__builtin_ve_vl_vstlncot_vssl", @@ -7166,8 +6945,6 @@ match name { "llvm.ve.vl.vstncot.vssml" => "__builtin_ve_vl_vstncot_vssml", "llvm.ve.vl.vstot.vssl" => "__builtin_ve_vl_vstot_vssl", "llvm.ve.vl.vstot.vssml" => "__builtin_ve_vl_vstot_vssml", - "llvm.ve.vl.vstu.vssl" => "__builtin_ve_vl_vstu_vssl", - "llvm.ve.vl.vstu.vssml" => "__builtin_ve_vl_vstu_vssml", "llvm.ve.vl.vstu2d.vssl" => "__builtin_ve_vl_vstu2d_vssl", "llvm.ve.vl.vstu2d.vssml" => "__builtin_ve_vl_vstu2d_vssml", "llvm.ve.vl.vstu2dnc.vssl" => "__builtin_ve_vl_vstu2dnc_vssl", @@ -7176,6 +6953,8 @@ match name { "llvm.ve.vl.vstu2dncot.vssml" => "__builtin_ve_vl_vstu2dncot_vssml", "llvm.ve.vl.vstu2dot.vssl" => "__builtin_ve_vl_vstu2dot_vssl", "llvm.ve.vl.vstu2dot.vssml" => "__builtin_ve_vl_vstu2dot_vssml", + "llvm.ve.vl.vstu.vssl" => "__builtin_ve_vl_vstu_vssl", + "llvm.ve.vl.vstu.vssml" => "__builtin_ve_vl_vstu_vssml", "llvm.ve.vl.vstunc.vssl" => "__builtin_ve_vl_vstunc_vssl", "llvm.ve.vl.vstunc.vssml" => "__builtin_ve_vl_vstunc_vssml", "llvm.ve.vl.vstuncot.vssl" => "__builtin_ve_vl_vstuncot_vssl", @@ -7231,10 +7010,6 @@ match name { "llvm.x86.aadd64" => "__builtin_ia32_aadd64", "llvm.x86.aand32" => "__builtin_ia32_aand32", "llvm.x86.aand64" => "__builtin_ia32_aand64", - "llvm.x86.addcarry.u32" => "__builtin_ia32_addcarry_u32", - "llvm.x86.addcarry.u64" => "__builtin_ia32_addcarry_u64", - "llvm.x86.addcarryx.u32" => "__builtin_ia32_addcarryx_u32", - "llvm.x86.addcarryx.u64" => "__builtin_ia32_addcarryx_u64", "llvm.x86.aesni.aesdec" => "__builtin_ia32_aesdec128", "llvm.x86.aesni.aesdec.256" => "__builtin_ia32_aesdec256", "llvm.x86.aesni.aesdec.512" => "__builtin_ia32_aesdec512", @@ -7251,284 +7026,6 @@ match name { "llvm.x86.aesni.aeskeygenassist" => "__builtin_ia32_aeskeygenassist128", "llvm.x86.aor32" => "__builtin_ia32_aor32", "llvm.x86.aor64" => "__builtin_ia32_aor64", - "llvm.x86.avx.addsub.pd.256" => "__builtin_ia32_addsubpd256", - "llvm.x86.avx.addsub.ps.256" => "__builtin_ia32_addsubps256", - "llvm.x86.avx.blend.pd.256" => "__builtin_ia32_blendpd256", - "llvm.x86.avx.blend.ps.256" => "__builtin_ia32_blendps256", - "llvm.x86.avx.blendv.pd.256" => "__builtin_ia32_blendvpd256", - "llvm.x86.avx.blendv.ps.256" => "__builtin_ia32_blendvps256", - "llvm.x86.avx.cmp.pd.256" => "__builtin_ia32_cmppd256", - "llvm.x86.avx.cmp.ps.256" => "__builtin_ia32_cmpps256", - "llvm.x86.avx.cvt.pd2.ps.256" => "__builtin_ia32_cvtpd2ps256", - "llvm.x86.avx.cvt.pd2dq.256" => "__builtin_ia32_cvtpd2dq256", - "llvm.x86.avx.cvt.ps2.pd.256" => "__builtin_ia32_cvtps2pd256", - "llvm.x86.avx.cvt.ps2dq.256" => "__builtin_ia32_cvtps2dq256", - "llvm.x86.avx.cvtdq2.pd.256" => "__builtin_ia32_cvtdq2pd256", - "llvm.x86.avx.cvtdq2.ps.256" => "__builtin_ia32_cvtdq2ps256", - "llvm.x86.avx.cvtt.pd2dq.256" => "__builtin_ia32_cvttpd2dq256", - "llvm.x86.avx.cvtt.ps2dq.256" => "__builtin_ia32_cvttps2dq256", - "llvm.x86.avx.dp.ps.256" => "__builtin_ia32_dpps256", - "llvm.x86.avx.hadd.pd.256" => "__builtin_ia32_haddpd256", - "llvm.x86.avx.hadd.ps.256" => "__builtin_ia32_haddps256", - "llvm.x86.avx.hsub.pd.256" => "__builtin_ia32_hsubpd256", - "llvm.x86.avx.hsub.ps.256" => "__builtin_ia32_hsubps256", - "llvm.x86.avx.ldu.dq.256" => "__builtin_ia32_lddqu256", - "llvm.x86.avx.maskload.pd" => "__builtin_ia32_maskloadpd", - "llvm.x86.avx.maskload.pd.256" => "__builtin_ia32_maskloadpd256", - "llvm.x86.avx.maskload.ps" => "__builtin_ia32_maskloadps", - "llvm.x86.avx.maskload.ps.256" => "__builtin_ia32_maskloadps256", - "llvm.x86.avx.maskstore.pd" => "__builtin_ia32_maskstorepd", - "llvm.x86.avx.maskstore.pd.256" => "__builtin_ia32_maskstorepd256", - "llvm.x86.avx.maskstore.ps" => "__builtin_ia32_maskstoreps", - "llvm.x86.avx.maskstore.ps.256" => "__builtin_ia32_maskstoreps256", - "llvm.x86.avx.max.pd.256" => "__builtin_ia32_maxpd256", - "llvm.x86.avx.max.ps.256" => "__builtin_ia32_maxps256", - "llvm.x86.avx.min.pd.256" => "__builtin_ia32_minpd256", - "llvm.x86.avx.min.ps.256" => "__builtin_ia32_minps256", - "llvm.x86.avx.movmsk.pd.256" => "__builtin_ia32_movmskpd256", - "llvm.x86.avx.movmsk.ps.256" => "__builtin_ia32_movmskps256", - "llvm.x86.avx.ptestc.256" => "__builtin_ia32_ptestc256", - "llvm.x86.avx.ptestnzc.256" => "__builtin_ia32_ptestnzc256", - "llvm.x86.avx.ptestz.256" => "__builtin_ia32_ptestz256", - "llvm.x86.avx.rcp.ps.256" => "__builtin_ia32_rcpps256", - "llvm.x86.avx.round.pd.256" => "__builtin_ia32_roundpd256", - "llvm.x86.avx.round.ps.256" => "__builtin_ia32_roundps256", - "llvm.x86.avx.rsqrt.ps.256" => "__builtin_ia32_rsqrtps256", - "llvm.x86.avx.sqrt.pd.256" => "__builtin_ia32_sqrtpd256", - "llvm.x86.avx.sqrt.ps.256" => "__builtin_ia32_sqrtps256", - "llvm.x86.avx.storeu.dq.256" => "__builtin_ia32_storedqu256", - "llvm.x86.avx.storeu.pd.256" => "__builtin_ia32_storeupd256", - "llvm.x86.avx.storeu.ps.256" => "__builtin_ia32_storeups256", - "llvm.x86.avx.vbroadcastf128.pd.256" => "__builtin_ia32_vbroadcastf128_pd256", - "llvm.x86.avx.vbroadcastf128.ps.256" => "__builtin_ia32_vbroadcastf128_ps256", - "llvm.x86.avx.vextractf128.pd.256" => "__builtin_ia32_vextractf128_pd256", - "llvm.x86.avx.vextractf128.ps.256" => "__builtin_ia32_vextractf128_ps256", - "llvm.x86.avx.vextractf128.si.256" => "__builtin_ia32_vextractf128_si256", - "llvm.x86.avx.vinsertf128.pd.256" => "__builtin_ia32_vinsertf128_pd256", - "llvm.x86.avx.vinsertf128.ps.256" => "__builtin_ia32_vinsertf128_ps256", - "llvm.x86.avx.vinsertf128.si.256" => "__builtin_ia32_vinsertf128_si256", - "llvm.x86.avx.vperm2f128.pd.256" => "__builtin_ia32_vperm2f128_pd256", - "llvm.x86.avx.vperm2f128.ps.256" => "__builtin_ia32_vperm2f128_ps256", - "llvm.x86.avx.vperm2f128.si.256" => "__builtin_ia32_vperm2f128_si256", - "llvm.x86.avx.vpermilvar.pd" => "__builtin_ia32_vpermilvarpd", - "llvm.x86.avx.vpermilvar.pd.256" => "__builtin_ia32_vpermilvarpd256", - "llvm.x86.avx.vpermilvar.ps" => "__builtin_ia32_vpermilvarps", - "llvm.x86.avx.vpermilvar.ps.256" => "__builtin_ia32_vpermilvarps256", - "llvm.x86.avx.vtestc.pd" => "__builtin_ia32_vtestcpd", - "llvm.x86.avx.vtestc.pd.256" => "__builtin_ia32_vtestcpd256", - "llvm.x86.avx.vtestc.ps" => "__builtin_ia32_vtestcps", - "llvm.x86.avx.vtestc.ps.256" => "__builtin_ia32_vtestcps256", - "llvm.x86.avx.vtestnzc.pd" => "__builtin_ia32_vtestnzcpd", - "llvm.x86.avx.vtestnzc.pd.256" => "__builtin_ia32_vtestnzcpd256", - "llvm.x86.avx.vtestnzc.ps" => "__builtin_ia32_vtestnzcps", - "llvm.x86.avx.vtestnzc.ps.256" => "__builtin_ia32_vtestnzcps256", - "llvm.x86.avx.vtestz.pd" => "__builtin_ia32_vtestzpd", - "llvm.x86.avx.vtestz.pd.256" => "__builtin_ia32_vtestzpd256", - "llvm.x86.avx.vtestz.ps" => "__builtin_ia32_vtestzps", - "llvm.x86.avx.vtestz.ps.256" => "__builtin_ia32_vtestzps256", - "llvm.x86.avx.vzeroall" => "__builtin_ia32_vzeroall", - "llvm.x86.avx.vzeroupper" => "__builtin_ia32_vzeroupper", - "llvm.x86.avx10.mask.vcvt2ps2phx.128" => "__builtin_ia32_vcvt2ps2phx128_mask", - "llvm.x86.avx10.mask.vcvt2ps2phx.256" => "__builtin_ia32_vcvt2ps2phx256_mask", - "llvm.x86.avx10.mask.vcvt2ps2phx.512" => "__builtin_ia32_vcvt2ps2phx512_mask", - "llvm.x86.avx10.mask.vcvtbiasph2bf8128" => "__builtin_ia32_vcvtbiasph2bf8_128_mask", - "llvm.x86.avx10.mask.vcvtbiasph2bf8256" => "__builtin_ia32_vcvtbiasph2bf8_256_mask", - "llvm.x86.avx10.mask.vcvtbiasph2bf8512" => "__builtin_ia32_vcvtbiasph2bf8_512_mask", - "llvm.x86.avx10.mask.vcvtbiasph2bf8s128" => "__builtin_ia32_vcvtbiasph2bf8s_128_mask", - "llvm.x86.avx10.mask.vcvtbiasph2bf8s256" => "__builtin_ia32_vcvtbiasph2bf8s_256_mask", - "llvm.x86.avx10.mask.vcvtbiasph2bf8s512" => "__builtin_ia32_vcvtbiasph2bf8s_512_mask", - "llvm.x86.avx10.mask.vcvtbiasph2hf8128" => "__builtin_ia32_vcvtbiasph2hf8_128_mask", - "llvm.x86.avx10.mask.vcvtbiasph2hf8256" => "__builtin_ia32_vcvtbiasph2hf8_256_mask", - "llvm.x86.avx10.mask.vcvtbiasph2hf8512" => "__builtin_ia32_vcvtbiasph2hf8_512_mask", - "llvm.x86.avx10.mask.vcvtbiasph2hf8s128" => "__builtin_ia32_vcvtbiasph2hf8s_128_mask", - "llvm.x86.avx10.mask.vcvtbiasph2hf8s256" => "__builtin_ia32_vcvtbiasph2hf8s_256_mask", - "llvm.x86.avx10.mask.vcvtbiasph2hf8s512" => "__builtin_ia32_vcvtbiasph2hf8s_512_mask", - "llvm.x86.avx10.mask.vcvthf82ph128" => "__builtin_ia32_vcvthf8_2ph128_mask", - "llvm.x86.avx10.mask.vcvthf82ph256" => "__builtin_ia32_vcvthf8_2ph256_mask", - "llvm.x86.avx10.mask.vcvthf82ph512" => "__builtin_ia32_vcvthf8_2ph512_mask", - "llvm.x86.avx10.mask.vcvtneph2bf8128" => "__builtin_ia32_vcvtneph2bf8_128_mask", - "llvm.x86.avx10.mask.vcvtneph2bf8256" => "__builtin_ia32_vcvtneph2bf8_256_mask", - "llvm.x86.avx10.mask.vcvtneph2bf8512" => "__builtin_ia32_vcvtneph2bf8_512_mask", - "llvm.x86.avx10.mask.vcvtneph2bf8s128" => "__builtin_ia32_vcvtneph2bf8s_128_mask", - "llvm.x86.avx10.mask.vcvtneph2bf8s256" => "__builtin_ia32_vcvtneph2bf8s_256_mask", - "llvm.x86.avx10.mask.vcvtneph2bf8s512" => "__builtin_ia32_vcvtneph2bf8s_512_mask", - "llvm.x86.avx10.mask.vcvtneph2hf8128" => "__builtin_ia32_vcvtneph2hf8_128_mask", - "llvm.x86.avx10.mask.vcvtneph2hf8256" => "__builtin_ia32_vcvtneph2hf8_256_mask", - "llvm.x86.avx10.mask.vcvtneph2hf8512" => "__builtin_ia32_vcvtneph2hf8_512_mask", - "llvm.x86.avx10.mask.vcvtneph2hf8s128" => "__builtin_ia32_vcvtneph2hf8s_128_mask", - "llvm.x86.avx10.mask.vcvtneph2hf8s256" => "__builtin_ia32_vcvtneph2hf8s_256_mask", - "llvm.x86.avx10.mask.vcvtneph2hf8s512" => "__builtin_ia32_vcvtneph2hf8s_512_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvtpd2dq256" => "__builtin_ia32_vcvtpd2dq256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvtpd2ph256" => "__builtin_ia32_vcvtpd2ph256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvtpd2ps256" => "__builtin_ia32_vcvtpd2ps256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvtpd2qq256" => "__builtin_ia32_vcvtpd2qq256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvtpd2udq256" => "__builtin_ia32_vcvtpd2udq256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvtpd2uqq256" => "__builtin_ia32_vcvtpd2uqq256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvtph2dq256" => "__builtin_ia32_vcvtph2dq256_round_mask", - "llvm.x86.avx10.mask.vcvtph2ibs128" => "__builtin_ia32_vcvtph2ibs128_mask", - "llvm.x86.avx10.mask.vcvtph2ibs256" => "__builtin_ia32_vcvtph2ibs256_mask", - "llvm.x86.avx10.mask.vcvtph2ibs512" => "__builtin_ia32_vcvtph2ibs512_mask", - "llvm.x86.avx10.mask.vcvtph2iubs128" => "__builtin_ia32_vcvtph2iubs128_mask", - "llvm.x86.avx10.mask.vcvtph2iubs256" => "__builtin_ia32_vcvtph2iubs256_mask", - "llvm.x86.avx10.mask.vcvtph2iubs512" => "__builtin_ia32_vcvtph2iubs512_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvtph2pd256" => "__builtin_ia32_vcvtph2pd256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvtph2psx256" => "__builtin_ia32_vcvtph2psx256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvtph2qq256" => "__builtin_ia32_vcvtph2qq256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvtph2udq256" => "__builtin_ia32_vcvtph2udq256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvtph2uqq256" => "__builtin_ia32_vcvtph2uqq256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvtph2uw256" => "__builtin_ia32_vcvtph2uw256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvtph2w256" => "__builtin_ia32_vcvtph2w256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvtps2dq256" => "__builtin_ia32_vcvtps2dq256_round_mask", - "llvm.x86.avx10.mask.vcvtps2ibs128" => "__builtin_ia32_vcvtps2ibs128_mask", - "llvm.x86.avx10.mask.vcvtps2ibs256" => "__builtin_ia32_vcvtps2ibs256_mask", - "llvm.x86.avx10.mask.vcvtps2ibs512" => "__builtin_ia32_vcvtps2ibs512_mask", - "llvm.x86.avx10.mask.vcvtps2iubs128" => "__builtin_ia32_vcvtps2iubs128_mask", - "llvm.x86.avx10.mask.vcvtps2iubs256" => "__builtin_ia32_vcvtps2iubs256_mask", - "llvm.x86.avx10.mask.vcvtps2iubs512" => "__builtin_ia32_vcvtps2iubs512_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvtps2pd256" => "__builtin_ia32_vcvtps2pd256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvtps2ph256" => "__builtin_ia32_vcvtps2ph256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvtps2phx256" => "__builtin_ia32_vcvtps2phx256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvtps2qq256" => "__builtin_ia32_vcvtps2qq256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvtps2udq256" => "__builtin_ia32_vcvtps2udq256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvtps2uqq256" => "__builtin_ia32_vcvtps2uqq256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvttpd2dq256" => "__builtin_ia32_vcvttpd2dq256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvttpd2qq256" => "__builtin_ia32_vcvttpd2qq256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvttpd2udq256" => "__builtin_ia32_vcvttpd2udq256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvttpd2uqq256" => "__builtin_ia32_vcvttpd2uqq256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvttph2dq256" => "__builtin_ia32_vcvttph2dq256_round_mask", - "llvm.x86.avx10.mask.vcvttph2ibs128" => "__builtin_ia32_vcvttph2ibs128_mask", - "llvm.x86.avx10.mask.vcvttph2ibs256" => "__builtin_ia32_vcvttph2ibs256_mask", - "llvm.x86.avx10.mask.vcvttph2ibs512" => "__builtin_ia32_vcvttph2ibs512_mask", - "llvm.x86.avx10.mask.vcvttph2iubs128" => "__builtin_ia32_vcvttph2iubs128_mask", - "llvm.x86.avx10.mask.vcvttph2iubs256" => "__builtin_ia32_vcvttph2iubs256_mask", - "llvm.x86.avx10.mask.vcvttph2iubs512" => "__builtin_ia32_vcvttph2iubs512_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvttph2qq256" => "__builtin_ia32_vcvttph2qq256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvttph2udq256" => "__builtin_ia32_vcvttph2udq256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvttph2uqq256" => "__builtin_ia32_vcvttph2uqq256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvttph2uw256" => "__builtin_ia32_vcvttph2uw256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvttph2w256" => "__builtin_ia32_vcvttph2w256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvttps2dq256" => "__builtin_ia32_vcvttps2dq256_round_mask", - "llvm.x86.avx10.mask.vcvttps2ibs128" => "__builtin_ia32_vcvttps2ibs128_mask", - "llvm.x86.avx10.mask.vcvttps2ibs256" => "__builtin_ia32_vcvttps2ibs256_mask", - "llvm.x86.avx10.mask.vcvttps2ibs512" => "__builtin_ia32_vcvttps2ibs512_mask", - "llvm.x86.avx10.mask.vcvttps2iubs128" => "__builtin_ia32_vcvttps2iubs128_mask", - "llvm.x86.avx10.mask.vcvttps2iubs256" => "__builtin_ia32_vcvttps2iubs256_mask", - "llvm.x86.avx10.mask.vcvttps2iubs512" => "__builtin_ia32_vcvttps2iubs512_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvttps2qq256" => "__builtin_ia32_vcvttps2qq256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvttps2udq256" => "__builtin_ia32_vcvttps2udq256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvttps2uqq256" => "__builtin_ia32_vcvttps2uqq256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vfcmaddcph256" => "__builtin_ia32_vfcmaddcph256_round_mask3", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vfcmulcph256" => "__builtin_ia32_vfcmulcph256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vfixupimmpd256" => "__builtin_ia32_vfixupimmpd256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vfixupimmps256" => "__builtin_ia32_vfixupimmps256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vfmaddcph256" => "__builtin_ia32_vfmaddcph256_round_mask3", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vfmulcph256" => "__builtin_ia32_vfmulcph256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vgetexppd256" => "__builtin_ia32_vgetexppd256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vgetexpph256" => "__builtin_ia32_vgetexpph256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vgetexpps256" => "__builtin_ia32_vgetexpps256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vgetmantpd256" => "__builtin_ia32_vgetmantpd256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vgetmantph256" => "__builtin_ia32_vgetmantph256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vgetmantps256" => "__builtin_ia32_vgetmantps256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vminmaxpd.round" => "__builtin_ia32_vminmaxpd512_round_mask", - "llvm.x86.avx10.mask.vminmaxpd128" => "__builtin_ia32_vminmaxpd128_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vminmaxpd256.round" => "__builtin_ia32_vminmaxpd256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vminmaxph.round" => "__builtin_ia32_vminmaxph512_round_mask", - "llvm.x86.avx10.mask.vminmaxph128" => "__builtin_ia32_vminmaxph128_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vminmaxph256.round" => "__builtin_ia32_vminmaxph256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vminmaxps.round" => "__builtin_ia32_vminmaxps512_round_mask", - "llvm.x86.avx10.mask.vminmaxps128" => "__builtin_ia32_vminmaxps128_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vminmaxps256.round" => "__builtin_ia32_vminmaxps256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vminmaxsd.round" => "__builtin_ia32_vminmaxsd_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vminmaxsh.round" => "__builtin_ia32_vminmaxsh_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vminmaxss.round" => "__builtin_ia32_vminmaxss_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vrangepd256" => "__builtin_ia32_vrangepd256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vrangeps256" => "__builtin_ia32_vrangeps256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vreducepd256" => "__builtin_ia32_vreducepd256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vreduceph256" => "__builtin_ia32_vreduceph256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vreduceps256" => "__builtin_ia32_vreduceps256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vrndscalepd256" => "__builtin_ia32_vrndscalepd256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vrndscaleph256" => "__builtin_ia32_vrndscaleph256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vrndscaleps256" => "__builtin_ia32_vrndscaleps256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vscalefpd256" => "__builtin_ia32_vscalefpd256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vscalefph256" => "__builtin_ia32_vscalefph256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vscalefps256" => "__builtin_ia32_vscalefps256_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.maskz.vfcmaddcph256" => "__builtin_ia32_vfcmaddcph256_round_maskz", - // [INVALID CONVERSION]: "llvm.x86.avx10.maskz.vfixupimmpd256" => "__builtin_ia32_vfixupimmpd256_round_maskz", - // [INVALID CONVERSION]: "llvm.x86.avx10.maskz.vfixupimmps256" => "__builtin_ia32_vfixupimmps256_round_maskz", - // [INVALID CONVERSION]: "llvm.x86.avx10.maskz.vfmaddcph256" => "__builtin_ia32_vfmaddcph256_round_maskz", - "llvm.x86.avx10.vaddpd256" => "__builtin_ia32_vaddpd256_round", - "llvm.x86.avx10.vaddph256" => "__builtin_ia32_vaddph256_round", - "llvm.x86.avx10.vaddps256" => "__builtin_ia32_vaddps256_round", - "llvm.x86.avx10.vcvtne2ph2bf8128" => "__builtin_ia32_vcvtne2ph2bf8_128", - "llvm.x86.avx10.vcvtne2ph2bf8256" => "__builtin_ia32_vcvtne2ph2bf8_256", - "llvm.x86.avx10.vcvtne2ph2bf8512" => "__builtin_ia32_vcvtne2ph2bf8_512", - "llvm.x86.avx10.vcvtne2ph2bf8s128" => "__builtin_ia32_vcvtne2ph2bf8s_128", - "llvm.x86.avx10.vcvtne2ph2bf8s256" => "__builtin_ia32_vcvtne2ph2bf8s_256", - "llvm.x86.avx10.vcvtne2ph2bf8s512" => "__builtin_ia32_vcvtne2ph2bf8s_512", - "llvm.x86.avx10.vcvtne2ph2hf8128" => "__builtin_ia32_vcvtne2ph2hf8_128", - "llvm.x86.avx10.vcvtne2ph2hf8256" => "__builtin_ia32_vcvtne2ph2hf8_256", - "llvm.x86.avx10.vcvtne2ph2hf8512" => "__builtin_ia32_vcvtne2ph2hf8_512", - "llvm.x86.avx10.vcvtne2ph2hf8s128" => "__builtin_ia32_vcvtne2ph2hf8s_128", - "llvm.x86.avx10.vcvtne2ph2hf8s256" => "__builtin_ia32_vcvtne2ph2hf8s_256", - "llvm.x86.avx10.vcvtne2ph2hf8s512" => "__builtin_ia32_vcvtne2ph2hf8s_512", - "llvm.x86.avx10.vcvtnebf162ibs128" => "__builtin_ia32_vcvtnebf162ibs128", - "llvm.x86.avx10.vcvtnebf162ibs256" => "__builtin_ia32_vcvtnebf162ibs256", - "llvm.x86.avx10.vcvtnebf162ibs512" => "__builtin_ia32_vcvtnebf162ibs512", - "llvm.x86.avx10.vcvtnebf162iubs128" => "__builtin_ia32_vcvtnebf162iubs128", - "llvm.x86.avx10.vcvtnebf162iubs256" => "__builtin_ia32_vcvtnebf162iubs256", - "llvm.x86.avx10.vcvtnebf162iubs512" => "__builtin_ia32_vcvtnebf162iubs512", - "llvm.x86.avx10.vcvttnebf162ibs128" => "__builtin_ia32_vcvttnebf162ibs128", - "llvm.x86.avx10.vcvttnebf162ibs256" => "__builtin_ia32_vcvttnebf162ibs256", - "llvm.x86.avx10.vcvttnebf162ibs512" => "__builtin_ia32_vcvttnebf162ibs512", - "llvm.x86.avx10.vcvttnebf162iubs128" => "__builtin_ia32_vcvttnebf162iubs128", - "llvm.x86.avx10.vcvttnebf162iubs256" => "__builtin_ia32_vcvttnebf162iubs256", - "llvm.x86.avx10.vcvttnebf162iubs512" => "__builtin_ia32_vcvttnebf162iubs512", - "llvm.x86.avx10.vdivpd256" => "__builtin_ia32_vdivpd256_round", - "llvm.x86.avx10.vdivph256" => "__builtin_ia32_vdivph256_round", - "llvm.x86.avx10.vdivps256" => "__builtin_ia32_vdivps256_round", - "llvm.x86.avx10.vdpphps.128" => "__builtin_ia32_vdpphps128", - "llvm.x86.avx10.vdpphps.256" => "__builtin_ia32_vdpphps256", - "llvm.x86.avx10.vdpphps.512" => "__builtin_ia32_vdpphps512", - "llvm.x86.avx10.vfmaddsubpd256" => "__builtin_ia32_vfmaddsubpd256_round", - "llvm.x86.avx10.vfmaddsubph256" => "__builtin_ia32_vfmaddsubph256_round", - "llvm.x86.avx10.vfmaddsubps256" => "__builtin_ia32_vfmaddsubps256_round", - "llvm.x86.avx10.vmaxpd256" => "__builtin_ia32_vmaxpd256_round", - "llvm.x86.avx10.vmaxph256" => "__builtin_ia32_vmaxph256_round", - "llvm.x86.avx10.vmaxps256" => "__builtin_ia32_vmaxps256_round", - "llvm.x86.avx10.vminmaxnepbf16128" => "__builtin_ia32_vminmaxnepbf16128", - "llvm.x86.avx10.vminmaxnepbf16256" => "__builtin_ia32_vminmaxnepbf16256", - "llvm.x86.avx10.vminmaxnepbf16512" => "__builtin_ia32_vminmaxnepbf16512", - "llvm.x86.avx10.vminmaxpd128" => "__builtin_ia32_vminmaxpd128", - "llvm.x86.avx10.vminmaxpd256" => "__builtin_ia32_vminmaxpd256", - "llvm.x86.avx10.vminmaxph128" => "__builtin_ia32_vminmaxph128", - "llvm.x86.avx10.vminmaxph256" => "__builtin_ia32_vminmaxph256", - "llvm.x86.avx10.vminmaxps128" => "__builtin_ia32_vminmaxps128", - "llvm.x86.avx10.vminmaxps256" => "__builtin_ia32_vminmaxps256", - "llvm.x86.avx10.vminpd256" => "__builtin_ia32_vminpd256_round", - "llvm.x86.avx10.vminph256" => "__builtin_ia32_vminph256_round", - "llvm.x86.avx10.vminps256" => "__builtin_ia32_vminps256_round", - "llvm.x86.avx10.vmpsadbw.512" => "__builtin_ia32_mpsadbw512", - "llvm.x86.avx10.vmulpd256" => "__builtin_ia32_vmulpd256_round", - "llvm.x86.avx10.vmulph256" => "__builtin_ia32_vmulph256_round", - "llvm.x86.avx10.vmulps256" => "__builtin_ia32_vmulps256_round", - "llvm.x86.avx10.vpdpbssd.512" => "__builtin_ia32_vpdpbssd512", - "llvm.x86.avx10.vpdpbssds.512" => "__builtin_ia32_vpdpbssds512", - "llvm.x86.avx10.vpdpbsud.512" => "__builtin_ia32_vpdpbsud512", - "llvm.x86.avx10.vpdpbsuds.512" => "__builtin_ia32_vpdpbsuds512", - "llvm.x86.avx10.vpdpbuud.512" => "__builtin_ia32_vpdpbuud512", - "llvm.x86.avx10.vpdpbuuds.512" => "__builtin_ia32_vpdpbuuds512", - "llvm.x86.avx10.vpdpwsud.512" => "__builtin_ia32_vpdpwsud512", - "llvm.x86.avx10.vpdpwsuds.512" => "__builtin_ia32_vpdpwsuds512", - "llvm.x86.avx10.vpdpwusd.512" => "__builtin_ia32_vpdpwusd512", - "llvm.x86.avx10.vpdpwusds.512" => "__builtin_ia32_vpdpwusds512", - "llvm.x86.avx10.vpdpwuud.512" => "__builtin_ia32_vpdpwuud512", - "llvm.x86.avx10.vpdpwuuds.512" => "__builtin_ia32_vpdpwuuds512", - "llvm.x86.avx10.vsqrtpd256" => "__builtin_ia32_vsqrtpd256_round", - "llvm.x86.avx10.vsqrtph256" => "__builtin_ia32_vsqrtph256_round", - "llvm.x86.avx10.vsqrtps256" => "__builtin_ia32_vsqrtps256_round", - "llvm.x86.avx10.vsubpd256" => "__builtin_ia32_vsubpd256_round", - "llvm.x86.avx10.vsubph256" => "__builtin_ia32_vsubph256_round", - "llvm.x86.avx10.vsubps256" => "__builtin_ia32_vsubps256_round", "llvm.x86.avx2.gather.d.d" => "__builtin_ia32_gatherd_d", "llvm.x86.avx2.gather.d.d.256" => "__builtin_ia32_gatherd_d256", "llvm.x86.avx2.gather.d.pd" => "__builtin_ia32_gatherd_pd", @@ -7553,33 +7050,14 @@ match name { "llvm.x86.avx2.maskstore.d.256" => "__builtin_ia32_maskstored256", "llvm.x86.avx2.maskstore.q" => "__builtin_ia32_maskstoreq", "llvm.x86.avx2.maskstore.q.256" => "__builtin_ia32_maskstoreq256", - "llvm.x86.avx2.movntdqa" => "__builtin_ia32_movntdqa256", "llvm.x86.avx2.mpsadbw" => "__builtin_ia32_mpsadbw256", - "llvm.x86.avx2.pabs.b" => "__builtin_ia32_pabsb256", - "llvm.x86.avx2.pabs.d" => "__builtin_ia32_pabsd256", - "llvm.x86.avx2.pabs.w" => "__builtin_ia32_pabsw256", "llvm.x86.avx2.packssdw" => "__builtin_ia32_packssdw256", "llvm.x86.avx2.packsswb" => "__builtin_ia32_packsswb256", "llvm.x86.avx2.packusdw" => "__builtin_ia32_packusdw256", "llvm.x86.avx2.packuswb" => "__builtin_ia32_packuswb256", - "llvm.x86.avx2.padds.b" => "__builtin_ia32_paddsb256", - "llvm.x86.avx2.padds.w" => "__builtin_ia32_paddsw256", - "llvm.x86.avx2.paddus.b" => "__builtin_ia32_paddusb256", - "llvm.x86.avx2.paddus.w" => "__builtin_ia32_paddusw256", "llvm.x86.avx2.pavg.b" => "__builtin_ia32_pavgb256", "llvm.x86.avx2.pavg.w" => "__builtin_ia32_pavgw256", - "llvm.x86.avx2.pblendd.128" => "__builtin_ia32_pblendd128", - "llvm.x86.avx2.pblendd.256" => "__builtin_ia32_pblendd256", "llvm.x86.avx2.pblendvb" => "__builtin_ia32_pblendvb256", - "llvm.x86.avx2.pblendw" => "__builtin_ia32_pblendw256", - "llvm.x86.avx2.pbroadcastb.128" => "__builtin_ia32_pbroadcastb128", - "llvm.x86.avx2.pbroadcastb.256" => "__builtin_ia32_pbroadcastb256", - "llvm.x86.avx2.pbroadcastd.128" => "__builtin_ia32_pbroadcastd128", - "llvm.x86.avx2.pbroadcastd.256" => "__builtin_ia32_pbroadcastd256", - "llvm.x86.avx2.pbroadcastq.128" => "__builtin_ia32_pbroadcastq128", - "llvm.x86.avx2.pbroadcastq.256" => "__builtin_ia32_pbroadcastq256", - "llvm.x86.avx2.pbroadcastw.128" => "__builtin_ia32_pbroadcastw128", - "llvm.x86.avx2.pbroadcastw.256" => "__builtin_ia32_pbroadcastw256", "llvm.x86.avx2.permd" => "__builtin_ia32_permvarsi256", "llvm.x86.avx2.permps" => "__builtin_ia32_permvarsf256", "llvm.x86.avx2.phadd.d" => "__builtin_ia32_phaddd256", @@ -7590,44 +7068,16 @@ match name { "llvm.x86.avx2.phsub.w" => "__builtin_ia32_phsubw256", "llvm.x86.avx2.pmadd.ub.sw" => "__builtin_ia32_pmaddubsw256", "llvm.x86.avx2.pmadd.wd" => "__builtin_ia32_pmaddwd256", - "llvm.x86.avx2.pmaxs.b" => "__builtin_ia32_pmaxsb256", - "llvm.x86.avx2.pmaxs.d" => "__builtin_ia32_pmaxsd256", - "llvm.x86.avx2.pmaxs.w" => "__builtin_ia32_pmaxsw256", - "llvm.x86.avx2.pmaxu.b" => "__builtin_ia32_pmaxub256", - "llvm.x86.avx2.pmaxu.d" => "__builtin_ia32_pmaxud256", - "llvm.x86.avx2.pmaxu.w" => "__builtin_ia32_pmaxuw256", - "llvm.x86.avx2.pmins.b" => "__builtin_ia32_pminsb256", - "llvm.x86.avx2.pmins.d" => "__builtin_ia32_pminsd256", - "llvm.x86.avx2.pmins.w" => "__builtin_ia32_pminsw256", - "llvm.x86.avx2.pminu.b" => "__builtin_ia32_pminub256", - "llvm.x86.avx2.pminu.d" => "__builtin_ia32_pminud256", - "llvm.x86.avx2.pminu.w" => "__builtin_ia32_pminuw256", "llvm.x86.avx2.pmovmskb" => "__builtin_ia32_pmovmskb256", - "llvm.x86.avx2.pmovsxbd" => "__builtin_ia32_pmovsxbd256", - "llvm.x86.avx2.pmovsxbq" => "__builtin_ia32_pmovsxbq256", - "llvm.x86.avx2.pmovsxbw" => "__builtin_ia32_pmovsxbw256", - "llvm.x86.avx2.pmovsxdq" => "__builtin_ia32_pmovsxdq256", - "llvm.x86.avx2.pmovsxwd" => "__builtin_ia32_pmovsxwd256", - "llvm.x86.avx2.pmovsxwq" => "__builtin_ia32_pmovsxwq256", - "llvm.x86.avx2.pmovzxbd" => "__builtin_ia32_pmovzxbd256", - "llvm.x86.avx2.pmovzxbq" => "__builtin_ia32_pmovzxbq256", - "llvm.x86.avx2.pmovzxbw" => "__builtin_ia32_pmovzxbw256", - "llvm.x86.avx2.pmovzxdq" => "__builtin_ia32_pmovzxdq256", - "llvm.x86.avx2.pmovzxwd" => "__builtin_ia32_pmovzxwd256", - "llvm.x86.avx2.pmovzxwq" => "__builtin_ia32_pmovzxwq256", - "llvm.x86.avx2.pmul.dq" => "__builtin_ia32_pmuldq256", "llvm.x86.avx2.pmul.hr.sw" => "__builtin_ia32_pmulhrsw256", "llvm.x86.avx2.pmulh.w" => "__builtin_ia32_pmulhw256", "llvm.x86.avx2.pmulhu.w" => "__builtin_ia32_pmulhuw256", - "llvm.x86.avx2.pmulu.dq" => "__builtin_ia32_pmuludq256", "llvm.x86.avx2.psad.bw" => "__builtin_ia32_psadbw256", "llvm.x86.avx2.pshuf.b" => "__builtin_ia32_pshufb256", "llvm.x86.avx2.psign.b" => "__builtin_ia32_psignb256", "llvm.x86.avx2.psign.d" => "__builtin_ia32_psignd256", "llvm.x86.avx2.psign.w" => "__builtin_ia32_psignw256", "llvm.x86.avx2.psll.d" => "__builtin_ia32_pslld256", - "llvm.x86.avx2.psll.dq" => "__builtin_ia32_pslldqi256", - "llvm.x86.avx2.psll.dq.bs" => "__builtin_ia32_pslldqi256_byteshift", "llvm.x86.avx2.psll.q" => "__builtin_ia32_psllq256", "llvm.x86.avx2.psll.w" => "__builtin_ia32_psllw256", "llvm.x86.avx2.pslli.d" => "__builtin_ia32_pslldi256", @@ -7644,8 +7094,6 @@ match name { "llvm.x86.avx2.psrav.d" => "__builtin_ia32_psrav4si", "llvm.x86.avx2.psrav.d.256" => "__builtin_ia32_psrav8si", "llvm.x86.avx2.psrl.d" => "__builtin_ia32_psrld256", - "llvm.x86.avx2.psrl.dq" => "__builtin_ia32_psrldqi256", - "llvm.x86.avx2.psrl.dq.bs" => "__builtin_ia32_psrldqi256_byteshift", "llvm.x86.avx2.psrl.q" => "__builtin_ia32_psrlq256", "llvm.x86.avx2.psrl.w" => "__builtin_ia32_psrlw256", "llvm.x86.avx2.psrli.d" => "__builtin_ia32_psrldi256", @@ -7655,15 +7103,6 @@ match name { "llvm.x86.avx2.psrlv.d.256" => "__builtin_ia32_psrlv8si", "llvm.x86.avx2.psrlv.q" => "__builtin_ia32_psrlv2di", "llvm.x86.avx2.psrlv.q.256" => "__builtin_ia32_psrlv4di", - "llvm.x86.avx2.psubs.b" => "__builtin_ia32_psubsb256", - "llvm.x86.avx2.psubs.w" => "__builtin_ia32_psubsw256", - "llvm.x86.avx2.psubus.b" => "__builtin_ia32_psubusb256", - "llvm.x86.avx2.psubus.w" => "__builtin_ia32_psubusw256", - "llvm.x86.avx2.vbroadcast.sd.pd.256" => "__builtin_ia32_vbroadcastsd_pd256", - "llvm.x86.avx2.vbroadcast.ss.ps" => "__builtin_ia32_vbroadcastss_ps", - "llvm.x86.avx2.vbroadcast.ss.ps.256" => "__builtin_ia32_vbroadcastss_ps256", - "llvm.x86.avx2.vextracti128" => "__builtin_ia32_extract128i256", - "llvm.x86.avx2.vinserti128" => "__builtin_ia32_insert128i256", "llvm.x86.avx2.vpdpbssd.128" => "__builtin_ia32_vpdpbssd128", "llvm.x86.avx2.vpdpbssd.256" => "__builtin_ia32_vpdpbssd256", "llvm.x86.avx2.vpdpbssds.128" => "__builtin_ia32_vpdpbssds128", @@ -7688,7 +7127,6 @@ match name { "llvm.x86.avx2.vpdpwuud.256" => "__builtin_ia32_vpdpwuud256", "llvm.x86.avx2.vpdpwuuds.128" => "__builtin_ia32_vpdpwuuds128", "llvm.x86.avx2.vpdpwuuds.256" => "__builtin_ia32_vpdpwuuds256", - "llvm.x86.avx2.vperm2i128" => "__builtin_ia32_permti256", "llvm.x86.avx512.add.pd.512" => "__builtin_ia32_addpd512", "llvm.x86.avx512.add.ps.512" => "__builtin_ia32_addps512", "llvm.x86.avx512.broadcastmb.128" => "__builtin_ia32_broadcastmb128", @@ -7703,194 +7141,32 @@ match name { "llvm.x86.avx512.conflict.q.128" => "__builtin_ia32_vpconflictdi_128", "llvm.x86.avx512.conflict.q.256" => "__builtin_ia32_vpconflictdi_256", "llvm.x86.avx512.conflict.q.512" => "__builtin_ia32_vpconflictdi_512", - "llvm.x86.avx512.cvtb2mask.128" => "__builtin_ia32_cvtb2mask128", - "llvm.x86.avx512.cvtb2mask.256" => "__builtin_ia32_cvtb2mask256", - "llvm.x86.avx512.cvtb2mask.512" => "__builtin_ia32_cvtb2mask512", - "llvm.x86.avx512.cvtd2mask.128" => "__builtin_ia32_cvtd2mask128", - "llvm.x86.avx512.cvtd2mask.256" => "__builtin_ia32_cvtd2mask256", - "llvm.x86.avx512.cvtd2mask.512" => "__builtin_ia32_cvtd2mask512", - "llvm.x86.avx512.cvtmask2b.128" => "__builtin_ia32_cvtmask2b128", - "llvm.x86.avx512.cvtmask2b.256" => "__builtin_ia32_cvtmask2b256", - "llvm.x86.avx512.cvtmask2b.512" => "__builtin_ia32_cvtmask2b512", - "llvm.x86.avx512.cvtmask2d.128" => "__builtin_ia32_cvtmask2d128", - "llvm.x86.avx512.cvtmask2d.256" => "__builtin_ia32_cvtmask2d256", - "llvm.x86.avx512.cvtmask2d.512" => "__builtin_ia32_cvtmask2d512", - "llvm.x86.avx512.cvtmask2q.128" => "__builtin_ia32_cvtmask2q128", - "llvm.x86.avx512.cvtmask2q.256" => "__builtin_ia32_cvtmask2q256", - "llvm.x86.avx512.cvtmask2q.512" => "__builtin_ia32_cvtmask2q512", - "llvm.x86.avx512.cvtmask2w.128" => "__builtin_ia32_cvtmask2w128", - "llvm.x86.avx512.cvtmask2w.256" => "__builtin_ia32_cvtmask2w256", - "llvm.x86.avx512.cvtmask2w.512" => "__builtin_ia32_cvtmask2w512", - "llvm.x86.avx512.cvtq2mask.128" => "__builtin_ia32_cvtq2mask128", - "llvm.x86.avx512.cvtq2mask.256" => "__builtin_ia32_cvtq2mask256", - "llvm.x86.avx512.cvtq2mask.512" => "__builtin_ia32_cvtq2mask512", - "llvm.x86.avx512.cvtsd2usi" => "__builtin_ia32_cvtsd2usi", - "llvm.x86.avx512.cvtsd2usi64" => "__builtin_ia32_cvtsd2usi64", - "llvm.x86.avx512.cvtsi2sd32" => "__builtin_ia32_cvtsi2sd32", "llvm.x86.avx512.cvtsi2sd64" => "__builtin_ia32_cvtsi2sd64", "llvm.x86.avx512.cvtsi2ss32" => "__builtin_ia32_cvtsi2ss32", "llvm.x86.avx512.cvtsi2ss64" => "__builtin_ia32_cvtsi2ss64", - "llvm.x86.avx512.cvtss2usi" => "__builtin_ia32_cvtss2usi", - "llvm.x86.avx512.cvtss2usi64" => "__builtin_ia32_cvtss2usi64", "llvm.x86.avx512.cvttsd2si" => "__builtin_ia32_vcvttsd2si32", "llvm.x86.avx512.cvttsd2si64" => "__builtin_ia32_vcvttsd2si64", "llvm.x86.avx512.cvttsd2usi" => "__builtin_ia32_vcvttsd2usi32", - // [DUPLICATE]: "llvm.x86.avx512.cvttsd2usi" => "__builtin_ia32_cvttsd2usi", "llvm.x86.avx512.cvttsd2usi64" => "__builtin_ia32_vcvttsd2usi64", - // [DUPLICATE]: "llvm.x86.avx512.cvttsd2usi64" => "__builtin_ia32_cvttsd2usi64", "llvm.x86.avx512.cvttss2si" => "__builtin_ia32_vcvttss2si32", "llvm.x86.avx512.cvttss2si64" => "__builtin_ia32_vcvttss2si64", "llvm.x86.avx512.cvttss2usi" => "__builtin_ia32_vcvttss2usi32", - // [DUPLICATE]: "llvm.x86.avx512.cvttss2usi" => "__builtin_ia32_cvttss2usi", "llvm.x86.avx512.cvttss2usi64" => "__builtin_ia32_vcvttss2usi64", - // [DUPLICATE]: "llvm.x86.avx512.cvttss2usi64" => "__builtin_ia32_cvttss2usi64", - "llvm.x86.avx512.cvtusi2sd" => "__builtin_ia32_cvtusi2sd", - // [DUPLICATE]: "llvm.x86.avx512.cvtusi2sd" => "__builtin_ia32_cvtusi2sd32", "llvm.x86.avx512.cvtusi2ss" => "__builtin_ia32_cvtusi2ss32", - // [DUPLICATE]: "llvm.x86.avx512.cvtusi2ss" => "__builtin_ia32_cvtusi2ss", "llvm.x86.avx512.cvtusi642sd" => "__builtin_ia32_cvtusi2sd64", - // [DUPLICATE]: "llvm.x86.avx512.cvtusi642sd" => "__builtin_ia32_cvtusi642sd", "llvm.x86.avx512.cvtusi642ss" => "__builtin_ia32_cvtusi2ss64", - // [DUPLICATE]: "llvm.x86.avx512.cvtusi642ss" => "__builtin_ia32_cvtusi642ss", - "llvm.x86.avx512.cvtw2mask.128" => "__builtin_ia32_cvtw2mask128", - "llvm.x86.avx512.cvtw2mask.256" => "__builtin_ia32_cvtw2mask256", - "llvm.x86.avx512.cvtw2mask.512" => "__builtin_ia32_cvtw2mask512", "llvm.x86.avx512.dbpsadbw.128" => "__builtin_ia32_dbpsadbw128", "llvm.x86.avx512.dbpsadbw.256" => "__builtin_ia32_dbpsadbw256", "llvm.x86.avx512.dbpsadbw.512" => "__builtin_ia32_dbpsadbw512", "llvm.x86.avx512.div.pd.512" => "__builtin_ia32_divpd512", "llvm.x86.avx512.div.ps.512" => "__builtin_ia32_divps512", - "llvm.x86.avx512.exp2.pd" => "__builtin_ia32_exp2pd_mask", - "llvm.x86.avx512.exp2.ps" => "__builtin_ia32_exp2ps_mask", - "llvm.x86.avx512.gather.dpd.512" => "__builtin_ia32_gathersiv8df", - "llvm.x86.avx512.gather.dpi.512" => "__builtin_ia32_gathersiv16si", - "llvm.x86.avx512.gather.dpq.512" => "__builtin_ia32_gathersiv8di", - "llvm.x86.avx512.gather.dps.512" => "__builtin_ia32_gathersiv16sf", - "llvm.x86.avx512.gather.qpd.512" => "__builtin_ia32_gatherdiv8df", - "llvm.x86.avx512.gather.qpi.512" => "__builtin_ia32_gatherdiv16si", - "llvm.x86.avx512.gather.qpq.512" => "__builtin_ia32_gatherdiv8di", - "llvm.x86.avx512.gather.qps.512" => "__builtin_ia32_gatherdiv16sf", - "llvm.x86.avx512.gather3div2.df" => "__builtin_ia32_gather3div2df", - "llvm.x86.avx512.gather3div2.di" => "__builtin_ia32_gather3div2di", - "llvm.x86.avx512.gather3div4.df" => "__builtin_ia32_gather3div4df", - "llvm.x86.avx512.gather3div4.di" => "__builtin_ia32_gather3div4di", - "llvm.x86.avx512.gather3div4.sf" => "__builtin_ia32_gather3div4sf", - "llvm.x86.avx512.gather3div4.si" => "__builtin_ia32_gather3div4si", - "llvm.x86.avx512.gather3div8.sf" => "__builtin_ia32_gather3div8sf", - "llvm.x86.avx512.gather3div8.si" => "__builtin_ia32_gather3div8si", - "llvm.x86.avx512.gather3siv2.df" => "__builtin_ia32_gather3siv2df", - "llvm.x86.avx512.gather3siv2.di" => "__builtin_ia32_gather3siv2di", - "llvm.x86.avx512.gather3siv4.df" => "__builtin_ia32_gather3siv4df", - "llvm.x86.avx512.gather3siv4.di" => "__builtin_ia32_gather3siv4di", - "llvm.x86.avx512.gather3siv4.sf" => "__builtin_ia32_gather3siv4sf", - "llvm.x86.avx512.gather3siv4.si" => "__builtin_ia32_gather3siv4si", - "llvm.x86.avx512.gather3siv8.sf" => "__builtin_ia32_gather3siv8sf", - "llvm.x86.avx512.gather3siv8.si" => "__builtin_ia32_gather3siv8si", - "llvm.x86.avx512.gatherpf.dpd.512" => "__builtin_ia32_gatherpfdpd", - "llvm.x86.avx512.gatherpf.dps.512" => "__builtin_ia32_gatherpfdps", - "llvm.x86.avx512.gatherpf.qpd.512" => "__builtin_ia32_gatherpfqpd", - "llvm.x86.avx512.gatherpf.qps.512" => "__builtin_ia32_gatherpfqps", - "llvm.x86.avx512.kand.w" => "__builtin_ia32_kandhi", - "llvm.x86.avx512.kandn.w" => "__builtin_ia32_kandnhi", - "llvm.x86.avx512.knot.w" => "__builtin_ia32_knothi", - "llvm.x86.avx512.kor.w" => "__builtin_ia32_korhi", - "llvm.x86.avx512.kortestc.w" => "__builtin_ia32_kortestchi", - "llvm.x86.avx512.kortestz.w" => "__builtin_ia32_kortestzhi", - "llvm.x86.avx512.kunpck.bw" => "__builtin_ia32_kunpckhi", - "llvm.x86.avx512.kunpck.dq" => "__builtin_ia32_kunpckdi", - "llvm.x86.avx512.kunpck.wd" => "__builtin_ia32_kunpcksi", - "llvm.x86.avx512.kxnor.w" => "__builtin_ia32_kxnorhi", - "llvm.x86.avx512.kxor.w" => "__builtin_ia32_kxorhi", - "llvm.x86.avx512.mask.add.pd.128" => "__builtin_ia32_addpd128_mask", - "llvm.x86.avx512.mask.add.pd.256" => "__builtin_ia32_addpd256_mask", - "llvm.x86.avx512.mask.add.pd.512" => "__builtin_ia32_addpd512_mask", - "llvm.x86.avx512.mask.add.ps.128" => "__builtin_ia32_addps128_mask", - "llvm.x86.avx512.mask.add.ps.256" => "__builtin_ia32_addps256_mask", - "llvm.x86.avx512.mask.add.ps.512" => "__builtin_ia32_addps512_mask", // [INVALID CONVERSION]: "llvm.x86.avx512.mask.add.sd.round" => "__builtin_ia32_addsd_round_mask", // [INVALID CONVERSION]: "llvm.x86.avx512.mask.add.ss.round" => "__builtin_ia32_addss_round_mask", - "llvm.x86.avx512.mask.and.pd.128" => "__builtin_ia32_andpd128_mask", - "llvm.x86.avx512.mask.and.pd.256" => "__builtin_ia32_andpd256_mask", - "llvm.x86.avx512.mask.and.pd.512" => "__builtin_ia32_andpd512_mask", - "llvm.x86.avx512.mask.and.ps.128" => "__builtin_ia32_andps128_mask", - "llvm.x86.avx512.mask.and.ps.256" => "__builtin_ia32_andps256_mask", - "llvm.x86.avx512.mask.and.ps.512" => "__builtin_ia32_andps512_mask", - "llvm.x86.avx512.mask.andn.pd.128" => "__builtin_ia32_andnpd128_mask", - "llvm.x86.avx512.mask.andn.pd.256" => "__builtin_ia32_andnpd256_mask", - "llvm.x86.avx512.mask.andn.pd.512" => "__builtin_ia32_andnpd512_mask", - "llvm.x86.avx512.mask.andn.ps.128" => "__builtin_ia32_andnps128_mask", - "llvm.x86.avx512.mask.andn.ps.256" => "__builtin_ia32_andnps256_mask", - "llvm.x86.avx512.mask.andn.ps.512" => "__builtin_ia32_andnps512_mask", - "llvm.x86.avx512.mask.blend.d.512" => "__builtin_ia32_blendmd_512_mask", - "llvm.x86.avx512.mask.blend.pd.512" => "__builtin_ia32_blendmpd_512_mask", - "llvm.x86.avx512.mask.blend.ps.512" => "__builtin_ia32_blendmps_512_mask", - "llvm.x86.avx512.mask.blend.q.512" => "__builtin_ia32_blendmq_512_mask", - "llvm.x86.avx512.mask.broadcastf32x2.256" => "__builtin_ia32_broadcastf32x2_256_mask", - "llvm.x86.avx512.mask.broadcastf32x2.512" => "__builtin_ia32_broadcastf32x2_512_mask", - "llvm.x86.avx512.mask.broadcastf32x4.256" => "__builtin_ia32_broadcastf32x4_256_mask", - "llvm.x86.avx512.mask.broadcastf32x4.512" => "__builtin_ia32_broadcastf32x4_512", - "llvm.x86.avx512.mask.broadcastf32x8.512" => "__builtin_ia32_broadcastf32x8_512_mask", - "llvm.x86.avx512.mask.broadcastf64x2.256" => "__builtin_ia32_broadcastf64x2_256_mask", - "llvm.x86.avx512.mask.broadcastf64x2.512" => "__builtin_ia32_broadcastf64x2_512_mask", - "llvm.x86.avx512.mask.broadcastf64x4.512" => "__builtin_ia32_broadcastf64x4_512", - "llvm.x86.avx512.mask.broadcasti32x2.128" => "__builtin_ia32_broadcasti32x2_128_mask", - "llvm.x86.avx512.mask.broadcasti32x2.256" => "__builtin_ia32_broadcasti32x2_256_mask", - "llvm.x86.avx512.mask.broadcasti32x2.512" => "__builtin_ia32_broadcasti32x2_512_mask", - "llvm.x86.avx512.mask.broadcasti32x4.256" => "__builtin_ia32_broadcasti32x4_256_mask", - "llvm.x86.avx512.mask.broadcasti32x4.512" => "__builtin_ia32_broadcasti32x4_512", - "llvm.x86.avx512.mask.broadcasti32x8.512" => "__builtin_ia32_broadcasti32x8_512_mask", - "llvm.x86.avx512.mask.broadcasti64x2.256" => "__builtin_ia32_broadcasti64x2_256_mask", - "llvm.x86.avx512.mask.broadcasti64x2.512" => "__builtin_ia32_broadcasti64x2_512_mask", - "llvm.x86.avx512.mask.broadcasti64x4.512" => "__builtin_ia32_broadcasti64x4_512", - "llvm.x86.avx512.mask.cmp.pd.128" => "__builtin_ia32_cmppd128_mask", - "llvm.x86.avx512.mask.cmp.pd.256" => "__builtin_ia32_cmppd256_mask", - "llvm.x86.avx512.mask.cmp.pd.512" => "__builtin_ia32_cmppd512_mask", - "llvm.x86.avx512.mask.cmp.ps.128" => "__builtin_ia32_cmpps128_mask", - "llvm.x86.avx512.mask.cmp.ps.256" => "__builtin_ia32_cmpps256_mask", - "llvm.x86.avx512.mask.cmp.ps.512" => "__builtin_ia32_cmpps512_mask", "llvm.x86.avx512.mask.cmp.sd" => "__builtin_ia32_cmpsd_mask", "llvm.x86.avx512.mask.cmp.ss" => "__builtin_ia32_cmpss_mask", - "llvm.x86.avx512.mask.compress.d.128" => "__builtin_ia32_compresssi128_mask", - "llvm.x86.avx512.mask.compress.d.256" => "__builtin_ia32_compresssi256_mask", - "llvm.x86.avx512.mask.compress.d.512" => "__builtin_ia32_compresssi512_mask", - "llvm.x86.avx512.mask.compress.pd.128" => "__builtin_ia32_compressdf128_mask", - "llvm.x86.avx512.mask.compress.pd.256" => "__builtin_ia32_compressdf256_mask", - "llvm.x86.avx512.mask.compress.pd.512" => "__builtin_ia32_compressdf512_mask", - "llvm.x86.avx512.mask.compress.ps.128" => "__builtin_ia32_compresssf128_mask", - "llvm.x86.avx512.mask.compress.ps.256" => "__builtin_ia32_compresssf256_mask", - "llvm.x86.avx512.mask.compress.ps.512" => "__builtin_ia32_compresssf512_mask", - "llvm.x86.avx512.mask.compress.q.128" => "__builtin_ia32_compressdi128_mask", - "llvm.x86.avx512.mask.compress.q.256" => "__builtin_ia32_compressdi256_mask", - "llvm.x86.avx512.mask.compress.q.512" => "__builtin_ia32_compressdi512_mask", - "llvm.x86.avx512.mask.compress.store.d.128" => "__builtin_ia32_compressstoresi128_mask", - "llvm.x86.avx512.mask.compress.store.d.256" => "__builtin_ia32_compressstoresi256_mask", - "llvm.x86.avx512.mask.compress.store.d.512" => "__builtin_ia32_compressstoresi512_mask", - "llvm.x86.avx512.mask.compress.store.pd.128" => "__builtin_ia32_compressstoredf128_mask", - "llvm.x86.avx512.mask.compress.store.pd.256" => "__builtin_ia32_compressstoredf256_mask", - "llvm.x86.avx512.mask.compress.store.pd.512" => "__builtin_ia32_compressstoredf512_mask", - "llvm.x86.avx512.mask.compress.store.ps.128" => "__builtin_ia32_compressstoresf128_mask", - "llvm.x86.avx512.mask.compress.store.ps.256" => "__builtin_ia32_compressstoresf256_mask", - "llvm.x86.avx512.mask.compress.store.ps.512" => "__builtin_ia32_compressstoresf512_mask", - "llvm.x86.avx512.mask.compress.store.q.128" => "__builtin_ia32_compressstoredi128_mask", - "llvm.x86.avx512.mask.compress.store.q.256" => "__builtin_ia32_compressstoredi256_mask", - "llvm.x86.avx512.mask.compress.store.q.512" => "__builtin_ia32_compressstoredi512_mask", - "llvm.x86.avx512.mask.conflict.d.128" => "__builtin_ia32_vpconflictsi_128_mask", - "llvm.x86.avx512.mask.conflict.d.256" => "__builtin_ia32_vpconflictsi_256_mask", - "llvm.x86.avx512.mask.conflict.d.512" => "__builtin_ia32_vpconflictsi_512_mask", - "llvm.x86.avx512.mask.conflict.q.128" => "__builtin_ia32_vpconflictdi_128_mask", - "llvm.x86.avx512.mask.conflict.q.256" => "__builtin_ia32_vpconflictdi_256_mask", - "llvm.x86.avx512.mask.conflict.q.512" => "__builtin_ia32_vpconflictdi_512_mask", - "llvm.x86.avx512.mask.cvtdq2pd.128" => "__builtin_ia32_cvtdq2pd128_mask", - "llvm.x86.avx512.mask.cvtdq2pd.256" => "__builtin_ia32_cvtdq2pd256_mask", - "llvm.x86.avx512.mask.cvtdq2pd.512" => "__builtin_ia32_cvtdq2pd512_mask", - "llvm.x86.avx512.mask.cvtdq2ps.128" => "__builtin_ia32_cvtdq2ps128_mask", - "llvm.x86.avx512.mask.cvtdq2ps.256" => "__builtin_ia32_cvtdq2ps256_mask", - "llvm.x86.avx512.mask.cvtdq2ps.512" => "__builtin_ia32_cvtdq2ps512_mask", "llvm.x86.avx512.mask.cvtpd2dq.128" => "__builtin_ia32_cvtpd2dq128_mask", - "llvm.x86.avx512.mask.cvtpd2dq.256" => "__builtin_ia32_cvtpd2dq256_mask", "llvm.x86.avx512.mask.cvtpd2dq.512" => "__builtin_ia32_cvtpd2dq512_mask", "llvm.x86.avx512.mask.cvtpd2ps" => "__builtin_ia32_cvtpd2ps_mask", - "llvm.x86.avx512.mask.cvtpd2ps.256" => "__builtin_ia32_cvtpd2ps256_mask", "llvm.x86.avx512.mask.cvtpd2ps.512" => "__builtin_ia32_cvtpd2ps512_mask", "llvm.x86.avx512.mask.cvtpd2qq.128" => "__builtin_ia32_cvtpd2qq128_mask", "llvm.x86.avx512.mask.cvtpd2qq.256" => "__builtin_ia32_cvtpd2qq256_mask", @@ -7904,8 +7180,6 @@ match name { "llvm.x86.avx512.mask.cvtps2dq.128" => "__builtin_ia32_cvtps2dq128_mask", "llvm.x86.avx512.mask.cvtps2dq.256" => "__builtin_ia32_cvtps2dq256_mask", "llvm.x86.avx512.mask.cvtps2dq.512" => "__builtin_ia32_cvtps2dq512_mask", - "llvm.x86.avx512.mask.cvtps2pd.128" => "__builtin_ia32_cvtps2pd128_mask", - "llvm.x86.avx512.mask.cvtps2pd.256" => "__builtin_ia32_cvtps2pd256_mask", "llvm.x86.avx512.mask.cvtps2pd.512" => "__builtin_ia32_cvtps2pd512_mask", "llvm.x86.avx512.mask.cvtps2qq.128" => "__builtin_ia32_cvtps2qq128_mask", "llvm.x86.avx512.mask.cvtps2qq.256" => "__builtin_ia32_cvtps2qq256_mask", @@ -7916,16 +7190,10 @@ match name { "llvm.x86.avx512.mask.cvtps2uqq.128" => "__builtin_ia32_cvtps2uqq128_mask", "llvm.x86.avx512.mask.cvtps2uqq.256" => "__builtin_ia32_cvtps2uqq256_mask", "llvm.x86.avx512.mask.cvtps2uqq.512" => "__builtin_ia32_cvtps2uqq512_mask", - "llvm.x86.avx512.mask.cvtqq2pd.128" => "__builtin_ia32_cvtqq2pd128_mask", - "llvm.x86.avx512.mask.cvtqq2pd.256" => "__builtin_ia32_cvtqq2pd256_mask", - "llvm.x86.avx512.mask.cvtqq2pd.512" => "__builtin_ia32_cvtqq2pd512_mask", "llvm.x86.avx512.mask.cvtqq2ps.128" => "__builtin_ia32_cvtqq2ps128_mask", - "llvm.x86.avx512.mask.cvtqq2ps.256" => "__builtin_ia32_cvtqq2ps256_mask", - "llvm.x86.avx512.mask.cvtqq2ps.512" => "__builtin_ia32_cvtqq2ps512_mask", // [INVALID CONVERSION]: "llvm.x86.avx512.mask.cvtsd2ss.round" => "__builtin_ia32_cvtsd2ss_round_mask", // [INVALID CONVERSION]: "llvm.x86.avx512.mask.cvtss2sd.round" => "__builtin_ia32_cvtss2sd_round_mask", "llvm.x86.avx512.mask.cvttpd2dq.128" => "__builtin_ia32_cvttpd2dq128_mask", - "llvm.x86.avx512.mask.cvttpd2dq.256" => "__builtin_ia32_cvttpd2dq256_mask", "llvm.x86.avx512.mask.cvttpd2dq.512" => "__builtin_ia32_cvttpd2dq512_mask", "llvm.x86.avx512.mask.cvttpd2qq.128" => "__builtin_ia32_cvttpd2qq128_mask", "llvm.x86.avx512.mask.cvttpd2qq.256" => "__builtin_ia32_cvttpd2qq256_mask", @@ -7936,8 +7204,6 @@ match name { "llvm.x86.avx512.mask.cvttpd2uqq.128" => "__builtin_ia32_cvttpd2uqq128_mask", "llvm.x86.avx512.mask.cvttpd2uqq.256" => "__builtin_ia32_cvttpd2uqq256_mask", "llvm.x86.avx512.mask.cvttpd2uqq.512" => "__builtin_ia32_cvttpd2uqq512_mask", - "llvm.x86.avx512.mask.cvttps2dq.128" => "__builtin_ia32_cvttps2dq128_mask", - "llvm.x86.avx512.mask.cvttps2dq.256" => "__builtin_ia32_cvttps2dq256_mask", "llvm.x86.avx512.mask.cvttps2dq.512" => "__builtin_ia32_cvttps2dq512_mask", "llvm.x86.avx512.mask.cvttps2qq.128" => "__builtin_ia32_cvttps2qq128_mask", "llvm.x86.avx512.mask.cvttps2qq.256" => "__builtin_ia32_cvttps2qq256_mask", @@ -7948,53 +7214,9 @@ match name { "llvm.x86.avx512.mask.cvttps2uqq.128" => "__builtin_ia32_cvttps2uqq128_mask", "llvm.x86.avx512.mask.cvttps2uqq.256" => "__builtin_ia32_cvttps2uqq256_mask", "llvm.x86.avx512.mask.cvttps2uqq.512" => "__builtin_ia32_cvttps2uqq512_mask", - "llvm.x86.avx512.mask.cvtudq2pd.128" => "__builtin_ia32_cvtudq2pd128_mask", - "llvm.x86.avx512.mask.cvtudq2pd.256" => "__builtin_ia32_cvtudq2pd256_mask", - "llvm.x86.avx512.mask.cvtudq2pd.512" => "__builtin_ia32_cvtudq2pd512_mask", - "llvm.x86.avx512.mask.cvtudq2ps.128" => "__builtin_ia32_cvtudq2ps128_mask", - "llvm.x86.avx512.mask.cvtudq2ps.256" => "__builtin_ia32_cvtudq2ps256_mask", - "llvm.x86.avx512.mask.cvtudq2ps.512" => "__builtin_ia32_cvtudq2ps512_mask", - "llvm.x86.avx512.mask.cvtuqq2pd.128" => "__builtin_ia32_cvtuqq2pd128_mask", - "llvm.x86.avx512.mask.cvtuqq2pd.256" => "__builtin_ia32_cvtuqq2pd256_mask", - "llvm.x86.avx512.mask.cvtuqq2pd.512" => "__builtin_ia32_cvtuqq2pd512_mask", "llvm.x86.avx512.mask.cvtuqq2ps.128" => "__builtin_ia32_cvtuqq2ps128_mask", - "llvm.x86.avx512.mask.cvtuqq2ps.256" => "__builtin_ia32_cvtuqq2ps256_mask", - "llvm.x86.avx512.mask.cvtuqq2ps.512" => "__builtin_ia32_cvtuqq2ps512_mask", - "llvm.x86.avx512.mask.dbpsadbw.128" => "__builtin_ia32_dbpsadbw128_mask", - "llvm.x86.avx512.mask.dbpsadbw.256" => "__builtin_ia32_dbpsadbw256_mask", - "llvm.x86.avx512.mask.dbpsadbw.512" => "__builtin_ia32_dbpsadbw512_mask", - "llvm.x86.avx512.mask.div.pd.128" => "__builtin_ia32_divpd_mask", - "llvm.x86.avx512.mask.div.pd.256" => "__builtin_ia32_divpd256_mask", - "llvm.x86.avx512.mask.div.pd.512" => "__builtin_ia32_divpd512_mask", - "llvm.x86.avx512.mask.div.ps.128" => "__builtin_ia32_divps_mask", - "llvm.x86.avx512.mask.div.ps.256" => "__builtin_ia32_divps256_mask", - "llvm.x86.avx512.mask.div.ps.512" => "__builtin_ia32_divps512_mask", // [INVALID CONVERSION]: "llvm.x86.avx512.mask.div.sd.round" => "__builtin_ia32_divsd_round_mask", // [INVALID CONVERSION]: "llvm.x86.avx512.mask.div.ss.round" => "__builtin_ia32_divss_round_mask", - "llvm.x86.avx512.mask.expand.d.128" => "__builtin_ia32_expandsi128_mask", - "llvm.x86.avx512.mask.expand.d.256" => "__builtin_ia32_expandsi256_mask", - "llvm.x86.avx512.mask.expand.d.512" => "__builtin_ia32_expandsi512_mask", - "llvm.x86.avx512.mask.expand.load.d.128" => "__builtin_ia32_expandloadsi128_mask", - "llvm.x86.avx512.mask.expand.load.d.256" => "__builtin_ia32_expandloadsi256_mask", - "llvm.x86.avx512.mask.expand.load.d.512" => "__builtin_ia32_expandloadsi512_mask", - "llvm.x86.avx512.mask.expand.load.pd.128" => "__builtin_ia32_expandloaddf128_mask", - "llvm.x86.avx512.mask.expand.load.pd.256" => "__builtin_ia32_expandloaddf256_mask", - "llvm.x86.avx512.mask.expand.load.pd.512" => "__builtin_ia32_expandloaddf512_mask", - "llvm.x86.avx512.mask.expand.load.ps.128" => "__builtin_ia32_expandloadsf128_mask", - "llvm.x86.avx512.mask.expand.load.ps.256" => "__builtin_ia32_expandloadsf256_mask", - "llvm.x86.avx512.mask.expand.load.ps.512" => "__builtin_ia32_expandloadsf512_mask", - "llvm.x86.avx512.mask.expand.load.q.128" => "__builtin_ia32_expandloaddi128_mask", - "llvm.x86.avx512.mask.expand.load.q.256" => "__builtin_ia32_expandloaddi256_mask", - "llvm.x86.avx512.mask.expand.load.q.512" => "__builtin_ia32_expandloaddi512_mask", - "llvm.x86.avx512.mask.expand.pd.128" => "__builtin_ia32_expanddf128_mask", - "llvm.x86.avx512.mask.expand.pd.256" => "__builtin_ia32_expanddf256_mask", - "llvm.x86.avx512.mask.expand.pd.512" => "__builtin_ia32_expanddf512_mask", - "llvm.x86.avx512.mask.expand.ps.128" => "__builtin_ia32_expandsf128_mask", - "llvm.x86.avx512.mask.expand.ps.256" => "__builtin_ia32_expandsf256_mask", - "llvm.x86.avx512.mask.expand.ps.512" => "__builtin_ia32_expandsf512_mask", - "llvm.x86.avx512.mask.expand.q.128" => "__builtin_ia32_expanddi128_mask", - "llvm.x86.avx512.mask.expand.q.256" => "__builtin_ia32_expanddi256_mask", - "llvm.x86.avx512.mask.expand.q.512" => "__builtin_ia32_expanddi512_mask", "llvm.x86.avx512.mask.fixupimm.pd.128" => "__builtin_ia32_fixupimmpd128_mask", "llvm.x86.avx512.mask.fixupimm.pd.256" => "__builtin_ia32_fixupimmpd256_mask", "llvm.x86.avx512.mask.fixupimm.pd.512" => "__builtin_ia32_fixupimmpd512_mask", @@ -8003,12 +7225,6 @@ match name { "llvm.x86.avx512.mask.fixupimm.ps.512" => "__builtin_ia32_fixupimmps512_mask", "llvm.x86.avx512.mask.fixupimm.sd" => "__builtin_ia32_fixupimmsd_mask", "llvm.x86.avx512.mask.fixupimm.ss" => "__builtin_ia32_fixupimmss_mask", - "llvm.x86.avx512.mask.fpclass.pd.128" => "__builtin_ia32_fpclasspd128_mask", - "llvm.x86.avx512.mask.fpclass.pd.256" => "__builtin_ia32_fpclasspd256_mask", - "llvm.x86.avx512.mask.fpclass.pd.512" => "__builtin_ia32_fpclasspd512_mask", - "llvm.x86.avx512.mask.fpclass.ps.128" => "__builtin_ia32_fpclassps128_mask", - "llvm.x86.avx512.mask.fpclass.ps.256" => "__builtin_ia32_fpclassps256_mask", - "llvm.x86.avx512.mask.fpclass.ps.512" => "__builtin_ia32_fpclassps512_mask", "llvm.x86.avx512.mask.fpclass.sd" => "__builtin_ia32_fpclasssd_mask", "llvm.x86.avx512.mask.fpclass.ss" => "__builtin_ia32_fpclassss_mask", "llvm.x86.avx512.mask.getexp.pd.128" => "__builtin_ia32_getexppd128_mask", @@ -8027,226 +7243,19 @@ match name { "llvm.x86.avx512.mask.getmant.ps.512" => "__builtin_ia32_getmantps512_mask", // [INVALID CONVERSION]: "llvm.x86.avx512.mask.getmant.sd" => "__builtin_ia32_getmantsd_round_mask", // [INVALID CONVERSION]: "llvm.x86.avx512.mask.getmant.ss" => "__builtin_ia32_getmantss_round_mask", - "llvm.x86.avx512.mask.insertf32x4.256" => "__builtin_ia32_insertf32x4_256_mask", - "llvm.x86.avx512.mask.insertf32x4.512" => "__builtin_ia32_insertf32x4_mask", - "llvm.x86.avx512.mask.insertf32x8.512" => "__builtin_ia32_insertf32x8_mask", - "llvm.x86.avx512.mask.insertf64x2.256" => "__builtin_ia32_insertf64x2_256_mask", - "llvm.x86.avx512.mask.insertf64x2.512" => "__builtin_ia32_insertf64x2_512_mask", - "llvm.x86.avx512.mask.insertf64x4.512" => "__builtin_ia32_insertf64x4_mask", - "llvm.x86.avx512.mask.inserti32x4.256" => "__builtin_ia32_inserti32x4_256_mask", - "llvm.x86.avx512.mask.inserti32x4.512" => "__builtin_ia32_inserti32x4_mask", - "llvm.x86.avx512.mask.inserti32x8.512" => "__builtin_ia32_inserti32x8_mask", - "llvm.x86.avx512.mask.inserti64x2.256" => "__builtin_ia32_inserti64x2_256_mask", - "llvm.x86.avx512.mask.inserti64x2.512" => "__builtin_ia32_inserti64x2_512_mask", - "llvm.x86.avx512.mask.inserti64x4.512" => "__builtin_ia32_inserti64x4_mask", - "llvm.x86.avx512.mask.loadu.d.512" => "__builtin_ia32_loaddqusi512_mask", - "llvm.x86.avx512.mask.loadu.pd.512" => "__builtin_ia32_loadupd512_mask", - "llvm.x86.avx512.mask.loadu.ps.512" => "__builtin_ia32_loadups512_mask", - "llvm.x86.avx512.mask.loadu.q.512" => "__builtin_ia32_loaddqudi512_mask", - "llvm.x86.avx512.mask.lzcnt.d.512" => "__builtin_ia32_vplzcntd_512_mask", - "llvm.x86.avx512.mask.lzcnt.q.512" => "__builtin_ia32_vplzcntq_512_mask", - "llvm.x86.avx512.mask.max.pd.128" => "__builtin_ia32_maxpd_mask", - "llvm.x86.avx512.mask.max.pd.256" => "__builtin_ia32_maxpd256_mask", - "llvm.x86.avx512.mask.max.pd.512" => "__builtin_ia32_maxpd512_mask", - "llvm.x86.avx512.mask.max.ps.128" => "__builtin_ia32_maxps_mask", - "llvm.x86.avx512.mask.max.ps.256" => "__builtin_ia32_maxps256_mask", - "llvm.x86.avx512.mask.max.ps.512" => "__builtin_ia32_maxps512_mask", // [INVALID CONVERSION]: "llvm.x86.avx512.mask.max.sd.round" => "__builtin_ia32_maxsd_round_mask", // [INVALID CONVERSION]: "llvm.x86.avx512.mask.max.ss.round" => "__builtin_ia32_maxss_round_mask", - "llvm.x86.avx512.mask.min.pd.128" => "__builtin_ia32_minpd_mask", - "llvm.x86.avx512.mask.min.pd.256" => "__builtin_ia32_minpd256_mask", - "llvm.x86.avx512.mask.min.pd.512" => "__builtin_ia32_minpd512_mask", - "llvm.x86.avx512.mask.min.ps.128" => "__builtin_ia32_minps_mask", - "llvm.x86.avx512.mask.min.ps.256" => "__builtin_ia32_minps256_mask", - "llvm.x86.avx512.mask.min.ps.512" => "__builtin_ia32_minps512_mask", // [INVALID CONVERSION]: "llvm.x86.avx512.mask.min.sd.round" => "__builtin_ia32_minsd_round_mask", // [INVALID CONVERSION]: "llvm.x86.avx512.mask.min.ss.round" => "__builtin_ia32_minss_round_mask", - "llvm.x86.avx512.mask.move.sd" => "__builtin_ia32_movsd_mask", - "llvm.x86.avx512.mask.move.ss" => "__builtin_ia32_movss_mask", - "llvm.x86.avx512.mask.mul.pd.128" => "__builtin_ia32_mulpd_mask", - "llvm.x86.avx512.mask.mul.pd.256" => "__builtin_ia32_mulpd256_mask", - "llvm.x86.avx512.mask.mul.pd.512" => "__builtin_ia32_mulpd512_mask", - "llvm.x86.avx512.mask.mul.ps.128" => "__builtin_ia32_mulps_mask", - "llvm.x86.avx512.mask.mul.ps.256" => "__builtin_ia32_mulps256_mask", - "llvm.x86.avx512.mask.mul.ps.512" => "__builtin_ia32_mulps512_mask", // [INVALID CONVERSION]: "llvm.x86.avx512.mask.mul.sd.round" => "__builtin_ia32_mulsd_round_mask", // [INVALID CONVERSION]: "llvm.x86.avx512.mask.mul.ss.round" => "__builtin_ia32_mulss_round_mask", - "llvm.x86.avx512.mask.or.pd.128" => "__builtin_ia32_orpd128_mask", - "llvm.x86.avx512.mask.or.pd.256" => "__builtin_ia32_orpd256_mask", - "llvm.x86.avx512.mask.or.pd.512" => "__builtin_ia32_orpd512_mask", - "llvm.x86.avx512.mask.or.ps.128" => "__builtin_ia32_orps128_mask", - "llvm.x86.avx512.mask.or.ps.256" => "__builtin_ia32_orps256_mask", - "llvm.x86.avx512.mask.or.ps.512" => "__builtin_ia32_orps512_mask", - "llvm.x86.avx512.mask.pabs.b.128" => "__builtin_ia32_pabsb128_mask", - "llvm.x86.avx512.mask.pabs.b.256" => "__builtin_ia32_pabsb256_mask", - "llvm.x86.avx512.mask.pabs.b.512" => "__builtin_ia32_pabsb512_mask", - "llvm.x86.avx512.mask.pabs.d.128" => "__builtin_ia32_pabsd128_mask", - "llvm.x86.avx512.mask.pabs.d.256" => "__builtin_ia32_pabsd256_mask", - "llvm.x86.avx512.mask.pabs.d.512" => "__builtin_ia32_pabsd512_mask", - "llvm.x86.avx512.mask.pabs.q.128" => "__builtin_ia32_pabsq128_mask", - "llvm.x86.avx512.mask.pabs.q.256" => "__builtin_ia32_pabsq256_mask", - "llvm.x86.avx512.mask.pabs.q.512" => "__builtin_ia32_pabsq512_mask", - "llvm.x86.avx512.mask.pabs.w.128" => "__builtin_ia32_pabsw128_mask", - "llvm.x86.avx512.mask.pabs.w.256" => "__builtin_ia32_pabsw256_mask", - "llvm.x86.avx512.mask.pabs.w.512" => "__builtin_ia32_pabsw512_mask", - "llvm.x86.avx512.mask.packssdw.128" => "__builtin_ia32_packssdw128_mask", - "llvm.x86.avx512.mask.packssdw.256" => "__builtin_ia32_packssdw256_mask", - "llvm.x86.avx512.mask.packssdw.512" => "__builtin_ia32_packssdw512_mask", - "llvm.x86.avx512.mask.packsswb.128" => "__builtin_ia32_packsswb128_mask", - "llvm.x86.avx512.mask.packsswb.256" => "__builtin_ia32_packsswb256_mask", - "llvm.x86.avx512.mask.packsswb.512" => "__builtin_ia32_packsswb512_mask", - "llvm.x86.avx512.mask.packusdw.128" => "__builtin_ia32_packusdw128_mask", - "llvm.x86.avx512.mask.packusdw.256" => "__builtin_ia32_packusdw256_mask", - "llvm.x86.avx512.mask.packusdw.512" => "__builtin_ia32_packusdw512_mask", - "llvm.x86.avx512.mask.packuswb.128" => "__builtin_ia32_packuswb128_mask", - "llvm.x86.avx512.mask.packuswb.256" => "__builtin_ia32_packuswb256_mask", - "llvm.x86.avx512.mask.packuswb.512" => "__builtin_ia32_packuswb512_mask", - "llvm.x86.avx512.mask.padd.b.128" => "__builtin_ia32_paddb128_mask", - "llvm.x86.avx512.mask.padd.b.256" => "__builtin_ia32_paddb256_mask", - "llvm.x86.avx512.mask.padd.b.512" => "__builtin_ia32_paddb512_mask", - "llvm.x86.avx512.mask.padd.d.128" => "__builtin_ia32_paddd128_mask", - "llvm.x86.avx512.mask.padd.d.256" => "__builtin_ia32_paddd256_mask", - "llvm.x86.avx512.mask.padd.d.512" => "__builtin_ia32_paddd512_mask", - "llvm.x86.avx512.mask.padd.q.128" => "__builtin_ia32_paddq128_mask", - "llvm.x86.avx512.mask.padd.q.256" => "__builtin_ia32_paddq256_mask", - "llvm.x86.avx512.mask.padd.q.512" => "__builtin_ia32_paddq512_mask", - "llvm.x86.avx512.mask.padd.w.128" => "__builtin_ia32_paddw128_mask", - "llvm.x86.avx512.mask.padd.w.256" => "__builtin_ia32_paddw256_mask", - "llvm.x86.avx512.mask.padd.w.512" => "__builtin_ia32_paddw512_mask", - "llvm.x86.avx512.mask.padds.b.128" => "__builtin_ia32_paddsb128_mask", - "llvm.x86.avx512.mask.padds.b.256" => "__builtin_ia32_paddsb256_mask", - "llvm.x86.avx512.mask.padds.b.512" => "__builtin_ia32_paddsb512_mask", - "llvm.x86.avx512.mask.padds.w.128" => "__builtin_ia32_paddsw128_mask", - "llvm.x86.avx512.mask.padds.w.256" => "__builtin_ia32_paddsw256_mask", - "llvm.x86.avx512.mask.padds.w.512" => "__builtin_ia32_paddsw512_mask", - "llvm.x86.avx512.mask.paddus.b.128" => "__builtin_ia32_paddusb128_mask", - "llvm.x86.avx512.mask.paddus.b.256" => "__builtin_ia32_paddusb256_mask", - "llvm.x86.avx512.mask.paddus.b.512" => "__builtin_ia32_paddusb512_mask", - "llvm.x86.avx512.mask.paddus.w.128" => "__builtin_ia32_paddusw128_mask", - "llvm.x86.avx512.mask.paddus.w.256" => "__builtin_ia32_paddusw256_mask", - "llvm.x86.avx512.mask.paddus.w.512" => "__builtin_ia32_paddusw512_mask", - "llvm.x86.avx512.mask.pand.d.512" => "__builtin_ia32_pandd512_mask", - "llvm.x86.avx512.mask.pand.q.512" => "__builtin_ia32_pandq512_mask", - "llvm.x86.avx512.mask.pavg.b.128" => "__builtin_ia32_pavgb128_mask", - "llvm.x86.avx512.mask.pavg.b.256" => "__builtin_ia32_pavgb256_mask", - "llvm.x86.avx512.mask.pavg.b.512" => "__builtin_ia32_pavgb512_mask", - "llvm.x86.avx512.mask.pavg.w.128" => "__builtin_ia32_pavgw128_mask", - "llvm.x86.avx512.mask.pavg.w.256" => "__builtin_ia32_pavgw256_mask", - "llvm.x86.avx512.mask.pavg.w.512" => "__builtin_ia32_pavgw512_mask", - "llvm.x86.avx512.mask.pbroadcast.b.gpr.128" => "__builtin_ia32_pbroadcastb128_gpr_mask", - "llvm.x86.avx512.mask.pbroadcast.b.gpr.256" => "__builtin_ia32_pbroadcastb256_gpr_mask", - "llvm.x86.avx512.mask.pbroadcast.b.gpr.512" => "__builtin_ia32_pbroadcastb512_gpr_mask", - "llvm.x86.avx512.mask.pbroadcast.d.gpr.128" => "__builtin_ia32_pbroadcastd128_gpr_mask", - "llvm.x86.avx512.mask.pbroadcast.d.gpr.256" => "__builtin_ia32_pbroadcastd256_gpr_mask", - "llvm.x86.avx512.mask.pbroadcast.d.gpr.512" => "__builtin_ia32_pbroadcastd512_gpr_mask", - "llvm.x86.avx512.mask.pbroadcast.q.gpr.128" => "__builtin_ia32_pbroadcastq128_gpr_mask", - "llvm.x86.avx512.mask.pbroadcast.q.gpr.256" => "__builtin_ia32_pbroadcastq256_gpr_mask", - "llvm.x86.avx512.mask.pbroadcast.q.gpr.512" => "__builtin_ia32_pbroadcastq512_gpr_mask", - "llvm.x86.avx512.mask.pbroadcast.q.mem.512" => "__builtin_ia32_pbroadcastq512_mem_mask", - "llvm.x86.avx512.mask.pbroadcast.w.gpr.128" => "__builtin_ia32_pbroadcastw128_gpr_mask", - "llvm.x86.avx512.mask.pbroadcast.w.gpr.256" => "__builtin_ia32_pbroadcastw256_gpr_mask", - "llvm.x86.avx512.mask.pbroadcast.w.gpr.512" => "__builtin_ia32_pbroadcastw512_gpr_mask", - "llvm.x86.avx512.mask.pcmpeq.b.128" => "__builtin_ia32_pcmpeqb128_mask", - "llvm.x86.avx512.mask.pcmpeq.b.256" => "__builtin_ia32_pcmpeqb256_mask", - "llvm.x86.avx512.mask.pcmpeq.b.512" => "__builtin_ia32_pcmpeqb512_mask", - "llvm.x86.avx512.mask.pcmpeq.d.128" => "__builtin_ia32_pcmpeqd128_mask", - "llvm.x86.avx512.mask.pcmpeq.d.256" => "__builtin_ia32_pcmpeqd256_mask", - "llvm.x86.avx512.mask.pcmpeq.d.512" => "__builtin_ia32_pcmpeqd512_mask", - "llvm.x86.avx512.mask.pcmpeq.q.128" => "__builtin_ia32_pcmpeqq128_mask", - "llvm.x86.avx512.mask.pcmpeq.q.256" => "__builtin_ia32_pcmpeqq256_mask", - "llvm.x86.avx512.mask.pcmpeq.q.512" => "__builtin_ia32_pcmpeqq512_mask", - "llvm.x86.avx512.mask.pcmpeq.w.128" => "__builtin_ia32_pcmpeqw128_mask", - "llvm.x86.avx512.mask.pcmpeq.w.256" => "__builtin_ia32_pcmpeqw256_mask", - "llvm.x86.avx512.mask.pcmpeq.w.512" => "__builtin_ia32_pcmpeqw512_mask", - "llvm.x86.avx512.mask.pcmpgt.b.128" => "__builtin_ia32_pcmpgtb128_mask", - "llvm.x86.avx512.mask.pcmpgt.b.256" => "__builtin_ia32_pcmpgtb256_mask", - "llvm.x86.avx512.mask.pcmpgt.b.512" => "__builtin_ia32_pcmpgtb512_mask", - "llvm.x86.avx512.mask.pcmpgt.d.128" => "__builtin_ia32_pcmpgtd128_mask", - "llvm.x86.avx512.mask.pcmpgt.d.256" => "__builtin_ia32_pcmpgtd256_mask", - "llvm.x86.avx512.mask.pcmpgt.d.512" => "__builtin_ia32_pcmpgtd512_mask", - "llvm.x86.avx512.mask.pcmpgt.q.128" => "__builtin_ia32_pcmpgtq128_mask", - "llvm.x86.avx512.mask.pcmpgt.q.256" => "__builtin_ia32_pcmpgtq256_mask", - "llvm.x86.avx512.mask.pcmpgt.q.512" => "__builtin_ia32_pcmpgtq512_mask", - "llvm.x86.avx512.mask.pcmpgt.w.128" => "__builtin_ia32_pcmpgtw128_mask", - "llvm.x86.avx512.mask.pcmpgt.w.256" => "__builtin_ia32_pcmpgtw256_mask", - "llvm.x86.avx512.mask.pcmpgt.w.512" => "__builtin_ia32_pcmpgtw512_mask", - "llvm.x86.avx512.mask.permvar.df.256" => "__builtin_ia32_permvardf256_mask", - "llvm.x86.avx512.mask.permvar.df.512" => "__builtin_ia32_permvardf512_mask", - "llvm.x86.avx512.mask.permvar.di.256" => "__builtin_ia32_permvardi256_mask", - "llvm.x86.avx512.mask.permvar.di.512" => "__builtin_ia32_permvardi512_mask", - "llvm.x86.avx512.mask.permvar.hi.128" => "__builtin_ia32_permvarhi128_mask", - "llvm.x86.avx512.mask.permvar.hi.256" => "__builtin_ia32_permvarhi256_mask", - "llvm.x86.avx512.mask.permvar.hi.512" => "__builtin_ia32_permvarhi512_mask", - "llvm.x86.avx512.mask.permvar.qi.128" => "__builtin_ia32_permvarqi128_mask", - "llvm.x86.avx512.mask.permvar.qi.256" => "__builtin_ia32_permvarqi256_mask", - "llvm.x86.avx512.mask.permvar.qi.512" => "__builtin_ia32_permvarqi512_mask", - "llvm.x86.avx512.mask.permvar.sf.256" => "__builtin_ia32_permvarsf256_mask", - "llvm.x86.avx512.mask.permvar.sf.512" => "__builtin_ia32_permvarsf512_mask", - "llvm.x86.avx512.mask.permvar.si.256" => "__builtin_ia32_permvarsi256_mask", - "llvm.x86.avx512.mask.permvar.si.512" => "__builtin_ia32_permvarsi512_mask", - "llvm.x86.avx512.mask.pmaddubs.w.128" => "__builtin_ia32_pmaddubsw128_mask", - "llvm.x86.avx512.mask.pmaddubs.w.256" => "__builtin_ia32_pmaddubsw256_mask", - "llvm.x86.avx512.mask.pmaddubs.w.512" => "__builtin_ia32_pmaddubsw512_mask", - "llvm.x86.avx512.mask.pmaddw.d.128" => "__builtin_ia32_pmaddwd128_mask", - "llvm.x86.avx512.mask.pmaddw.d.256" => "__builtin_ia32_pmaddwd256_mask", - "llvm.x86.avx512.mask.pmaddw.d.512" => "__builtin_ia32_pmaddwd512_mask", - "llvm.x86.avx512.mask.pmaxs.b.128" => "__builtin_ia32_pmaxsb128_mask", - "llvm.x86.avx512.mask.pmaxs.b.256" => "__builtin_ia32_pmaxsb256_mask", - "llvm.x86.avx512.mask.pmaxs.b.512" => "__builtin_ia32_pmaxsb512_mask", - "llvm.x86.avx512.mask.pmaxs.d.128" => "__builtin_ia32_pmaxsd128_mask", - "llvm.x86.avx512.mask.pmaxs.d.256" => "__builtin_ia32_pmaxsd256_mask", - "llvm.x86.avx512.mask.pmaxs.d.512" => "__builtin_ia32_pmaxsd512_mask", - "llvm.x86.avx512.mask.pmaxs.q.128" => "__builtin_ia32_pmaxsq128_mask", - "llvm.x86.avx512.mask.pmaxs.q.256" => "__builtin_ia32_pmaxsq256_mask", - "llvm.x86.avx512.mask.pmaxs.q.512" => "__builtin_ia32_pmaxsq512_mask", - "llvm.x86.avx512.mask.pmaxs.w.128" => "__builtin_ia32_pmaxsw128_mask", - "llvm.x86.avx512.mask.pmaxs.w.256" => "__builtin_ia32_pmaxsw256_mask", - "llvm.x86.avx512.mask.pmaxs.w.512" => "__builtin_ia32_pmaxsw512_mask", - "llvm.x86.avx512.mask.pmaxu.b.128" => "__builtin_ia32_pmaxub128_mask", - "llvm.x86.avx512.mask.pmaxu.b.256" => "__builtin_ia32_pmaxub256_mask", - "llvm.x86.avx512.mask.pmaxu.b.512" => "__builtin_ia32_pmaxub512_mask", - "llvm.x86.avx512.mask.pmaxu.d.128" => "__builtin_ia32_pmaxud128_mask", - "llvm.x86.avx512.mask.pmaxu.d.256" => "__builtin_ia32_pmaxud256_mask", - "llvm.x86.avx512.mask.pmaxu.d.512" => "__builtin_ia32_pmaxud512_mask", - "llvm.x86.avx512.mask.pmaxu.q.128" => "__builtin_ia32_pmaxuq128_mask", - "llvm.x86.avx512.mask.pmaxu.q.256" => "__builtin_ia32_pmaxuq256_mask", - "llvm.x86.avx512.mask.pmaxu.q.512" => "__builtin_ia32_pmaxuq512_mask", - "llvm.x86.avx512.mask.pmaxu.w.128" => "__builtin_ia32_pmaxuw128_mask", - "llvm.x86.avx512.mask.pmaxu.w.256" => "__builtin_ia32_pmaxuw256_mask", - "llvm.x86.avx512.mask.pmaxu.w.512" => "__builtin_ia32_pmaxuw512_mask", - "llvm.x86.avx512.mask.pmins.b.128" => "__builtin_ia32_pminsb128_mask", - "llvm.x86.avx512.mask.pmins.b.256" => "__builtin_ia32_pminsb256_mask", - "llvm.x86.avx512.mask.pmins.b.512" => "__builtin_ia32_pminsb512_mask", - "llvm.x86.avx512.mask.pmins.d.128" => "__builtin_ia32_pminsd128_mask", - "llvm.x86.avx512.mask.pmins.d.256" => "__builtin_ia32_pminsd256_mask", - "llvm.x86.avx512.mask.pmins.d.512" => "__builtin_ia32_pminsd512_mask", - "llvm.x86.avx512.mask.pmins.q.128" => "__builtin_ia32_pminsq128_mask", - "llvm.x86.avx512.mask.pmins.q.256" => "__builtin_ia32_pminsq256_mask", - "llvm.x86.avx512.mask.pmins.q.512" => "__builtin_ia32_pminsq512_mask", - "llvm.x86.avx512.mask.pmins.w.128" => "__builtin_ia32_pminsw128_mask", - "llvm.x86.avx512.mask.pmins.w.256" => "__builtin_ia32_pminsw256_mask", - "llvm.x86.avx512.mask.pmins.w.512" => "__builtin_ia32_pminsw512_mask", - "llvm.x86.avx512.mask.pminu.b.128" => "__builtin_ia32_pminub128_mask", - "llvm.x86.avx512.mask.pminu.b.256" => "__builtin_ia32_pminub256_mask", - "llvm.x86.avx512.mask.pminu.b.512" => "__builtin_ia32_pminub512_mask", - "llvm.x86.avx512.mask.pminu.d.128" => "__builtin_ia32_pminud128_mask", - "llvm.x86.avx512.mask.pminu.d.256" => "__builtin_ia32_pminud256_mask", - "llvm.x86.avx512.mask.pminu.d.512" => "__builtin_ia32_pminud512_mask", - "llvm.x86.avx512.mask.pminu.q.128" => "__builtin_ia32_pminuq128_mask", - "llvm.x86.avx512.mask.pminu.q.256" => "__builtin_ia32_pminuq256_mask", - "llvm.x86.avx512.mask.pminu.q.512" => "__builtin_ia32_pminuq512_mask", - "llvm.x86.avx512.mask.pminu.w.128" => "__builtin_ia32_pminuw128_mask", - "llvm.x86.avx512.mask.pminu.w.256" => "__builtin_ia32_pminuw256_mask", - "llvm.x86.avx512.mask.pminu.w.512" => "__builtin_ia32_pminuw512_mask", "llvm.x86.avx512.mask.pmov.db.128" => "__builtin_ia32_pmovdb128_mask", "llvm.x86.avx512.mask.pmov.db.256" => "__builtin_ia32_pmovdb256_mask", - "llvm.x86.avx512.mask.pmov.db.512" => "__builtin_ia32_pmovdb512_mask", "llvm.x86.avx512.mask.pmov.db.mem.128" => "__builtin_ia32_pmovdb128mem_mask", "llvm.x86.avx512.mask.pmov.db.mem.256" => "__builtin_ia32_pmovdb256mem_mask", "llvm.x86.avx512.mask.pmov.db.mem.512" => "__builtin_ia32_pmovdb512mem_mask", "llvm.x86.avx512.mask.pmov.dw.128" => "__builtin_ia32_pmovdw128_mask", "llvm.x86.avx512.mask.pmov.dw.256" => "__builtin_ia32_pmovdw256_mask", - "llvm.x86.avx512.mask.pmov.dw.512" => "__builtin_ia32_pmovdw512_mask", "llvm.x86.avx512.mask.pmov.dw.mem.128" => "__builtin_ia32_pmovdw128mem_mask", "llvm.x86.avx512.mask.pmov.dw.mem.256" => "__builtin_ia32_pmovdw256mem_mask", "llvm.x86.avx512.mask.pmov.dw.mem.512" => "__builtin_ia32_pmovdw512mem_mask", @@ -8257,20 +7266,15 @@ match name { "llvm.x86.avx512.mask.pmov.qb.mem.256" => "__builtin_ia32_pmovqb256mem_mask", "llvm.x86.avx512.mask.pmov.qb.mem.512" => "__builtin_ia32_pmovqb512mem_mask", "llvm.x86.avx512.mask.pmov.qd.128" => "__builtin_ia32_pmovqd128_mask", - "llvm.x86.avx512.mask.pmov.qd.256" => "__builtin_ia32_pmovqd256_mask", - "llvm.x86.avx512.mask.pmov.qd.512" => "__builtin_ia32_pmovqd512_mask", "llvm.x86.avx512.mask.pmov.qd.mem.128" => "__builtin_ia32_pmovqd128mem_mask", "llvm.x86.avx512.mask.pmov.qd.mem.256" => "__builtin_ia32_pmovqd256mem_mask", "llvm.x86.avx512.mask.pmov.qd.mem.512" => "__builtin_ia32_pmovqd512mem_mask", "llvm.x86.avx512.mask.pmov.qw.128" => "__builtin_ia32_pmovqw128_mask", "llvm.x86.avx512.mask.pmov.qw.256" => "__builtin_ia32_pmovqw256_mask", - "llvm.x86.avx512.mask.pmov.qw.512" => "__builtin_ia32_pmovqw512_mask", "llvm.x86.avx512.mask.pmov.qw.mem.128" => "__builtin_ia32_pmovqw128mem_mask", "llvm.x86.avx512.mask.pmov.qw.mem.256" => "__builtin_ia32_pmovqw256mem_mask", "llvm.x86.avx512.mask.pmov.qw.mem.512" => "__builtin_ia32_pmovqw512mem_mask", "llvm.x86.avx512.mask.pmov.wb.128" => "__builtin_ia32_pmovwb128_mask", - "llvm.x86.avx512.mask.pmov.wb.256" => "__builtin_ia32_pmovwb256_mask", - "llvm.x86.avx512.mask.pmov.wb.512" => "__builtin_ia32_pmovwb512_mask", "llvm.x86.avx512.mask.pmov.wb.mem.128" => "__builtin_ia32_pmovwb128mem_mask", "llvm.x86.avx512.mask.pmov.wb.mem.256" => "__builtin_ia32_pmovwb256mem_mask", "llvm.x86.avx512.mask.pmov.wb.mem.512" => "__builtin_ia32_pmovwb512mem_mask", @@ -8310,24 +7314,6 @@ match name { "llvm.x86.avx512.mask.pmovs.wb.mem.128" => "__builtin_ia32_pmovswb128mem_mask", "llvm.x86.avx512.mask.pmovs.wb.mem.256" => "__builtin_ia32_pmovswb256mem_mask", "llvm.x86.avx512.mask.pmovs.wb.mem.512" => "__builtin_ia32_pmovswb512mem_mask", - "llvm.x86.avx512.mask.pmovsxb.d.128" => "__builtin_ia32_pmovsxbd128_mask", - "llvm.x86.avx512.mask.pmovsxb.d.256" => "__builtin_ia32_pmovsxbd256_mask", - "llvm.x86.avx512.mask.pmovsxb.d.512" => "__builtin_ia32_pmovsxbd512_mask", - "llvm.x86.avx512.mask.pmovsxb.q.128" => "__builtin_ia32_pmovsxbq128_mask", - "llvm.x86.avx512.mask.pmovsxb.q.256" => "__builtin_ia32_pmovsxbq256_mask", - "llvm.x86.avx512.mask.pmovsxb.q.512" => "__builtin_ia32_pmovsxbq512_mask", - "llvm.x86.avx512.mask.pmovsxb.w.128" => "__builtin_ia32_pmovsxbw128_mask", - "llvm.x86.avx512.mask.pmovsxb.w.256" => "__builtin_ia32_pmovsxbw256_mask", - "llvm.x86.avx512.mask.pmovsxb.w.512" => "__builtin_ia32_pmovsxbw512_mask", - "llvm.x86.avx512.mask.pmovsxd.q.128" => "__builtin_ia32_pmovsxdq128_mask", - "llvm.x86.avx512.mask.pmovsxd.q.256" => "__builtin_ia32_pmovsxdq256_mask", - "llvm.x86.avx512.mask.pmovsxd.q.512" => "__builtin_ia32_pmovsxdq512_mask", - "llvm.x86.avx512.mask.pmovsxw.d.128" => "__builtin_ia32_pmovsxwd128_mask", - "llvm.x86.avx512.mask.pmovsxw.d.256" => "__builtin_ia32_pmovsxwd256_mask", - "llvm.x86.avx512.mask.pmovsxw.d.512" => "__builtin_ia32_pmovsxwd512_mask", - "llvm.x86.avx512.mask.pmovsxw.q.128" => "__builtin_ia32_pmovsxwq128_mask", - "llvm.x86.avx512.mask.pmovsxw.q.256" => "__builtin_ia32_pmovsxwq256_mask", - "llvm.x86.avx512.mask.pmovsxw.q.512" => "__builtin_ia32_pmovsxwq512_mask", "llvm.x86.avx512.mask.pmovus.db.128" => "__builtin_ia32_pmovusdb128_mask", "llvm.x86.avx512.mask.pmovus.db.256" => "__builtin_ia32_pmovusdb256_mask", "llvm.x86.avx512.mask.pmovus.db.512" => "__builtin_ia32_pmovusdb512_mask", @@ -8364,191 +7350,6 @@ match name { "llvm.x86.avx512.mask.pmovus.wb.mem.128" => "__builtin_ia32_pmovuswb128mem_mask", "llvm.x86.avx512.mask.pmovus.wb.mem.256" => "__builtin_ia32_pmovuswb256mem_mask", "llvm.x86.avx512.mask.pmovus.wb.mem.512" => "__builtin_ia32_pmovuswb512mem_mask", - "llvm.x86.avx512.mask.pmovzxb.d.128" => "__builtin_ia32_pmovzxbd128_mask", - "llvm.x86.avx512.mask.pmovzxb.d.256" => "__builtin_ia32_pmovzxbd256_mask", - "llvm.x86.avx512.mask.pmovzxb.d.512" => "__builtin_ia32_pmovzxbd512_mask", - "llvm.x86.avx512.mask.pmovzxb.q.128" => "__builtin_ia32_pmovzxbq128_mask", - "llvm.x86.avx512.mask.pmovzxb.q.256" => "__builtin_ia32_pmovzxbq256_mask", - "llvm.x86.avx512.mask.pmovzxb.q.512" => "__builtin_ia32_pmovzxbq512_mask", - "llvm.x86.avx512.mask.pmovzxb.w.128" => "__builtin_ia32_pmovzxbw128_mask", - "llvm.x86.avx512.mask.pmovzxb.w.256" => "__builtin_ia32_pmovzxbw256_mask", - "llvm.x86.avx512.mask.pmovzxb.w.512" => "__builtin_ia32_pmovzxbw512_mask", - "llvm.x86.avx512.mask.pmovzxd.q.128" => "__builtin_ia32_pmovzxdq128_mask", - "llvm.x86.avx512.mask.pmovzxd.q.256" => "__builtin_ia32_pmovzxdq256_mask", - "llvm.x86.avx512.mask.pmovzxd.q.512" => "__builtin_ia32_pmovzxdq512_mask", - "llvm.x86.avx512.mask.pmovzxw.d.128" => "__builtin_ia32_pmovzxwd128_mask", - "llvm.x86.avx512.mask.pmovzxw.d.256" => "__builtin_ia32_pmovzxwd256_mask", - "llvm.x86.avx512.mask.pmovzxw.d.512" => "__builtin_ia32_pmovzxwd512_mask", - "llvm.x86.avx512.mask.pmovzxw.q.128" => "__builtin_ia32_pmovzxwq128_mask", - "llvm.x86.avx512.mask.pmovzxw.q.256" => "__builtin_ia32_pmovzxwq256_mask", - "llvm.x86.avx512.mask.pmovzxw.q.512" => "__builtin_ia32_pmovzxwq512_mask", - "llvm.x86.avx512.mask.pmul.dq.128" => "__builtin_ia32_pmuldq128_mask", - "llvm.x86.avx512.mask.pmul.dq.256" => "__builtin_ia32_pmuldq256_mask", - "llvm.x86.avx512.mask.pmul.dq.512" => "__builtin_ia32_pmuldq512_mask", - "llvm.x86.avx512.mask.pmul.hr.sw.128" => "__builtin_ia32_pmulhrsw128_mask", - "llvm.x86.avx512.mask.pmul.hr.sw.256" => "__builtin_ia32_pmulhrsw256_mask", - "llvm.x86.avx512.mask.pmul.hr.sw.512" => "__builtin_ia32_pmulhrsw512_mask", - "llvm.x86.avx512.mask.pmulh.w.128" => "__builtin_ia32_pmulhw128_mask", - "llvm.x86.avx512.mask.pmulh.w.256" => "__builtin_ia32_pmulhw256_mask", - "llvm.x86.avx512.mask.pmulh.w.512" => "__builtin_ia32_pmulhw512_mask", - "llvm.x86.avx512.mask.pmulhu.w.128" => "__builtin_ia32_pmulhuw128_mask", - "llvm.x86.avx512.mask.pmulhu.w.256" => "__builtin_ia32_pmulhuw256_mask", - "llvm.x86.avx512.mask.pmulhu.w.512" => "__builtin_ia32_pmulhuw512_mask", - "llvm.x86.avx512.mask.pmull.d.128" => "__builtin_ia32_pmulld128_mask", - "llvm.x86.avx512.mask.pmull.d.256" => "__builtin_ia32_pmulld256_mask", - "llvm.x86.avx512.mask.pmull.d.512" => "__builtin_ia32_pmulld512_mask", - "llvm.x86.avx512.mask.pmull.q.128" => "__builtin_ia32_pmullq128_mask", - "llvm.x86.avx512.mask.pmull.q.256" => "__builtin_ia32_pmullq256_mask", - "llvm.x86.avx512.mask.pmull.q.512" => "__builtin_ia32_pmullq512_mask", - "llvm.x86.avx512.mask.pmull.w.128" => "__builtin_ia32_pmullw128_mask", - "llvm.x86.avx512.mask.pmull.w.256" => "__builtin_ia32_pmullw256_mask", - "llvm.x86.avx512.mask.pmull.w.512" => "__builtin_ia32_pmullw512_mask", - "llvm.x86.avx512.mask.pmultishift.qb.128" => "__builtin_ia32_vpmultishiftqb128_mask", - "llvm.x86.avx512.mask.pmultishift.qb.256" => "__builtin_ia32_vpmultishiftqb256_mask", - "llvm.x86.avx512.mask.pmultishift.qb.512" => "__builtin_ia32_vpmultishiftqb512_mask", - "llvm.x86.avx512.mask.pmulu.dq.128" => "__builtin_ia32_pmuludq128_mask", - "llvm.x86.avx512.mask.pmulu.dq.256" => "__builtin_ia32_pmuludq256_mask", - "llvm.x86.avx512.mask.pmulu.dq.512" => "__builtin_ia32_pmuludq512_mask", - "llvm.x86.avx512.mask.prol.d.128" => "__builtin_ia32_prold128_mask", - "llvm.x86.avx512.mask.prol.d.256" => "__builtin_ia32_prold256_mask", - "llvm.x86.avx512.mask.prol.d.512" => "__builtin_ia32_prold512_mask", - "llvm.x86.avx512.mask.prol.q.128" => "__builtin_ia32_prolq128_mask", - "llvm.x86.avx512.mask.prol.q.256" => "__builtin_ia32_prolq256_mask", - "llvm.x86.avx512.mask.prol.q.512" => "__builtin_ia32_prolq512_mask", - "llvm.x86.avx512.mask.prolv.d.128" => "__builtin_ia32_prolvd128_mask", - "llvm.x86.avx512.mask.prolv.d.256" => "__builtin_ia32_prolvd256_mask", - "llvm.x86.avx512.mask.prolv.d.512" => "__builtin_ia32_prolvd512_mask", - "llvm.x86.avx512.mask.prolv.q.128" => "__builtin_ia32_prolvq128_mask", - "llvm.x86.avx512.mask.prolv.q.256" => "__builtin_ia32_prolvq256_mask", - "llvm.x86.avx512.mask.prolv.q.512" => "__builtin_ia32_prolvq512_mask", - "llvm.x86.avx512.mask.pror.d.128" => "__builtin_ia32_prord128_mask", - "llvm.x86.avx512.mask.pror.d.256" => "__builtin_ia32_prord256_mask", - "llvm.x86.avx512.mask.pror.d.512" => "__builtin_ia32_prord512_mask", - "llvm.x86.avx512.mask.pror.q.128" => "__builtin_ia32_prorq128_mask", - "llvm.x86.avx512.mask.pror.q.256" => "__builtin_ia32_prorq256_mask", - "llvm.x86.avx512.mask.pror.q.512" => "__builtin_ia32_prorq512_mask", - "llvm.x86.avx512.mask.prorv.d.128" => "__builtin_ia32_prorvd128_mask", - "llvm.x86.avx512.mask.prorv.d.256" => "__builtin_ia32_prorvd256_mask", - "llvm.x86.avx512.mask.prorv.d.512" => "__builtin_ia32_prorvd512_mask", - "llvm.x86.avx512.mask.prorv.q.128" => "__builtin_ia32_prorvq128_mask", - "llvm.x86.avx512.mask.prorv.q.256" => "__builtin_ia32_prorvq256_mask", - "llvm.x86.avx512.mask.prorv.q.512" => "__builtin_ia32_prorvq512_mask", - "llvm.x86.avx512.mask.pshuf.b.128" => "__builtin_ia32_pshufb128_mask", - "llvm.x86.avx512.mask.pshuf.b.256" => "__builtin_ia32_pshufb256_mask", - "llvm.x86.avx512.mask.pshuf.b.512" => "__builtin_ia32_pshufb512_mask", - "llvm.x86.avx512.mask.psll.d" => "__builtin_ia32_pslld512_mask", - "llvm.x86.avx512.mask.psll.d.128" => "__builtin_ia32_pslld128_mask", - "llvm.x86.avx512.mask.psll.d.256" => "__builtin_ia32_pslld256_mask", - "llvm.x86.avx512.mask.psll.di.128" => "__builtin_ia32_pslldi128_mask", - "llvm.x86.avx512.mask.psll.di.256" => "__builtin_ia32_pslldi256_mask", - "llvm.x86.avx512.mask.psll.di.512" => "__builtin_ia32_pslldi512_mask", - "llvm.x86.avx512.mask.psll.q" => "__builtin_ia32_psllq512_mask", - "llvm.x86.avx512.mask.psll.q.128" => "__builtin_ia32_psllq128_mask", - "llvm.x86.avx512.mask.psll.q.256" => "__builtin_ia32_psllq256_mask", - "llvm.x86.avx512.mask.psll.qi.128" => "__builtin_ia32_psllqi128_mask", - "llvm.x86.avx512.mask.psll.qi.256" => "__builtin_ia32_psllqi256_mask", - "llvm.x86.avx512.mask.psll.qi.512" => "__builtin_ia32_psllqi512_mask", - "llvm.x86.avx512.mask.psll.w.128" => "__builtin_ia32_psllw128_mask", - "llvm.x86.avx512.mask.psll.w.256" => "__builtin_ia32_psllw256_mask", - "llvm.x86.avx512.mask.psll.w.512" => "__builtin_ia32_psllw512_mask", - "llvm.x86.avx512.mask.psll.wi.128" => "__builtin_ia32_psllwi128_mask", - "llvm.x86.avx512.mask.psll.wi.256" => "__builtin_ia32_psllwi256_mask", - "llvm.x86.avx512.mask.psll.wi.512" => "__builtin_ia32_psllwi512_mask", - "llvm.x86.avx512.mask.psllv.d" => "__builtin_ia32_psllv16si_mask", - "llvm.x86.avx512.mask.psllv.q" => "__builtin_ia32_psllv8di_mask", - "llvm.x86.avx512.mask.psllv16.hi" => "__builtin_ia32_psllv16hi_mask", - "llvm.x86.avx512.mask.psllv2.di" => "__builtin_ia32_psllv2di_mask", - "llvm.x86.avx512.mask.psllv32hi" => "__builtin_ia32_psllv32hi_mask", - "llvm.x86.avx512.mask.psllv4.di" => "__builtin_ia32_psllv4di_mask", - "llvm.x86.avx512.mask.psllv4.si" => "__builtin_ia32_psllv4si_mask", - "llvm.x86.avx512.mask.psllv8.hi" => "__builtin_ia32_psllv8hi_mask", - "llvm.x86.avx512.mask.psllv8.si" => "__builtin_ia32_psllv8si_mask", - "llvm.x86.avx512.mask.psra.d" => "__builtin_ia32_psrad512_mask", - "llvm.x86.avx512.mask.psra.d.128" => "__builtin_ia32_psrad128_mask", - "llvm.x86.avx512.mask.psra.d.256" => "__builtin_ia32_psrad256_mask", - "llvm.x86.avx512.mask.psra.di.128" => "__builtin_ia32_psradi128_mask", - "llvm.x86.avx512.mask.psra.di.256" => "__builtin_ia32_psradi256_mask", - "llvm.x86.avx512.mask.psra.di.512" => "__builtin_ia32_psradi512_mask", - "llvm.x86.avx512.mask.psra.q" => "__builtin_ia32_psraq512_mask", - "llvm.x86.avx512.mask.psra.q.128" => "__builtin_ia32_psraq128_mask", - "llvm.x86.avx512.mask.psra.q.256" => "__builtin_ia32_psraq256_mask", - "llvm.x86.avx512.mask.psra.qi.128" => "__builtin_ia32_psraqi128_mask", - "llvm.x86.avx512.mask.psra.qi.256" => "__builtin_ia32_psraqi256_mask", - "llvm.x86.avx512.mask.psra.qi.512" => "__builtin_ia32_psraqi512_mask", - "llvm.x86.avx512.mask.psra.w.128" => "__builtin_ia32_psraw128_mask", - "llvm.x86.avx512.mask.psra.w.256" => "__builtin_ia32_psraw256_mask", - "llvm.x86.avx512.mask.psra.w.512" => "__builtin_ia32_psraw512_mask", - "llvm.x86.avx512.mask.psra.wi.128" => "__builtin_ia32_psrawi128_mask", - "llvm.x86.avx512.mask.psra.wi.256" => "__builtin_ia32_psrawi256_mask", - "llvm.x86.avx512.mask.psra.wi.512" => "__builtin_ia32_psrawi512_mask", - "llvm.x86.avx512.mask.psrav.d" => "__builtin_ia32_psrav16si_mask", - "llvm.x86.avx512.mask.psrav.q" => "__builtin_ia32_psrav8di_mask", - "llvm.x86.avx512.mask.psrav.q.128" => "__builtin_ia32_psravq128_mask", - "llvm.x86.avx512.mask.psrav.q.256" => "__builtin_ia32_psravq256_mask", - "llvm.x86.avx512.mask.psrav16.hi" => "__builtin_ia32_psrav16hi_mask", - "llvm.x86.avx512.mask.psrav32.hi" => "__builtin_ia32_psrav32hi_mask", - "llvm.x86.avx512.mask.psrav4.si" => "__builtin_ia32_psrav4si_mask", - "llvm.x86.avx512.mask.psrav8.hi" => "__builtin_ia32_psrav8hi_mask", - "llvm.x86.avx512.mask.psrav8.si" => "__builtin_ia32_psrav8si_mask", - "llvm.x86.avx512.mask.psrl.d" => "__builtin_ia32_psrld512_mask", - "llvm.x86.avx512.mask.psrl.d.128" => "__builtin_ia32_psrld128_mask", - "llvm.x86.avx512.mask.psrl.d.256" => "__builtin_ia32_psrld256_mask", - "llvm.x86.avx512.mask.psrl.di.128" => "__builtin_ia32_psrldi128_mask", - "llvm.x86.avx512.mask.psrl.di.256" => "__builtin_ia32_psrldi256_mask", - "llvm.x86.avx512.mask.psrl.di.512" => "__builtin_ia32_psrldi512_mask", - "llvm.x86.avx512.mask.psrl.q" => "__builtin_ia32_psrlq512_mask", - "llvm.x86.avx512.mask.psrl.q.128" => "__builtin_ia32_psrlq128_mask", - "llvm.x86.avx512.mask.psrl.q.256" => "__builtin_ia32_psrlq256_mask", - "llvm.x86.avx512.mask.psrl.qi.128" => "__builtin_ia32_psrlqi128_mask", - "llvm.x86.avx512.mask.psrl.qi.256" => "__builtin_ia32_psrlqi256_mask", - "llvm.x86.avx512.mask.psrl.qi.512" => "__builtin_ia32_psrlqi512_mask", - "llvm.x86.avx512.mask.psrl.w.128" => "__builtin_ia32_psrlw128_mask", - "llvm.x86.avx512.mask.psrl.w.256" => "__builtin_ia32_psrlw256_mask", - "llvm.x86.avx512.mask.psrl.w.512" => "__builtin_ia32_psrlw512_mask", - "llvm.x86.avx512.mask.psrl.wi.128" => "__builtin_ia32_psrlwi128_mask", - "llvm.x86.avx512.mask.psrl.wi.256" => "__builtin_ia32_psrlwi256_mask", - "llvm.x86.avx512.mask.psrl.wi.512" => "__builtin_ia32_psrlwi512_mask", - "llvm.x86.avx512.mask.psrlv.d" => "__builtin_ia32_psrlv16si_mask", - "llvm.x86.avx512.mask.psrlv.q" => "__builtin_ia32_psrlv8di_mask", - "llvm.x86.avx512.mask.psrlv16.hi" => "__builtin_ia32_psrlv16hi_mask", - "llvm.x86.avx512.mask.psrlv2.di" => "__builtin_ia32_psrlv2di_mask", - "llvm.x86.avx512.mask.psrlv32hi" => "__builtin_ia32_psrlv32hi_mask", - "llvm.x86.avx512.mask.psrlv4.di" => "__builtin_ia32_psrlv4di_mask", - "llvm.x86.avx512.mask.psrlv4.si" => "__builtin_ia32_psrlv4si_mask", - "llvm.x86.avx512.mask.psrlv8.hi" => "__builtin_ia32_psrlv8hi_mask", - "llvm.x86.avx512.mask.psrlv8.si" => "__builtin_ia32_psrlv8si_mask", - "llvm.x86.avx512.mask.psub.b.128" => "__builtin_ia32_psubb128_mask", - "llvm.x86.avx512.mask.psub.b.256" => "__builtin_ia32_psubb256_mask", - "llvm.x86.avx512.mask.psub.b.512" => "__builtin_ia32_psubb512_mask", - "llvm.x86.avx512.mask.psub.d.128" => "__builtin_ia32_psubd128_mask", - "llvm.x86.avx512.mask.psub.d.256" => "__builtin_ia32_psubd256_mask", - "llvm.x86.avx512.mask.psub.d.512" => "__builtin_ia32_psubd512_mask", - "llvm.x86.avx512.mask.psub.q.128" => "__builtin_ia32_psubq128_mask", - "llvm.x86.avx512.mask.psub.q.256" => "__builtin_ia32_psubq256_mask", - "llvm.x86.avx512.mask.psub.q.512" => "__builtin_ia32_psubq512_mask", - "llvm.x86.avx512.mask.psub.w.128" => "__builtin_ia32_psubw128_mask", - "llvm.x86.avx512.mask.psub.w.256" => "__builtin_ia32_psubw256_mask", - "llvm.x86.avx512.mask.psub.w.512" => "__builtin_ia32_psubw512_mask", - "llvm.x86.avx512.mask.psubs.b.128" => "__builtin_ia32_psubsb128_mask", - "llvm.x86.avx512.mask.psubs.b.256" => "__builtin_ia32_psubsb256_mask", - "llvm.x86.avx512.mask.psubs.b.512" => "__builtin_ia32_psubsb512_mask", - "llvm.x86.avx512.mask.psubs.w.128" => "__builtin_ia32_psubsw128_mask", - "llvm.x86.avx512.mask.psubs.w.256" => "__builtin_ia32_psubsw256_mask", - "llvm.x86.avx512.mask.psubs.w.512" => "__builtin_ia32_psubsw512_mask", - "llvm.x86.avx512.mask.psubus.b.128" => "__builtin_ia32_psubusb128_mask", - "llvm.x86.avx512.mask.psubus.b.256" => "__builtin_ia32_psubusb256_mask", - "llvm.x86.avx512.mask.psubus.b.512" => "__builtin_ia32_psubusb512_mask", - "llvm.x86.avx512.mask.psubus.w.128" => "__builtin_ia32_psubusw128_mask", - "llvm.x86.avx512.mask.psubus.w.256" => "__builtin_ia32_psubusw256_mask", - "llvm.x86.avx512.mask.psubus.w.512" => "__builtin_ia32_psubusw512_mask", - "llvm.x86.avx512.mask.pternlog.d.128" => "__builtin_ia32_pternlogd128_mask", - "llvm.x86.avx512.mask.pternlog.d.256" => "__builtin_ia32_pternlogd256_mask", - "llvm.x86.avx512.mask.pternlog.d.512" => "__builtin_ia32_pternlogd512_mask", - "llvm.x86.avx512.mask.pternlog.q.128" => "__builtin_ia32_pternlogq128_mask", - "llvm.x86.avx512.mask.pternlog.q.256" => "__builtin_ia32_pternlogq256_mask", - "llvm.x86.avx512.mask.pternlog.q.512" => "__builtin_ia32_pternlogq512_mask", - "llvm.x86.avx512.mask.ptestm.d.512" => "__builtin_ia32_ptestmd512", - "llvm.x86.avx512.mask.ptestm.q.512" => "__builtin_ia32_ptestmq512", "llvm.x86.avx512.mask.range.pd.128" => "__builtin_ia32_rangepd128_mask", "llvm.x86.avx512.mask.range.pd.256" => "__builtin_ia32_rangepd256_mask", "llvm.x86.avx512.mask.range.pd.512" => "__builtin_ia32_rangepd512_mask", @@ -8581,181 +7382,11 @@ match name { "llvm.x86.avx512.mask.scalef.ps.512" => "__builtin_ia32_scalefps512_mask", // [INVALID CONVERSION]: "llvm.x86.avx512.mask.scalef.sd" => "__builtin_ia32_scalefsd_round_mask", // [INVALID CONVERSION]: "llvm.x86.avx512.mask.scalef.ss" => "__builtin_ia32_scalefss_round_mask", - "llvm.x86.avx512.mask.shuf.f32x4" => "__builtin_ia32_shuf_f32x4_mask", - "llvm.x86.avx512.mask.shuf.f32x4.256" => "__builtin_ia32_shuf_f32x4_256_mask", - "llvm.x86.avx512.mask.shuf.f64x2" => "__builtin_ia32_shuf_f64x2_mask", - "llvm.x86.avx512.mask.shuf.f64x2.256" => "__builtin_ia32_shuf_f64x2_256_mask", - "llvm.x86.avx512.mask.shuf.i32x4" => "__builtin_ia32_shuf_i32x4_mask", - "llvm.x86.avx512.mask.shuf.i32x4.256" => "__builtin_ia32_shuf_i32x4_256_mask", - "llvm.x86.avx512.mask.shuf.i64x2" => "__builtin_ia32_shuf_i64x2_mask", - "llvm.x86.avx512.mask.shuf.i64x2.256" => "__builtin_ia32_shuf_i64x2_256_mask", - "llvm.x86.avx512.mask.shuf.pd.128" => "__builtin_ia32_shufpd128_mask", - "llvm.x86.avx512.mask.shuf.pd.256" => "__builtin_ia32_shufpd256_mask", - "llvm.x86.avx512.mask.shuf.pd.512" => "__builtin_ia32_shufpd512_mask", - "llvm.x86.avx512.mask.shuf.ps.128" => "__builtin_ia32_shufps128_mask", - "llvm.x86.avx512.mask.shuf.ps.256" => "__builtin_ia32_shufps256_mask", - "llvm.x86.avx512.mask.shuf.ps.512" => "__builtin_ia32_shufps512_mask", - "llvm.x86.avx512.mask.sqrt.pd.128" => "__builtin_ia32_sqrtpd128_mask", - "llvm.x86.avx512.mask.sqrt.pd.256" => "__builtin_ia32_sqrtpd256_mask", - "llvm.x86.avx512.mask.sqrt.pd.512" => "__builtin_ia32_sqrtpd512_mask", - "llvm.x86.avx512.mask.sqrt.ps.128" => "__builtin_ia32_sqrtps128_mask", - "llvm.x86.avx512.mask.sqrt.ps.256" => "__builtin_ia32_sqrtps256_mask", - "llvm.x86.avx512.mask.sqrt.ps.512" => "__builtin_ia32_sqrtps512_mask", - // [INVALID CONVERSION]: "llvm.x86.avx512.mask.sqrt.sd" => "__builtin_ia32_sqrtsd_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx512.mask.sqrt.ss" => "__builtin_ia32_sqrtss_round_mask", - "llvm.x86.avx512.mask.store.ss" => "__builtin_ia32_storess_mask", - "llvm.x86.avx512.mask.storeu.d.512" => "__builtin_ia32_storedqusi512_mask", - "llvm.x86.avx512.mask.storeu.pd.512" => "__builtin_ia32_storeupd512_mask", - "llvm.x86.avx512.mask.storeu.ps.512" => "__builtin_ia32_storeups512_mask", - "llvm.x86.avx512.mask.storeu.q.512" => "__builtin_ia32_storedqudi512_mask", - "llvm.x86.avx512.mask.sub.pd.128" => "__builtin_ia32_subpd128_mask", - "llvm.x86.avx512.mask.sub.pd.256" => "__builtin_ia32_subpd256_mask", - "llvm.x86.avx512.mask.sub.pd.512" => "__builtin_ia32_subpd512_mask", - "llvm.x86.avx512.mask.sub.ps.128" => "__builtin_ia32_subps128_mask", - "llvm.x86.avx512.mask.sub.ps.256" => "__builtin_ia32_subps256_mask", - "llvm.x86.avx512.mask.sub.ps.512" => "__builtin_ia32_subps512_mask", // [INVALID CONVERSION]: "llvm.x86.avx512.mask.sub.sd.round" => "__builtin_ia32_subsd_round_mask", // [INVALID CONVERSION]: "llvm.x86.avx512.mask.sub.ss.round" => "__builtin_ia32_subss_round_mask", - "llvm.x86.avx512.mask.valign.d.128" => "__builtin_ia32_alignd128_mask", - "llvm.x86.avx512.mask.valign.d.256" => "__builtin_ia32_alignd256_mask", - "llvm.x86.avx512.mask.valign.d.512" => "__builtin_ia32_alignd512_mask", - "llvm.x86.avx512.mask.valign.q.128" => "__builtin_ia32_alignq128_mask", - "llvm.x86.avx512.mask.valign.q.256" => "__builtin_ia32_alignq256_mask", - "llvm.x86.avx512.mask.valign.q.512" => "__builtin_ia32_alignq512_mask", - "llvm.x86.avx512.mask.vcvtph2ps.128" => "__builtin_ia32_vcvtph2ps_mask", - "llvm.x86.avx512.mask.vcvtph2ps.256" => "__builtin_ia32_vcvtph2ps256_mask", - "llvm.x86.avx512.mask.vcvtph2ps.512" => "__builtin_ia32_vcvtph2ps512_mask", "llvm.x86.avx512.mask.vcvtps2ph.128" => "__builtin_ia32_vcvtps2ph_mask", "llvm.x86.avx512.mask.vcvtps2ph.256" => "__builtin_ia32_vcvtps2ph256_mask", "llvm.x86.avx512.mask.vcvtps2ph.512" => "__builtin_ia32_vcvtps2ph512_mask", - "llvm.x86.avx512.mask.vextractf32x4.256" => "__builtin_ia32_extractf32x4_256_mask", - "llvm.x86.avx512.mask.vextractf32x4.512" => "__builtin_ia32_extractf32x4_mask", - "llvm.x86.avx512.mask.vextractf32x8.512" => "__builtin_ia32_extractf32x8_mask", - "llvm.x86.avx512.mask.vextractf64x2.256" => "__builtin_ia32_extractf64x2_256_mask", - "llvm.x86.avx512.mask.vextractf64x2.512" => "__builtin_ia32_extractf64x2_512_mask", - "llvm.x86.avx512.mask.vextractf64x4.512" => "__builtin_ia32_extractf64x4_mask", - "llvm.x86.avx512.mask.vextracti32x4.256" => "__builtin_ia32_extracti32x4_256_mask", - "llvm.x86.avx512.mask.vextracti32x4.512" => "__builtin_ia32_extracti32x4_mask", - "llvm.x86.avx512.mask.vextracti32x8.512" => "__builtin_ia32_extracti32x8_mask", - "llvm.x86.avx512.mask.vextracti64x2.256" => "__builtin_ia32_extracti64x2_256_mask", - "llvm.x86.avx512.mask.vextracti64x2.512" => "__builtin_ia32_extracti64x2_512_mask", - "llvm.x86.avx512.mask.vextracti64x4.512" => "__builtin_ia32_extracti64x4_mask", - "llvm.x86.avx512.mask.vfmadd.pd.128" => "__builtin_ia32_vfmaddpd128_mask", - "llvm.x86.avx512.mask.vfmadd.pd.256" => "__builtin_ia32_vfmaddpd256_mask", - "llvm.x86.avx512.mask.vfmadd.pd.512" => "__builtin_ia32_vfmaddpd512_mask", - "llvm.x86.avx512.mask.vfmadd.ps.128" => "__builtin_ia32_vfmaddps128_mask", - "llvm.x86.avx512.mask.vfmadd.ps.256" => "__builtin_ia32_vfmaddps256_mask", - "llvm.x86.avx512.mask.vfmadd.ps.512" => "__builtin_ia32_vfmaddps512_mask", - "llvm.x86.avx512.mask.vfmadd.sd" => "__builtin_ia32_vfmaddsd3_mask", - "llvm.x86.avx512.mask.vfmadd.ss" => "__builtin_ia32_vfmaddss3_mask", - "llvm.x86.avx512.mask.vfmaddsub.pd.128" => "__builtin_ia32_vfmaddsubpd128_mask", - "llvm.x86.avx512.mask.vfmaddsub.pd.256" => "__builtin_ia32_vfmaddsubpd256_mask", - "llvm.x86.avx512.mask.vfmaddsub.pd.512" => "__builtin_ia32_vfmaddsubpd512_mask", - "llvm.x86.avx512.mask.vfmaddsub.ps.128" => "__builtin_ia32_vfmaddsubps128_mask", - "llvm.x86.avx512.mask.vfmaddsub.ps.256" => "__builtin_ia32_vfmaddsubps256_mask", - "llvm.x86.avx512.mask.vfmaddsub.ps.512" => "__builtin_ia32_vfmaddsubps512_mask", - "llvm.x86.avx512.mask.vfnmadd.pd.128" => "__builtin_ia32_vfnmaddpd128_mask", - "llvm.x86.avx512.mask.vfnmadd.pd.256" => "__builtin_ia32_vfnmaddpd256_mask", - "llvm.x86.avx512.mask.vfnmadd.pd.512" => "__builtin_ia32_vfnmaddpd512_mask", - "llvm.x86.avx512.mask.vfnmadd.ps.128" => "__builtin_ia32_vfnmaddps128_mask", - "llvm.x86.avx512.mask.vfnmadd.ps.256" => "__builtin_ia32_vfnmaddps256_mask", - "llvm.x86.avx512.mask.vfnmadd.ps.512" => "__builtin_ia32_vfnmaddps512_mask", - "llvm.x86.avx512.mask.vfnmsub.pd.128" => "__builtin_ia32_vfnmsubpd128_mask", - "llvm.x86.avx512.mask.vfnmsub.pd.256" => "__builtin_ia32_vfnmsubpd256_mask", - "llvm.x86.avx512.mask.vfnmsub.pd.512" => "__builtin_ia32_vfnmsubpd512_mask", - "llvm.x86.avx512.mask.vfnmsub.ps.128" => "__builtin_ia32_vfnmsubps128_mask", - "llvm.x86.avx512.mask.vfnmsub.ps.256" => "__builtin_ia32_vfnmsubps256_mask", - "llvm.x86.avx512.mask.vfnmsub.ps.512" => "__builtin_ia32_vfnmsubps512_mask", - "llvm.x86.avx512.mask.vpermi2var.d.128" => "__builtin_ia32_vpermi2vard128_mask", - "llvm.x86.avx512.mask.vpermi2var.d.256" => "__builtin_ia32_vpermi2vard256_mask", - "llvm.x86.avx512.mask.vpermi2var.d.512" => "__builtin_ia32_vpermi2vard512_mask", - "llvm.x86.avx512.mask.vpermi2var.hi.128" => "__builtin_ia32_vpermi2varhi128_mask", - "llvm.x86.avx512.mask.vpermi2var.hi.256" => "__builtin_ia32_vpermi2varhi256_mask", - "llvm.x86.avx512.mask.vpermi2var.hi.512" => "__builtin_ia32_vpermi2varhi512_mask", - "llvm.x86.avx512.mask.vpermi2var.pd.128" => "__builtin_ia32_vpermi2varpd128_mask", - "llvm.x86.avx512.mask.vpermi2var.pd.256" => "__builtin_ia32_vpermi2varpd256_mask", - "llvm.x86.avx512.mask.vpermi2var.pd.512" => "__builtin_ia32_vpermi2varpd512_mask", - "llvm.x86.avx512.mask.vpermi2var.ps.128" => "__builtin_ia32_vpermi2varps128_mask", - "llvm.x86.avx512.mask.vpermi2var.ps.256" => "__builtin_ia32_vpermi2varps256_mask", - "llvm.x86.avx512.mask.vpermi2var.ps.512" => "__builtin_ia32_vpermi2varps512_mask", - "llvm.x86.avx512.mask.vpermi2var.q.128" => "__builtin_ia32_vpermi2varq128_mask", - "llvm.x86.avx512.mask.vpermi2var.q.256" => "__builtin_ia32_vpermi2varq256_mask", - "llvm.x86.avx512.mask.vpermi2var.q.512" => "__builtin_ia32_vpermi2varq512_mask", - "llvm.x86.avx512.mask.vpermi2var.qi.128" => "__builtin_ia32_vpermi2varqi128_mask", - "llvm.x86.avx512.mask.vpermi2var.qi.256" => "__builtin_ia32_vpermi2varqi256_mask", - "llvm.x86.avx512.mask.vpermi2var.qi.512" => "__builtin_ia32_vpermi2varqi512_mask", - "llvm.x86.avx512.mask.vpermilvar.pd.128" => "__builtin_ia32_vpermilvarpd_mask", - "llvm.x86.avx512.mask.vpermilvar.pd.256" => "__builtin_ia32_vpermilvarpd256_mask", - "llvm.x86.avx512.mask.vpermilvar.pd.512" => "__builtin_ia32_vpermilvarpd512_mask", - "llvm.x86.avx512.mask.vpermilvar.ps.128" => "__builtin_ia32_vpermilvarps_mask", - "llvm.x86.avx512.mask.vpermilvar.ps.256" => "__builtin_ia32_vpermilvarps256_mask", - "llvm.x86.avx512.mask.vpermilvar.ps.512" => "__builtin_ia32_vpermilvarps512_mask", - "llvm.x86.avx512.mask.vpermt.d.512" => "__builtin_ia32_vpermt2vard512_mask", - "llvm.x86.avx512.mask.vpermt.pd.512" => "__builtin_ia32_vpermt2varpd512_mask", - "llvm.x86.avx512.mask.vpermt.ps.512" => "__builtin_ia32_vpermt2varps512_mask", - "llvm.x86.avx512.mask.vpermt.q.512" => "__builtin_ia32_vpermt2varq512_mask", - "llvm.x86.avx512.mask.vpermt2var.d.128" => "__builtin_ia32_vpermt2vard128_mask", - "llvm.x86.avx512.mask.vpermt2var.d.256" => "__builtin_ia32_vpermt2vard256_mask", - "llvm.x86.avx512.mask.vpermt2var.d.512" => "__builtin_ia32_vpermt2vard512_mask", - "llvm.x86.avx512.mask.vpermt2var.hi.128" => "__builtin_ia32_vpermt2varhi128_mask", - "llvm.x86.avx512.mask.vpermt2var.hi.256" => "__builtin_ia32_vpermt2varhi256_mask", - "llvm.x86.avx512.mask.vpermt2var.hi.512" => "__builtin_ia32_vpermt2varhi512_mask", - "llvm.x86.avx512.mask.vpermt2var.pd.128" => "__builtin_ia32_vpermt2varpd128_mask", - "llvm.x86.avx512.mask.vpermt2var.pd.256" => "__builtin_ia32_vpermt2varpd256_mask", - "llvm.x86.avx512.mask.vpermt2var.pd.512" => "__builtin_ia32_vpermt2varpd512_mask", - "llvm.x86.avx512.mask.vpermt2var.ps.128" => "__builtin_ia32_vpermt2varps128_mask", - "llvm.x86.avx512.mask.vpermt2var.ps.256" => "__builtin_ia32_vpermt2varps256_mask", - "llvm.x86.avx512.mask.vpermt2var.ps.512" => "__builtin_ia32_vpermt2varps512_mask", - "llvm.x86.avx512.mask.vpermt2var.q.128" => "__builtin_ia32_vpermt2varq128_mask", - "llvm.x86.avx512.mask.vpermt2var.q.256" => "__builtin_ia32_vpermt2varq256_mask", - "llvm.x86.avx512.mask.vpermt2var.q.512" => "__builtin_ia32_vpermt2varq512_mask", - "llvm.x86.avx512.mask.vpermt2var.qi.128" => "__builtin_ia32_vpermt2varqi128_mask", - "llvm.x86.avx512.mask.vpermt2var.qi.256" => "__builtin_ia32_vpermt2varqi256_mask", - "llvm.x86.avx512.mask.vpermt2var.qi.512" => "__builtin_ia32_vpermt2varqi512_mask", - "llvm.x86.avx512.mask.vpmadd52h.uq.128" => "__builtin_ia32_vpmadd52huq128_mask", - "llvm.x86.avx512.mask.vpmadd52h.uq.256" => "__builtin_ia32_vpmadd52huq256_mask", - "llvm.x86.avx512.mask.vpmadd52h.uq.512" => "__builtin_ia32_vpmadd52huq512_mask", - "llvm.x86.avx512.mask.vpmadd52l.uq.128" => "__builtin_ia32_vpmadd52luq128_mask", - "llvm.x86.avx512.mask.vpmadd52l.uq.256" => "__builtin_ia32_vpmadd52luq256_mask", - "llvm.x86.avx512.mask.vpmadd52l.uq.512" => "__builtin_ia32_vpmadd52luq512_mask", - "llvm.x86.avx512.mask.xor.pd.128" => "__builtin_ia32_xorpd128_mask", - "llvm.x86.avx512.mask.xor.pd.256" => "__builtin_ia32_xorpd256_mask", - "llvm.x86.avx512.mask.xor.pd.512" => "__builtin_ia32_xorpd512_mask", - "llvm.x86.avx512.mask.xor.ps.128" => "__builtin_ia32_xorps128_mask", - "llvm.x86.avx512.mask.xor.ps.256" => "__builtin_ia32_xorps256_mask", - "llvm.x86.avx512.mask.xor.ps.512" => "__builtin_ia32_xorps512_mask", - "llvm.x86.avx512.mask3.vfmadd.pd.128" => "__builtin_ia32_vfmaddpd128_mask3", - "llvm.x86.avx512.mask3.vfmadd.pd.256" => "__builtin_ia32_vfmaddpd256_mask3", - "llvm.x86.avx512.mask3.vfmadd.pd.512" => "__builtin_ia32_vfmaddpd512_mask3", - "llvm.x86.avx512.mask3.vfmadd.ps.128" => "__builtin_ia32_vfmaddps128_mask3", - "llvm.x86.avx512.mask3.vfmadd.ps.256" => "__builtin_ia32_vfmaddps256_mask3", - "llvm.x86.avx512.mask3.vfmadd.ps.512" => "__builtin_ia32_vfmaddps512_mask3", - "llvm.x86.avx512.mask3.vfmadd.sd" => "__builtin_ia32_vfmaddsd3_mask3", - "llvm.x86.avx512.mask3.vfmadd.ss" => "__builtin_ia32_vfmaddss3_mask3", - "llvm.x86.avx512.mask3.vfmaddsub.pd.128" => "__builtin_ia32_vfmaddsubpd128_mask3", - "llvm.x86.avx512.mask3.vfmaddsub.pd.256" => "__builtin_ia32_vfmaddsubpd256_mask3", - "llvm.x86.avx512.mask3.vfmaddsub.pd.512" => "__builtin_ia32_vfmaddsubpd512_mask3", - "llvm.x86.avx512.mask3.vfmaddsub.ps.128" => "__builtin_ia32_vfmaddsubps128_mask3", - "llvm.x86.avx512.mask3.vfmaddsub.ps.256" => "__builtin_ia32_vfmaddsubps256_mask3", - "llvm.x86.avx512.mask3.vfmaddsub.ps.512" => "__builtin_ia32_vfmaddsubps512_mask3", - "llvm.x86.avx512.mask3.vfmsub.pd.128" => "__builtin_ia32_vfmsubpd128_mask3", - "llvm.x86.avx512.mask3.vfmsub.pd.256" => "__builtin_ia32_vfmsubpd256_mask3", - "llvm.x86.avx512.mask3.vfmsub.pd.512" => "__builtin_ia32_vfmsubpd512_mask3", - "llvm.x86.avx512.mask3.vfmsub.ps.128" => "__builtin_ia32_vfmsubps128_mask3", - "llvm.x86.avx512.mask3.vfmsub.ps.256" => "__builtin_ia32_vfmsubps256_mask3", - "llvm.x86.avx512.mask3.vfmsub.ps.512" => "__builtin_ia32_vfmsubps512_mask3", - "llvm.x86.avx512.mask3.vfmsubadd.pd.128" => "__builtin_ia32_vfmsubaddpd128_mask3", - "llvm.x86.avx512.mask3.vfmsubadd.pd.256" => "__builtin_ia32_vfmsubaddpd256_mask3", - "llvm.x86.avx512.mask3.vfmsubadd.pd.512" => "__builtin_ia32_vfmsubaddpd512_mask3", - "llvm.x86.avx512.mask3.vfmsubadd.ps.128" => "__builtin_ia32_vfmsubaddps128_mask3", - "llvm.x86.avx512.mask3.vfmsubadd.ps.256" => "__builtin_ia32_vfmsubaddps256_mask3", - "llvm.x86.avx512.mask3.vfmsubadd.ps.512" => "__builtin_ia32_vfmsubaddps512_mask3", - "llvm.x86.avx512.mask3.vfnmsub.pd.128" => "__builtin_ia32_vfnmsubpd128_mask3", - "llvm.x86.avx512.mask3.vfnmsub.pd.256" => "__builtin_ia32_vfnmsubpd256_mask3", - "llvm.x86.avx512.mask3.vfnmsub.pd.512" => "__builtin_ia32_vfnmsubpd512_mask3", - "llvm.x86.avx512.mask3.vfnmsub.ps.128" => "__builtin_ia32_vfnmsubps128_mask3", - "llvm.x86.avx512.mask3.vfnmsub.ps.256" => "__builtin_ia32_vfnmsubps256_mask3", - "llvm.x86.avx512.mask3.vfnmsub.ps.512" => "__builtin_ia32_vfnmsubps512_mask3", "llvm.x86.avx512.maskz.fixupimm.pd.128" => "__builtin_ia32_fixupimmpd128_maskz", "llvm.x86.avx512.maskz.fixupimm.pd.256" => "__builtin_ia32_fixupimmpd256_maskz", "llvm.x86.avx512.maskz.fixupimm.pd.512" => "__builtin_ia32_fixupimmpd512_maskz", @@ -8764,55 +7395,10 @@ match name { "llvm.x86.avx512.maskz.fixupimm.ps.512" => "__builtin_ia32_fixupimmps512_maskz", "llvm.x86.avx512.maskz.fixupimm.sd" => "__builtin_ia32_fixupimmsd_maskz", "llvm.x86.avx512.maskz.fixupimm.ss" => "__builtin_ia32_fixupimmss_maskz", - "llvm.x86.avx512.maskz.pternlog.d.128" => "__builtin_ia32_pternlogd128_maskz", - "llvm.x86.avx512.maskz.pternlog.d.256" => "__builtin_ia32_pternlogd256_maskz", - "llvm.x86.avx512.maskz.pternlog.d.512" => "__builtin_ia32_pternlogd512_maskz", - "llvm.x86.avx512.maskz.pternlog.q.128" => "__builtin_ia32_pternlogq128_maskz", - "llvm.x86.avx512.maskz.pternlog.q.256" => "__builtin_ia32_pternlogq256_maskz", - "llvm.x86.avx512.maskz.pternlog.q.512" => "__builtin_ia32_pternlogq512_maskz", - "llvm.x86.avx512.maskz.vfmadd.pd.128" => "__builtin_ia32_vfmaddpd128_maskz", - "llvm.x86.avx512.maskz.vfmadd.pd.256" => "__builtin_ia32_vfmaddpd256_maskz", - "llvm.x86.avx512.maskz.vfmadd.pd.512" => "__builtin_ia32_vfmaddpd512_maskz", - "llvm.x86.avx512.maskz.vfmadd.ps.128" => "__builtin_ia32_vfmaddps128_maskz", - "llvm.x86.avx512.maskz.vfmadd.ps.256" => "__builtin_ia32_vfmaddps256_maskz", - "llvm.x86.avx512.maskz.vfmadd.ps.512" => "__builtin_ia32_vfmaddps512_maskz", - "llvm.x86.avx512.maskz.vfmadd.sd" => "__builtin_ia32_vfmaddsd3_maskz", - "llvm.x86.avx512.maskz.vfmadd.ss" => "__builtin_ia32_vfmaddss3_maskz", - "llvm.x86.avx512.maskz.vfmaddsub.pd.128" => "__builtin_ia32_vfmaddsubpd128_maskz", - "llvm.x86.avx512.maskz.vfmaddsub.pd.256" => "__builtin_ia32_vfmaddsubpd256_maskz", - "llvm.x86.avx512.maskz.vfmaddsub.pd.512" => "__builtin_ia32_vfmaddsubpd512_maskz", - "llvm.x86.avx512.maskz.vfmaddsub.ps.128" => "__builtin_ia32_vfmaddsubps128_maskz", - "llvm.x86.avx512.maskz.vfmaddsub.ps.256" => "__builtin_ia32_vfmaddsubps256_maskz", - "llvm.x86.avx512.maskz.vfmaddsub.ps.512" => "__builtin_ia32_vfmaddsubps512_maskz", - "llvm.x86.avx512.maskz.vpermt2var.d.128" => "__builtin_ia32_vpermt2vard128_maskz", - "llvm.x86.avx512.maskz.vpermt2var.d.256" => "__builtin_ia32_vpermt2vard256_maskz", - "llvm.x86.avx512.maskz.vpermt2var.d.512" => "__builtin_ia32_vpermt2vard512_maskz", - "llvm.x86.avx512.maskz.vpermt2var.hi.128" => "__builtin_ia32_vpermt2varhi128_maskz", - "llvm.x86.avx512.maskz.vpermt2var.hi.256" => "__builtin_ia32_vpermt2varhi256_maskz", - "llvm.x86.avx512.maskz.vpermt2var.hi.512" => "__builtin_ia32_vpermt2varhi512_maskz", - "llvm.x86.avx512.maskz.vpermt2var.pd.128" => "__builtin_ia32_vpermt2varpd128_maskz", - "llvm.x86.avx512.maskz.vpermt2var.pd.256" => "__builtin_ia32_vpermt2varpd256_maskz", - "llvm.x86.avx512.maskz.vpermt2var.pd.512" => "__builtin_ia32_vpermt2varpd512_maskz", - "llvm.x86.avx512.maskz.vpermt2var.ps.128" => "__builtin_ia32_vpermt2varps128_maskz", - "llvm.x86.avx512.maskz.vpermt2var.ps.256" => "__builtin_ia32_vpermt2varps256_maskz", - "llvm.x86.avx512.maskz.vpermt2var.ps.512" => "__builtin_ia32_vpermt2varps512_maskz", - "llvm.x86.avx512.maskz.vpermt2var.q.128" => "__builtin_ia32_vpermt2varq128_maskz", - "llvm.x86.avx512.maskz.vpermt2var.q.256" => "__builtin_ia32_vpermt2varq256_maskz", - "llvm.x86.avx512.maskz.vpermt2var.q.512" => "__builtin_ia32_vpermt2varq512_maskz", - "llvm.x86.avx512.maskz.vpermt2var.qi.128" => "__builtin_ia32_vpermt2varqi128_maskz", - "llvm.x86.avx512.maskz.vpermt2var.qi.256" => "__builtin_ia32_vpermt2varqi256_maskz", - "llvm.x86.avx512.maskz.vpermt2var.qi.512" => "__builtin_ia32_vpermt2varqi512_maskz", - "llvm.x86.avx512.maskz.vpmadd52h.uq.128" => "__builtin_ia32_vpmadd52huq128_maskz", - "llvm.x86.avx512.maskz.vpmadd52h.uq.256" => "__builtin_ia32_vpmadd52huq256_maskz", - "llvm.x86.avx512.maskz.vpmadd52h.uq.512" => "__builtin_ia32_vpmadd52huq512_maskz", - "llvm.x86.avx512.maskz.vpmadd52l.uq.128" => "__builtin_ia32_vpmadd52luq128_maskz", - "llvm.x86.avx512.maskz.vpmadd52l.uq.256" => "__builtin_ia32_vpmadd52luq256_maskz", - "llvm.x86.avx512.maskz.vpmadd52l.uq.512" => "__builtin_ia32_vpmadd52luq512_maskz", "llvm.x86.avx512.max.pd.512" => "__builtin_ia32_maxpd512", "llvm.x86.avx512.max.ps.512" => "__builtin_ia32_maxps512", "llvm.x86.avx512.min.pd.512" => "__builtin_ia32_minpd512", "llvm.x86.avx512.min.ps.512" => "__builtin_ia32_minps512", - "llvm.x86.avx512.movntdqa" => "__builtin_ia32_movntdqa512", "llvm.x86.avx512.mul.pd.512" => "__builtin_ia32_mulpd512", "llvm.x86.avx512.mul.ps.512" => "__builtin_ia32_mulps512", "llvm.x86.avx512.packssdw.512" => "__builtin_ia32_packssdw512", @@ -8821,8 +7407,6 @@ match name { "llvm.x86.avx512.packuswb.512" => "__builtin_ia32_packuswb512", "llvm.x86.avx512.pavg.b.512" => "__builtin_ia32_pavgb512", "llvm.x86.avx512.pavg.w.512" => "__builtin_ia32_pavgw512", - "llvm.x86.avx512.pbroadcastd.512" => "__builtin_ia32_pbroadcastd512", - "llvm.x86.avx512.pbroadcastq.512" => "__builtin_ia32_pbroadcastq512", "llvm.x86.avx512.permvar.df.256" => "__builtin_ia32_permvardf256", "llvm.x86.avx512.permvar.df.512" => "__builtin_ia32_permvardf512", "llvm.x86.avx512.permvar.di.256" => "__builtin_ia32_permvardi256", @@ -8837,11 +7421,6 @@ match name { "llvm.x86.avx512.permvar.si.512" => "__builtin_ia32_permvarsi512", "llvm.x86.avx512.pmaddubs.w.512" => "__builtin_ia32_pmaddubsw512", "llvm.x86.avx512.pmaddw.d.512" => "__builtin_ia32_pmaddwd512", - "llvm.x86.avx512.pmovzxbd" => "__builtin_ia32_pmovzxbd512", - "llvm.x86.avx512.pmovzxbq" => "__builtin_ia32_pmovzxbq512", - "llvm.x86.avx512.pmovzxdq" => "__builtin_ia32_pmovzxdq512", - "llvm.x86.avx512.pmovzxwd" => "__builtin_ia32_pmovzxwd512", - "llvm.x86.avx512.pmovzxwq" => "__builtin_ia32_pmovzxwq512", "llvm.x86.avx512.pmul.hr.sw.512" => "__builtin_ia32_pmulhrsw512", "llvm.x86.avx512.pmulh.w.512" => "__builtin_ia32_pmulhw512", "llvm.x86.avx512.pmulhu.w.512" => "__builtin_ia32_pmulhuw512", @@ -8851,8 +7430,6 @@ match name { "llvm.x86.avx512.psad.bw.512" => "__builtin_ia32_psadbw512", "llvm.x86.avx512.pshuf.b.512" => "__builtin_ia32_pshufb512", "llvm.x86.avx512.psll.d.512" => "__builtin_ia32_pslld512", - "llvm.x86.avx512.psll.dq" => "__builtin_ia32_pslldqi512", - "llvm.x86.avx512.psll.dq.bs" => "__builtin_ia32_pslldqi512_byteshift", "llvm.x86.avx512.psll.q.512" => "__builtin_ia32_psllq512", "llvm.x86.avx512.psll.w.512" => "__builtin_ia32_psllw512", "llvm.x86.avx512.pslli.d.512" => "__builtin_ia32_pslldi512", @@ -8881,8 +7458,6 @@ match name { "llvm.x86.avx512.psrav.w.256" => "__builtin_ia32_psrav16hi", "llvm.x86.avx512.psrav.w.512" => "__builtin_ia32_psrav32hi", "llvm.x86.avx512.psrl.d.512" => "__builtin_ia32_psrld512", - "llvm.x86.avx512.psrl.dq" => "__builtin_ia32_psrldqi512", - "llvm.x86.avx512.psrl.dq.bs" => "__builtin_ia32_psrldqi512_byteshift", "llvm.x86.avx512.psrl.q.512" => "__builtin_ia32_psrlq512", "llvm.x86.avx512.psrl.w.512" => "__builtin_ia32_psrlw512", "llvm.x86.avx512.psrli.d.512" => "__builtin_ia32_psrldi512", @@ -8899,30 +7474,6 @@ match name { "llvm.x86.avx512.pternlog.q.128" => "__builtin_ia32_pternlogq128", "llvm.x86.avx512.pternlog.q.256" => "__builtin_ia32_pternlogq256", "llvm.x86.avx512.pternlog.q.512" => "__builtin_ia32_pternlogq512", - "llvm.x86.avx512.ptestm.b.128" => "__builtin_ia32_ptestmb128", - "llvm.x86.avx512.ptestm.b.256" => "__builtin_ia32_ptestmb256", - "llvm.x86.avx512.ptestm.b.512" => "__builtin_ia32_ptestmb512", - "llvm.x86.avx512.ptestm.d.128" => "__builtin_ia32_ptestmd128", - "llvm.x86.avx512.ptestm.d.256" => "__builtin_ia32_ptestmd256", - "llvm.x86.avx512.ptestm.d.512" => "__builtin_ia32_ptestmd512", - "llvm.x86.avx512.ptestm.q.128" => "__builtin_ia32_ptestmq128", - "llvm.x86.avx512.ptestm.q.256" => "__builtin_ia32_ptestmq256", - "llvm.x86.avx512.ptestm.q.512" => "__builtin_ia32_ptestmq512", - "llvm.x86.avx512.ptestm.w.128" => "__builtin_ia32_ptestmw128", - "llvm.x86.avx512.ptestm.w.256" => "__builtin_ia32_ptestmw256", - "llvm.x86.avx512.ptestm.w.512" => "__builtin_ia32_ptestmw512", - "llvm.x86.avx512.ptestnm.b.128" => "__builtin_ia32_ptestnmb128", - "llvm.x86.avx512.ptestnm.b.256" => "__builtin_ia32_ptestnmb256", - "llvm.x86.avx512.ptestnm.b.512" => "__builtin_ia32_ptestnmb512", - "llvm.x86.avx512.ptestnm.d.128" => "__builtin_ia32_ptestnmd128", - "llvm.x86.avx512.ptestnm.d.256" => "__builtin_ia32_ptestnmd256", - "llvm.x86.avx512.ptestnm.d.512" => "__builtin_ia32_ptestnmd512", - "llvm.x86.avx512.ptestnm.q.128" => "__builtin_ia32_ptestnmq128", - "llvm.x86.avx512.ptestnm.q.256" => "__builtin_ia32_ptestnmq256", - "llvm.x86.avx512.ptestnm.q.512" => "__builtin_ia32_ptestnmq512", - "llvm.x86.avx512.ptestnm.w.128" => "__builtin_ia32_ptestnmw128", - "llvm.x86.avx512.ptestnm.w.256" => "__builtin_ia32_ptestnmw256", - "llvm.x86.avx512.ptestnm.w.512" => "__builtin_ia32_ptestnmw512", "llvm.x86.avx512.rcp14.pd.128" => "__builtin_ia32_rcp14pd128_mask", "llvm.x86.avx512.rcp14.pd.256" => "__builtin_ia32_rcp14pd256_mask", "llvm.x86.avx512.rcp14.pd.512" => "__builtin_ia32_rcp14pd512_mask", @@ -8931,14 +7482,6 @@ match name { "llvm.x86.avx512.rcp14.ps.512" => "__builtin_ia32_rcp14ps512_mask", "llvm.x86.avx512.rcp14.sd" => "__builtin_ia32_rcp14sd_mask", "llvm.x86.avx512.rcp14.ss" => "__builtin_ia32_rcp14ss_mask", - "llvm.x86.avx512.rcp28.pd" => "__builtin_ia32_rcp28pd_mask", - "llvm.x86.avx512.rcp28.ps" => "__builtin_ia32_rcp28ps_mask", - "llvm.x86.avx512.rcp28.sd" => "__builtin_ia32_rcp28sd_mask", - // [DUPLICATE]: "llvm.x86.avx512.rcp28.sd" => "__builtin_ia32_rcp28sd_round_mask", - "llvm.x86.avx512.rcp28.ss" => "__builtin_ia32_rcp28ss_mask", - // [DUPLICATE]: "llvm.x86.avx512.rcp28.ss" => "__builtin_ia32_rcp28ss_round_mask", - "llvm.x86.avx512.rndscale.sd" => "__builtin_ia32_rndscalesd", - "llvm.x86.avx512.rndscale.ss" => "__builtin_ia32_rndscaless", "llvm.x86.avx512.rsqrt14.pd.128" => "__builtin_ia32_rsqrt14pd128_mask", "llvm.x86.avx512.rsqrt14.pd.256" => "__builtin_ia32_rsqrt14pd256_mask", "llvm.x86.avx512.rsqrt14.pd.512" => "__builtin_ia32_rsqrt14pd512_mask", @@ -8947,50 +7490,8 @@ match name { "llvm.x86.avx512.rsqrt14.ps.512" => "__builtin_ia32_rsqrt14ps512_mask", "llvm.x86.avx512.rsqrt14.sd" => "__builtin_ia32_rsqrt14sd_mask", "llvm.x86.avx512.rsqrt14.ss" => "__builtin_ia32_rsqrt14ss_mask", - "llvm.x86.avx512.rsqrt28.pd" => "__builtin_ia32_rsqrt28pd_mask", - "llvm.x86.avx512.rsqrt28.ps" => "__builtin_ia32_rsqrt28ps_mask", - "llvm.x86.avx512.rsqrt28.sd" => "__builtin_ia32_rsqrt28sd_mask", - // [DUPLICATE]: "llvm.x86.avx512.rsqrt28.sd" => "__builtin_ia32_rsqrt28sd_round_mask", - "llvm.x86.avx512.rsqrt28.ss" => "__builtin_ia32_rsqrt28ss_mask", - // [DUPLICATE]: "llvm.x86.avx512.rsqrt28.ss" => "__builtin_ia32_rsqrt28ss_round_mask", - "llvm.x86.avx512.scatter.dpd.512" => "__builtin_ia32_scattersiv8df", - "llvm.x86.avx512.scatter.dpi.512" => "__builtin_ia32_scattersiv16si", - "llvm.x86.avx512.scatter.dpq.512" => "__builtin_ia32_scattersiv8di", - "llvm.x86.avx512.scatter.dps.512" => "__builtin_ia32_scattersiv16sf", - "llvm.x86.avx512.scatter.qpd.512" => "__builtin_ia32_scatterdiv8df", - "llvm.x86.avx512.scatter.qpi.512" => "__builtin_ia32_scatterdiv16si", - "llvm.x86.avx512.scatter.qpq.512" => "__builtin_ia32_scatterdiv8di", - "llvm.x86.avx512.scatter.qps.512" => "__builtin_ia32_scatterdiv16sf", - "llvm.x86.avx512.scatterdiv2.df" => "__builtin_ia32_scatterdiv2df", - "llvm.x86.avx512.scatterdiv2.di" => "__builtin_ia32_scatterdiv2di", - "llvm.x86.avx512.scatterdiv4.df" => "__builtin_ia32_scatterdiv4df", - "llvm.x86.avx512.scatterdiv4.di" => "__builtin_ia32_scatterdiv4di", - "llvm.x86.avx512.scatterdiv4.sf" => "__builtin_ia32_scatterdiv4sf", - "llvm.x86.avx512.scatterdiv4.si" => "__builtin_ia32_scatterdiv4si", - "llvm.x86.avx512.scatterdiv8.sf" => "__builtin_ia32_scatterdiv8sf", - "llvm.x86.avx512.scatterdiv8.si" => "__builtin_ia32_scatterdiv8si", - "llvm.x86.avx512.scatterpf.dpd.512" => "__builtin_ia32_scatterpfdpd", - "llvm.x86.avx512.scatterpf.dps.512" => "__builtin_ia32_scatterpfdps", - "llvm.x86.avx512.scatterpf.qpd.512" => "__builtin_ia32_scatterpfqpd", - "llvm.x86.avx512.scatterpf.qps.512" => "__builtin_ia32_scatterpfqps", - "llvm.x86.avx512.scattersiv2.df" => "__builtin_ia32_scattersiv2df", - "llvm.x86.avx512.scattersiv2.di" => "__builtin_ia32_scattersiv2di", - "llvm.x86.avx512.scattersiv4.df" => "__builtin_ia32_scattersiv4df", - "llvm.x86.avx512.scattersiv4.di" => "__builtin_ia32_scattersiv4di", - "llvm.x86.avx512.scattersiv4.sf" => "__builtin_ia32_scattersiv4sf", - "llvm.x86.avx512.scattersiv4.si" => "__builtin_ia32_scattersiv4si", - "llvm.x86.avx512.scattersiv8.sf" => "__builtin_ia32_scattersiv8sf", - "llvm.x86.avx512.scattersiv8.si" => "__builtin_ia32_scattersiv8si", - "llvm.x86.avx512.sqrt.pd.512" => "__builtin_ia32_sqrtpd512_mask", - "llvm.x86.avx512.sqrt.ps.512" => "__builtin_ia32_sqrtps512_mask", - "llvm.x86.avx512.sqrt.sd" => "__builtin_ia32_sqrtrndsd", - "llvm.x86.avx512.sqrt.ss" => "__builtin_ia32_sqrtrndss", "llvm.x86.avx512.sub.pd.512" => "__builtin_ia32_subpd512", "llvm.x86.avx512.sub.ps.512" => "__builtin_ia32_subps512", - "llvm.x86.avx512.vbroadcast.sd.512" => "__builtin_ia32_vbroadcastsd512", - "llvm.x86.avx512.vbroadcast.sd.pd.512" => "__builtin_ia32_vbroadcastsd_pd512", - "llvm.x86.avx512.vbroadcast.ss.512" => "__builtin_ia32_vbroadcastss512", - "llvm.x86.avx512.vbroadcast.ss.ps.512" => "__builtin_ia32_vbroadcastss_ps512", "llvm.x86.avx512.vcomi.sd" => "__builtin_ia32_vcomisd", "llvm.x86.avx512.vcomi.ss" => "__builtin_ia32_vcomiss", "llvm.x86.avx512.vcvtsd2si32" => "__builtin_ia32_vcvtsd2si32", @@ -9190,6 +7691,60 @@ match name { "llvm.x86.avx512fp16.vcvtusi642sh" => "__builtin_ia32_vcvtusi642sh", "llvm.x86.avx512fp16.vfmaddsub.ph.128" => "__builtin_ia32_vfmaddsubph", "llvm.x86.avx512fp16.vfmaddsub.ph.256" => "__builtin_ia32_vfmaddsubph256", + "llvm.x86.avx.addsub.pd.256" => "__builtin_ia32_addsubpd256", + "llvm.x86.avx.addsub.ps.256" => "__builtin_ia32_addsubps256", + "llvm.x86.avx.blendv.pd.256" => "__builtin_ia32_blendvpd256", + "llvm.x86.avx.blendv.ps.256" => "__builtin_ia32_blendvps256", + "llvm.x86.avx.cvt.pd2.ps.256" => "__builtin_ia32_cvtpd2ps256", + "llvm.x86.avx.cvt.pd2dq.256" => "__builtin_ia32_cvtpd2dq256", + "llvm.x86.avx.cvt.ps2dq.256" => "__builtin_ia32_cvtps2dq256", + "llvm.x86.avx.cvtt.pd2dq.256" => "__builtin_ia32_cvttpd2dq256", + "llvm.x86.avx.cvtt.ps2dq.256" => "__builtin_ia32_cvttps2dq256", + "llvm.x86.avx.dp.ps.256" => "__builtin_ia32_dpps256", + "llvm.x86.avx.hadd.pd.256" => "__builtin_ia32_haddpd256", + "llvm.x86.avx.hadd.ps.256" => "__builtin_ia32_haddps256", + "llvm.x86.avx.hsub.pd.256" => "__builtin_ia32_hsubpd256", + "llvm.x86.avx.hsub.ps.256" => "__builtin_ia32_hsubps256", + "llvm.x86.avx.ldu.dq.256" => "__builtin_ia32_lddqu256", + "llvm.x86.avx.maskload.pd" => "__builtin_ia32_maskloadpd", + "llvm.x86.avx.maskload.pd.256" => "__builtin_ia32_maskloadpd256", + "llvm.x86.avx.maskload.ps" => "__builtin_ia32_maskloadps", + "llvm.x86.avx.maskload.ps.256" => "__builtin_ia32_maskloadps256", + "llvm.x86.avx.maskstore.pd" => "__builtin_ia32_maskstorepd", + "llvm.x86.avx.maskstore.pd.256" => "__builtin_ia32_maskstorepd256", + "llvm.x86.avx.maskstore.ps" => "__builtin_ia32_maskstoreps", + "llvm.x86.avx.maskstore.ps.256" => "__builtin_ia32_maskstoreps256", + "llvm.x86.avx.max.pd.256" => "__builtin_ia32_maxpd256", + "llvm.x86.avx.max.ps.256" => "__builtin_ia32_maxps256", + "llvm.x86.avx.min.pd.256" => "__builtin_ia32_minpd256", + "llvm.x86.avx.min.ps.256" => "__builtin_ia32_minps256", + "llvm.x86.avx.movmsk.pd.256" => "__builtin_ia32_movmskpd256", + "llvm.x86.avx.movmsk.ps.256" => "__builtin_ia32_movmskps256", + "llvm.x86.avx.ptestc.256" => "__builtin_ia32_ptestc256", + "llvm.x86.avx.ptestnzc.256" => "__builtin_ia32_ptestnzc256", + "llvm.x86.avx.ptestz.256" => "__builtin_ia32_ptestz256", + "llvm.x86.avx.rcp.ps.256" => "__builtin_ia32_rcpps256", + "llvm.x86.avx.round.pd.256" => "__builtin_ia32_roundpd256", + "llvm.x86.avx.round.ps.256" => "__builtin_ia32_roundps256", + "llvm.x86.avx.rsqrt.ps.256" => "__builtin_ia32_rsqrtps256", + "llvm.x86.avx.vpermilvar.pd" => "__builtin_ia32_vpermilvarpd", + "llvm.x86.avx.vpermilvar.pd.256" => "__builtin_ia32_vpermilvarpd256", + "llvm.x86.avx.vpermilvar.ps" => "__builtin_ia32_vpermilvarps", + "llvm.x86.avx.vpermilvar.ps.256" => "__builtin_ia32_vpermilvarps256", + "llvm.x86.avx.vtestc.pd" => "__builtin_ia32_vtestcpd", + "llvm.x86.avx.vtestc.pd.256" => "__builtin_ia32_vtestcpd256", + "llvm.x86.avx.vtestc.ps" => "__builtin_ia32_vtestcps", + "llvm.x86.avx.vtestc.ps.256" => "__builtin_ia32_vtestcps256", + "llvm.x86.avx.vtestnzc.pd" => "__builtin_ia32_vtestnzcpd", + "llvm.x86.avx.vtestnzc.pd.256" => "__builtin_ia32_vtestnzcpd256", + "llvm.x86.avx.vtestnzc.ps" => "__builtin_ia32_vtestnzcps", + "llvm.x86.avx.vtestnzc.ps.256" => "__builtin_ia32_vtestnzcps256", + "llvm.x86.avx.vtestz.pd" => "__builtin_ia32_vtestzpd", + "llvm.x86.avx.vtestz.pd.256" => "__builtin_ia32_vtestzpd256", + "llvm.x86.avx.vtestz.ps" => "__builtin_ia32_vtestzps", + "llvm.x86.avx.vtestz.ps.256" => "__builtin_ia32_vtestzps256", + "llvm.x86.avx.vzeroall" => "__builtin_ia32_vzeroall", + "llvm.x86.avx.vzeroupper" => "__builtin_ia32_vzeroupper", "llvm.x86.axor32" => "__builtin_ia32_axor32", "llvm.x86.axor64" => "__builtin_ia32_axor64", "llvm.x86.bmi.bextr.32" => "__builtin_ia32_bextr_u32", @@ -9216,50 +7771,10 @@ match name { "llvm.x86.flags.read.u64" => "__builtin_ia32_readeflags_u64", "llvm.x86.flags.write.u32" => "__builtin_ia32_writeeflags_u32", "llvm.x86.flags.write.u64" => "__builtin_ia32_writeeflags_u64", - "llvm.x86.fma.mask.vfmadd.pd.512" => "__builtin_ia32_vfmaddpd512_mask", - "llvm.x86.fma.mask.vfmadd.ps.512" => "__builtin_ia32_vfmaddps512_mask", - "llvm.x86.fma.mask.vfmaddsub.pd.512" => "__builtin_ia32_vfmaddsubpd512_mask", - "llvm.x86.fma.mask.vfmaddsub.ps.512" => "__builtin_ia32_vfmaddsubps512_mask", - "llvm.x86.fma.mask.vfmsub.pd.512" => "__builtin_ia32_vfmsubpd512_mask", - "llvm.x86.fma.mask.vfmsub.ps.512" => "__builtin_ia32_vfmsubps512_mask", - "llvm.x86.fma.mask.vfmsubadd.pd.512" => "__builtin_ia32_vfmsubaddpd512_mask", - "llvm.x86.fma.mask.vfmsubadd.ps.512" => "__builtin_ia32_vfmsubaddps512_mask", - "llvm.x86.fma.mask.vfnmadd.pd.512" => "__builtin_ia32_vfnmaddpd512_mask", - "llvm.x86.fma.mask.vfnmadd.ps.512" => "__builtin_ia32_vfnmaddps512_mask", - "llvm.x86.fma.mask.vfnmsub.pd.512" => "__builtin_ia32_vfnmsubpd512_mask", - "llvm.x86.fma.mask.vfnmsub.ps.512" => "__builtin_ia32_vfnmsubps512_mask", - "llvm.x86.fma.vfmadd.pd" => "__builtin_ia32_vfmaddpd", - "llvm.x86.fma.vfmadd.pd.256" => "__builtin_ia32_vfmaddpd256", - "llvm.x86.fma.vfmadd.ps" => "__builtin_ia32_vfmaddps", - "llvm.x86.fma.vfmadd.ps.256" => "__builtin_ia32_vfmaddps256", - "llvm.x86.fma.vfmadd.sd" => "__builtin_ia32_vfmaddsd", - "llvm.x86.fma.vfmadd.ss" => "__builtin_ia32_vfmaddss", "llvm.x86.fma.vfmaddsub.pd" => "__builtin_ia32_vfmaddsubpd", "llvm.x86.fma.vfmaddsub.pd.256" => "__builtin_ia32_vfmaddsubpd256", "llvm.x86.fma.vfmaddsub.ps" => "__builtin_ia32_vfmaddsubps", "llvm.x86.fma.vfmaddsub.ps.256" => "__builtin_ia32_vfmaddsubps256", - "llvm.x86.fma.vfmsub.pd" => "__builtin_ia32_vfmsubpd", - "llvm.x86.fma.vfmsub.pd.256" => "__builtin_ia32_vfmsubpd256", - "llvm.x86.fma.vfmsub.ps" => "__builtin_ia32_vfmsubps", - "llvm.x86.fma.vfmsub.ps.256" => "__builtin_ia32_vfmsubps256", - "llvm.x86.fma.vfmsub.sd" => "__builtin_ia32_vfmsubsd", - "llvm.x86.fma.vfmsub.ss" => "__builtin_ia32_vfmsubss", - "llvm.x86.fma.vfmsubadd.pd" => "__builtin_ia32_vfmsubaddpd", - "llvm.x86.fma.vfmsubadd.pd.256" => "__builtin_ia32_vfmsubaddpd256", - "llvm.x86.fma.vfmsubadd.ps" => "__builtin_ia32_vfmsubaddps", - "llvm.x86.fma.vfmsubadd.ps.256" => "__builtin_ia32_vfmsubaddps256", - "llvm.x86.fma.vfnmadd.pd" => "__builtin_ia32_vfnmaddpd", - "llvm.x86.fma.vfnmadd.pd.256" => "__builtin_ia32_vfnmaddpd256", - "llvm.x86.fma.vfnmadd.ps" => "__builtin_ia32_vfnmaddps", - "llvm.x86.fma.vfnmadd.ps.256" => "__builtin_ia32_vfnmaddps256", - "llvm.x86.fma.vfnmadd.sd" => "__builtin_ia32_vfnmaddsd", - "llvm.x86.fma.vfnmadd.ss" => "__builtin_ia32_vfnmaddss", - "llvm.x86.fma.vfnmsub.pd" => "__builtin_ia32_vfnmsubpd", - "llvm.x86.fma.vfnmsub.pd.256" => "__builtin_ia32_vfnmsubpd256", - "llvm.x86.fma.vfnmsub.ps" => "__builtin_ia32_vfnmsubps", - "llvm.x86.fma.vfnmsub.ps.256" => "__builtin_ia32_vfnmsubps256", - "llvm.x86.fma.vfnmsub.sd" => "__builtin_ia32_vfnmsubsd", - "llvm.x86.fma.vfnmsub.ss" => "__builtin_ia32_vfnmsubss", "llvm.x86.fxrstor" => "__builtin_ia32_fxrstor", "llvm.x86.fxrstor64" => "__builtin_ia32_fxrstor64", "llvm.x86.fxsave" => "__builtin_ia32_fxsave", @@ -9276,7 +7791,75 @@ match name { "llvm.x86.lwpval32" => "__builtin_ia32_lwpval32", "llvm.x86.lwpval64" => "__builtin_ia32_lwpval64", "llvm.x86.mmx.emms" => "__builtin_ia32_emms", - "llvm.x86.mmx.femms" => "__builtin_ia32_femms", + "llvm.x86.mmx.maskmovq" => "__builtin_ia32_maskmovq", + "llvm.x86.mmx.movnt.dq" => "__builtin_ia32_movntq", + "llvm.x86.mmx.packssdw" => "__builtin_ia32_packssdw", + "llvm.x86.mmx.packsswb" => "__builtin_ia32_packsswb", + "llvm.x86.mmx.packuswb" => "__builtin_ia32_packuswb", + "llvm.x86.mmx.padd.b" => "__builtin_ia32_paddb", + "llvm.x86.mmx.padd.d" => "__builtin_ia32_paddd", + "llvm.x86.mmx.padd.q" => "__builtin_ia32_paddq", + "llvm.x86.mmx.padd.w" => "__builtin_ia32_paddw", + "llvm.x86.mmx.padds.b" => "__builtin_ia32_paddsb", + "llvm.x86.mmx.padds.w" => "__builtin_ia32_paddsw", + "llvm.x86.mmx.paddus.b" => "__builtin_ia32_paddusb", + "llvm.x86.mmx.paddus.w" => "__builtin_ia32_paddusw", + "llvm.x86.mmx.palignr.b" => "__builtin_ia32_palignr", + "llvm.x86.mmx.pand" => "__builtin_ia32_pand", + "llvm.x86.mmx.pandn" => "__builtin_ia32_pandn", + "llvm.x86.mmx.pavg.b" => "__builtin_ia32_pavgb", + "llvm.x86.mmx.pavg.w" => "__builtin_ia32_pavgw", + "llvm.x86.mmx.pcmpeq.b" => "__builtin_ia32_pcmpeqb", + "llvm.x86.mmx.pcmpeq.d" => "__builtin_ia32_pcmpeqd", + "llvm.x86.mmx.pcmpeq.w" => "__builtin_ia32_pcmpeqw", + "llvm.x86.mmx.pcmpgt.b" => "__builtin_ia32_pcmpgtb", + "llvm.x86.mmx.pcmpgt.d" => "__builtin_ia32_pcmpgtd", + "llvm.x86.mmx.pcmpgt.w" => "__builtin_ia32_pcmpgtw", + "llvm.x86.mmx.pextr.w" => "__builtin_ia32_vec_ext_v4hi", + "llvm.x86.mmx.pinsr.w" => "__builtin_ia32_vec_set_v4hi", + "llvm.x86.mmx.pmadd.wd" => "__builtin_ia32_pmaddwd", + "llvm.x86.mmx.pmaxs.w" => "__builtin_ia32_pmaxsw", + "llvm.x86.mmx.pmaxu.b" => "__builtin_ia32_pmaxub", + "llvm.x86.mmx.pmins.w" => "__builtin_ia32_pminsw", + "llvm.x86.mmx.pminu.b" => "__builtin_ia32_pminub", + "llvm.x86.mmx.pmovmskb" => "__builtin_ia32_pmovmskb", + "llvm.x86.mmx.pmulh.w" => "__builtin_ia32_pmulhw", + "llvm.x86.mmx.pmulhu.w" => "__builtin_ia32_pmulhuw", + "llvm.x86.mmx.pmull.w" => "__builtin_ia32_pmullw", + "llvm.x86.mmx.pmulu.dq" => "__builtin_ia32_pmuludq", + "llvm.x86.mmx.por" => "__builtin_ia32_por", + "llvm.x86.mmx.psad.bw" => "__builtin_ia32_psadbw", + "llvm.x86.mmx.psll.d" => "__builtin_ia32_pslld", + "llvm.x86.mmx.psll.q" => "__builtin_ia32_psllq", + "llvm.x86.mmx.psll.w" => "__builtin_ia32_psllw", + "llvm.x86.mmx.pslli.d" => "__builtin_ia32_pslldi", + "llvm.x86.mmx.pslli.q" => "__builtin_ia32_psllqi", + "llvm.x86.mmx.pslli.w" => "__builtin_ia32_psllwi", + "llvm.x86.mmx.psra.d" => "__builtin_ia32_psrad", + "llvm.x86.mmx.psra.w" => "__builtin_ia32_psraw", + "llvm.x86.mmx.psrai.d" => "__builtin_ia32_psradi", + "llvm.x86.mmx.psrai.w" => "__builtin_ia32_psrawi", + "llvm.x86.mmx.psrl.d" => "__builtin_ia32_psrld", + "llvm.x86.mmx.psrl.q" => "__builtin_ia32_psrlq", + "llvm.x86.mmx.psrl.w" => "__builtin_ia32_psrlw", + "llvm.x86.mmx.psrli.d" => "__builtin_ia32_psrldi", + "llvm.x86.mmx.psrli.q" => "__builtin_ia32_psrlqi", + "llvm.x86.mmx.psrli.w" => "__builtin_ia32_psrlwi", + "llvm.x86.mmx.psub.b" => "__builtin_ia32_psubb", + "llvm.x86.mmx.psub.d" => "__builtin_ia32_psubd", + "llvm.x86.mmx.psub.q" => "__builtin_ia32_psubq", + "llvm.x86.mmx.psub.w" => "__builtin_ia32_psubw", + "llvm.x86.mmx.psubs.b" => "__builtin_ia32_psubsb", + "llvm.x86.mmx.psubs.w" => "__builtin_ia32_psubsw", + "llvm.x86.mmx.psubus.b" => "__builtin_ia32_psubusb", + "llvm.x86.mmx.psubus.w" => "__builtin_ia32_psubusw", + "llvm.x86.mmx.punpckhbw" => "__builtin_ia32_punpckhbw", + "llvm.x86.mmx.punpckhdq" => "__builtin_ia32_punpckhdq", + "llvm.x86.mmx.punpckhwd" => "__builtin_ia32_punpckhwd", + "llvm.x86.mmx.punpcklbw" => "__builtin_ia32_punpcklbw", + "llvm.x86.mmx.punpckldq" => "__builtin_ia32_punpckldq", + "llvm.x86.mmx.punpcklwd" => "__builtin_ia32_punpcklwd", + "llvm.x86.mmx.pxor" => "__builtin_ia32_pxor", "llvm.x86.monitorx" => "__builtin_ia32_monitorx", "llvm.x86.movdir64b" => "__builtin_ia32_movdir64b", "llvm.x86.mwaitx" => "__builtin_ia32_mwaitx", @@ -9296,7 +7879,6 @@ match name { "llvm.x86.rdsspd" => "__builtin_ia32_rdsspd", "llvm.x86.rdsspq" => "__builtin_ia32_rdsspq", "llvm.x86.rdtsc" => "__builtin_ia32_rdtsc", - "llvm.x86.rdtscp" => "__builtin_ia32_rdtscp", "llvm.x86.rstorssp" => "__builtin_ia32_rstorssp", "llvm.x86.saveprevssp" => "__builtin_ia32_saveprevssp", "llvm.x86.senduipi" => "__builtin_ia32_senduipi", @@ -9310,46 +7892,7 @@ match name { "llvm.x86.sha256msg2" => "__builtin_ia32_sha256msg2", "llvm.x86.sha256rnds2" => "__builtin_ia32_sha256rnds2", "llvm.x86.slwpcb" => "__builtin_ia32_slwpcb", - "llvm.x86.sse.add.ss" => "__builtin_ia32_addss", - "llvm.x86.sse.cmp.ps" => "__builtin_ia32_cmpps", - "llvm.x86.sse.cmp.ss" => "__builtin_ia32_cmpss", - "llvm.x86.sse.comieq.ss" => "__builtin_ia32_comieq", - "llvm.x86.sse.comige.ss" => "__builtin_ia32_comige", - "llvm.x86.sse.comigt.ss" => "__builtin_ia32_comigt", - "llvm.x86.sse.comile.ss" => "__builtin_ia32_comile", - "llvm.x86.sse.comilt.ss" => "__builtin_ia32_comilt", - "llvm.x86.sse.comineq.ss" => "__builtin_ia32_comineq", - "llvm.x86.sse.cvtsi2ss" => "__builtin_ia32_cvtsi2ss", - "llvm.x86.sse.cvtsi642ss" => "__builtin_ia32_cvtsi642ss", - "llvm.x86.sse.cvtss2si" => "__builtin_ia32_cvtss2si", - "llvm.x86.sse.cvtss2si64" => "__builtin_ia32_cvtss2si64", - "llvm.x86.sse.cvttss2si" => "__builtin_ia32_cvttss2si", - "llvm.x86.sse.cvttss2si64" => "__builtin_ia32_cvttss2si64", - "llvm.x86.sse.div.ss" => "__builtin_ia32_divss", - "llvm.x86.sse.max.ps" => "__builtin_ia32_maxps", - "llvm.x86.sse.max.ss" => "__builtin_ia32_maxss", - "llvm.x86.sse.min.ps" => "__builtin_ia32_minps", - "llvm.x86.sse.min.ss" => "__builtin_ia32_minss", - "llvm.x86.sse.movmsk.ps" => "__builtin_ia32_movmskps", - "llvm.x86.sse.mul.ss" => "__builtin_ia32_mulss", - "llvm.x86.sse.rcp.ps" => "__builtin_ia32_rcpps", - "llvm.x86.sse.rcp.ss" => "__builtin_ia32_rcpss", - "llvm.x86.sse.rsqrt.ps" => "__builtin_ia32_rsqrtps", - "llvm.x86.sse.rsqrt.ss" => "__builtin_ia32_rsqrtss", - "llvm.x86.sse.sfence" => "__builtin_ia32_sfence", - "llvm.x86.sse.sqrt.ps" => "__builtin_ia32_sqrtps", - "llvm.x86.sse.sqrt.ss" => "__builtin_ia32_sqrtss", - "llvm.x86.sse.storeu.ps" => "__builtin_ia32_storeups", - "llvm.x86.sse.sub.ss" => "__builtin_ia32_subss", - "llvm.x86.sse.ucomieq.ss" => "__builtin_ia32_ucomieq", - "llvm.x86.sse.ucomige.ss" => "__builtin_ia32_ucomige", - "llvm.x86.sse.ucomigt.ss" => "__builtin_ia32_ucomigt", - "llvm.x86.sse.ucomile.ss" => "__builtin_ia32_ucomile", - "llvm.x86.sse.ucomilt.ss" => "__builtin_ia32_ucomilt", - "llvm.x86.sse.ucomineq.ss" => "__builtin_ia32_ucomineq", - "llvm.x86.sse2.add.sd" => "__builtin_ia32_addsd", "llvm.x86.sse2.clflush" => "__builtin_ia32_clflush", - "llvm.x86.sse2.cmp.pd" => "__builtin_ia32_cmppd", "llvm.x86.sse2.cmp.sd" => "__builtin_ia32_cmpsd", "llvm.x86.sse2.comieq.sd" => "__builtin_ia32_comisdeq", "llvm.x86.sse2.comige.sd" => "__builtin_ia32_comisdge", @@ -9357,23 +7900,16 @@ match name { "llvm.x86.sse2.comile.sd" => "__builtin_ia32_comisdle", "llvm.x86.sse2.comilt.sd" => "__builtin_ia32_comisdlt", "llvm.x86.sse2.comineq.sd" => "__builtin_ia32_comisdneq", - "llvm.x86.sse2.cvtdq2pd" => "__builtin_ia32_cvtdq2pd", - "llvm.x86.sse2.cvtdq2ps" => "__builtin_ia32_cvtdq2ps", "llvm.x86.sse2.cvtpd2dq" => "__builtin_ia32_cvtpd2dq", "llvm.x86.sse2.cvtpd2ps" => "__builtin_ia32_cvtpd2ps", "llvm.x86.sse2.cvtps2dq" => "__builtin_ia32_cvtps2dq", - "llvm.x86.sse2.cvtps2pd" => "__builtin_ia32_cvtps2pd", "llvm.x86.sse2.cvtsd2si" => "__builtin_ia32_cvtsd2si", "llvm.x86.sse2.cvtsd2si64" => "__builtin_ia32_cvtsd2si64", "llvm.x86.sse2.cvtsd2ss" => "__builtin_ia32_cvtsd2ss", - "llvm.x86.sse2.cvtsi2sd" => "__builtin_ia32_cvtsi2sd", - "llvm.x86.sse2.cvtsi642sd" => "__builtin_ia32_cvtsi642sd", - "llvm.x86.sse2.cvtss2sd" => "__builtin_ia32_cvtss2sd", "llvm.x86.sse2.cvttpd2dq" => "__builtin_ia32_cvttpd2dq", "llvm.x86.sse2.cvttps2dq" => "__builtin_ia32_cvttps2dq", "llvm.x86.sse2.cvttsd2si" => "__builtin_ia32_cvttsd2si", "llvm.x86.sse2.cvttsd2si64" => "__builtin_ia32_cvttsd2si64", - "llvm.x86.sse2.div.sd" => "__builtin_ia32_divsd", "llvm.x86.sse2.lfence" => "__builtin_ia32_lfence", "llvm.x86.sse2.maskmov.dqu" => "__builtin_ia32_maskmovdqu", "llvm.x86.sse2.max.pd" => "__builtin_ia32_maxpd", @@ -9382,33 +7918,18 @@ match name { "llvm.x86.sse2.min.pd" => "__builtin_ia32_minpd", "llvm.x86.sse2.min.sd" => "__builtin_ia32_minsd", "llvm.x86.sse2.movmsk.pd" => "__builtin_ia32_movmskpd", - "llvm.x86.sse2.mul.sd" => "__builtin_ia32_mulsd", "llvm.x86.sse2.packssdw.128" => "__builtin_ia32_packssdw128", "llvm.x86.sse2.packsswb.128" => "__builtin_ia32_packsswb128", "llvm.x86.sse2.packuswb.128" => "__builtin_ia32_packuswb128", - "llvm.x86.sse2.padds.b" => "__builtin_ia32_paddsb128", - "llvm.x86.sse2.padds.w" => "__builtin_ia32_paddsw128", - "llvm.x86.sse2.paddus.b" => "__builtin_ia32_paddusb128", - "llvm.x86.sse2.paddus.w" => "__builtin_ia32_paddusw128", "llvm.x86.sse2.pause" => "__builtin_ia32_pause", "llvm.x86.sse2.pavg.b" => "__builtin_ia32_pavgb128", "llvm.x86.sse2.pavg.w" => "__builtin_ia32_pavgw128", "llvm.x86.sse2.pmadd.wd" => "__builtin_ia32_pmaddwd128", - "llvm.x86.sse2.pmaxs.w" => "__builtin_ia32_pmaxsw128", - "llvm.x86.sse2.pmaxu.b" => "__builtin_ia32_pmaxub128", - "llvm.x86.sse2.pmins.w" => "__builtin_ia32_pminsw128", - "llvm.x86.sse2.pminu.b" => "__builtin_ia32_pminub128", "llvm.x86.sse2.pmovmskb.128" => "__builtin_ia32_pmovmskb128", "llvm.x86.sse2.pmulh.w" => "__builtin_ia32_pmulhw128", "llvm.x86.sse2.pmulhu.w" => "__builtin_ia32_pmulhuw128", - "llvm.x86.sse2.pmulu.dq" => "__builtin_ia32_pmuludq128", "llvm.x86.sse2.psad.bw" => "__builtin_ia32_psadbw128", - "llvm.x86.sse2.pshuf.d" => "__builtin_ia32_pshufd", - "llvm.x86.sse2.pshufh.w" => "__builtin_ia32_pshufhw", - "llvm.x86.sse2.pshufl.w" => "__builtin_ia32_pshuflw", "llvm.x86.sse2.psll.d" => "__builtin_ia32_pslld128", - "llvm.x86.sse2.psll.dq" => "__builtin_ia32_pslldqi128", - "llvm.x86.sse2.psll.dq.bs" => "__builtin_ia32_pslldqi128_byteshift", "llvm.x86.sse2.psll.q" => "__builtin_ia32_psllq128", "llvm.x86.sse2.psll.w" => "__builtin_ia32_psllw128", "llvm.x86.sse2.pslli.d" => "__builtin_ia32_pslldi128", @@ -9419,23 +7940,11 @@ match name { "llvm.x86.sse2.psrai.d" => "__builtin_ia32_psradi128", "llvm.x86.sse2.psrai.w" => "__builtin_ia32_psrawi128", "llvm.x86.sse2.psrl.d" => "__builtin_ia32_psrld128", - "llvm.x86.sse2.psrl.dq" => "__builtin_ia32_psrldqi128", - "llvm.x86.sse2.psrl.dq.bs" => "__builtin_ia32_psrldqi128_byteshift", "llvm.x86.sse2.psrl.q" => "__builtin_ia32_psrlq128", "llvm.x86.sse2.psrl.w" => "__builtin_ia32_psrlw128", "llvm.x86.sse2.psrli.d" => "__builtin_ia32_psrldi128", "llvm.x86.sse2.psrli.q" => "__builtin_ia32_psrlqi128", "llvm.x86.sse2.psrli.w" => "__builtin_ia32_psrlwi128", - "llvm.x86.sse2.psubs.b" => "__builtin_ia32_psubsb128", - "llvm.x86.sse2.psubs.w" => "__builtin_ia32_psubsw128", - "llvm.x86.sse2.psubus.b" => "__builtin_ia32_psubusb128", - "llvm.x86.sse2.psubus.w" => "__builtin_ia32_psubusw128", - "llvm.x86.sse2.sqrt.pd" => "__builtin_ia32_sqrtpd", - "llvm.x86.sse2.sqrt.sd" => "__builtin_ia32_sqrtsd", - "llvm.x86.sse2.storel.dq" => "__builtin_ia32_storelv4si", - "llvm.x86.sse2.storeu.dq" => "__builtin_ia32_storedqu", - "llvm.x86.sse2.storeu.pd" => "__builtin_ia32_storeupd", - "llvm.x86.sse2.sub.sd" => "__builtin_ia32_subsd", "llvm.x86.sse2.ucomieq.sd" => "__builtin_ia32_ucomisdeq", "llvm.x86.sse2.ucomige.sd" => "__builtin_ia32_ucomisdge", "llvm.x86.sse2.ucomigt.sd" => "__builtin_ia32_ucomisdgt", @@ -9451,41 +7960,15 @@ match name { "llvm.x86.sse3.ldu.dq" => "__builtin_ia32_lddqu", "llvm.x86.sse3.monitor" => "__builtin_ia32_monitor", "llvm.x86.sse3.mwait" => "__builtin_ia32_mwait", - "llvm.x86.sse41.blendpd" => "__builtin_ia32_blendpd", - "llvm.x86.sse41.blendps" => "__builtin_ia32_blendps", "llvm.x86.sse41.blendvpd" => "__builtin_ia32_blendvpd", "llvm.x86.sse41.blendvps" => "__builtin_ia32_blendvps", "llvm.x86.sse41.dppd" => "__builtin_ia32_dppd", "llvm.x86.sse41.dpps" => "__builtin_ia32_dpps", - "llvm.x86.sse41.extractps" => "__builtin_ia32_extractps128", "llvm.x86.sse41.insertps" => "__builtin_ia32_insertps128", - "llvm.x86.sse41.movntdqa" => "__builtin_ia32_movntdqa", "llvm.x86.sse41.mpsadbw" => "__builtin_ia32_mpsadbw128", "llvm.x86.sse41.packusdw" => "__builtin_ia32_packusdw128", "llvm.x86.sse41.pblendvb" => "__builtin_ia32_pblendvb128", - "llvm.x86.sse41.pblendw" => "__builtin_ia32_pblendw128", "llvm.x86.sse41.phminposuw" => "__builtin_ia32_phminposuw128", - "llvm.x86.sse41.pmaxsb" => "__builtin_ia32_pmaxsb128", - "llvm.x86.sse41.pmaxsd" => "__builtin_ia32_pmaxsd128", - "llvm.x86.sse41.pmaxud" => "__builtin_ia32_pmaxud128", - "llvm.x86.sse41.pmaxuw" => "__builtin_ia32_pmaxuw128", - "llvm.x86.sse41.pminsb" => "__builtin_ia32_pminsb128", - "llvm.x86.sse41.pminsd" => "__builtin_ia32_pminsd128", - "llvm.x86.sse41.pminud" => "__builtin_ia32_pminud128", - "llvm.x86.sse41.pminuw" => "__builtin_ia32_pminuw128", - "llvm.x86.sse41.pmovsxbd" => "__builtin_ia32_pmovsxbd128", - "llvm.x86.sse41.pmovsxbq" => "__builtin_ia32_pmovsxbq128", - "llvm.x86.sse41.pmovsxbw" => "__builtin_ia32_pmovsxbw128", - "llvm.x86.sse41.pmovsxdq" => "__builtin_ia32_pmovsxdq128", - "llvm.x86.sse41.pmovsxwd" => "__builtin_ia32_pmovsxwd128", - "llvm.x86.sse41.pmovsxwq" => "__builtin_ia32_pmovsxwq128", - "llvm.x86.sse41.pmovzxbd" => "__builtin_ia32_pmovzxbd128", - "llvm.x86.sse41.pmovzxbq" => "__builtin_ia32_pmovzxbq128", - "llvm.x86.sse41.pmovzxbw" => "__builtin_ia32_pmovzxbw128", - "llvm.x86.sse41.pmovzxdq" => "__builtin_ia32_pmovzxdq128", - "llvm.x86.sse41.pmovzxwd" => "__builtin_ia32_pmovzxwd128", - "llvm.x86.sse41.pmovzxwq" => "__builtin_ia32_pmovzxwq128", - "llvm.x86.sse41.pmuldq" => "__builtin_ia32_pmuldq128", "llvm.x86.sse41.ptestc" => "__builtin_ia32_ptestc128", "llvm.x86.sse41.ptestnzc" => "__builtin_ia32_ptestnzc128", "llvm.x86.sse41.ptestz" => "__builtin_ia32_ptestz128", @@ -9515,27 +7998,69 @@ match name { "llvm.x86.sse4a.extrqi" => "__builtin_ia32_extrqi", "llvm.x86.sse4a.insertq" => "__builtin_ia32_insertq", "llvm.x86.sse4a.insertqi" => "__builtin_ia32_insertqi", - "llvm.x86.sse4a.movnt.sd" => "__builtin_ia32_movntsd", - "llvm.x86.sse4a.movnt.ss" => "__builtin_ia32_movntss", - "llvm.x86.ssse3.pabs.b.128" => "__builtin_ia32_pabsb128", - "llvm.x86.ssse3.pabs.d.128" => "__builtin_ia32_pabsd128", - "llvm.x86.ssse3.pabs.w.128" => "__builtin_ia32_pabsw128", + "llvm.x86.sse.cmp.ss" => "__builtin_ia32_cmpss", + "llvm.x86.sse.comieq.ss" => "__builtin_ia32_comieq", + "llvm.x86.sse.comige.ss" => "__builtin_ia32_comige", + "llvm.x86.sse.comigt.ss" => "__builtin_ia32_comigt", + "llvm.x86.sse.comile.ss" => "__builtin_ia32_comile", + "llvm.x86.sse.comilt.ss" => "__builtin_ia32_comilt", + "llvm.x86.sse.comineq.ss" => "__builtin_ia32_comineq", + "llvm.x86.sse.cvtpd2pi" => "__builtin_ia32_cvtpd2pi", + "llvm.x86.sse.cvtpi2pd" => "__builtin_ia32_cvtpi2pd", + "llvm.x86.sse.cvtpi2ps" => "__builtin_ia32_cvtpi2ps", + "llvm.x86.sse.cvtps2pi" => "__builtin_ia32_cvtps2pi", + "llvm.x86.sse.cvtss2si" => "__builtin_ia32_cvtss2si", + "llvm.x86.sse.cvtss2si64" => "__builtin_ia32_cvtss2si64", + "llvm.x86.sse.cvttpd2pi" => "__builtin_ia32_cvttpd2pi", + "llvm.x86.sse.cvttps2pi" => "__builtin_ia32_cvttps2pi", + "llvm.x86.sse.cvttss2si" => "__builtin_ia32_cvttss2si", + "llvm.x86.sse.cvttss2si64" => "__builtin_ia32_cvttss2si64", + "llvm.x86.sse.max.ps" => "__builtin_ia32_maxps", + "llvm.x86.sse.max.ss" => "__builtin_ia32_maxss", + "llvm.x86.sse.min.ps" => "__builtin_ia32_minps", + "llvm.x86.sse.min.ss" => "__builtin_ia32_minss", + "llvm.x86.sse.movmsk.ps" => "__builtin_ia32_movmskps", + "llvm.x86.sse.pshuf.w" => "__builtin_ia32_pshufw", + "llvm.x86.sse.rcp.ps" => "__builtin_ia32_rcpps", + "llvm.x86.sse.rcp.ss" => "__builtin_ia32_rcpss", + "llvm.x86.sse.rsqrt.ps" => "__builtin_ia32_rsqrtps", + "llvm.x86.sse.rsqrt.ss" => "__builtin_ia32_rsqrtss", + "llvm.x86.sse.sfence" => "__builtin_ia32_sfence", + "llvm.x86.sse.ucomieq.ss" => "__builtin_ia32_ucomieq", + "llvm.x86.sse.ucomige.ss" => "__builtin_ia32_ucomige", + "llvm.x86.sse.ucomigt.ss" => "__builtin_ia32_ucomigt", + "llvm.x86.sse.ucomile.ss" => "__builtin_ia32_ucomile", + "llvm.x86.sse.ucomilt.ss" => "__builtin_ia32_ucomilt", + "llvm.x86.sse.ucomineq.ss" => "__builtin_ia32_ucomineq", + "llvm.x86.ssse3.pabs.b" => "__builtin_ia32_pabsb", + "llvm.x86.ssse3.pabs.d" => "__builtin_ia32_pabsd", + "llvm.x86.ssse3.pabs.w" => "__builtin_ia32_pabsw", + "llvm.x86.ssse3.phadd.d" => "__builtin_ia32_phaddd", "llvm.x86.ssse3.phadd.d.128" => "__builtin_ia32_phaddd128", + "llvm.x86.ssse3.phadd.sw" => "__builtin_ia32_phaddsw", "llvm.x86.ssse3.phadd.sw.128" => "__builtin_ia32_phaddsw128", + "llvm.x86.ssse3.phadd.w" => "__builtin_ia32_phaddw", "llvm.x86.ssse3.phadd.w.128" => "__builtin_ia32_phaddw128", + "llvm.x86.ssse3.phsub.d" => "__builtin_ia32_phsubd", "llvm.x86.ssse3.phsub.d.128" => "__builtin_ia32_phsubd128", + "llvm.x86.ssse3.phsub.sw" => "__builtin_ia32_phsubsw", "llvm.x86.ssse3.phsub.sw.128" => "__builtin_ia32_phsubsw128", + "llvm.x86.ssse3.phsub.w" => "__builtin_ia32_phsubw", "llvm.x86.ssse3.phsub.w.128" => "__builtin_ia32_phsubw128", + "llvm.x86.ssse3.pmadd.ub.sw" => "__builtin_ia32_pmaddubsw", "llvm.x86.ssse3.pmadd.ub.sw.128" => "__builtin_ia32_pmaddubsw128", + "llvm.x86.ssse3.pmul.hr.sw" => "__builtin_ia32_pmulhrsw", "llvm.x86.ssse3.pmul.hr.sw.128" => "__builtin_ia32_pmulhrsw128", + "llvm.x86.ssse3.pshuf.b" => "__builtin_ia32_pshufb", "llvm.x86.ssse3.pshuf.b.128" => "__builtin_ia32_pshufb128", + "llvm.x86.ssse3.psign.b" => "__builtin_ia32_psignb", "llvm.x86.ssse3.psign.b.128" => "__builtin_ia32_psignb128", + "llvm.x86.ssse3.psign.d" => "__builtin_ia32_psignd", "llvm.x86.ssse3.psign.d.128" => "__builtin_ia32_psignd128", + "llvm.x86.ssse3.psign.w" => "__builtin_ia32_psignw", "llvm.x86.ssse3.psign.w.128" => "__builtin_ia32_psignw128", "llvm.x86.sttilecfg" => "__builtin_ia32_tile_storeconfig", "llvm.x86.stui" => "__builtin_ia32_stui", - "llvm.x86.subborrow.u32" => "__builtin_ia32_subborrow_u32", - "llvm.x86.subborrow.u64" => "__builtin_ia32_subborrow_u64", "llvm.x86.tbm.bextri.u32" => "__builtin_ia32_bextri_u32", "llvm.x86.tbm.bextri.u64" => "__builtin_ia32_bextri_u64", "llvm.x86.tcmmimfp16ps" => "__builtin_ia32_tcmmimfp16ps", @@ -9583,8 +8108,6 @@ match name { "llvm.x86.vcvtneoph2ps256" => "__builtin_ia32_vcvtneoph2ps256", "llvm.x86.vcvtneps2bf16128" => "__builtin_ia32_vcvtneps2bf16128", "llvm.x86.vcvtneps2bf16256" => "__builtin_ia32_vcvtneps2bf16256", - "llvm.x86.vcvtph2ps.128" => "__builtin_ia32_vcvtph2ps", - "llvm.x86.vcvtph2ps.256" => "__builtin_ia32_vcvtph2ps256", "llvm.x86.vcvtps2ph.128" => "__builtin_ia32_vcvtps2ph", "llvm.x86.vcvtps2ph.256" => "__builtin_ia32_vcvtps2ph256", "llvm.x86.vgf2p8affineinvqb.128" => "__builtin_ia32_vgf2p8affineinvqb_v16qi", @@ -9626,16 +8149,6 @@ match name { "llvm.x86.xop.vfrcz.ps.256" => "__builtin_ia32_vfrczps256", "llvm.x86.xop.vfrcz.sd" => "__builtin_ia32_vfrczsd", "llvm.x86.xop.vfrcz.ss" => "__builtin_ia32_vfrczss", - "llvm.x86.xop.vpcmov" => "__builtin_ia32_vpcmov", - "llvm.x86.xop.vpcmov.256" => "__builtin_ia32_vpcmov_256", - "llvm.x86.xop.vpcomb" => "__builtin_ia32_vpcomb", - "llvm.x86.xop.vpcomd" => "__builtin_ia32_vpcomd", - "llvm.x86.xop.vpcomq" => "__builtin_ia32_vpcomq", - "llvm.x86.xop.vpcomub" => "__builtin_ia32_vpcomub", - "llvm.x86.xop.vpcomud" => "__builtin_ia32_vpcomud", - "llvm.x86.xop.vpcomuq" => "__builtin_ia32_vpcomuq", - "llvm.x86.xop.vpcomuw" => "__builtin_ia32_vpcomuw", - "llvm.x86.xop.vpcomw" => "__builtin_ia32_vpcomw", "llvm.x86.xop.vpermil2pd" => "__builtin_ia32_vpermil2pd", "llvm.x86.xop.vpermil2pd.256" => "__builtin_ia32_vpermil2pd256", "llvm.x86.xop.vpermil2ps" => "__builtin_ia32_vpermil2ps", @@ -9668,14 +8181,6 @@ match name { "llvm.x86.xop.vpmadcsswd" => "__builtin_ia32_vpmadcsswd", "llvm.x86.xop.vpmadcswd" => "__builtin_ia32_vpmadcswd", "llvm.x86.xop.vpperm" => "__builtin_ia32_vpperm", - "llvm.x86.xop.vprotb" => "__builtin_ia32_vprotb", - "llvm.x86.xop.vprotbi" => "__builtin_ia32_vprotbi", - "llvm.x86.xop.vprotd" => "__builtin_ia32_vprotd", - "llvm.x86.xop.vprotdi" => "__builtin_ia32_vprotdi", - "llvm.x86.xop.vprotq" => "__builtin_ia32_vprotq", - "llvm.x86.xop.vprotqi" => "__builtin_ia32_vprotqi", - "llvm.x86.xop.vprotw" => "__builtin_ia32_vprotw", - "llvm.x86.xop.vprotwi" => "__builtin_ia32_vprotwi", "llvm.x86.xop.vpshab" => "__builtin_ia32_vpshab", "llvm.x86.xop.vpshad" => "__builtin_ia32_vpshad", "llvm.x86.xop.vpshaq" => "__builtin_ia32_vpshaq",