SpiceModel_TLV9052.mod

* TLV9052 - Rev. C
* Created by Paul Goedeke, Bala Ravi; May 22, 2019
* Created with Green-Williams-Lis Op Amp Macro-model Architecture
* Copyright 2019 by Texas Instruments Corporation
******************************************************
* MACRO-MODEL SIMULATED PARAMETERS:
******************************************************
* OPEN-LOOP GAIN AND PHASE VS. FREQUENCY  WITH RL, CL EFFECTS (Aol)
* UNITY GAIN BANDWIDTH (GBW)
* INPUT COMMON-MODE REJECTION RATIO VS. FREQUENCY (CMRR)
* POWER SUPPLY REJECTION RATIO VS. FREQUENCY (PSRR)
* DIFFERENTIAL INPUT IMPEDANCE (Zid)
* COMMON-MODE INPUT IMPEDANCE (Zic)
* OPEN-LOOP OUTPUT IMPEDANCE VS. FREQUENCY (Zo)
* OUTPUT CURRENT THROUGH THE SUPPLY (Iout)
* INPUT VOLTAGE NOISE DENSITY VS. FREQUENCY (en)
* INPUT CURRENT NOISE DENSITY VS. FREQUENCY (in)
* OUTPUT VOLTAGE SWING vs. OUTPUT CURRENT (Vo)
* SHORT-CIRCUIT OUTPUT CURRENT (Isc)
* QUIESCENT CURRENT (Iq)
* SETTLING TIME VS. CAPACITIVE LOAD (ts)
* SLEW RATE (SR)
* SMALL SIGNAL OVERSHOOT VS. CAPACITIVE LOAD
* LARGE SIGNAL RESPONSE
* OVERLOAD RECOVERY TIME (tor)
* INPUT BIAS CURRENT (Ib)
* INPUT OFFSET CURRENT (Ios)
* INPUT OFFSET VOLTAGE (Vos)
* INPUT COMMON-MODE VOLTAGE RANGE (Vcm)
* INPUT OFFSET VOLTAGE VS. INPUT COMMON-MODE VOLTAGE (Vos vs. Vcm)
* INPUT/OUTPUT ESD CELLS (ESDin, ESDout)
******************************************************
.subckt TLV9052 IN+ IN- VCC VEE OUT
******************************************************
* MODEL DEFINITIONS:
.model BB_SW VSWITCH(Ron=50 Roff=1e12 Von=700e-3 Voff=0)
.model ESD_SW VSWITCH(Ron=50 Roff=1e12 Von=250e-3 Voff=0)
.model OL_SW VSWITCH(Ron=1e-3 Roff=1e9 Von=900e-3 Voff=800e-3)
.model OR_SW VSWITCH(Ron=10e-3 Roff=1e9 Von=1e-3 Voff=0)
.model R_NOISELESS RES(T_ABS=-273.15)
******************************************************


I_OS        ESDn MID 1P
I_B         30 MID 2P
V_GRp       59 MID 310
V_GRn       60 MID -310
V_ISCp      53 MID 50
V_ISCn      54 MID -50
V_ORn       50 VCLP -2.6
V11         58 49 0
V_ORp       48 VCLP 2.6
V12         57 47 0
V4          42 OUT 0
VCM_MIN     79 VEE_B -100M
VCM_MAX     80 VCC_B 100M
I_Q         VCC VEE 330U
XCLAWp      VIMON MID 21 VCC_B VCCS_LIM_CLAW+_0
XCLAWn      MID VIMON VEE_B 22 VCCS_LIM_CLAW-_0
R57         MID 23 R_NOISELESS 1.25K 
C16         23 24 6.366P 
R56         24 23 R_NOISELESS 10MEG 
G_adjust    24 MID ESDp MID  -80M
Rsrc        MID 24 R_NOISELESS 1 
R55         MID 25 R_NOISELESS 44.44 
C14         25 26 530.5P 
R49         26 25 R_NOISELESS 10MEG 
GVCCS3      26 MID VCC_B MID  -711.5M
R48         MID 26 R_NOISELESS 1 
R54         MID 27 R_NOISELESS 20 
C15         27 28 397.9P 
R51         28 27 R_NOISELESS 10MEG 
GVCCS1      28 MID VEE_B MID  -1.581
R50         MID 28 R_NOISELESS 1 
XU1         29 30 VOS_DRIFT_0
XVCCS_LIM_2 31 MID MID CLAMP VCCS_LIM_2_0
XVOS_VCM    32 29 VCC VEE VOS_SRC_0
C25         33 MID 13F  
C20         CLAMP MID 115N  
R94         34 MID R_NOISELESS 1 
XZo         35 MID MID 34 VCCS_LIM_ZO_0
R93         35 MID R_NOISELESS 1.111K 
C33         35 36 1.59F  
R92         35 36 R_NOISELESS 10K 
R91         36 MID R_NOISELESS 1 
GVCCS12     36 MID 37 MID  -1
C32         38 MID 15.92F  
R90         37 38 R_NOISELESS 10K 
R87         37 39 R_NOISELESS 40K 
R86         39 MID R_NOISELESS 1 
GVCCS11     39 MID 40 MID  -18
C31         41 40 15.92U  
R85         40 MID R_NOISELESS 588.2 
R84         40 41 R_NOISELESS 10K 
Rdummy      MID 42 R_NOISELESS 40K 
Rx          42 34 R_NOISELESS 400K 
R81         41 MID R_NOISELESS 1 
GVCCS10     41 MID CL_CLAMP 42  -89
Xe_n        ESDp 30 VNSE_0
S5          VEE ESDp VEE ESDp  S_VSWITCH_1
S4          VEE ESDn VEE ESDn  S_VSWITCH_2
S2          ESDn VCC ESDn VCC  S_VSWITCH_3
S3          ESDp VCC ESDp VCC  S_VSWITCH_4
C28         43 MID 1P 
R77         44 43 R_NOISELESS 100 
C27         45 MID 1P 
R76         46 45 R_NOISELESS 100 
R75         MID 47 R_NOISELESS 1 
GVCCS8      47 MID 48 MID  -1
R74         49 MID R_NOISELESS 1 
GVCCS7      49 MID 50 MID  -1
Xi_nn       ESDn MID FEMT_0
Xi_np       MID 30 FEMT_0
R69         MID 33 R_NOISELESS 1MEG 
GVCCS6      33 MID VSENSE MID  -1U
R68         MID CLAMP R_NOISELESS 1MEG 
R44         MID 31 R_NOISELESS 1MEG 
XVCCS_LIM_1 51 52 MID 31 VCCS_LIM_1_0
XIQp        VIMON MID MID VCC VCCS_LIMIT_IQ_0
XIQn        MID VIMON VEE MID VCCS_LIMIT_IQ_0
C_DIFF      ESDp ESDn 2P 
XCL_AMP     53 54 VIMON MID 55 56 CLAMP_AMP_LO_0
SOR_SWp     CLAMP 57 CLAMP 57  S_VSWITCH_5
SOR_SWn     58 CLAMP 58 CLAMP  S_VSWITCH_6
XGR_AMP     59 60 61 MID 62 63 CLAMP_AMP_HI_0
R39         59 MID R_NOISELESS 1T 
R37         60 MID R_NOISELESS 1T 
R42         VSENSE 61 R_NOISELESS 1M 
C19         61 MID 1F 
R38         62 MID R_NOISELESS 1 
R36         MID 63 R_NOISELESS 1 
R40         62 64 R_NOISELESS 1M 
R41         63 65 R_NOISELESS 1M 
C17         64 MID 1F 
C18         MID 65 1F 
XGR_SRC     64 65 CLAMP MID VCCS_LIM_GR_0
R21         55 MID R_NOISELESS 1 
R20         MID 56 R_NOISELESS 1 
R29         55 66 R_NOISELESS 1M 
R30         56 67 R_NOISELESS 1M 
C9          66 MID 1F 
C8          MID 67 1F 
XCL_SRC     66 67 CL_CLAMP MID VCCS_LIM_4_0
R22         53 MID R_NOISELESS 1T 
R19         MID 54 R_NOISELESS 1T 
R12         21 VCC_B R_NOISELESS 1K 
R16         21 68 R_NOISELESS 1M 
R13         VEE_B 22 R_NOISELESS 1K 
R17         69 22 R_NOISELESS 1M 
C6          69 MID 1F 
C5          MID 68 1F 
G2          VCC_CLP MID 68 MID  -1M
R15         VCC_CLP MID R_NOISELESS 1K 
G3          VEE_CLP MID 69 MID  -1M
R14         MID VEE_CLP R_NOISELESS 1K 
XCLAW_AMP   VCC_CLP VEE_CLP VOUT_S MID 70 71 CLAMP_AMP_LO_0
R26         VCC_CLP MID R_NOISELESS 1T 
R23         VEE_CLP MID R_NOISELESS 1T 
R25         70 MID R_NOISELESS 1 
R24         MID 71 R_NOISELESS 1 
R27         70 72 R_NOISELESS 1M 
R28         71 73 R_NOISELESS 1M 
C11         72 MID 1F 
C10         MID 73 1F 
XCLAW_SRC   72 73 CLAW_CLAMP MID VCCS_LIM_3_0
H2          46 MID V11 -1
H3          44 MID V12 1
C12         SW_OL MID 100P 
R32         74 SW_OL R_NOISELESS 100 
R31         74 MID R_NOISELESS 1 
XOL_SENSE   MID 74 45 43 OL_SENSE_0
S1          41 40 SW_OL MID  S_VSWITCH_7
H1          75 MID V4 1K
S7          VEE OUT VEE OUT  S_VSWITCH_8
S6          OUT VCC OUT VCC  S_VSWITCH_9
R11         MID 76 R_NOISELESS 1T 
R18         76 VOUT_S R_NOISELESS 100 
C7          VOUT_S MID 1P 
E5          76 MID OUT MID  1
C13         VIMON MID 100P 
R33         75 VIMON R_NOISELESS 100 
R10         MID 75 R_NOISELESS 1T 
R47         77 VCLP R_NOISELESS 100 
C24         VCLP MID 100P 
E4          77 MID CL_CLAMP MID  1
R46         MID CL_CLAMP R_NOISELESS 1K 
G9          CL_CLAMP MID CLAW_CLAMP MID  -1M
R45         MID CLAW_CLAMP R_NOISELESS 1K 
G8          CLAW_CLAMP MID 33 MID  -1M
R43         MID VSENSE R_NOISELESS 1K 
G15         VSENSE MID CLAMP MID  -1M
C4          51 MID 1F 
R9          51 78 R_NOISELESS 1M 
R7          MID 79 R_NOISELESS 1T 
R6          80 MID R_NOISELESS 1T 
R8          MID 78 R_NOISELESS 1 
XVCM_CLAMP  81 MID 78 MID 80 79 VCCS_EXT_LIM_0
E1          MID 0 82 0  1
R89         VEE_B 0 R_NOISELESS 1 
R5          83 VEE_B R_NOISELESS 1M 
C3          83 0 1F 
R60         82 83 R_NOISELESS 1MEG 
C1          82 0 1 
R3          82 0 R_NOISELESS 1T 
R59         84 82 R_NOISELESS 1MEG 
C2          84 0 1F 
R4          VCC_B 84 R_NOISELESS 1M 
R88         VCC_B 0 R_NOISELESS 1 
G17         VEE_B 0 VEE 0  -1
G16         VCC_B 0 VCC 0  -1
R_PSR       85 81 R_NOISELESS 1K 
G_PSR       81 85 25 27  -1M
R2          52 ESDn R_NOISELESS 1M 
R1          85 86 R_NOISELESS 1M 
R_CMR       32 86 R_NOISELESS 1K 
G_CMR       86 32 23 MID  -1M
C_CMn       ESDn MID 4P 
C_CMp       MID ESDp 4P 
R53         ESDn MID R_NOISELESS 1T 
R52         MID ESDp R_NOISELESS 1T 
R35         IN- ESDn R_NOISELESS 10M 
R34         IN+ ESDp R_NOISELESS 10M 

.MODEL S_VSWITCH_1 VSWITCH (RON=50 ROFF=1T VON=500M VOFF=450M)
.MODEL S_VSWITCH_2 VSWITCH (RON=50 ROFF=1T VON=500M VOFF=450M)
.MODEL S_VSWITCH_3 VSWITCH (RON=50 ROFF=1T VON=500M VOFF=450M)
.MODEL S_VSWITCH_4 VSWITCH (RON=50 ROFF=1T VON=500M VOFF=450M)
.MODEL S_VSWITCH_5 VSWITCH (RON=10M ROFF=1T VON=10M VOFF=0)
.MODEL S_VSWITCH_6 VSWITCH (RON=10M ROFF=1T VON=10M VOFF=0)
.MODEL S_VSWITCH_7 VSWITCH (RON=1M ROFF=1T VON=500M VOFF=100M)
.MODEL S_VSWITCH_8 VSWITCH (RON=50 ROFF=1T VON=500M VOFF=100M)
.MODEL S_VSWITCH_9 VSWITCH (RON=50 ROFF=1T VON=500M VOFF=100M)

.ENDS TLV9052
*
.SUBCKT VCCS_LIM_CLAW+_0  VC+ VC- IOUT+ IOUT-
G1 IOUT+ IOUT- TABLE {ABS(V(VC+,VC-))} =
+(00, 2.00E-5)
+(02, 3.00E-5)
+(05, 9.00E-5)
+(10, 1.80E-4)
+(15, 2.80E-4)
+(20, 3.80E-4)
+(25, 5.00E-4)
+(30, 6.35E-4)
+(35, 8.00E-4)
+(40, 1.01E-3)
+(42, 1.12E-3)
+(45, 1.37E-3)
+(48, 2.00E-3)
.ENDS
*


.SUBCKT VCCS_LIM_CLAW-_0  VC+ VC- IOUT+ IOUT-
G1 IOUT+ IOUT- TABLE {ABS(V(VC+,VC-))} =
+(00, 2.00E-5)
+(02, 3.00E-5)
+(05, 7.50E-5)
+(10, 1.55E-4)
+(15, 2.35E-4)
+(20, 3.30E-4)
+(25, 4.30E-4)
+(30, 5.40E-4)
+(35, 6.75E-4)
+(40, 8.55E-4)
+(42, 9.50E-4)
+(45, 1.18E-3)
+(47, 1.53E-3)
+(48, 2.24E-3)
.ENDS
*


.SUBCKT VOS_DRIFT_0  VOS+ VOS-
.PARAM DC = 3.1261E-4
.PARAM POL = -1
.PARAM DRIFT = 0.5E-6
E1 VOS+ VOS- VALUE={DC+POL*DRIFT*(TEMP-27)}
.ENDS
*


.SUBCKT VCCS_LIM_2_0  VC+ VC- IOUT+ IOUT-
.PARAM GAIN = 3.969E-2
.PARAM IPOS = 2.8
.PARAM INEG = -2.8
G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}
.ENDS
*


.SUBCKT VOS_SRC_0  V+ V- REF+ REF-
E1 V+ 1 TABLE {(V(REF+, V-))} =
+(0, 0.0003)
+(1, 0.0003)
+(1.3, 0)
+(5.5, 0)
E2 1 V- TABLE {(V(V-, REF-))}=
+(-0.7, -2E-4)
+(-0.5, -2E-4)
+(-0.4, 0)
+(5.5, 0)
.ENDS VOS_SRC_0 
*


.SUBCKT VCCS_LIM_ZO_0  VC+ VC- IOUT+ IOUT-
.PARAM GAIN = 10
.PARAM IPOS = 45K
.PARAM INEG = -45K
G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}
.ENDS
*


.SUBCKT VNSE_0  1 2
.PARAM FLW= 10
.PARAM NLF= 116
.PARAM NVR=12.5
.PARAM GLF={PWR(FLW,0.25)*NLF/1164}
.PARAM RNV={1.184*PWR(NVR,2)}
.MODEL DVN D KF={PWR(FLW,0.5)/1E11} IS=1.0E-16
I1 0 7 10E-3
I2 0 8 10E-3
D1 7 0 DVN
D2 8 0 DVN
E1 3 6 7 8 {GLF}
R1 3 0 1E9
R2 3 0 1E9
R3 3 6 1E9
E2 6 4 5 0 10
R4 5 0 {RNV}
R5 5 0 {RNV}
R6 3 4 1E9
R7 4 0 1E9
E3 1 2 3 4 1
.ENDS
*


.SUBCKT FEMT_0  1 2
.PARAM FLWF=1E-3
.PARAM NLFF=18
.PARAM NVRF=18
.PARAM GLFF={PWR(FLWF,0.25)*NLFF/1164}
.PARAM RNVF={1.184*PWR(NVRF,2)}
.MODEL DVNF D KF={PWR(FLWF,0.5)/1E11} IS=1.0E-16
I1 0 7 10E-3
I2 0 8 10E-3
D1 7 0 DVNF
D2 8 0 DVNF
E1 3 6 7 8 {GLFF}
R1 3 0 1E9
R2 3 0 1E9
R3 3 6 1E9
E2 6 4 5 0 10
R4 5 0 {RNVF}
R5 5 0 {RNVF}
R6 3 4 1E9
R7 4 0 1E9
G1 1 2 3 4 1E-6
.ENDS
*


.SUBCKT VCCS_LIM_1_0  VC+ VC- IOUT+ IOUT-
.PARAM GAIN = 1E-4
.PARAM IPOS = .5
.PARAM INEG = -.5
G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}
.ENDS
*


.SUBCKT VCCS_LIMIT_IQ_0  VC+ VC- IOUT+ IOUT-
.PARAM GAIN = 1E-3
G1 IOUT- IOUT+ VALUE={IF( (V(VC+,VC-)<=0),0,GAIN*V(VC+,VC-) )}
.ENDS
*


.SUBCKT CLAMP_AMP_LO_0  VC+ VC- VIN COM VO+ VO-
.PARAM G=1
GVO+ COM VO+ VALUE = {IF(V(VIN,COM)>V(VC+,COM),((V(VIN,COM)-V(VC+,COM))*G),0)}
GVO- COM VO- VALUE = {IF(V(VIN,COM)<V(VC-,COM),((V(VC-,COM)-V(VIN,COM))*G),0)}
.ENDS
*


.SUBCKT CLAMP_AMP_HI_0  VC+ VC- VIN COM VO+ VO-
.PARAM G=10
GVO+ COM VO+ VALUE = {IF(V(VIN,COM)>V(VC+,COM),((V(VIN,COM)-V(VC+,COM))*G),0)}
GVO- COM VO- VALUE = {IF(V(VIN,COM)<V(VC-,COM),((V(VC-,COM)-V(VIN,COM))*G),0)}
.ENDS
*


.SUBCKT VCCS_LIM_GR_0  VC+ VC- IOUT+ IOUT-
.PARAM GAIN = 1
.PARAM IPOS = 4
.PARAM INEG = -4
G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}
.ENDS
*


.SUBCKT VCCS_LIM_4_0  VC+ VC- IOUT+ IOUT-
.PARAM GAIN = 1
.PARAM IPOS = 1.8
.PARAM INEG = -1.8
G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}
.ENDS
*


.SUBCKT VCCS_LIM_3_0  VC+ VC- IOUT+ IOUT-
.PARAM GAIN = 1
.PARAM IPOS = 740E-3
.PARAM INEG = -740E-3
G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}
.ENDS
*


.SUBCKT OL_SENSE_0  COM SW+ OLN  OLP
GSW+ COM SW+ VALUE = {IF((V(OLN,COM)>10E-3 | V(OLP,COM)>10E-3),1,0)}
.ENDS
*


.SUBCKT VCCS_EXT_LIM_0  VIN+ VIN- IOUT- IOUT+ VP+ VP-
.PARAM GAIN = 1
G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VIN+,VIN-),V(VP-,VIN-), V(VP+,VIN-))}
.ENDS
*