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vivado.log
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#-----------------------------------------------------------
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Mon Apr 1 19:31:59 2019
# Process ID: 10808
# Current directory: C:/Users/Neha Jain/PRESENT_4
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent10168 C:\Users\Neha Jain\PRESENT_4\PRESENT_4.xpr
# Log file: C:/Users/Neha Jain/PRESENT_4/vivado.log
# Journal file: C:/Users/Neha Jain/PRESENT_4\vivado.jou
#-----------------------------------------------------------
start_gui
open_project {C:/Users/Neha Jain/PRESENT_4/PRESENT_4.xpr}
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/xilinks/Vivado/2018.3/data/ip'.
open_project: Time (s): cpu = 00:00:28 ; elapsed = 00:00:54 . Memory (MB): peak = 660.988 ; gain = 97.684
update_compile_order -fileset sources_1
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Neha Jain/PRESENT_4/PRESENT_4.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'simu' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Neha Jain/PRESENT_4/PRESENT_4.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj simu_vlog.prj"
run_program: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 670.500 ; gain = 0.000
INFO: [USF-XSim-69] 'compile' step finished in '8' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Neha Jain/PRESENT_4/PRESENT_4.sim/sim_1/behav/xsim'
Vivado Simulator 2018.3
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: C:/xilinks/Vivado/2018.3/bin/unwrapped/win64.o/xelab.exe -wto ad529f38f87440d79c18f3fee1d17bb9 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot simu_behav xil_defaultlib.simu xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 4 for port 'rc' [C:/Users/Neha Jain/PRESENT_4/PRESENT_4.srcs/sources_1/new/presentcipher.v:68]
WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 8 for port 'rc' [C:/Users/Neha Jain/PRESENT_4/PRESENT_4.srcs/sources_1/new/rounds.v:221]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 4 for port 'rc' [C:/Users/Neha Jain/PRESENT_4/PRESENT_4.srcs/sources_1/new/presentcipher.v:69]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 4 for port 'rc' [C:/Users/Neha Jain/PRESENT_4/PRESENT_4.srcs/sources_1/new/presentcipher.v:70]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 4 for port 'rc' [C:/Users/Neha Jain/PRESENT_4/PRESENT_4.srcs/sources_1/new/presentcipher.v:71]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 4 for port 'rc' [C:/Users/Neha Jain/PRESENT_4/PRESENT_4.srcs/sources_1/new/presentcipher.v:72]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 4 for port 'rc' [C:/Users/Neha Jain/PRESENT_4/PRESENT_4.srcs/sources_1/new/presentcipher.v:73]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 4 for port 'rc' [C:/Users/Neha Jain/PRESENT_4/PRESENT_4.srcs/sources_1/new/presentcipher.v:74]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 4 for port 'rc' [C:/Users/Neha Jain/PRESENT_4/PRESENT_4.srcs/sources_1/new/presentcipher.v:75]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 4 for port 'rc' [C:/Users/Neha Jain/PRESENT_4/PRESENT_4.srcs/sources_1/new/presentcipher.v:76]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 4 for port 'rc' [C:/Users/Neha Jain/PRESENT_4/PRESENT_4.srcs/sources_1/new/presentcipher.v:77]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 4 for port 'rc' [C:/Users/Neha Jain/PRESENT_4/PRESENT_4.srcs/sources_1/new/presentcipher.v:78]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 4 for port 'rc' [C:/Users/Neha Jain/PRESENT_4/PRESENT_4.srcs/sources_1/new/presentcipher.v:79]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 4 for port 'rc' [C:/Users/Neha Jain/PRESENT_4/PRESENT_4.srcs/sources_1/new/presentcipher.v:80]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 4 for port 'rc' [C:/Users/Neha Jain/PRESENT_4/PRESENT_4.srcs/sources_1/new/presentcipher.v:81]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 4 for port 'rc' [C:/Users/Neha Jain/PRESENT_4/PRESENT_4.srcs/sources_1/new/presentcipher.v:82]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 4 for port 'rc' [C:/Users/Neha Jain/PRESENT_4/PRESENT_4.srcs/sources_1/new/presentcipher.v:83]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 4 for port 'rc' [C:/Users/Neha Jain/PRESENT_4/PRESENT_4.srcs/sources_1/new/presentcipher.v:84]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 4 for port 'rc' [C:/Users/Neha Jain/PRESENT_4/PRESENT_4.srcs/sources_1/new/presentcipher.v:85]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 4 for port 'rc' [C:/Users/Neha Jain/PRESENT_4/PRESENT_4.srcs/sources_1/new/presentcipher.v:86]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 4 for port 'rc' [C:/Users/Neha Jain/PRESENT_4/PRESENT_4.srcs/sources_1/new/presentcipher.v:87]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 4 for port 'rc' [C:/Users/Neha Jain/PRESENT_4/PRESENT_4.srcs/sources_1/new/presentcipher.v:88]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 4 for port 'rc' [C:/Users/Neha Jain/PRESENT_4/PRESENT_4.srcs/sources_1/new/presentcipher.v:89]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 4 for port 'rc' [C:/Users/Neha Jain/PRESENT_4/PRESENT_4.srcs/sources_1/new/presentcipher.v:90]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 4 for port 'rc' [C:/Users/Neha Jain/PRESENT_4/PRESENT_4.srcs/sources_1/new/presentcipher.v:91]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 4 for port 'rc' [C:/Users/Neha Jain/PRESENT_4/PRESENT_4.srcs/sources_1/new/presentcipher.v:92]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 4 for port 'rc' [C:/Users/Neha Jain/PRESENT_4/PRESENT_4.srcs/sources_1/new/presentcipher.v:93]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 4 for port 'rc' [C:/Users/Neha Jain/PRESENT_4/PRESENT_4.srcs/sources_1/new/presentcipher.v:94]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 4 for port 'rc' [C:/Users/Neha Jain/PRESENT_4/PRESENT_4.srcs/sources_1/new/presentcipher.v:95]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 4 for port 'rc' [C:/Users/Neha Jain/PRESENT_4/PRESENT_4.srcs/sources_1/new/presentcipher.v:96]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 4 for port 'rc' [C:/Users/Neha Jain/PRESENT_4/PRESENT_4.srcs/sources_1/new/presentcipher.v:97]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 4 for port 'rc' [C:/Users/Neha Jain/PRESENT_4/PRESENT_4.srcs/sources_1/new/presentcipher.v:98]
Completed static elaboration
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
run_program: Time (s): cpu = 00:00:01 ; elapsed = 00:00:08 . Memory (MB): peak = 670.500 ; gain = 0.000
INFO: [USF-XSim-69] 'elaborate' step finished in '8' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Neha Jain/PRESENT_4/PRESENT_4.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "simu_behav -key {Behavioral:sim_1:Functional:simu} -tclbatch {simu.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2018.3
Time resolution is 1 ps
source simu.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
xsim: Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 693.855 ; gain = 23.355
INFO: [USF-XSim-96] XSim completed. Design snapshot 'simu_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:19 ; elapsed = 00:00:30 . Memory (MB): peak = 693.855 ; gain = 24.156