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dpbram0.vhd
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--
-- dpbram0.vhd - entity "dpbram0"
--
-- SYNTHESIZABLE
--
-- Parameterisable dual port BlockRAM
--
-- Constraints on parameters
-- =========================
--
-- 1. 'width0' must be less than or equal to 'width1'
-- 2. 'width0' and 'width1' must be valid port data widths for a BlockRAM
-- of the specified family
-- 3. 'order0' and 'order1' must be valid port address widths for a
-- BlockRAM of the specified family
-- 4. The number of bits of BlockRAM storage required by the wider of the
-- two ports must be valid for a BlockRAM of the specified family.
-- 5. The length of 'init' must the same as the number of bits of BlockRAM
-- sotrage required by the wider of the two ports.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
library work;
use work.dpmem.all;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
library std;
use std.textio.all;
-- synopsys translate_on
entity dpbram0 is
generic(
order0 : in natural; -- number of address bits in port 0
width0 : in natural; -- width of port 0
order1 : in natural; -- number of address bits in port 1
width1 : in natural; -- width of port 1
-- synopsys translate_off
init : in std_logic_vector; -- initial contents of RAM
-- synopsys translate_on
family : in family_t); -- FPGA family to target
port(
rst : in std_logic;
k0 : in std_logic;
sr0 : in std_logic;
en0 : in std_logic;
w0 : in std_logic;
a0 : in std_logic_vector(order0 - 1 downto 0);
d0 : in std_logic_vector(width0 - 1 downto 0);
q0 : out std_logic_vector(width0 - 1 downto 0);
k1 : in std_logic;
sr1 : in std_logic;
en1 : in std_logic;
w1 : in std_logic;
a1 : in std_logic_vector(order1 - 1 downto 0);
d1 : in std_logic_vector(width1 - 1 downto 0);
q1 : out std_logic_vector(width1 - 1 downto 0));
end;
architecture struct of dpbram0 is
constant this_module : string := "dpmem.dpbram0";
function choice(
a : in integer;
b : in integer;
m : in boolean)
return integer is
begin
if m then
return b;
else
return a;
end if;
end;
function log2up(
n : in integer)
return integer is begin
assert n > 0
report "*** log2up: n > 0 violated"
severity failure;
for i in 0 to 30 loop
if 2**i >= n then
return i;
end if;
end loop;
assert false
report "*** log2up: n out of range"
severity failure;
return -1;
end;
-- synopsys translate_off
function conv_string(
val : in integer)
return string is
variable l : line;
variable len : integer;
variable s : string(1 to 64);
begin
write(l, val);
len := l'length;
read(l, s(1 to len));
return s(1 to len);
end;
-- synopsys translate_on
-- Minimum/maximum number of address bits for BlockRAMs of specified FPGA family
constant order_min : natural := log2up(blockram_min_depth(family));
constant order_max : natural := log2up(blockram_max_depth(family));
constant data_width_max : natural := blockram_max_data_width(family);
constant parity_width_max : natural := data_width_max / blockram_parity_ratio(family);
constant width_max : natural := data_width_max + parity_width_max;
-- Make port A the narrower port
constant a_width : natural := choice(width1, width0, order1 < order0);
constant a_order : natural := choice(order1, order0, order1 < order0);
constant b_width : natural := choice(width0, width1, order1 < order0);
constant b_order : natural := choice(order0, order1, order1 < order0);
constant a_depth : natural := 2**a_order;
constant a_inst_data_width : natural := blockram_data_size(family) / a_depth;
constant a_inst_parity_width : natural := a_inst_data_width / blockram_parity_ratio(family);
constant a_inst_width : natural := a_inst_data_width + a_inst_parity_width;
constant b_depth : natural := 2**b_order;
constant b_inst_data_width : natural := blockram_data_size(family) / b_depth;
constant b_inst_parity_width : natural := b_inst_data_width / blockram_parity_ratio(family);
constant b_inst_width : natural := b_inst_data_width + b_inst_parity_width;
constant str_write_mode_a : string := "READ_FIRST";
constant str_write_mode_b : string := "READ_FIRST";
function generate_n(
f : in family_t;
x : in natural;
y : in natural)
return integer is
variable match : boolean;
begin
case f is
when family_virtex2 =>
case family is
when family_virtex2 | family_virtex2p | family_virtex4 | family_virtex5 =>
match := true;
when family_virtex =>
match := false;
end case;
when family_virtex =>
case family is
when family_virtex2 | family_virtex2p | family_virtex4 | family_virtex5 =>
match := false;
when family_virtex =>
match := true;
end case;
when others =>
match := false;
end case;
if match and x = a_inst_width and y = b_inst_width then
return 1;
else
return 0;
end if;
end;
function get_init_slice(
idx : in natural;
init : in std_logic_vector)
return bit_vector is
variable x : bit_vector(255 downto 0);
variable tmp : std_logic;
variable offs : natural;
variable j, k, l, m : natural;
begin
offs := 256 * idx;
for i in 255 downto 0 loop
j := offs + i;
k := j / b_inst_data_width;
l := j rem b_inst_data_width;
m := k * b_inst_width + l;
if m < init'length then
tmp := init(m);
else
tmp := '0';
end if;
if tmp = '1' then
x(i) := '1';
else
x(i) := '0';
end if;
end loop;
return x;
end;
function get_initp_slice(
idx : in natural;
init : in std_logic_vector)
return bit_vector is
variable x : bit_vector(255 downto 0);
variable tmp : std_logic;
variable offs : natural;
variable j, k, l, m : natural;
begin
if b_inst_parity_width = 0 then
x := (others => '0');
else
offs := 256 * idx;
for i in 255 downto 0 loop
j := offs + i;
k := j / b_inst_parity_width;
l := j rem b_inst_parity_width;
m := k * b_inst_width + l + b_inst_data_width;
if m < init'length then
tmp := init(m);
else
tmp := '0';
end if;
if tmp = '1' then
x(i) := '1';
else
x(i) := '0';
end if;
end loop;
end if;
return x;
end;
signal ram_addra : std_logic_vector(a_order - 1 downto 0);
signal ram_dia : std_logic_vector(a_inst_width - 1 downto 0);
signal ram_doa : std_logic_vector(a_inst_width - 1 downto 0);
signal ram_ena : std_logic;
signal ram_clka : std_logic;
signal ram_wea : std_logic;
signal ram_ssra : std_logic;
signal ram_addrb : std_logic_vector(b_order - 1 downto 0);
signal ram_dib : std_logic_vector(b_inst_width - 1 downto 0);
signal ram_dob : std_logic_vector(b_inst_width - 1 downto 0);
signal ram_enb : std_logic;
signal ram_clkb : std_logic;
signal ram_web : std_logic;
signal ram_ssrb : std_logic;
attribute syn_black_box : boolean;
--
-- Virtex/Virtex-E/Virtex-EM BlockRAM components
--
component RAMB4_S1_S1
-- synopsys translate_off
generic(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000");
-- synopsys translate_on
port(
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (11 downto 0);
DIA : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;
CLKA : in std_ulogic;
WEA : in std_ulogic;
RSTA : in std_ulogic;
ADDRB : in std_logic_vector (11 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENB : in std_ulogic;
CLKB : in std_ulogic;
WEB : in std_ulogic;
RSTB : in std_ulogic);
end component;
attribute syn_black_box of RAMB4_S1_S1 : component is true;
component RAMB4_S1_S2
-- synopsys translate_off
generic(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000");
-- synopsys translate_on
port(
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (11 downto 0);
DIA : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;
CLKA : in std_ulogic;
WEA : in std_ulogic;
RSTA : in std_ulogic;
ADDRB : in std_logic_vector (10 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENB : in std_ulogic;
CLKB : in std_ulogic;
WEB : in std_ulogic;
RSTB : in std_ulogic);
end component;
attribute syn_black_box of RAMB4_S1_S2 : component is true;
component RAMB4_S1_S4
-- synopsys translate_off
generic(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000");
-- synopsys translate_on
port(
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (11 downto 0);
DIA : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;
CLKA : in std_ulogic;
WEA : in std_ulogic;
RSTA : in std_ulogic;
ADDRB : in std_logic_vector (9 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENB : in std_ulogic;
CLKB : in std_ulogic;
WEB : in std_ulogic;
RSTB : in std_ulogic);
end component;
attribute syn_black_box of RAMB4_S1_S4 : component is true;
component RAMB4_S1_S8
-- synopsys translate_off
generic(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000");
-- synopsys translate_on
port(
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (7 downto 0);
ADDRA : in std_logic_vector (11 downto 0);
DIA : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;
CLKA : in std_ulogic;
WEA : in std_ulogic;
RSTA : in std_ulogic;
ADDRB : in std_logic_vector (8 downto 0);
DIB : in std_logic_vector (7 downto 0);
ENB : in std_ulogic;
CLKB : in std_ulogic;
WEB : in std_ulogic;
RSTB : in std_ulogic);
end component;
attribute syn_black_box of RAMB4_S1_S8: component is true;
component RAMB4_S1_S16
-- synopsys translate_off
generic(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000");
-- synopsys translate_on
port(
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (15 downto 0);
ADDRA : in std_logic_vector (11 downto 0);
DIA : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;
CLKA : in std_ulogic;
WEA : in std_ulogic;
RSTA : in std_ulogic;
ADDRB : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (15 downto 0);
ENB : in std_ulogic;
CLKB : in std_ulogic;
WEB : in std_ulogic;
RSTB : in std_ulogic);
end component;
attribute syn_black_box of RAMB4_S1_S16 : component is true;
component RAMB4_S2_S2
-- synopsys translate_off
generic(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000");
-- synopsys translate_on
port(
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (10 downto 0);
DIA : in std_logic_vector (1 downto 0);
ENA : in std_ulogic;
CLKA : in std_ulogic;
WEA : in std_ulogic;
RSTA : in std_ulogic;
ADDRB : in std_logic_vector (10 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENB : in std_ulogic;
CLKB : in std_ulogic;
WEB : in std_ulogic;
RSTB : in std_ulogic);
end component;
attribute syn_black_box of RAMB4_S2_S2 : component is true;
component RAMB4_S2_S4
-- synopsys translate_off
generic(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000");
-- synopsys translate_on
port(
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (10 downto 0);
DIA : in std_logic_vector (1 downto 0);
ENA : in std_ulogic;
CLKA : in std_ulogic;
WEA : in std_ulogic;
RSTA : in std_ulogic;
ADDRB : in std_logic_vector (9 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENB : in std_ulogic;
CLKB : in std_ulogic;
WEB : in std_ulogic;
RSTB : in std_ulogic);
end component;
attribute syn_black_box of RAMB4_S2_S4 : component is true;
component RAMB4_S2_S8
-- synopsys translate_off
generic(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000");
-- synopsys translate_on
port(
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (7 downto 0);
ADDRA : in std_logic_vector (10 downto 0);
DIA : in std_logic_vector (1 downto 0);
ENA : in std_ulogic;
CLKA : in std_ulogic;
WEA : in std_ulogic;
RSTA : in std_ulogic;
ADDRB : in std_logic_vector (8 downto 0);
DIB : in std_logic_vector (7 downto 0);
ENB : in std_ulogic;
CLKB : in std_ulogic;
WEB : in std_ulogic;
RSTB : in std_ulogic);
end component;
attribute syn_black_box of RAMB4_S2_S8 : component is true;
component RAMB4_S2_S16
-- synopsys translate_off
generic(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000");
-- synopsys translate_on
port(
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (15 downto 0);
ADDRA : in std_logic_vector (10 downto 0);
DIA : in std_logic_vector (1 downto 0);
ENA : in std_ulogic;
CLKA : in std_ulogic;
WEA : in std_ulogic;
RSTA : in std_ulogic;
ADDRB : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (15 downto 0);
ENB : in std_ulogic;
CLKB : in std_ulogic;
WEB : in std_ulogic;
RSTB : in std_ulogic);
end component;
attribute syn_black_box of RAMB4_S2_S16 : component is true;
component RAMB4_S4_S4
-- synopsys translate_off
generic(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000");
-- synopsys translate_on
port(
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (9 downto 0);
DIA : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
CLKA : in std_ulogic;
WEA : in std_ulogic;
RSTA : in std_ulogic;
ADDRB : in std_logic_vector (9 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENB : in std_ulogic;
CLKB : in std_ulogic;
WEB : in std_ulogic;
RSTB : in std_ulogic);
end component;
attribute syn_black_box of RAMB4_S4_S4 : component is true;
component RAMB4_S4_S8
-- synopsys translate_off
generic(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000");
-- synopsys translate_on
port(
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (7 downto 0);
ADDRA : in std_logic_vector (9 downto 0);
DIA : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
CLKA : in std_ulogic;
WEA : in std_ulogic;
RSTA : in std_ulogic;
ADDRB : in std_logic_vector (8 downto 0);
DIB : in std_logic_vector (7 downto 0);
ENB : in std_ulogic;
CLKB : in std_ulogic;
WEB : in std_ulogic;
RSTB : in std_ulogic);
end component;
attribute syn_black_box of RAMB4_S4_S8 : component is true;
component RAMB4_S4_S16
-- synopsys translate_off
generic(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000");
-- synopsys translate_on
port(
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (15 downto 0);
ADDRA : in std_logic_vector (9 downto 0);
DIA : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
CLKA : in std_ulogic;
WEA : in std_ulogic;
RSTA : in std_ulogic;
ADDRB : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (15 downto 0);
ENB : in std_ulogic;
CLKB : in std_ulogic;
WEB : in std_ulogic;
RSTB : in std_ulogic);
end component;
attribute syn_black_box of RAMB4_S4_S16 : component is true;
component RAMB4_S8_S8
-- synopsys translate_off
generic(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000");
-- synopsys translate_on
port(
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
ADDRA : in std_logic_vector (8 downto 0);
DIA : in std_logic_vector (7 downto 0);
ENA : in std_ulogic;
CLKA : in std_ulogic;
WEA : in std_ulogic;
RSTA : in std_ulogic;
ADDRB : in std_logic_vector (8 downto 0);
DIB : in std_logic_vector (7 downto 0);
ENB : in std_ulogic;
CLKB : in std_ulogic;
WEB : in std_ulogic;
RSTB : in std_ulogic);
end component;
attribute syn_black_box of RAMB4_S8_S8 : component is true;
component RAMB4_S8_S16
-- synopsys translate_off
generic(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000");
-- synopsys translate_on
port(
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (15 downto 0);
ADDRA : in std_logic_vector (8 downto 0);
DIA : in std_logic_vector (7 downto 0);
ENA : in std_ulogic;
CLKA : in std_ulogic;
WEA : in std_ulogic;
RSTA : in std_ulogic;
ADDRB : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (15 downto 0);
ENB : in std_ulogic;
CLKB : in std_ulogic;
WEB : in std_ulogic;
RSTB : in std_ulogic);
end component;
attribute syn_black_box of RAMB4_S8_S16 : component is true;
component RAMB4_S16_S16
-- synopsys translate_off
generic(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000");
-- synopsys translate_on
port(
DOA : out std_logic_vector (15 downto 0);
DOB : out std_logic_vector (15 downto 0);
ADDRA : in std_logic_vector (7 downto 0);
DIA : in std_logic_vector (15 downto 0);
ENA : in std_ulogic;
CLKA : in std_ulogic;
WEA : in std_ulogic;
RSTA : in std_ulogic;
ADDRB : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (15 downto 0);
ENB : in std_ulogic;
CLKB : in std_ulogic;
WEB : in std_ulogic;
RSTB : in std_ulogic);
end component;
attribute syn_black_box of RAMB4_S16_S16 : component is true;
--
-- Virtex-II BlockRAM components
--
component RAMB16_S1_S1
-- synopsys translate_off
generic(
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000");
-- synopsys translate_on
port(
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (13 downto 0);
DIA : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;
CLKA : in std_ulogic;
WEA : in std_ulogic;
SSRA : in std_ulogic;
ADDRB : in std_logic_vector (13 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENB : in std_ulogic;
CLKB : in std_ulogic;
WEB : in std_ulogic;
SSRB : in std_ulogic);
end component;
attribute syn_black_box of RAMB16_S1_S1 : component is true;
component RAMB16_S1_S2
-- synopsys translate_off
generic(
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000");
-- synopsys translate_on
port(
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (13 downto 0);
DIA : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;