blockram_10b1024.xco

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#
# Xilinx Core Generator version J.36
# Date: Sun Oct 12 10:40:54 2014
#
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#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc4vsx55
SET devicefamily = virtex4
SET flowvendor = Foundation_iSE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = ff1148
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -10
SET verilogsim = True
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator family Xilinx,_Inc. 2.4
# END Select
# BEGIN Parameters
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=false
CSET byte_size=9
CSET coe_file=no_coe_file_loaded
CSET collision_warnings=ALL
CSET component_name=blockram_10b1024
CSET disable_collision_warnings=false
CSET disable_out_of_range_warnings=false
CSET ecc=false
CSET enable_a=Always_Enabled
CSET enable_b=Always_Enabled
CSET fill_remaining_memory_locations=false
CSET load_init_file=false
CSET memory_type=Simple_Dual_Port_RAM
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_b=WRITE_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET primitive=8kx2
CSET read_width_a=10
CSET read_width_b=10
CSET register_output_of_memory_core=false
CSET register_output_of_memory_primitives=false
CSET remaining_memory_locations=0
CSET single_bit_ecc=false
CSET use_byte_write_enable=false
CSET use_ramb16bwer_reset_behavior=false
CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_ssra_pin=false
CSET use_ssrb_pin=false
CSET write_depth_a=1024
CSET write_width_a=10
CSET write_width_b=10
# END Parameters
GENERATE
# CRC: c8e2b20e