-
Notifications
You must be signed in to change notification settings - Fork 5
/
Copy pathKconfig.nxp
305 lines (243 loc) · 7.99 KB
/
Kconfig.nxp
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
menu "Functionality shared between NXP SoCs"
config FSL_TRUST_ARCH_v1
bool
config NXP_ESBC
bool "NXP ESBC (secure boot) functionality"
select FSL_TRUST_ARCH_v1 if ARCH_P3041 || ARCH_P4080 || \
ARCH_P5040 || ARCH_P2041
help
Enable Freescale Secure Boot feature. Normally selected by defconfig.
If unsure, do not change.
menu "Chain of trust / secure boot options"
depends on !FIT_SIGNATURE && NXP_ESBC
config CHAIN_OF_TRUST
select FSL_CAAM
select ARCH_MISC_INIT
select FSL_ISBC_KEY_EXT if (ARM || FSL_CORENET) && !SYS_RAMBOOT
select FSL_SEC_MON
select ARCH_MISC_INIT
select SPL_BOARD_INIT if (ARM && SPL)
select SPL_HASH if (ARM && SPL)
select SHA_HW_ACCEL
select SHA_PROG_HW_ACCEL
select ENV_IS_NOWHERE
select SYS_CPC_REINIT_F if MPC85xx && !SYS_RAMBOOT
select CMD_EXT4 if ARM
select CMD_EXT4_WRITE if ARM
imply CMD_BLOB
imply CMD_HASH if ARM
def_bool y
config CMD_ESBC_VALIDATE
bool "Enable the 'esbc_validate' and 'esbc_halt' commands"
default y
help
This option enables two commands used for secure booting:
esbc_validate - validate signature using RSA verification
esbc_halt - put the core in spin loop (Secure Boot Only)
config ESBC_HDR_LS
bool
config ESBC_ADDR_64BIT
def_bool y
depends on FSL_LAYERSCAPE
help
For Layerscape based platforms, ESBC image Address in Header is 64bit.
config FSL_ISBC_KEY_EXT
bool
help
The key used for verification of next level images is picked up from
an Extension Table which has been verified by the ISBC (Internal
Secure boot Code) in boot ROM of the SoC. The feature is only
applicable in case of NOR boot and is not applicable in case of
RAMBOOT (NAND, SD, SPI). For Layerscape, this feature is available
for all device if IE Table is copied to XIP memory Also, for
Layerscape, ISBC doesn't verify this table.
config SYS_FSL_SFP_BE
def_bool y
depends on PPC || FSL_LSCH2 || ARCH_LS1021A
config SYS_FSL_SFP_LE
def_bool y
depends on !SYS_FSL_SFP_BE
choice
prompt "SFP IP revision"
default SYS_FSL_SFP_VER_3_0 if PPC
default SYS_FSL_SFP_VER_3_4
config SYS_FSL_SFP_VER_3_0
bool "SFP version 3.0"
config SYS_FSL_SFP_VER_3_2
bool "SFP version 3.2"
config SYS_FSL_SFP_VER_3_4
bool "SFP version 3.4"
endchoice
config SPL_UBOOT_KEY_HASH
string "Non-SRK key hash for U-Boot public/private key pair"
depends on SPL
default ""
help
Set the key hash for U-Boot here if public/private key pair used to
sign U-boot are different from the SRK hash put in the fuse. Example
of a key hash is
41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b.
Otherwise leave this empty.
if PPC
config BOOTSCRIPT_COPY_RAM
bool "Secure boot copies boot script to RAM"
help
On systems that support chain of trust booting, a number of addresses
are required to set variables that are used in the copying and then
verification of different parts of the system. If enabled, the subsequent
options are for what location to use in each step.
config BS_ADDR_DEVICE
hex "Address in RAM for bs_device"
depends on BOOTSCRIPT_COPY_RAM
config BS_SIZE
hex "The size of bs_size which is the amount read from bs_device"
depends on BOOTSCRIPT_COPY_RAM
config BS_ADDR_RAM
hex "Address in RAM for bs_ram"
depends on BOOTSCRIPT_COPY_RAM
config BS_HDR_ADDR_DEVICE
hex "Address in RAM for bs_hdr_device"
depends on BOOTSCRIPT_COPY_RAM
config BS_HDR_SIZE
hex "The size of bs_hdr_size which is the amount read from bs_hdr_device"
depends on BOOTSCRIPT_COPY_RAM
config BS_HDR_ADDR_RAM
hex "Address in RAM for bs_hdr_ram"
depends on BOOTSCRIPT_COPY_RAM
config BOOTSCRIPT_HDR_ADDR
hex "CONFIG_BOOTSCRIPT_HDR_ADDR"
default BS_ADDR_RAM if BOOTSCRIPT_COPY_RAM
endif
config SYS_FSL_SRK_LE
def_bool y
depends on ARM
config KEY_REVOCATION
def_bool y
endmenu
config DEEP_SLEEP
bool "Enable SoC deep sleep feature"
depends on ARCH_T1024 || ARCH_T1040 || ARCH_T1042 || ARCH_LS1021A
default y
help
Indicates this SoC supports deep sleep feature. If deep sleep is
supported, core will start to execute uboot when wakes up.
config LAYERSCAPE_NS_ACCESS
bool "Layerscape non-secure access support"
depends on ARCH_LS1021A || FSL_LSCH2
config PCIE1
bool "PCIe controller #1"
depends on LAYERSCAPE_NS_ACCESS || PPC
config PCIE2
bool "PCIe controller #2"
depends on LAYERSCAPE_NS_ACCESS || PPC
config PCIE3
bool "PCIe controller #3"
depends on LAYERSCAPE_NS_ACCESS || PPC
config PCIE4
bool "PCIe controller #4"
depends on LAYERSCAPE_NS_ACCESS || PPC
config FSL_USE_PCA9547_MUX
bool "Enable PCA9547 I2C Mux on Freescale boards"
depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
help
This option enables the PCA9547 I2C mux on Freescale boards.
config USB_TCPC
bool "USB Typec port controller simple driver"
default n
help
Enable USB type-c port controller (TCPC) driver
config VID
bool "Enable Freescale VID"
depends on (PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3) && (I2C || DM_I2C)
help
This option enables setting core voltage based on individual
values saved in SoC fuses.
config SPL_VID
bool "Enable Freescale VID in SPL"
depends on (PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3) && (SPL_I2C || DM_SPL_I2C)
help
This option enables setting core voltage based on individual
values saved in SoC fuses, in SPL.
if VID || SPL_VID
config VID_FLS_ENV
string "Environment variable for overriding VDD"
help
This option allows for specifying the environment variable
to check to override VDD information.
config VOL_MONITOR_INA220
bool "Enable the INA220 voltage monitor read"
help
This option enables INA220 voltage monitor read
functionality. It is used by the common VID driver.
config VOL_MONITOR_IR36021_READ
bool "Enable the IR36021 voltage monitor read"
help
This option enables IR36021 voltage monitor read
functionality. It is used by the common VID driver.
config VOL_MONITOR_IR36021_SET
bool "Enable the IR36021 voltage monitor set"
help
This option enables IR36021 voltage monitor set
functionality. It is used by the common VID driver.
config VOL_MONITOR_LTC3882_READ
bool "Enable the LTC3882 voltage monitor read"
help
This option enables LTC3882 voltage monitor read
functionality. It is used by the common VID driver.
config VOL_MONITOR_LTC3882_SET
bool "Enable the LTC3882 voltage monitor set"
help
This option enables LTC3882 voltage monitor set
functionality. It is used by the common VID driver.
config VOL_MONITOR_ISL68233_READ
bool "Enable the ISL68233 voltage monitor read"
help
This option enables ISL68233 voltage monitor read
functionality. It is used by the common VID driver.
config VOL_MONITOR_ISL68233_SET
bool "Enable the ISL68233 voltage monitor set"
help
This option enables ISL68233 voltage monitor set
functionality. It is used by the common VID driver.
endif
config SYS_FSL_NUM_CC_PLLS
int "Number of clock control PLLs"
depends on MPC85xx || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A || ARCH_LS1028A
default 2 if ARCH_LS1021A || ARCH_LS1028A || FSL_LSCH2
default 6 if FSL_LSCH3 || MPC85xx
config SYS_FSL_ESDHC_BE
bool
config SYS_FSL_IFC_BE
bool
config SYS_FSL_IFC_BANK_COUNT
int "Maximum banks of Integrated flash controller"
depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || \
ARCH_LS1088A || ARCH_LS1021A || ARCH_B4860 || ARCH_B4420 || \
ARCH_T4240 || ARCH_T1040 || ARCH_T1042 || ARCH_T1024 || \
ARCH_T2080 || ARCH_C29X || ARCH_P1010 || ARCH_BSC9131 || \
ARCH_BSC9132
default 3 if ARCH_BSC9131 || ARCH_BSC9132
default 4 if ARCH_LS1043A || ARCH_LS1046A || ARCH_B4860 || \
ARCH_B4420 || ARCH_P1010
default 8 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LS1021A || \
ARCH_T4240 || ARCH_T1040 || ARCH_T1042 || \
ARCH_T1024 || ARCH_T2080 || ARCH_C29X
config FSL_QIXIS
bool "Enable QIXIS support"
depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
config QIXIS_I2C_ACCESS
bool "Access to QIXIS is over i2c"
depends on FSL_QIXIS
default y
config HAS_FSL_DR_USB
def_bool y
depends on USB_EHCI_HCD && PPC
config SYS_DPAA_FMAN
bool
config SYS_FSL_SRDS_1
bool
config SYS_FSL_SRDS_2
bool
config SYS_HAS_SERDES
bool
endmenu